100350FC - National Semiconductor

TL/F/9884

100350 Low Power Hex D-Latch

July 1992

100350

Low Power Hex D-Latch

General Description

The 100350 contains six D-type latches with true and com-

plement outputs, a pair of common Enables (Eaand Eb),

and a common Master Reset (MR). A Q output follows its D

input when both Eaand Ebare LOW. When either Eaor Eb

(or both) are HIGH, a latch stores the last valid data present

on its D input before Eaor Ebwent HIGH. The MR input

overrides all other inputs and makes the Q outputs LOW. All

inputs have 50 kXpull-down resistors.

Features

Y20% power reduction of the 100150

Y2000V ESD protection

YPin/function compatible with 100150

YVoltage compensated operating range e

b4.2V to b5.7V

Logic Symbol

TL/F/9884–10

Pin Names Description

D0–D5Data Inputs

Ea,E

bCommon Enable Inputs (Active LOW)

MR Asynchronous Master Reset Input

Q0–Q5Data Outputs

Q0–Q5Complementary Data Outputs

Connection Diagrams

24-Pin DIP

TL/F/9884–1

28-Pin PCC

TL/F/9884–3

24-Pin Quad Cerpak

TL/F/9884–2

C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Logic Diagram

TL/F/9884–4

Truth Tables (Each Latch)

Latch Operation

Inputs Outputs

DnEaEbMR Qn

LLL L L

HLL L H

X H X L Latched*

X X H L Latched*

*Retains data present before E positive transition

HeHIGH Voltage Level

LeLOW Voltage Level

XeDon’t Care

Asynchronous Operation

Inputs Outputs

DnEaEbMR Qn

XXX H L

Absolute Maximum Ratings

Above which the useful life may be impaired. (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Storage Temperature (TSTG)b65§Ctoa

150§C

Maximum Junction Temperature (TJ)

Ceramic a175§C

Plastic a150§C

VEE Pin Potential to Ground Pin b7.0V to a0.5V

Input Voltage (DC) VEE to a0.5V

Output Current (DC Output HIGH) b50 mA

ESD (Note 2) t2000V

Note 1: Absolute maximum ratings are those values beyond which the de-

vice may be damaged or have its useful life impaired. Functional operation

under these conditions is not implied.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Recommended Operating

Conditions

Case Temperature (TC)

Commercial 0§Ctoa

85§C

Military b55§Ctoa

125§C

Supply Voltage (VEE)b5.7V to b4.2V

Commercial Version

DC Electrical Characteristics

VEE eb

4.5V to b5.7V, VCC eVCCA eGND, TCe0§Ctoa

85§C (Note 3)

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Voltage b1025 b955 b870 mV VIN eVIH (Max) Loading with

VOL Output LOW Voltage b1830 b1705 b1620 or VIL (Min) 50Xto b2.0V

VOHC Output HIGH Voltage b1035 mV VIN eVIH (Min) Loading with

VOLC Output LOW Voltage b1610 or VIL (Max) 50Xto b2.0V

VIH Input HIGH Voltage b1165 b870 mV Guaranteed HIGH Signal

for All Inputs

VIL Input LOW Voltage b1830 b1475 mV Guaranteed LOW Signal

for All Inputs

IIL Input LOW Current 0.50 mAV

IN eVIL (Min)

IIH Input HIGH Current

MR 240

Dn240 mAV

IN eVIH (Max)

Ea,E

b240

IEE Power Supply Inputs Open

Current b89 b44 mA VEE eb

4.2V to b4.8V

b93 b44 VEE eb

4.2V to b5.7V

Note 3: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these values normally occur at the temperature extremes, additional noise

immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to

guarantee operation under ‘‘worst case’’ conditions.

Commercial Version (Continued)

DIP AC Electrical Characteristics VEE eb

4.2V to b5.7V, VCC eVCCA eGND

Symbol Parameter TCe0§CT

25§CT

85§CUnits Conditions

Min Max Min Max Min Max

tPLH Propagation Delay

tPHL Dnto Output 0.50 1.40 0.50 1.40 0.50 1.50 ns

(Transparent Mode)

Figures 1

and

tPLH Propagation Delay 0.75 1.85 0.75 1.85 0.75 2.05 ns

tPHL Ea,E

bto Output

tPLH Propagation Delay 0.90 2.10 0.90 2.10 0.90 2.10 ns

Figures 1

and

tPHL MR to Output

tTLH Transition Time 0.35 1.30 0.35 1.30 0.35 1.30 ns

Figures 1

and

tTHL 20% to 80%, 80% to 20%

tsSetup Time

D0–D51.00 1.00 1.00 ns

Figures 3

and

MR (Release Time) 1.60 1.60 1.60

thHold Time, D0–D50.40 0.40 0.40 ns

Figure 4

tpw(L) Pulse Width LOW 2.00 2.00 2.00 ns

Figure 2

Ea,E

pw(H) Pulse Width HIGH, MR 2.00 2.00 2.00 ns

Figure 3

PCC and Cerpak AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND

Symbol Parameter TCe0§CT

25§CT

85§CUnits Conditions

Min Max Min Max Min Max

tPLH Propagation Delay

tPHL Dnto Output 0.50 1.20 0.50 1.20 0.50 1.30 ns

(Transparent Mode)

Figures 1

and

tPLH Propagation Delay 0.75 1.65 0.75 1.65 0.75 1.85 ns

tPHL Ea,E

bto Output

tPLH Propagation Delay 0.90 1.90 0.90 1.90 0.90 1.90 ns

Figures 1

and

tPHL MR to Output

tTLH Transition Time 0.35 1.10 0.35 1.10 0.35 1.10 ns

Figures 1

and

tTHL 20% to 80%, 80% to 20%

tsSetup Time

D0–D50.90 0.90 0.90 ns

Figures 3

and

MR (Release Time) 1.50 1.50 1.50

thHold Time, D0–D50.30 0.30 0.30 ns

Figure 4

tpw(L) Pulse Width LOW 2.00 2.00 2.00 ns

Figure 2

Ea,E

pw(H) Pulse Width HIGH, MR 2.00 2.00 2.00 ns

Figure 3

Military VersionÐPreliminary

DC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND, TCeb

55§Ctoa

125§C

Symbol Parameter Min Max Units TCConditions Notes

VOH Output HIGH Voltage b1025 b870 mV 0§Ctoa

125§C

b1085 b870 mV b55§CV

IN eVIH(Max) Loading with 1, 2, 3

VOL Output LOW Voltage b1830 b1620 mV 0§Ctoa

125§Cor VIL (Min) 50Xto b2.0V

b1830 b1555 mV b55§C

VOHC Output HIGH Voltage b1035 mV 0§Ctoa

125§C

b1085 mV b55§CV

IN eVIH(Min) Loading with 1, 2, 3

VOLC Output LOW Voltage b1610 mV 0§Ctoa

125§Cor VIL (Min) 50Xto b2.0V

b1555 mV b55§C

VIH Input HIGH Voltage b1165 b870 mV b55§Ctoa

125§CGuaranteed HIGH Signal 1, 2, 3, 4

for All Inputs

VIL Input LOW Voltage b1830 b1475 mV b55§Ctoa

125§CGuaranteed LOW Signal 1, 2, 3, 4

for All Inputs

IIL Input LOW Current 0.50 mAb55§Ctoa

125§CVEE eb

4.2V 1, 2, 3

VIN eVIL (Min)

IIH Input HIGH Current

MR 300

Dn250 mA0

Ctoa

125§C

Ea,E

b520 VEE eb

5.7V 1, 2, 3

MR 450 VIN eVIH (Max)

Dn350 mAb55§C

Ea,E

b750

IEE Power Supply Current b138 b64 mA b55§Ctoa

125§C Inputs Open 1, 2, 3

Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b55§C), then testing

immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides ‘‘cold start’’ specs which can be

considered a worst case condition at cold temperatures.

Note 2: Screen tested 100% on each device at b55§C, a25§C, and a125§C, Subgroups 1, 2, 3, 7, and 8.

Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at b55§C, a25§C, and a125§C, Subgroups A1, 2, 3, 7, and 8.

Note 4: Guaranteed by applying specified input condition and testing VOH/VOL.

Military Version-Preliminary (Continued)

AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND

Symbol Parameter TCeb

55§CT

25§CT

125§CUnits Conditions Notes

Min Max Min Max Min Max

tPLH Propagation Delay

tPHL Dnto Output 0.45 1.50 0.50 1.40 0.50 1.50 ns

(Transparent Mode)

Figures 1

and

tPLH Propagation Delay 0.75 2.05 0.75 1.85 0.75 2.05 ns

1, 2, 3

tPHL Ea,E

bto Output

tPLH Propagation Delay 0.80 2.40 0.90 2.40 0.90 2.60 ns

Figures 1

and

tPHL MR to Output

tTLH Transition Time 0.45 1.70 0.45 1.60 0.45 1.60 ns

Figures 1

and

tTHL 20% to 80%, 80% to 20%

tSSetup Time

D0-D50.70 0.70 0.70 ns

Figures 1

and

MR (Release Time) 2.10 2.10 2.10

tHHold Time, D0-D50.70 0.70 0.70 ns

Figure 4

tpw(L) Pulse Width LOW 2.00 2.00 2.00 ns

Figure 2

Ea,E

pw(L) Pulse Width HIGH, MR 2.00 2.00 2.00 ns

Figure 3

Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b55§C), then testing

immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides ‘‘cold start’’ specs which can be

considered a worst case condition at cold temperatures.

Note 2: Screen tested 100% on each device at a25§C, temperature only, Subgroup A9.

Note 3: Sample tested (Method 5005, Table I) on each Mfg. lot at a25§C, Subgroup A9, and at a125§C, and b55§C temp., Subgroups A10 and A11.

Note 4: Not tested at a25§C, a125§C, and b55§C temperature (design characterization data).

Test Circuit

TL/F/9884–5

Notes:

VCC,V

CCA ea

2V, VEE eb

2.5V

L1 and L2 eequal length 50Ximpedance lines

RTe50Xterminator internal to scope

Decoupling 0.1 mF from GND to VCC and VEE

All unused outputs are loaded with 50Xto GND

CLeFixture and stray capacitance s3pF

FIGURE 1. AC Test Circuit

Switching Waveforms

TL/F/9884–6

FIGURE 2. Enable Timing

Switching Waveforms (Continued)

TL/F/9884–7

FIGURE 3. Reset Timing

TL/F/9884–8

Notes:

tsis the minimum time before the transition of the enable that information must be present at the data input.

this the minimum time after the transition of the enable that information must remain unchanged at the data input.

FIGURE 4. Data Setup and Hold Time

Ordering Information

The device number is used to form part of a simplified purchasing code where a package type and temperature range are

defined as follows:

100350 D C QB

Device Type Special Variation

(Basic) QB eMilitary grade device with

environmental processing

Package Code shipped in tubes

DeCeramic DIP

FeFlatpak Temperature Range

PePlastic DIP C eCommercial (0§Ctoa

85§C)

QePlastic Leaded Chip Carrier (PCC) M eMilitary (b55§Ctoa

125§C)

Physical Dimensions inches (millimeters)

24-Lead Ceramic Dual-In-Line Package (0.400×Wide) (D)

NS Package Number J24E

24-Lead Plastic Dual-In-Line Package (P)

NS Package Number N24E

Physical Dimensions inches (millimeters) (Continued)

28-Lead Plastic Chip Carrier (Q)

NS Package Number V28A

100350 Low Power Hex D-Latch

Physical Dimensions inches (millimeters) (Continued) Lit. Ý103902

24-Lead Quad Cerpak (F)

NS Package Number W24B

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with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

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