FN7288 Rev.5.00 Page 1 of 13
Jul 17, 2020
FN7288
Rev.5.00
Jul 17, 2020
EL7457
40MHz Non-Inverting Quad CMOS Driver
DATASHEET
The EL7457 is a high speed, non-inverting, quad CMOS
driver. It is capable of running at clock rates up to 40MHz
and features 2A peak drive capability and a nominal
on-resistance of just 3. The EL7457 is ideal for driving
highly capacitive loads, such as storage and vertical clocks
in CCD applications. It is also well suited to ATE pin driving,
level-shifting, and clock-driving applications.
The EL7457 is capable of running from single or dual power
supplies while using ground referenced inputs. Each output
can be switched to either the high (VH) or low (VL) supply
pins, depending on the related input pin. The inputs are
compatible with both 3V and 5V CMOS and TTL logic. The
output enable (OE) pin can be used to put the outputs into a
high-impedance state. This is especially useful in CCD
applications, where the driver should be disabled during
power down.
The EL7457 also features very fast rise and fall times which
are matched to within 1ns. The propagation delay is also
matched between rising and falling edges to within 2ns.
The EL7457 is available in 16-pin QSOP, 16-pin SO
(0.150"), and 16-pin QFN packages. All are specified for
operation over the full -40°C to +85°C temperature range.
Pinouts
Features
• Clocking speeds up to 40MHz
• 4 channels
• 12ns tR/tF at 1000pF CLOAD
• 1ns rise and fall time match
• 1.5ns prop delay match
• Low quiescent current - <1mA
• Fast output enable function - 12ns
• Wide output voltage range
•8V VL -5V
•-2V VH 16.5V
• 2A peak drive
•3 on resistance
• Input level shifters
• TTL/CMOS input-compatible
• Pb-free (RoHS compliant)
Applications
• CCD drivers
• Digital cameras
• Pin drivers
• Clock/line drivers
• Ultrasound transducer drivers
• Ultrasonic and RF generators
• Level shifting
1
2
3
4
16
15
14
13
5
6
7
12
11
10
8 9
1
2
3
4
12
11
10
9
5
6
7
8
16
15
14
13
INB
VL
VL
GND
INC
IND
VS-
OUTD
OE
INA
VS+
OUTA
OUTB
VH
VH
OUTC
THERMAL
PAD*
INA
OE
INB
VL
GND
NC
INC
IND
VS+
OUTA
OUTB
NC
VH
OUTC
OUTD
VS-
EL7457
[16-PIN SO (0.150”),
QSOP (0.150”)]
TOP VIEW
EL7457
[16-PIN QFN (4X4MM)]
TOP VIEW
* THERMAL PAD CONNECTED
TO PIN 7 (VS-)
EL7457
FN7288 Rev.5.00 Page 2 of 13
Jul 17, 2020
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
TEMP.
RANGE (°C)
TAPE AND REEL
(Units) (Note 1)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
EL7457CUZ 7457CUZ -40°C to +85°C - 16 Ld QSOP (0.150”) MDP0040
EL7457CUZ-T13 7457CUZ -40°C to +85°C 2.5k 16 Ld QSOP (0.150”) MDP0040
EL7457CUZ-T7 7457CUZ -40°C to +85°C 1k 16 Ld QSOP (0.150”) MDP0040
EL7457CUZ-T7A 7457CUZ -40°C to +85°C 250 16 Ld QSOP (0.150”) MDP0040
EL7457CSZ EL7457CSZ -40°C to +85°C - 16 Ld SO (0.150”) MDP0027
EL7457CSZ-T13 EL7457CSZ -40°C to +85°C 2.5k 16 Ld SO (0.150”) MDP0027
EL7457CSZ-T7 EL7457CSZ -40°C to +85°C 1k 16 Ld SO (0.150”) MDP0027
EL7457CSZ-T7A EL7457CSZ -40°C to +85°C 250 16 Ld SO (0.150”) MDP0027
EL7457CLZ 7457CLZ -40°C to +85°C - 16 Ld QFN (4x4mm) L16.4X4H
EL7457CLZ-T13 7457CLZ -40°C to +85°C 2.5k 16 Ld QFN (4x4mm) L16.4X4H
EL7457CLZ-T7 7457CLZ -40°C to +85°C 1k 16 Ld QFN (4x4mm) L16.4X4H
EL7457CLZ-T7A 7457CLZ -40°C to +85°C 250 16 Ld QFN (4x4mm) L16.4X4H
NOTES:
1. See TB347 for details on reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus
anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see device information page for EL7457. For more information about MSL see TB363.
EL7457
FN7288 Rev.5.00 Page 3 of 13
Jul 17, 2020
Absolute Maximum Ratings (TA = 25°C) Thermal Information
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.3V, VS+ +0.3V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Thermal Resistance JA (°C/W) JC (°C/W)
16 Ld QFN (Notes 4, 5) . . . . . . . . . . . . 43 5
16 Ld SOIC (Notes 6, 7). . . . . . . . . . . . 73 45
16 Ld QSOP (Note 6). . . . . . . . . . . . . . 112 N/A
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See TB379 for details.
7. For JC, the “case temp” location is taken at the package top center.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications VS+ = +5V, VS- = -5V, VH = +5V, VL = -5V, TA = 25°C, unless otherwise specified.
PARAMETER DESCRIPTION CONDITION
MIN
(Note 8) TYP
MAX
(Note 8) UNIT
INPUT
VIH Logic “1” Input Voltage 2.0 V
IIH Logic “1” Input Current VIH = 5V 0.1 10 µA
VIL Logic “0” Input Voltage 0.8 V
IIL Logic “0” Input Current VIL = 0V 0.1 10 µA
CIN Input Capacitance 3.5 pF
RIN Input Resistance 50 M
OUTPUT
ROH ON Resistance VH to OUTx IOUT = -100mA 4.5 6
ROL ON Resistance VL to OUTx IOUT = +100mA 4 6
ILEAK Output Leakage Current VH = VS+, VL = VS-0.110µA
IPK Peak Output Current Source 2.0 A
Sink 2.0 A
POWER SUPPLY
ISPower Supply Current Inputs = VS+0.51.5mA
SWITCHING CHARACTERISTICS
tRRise Time CL = 1000pF 13.5 ns
tFFall Time CL = 1000pF 13 ns
tRFtR, tF Mismatch CL = 1000pF 0.5 ns
tD+ Turn-Off Delay Time CL = 1000pF 12.5 ns
tD- Turn-On Delay Time CL = 1000pF 14.5 ns
tDD tD-1 - tD-2 Mismatch CL = 1000pF 2 ns
tENABLE Enable Delay Time 12 ns
EL7457
FN7288 Rev.5.00 Page 4 of 13
Jul 17, 2020
tDISABLE Disable Delay Time 12 ns
Electrical Specifications VS+ = +5V, VS- = -5V, VH = +5V, VL = -5V, TA = 25°C, unless otherwise specified.
PARAMETER DESCRIPTION CONDITION
MIN
(Note 8) TYP
MAX
(Note 8) UNIT
Electrical Specifications VS+ = +15V, VS- = 0V, VH = +15V, VL = 0V, TA = 25°C, unless otherwise specified
PARAMETER DESCRIPTION CONDITION
MIN
(Note 8) TYP
MAX
(Note 8) UNIT
INPUT
VIH Logic “1” Input Voltage 2.4 V
IIH Logic “1” Input Current VIH = 5V 0.1 10 µA
VIL Logic “0” Input Voltage 0.8 V
IIL Logic “0” Input Current VIL = 0V 0.1 10 µA
CIN Input Capacitance 3.5 pF
RIN Input Resistance 50 M
OUTPUT
ROH ON Resistance VH to OUT IOUT = -100mA 3.5 5
ROL ON Resistance VL to OUT IOUT = +100mA 3 5
ILEAK Output Leakage Current VH = VS+, VL = VS-0.110µA
IPK Peak Output Current Source 2.0 A
Sink 2.0 A
POWER SUPPLY
ISPower Supply Current Inputs = VS+0.82mA
SWITCHING CHARACTERISTICS
tRRise Time CL = 1000pF 11 ns
tFFall Time CL = 1000pF 12 ns
tRFtR, tF Mismatch CL = 1000pF 1 ns
tD+ Turn-Off Delay Time CL = 1000pF 11.5 ns
tD- Turn-On Delay Time CL = 1000pF 13 ns
tDD tD-1 - tD-2 Mismatch CL = 1000pF 1.5 ns
tENABLE Enable Delay Time 12 ns
tDISABLE Disable Delay Time 12 ns
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
EL7457
FN7288 Rev.5.00 Page 5 of 13
Jul 17, 2020
Typical Performance Curves
FIGURE 1. SWITCH THRESHOLD vs SUPPLY VOLTAGE FIGURE 2. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE
FIGURE 3. “ON” RESISTANCE vs SUPPLY VOLTAGE FIGURE 4. RISE/FALL TIME vs SUPPLY VOLTAGE
FIGURE 5. RISE/FALL TIME vs TEMPERATURE FIGURE 6. PROPAGATION DELAY vs SUPPLY VOLTAGE
T=25°C HIGH LIMIT=2.4V
LOW LIMIT=0.8V
HYSTERESIS
1.8
1.6
1.4
1.2
1
5 7 10 12 15
SUPPLY VOLTAGE (V)
INPUT VOLTAGE (V)
T=25°C
ALL INPUTS=0
ALL INPUTS=VS+
2
1.6
1.2
0.8
0
5 7 10 12 15
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (V)
0.4
IOUT=100mA
T=25°C
VL TO OUT
9
8
6
4
2
5 7 10 12 15
SUPPLY VOLTAGE (V)
“ON” RESISTANCE ()
3
7
5
VH TO OUT
CL=1000pF
T=25°C
25
20
15
10
5
5 7 10 12 15
SUPPLY VOLTAGE (V)
RISE/FALL TIME (ns)
tF
tR
CL=1000pF
VS+=15V
16
14
12
8
6
-50 0 50 100 125
TEMPERATURE (°C)
RISE/FALL TIME (ns)
tF
tR
10
25 75-25
CL=1000pF
25
20
15
5
51015
SUPPLY VOLTAGE (V)
DELAY TIME (ns)
10
127
tD2
tD1
EL7457
FN7288 Rev.5.00 Page 6 of 13
Jul 17, 2020
FIGURE 7. PROPAGATION DELAY vs TEMPERATURE FIGURE 8. RISE/FALL TIME vs LOAD
FIGURE 9. SUPPLY CURRENT PER CHANNEL vs CAPACITIVE LOAD
Typical Performance Curves (Continued)
CL=1000pF
VS+=15V
18
14
12
8
6
-50 0 50 100 125
TEMPERATURE (°C)
DELAY TIME (ns)
10
25 75-25
16
tD2
tD1
VS+=15V
140
120
100
20
0
100 1K 4.7K 10K
LOAD CAPACITANCE (pF)
RISE/FALL TIME (ns)
tF
tR
60
2.2K470
80
40
VS+=VH=10V
VS-=VL=0V
f=100kHz
12
8
6
2
0
100 1K 10K
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
4
10
EL7457
FN7288 Rev.5.00 Page 7 of 13
Jul 17, 2020
Timing Diagram
Standard Test Configuration (CS/CU)
TABLE 1. NOMINAL OPERATING VOLTAGE RANGE
PIN MIN MAX
VS+ to VS- 5V 16.5V
VS- to GND -5V 0V
VHVS- + 2.5V VS+
VLVS-V
S+
VH to VL0V 16.5V
VL to VS-0V 8V
90%
10%
OUTPUT
2.5V
5V
INPUT
0
tD+
tR
tD-
tF
1
2
3
4
16
15
14
13
5
6
7
12
11
10
8 9
4.7µF 0.1µF
INA
INB
VL
INC
IND
10k
VS+
EN
VS-
OUTD
OUTC
VH
OUTB
OUTA
VS+
0.1µF 4.7µF
1000pF
1000pF
0.1µF 4.7µF
1000pF
1000pF
0.1µF 4.7µF
EL7457
FN7288 Rev.5.00 Page 8 of 13
Jul 17, 2020
Pin Descriptions
16-PIN
QSOP (0.150”),
SO (0.150”)
16-PIN QFN
(4x4mm) NAME FUNCTION EQUIVALENT CIRCUIT
1 15 INA Input channel A
CIRCUIT 1
2 16 OE Output Enable (Reference Circuit 1)
3 1 INB Input channel B (Reference Circuit 1)
4 2, 3 VL Low voltage input pin
5 4 GND Input logic ground
6, 13 NC No connection
7 5 INC Input channel C (Reference Circuit 1)
8 6 IND Input channel D (Reference Circuit 1)
9 7 VS- Negative supply voltage
10 8 OUTD Output channel D
CIRCUIT 2
11 9 OUTC Output channel C (Reference Circuit 2)
12 10, 11 VH High voltage input pin
14 12 OUTB Output channel B (Reference Circuit 2)
15 13 OUTA Output channel A (Reference Circuit 2)
16 14 VS+ Positive supply voltage
VS-VS-
VS+
VS+
INPUT
VS-
VS+
OUTPUT
VS-
VL
VH
EL7457
FN7288 Rev.5.00 Page 9 of 13
Jul 17, 2020
Block Diagram
Applications Information
Product Description
The EL7457 is a high performance 40MHz high speed quad
driver. Each channel of the EL7457 consists of a single
P-channel high side driver and a single N-channel low side
driver. These 3 devices will pull the output (OUTX) to either
the high or low voltage, on VH and VL respectively,
depending on the input logic signal (INX). It should be noted
that there is only one set of high and low voltage pins.
A common output enable (OE) pin is available on the
EL7457. This pin, when pulled low will put all outputs in to
the high impedance state.
The EL7457 is available in 16-pin SO (0.150"), 16-pin
QSOP, and ultra-small 16-pin QFN packages. The relevant
package should be chosen depending on the calculated
power dissipation.
Supply Voltage Range and Input Compatibility
The EL7457 is designed for operation on supplies from 5V to
15V with 10% tolerance (i.e. 4.5V to 18V). The table on page
6 shows the specifications for the relationship between the
VS+, VS-, VH, VL, and GND pins. The EL7457 does not
contain a true analog switch and therefore VL should always
be less than VH.
All input pins are compatible with both 3V and 5V CMOS
signals With a positive supply (VS+) of 5V, the EL7457 is
also compatible with TTL inputs.
Power Supply Bypassing
When using the EL7457, it is very important to use adequate
power supply bypassing. The high switching currents
developed by the EL7457 necessitate the use of a bypass
capacitor on both the positive and negative supplies. It is
recommended that a 4.7µF tantalum capacitor be used in
parallel with a 0.1µF low-inductance ceramic MLC capacitor.
These should be placed as close to the supply pins as
possible. It is also recommended that the VH and VL pins
have some level of bypassing, especially if the EL7457 is
driving highly capacitive loads.
Power Dissipation Calculation
When switching at high speeds, or driving heavy loads, the
EL7457 drive capability is limited by the rise in die
temperature brought about by internal power dissipation. For
reliable operation die temperature must be kept below
TJMAX (125°C). It is necessary to calculate the power
dissipation for a given application prior to selecting package
type.
Power dissipation may be calculated:
where:
VS is the total power supply to the EL7457 (from VS+ to
VS-)
VOUT is the swing on the output (VH - VL)
CL is the load capacitance
CINT is the internal load capacitance (80pF max)
IS is the quiescent supply current (3mA max)
f is frequency
Having obtained the application’s power dissipation, the
maximum junction temperature can be calculated:
where:
TJMAX is the maximum junction temperature (125°C)
TMAX is the maximum ambient operating temperature
PD is the power dissipation calculated above
JA is the thermal resistance, junction to ambient, of the
application (package + PCB combination). Refer to the
Package Power Dissipation curves on page 6.
3-STATE
CONTROL
LEVEL
SHIFTER OUTPUT
VL
VH
OE
INPUT
VS+
GND
VS-
PD VSIS
CINT VS
2
fCLVOUT
2
f+
1
4
+= (EQ. 1)
TJMAX TMAX JA PD+= (EQ. 2)
EL7457
FN7288 Rev.5.00 Page 10 of 13
Jul 17, 2020
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make
sure you have the latest revision.
DATE REVISION CHANGE
Jul 17, 2020 5.00 Updated links throughout.
Updated Ordering Information table adding the tape and reel column.
Added Revision History section.
Updated POD L16.4X4H to the latest revision, the changes are as follows:
Added note 7 and the Note 7 references to bottom view and Typ Pattern view
Removed “base plane” from side view
Updated the lead width dimension from 0.33 ±0.02 to 0.33 ±0.05
EL7457
FN7288 Rev.5.00 Page 11 of 13
Jul 17, 2020
Package Outline Drawings
GAUGE
PLANE
A2
A1 L
L1
DETAIL X
4° ±4°
SEATING
PLANE
eH
b
C
0.010 BMCA
0.004 C
0.010 BMCA
B
D
(N/2)
1
E1
E
NN (N/2)+1
A
PIN #1
I.D. MARK
h X 45°
A
SEE DETAIL “X”
c
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
INCHES
TOLERANCE NOTESSO-8 SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -
A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 -
A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 -
b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 -
c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 -
D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3
E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 -
E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3
e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -
L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 -
L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -
h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -
N 8 14 16 16 20 24 28 Reference -
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
For the most recent package outline drawing, see MDP0027.
EL7457
FN7288 Rev.5.00 Page 12 of 13
Jul 17, 2020
0.010 CAB
SEATING
PLANE
DETAIL X
EE1
1(N/2)
(N/2)+1
N
PIN #1
I.D. MARK
b
0.004 C
c
A
SEE DETAIL "X"
A2
4°±4°
GAUGE
PLANE
0.010
L
A1
D
B
H
C
e
A
0.007 CAB
L1
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
SYMBOL
INCHES
TOLERANCE NOTESQSOP16 QSOP24 QSOP28
A 0.068 0.068 0.068 Max. -
A1 0.006 0.006 0.006 ±0.002 -
A2 0.056 0.056 0.056 ±0.004 -
b 0.010 0.010 0.010 ±0.002 -
c 0.008 0.008 0.008 ±0.001 -
D 0.193 0.341 0.390 ±0.004 1, 3
E 0.236 0.236 0.236 ±0.008 -
E1 0.154 0.154 0.154 ±0.004 2, 3
e 0.025 0.025 0.025 Basic -
L 0.025 0.025 0.025 ±0.009 -
L1 0.041 0.041 0.041 Basic -
N 16 24 28 Reference -
Rev. F 2/07
NOTES:
5. Plastic or metal protrusions of 0.006” maximum per side are not
included.
6. Plastic interlead protrusions of 0.010” maximum per side are not
included.
7. Dimensions “D” and “E1” are measured at Datum Plane “H”.
8. Dimensioning and tolerancing per ASME Y14.5M-1994.
For the most recent package outline drawing, see MDP0040.
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