MXT3010
Reference Manual
Version 4.1
Order Number: 100108-05
October 1999
Copyright (c) 1999 by Maker Communications, Inc. All rights reserved.
Printed in the United States of America.
The information in this document is believed to be correct, however, the
information can change without notice. Maker Communications, Inc. disclaims
any responsibility for any consequences resulting from the use of the information
contained in this document.
The hardware, software, and the related docume ntation is provid ed with
RESTRICTED RIGHTS. Use, duplication, or disclosure by the U.S. Government
is subject to restrictions as set forth in subparagraph (c)(1) (ii) of The Rights in
Technical Data and Computer Program Product clause at DFARS 252.227-7013
or subparagraphs (c)(1) and (2) of the Commercial Computer Software-
Restricted Rights at 48 CFR 52.227-19, as applicable.
Contractor/manufacturer is:
Maker Communications, Inc.
73 Mount Wayte Aven ue, Framingham, MA 01702
CellMaker and BridgeMaker are registered trademarks of Maker
Communicat ions , In c. Acces s Maker, High-Int ensi ty C ommu ni cati ons Proces so r,
High-Intensity Communications Processing, PortMaker, Octave, and SimMaker
are trademarks of Maker Communications, Inc.
All other trademarks are owned by their respective companies.
This manual supercedes and obsoletes the following Maker Communications
publications:
100108-03 - MXT3010 Reference Manual, dated June 1999
100108-04 - MXT3010 Reference Manual, dated October 1999
MXT3010 Reference Manu al iii
CONTENTS
Preface xxi Maker Products xxi
Using thi s m a nual xxiii
Contacting Maker Support Services xxiv
Changes Installed in This Version of the Manual xx v
Section 1 Subsystems 1
CHAPTER 1 Introduction 3
MXT3010 features 4
MXT3010 subsystems 5
What informatio n is in this manual 6
CHAPTER 2 The SWAN Processor 9
The SWAN advantage 10
SWAN’s instructions an d address spaces 10
iv MXT3010 Reference Manual
Instruction execution 13
Instruction space organization 14
Instructio n cac he 15
SWAN processor instruction classes 18
Arithmetic Logic Unit (ALU) instructions 19
Branch instructio ns 19
Registers 21
Flag registers 24
HEC generation and check circuit 25
CHAPTER 3 The Cell Scheduling System 27
How the Cell Scheduling System works 28
Data transmiss ion - servicing and sche duling 31
Servicing 31
Scheduling 32
Pacing the transmission rate of cells 37
Programming the Cell Scheduling System 38
Guaranteeing the availabi lity of a location in the
Connect io n ID tab l e 41
The PUSHC/POPC instruction buffer 42
POPC, PUSHC, POP F, and PUS HF instruction operation 42
POPC and PUSHC timing 42
POPF and PUSHF timing 42
Connection ID table and Scoreboard addressing 43
Initializing th e Scoreboard 4 5
Selecting a Scoreboard size 45
Supporting m ultiple S coreboard sections 46
CHAPTER 4 The Fast Memory Interface 47
SWAN processor accesses to Fast Memory 48
Loading 48
Storing 50
Cell Scheduling System accesses to Fast Memory 51
SWAN executable fetches from Fast Memory 51
Fast Memory configuratio ns 52
Memory sizes supported 52
RAM selection and configuration 53
MXT3010 Reference Manua l v
Mode 0 op er a tion 53
Mode 1 op er a tion 54
Bus cont ention av oidance 55
Fast Memory sequence diagrams 56
CHAPTER 5 The Cell Buffer RAM 59
Internal cell storage in th e Cell Buffer RAM 60
Cell Buffer RAM memor y constr uction 64
Cell Buffer RAM access 67
CHAPTER 6 The UTOPIA port 69
UTOPIA port interface overview 70
Features 70
Operating mod es 71
UTOPIA cell formats 74
Receive cell flow 77
UTOPIA rec eiver counters 78
Transmit cell flow 82
UTOPIA transmitter counters 8 4
The TXBUSY counter 84
The TXFULL counter 86
CRC10 generation and checking support 87
Multi-PHY support 88
Receive Header Reduction hardware 91
UT OPIA port configurat ion summar y 93
UTOPIA port sequence diagrams 94
CHAPTER 7 The Port1 and Port2 Interfaces 97
Port interface overview 98
The Port DMA command queues 1 00
Port1 and Port2 DMA com m and queues 100
Testing DMA Con troller queues with the ESS bits 101
Port Controller features 103
The Cyclical Redundan c y Che c k 32 gene r ato r for Port1 103
Cyclical Redundancy Check operation acceleration 104
Silent transfe rs 105
vi MXT3010 Reference Manual
Post-i ncrement opt ion on rla operations 107
Data alignment 107
Byte manipulations on Port1 108
Post-DMA Operation Directives (PODs) 109
Burst and no n-burst operation (P ort2) 109
Port Operations 110
Port1 basic protocol 110
The Port1 control state machine 113
Communication register I/O transfers 133
Port2 basic protocol 137
The Port2 control state machine 142
Port2 D MA no n-b urst-mo de read transfer s 150
Port2 D MA no n-b urst-mo de w ri te trans fe r s 154
Additional Port1 and Port2 Design Information 156
Arbitrating access to Port1 156
Simplified Port2 interfaces 157
Bus driving, turnaround, and bus parking 158
Data Alignmen t 159
Transfer complete 161
Byte Count zero 161
External DMA cycle abort (P1ABORT_) 163
Endian-ness 164
Port 1 and Port2 Ref erence Design s 169
P1MemMaker 169
P2MemMaker 172
CHAPTER 8 Communications 177
The COMMIN/COMMOUT register 178
Interchip communications 180
Section 2 Register and Instruction Reference 183
Registers 183
Instructions 185
Instructio n de scriptio n no ta tio ns 188
MXT3010 Reference Manua l vii
CHAPTER 9 Registers 189
Register types 189
Software registers 189
Hardware registers 190
Specifying registers in SWAN instructions 190
Initializing software and hardware registers 191
R32 General Purpose - 0000 193
R33 General Purpose - FFFF 194
R34 General Purpose - FF00 195
R35 General Purpose - 0040 196
R36-write Bit Bucket register 197
R37-R39 General Purpose registers 198
R40-R41 Host Communication registers 199
R42-read External State Signals (ESS) register 200
R42-write Mode Configuration register 201
R43-read Fast Memory Bit Swap register (R42w[8]=0) 203
R43-read Special Features register (R42w[8]=1) 204
R43-write UTOPIA Control FIFO register 205
R44-R47 CRC32PRX and CRC32PRY registers 207
R48-R51 Local Address registers (rla) 208
R52 Alternate Byte Count/ID register 209
R53 Instruction Base Address register 210
R54-R55 Programmable Interval Timer registers 211
R56 Fast Memory Data register 212
R57-read Sparse Event/ICS register 213
R57-write Sparse Event/ICS register (Set/Clear) 214
R58 Fast Memory Shadow register 215
R59 Branch register 216
R60 The Cell Scheduling System (CSS) Configuration
register 217
R61-read Scheduled Address register 218
R62 The UTOPIA Configuration register 219
R63 The System register 221
CHAPTER 10 Arithmetic Logic Unit Instructions 223
Addressing modes 223
viii MXT3010 Reference Manual
Triadic register 223
Immediate 224
Overflow flag 225
Instruction options 226
Modulo arithmetic 226
Automatic memory updates 228
ALU branching 228
ADD Add Registers 234
ADDI Add Register and Immediate 235
AND And Registers 236
ANDI And Register and Immediate 237
CMP Compare Two Registers 238
CMPI Compare Register and Immediate 239
CMPP Compare Two Regi s ter s with Previous 240
CMPPI Compare Register and Immediate with
Previous 241
FLS Find Last Set 242
LIMD Load Immediate 243
MAX Maximum of Two Registers 244
MAXI Maximum of Register and Imm ediat e 245
MIN Minimum of Two Registers 246
MINI Minimum of Register and Immediate 247
OR Or Registers 248
ORI Or Register and Immediate 249
SFT Shift Signed Amount 250
SFTA Shift Right Arithmetic 251
SFTAI Shift Rig ht Arithmetic Imm e diate 252
SFTC Shift Left Circular 253
SFTCI Shift Circular Immediate 254
SFTRI/SFTLI Shift Right or Left Immediate 255
SUB Subtract Registers 256
SUBI Subtract Register and Immediate 257
XOR XOR Registers 258
XORI XOR Register and Immediate 259
CHAPTER 11 Branch Instructions 261
General Branch instruction information 262
MXT3010 Reference Manua l ix
Introduction 262
Target address 262
Condition code (ESS Field) 263
The logical state identifier (S-Bit) 264
Committe d slot instru c tion s 264
The Conditional operator (C-bit) 265
Subroutine linking 268
Counter system operation 269
BF Branch Fast Memory Shadow
Register 270
BFL Branch Fast Memory Shadow
Register and Link 271
BI Branch Immediate 272
BIL Branch Immediate and Link 273
BR Branch Register 274
BRL Branch Register and Link 275
CHAPTER 12 Cell Scheduling Instructions 277
Cell Scheduling System target address 277
POPC Service Schedule 278
POPF POP Fa s t 279
PUSHC Schedule 280
PUSHF Push Fast 281
CHAPTER 13 Direct Memory Access Instructions 283
General DMA instruction information 284
Introduction 284
Op codes for DMA instructions 284
The RLA increment bit (i-bit) 285
The Byte Count instruction field option (BC) 286
The Control instruction field option 287
DMA1R Direct Memory Operation - Port1 Read 289
DMA1W Direct Memory Operation - Port1 Write 290
DMA2R Direct Memory Operation - Port2 Read 291
DMA2W Direct Memory Operation - Port2 Write 292
x MXT3010 Reference Manual
CHAPTER 14 Load and Store Fast Memory
Instructions 293
General information for Load and Store Fast Memory
instructions 294
Introduction 294
Transfer size (the #HW field) 295
Fast Memory add ress (the rsa and rsb fields) 296
Address masking (the Z-bit) 296
Destination register (the rd field) 299
Linking (the LNK bit) 299
Instructions for accelerating CRC operations 305
Alternate address (the adr field) 306
Hardware register (reg field) 307
Least significant bits (the lsbs field) 307
LMFM Load Multiple from Fast Memory 3 08
SHFM Store Halfword to Fast Memory 311
SRH Store Register Halfword 31 2
CHAPTER 15 Load and Store Internal RAM
Instructions 313
General information for Load and Store internal RAM
instructions 314
Introduction 314
Register load ad dress (rla field) 314
The index field (IDX) 315
Byte swap support 319
The Swap field 319
LD Load Register 321
LDD Load Double Register 322
ST Store Register 323
STD Store D ouble Register 324
CHAPTER 16 Swan Instructi on Reference Examples 325
Add and Subtract examples 326
Branch examples 328
Load and Store Fast Memory examples 331
MXT3010 Reference Manua l xi
Load and Store Internal RAM examples 332
Logical examples 334
Shift examples 335
Miscellaneous examples 338
Section 3 Signal Descriptions and Electrical
Characteristics 341
CHAPTER 17 Timing 343
MXT3010EP tim i ng - general information 343
Definition of switching levels 343
Input clock deta ils 344
MXT3010EP Fast Memory interface timing 345
MXT3010EP UTOPIA interface timing 348
MXT3010EP Port1 timing 352
MXT3010EP Port2 timing 356
MXT3010EP miscellaneous control signal timing 359
MXT3010EP Reset timing 360
MXT3010EP Fast Memory interface operation 364
MXT3010EP JTAG operation 365
CHAPTER 18 Pin Information 367
MXT3010E P pinout 368
MXT3010EP signal descriptions 369
MXT3010EP JTAG/PLL pin termination 377
MXT3010EP pin listing 378
I/O pad reference 381
CHAPTER 19 Electrical Parameters 383
MXT3010EP maximum ratings and operating conditions 384
DC electrica l characteristics 385
AC electrical characteristics 385
MXT3010EP power seq uenci ng 386
xii MXT3010 Reference Manual
Overview 386
Damage to I/O pad metal 387
I/O pad latch-up 389
MXT3010EP PLL considerations 390
Overview 390
VAA decou pli ng 391
General decoupling 392
Reference clock jitter 393
Circuit design goals 394
CHAPTER 20 Mechanical and Thermal Information 395
MXT3010EP mechanical/thermal information 396
APPENDIX A Acronyms 399
APPENDIX B Device Initialization 401
Initializing th e MXT3010EP 402
Downloading firmware 402
How the system determines the boot path 402
How the application uses the output pins 403
How the code set is structured 404
How to boot 405
Limitations on the size of boot code 407
Initializing th e Mode Configuration register 4 08
Restrict ions on star ting addresses 409
APPENDIX C Quick Reference 411
Hardware register summary 4 12
ALU instruction field summary 413
Shift amount summary 414
Branch instruction field summary 416
DMA instruction field summary 417
Instruction summary 418
MXT3010 Reference Manua l xiii
List of Figures
FIGURE 1. MXT3010 and s urroun ding sy stem devices 5
FIGURE 2. SWAN processor address spaces and access instructions 11
FIGURE 3. SWAN instruction space 14
FIGURE 4. Formation of the page offset and the instruction tag 16
FIGURE 5. Target address format in Fast Memory 20
FIGURE 6. Pipeline feedback 22
FIGURE 7. Connection ID entries 30
FIGURE 8. Servicing and scheduling 34
FIGURE 9. Scoreboard operation 38
FIGURE 10. Connection ID table address generation 44
FIGURE 11. Scoreboard address generation 44
FIGURE 12. Load Fast Memory instruction 48
FIGURE 13. Store Fast Memory instruction 50
FIGURE 14. Fast Memory SRAM options 52
FIGURE 15. Mode 0 design example 54
FIGURE 16. Mode 1 design example 55
FIGURE 17. Fast Memory read operations - single bank 56
FIGURE 18. Fast Memory write operations - single bank 57
FIGURE 19. Fast Memory reads and writes - back-to-back and dual bank 57
FIGURE 20. Cell Buffer RAM organization 61
FIGURE 21. Cell fields defined 62
FIGURE 22. Receive cell organization: 52-byte and 56-byte cells 63
FIGURE 23. Gather method accesses 66
FIGURE 24. Cell Buffer RAM access 67
FIGURE 25. The UTOPIA port: 8/8 and 16-bit modes 7 2
FIGURE 26. Clock phases for RX/TX CLK = 1/2 Internal Clock 73
FIGURE 27. Clock phases for RX/TX CLK = 1/4 Internal Clock 73
FIGURE 28. UTOPIA 8-bit and 16-bit cell formats 74
FIGURE 29. HEC-e nabled 52-byte mode 75
FIGURE 30. HEC-disabled 52-byte mode 75
FIGURE 31. HEC-e nabled 56-byte mode 76
FIGURE 32. HEC-disabled 56-byte mode 76
FIGURE 33. The RXBUSY counter 79
FIGURE 34. The RXFULL counter 81
FIGURE 35. The TXBUSY counter 84
xiv MXT3010 Reference Manual
FIGURE 36. The TXFULL counter 85
FIGURE 37. Level 2 PHY configurations 89
FIGURE 38. Mixed Level 1 and Level 2 PHY configuration 90
FIGURE 39. UTOPIA Port receive timing - single PHY, 8-bit mode 94
FIGURE 40. UTOPIA Port transmit timing - single PHY, 8-bit mode 95
FIGURE 41. UTOPIA Port receive full timing - single PHY, 8-bit mode 95
FIGURE 42. UTOPIA Port transmit full timing - single PHY, 8-bit mode 95
FIGURE 43. DMA command queues for the MXT3010EP 100
FIGURE 44. Diagram of Port1 DMA instruction bits 111
FIGURE 45. Port1 DMA Read transfer with a Wait state 119
FIGURE 46. Port1 DMA Read transfer without a Wait state 122
FIGURE 47. Port1 DMA Write transfer with a Wait state 127
FIGURE 48. Port1 DMA Write transfer without a Wait state 130
FIGURE 49. Cut-and-Paste Version of Port1 Read 131
FIGURE 50. Cut-and-Paste Version of Port1 Write 132
FIGURE 51. COMMIN write followed by COMMOUT read 134
FIGURE 52. Diagram of Port2 burst DMA instruction bits 137
FIGURE 53. Diagram of Port2 non-burst DMA instruction bits 139
FIGURE 54. Port2 DMA burst-mode Read transfer with a Wait state 144
FIGURE 55. Port2 DMA burst-mode Read transfer without a Wait state 145
FIGURE 56. Port2 DMA burst-mode write transfer with a Wait state 148
FIGURE 57. Port2 DMA burst-mode write transfer without a Wait state 149
FIGURE 58. Port2 DMA non-burst-mode Read transfer. 151
FIGURE 59. Port2 DMA non-burst-mode Write transfer. 155
FIGURE 60. System example for Port1 bus. 156
FIGURE 61. DMA Read transfer with standard END_ signal 161
FIGURE 62. DMA Read transfer with Early END 162
FIGURE 63. DMA Read transfer terminated by P1ABORT_ 163
FIGURE 64. Most Significant Byte is the Lowest Address (“Big-endian”) 164
FIGURE 65. Least Significant Byte is the Lowest Address (“Little-endia n”) 164
FIGURE 66. Hardware Byte-swapping Circuit 165
FIGURE 67. Word Access 166
FIGURE 68. 16-bit xxx0 Access 167
FIGURE 69. 16-bit xxx2 Access 167
FIGURE 70. Byte Access 168
FIGURE 71. The Port1 MemMaker FPGA 171
FIGURE 72. Data Path Connections - Shared Memory to PCI 172
MXT3010 Reference Manua l xv
FIGURE 73. Data Path Connections - Shared Memory to MXT3010 1 72
FIGURE 74. The Port2 MemMaker FPGA 174
FIGURE 75. Data Path Connections - Shared Memory to PCI 174
FIGURE 76. Data Path Connections - Shared Memory to MXT3010 1 75
FIGURE 77. Timing of CIN_BUSY and COUT_RDY 180
FIGURE 78. Triadic register operation 224
FIGURE 79. Tr iadic instruction format 224
FIGURE 80. Immediate 10-bit instruction format 225
FIGURE 81. Immediate 6-bit instruction format 225
FIGURE 82. Branch instruction format (simplified) 262
FIGURE 83. Target address format in Fast Memory 262
FIGURE 84. DMA instruction format (simplified) 284
FIGURE 85. Control field format) 287
FIGURE 86. Z-bit usage example 298
FIGURE 87. Simplified Channel Descriptors 300
FIGURE 88. Channel Descriptor for LMFM and UM example 302
FIGURE 89. XOR operation between IDX and rla 316
FIGURE 90. Gather method accesses 318
FIGURE 91. Switching level voltages 343
FIGURE 92. Input clock waveform (pin FN) 344
FIGURE 93. Timing for Fast Memory reads 347
FIGURE 94. Timing for Fast Memory writes 347
FIGURE 95. FN and half-speed RX_CLK/TX_CLK 348
FIGURE 96. FN and quarter-speed RX_CLK/TX_CLK 348
FIGURE 97. UTOPIA port receive timing 350
FIGURE 98. UTOPIA por t transmi t timin g 351
FIGURE 99. Port1 read timing 354
FIGURE 100.P ort1 wr ite timi n g 354
FIGURE 101.COMMIN register write, COMMOUT register read timing 355
FIGURE 102.Port2 read timing 358
FIGURE 103.P ort2 wr ite timi n g 358
FIGURE 104.Timing of CIN_BUSY and COUT_RDY 359
FIGURE 105.MXT3010EP reset timing 361
FIGURE 106.Reset trailing edge timing 362
FIGURE 107.Reset timing circuit 363
FIGURE 108.MXT3010EP package/pin diagram 368
FIGURE 109.Generating a quiet VAA 3 92
MXT3010 Reference Manua l xvii
List of Tables
Table 1 SWAN processor instruction classes 18
Table 2 Methods of specifying the branch target field 21
Table 3 Hardware registers requiring one instruction delay 23
Table 4 Hardware registers requiring tw o instruction delays 24
Table 5 Scoreboard sectioning control 29
Table 6 Connection ID table address bits 44
Table 7 Scoreboard address bits 44
Table 8 Comparison of Mode 0 and Mode 1 operation 53
Table 9 UTOPIA Configuratio n control of the Cell Buffer RAM 60
Table 10 Cell field functions 62
Table 11 UTOPIA port data bus width selection 71
Table 12 UTOPIA port Tx and Rx pin utilization in 16-bit mode 71
Table 13 Cell l ength an d HEC co ntrol 72
Table 14 UTOPIA port clock selection 73
Table 15 Bi t assig nments for multi-PHY operation 88
Table 16 Receive Header Reduction control 91
Table 17 Receive Header Reduction enable bit 92
Table 18 UTOP IA conf iguration information 93
Table 19 Characteristics of Port1 and Port2 98
Table 20 ESS Bits for DMA Co ntroller status 102
Table 21 Example of DMA Controller status bit utilization 102
Table 22 Specification of the CRCX/CRCY instruction field option 103
Table 23 Valid and invalid first, mid-cell, and last transfers. 108
Table 24 Port 1 DMA instruction bit mapping 111
Table 25 Signals to control Port1 transfers 112
Table 26 State table for the Port1 DMA burst read state machine 118
Table 27 State table for the Port1 DMA burst write state machine 126
Table 28 State table for Port1 communication I/O state machine 133
Table 29 Port2 burst DMA instruction bit mapping 137
Table 30 Another view of Port2 burst DMA instruction bit mapping 138
Table 31 Port2 non-burst DMA instruction bit mapping 139
Table 32 Another view of Port2 non-burst DMA instruction bit mapping 140
Table 33 Signals to control Port2 transfers 141
Table 34 State table for the Port2 DMA burst-mode read state machine 143
Table 35 State table for the Port2 DMA burst write state machine 147
Table 36 State table for the Port2 DMA non-burst-mode read state machine 150
Table 37 State table for the Port2 DMA non-burst-mode write state machine 154
Table 38 Comparison of Big-endian and Little-end ian Read Operations 165
Table 39 Accesses With Hardware and Software Swaps, 32-bit 166
Table 40 Accesses With Hardware and Software Swaps, 32-bit and 16-bit 168
xviii MXT3010 Reference Manual
Table 41 Accesses With Hardware and Software Swaps, 32-bit, 16-bit, and 8-bit 168
Table 42 Definitions of CIN_BUSY and COUT_RDY 178
Table 43 ICSI pins 180
Table 44 ICSO pins 181
Table 45 Hardware registers 184
Table 46 Alphabetical list of instructions 186
Table 47 Abbreviations used in SWAN instruct ions 188
Table 48 Field abbreviations 190
Table 49 Hardware registers 191
Table 50 Signal utilization for 1-PHY and 2-PHY modes 220
Table 51 Modulo arithmetic options 227
Table 52 ALU Branch Conditions for all instructions except Compare and Min/Max in-
structions 23 0
Table 53 ALU Branch Conditions for Compare and Min/Max instructions 230
Table 54 Methods of specifying the Branch target field 263
Table 55 External State Signals register (R42) bits 264
Table 56 Use of the S-bit 264
Table 57 Use of the Conditional and Nullify operators 266
Table 58 Example - conditional branch, condition satisfied 266
Table 59 Example - conditional branch, condition not met 267
Table 60 Example - unconditional branch 267
Table 61 Example - conditional operator, conditional branch, condition satisfied 267
Table 62 Example - conditional operator, conditional branch, condition not satisfied 268
Table 63 Example - Branch with link, and return 269
Table 64 The CSO field 269
Table 65 Op codes for DMA instructions 284
Table 66 Use of Bit 26 285
Table 67 Timing chart for accessing rla after a DMA 286
Table 68 Use of the BC field 286
Table 69 Use of the Control byte 288
Table 70 Load Fast Memory instruction format 294
Table 71 Store Fast Memory instruction format 294
Table 72 Use of the rsa and rsb fields 296
Table 73 Use of the Z-bit 296
Table 74 Limits on #HW when linking to rd 300
Table 75 Memory alignment requirements 304
Table 76 Use of the adr field 306
Table 77 Use of the reg field 307
Table 78 Restrictions on access to rd registers after LMFM 309
Table 79 Load internal RAM instruction format 314
Table 80 Store internal RAM instruction format 314
Table 81 Use of the rla field 315
Table 82 Byte-swapping Load instructions 320
MXT3010 Reference Manua l xix
Table 83 Byte-swapping Store instructions 320
Table 84 Input clock timing parameters 344
Table 85 Fast Memory timing for the Maker MXT3010EP 346
Table 86 UTOPIA timing for Maker MXT3010EP 349
Table 87 Delay of UTOPIA clocks relative to MXT3010EP internal clock (CLK) 350
Table 88 Port1 timing table 353
Table 89 Port2 timing table 357
Table 90 Miscellaneous control signal timing 359
Table 91 MXT301 0EP reset timing 361
Table 92 MXT3010EP RESET_ timing parameters 362
Table 93 MXT3010EP Port1 signal descriptions 370
Table 94 MXT3010EP Port2 signal descriptions 371
Table 95 UT OPIA port sign al description 372
Table 96 MXT3010EP Fast Memory controller signal description 373
Table 97 MXT3010EP inter-chip and communication registers signal description 374
Table 98 MXT3010EP miscellaneous clock, control, and test signal descriptions 375
Table 99 Power and ground pin descriptions 376
Table 100 MXT3010EP pin terminations 377
Table 101 MXT3010EP pin listing 378
Table 102 I/O pad types 381
Table 103 Absolute maximum ratings (VSS = 0V) 384
Table 104 Recommended o perating conditions 384
Table 105 DC Electrical characteristics 385
Table 106 MXT3010EP package summary 397
Table 107 Selecting boot mode with ISCO_A and ICSO_B 403
Table 108 User code set’s four fields 404
Table 109 Bootstrap starting addresses for Fast Memory mode 1 409
Table 110 Hardware registers 412
Table 111 MODx fields 413
Table 112 abc fields 413
Table 113 AE field 413
Table 114 UM field 413
Table 115 Shift amount chart for SFT, SFTLI, and SFTRI 414
Table 116 Shift amount chart for SFTC and SFTCI 414
Table 117 Shift amount chart for SFTA 415
Table 118 Shift amount chart for SFTAI 415
Table 119 The CSO field 416
Table 120 The ESS field (condition codes) 416
Table 121 The S-bit field 416
Table 122 The C-bit field 416
Table 123 Use of the I-bit 417
Table 124 Use of the BC field 417
Table 125 Use of the Control byte 417
MXT3010 Reference Manual Ve rsion 4.1 xxi
Preface
Maker Prod ucts
Integrated
Circuits Maker Communications delivers a wide range of ATM solutions
based on the MXT3010 cell processing engine and the MXT3020
circuit interface coprocessor. The MXT3010 is a high-perfor-
mance progra mmable cel l processor engine specif ically de signed
to handle ATM cell manipulation and transmission at data rates up
to 622 Mb/s. The MXT3020 is an ATM circuit i nterface copro ces-
sor for the MXT3010 cell processor. It provides flexible inter-
working between Time Division Multiplexed (TDM) links and the
ATM network.
Software
Solutions The MXT3010 and MXT3020 are complemen ted with a serie s of
software applications that provide standard cell processing func-
tionality. CellMaker®-155 and CellMaker®-622 execut e on an
MXT3010 and provide ATM Adaptation Layer 5 (AAL5) Seg-
mentation and Reassembly (SAR) at data rates of 155 Mb/s and
622 Mb/s, respec ti vel y. AccessMaker™ executes on an
MXT3010 with up to four attached MXT3020 coprocessors. It
xxii Version 4.1 MXT3010 Reference Ma nual
provides cell processing functions for both packet and circuit
interworking to support multiple services concurrently includ-
ing AAL1, AAL5, IMA, and cell relay.
Development
Tools Maker Communi cations o ffe rs a full suite of de velopment t ools
for the MXT3010 Cell Processor including Verilog models of
the chips, the WASM assembler , CellMaker Simulator (CSIM),
and Graphical CellMaker Simula tor (GCSIM). CSIM is a Ver-
ilog -base d simu la tor th at pro vid es a ti ghtly c ontro lled a nd f ully
observable environment to execute and debug both processor
applications and ex ternal host programs before running them on
the target hardware. Maker also provides two development
boards. CSIM is complemented with a grap hical post pr ocessor ,
GCSIM. The MXT3016 is a 32-bit, PCI bus-based development
board used to te st 622Mb/s applicat ions. The MXT3025 is a 32-
bit, PCI bus-based evaluation board used to test OC-3 ATM
(MXT3010) and T1 (MXT3020) applications.
MXT3010 Reference Manua l Version 4.1 xxiii
Using this manual
Using this manual
This section provides information on the conventions used
within this manual.
Typographical
conventions This document uses the following typographical conventions
when describing features of the hardware and software, user-
machine interactions, and variables.
•Commands appear in mixed case, for example
Write_Channel_Map.
•Instruction mnemonics appear in uppercase, for example the
SUBBI in struction.
•User input appears in bold monospace font.
•System output and code examples appear in monospace font.
•Variables, such as user-definable names, appear in italics.
Instruction syntax All the instructions use the following syntax:
•Required values appear between (parentheses).
•Optional values appear between [square brackets].
•Optional descriptions appear in lowercase.
•Literal descriptions appear in UPPERCASE.
•Numbers are denoted by pound signs, #.
•A string of options f rom whic h you can o nly choose one appear
as follows: [option1 | option2 | option3]
•A string of options from which you can choose one or all the
options appear as follows: [option1] [option2] [option3]
•Bits whic h should be written as zeroes and igno red on read s
appear as Reserved
xxiv Version 4.1 MXT3010 Reference Ma nual
Terminology Common acronyms and abbreviations are defined in “Acro-
nyms” on page 39 9 and no t in the text. In add it io n, thi s manu al
uses the following term as defined:
Packets refer to Local Area Network (LA N) informat ion and
frames refer to ci rcuit information.
Contacting Maker Support Services
Maker Communicat ions, Inc. has the f ollowing forums for c om-
municating ideas, questions, and reporting problems:
• Sales and customer support 508-628-0622
• Product support support@maker.com
• Product inquires info@maker.com
• Facsimile 508-628-0256
• Web www.maker.com
MXT3010 Reference Manua l Version 4.1 xxv
Changes Installed in This Version of the Manual
Changes Installed in This Version of the Manual
Change Bars Change bars are provided to indicate revisions made since the
previous publication of the manual.
Changes 1. Additi onal t ext ha s been added to “Regist er a ccess rules ” on
page 22, and to the paragraph before that, concerning the
use of LD and LDD between accesses to rla registers. Cross
references to this warning have been added to “Avoiding
stale rla values” on page 315, to “LD Load Register” on
page 321, to “LDD Load Double Register” on page 322, and
to all hardware register descriptions in CHAPTER 9 "Regis-
ters" on page 189.
2. Figure 95, “FN and half-speed RX_CLK/TX_CLK,” on
page 348 and Figure 96, “FN and quarter-speed RX_CLK/
TX_CLK,” on page 348 have been added to show the rela-
tionship of UTOPIA clocks to FN.
3. Figure 22, “Receive cell organization: 52-byte and 56-byte
cells,” on page 63 has been modified to correctly identify
User Header bytes 2 and 3 in the 56-byte cell format.
4. The description of “LIMD Load Immediate” on page 243
has been corrected to indicate that the immediate is loaded
into regis ter rd, not register rsa.
5. Table 47, “Abbreviations used in SWAN instructions,” on
page 188 has been modified to generalize the definition of
usi.
6. The caption of Figure 89 on page 316 has been corrected to
indicate that it applies to XOR rather than OR.
7. A typographi c error (“3020 ” vs “3010”) in the description of
out-of-ba g floor life in “MXT30 10EP mechani cal/thermal
information” on page 396 has been corrected.
8. The note that explains the enabling/disabling of “R54-R55
Programmable Interval Timer registers” on page 211 has
been changed.
xxvi Version 4.1 MXT3010 Reference Ma nual
MXT3010 Reference Manual Version 4.1 1
Section 1 Subsystems
This section is composed of eight chapters. It provides an over-
view of t he MXT 3010 ATM cell pr oc ess ing engin e and it s ma jo r
functional subsystems.
2 Version 4.1 MXT3010 Reference Ma nual
MXT3010 Reference Manua l Version 4. 1 3
CHAPTER 1 Introduction
The MXT3010 is Maker Communication’s innovative, program-
mable ATM cell processing engine. The MXT3010 is built around
Maker Communication’s SWAN processor and specifically
designed for use in high-sp eed ATM cell-processing applications.
The MXT3010 delivers throughput at hard-wired speeds while
maintaining all of the benefits of programmable approaches.
4 Version 4.1 MXT3010 Reference Ma nual
Introduction
MXT3010 features
MXT3010-based systems are insulated against c hanges in ATM
standards because firmware modifications can accommodate
these changes. The MXT3010 can:
• Scale across both performance and application ranges.
• Run at speeds ranging from 1.5 Mb/s up to 622 Mb/s.
• Handle the ATM Forum’s Traffic Management 4.0 Avail-
able Bit Rate (ABR) service specification.
• Operate as a self-contained device managing concurrent
Constant Bit Rate (CBR), Variable Bit Rate (VBR), and
ABR connections, which frees host processing resources
for oth er tas ks.
• Support r ate-based and Quantum Flow Contr ol-based ABR
services with algorithmic implementation of traffic shap-
ing.
• Perform in ATM layer processing applications.
The MXT3010 h as a high sp eed glueless interfa ce to Fast Mem-
ory (SRAM) for storage of instructions and control structures,
two high-performance data interfaces, and a UTOPIA Level 2
compliant interface.
The MXT3010 device, packaged in a 240-pin plastic quad flat
package, is available in three speed grades, 100 MHz, 80 MHz
and 66 MHz. Full electrical and mechanical details are provided
in Section 3 of this manual.
Figure 1 shows the MXT3010’s internal subsystems and their
relationship to devices found in a typical ATM application.
MXT3010 Reference Manua l Version 4.1 5
MXT3010 subsystems
FIGURE 1.MXT3010 and surrounding system devices
MXT3010 subsystems
While the SWAN processor is the heart of the MXT3010, the
device also uses a series of subsystems or hardware agents cre-
ated to handle ATM-specific tasks. Not only do these sub-
systems off-load many time-critical functions from the SWAN
processor, but they also operate simultaneously with the SWAN
process or and wit h each ot her, achievin g a hi gh degre e of paral -
lelism. The su bsystems include:
• Th e Cell Scheduling Syste m (CSS), a hardwa re-based traf-
fic-shaping subsystem that allows concurrent shaping of
dissimilar traffic types.
• The Fast Memory port that provides low latency access to
external Channel Descriptors, program code, traffic shap-
ing memory, and the l ook up ta ble s used for Available Cell
Rate calculations.
• The Cell Buffer RAM that buffers cells in both the transmit
and receive directions.
Multi-purpose
DMA (Port2)
UTOPIA
Port
Cell Buffer High
Performance
DMA (Port1)
Instruction Cache
SWANTM Fast Memory
Controller
Cell Scheduling
System
Inter-chip
Signalling
PHY or
switch fabric
Application
specific
devices Main Memory
Message
buffers & other
information
32-bit
16-bit
Host
Processor
Fast Memory
Instructions &
data structures
RAM
Processor
bus bus
MXT3010
6 Version 4.1 MXT3010 Reference Ma nual
Introduction
• The UTOPIA port that provides connection to an ATM net-
work via a UTOPIA Level 2 Multi-PHY interface.
• The Port1 and Port2 interfaces: Port1 is a high performance
32-bit DMA host system interface and Po rt2 is a general
purpose 16-bit DMA interface.
How the
subsystems work
together
The Cell Scheduling System, the Fast Memory port, the Cell
Buffer RAM, and th e port interfaces utilize “dispatched”
instructions that operate outside of the CPU such that the SWAN
process or does no t stall while t he i ns tr uct ion is be ing execu ted.
Not only do dispatched instructions not interfere with the
SWAN, but those associated with different subsystems do not
interfere with each other, thus permitting simultaneous opera-
tion of several dispatched instructions within independent sub-
systems.
Although the Cell Scheduling System relies on the SWAN pro-
cessor for direction on required traffic patterns, the CSS man-
ages the traffic-shaping functions of the ATM task. This CSS
function provides all of the benefits of algorithmic traffic shap-
ing without decreasing overall performance.
What information is in this manual
This reference manual includes three sections: “Subsystems”,
“Register and Instruction Reference,” and “Signal Descriptions
and Electrical Characteristics.” Also included are Appendix A
“Acronyms,” Appendix B “Device Initialization,” and Appen-
dix C “Quick Reference.”
MXT3010 Reference Manua l Version 4.1 7
What information is in this manual
The “Subsystems” section includes information on:
• The SWAN processor
• The Cell Scheduling System
• The Fast Memory port
• The Cell Buffer RAM
• The UTOPIA port
• The Port1 and Port2 interfaces
• Interchip communications
The “Register and Instruction Reference” section describes the
software and hardware registers within the SWAN processor,
and includes bit assignments and functions for all of the hard-
ware registers. The “Register and Instruction Reference” section
also de scri bes i nstru ctions in fun ction al gr oups a nd pro vides an
alphabetical list of instructions within each group.
The “Signal Descriptions and Electrical Characteristics” section
includes information on:
• Timing information
• Pin out and pin listing
• Signal descriptions
• Ele ctrical parameters
• PLL details
• Thermal characteristics
• Mechanical information
8 Version 4.1 MXT3010 Reference Ma nual
Introduction
MXT3010 Reference Manua l Version 4. 1 9
CHAPTER 2 The SWAN Pr ocessor
The SWAN processor is used in network protocol processing
applications. This chapter describes how the SWAN processor
functions and provides functional descriptions of Arithmetic
Logic Unit (ALU) and Branch instructions of the SWAN proces-
sor.
Data
Stream
Cell
Stream
Multi-purpose
DMA (P ort2)
UTOPIA
Port
Cell Buffer RAM High
Performance
DMA (Port1)
Data
Stream
Instruction Cache
SWANTM Processor
Fast Memory
Controller
Cell Scheduling
System
Control
Memory
SRAM
Inter-chip
Signalling
10 Version 4.1 MXT3010 Reference Ma nual
The SWAN Processor
The SWAN advantage
The SWAN processor was designed using Reduced Instruction
Set Computer (RISC) and Complex Instruction Set Computer
(CISC) design techniques. By combining the high pipeline
speeds of a RISC processor with the instruction set power of a
CISC proces sor , the SWAN processor attains the l evel of perf or-
mance required to process a 622 Mb/s ATM cell stream.
SWAN’s in structions and address spaces
In addition to utilizing an advanced RISC/CISC design, the
SWAN processor employs highly efficient instructions and
address spaces optimized for ATM applications.
Instruction features
• The ALU instruct ions include a memory update feature th at
can writ e th e results of an ALU ope rat io n back into a mem-
ory location linked to the destination register.
• The ALU instructions include an integral branching capa-
bility that can perform a branch within the ALU instruction
cycle if the results of the ALU operation meet selected cri-
teria.
• The ALU ins tr uct io ns can pe rform mod ulo ar i thmet i c oper-
ations, selectable from 1 bit to 16 bits (full ALU width).
• The Branc h instru ctions can te st the status o f more tha n a
dozen internal hardware points and two external pins.
• Branch instructions and ALU branching facilities can be
programmed to eliminate the performance penalties nor-
mally exacted by branch failures in pipeline architectures.
• The Cell Sch eduling Syst em provides a powerful se t of cell
sched uli ng ins tructions.
MXT3010 Reference Manua l Version 4.1 11
The SWAN advant age
• DMA operations are dispatched with a single instruction,
and those for Port1 include flexible CRC capabilities.
• Load and Store instructions include indexing and byte-
swapping capability.
Address spaces
The architecture of the SWAN processor, a big-endian design,
provides several independent address spaces. The processor
accesses each space with instructions specifically designed for
optimal performance. Figure 2 shows these address spaces and
the instruc tions which ac cess them. The circled numbers in the
figure correspond to the explanatory paragraphs which follow.
FIGURE 2.SWAN processor address space s and access instru ctions
1. Instruction Space - 128K Words
The SWAN processor executes instructions stored in Fast
Memory. Fast Memory instructions are prefetched and
optionally cached in a direct mapped on-chip cache to
accelerate execution. A 17-bit Program Counter (allowing
up to 128K instructions) identifies the current instruction.
Port2
UTOPIA
Port
Cell Buffer Port1
Instruction Cache
SWANTM Fast Mem Cntl
Cell Scheduling
System
Inter-chip
Signalling
PHY or
switch fabric
Application
specific
devices Main Memory
Message
buffers & other
information
Host
Processor
Fast Memory
Instructions &
data structures
RAM
Processor
DMA2R
DMA2W
DMA1W
DMA1R
Instruction Fetches
LMFM
SHFM
Scoreboard
Register file
PUSH
POP
LD/ST
LD
ST
12
3
4
12 Version 4.1 MXT3010 Reference Ma nual
The SWAN Processor
The processor executes instructions in a four stage instruc-
tion pipeline. The four stages -- Fetch, Decode, Execute
and Store -- utilize scoreboarding and feedback to ensure
proper operation, minimize stalls, and safeguard against
illega l ins tr uction s eque nces. The Dec ode st age of th e pi pe-
line is the current Program Counter value.
2. Cont rol Me mory Space - 1MByte (i ncludes instr uction
space)
Fast Memory also provides a low latency store for control
structures such as descriptors for the applications objects
(VC descriptors, packet descriptors). The SWAN register
set is tightly coupl ed to this contro l memory space throug h
special purpose instructions -- Load Multiple from Fast
Memory (LMFM) and Store Halfword to Fast Me mory
(SHFM). See “Load and Store Fast Memory Instructions”
on page 293.
A powerful extension to ALU operations, linking, dynami-
cally associates Fast Memory with the register set. These
instructions virtually eliminate the context switching over-
head t hat l imits the perf ormance of o f f-the -shel f pr ocesso rs
in ATM systems. See “Automatic memory updates” on
page 228.
3. On-Chip Cell Buffer RAM - 1Kbytes
The Cell Buffer RAM on the MXT3010 provides the
SWAN processor with low latency access to cells in the
ATM data flow and to control inf ormation fr om the host . A
flexible Load/Store instruction paradigm provides an effi-
cient memory-register manipulation mechanism. In addi-
tion to byte swapping, the extended load/store operations
include an indexing method to facilitate control structure
parsing. See “Load and Store Internal RAM Instructions”
on pa ge 313. This mult i-port RAM is accessible to the
UTOPIA, Port1 and Port2 DMA engine as well as the
MXT3010 Reference Manua l Version 4.1 13
The SWAN advant age
SWAN. Since it is truly multi-ported, it provides very low
latency access to all arbiters. See “Direct Memory Access
Instructions” on page 283.
4. On-Chip Cell Scheduling System Scoreboard RAM -
2Kbytes
The Cell Scheduling System uses an on-chip RAM to
acceler ate cell sche duling opera tions. When not used by th e
CSS, this RAM is accessible to the SWAN processor
through the Load/Store instructions and may be used as
general purpose memory. See “The Cell Scheduling Sys-
tem” on pa ge 27.
Instruction execution
All SWAN instructions, exc ept dispatched instructions, execute
in a single clock cycle. Dispatched instructions include Load
Multip le Fast Memory (LMFM), the cell schedulin g instruc-
tions (PUSHC, POPC), the DMA instructions (DMA1, DMA2),
and the load and store double instructions (LDD, STD). Dis-
patched instructions require more than one cycle to complete,
but thei r executio n occu rs outside of t he CPU such tha t th e pro-
cessor can acc omplish other tasks while dispat ched instruct ions
execute.
Since the input clock is doubled in frequency by an on-chip
PLL, the SWAN processor execut es instructions at twice the fre-
quency of the input clock. Like other high performance RISC
processors, the SWAN utilizes a multi-stage pipeline. Delayed
branching techniques ensure that Branch instructions also oper-
ate at a n effecti ve rate of one instruct ion per cycle by preventing
pipeline delays.
14 Version 4.1 MXT3010 Reference Ma nual
The SWAN Processor
Inst ruction space or ganizatio n
The SWAN supports an instruction space of 128K 32-bit
instructions, which must be 4-byte aligned. The instruction
space spans 32 Segments of 4K instructions each. Figure 3
shows the SWAN instruction space.
FIGURE 3.SWAN ins truc t ion space
Notes: 1. The tag numbers wrap every 32K instructions
2. Page size is defined by the instruction cache size. Therefore,
the MXT3010 EP ha s sixty-four 2K pages.
Segments are defined by the branching range of the instruction
set. Since the Branch instruc tion has a 12 bit inst ruction addre ss
range, i t may jump a nywhere within a 4K segment. See “T ar get
field” on page 20.
Page 0, Tag = 0
Page 1, Tag = 1
Page 2, Tag = 2
Page 3, Tag = 3
Segment 0
Segment 1
0
2K
4K
8K
Page 14, Tag = 14
Page 15, Tag = 15
Page 16, Tag = 0
Page 17, Tag = 1
Segment 7
Segment 8
28K
32K
36K
Page 60, Tag = 12
Page 61, Tag = 13
Page 62, Tag = 14
Page 63, Tag = 15
Segment 30
Segment 31
120K
124K
128K
MXT3010 Reference Manua l Version 4.1 15
The SWAN advant age
Instruction cache
The internal Instruction Cache is 2048 instructions. The cache is
a direct-mapped cache, with each 32-bit entry having an inde-
pendent 4- bit tag. There ar e no sep arate valid bits for the ca che
entries. At device initialization time, all of the cache tags are
writte n to 0xF. After the micro-boot r outine downlo ads the firm -
ware, the SWAN processor jumps to the specified starting
address. The address must not map onto a cache tag of 0xF, as
these fet ches would caus e in cor rec t cache hits . For si mpli ci ty’s
sake, consider the code space of 32K instructions as an execut-
able spa ce of 30K in structio ns and with a top 2K of in struction s
inaccessible for execution.
Cache organization and mapping
The line size of the MXT3010 cache (i.e. the amount of cache
replaced on a cache miss) is 1 instruction. Each entry in the
cache is theref ore a si ngle in struc tion. Eac h entry or inst ruction
in the cache is 'tagged' with a 4 b it value that represen ts the
cache page. As shown in Figure 3 on page 14, each 4K instruc-
tion segment contains two 2K cache pages.
The NC (No-Cache) bit in the Instruction Base Address register
(R53) disables the cache. If this bit is set (one), the SWAN
fetches all instructions from Fast Memory, and these instruc-
tions are not stored in th e on-chip cache. Sin ce the Fast Memory
interface runs at 1/2 of the processor speed, it delivers an
instruction every other cycle. Therefore, while running out of
Fast Memory, the SWAN will stall, at a minimum, every other
cycle.
While NC is clear (zero), the cache is enabl ed. When the SWAN
fetches an instruction, the tag of the cache entry at the page off-
set of the ins truct ion is compar ed with the ta g of the i nst ructi on
address . Figu re 4 details the fo rmation of the pag e offset and t he
instruction tag.
16 Version 4.1 MXT3010 Reference Ma nual
The SWAN Processor
FIGURE 4.Formation of the page offset and the instruction tag
Note: The Instructi on Offset is a word offset, as opposed to a b yt e offset.
The byte in stru ction add res s in Fa st Me mory will be ((S egm ent_ ID
<< 14)+ (Instruction Offset << 2))
If the instruction tag matches the corresponding cache tag, a
cache hit has been achieved and the cache returns the instruction
within a single cycle. The processor continues execution with-
out stalling. However, if the tag does not match, a cache miss has
occurred and the instruction must be fetched from Fast Memory .
This will cause a processor stall as it awaits the instruction. Once
Fast Memory r eturns the instr uction, it is stored in the cache and
the tag is updated. Because the cache line si ze is a single instruc -
tion, on ly a single instructi on is repl aced in the cache on a c ache
miss. Subsequent cache misses may replace other instructions in
the cache. With an empty cache, such as when exiting the boot-
strap, every instruction must be fetched from Fast Memory.
Therefore, every other cycle will be a stall as the cache is cold
filled.
The firmware designer controls which segments are cacheable.
The NC bit in the Instruction Base Address register (R53) con-
trols the cache and is typically modified by firmware when a
code path jumps off the current segment. The firmware must
ensure that for each cache tag value (0x0-0xE), only a single
Cache
0
2047
Instructi on (32 bit s )
Tag (4 bits)
0
1
234
56
7
891011
0
1
234
Segment ID Instruction offset
4-bit tag Page offset
Program
counter
(17-bits)
MXT3010 Reference Manua l Version 4.1 17
The SWAN advant age
cache page is made cacheable. Otherwise, stale cache entries
prevent proper operation. The SWAN’s bootstrap program pre-
load s a tag of 0xF int o all cache entries a t init ializat ion. It is rec-
ommended that no cacheabl e code be pl aced at a lo cation with a
tag of 0xF.
Using the Cache
Code that is always executed, referred to as the ’fast path’, should
be placed in cacheable space, preferably within a single cache
page. Infrequently executed code (slow path) and performance
insensitive code (for example, initialization code) should be
located in non-cacheable segments. Maker’s development tools
provide code location features.
Many appli cat ions do n ot requi re more th an 2K inst ruc ti ons. In
this cas e, the applica tion may be located on a sin gle cache page.
The entire page will be mapped into cache. Obviously, this will
provide an optimal level of performance. However, it is not a
requirement, as a program can easily jump to a new segment
using the following instruction sequence:
LIMD R53 new-segment
BI offset_in_new_segment n
Instruction prefetch
The SWAN architecture is highl y pipel ined. The hardwa re may
prefetch instructions from Fast Memory in anticipation of exe-
cution. These prefetches may be cached. However, changes in
program flow (branches) may prevent the instructions from
being executed. This behavior is expected and does not cause
improper operation. Prefetches are mentioned here to alert the
user that fetches from Fast Memory do not correlate exactly to
the sequence of the Program Counter.
18 Version 4.1 MXT3010 Reference Ma nual
The SWAN Processor
Observing cached program flow
When the processor is executing out of cache, it does not need
to access Fast Memory. However, if Fast Memory is not being
used, the MXT3010 presents the program counter address on the
Fast Memory address lines. This helps to monitor code execu-
tion from cache.
SWAN processor ins truction cla sses
The SWAN processor includes powerful 32-bit instructions in
six functional areas or classes. Descriptions of each class of
instru ction are divided into two sections — one which describes
the subs ystem that uses that instruction and one which descri bes
the bi t utiliza tion and f ormat for e ach instru ction. These descrip-
tions appear in the chapters listed in Table 1.
TABLE 1. SWAN processor instruction classes
Functional Area Subsystem Description Instructi on Descrip tio n
Arithmetic Logic
Unit Instructions “The SWAN Proces-
sor” (this chapter) “Arithmetic Logic Unit
Inst r uc tio ns ” on pa ge 223
Branch Instructions “The SWAN Proces-
sor” (this chapter) “Branch Instructions” on
page 261
Cell Scheduling
Instructions “The Cell Scheduling
System ” on page 27 “Cell Scheduling Instruc-
tions” on pag e 277
Direct Memory
Access Instructions “ The Por t1 and Por t2
Interfaces” on page 97 “Di r ect Memory Access
Inst r uc tio ns ” on pa ge 283
Load and Store Inter-
nal RAM Instruc-
tions
“The Cell Buffer
RAM” on page 59 “Load and Store Inte rnal
RAM Instructions” on
page 313
Load and Store Fast
Memory Instructions “The Fast Mem ory
Interface” o n page 47 “Load and Store Fast
Memory Instructions” on
page 293
MXT3010 Reference Manua l Version 4.1 19
SWAN processor in struction cl asses
Arithmetic Logic Unit (ALU) instructions
Basic ALU
instructions The SWAN processor instruction set includes a complete suite
of arithmetic, logical, and shifting instructions implemented in a
high performance ALU. The format of a typical ALU instruction
is shown below:
ADD (rsa, rsb) rd [MODx][abc][AE][UM]
In the exampl e shown, inpu t dat a is sto red in rs a and r sb, whi le
the result is delivered to register rd. The notations shown in
square brackets represent the special features that optimize the
SWAN ALU for ATM cell processing. These features, referred
to as instruction field options (IFOs), include the modulo field
(MODx), the ALU branch condition field (abc), the always exe-
cute bit (AE), and the update memory feature (UM). For more
information see “Arithmetic Lo gic Unit Instructions” on
page 223.
Branch instructions
The SWAN processor include s two basic branc h cont rol mecha-
nisms:
• A suite of ALU instructions that includes conditional
branching capabiliti es. See “Arit hmetic Logi c Unit Instruc-
tions” on page 223.
• A suite of three basic branch instructions, each of which is
available with a return address linking version.
Basic Branch
instructions The format of a typical Branch instruction (Branch Fast Mem-
ory) is shown below:
BF [ESS#/(0|1)[/C]][cso][N]
20 Version 4.1 MXT3010 Reference Ma nual
The SWAN Processor
Branch instructions allow the programmer to specify condi-
tional branching decisions whic h will alter the instruction exe-
cution sequence. T he bran ching deci sions ar e based o n the st ate
of the MXT3010 subs yst ems, as indi cated in th e Exte rnal S ta te
Signals (ESS) registe r . The poi nt to be tested is specified by the
ESS field (ESS#). If the branch is to be taken when the point
tested is a 1, the ESS# is fol lo wed by a / 1. I f t he branch is to be
taken when the poin t test ed is a 0, the ESS# i s foll owed by a / 0.
Branch instructions c an also be used to manipulate the UT OPIA
port’s control counters via the counter system operation (cso)
field. The C an d N opti ons op timize the p erformance of Br anch
instructions in special circumstances. Descriptions of these
options appear in “The Conditional operator (C-bit)” on
page 265. Complete information on Branch instructions appears
in “Branch Instructions” on page 261.
Target address The branch tar get addr ess is the address at which execution con-
tinues if the specified branch condition is satisfied. The full
branch target address within Fast Memory is formed from the
Segment ID in the Instruction Base Address register (R53) and
the branch target field. Figure 5 shows the format of the target
address.
FIGURE 5.Target address format in Fast Memory
Target field The branch target field is a 12-bit field that specifies the absolute
word address within the current code segment (4096 words) at
which execution is to continue. The three basic branch instruc-
tions di ffe r on ly i n th eir method of spe ci fyi ng t he branch t arge t
address field. Ta ble 2 summarizes the methods used.
18 17 16 15 14 13 12 11 10 9876543210
Segment ID Branch Target Field 0 0
MXT3010 Reference Manua l Version 4.1 21
Registers
Note 1:The Fast Memory shad ow register is loaded with the first h alfword
returned from memory during a Fast Memory read operation that
specifies the LNK Instruction Field Option.
For a compl ete description of the t hree basic branch instr uctions
and the versions which include return address linking, see
“Branch Instructions” on page 261.
Registers
Register types The SWAN processor contains 64 software-visible registers of
two types, general-purpose and control/status. The general-pur-
pose registers are classified as software registers because their
usage and content is firmwa re dependent. The register s that con-
trol functions and provide status information are classified as
hardware registers.
The SWAN processor has 32 general-purpose software registers,
R0-R31, each 16- bits wide. The SWAN also has 32 control and
status hardware registers, R32-R63.
Pipeline feedback The SWAN processor includes two pipeline feedback features.
One of the feedback paths take s results from the execution stage
of the instruction pipeline and delivers those results to the
decode stage. A second feedback path takes results from the
storage stage of the pipeline and also delivers those results to the
decode stage. Figure 6 shows the general concept:
TABLE 2. Methods of specifying the branch target field
Instruction Method of specifying the branch target field
Branch Immediate (BI) As bits [11 :0] of the instruction
Branch Fast Memory
Shadow Register (BF) As bits [11:0] of the Fast Mem ory Shadow
register (R58). (N ote 1)
Branch Register (BR) As bits [11:0] of the Branch register (R59)
22 Version 4.1 MXT3010 Reference Ma nual
The SWAN Processor
FIGURE 6.Pipeline feedback
Using the execution stage feedback facility, an ALU instruction
that modi fies a regi ster can be fo llowed immediatel y by another
ALU instruc tion that accesses t hat same reg ister. Using the st or-
age s tag e f eedback facilit y, other inst ruction s that mo dif y a reg -
ister can be followed, afte r an intervening ins truction, by an
instruction that accesses the same register. This intervening
instruction must not be an LD or LDD to a hardware register.
Regi ster a ccess
rules Do not pe rf orm a loa d (LD, LDD) to a har dwar e re gis ter i mme-
diatel y between an ins truction tha t accesses an rl a register (R48 -
R51, GA-GD) and an instruction that stores to that rla register.
The number of processor cycles which must intervene between
an i nstruction that alte rs a regi ster and an instruc tion which u ses
the data in the altered register depends upon two factors:
• The instruction used
When a POPC is is sued, the destin ation register , r d, does not
contain the requested data until eight cycles after the POPC
instruction is decoded.
Cache Register
File
Fetch Stage Decode Stage
Other Logic ALU
Execution Stage
Storage
Stage
Execution Stage Feedback
Storage Stage Feedback
MXT3010 Reference Manua l Version 4.1 23
Registers
When a Load (LD) instruction is issued, the destination reg-
ister, rd, does not contain the requested data until one cycle
after the LD instruction is decoded.
When a Load Double (LDD) instruction is issued, the sec-
ond destination register, rd + 1, does not contain the
requested data un til two c ycles after the LDD i nstruction is
decoded.
When a Load Mult i ple F ast Me mory ( LMFM) i nst ruct ion is
issued, the destination registers are updated after delays
described in “LMFM Load Multiple from Fast Memory” on
page 308.
• The register accessed
A write to a software register, R0-R31, can be immediately
followed by an instruction that uses the data in that register.
Writes to the following hardware registers should be fol-
lowed by at least one other instruction before the new infor-
mation in the register is used for load, store, or branch
instructi ons. T his restrict ion does not a pply to their use in
ALU or DMA instructions.:
TABLE 3. Hardware registers requirin g one instruction delay
Location Name Read/Write
R44-R47 CRCX/CRCY
(when used a general purpose registers) R/W
R48 rla Address register R/W
R49 rla Address register R/W
R50 rla Address register R/W
R51 rla Address register R/W
R57-write Sparse Event/ICS register Set/Clear
R58 Fast Memory Shadow register R/W
R59 Branch register R/W
24 Version 4.1 MXT3010 Reference Ma nual
The SWAN Processor
Writes to the following hardware registers should be followed
by at least two other inst ructions before the new info rm at io n in
the register is used:
Flag registers
Flag registers include the Assigned Cell Flag register and the
Overflow Flag register. These registers are internal state bits;
programs do not manipulate them directly, but can use the statu s
of the flags to modify program flow.
Assigned Cell flag
register The Cell Schedul ing System manipulates t his register at the con-
clusion of a POPC operat ion. The state of the Scoreboa rd bit tar -
geted by the POPC operation is copied into this register, which
is connected to ESS4 and can be tested by ALU Conditional
Branch instructions.
Overflow flag
register Add and Subtract instructions that cause arithmetic overflow set
this register. ALU Con ditional Branch in struc tions test this reg-
ister.
For more
information For a complete description of the registers within the SWAN
processor, please see “Registers” on page 189.
TABLE 4. Hardware registers requiring two instruction delays
Location Name Read/Write
R42-w rite Mode Configuratio n r e gist e r Set/Cl ear
R43-read Fast Memory Bit Swap register R
R60 CSS Configuration register R/W
R62 UTOPIA Configuration register R/W
R63 System reg i ster R/W
MXT3010 Reference Manua l Version 4.1 25
HEC genera tion and check circuit
HEC generation and check circuit
The MXT3010 provides two HEC generation and checking
methods:
1. HEC generation and checking is provided in the UTOPIA
port. See “Receive cell flow” on page 77.
2. For applications which do not use the UTOPIA port, HEC
generation and checking is provided in the SWAN proces-
sor.
SWAN HEC
operation Bit 9 of the Mode Configuration Register (R42) enables HEC
generation mode in the SWAN processor and changes the defi-
nition of General Purpose register R33. In normal operation,
R33 is a read/write register and is initialized to 0xFFFF . In HEC-
enabled mode, R33 is redefined to include the output from the
HEC generat ion circuitry and is theref ore no longer available as
a simple read/write register or as a constant value.
Addition ally, the HEC circuitry uses R32 as a source of data for
HEC generation. This register is read/write and is initialized to
0x0000. Whe n not used f or HEC purpose s, R32 can continue to
function as a 16-bit read/write register.
The HEC generation logic takes in two 16-bit data values and
produces an 8-bit result. In normal ATM cell processing, the first
data value would be the first two bytes of the ATM cell header.
The second data value would be the second two bytes of the
ATM cell header, and the 8-bit result of that second operation
would be the HEC inserted (or checked) for the current cell.
The HEC circuitry initializes its 8-bit seed value when new data
is written to R32. A subsequent write to R33 completes the input
of data to the HEC circuit. Aft er appropriate pi peline delays, the
result ant HEC is ava il abl e r i ght just if ied in R33. The fo ll owing
code segmen t illustrates this.
26 Version 4.1 MXT3010 Reference Ma nual
The SWAN Processor
LIMD r32 #first_two_bytes ;load first half of cell
header
;this also resets the
SEED value
LIMD r33 #second_two_bytes ;load second half of
cell header
NOP ;execute stage
NOP ;store stage
NOP ;HEC processing
CMP r33, x ;HEC is returned in low
byte R33
The H EC result can be us ed directly in a transmitted cell, or
compared to the fifth byte in a received cell. The NOP instruc-
tions c an be repl aced wit h useful operatio ns, but th e HEC result
in R33 is not valid until the fourth instruction after data is writ-
ten to R33.
MXT3010 Reference Manua l Version 4. 1 27
CHAPTER 3 The Cell Scheduling System
The Cell Scheduling System (CSS) is a traffic-shaping system
that operates as a combination of algorithmic- and hardware-
assisted functions. The SWAN processor implements the algorith-
mic-assisted portion of the scheduling function, and the cell
schedule r perfor ms the hardwa re-assi sted port ion. By imple ment-
Data
Stream
Cell
Stream
Multi-purpose
DMA (P ort2)
UTOPIA
Port
Cell Buffer RAM High
Performance
DMA (Port1)
Data
Stream
Instruction Cache
SWANTM Processor
Fast Memory
Controller
Cell Scheduling
System
Control
Memory
SRAM
Inter-chip
Signalling
28 Version 4.1 MXT3010 Reference Ma nual
The Cell Scheduling System
ing traffic shaping as a combination of algorithmic- and hard-
ware-assisted functions, the programmer has complete control
over the traffic-shaping algorithms used.
This chapter includes the following informatio n:
• How the Cell Scheduling System works
• Data transmission - servicing and scheduling
• Pacing the transmission rate of cells
• Programming the Cell Scheduling System
How the Cell Scheduling System works
The Cell Scheduling System works by dividing the ATM cell
payload capacity of the transmission link into periodic contain-
ers of cells. The boundary of the periodic containers relative to
the transmission convergence framing structure is arbitrary. To
schedule cell usage wit hin the containers, the MXT3010 creates
a Scoreboard (schedule) on-chip and a Connection ID table in
Fast Memory. The Scoreboar d ca n cont ai n up to e igh t se ct ions,
each of which represents an independent periodic container for
a separa te physi cal l ink or prio rity l evel. Ea ch loca tion wit hin a
periodi c contai ner cor respon ds to a single bit in the Scor eboard
section and a single entry in the corresponding Connection ID
table. Bit s [13:12] of the Cell Schedu ling System (CSS) Config -
uration register (R60) control the number of sections in the
Scoreboard.
MXT3010 Reference Manua l Version 4.1 29
How the Cell Scheduling System works
TABLE 5. Scoreboard sectioning control
To clarify the dis cus si on whi ch f ollows, it wi ll be as sume d that
the Scoreboard contains only a single section of 16,384 bits/
entries.
The Scor eboard an d Connecti on ID tab le ar e main ta ine d by the
SWAN processor working with a specialized control circuit
referred to as the cell scheduler. The cell sched uler modi fies th e
Scoreboard and Connection ID table in response to servicing
and cell scheduling requests issued by the SWAN processor.
Successive bits in the Scoreboard and locations in the Connec-
tion ID table represent successive cell time slots on a transmis-
sion li nk. If the t ransmission l ink is not f ully loaded with traff ic,
only some of the entr ies in th e table have a virtual circuit (VC)
assigned to them, as indicated by a bit set to one in the Score-
board. Others are labeled Available, as indicated by a Score-
board bit that is zero. Figure 7 sho ws an example of Connecti on
ID tab le entries.
Bits Name Description
13:12 SZ Scoreboard Section Size
00 = 2,048 bits/entries per section; up to 8 sections
01 = 4,096 bits/entries per section; up to 4 sections
10 = 8,192 bits/entries per section; up to 2 sections
11 = 16,384 bits/entries per section; 1 section
30 Version 4.1 MXT3010 Reference Ma nual
The Cell Scheduling System
FIGURE 7.Connection ID entries
During the cell-scheduling process, status bits in the Scoreboard
table summarize the assigned or available status of each Con-
nection ID table entry. Since a bit in the Scoreboard represents
the sta tus of a 16-bi t entry in the Con nection ID ta ble, the Sc ore-
board is only 1/16th the size of the Connection ID table. This
compact ion of ta ble status accele rates the ce ll sched uler ta sk of
searching for available time slots. The searching task is further
accelerated by a proprietary algorithm that guarantees to iden-
tify an available cell-time slot from anywhere within the Score-
board and write the Connection ID into that slot within 121
processor cycles. High-speed searching is especially important
for high-speed ATM links and/or those links that carry a large
number of VCs, as lar ger Connecti on ID tables are used in such
systems.
Connection ID 145
Connection ID 47
Available
1
10
Note
The MXT3010 accommodates Scoreboards of
2,048 through 16,384 bits and Connection ID
tables of 2,048 through 16,384 16-bit halfwords.
Scoreboard
Connection ID Table
1. Under ideal conditions (Fast Memory write pipe empty), this number
could be as low as 10, but it is highly likely that a write pipe entry will
need to be displaced, raising the number to 12.
MXT3010 Reference Manua l Version 4.1 31
Data transmission - servicing and sche du lin g
Data tran smission - servicing and sche duling
The data transmission process consists of two major steps:
1. Servicing the Connection ID table to find entries represent-
ing assigned time slots that are scheduled for transmission
on an established virtual circuit.
2. Scheduling time slots for existing virtual circuits or estab-
lishing new VCs by placing entries into Connection ID
table locations that ensure the proper service quality for
that VC.
Servicing
The SWAN processor services the Connection ID table and
Scoreboa rd linearly and se rvices the VCs that have re served the
various locations. The SWAN processor determines which VC
reserved a time slot by examining the corresponding Connection
ID table entry. The SWAN processor reads the Connection ID
table entry by executing the POPC instruction. When POPC
executes, the cell scheduler returns the addressed Connection ID
table entry , copies the value of the Scoreboard bit corresponding
to th e ent r y into the Assigned Cell fl ag bit of the Exter nal State
Signals register (R42, bit 4), and clears the Scoreboard bit.
The processor maintains a pointer into the Connection ID table
that represents the current cell time slot. In a normal application,
the processor increments this pointer each time it issues the
POPC instruction. Because the Scoreboard and Connection ID
table represent periodic containers, the SWAN processor is
responsible for manipulating its Connection ID table pointer
modulo the container siz e. If multip le Scorebo ards and Connec-
tion ID tables are used, the SWAN is responsible for manipulat-
ing multiple Connection ID table pointers, each modulo its
respective container size.
32 Version 4.1 MXT3010 Reference Ma nual
The Cell Scheduling System
The POPC instruction is a dispatched instruction operating out-
side of the CPU such that the SWAN processor does not stall
while the cell scheduler executes the POPC instruction. The
SWAN processor can determine when the POPC operation is
comp lete by testing the state of bit 5 in the External States Sig-
nals register (R42). ESS5 is set while a cell scheduling operation
is in progress. Alternatively , the SWAN processor can determine
when the POPC operatio n is compl ete by accessi ng t he de stina-
tion register , al though this met hod can result in a proces sor stall.
Register scorebo arding guarant ees that the processor will stall if
the processor tries to access the destination register (rd) before
the cell sch eduler has written th e POPC r esult to that re gister.
However, the instruction immediately following the POPC is
not register scoreboarded and should not access register rd.
When a POPC instruction has executed, and the Assigned Cell
Flag indicates that the selected time slot had an assigned Con-
nection ID tab le ent ry, th e progr am can r ead the de stina tion reg-
ister of the PO PC ins truction to obtain a pointer to the Channel
Descriptor for the VC associated with that time slot. The Chan-
nel Descriptor contains the application-defined state informa-
tion needed to process the cell transmission event for the
associated VC. This data normally includes the pointer to the
data to b e transmitte d plus rate or fl ow control inf ormation used
in scheduling future activity for the VC.
If the Assi gned Cell Flag indicate s that the sel ected tim e slo t is
unassigned, the program must employ measures to ensure that
an appropriat e t ra nsmis si on rate i s mai nt ai ned. See “Pac ing the
transmission rate of cells” on page 37.
Scheduling
The SWAN processor schedules a VC when adding a new con-
nection or when servicing an existing VC. The SWAN processor
initiates a scheduling operation by executing a PUSHC instruc-
MXT3010 Reference Manua l Version 4.1 33
Data transmission - servicing and sche du lin g
tion. P USHC sp ecifi es a 1 6-bit Connec tion ID and a tar g et l oca-
tion within the p eriodic container (Scoreboard). The cell
schedule r responds to PUSHC by scanning the Score board look-
ing for the first available location at or after the targeted loca-
tion. If an ava ilabl e loca tion i s not f ound by t he time the la st bit
of the Scoreboard is reached, the cell scheduler loops back to the
beginning of the Scoreboard to continue the search. When the
cell scheduler finds an available location, it sets the bit in the
Scoreboard and writes the Connection ID into the corresponding
Connection ID table entry. In general, the Connection ID identi-
fies t h e F ast Memory add ress of t h e Chann el Descri ptor for the
VC.
Like POPC, PUSHC is a dispatched instruction operating out-
side of the CPU such that the SWAN processor does not stall
while the cell scheduler executes the PUSHC instruction. The
SWAN processor determines when the PUSHC operation is
complete by testing the state of bit 5 in the External Signal Sta-
tus regi ster (R42) . ESS5 is set while a cell sched uling opera tion
is in progress. When the scheduling operation is complete, the
processor reads the scheduled address in the Cell Scheduling
System Scheduled Address register (R61). This address differs
from the target address if the target address was previously
scheduled.
Software cannot de pend upon th e state o f r egi st er R61 until th e
PUSH/PUSHF instruction is complete, as no register score-
boarding mechanism protects access to this register during
PUSH/PUSHF instruction operation.
For example, Figure 8 shows the SWAN processor servicing the
third location in the Connection ID table and scheduling a new
time slot for Connection ID 47.
34 Version 4.1 MXT3010 Reference Ma nual
The Cell Scheduling System
FIGURE 8.Servicing and scheduling
In the example shown in Figure 8, the requested location was six
entries away from the entry being serviced. However, that loca-
tion was assigned, and the nearest available location was eight
entries away. The cell scheduler reserves the available location
and reports the location to the SWAN processor via the Cell
Scheduling System Scheduled Address register (R61). This
report -back f eatur e is impor tant when crea ting co ntrol led del ay
connecti ons, as i t enable s the pr ogram to de termine whe ther the
chosen location meets the cell delay variation (CDV) require-
ments. If the CDV requir ements are not met, th e SWAN proces-
sor can make another scheduling attempt or otherwise
reschedule or reject the connection.
Calculating target time slots
The SWAN processor uses the Channel Descriptor information
to calculate, via an algorithm, a target time slot location for the
next tran smissi on to serve the VC. A variety of method s can be
employed.
Connection ID 145
Connection ID 47
Available
1
10
Scoreboard
Connection ID Table
Pointer in CPU representing current time slot
110
Ideal next transmission time slot
First available transmission time slot
nearest the ideal time slot
Connection ID 321
Connection ID 123
Available
MXT3010 Reference Manua l Version 4.1 35
Data transmission - servicing and sche du lin g
Using GCRA to
calculate time
slots
The schedul ing of cells on a per -c onnect ion bas is is co mpletel y
implementation dependent. For example, an implementation
can use the Generic Cell Rate Algorithm1 as def ine d by Incre-
ment and Limit ((GCRA(I,L)) to schedule cells on a VC. The
Increment represents the minimum int er- cel l emis si on int erv al
for the VC.
The scheduling algorithm calculates target time slots for various
types of connection as follows:
• For an Ava ilabl e Bit Rate (ABR) con nection, the inter-cell
emission interv al is based on feedback from the network
(flow control information in the Channel Descriptor) and is
equal to 1/ACR. The impleme ntation can calculate the
Increment for ABR connections in accordance with the
ATM Forum's rate-based ABR service specification, but
other methods can be used.
• For a Variable Bit Rate (VBR) connection, the target time
slot calculation can use an algorithm that allows burst
transmission of a specified number of cells (Maximum
Burst Size) at a peak cell rate (Peak Cell Rate), not to
exceed a sustained cell rate (Sustained Cell Rate) over
time. In this case, the Increment depends upon the above
three parameters.
• For an Unspecified Bit Rate (UBR) connection, the target
time slot calculation is based on the information in the
Channel De scriptor wi thout regard to flow cont rol, but wit h
no effort at reliable transport.
• For a CBR connection, the algorithm can schedule all the
required time slots in the Scoreboard when the connection
is initially established. The quantity and spacing of these
time slots depends on the bandwidth and Cell Delay Varia-
tion (CDV) requirements associated with the connection.
Therefor e, when a tar get time slot calcul atio n is created for
1. Consult ATM Forum’s Traffic Management 4.0 for GCRA information.
36 Version 4.1 MXT3010 Reference Ma nual
The Cell Scheduling System
an established CBR connection, the target time slot is the
current time slot. Maintaining the currently assigned time
slots ensures consistent CBR connection performance.
For CBR connect ions, the inter -cell emis sion inte rval is no t
time varying and is equal to 1/Peak Cell Rate (PCR).
For VCs with dynamically allocated time slots, such as VBR
and ABR VCs, a single time sl ot can exist on the Connect ion ID
Table/ Scoreboard for each VC. VCs that use per manent reserva -
tion of bandwidth, such as CBR VCs, can have multiple time
slots.
All of the informat ion req uired to calculate the inter-cell emis-
sion inte rvals can be st ored in Fast Memory. Inter- cell emiss ion
intervals can be stored as fract ional integers to support high con-
nection rates. The program can store the inter-cell interval as a
fracti onal int eger a nd ma intai n a re main der. The SWAN pro ces-
sor can then schedule cells using the integer portion of the result,
saving the remainder for use in the next scheduling event on that
VC.
The SWAN processor can recover bandwidth lost due to cell
scheduling collisions by scheduling connections at the calcu-
lated Theoretical Arrival Time minus the Limit. A copy of the
scheduled time must be stored in the Channel Descriptor for
each VC scheduled in this fashion for proper operation of the
GCRA.
MXT3010 Reference Manua l Version 4.1 37
Paci ng the transmission rate of cell s
Pacing the transmission rate of cells
The MXT3010 can pace the transmission rate of cells in either
of two ways:
• Back pressure through the UTOPIA port
• Use of an external clock
Back pre ssure
method When the back pressure method is used, the Cell Scheduling
System is a self-pacing system—no external clock is required.
Back pressure from the transmission link through the UTOPIA
port limits the rate at which the SWAN processor can queue cells
for transmission. Therefore, the processor must maintain a con-
tinuously scheduled cell stream at the UTOPIA port. The pro-
cessor maintains this cell stream by issuing idle or u nassi gned
cells when no active VC is scheduled.
As indicated in “Servicing” on page 31, the SWAN processor
determin es if a ti me slot is ass igned or unas signed by tes ting the
state of the Assig ned Cel l f la g b it of t he ESS r egi st er followin g
a POPC inst ruction . If the Assign ed Cell flag bit i s 0, the time
slot is unassigned and an unassigned cell must be queued to
maintain the necessary back pressure. The queuing of unas-
signed cells guarantees that inter-cell emission intervals on the
transmission link remain synchronous with the intervals pro-
grammed into the schedule.
External clock
method When the external clock method is used, the Cell Scheduling
System is no longer a self-pacing system, as an external clock1
is required to indicate cell transmission opportunities. If there
are no cells to be sent, no cells are presented to the PHY. Only
user data cells are presented to the UTOPIA Port for transmis-
sion; no idle cells are sent.
1. Either of the Programmable Interval Timers (PIT0 or PIT1) can be used.
See “R54-R55 Programmable Interval Timer registers” on page 211.
38 Version 4.1 MXT3010 Reference Ma nual
The Cell Scheduling System
Advantages of
each method The bac k press ure meth od is pr efera ble when trans mitti ng cell s
over an ATM transmission link, as the ATM transmission link
must be kept full, and the transmission of idle cells is required.
The extern al cl ock method is pre ferabl e when the MXT30 10 is
connecte d to a switch f abric, as i t saves the sw itch the overhe ad
of dealing with idle cells.
Programming the Cell Scheduling System
The Cell Scheduling System example in Figure 9 shows the
SWAN processor maintaining a pointer that represents the
present transmission time slot, such as the service address, in
R7. In this example R7= 02, the halfword address of the third
location in the Connection ID table.
FIGURE 9.Scoreboard operation
Connection ID 145
Connection ID 47
Available
1
10
Scoreboard before POPC/PUSHC
Connection ID Table
Pointer in R7 representing current time slot
1
10
Ideal next transmission time slot
First available transmission time slot
nearest the ideal time slot
1
00
Scoreboard after POPC
1
10
1
00
Scoreboard after PUSHC
1
11
Connection ID 321
Connection ID 123
Available
MXT3010 Reference Manua l Version 4.1 39
Programming the Ce ll Scheduling Sy stem
The following instructions represent typical cell scheduling
operation:
POPC R10 @R7 If the UTOPIA Port Transmit queue is not full, the
SWAN processor executes a POPC requesting that
the cell scheduler access the Connection ID table
entry that R7 references (location 02), and place that
Connection ID into R10. The cell scheduler copies
the Sco r eboard bit associated with this Connection
ID table entry into the Assigned Cell Flag register,
then clears the Scoreboard bit (see “Scoreboard
after POP C ” in Figure 9). Because t he relevant
Scoreboard bit was set to 1 at the time that POPC
was executed, the Assigned Cell Flag register is set
to 1.
BI $RDY ESS5/0 The SWAN processor first tests for completion of
the POPC instruction (bit 5 in the External Signals
State (ESS) register) using a Branch Immediate (BI)
instruction. The BI instruction specifies a branch to
location $RDY if the point tested (ESS5) is a 0,
indicating the CSS scheduling operation is no
longer in progress.
$RDY BI $SAC ESS4/1 The SWAN processor then tests the Assigned Cell
Flag regi ster (bit 4 in the External Signals State
(ESS) register) using a Branch Immediate (BI)
instruction. The BI instruction specifies a branch to
location $SAC if the point tested (ESS4) is a 1.
$SAC LMFM R16 @R10/
R10 16HW LNK Since the time slot was assigned, the SWAN proces-
sor uses the connection ID returned in R10 to
retrieve the Fast Memory-based Channel Descriptor
for the VC that reserve d t he time slot. The Load
Multiple Fast Memory (LMFM) instruction is used
to copy 1 6 halfwo rds be ginn ing a t the Fa st Me mory
Address specified in R10 into 16 SWAN registers
starting with register R16. To ensure that any
changes to the Fas t M emory locations can be auto-
matically cop ied in to the e n tries sto red in R1 6-R3 1 ,
the Link (LNK) instructio n fiel d op tio n is invo ke d.
40 Version 4.1 MXT3010 Reference Ma nual
The Cell Scheduling System
The SWAN processor uses the information stored in the Channel
Descript or to build or retr ieve a cell for the VC. In a SAR appli -
cation that uses dynamic scheduling as part of the service rou-
tine, the SWAN processor determines when to service the next
connection. The SWAN processor does this by executing a
scheduling algorithm using parameters stored in the Channel
Descriptor. The Channel Descriptor contains the parameters
necessary to determine the connection scheduling rate.
From the information in the Channel Descriptor, the SWAN pro-
cessor determines the next location within the Connection ID
table th at should be sched uled for this VC. Then the SWAN pro-
cessor places the result into a software register, for example
R22. The SWAN processor activates the connection by execut-
ing the PUSHC instruction. The PUSHC instruction requests
that the cell scheduler find an available time slot at or after the
tar get addr ess specif ied in R22, as sign the ch osen time sl ot, and
write the Connection ID fr om regi st er R10 into the Conne ct ion
ID table location corresponding to that time slot.
PUSHC R10 @R22
The cell scheduler translates the tar get address indicated by R22
into a Scoreboard bit position and searches the Scoreboard,
beginni ng at that bit pos ition. In the example shown i n Figure 9,
the cel l schedul er discove rs that a previous connecti on reserve d
the target location. Therefore, the cell scheduler examines the
Scoreboard until it finds an available location. This location is
found two cell slots away from the target location. The cell
scheduler reserves the location fo r the present connection by s et-
ting the Scoreboard bit to 1 (see “Scoreboard after PUSHC” in
Figure 9) and by writing the Connection ID provided by the
SWAN processor in R10 into the selected location. When the
scheduling operation is complete, the cell scheduler reports the
scheduled address in the Cell Scheduling System Scheduled
Address r egi st er (R61). The SWAN processor can r ead this reg -
ister to determine whether the scheduled address meets the CDV
requirements fo r the service being provided.
MXT3010 Reference Manua l Version 4.1 41
Guaranteeing the availability of a location in the Connection ID table
The SWAN processor completes servicing the connection by
incrementing the service address contained in R7, modulo the
Connection ID table size. For example, the SWAN processor
can use the Add Immediate (ADDI) instruction to add 0x0002 to
the address contained in R7 and place the result in R7. If the
Connection ID table size is 4096 entries, the ADDI instruction
can include 4096 as a modulo va lue, limiting the incrementation
process to the lowest order twelve bits. This limitation causes
the inc reme n ta ti on p roc ess to cyc le through t he t abl e l o c ati ons .
ADDI R7 0x0002 R7 MOD4096
Guaranteeing the availability of a location in the
Connection ID table
If the Scoreboard is full while the cell scheduler is servicing or
adding a new connection, the Cell Scheduling System returns an
error by setting bit 15 in R60, the Cell Scheduling System Con-
figuration register. Constant checking for this error bit slows
down the effective operating rate of the device. Rather than
check the error bit setting, use either of these two methods to
ensure that a location is available:
1. Add new connections or ac ti vat e i nactive c onne ct ions only
when unassigned slots are encountered.
2. Maintain a count of the active VCs on the scoreboard,
being careful to adjust for connections (such as pre-allo-
cated CBR connections) that consume more than one slot in
the Scoreboard. Do not admit a new connection that
exceeds the capacity of the Scoreboard.
42 Version 4.1 MXT3010 Reference Ma nual
The Cell Scheduling System
The PUSHC/POPC instruction buffer
The cell scheduler contains a two-deep PUSHC/POPC instruc-
tion buffer. The SWAN processor can issue the following cell
scheduling instructions without entering a stall condition:
• A PUSHC or PUSHF followed by a PUSHC or PUSHF
• A PUSHC or PUSHF followed by a POPC or POPF
Execution of a cell scheduling instruction while the buffer is full
results in a SWAN processor stall until the first operation fin-
ishes.
POPC, PUSHC, POPF, and PUSHF ins tr uction operation
POPC and PUSHC timing
The POPC operati on completes i n eight cycle s from the inst ruc-
tion decode to loading of the rd register . The worst cas e PUSHC
time is 12 cycles from the instruction decode to the Fast Memory
write ackn owledge from the wri te buffe r . If the four -stage wri te
buffer is full at the tim e of the PUSHC o peratio n, this cycle
count increases so that the buffer can be flushed of one entry,
and space for the new write information can be provided.
POPF and PUSHF timing
Both the POPF (Pop Fast) and PUSHF (Push Fast) instructions
manipulat e the i nterna l Score boards without access ing the Con -
nection ID table in Fast Memory. By eliminating unnecessary
accesses to Fast Memory, memory read/write latencies are
avoided.
MXT3010 Reference Manua l Version 4.1 43
POPC, PUSHC, POPF, and PUSHF instruction operation
In POPF, as in POPC, the Cell Schedu ling System translat es the
target address into a Scoreboard bit position. The Cell Schedul-
ing System copies the state of that bit into the Assigned Cell flag
(see be low) , a nd c lea rs the bit lo cat io n. However, POPF dif f ers
from POPC in that the Cell Sche dul ing System does not a cce ss
the Fast Memory and does not provide a Connection ID in the
destination register. The POPF operation completes in five
cycles from the instruction decode.
In PUSHF, as in PUSHC, the Cell Scheduling Syst em translates
the target address into a Scoreboard bit position. The Cell
Scheduling System searches for the first available location in the
Scoreboard at or after that bit position and sets the bit for that
locati on to reserve it. However, PUSHF diff ers from PUSHC in
that the Cell Scheduling System does not write a new Connec-
tion ID into the Connection ID table location corresponding to
the rese rved Scorebo ard bit. Rath er , th e existing Connection ID
at that location is scheduled. The PUSHF operation completes in
12 cycles f rom the instruct ion decode. This is the same spe ed as
an optimum PUSHC that experiences no write buffer delays.
Unlike the PUSHC instruction, PUSHF will never experience
write buffer delays, as it does not perfo rm a Fast Memory writ e.
When servicing a Scoreboard where time slot assignments
rarely vary, a combination of POPF and PUSHF can be used to
service and schedule connections without the overhead of Fast
Memory access.
Connection ID table and Scoreboa rd add ressing
The Cell Scheduling System Configuration register specifies
bits(18:15) of the Connection ID table address. Bits (14:1) of the
Connection ID table address are provided by software in
bits(13:0) of the rsb register specified by POPC and PUSHC
instructions.
44 Version 4.1 MXT3010 Reference Ma nual
The Cell Scheduling System
FIGURE 10.Connection ID table address generatio n
TABLE 6. Connection ID table address bits
The Connection ID table entry generates the Scoreboard address
corres ponding to t h e spec if ied Connec ti on ID table ent r y as fol -
lows:
FIGURE 11.Sco rebo ard address generation
TABLE 7. Scoreboard address bits
Note:Bits [3:0] of the rsb register in POPC or PUSHC instruction select a
tar get bit with in t he 1 6 -bit Scoreboar d entry. (While the Cell Sched-
uling System searches the Scoreboard on the b asis of 32-bit quant i-
ties, the SWAN processo r addresses the Scoreboard on a 16-b it
basis.)
18 17 16 15 14 13 12 11 10 9876543210
Bits Source
[0] Fixed as zero (0)
[14:1] Bits [13:0] of the rsb register in POPC or PUSHC instruction
[18:15] Bit s [11:8] of “R60 The Cell Scheduling System (CSS) Config-
uration register” on page 217
18 17 16 15 14 13 12 11 10 9876543210
Reserved
Bits Source
18:11 Reserved. Write as zeros; ignore on reads
10:1 B its [13:4] of the rsb register in POPC or PUSHC inst ruction
0Fixed as zero (0)
MXT3010 Reference Manua l Version 4.1 45
Initializing the Scoreboard
Initializi ng the Scor eboard
The SWAN processor clears the Scoreboard during its system
initialization routine. The SW AN processor initializes the Score-
board by executing POPF instructions to all of the locations in
the Connect ion ID table. Once the SWAN processo r has cleared
the Scoreboard, it can execute cell-scheduling instructions. For
those portions of the Scoreboard used for cell scheduling, the
program must perform all scheduling changes through the
PUSHC and POPC instructions to ensure that the MXT3010’s
internal mechani sms remain cons istent. However, the SWAN
process or ca n rea d Co nnection ID table entr ies at a ny ti me with
the LMFM instruction, or read the Scoreboard using the LD
instruction, without affecting the internal mechanisms.
Selec ting a Scoreboard size
The Cell S cheduli ng System Configuration register in cludes the
desired Scoreboard size, rounded up to the nearest power of two.
The SWAN processo r can mark ce rtain l ocations as unavai lable
to support Scoreboard sizes other than powers of two.
For example, assume the desi red Schedule size is 2304 bits . The
program can execute a series of PUSHC operations to select a
4096 bit sc hedule and t o mark bits 2304 to 4095 as un available.
From that point on, the cell scheduler will not try to reserve
those lo cations in res ponse to cell s cheduling requ ests. As a pro-
gram executes POP instructions to the Scoreboard, it must return
to the beginning of the Scoreboard when it reaches location
2303. In oth er words, once t he unwanted locati ons are reserv ed,
the program must not specify them as the target address of a POP
operation. Also, the program must calculate the PUSHC target
addresses modulo 2304 instead of modulo 4096.
46 Version 4.1 MXT3010 Reference Ma nual
The Cell Scheduling System
Supporting multiple Scor eboard sections
As indicated in Table 5, “Scoreboard sectioning control,” on
page 29, th e MXT3010 supports multiple Con nection ID t ables/
Scoreboard sections. The device supports a maximum of:
• Eight 2K Connection ID tables/Scoreboard sections
• Four 4K Connection ID tables/Scoreboard sections
• Two 8K Connection ID tables/Scoreboard sections
• One 16K Connection ID table/Scoreboard section
If eight schedules are used, bits [13:11] of the rsb register in
POPC or PUSHC instruct ion sel ect a sche dule wit hin the bl ock
of eight. If four schedules are used, rsb bits [13:12] select a
schedule within the block of four, and so on.
PUSHC/POPC rsb register
address bit(s) Select(s) which schedule for
13 2 x 8K
13:12 4 x 4K
13:11 8 x 2K
MXT3010 Reference Manua l Version 4. 1 47
CHAPTER 4 The Fast Memory Interface
The Fast Memory port provides the SWAN proce ssor and the Cell
Scheduling System with low latency access to external Channel
Descript or s, pr ogr am co de, t ra ffic shaping memor y, and the look
up tabl es used f or Available Bit Rate calcul ations. Th e Fast Me m-
Data
Stream
Cell
Stream
Multi-purpose
DMA (Port2)
UTOPIA
Port
Cell Buffer RAM High
Performance
DMA (Port1)
Data
Stream
Instr uction Cache
SWANTM Processor
Fast Memory
Controller
Cell Scheduling
System
Control
Memory
SRAM
Inter-chip
Signalling
48 Version 4.1 MXT3010 Reference Ma nual
The Fast Memory Interface
ory controller provides a glue-less interface to synchronous,
flow-through, burst-mode cache RAMs. The Samsung
KM718B90 and compatible parts are examples of suitable
RAMs.
This chapter descri b es :
• SWAN processor accesses to Fast Memory
• Cell Scheduling System accesses to Fast Memory
• SWAN executable fetches from Fast memory
• Fast Memory configuration
SWAN processor accesses to Fast Memory
The processor accesses Fast Memory with Load Multiple Fast
Memory (LMFM) and Store Halfword (SHFM) instructions. A
special ized Fast Memory access and update protocol in the Fast
Memory controller accelerates access to and update of Fast
Memory-b ase d data st ruc tur es .
Loading
The software tables and data structures stored in Fast Memory
are ac cessed by the SWAN proce ssor th rough the LMFM (Load
Multip le Fast Memo ry) instruction. A simplified version of th e
LMFM instruction is shown below.
FIGURE 12.Load Fast Memory instruction
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Op Code rd LNK 00 Z rsa #HW rsb
MXT3010 Reference Manua l Version 4.1 49
SWAN processor accesses to Fast Memory
LMFM rd @rsa/rsb #HW [LNK]
The SWAN processor u ses the #HW field to specify th e number
of halfwords to be fetched and the rsa and rsb fields to specify
the Fast Memory byte address at which the transfer will begin.
In response to the LMFM instruction, the Fast Memory interface
contr oller will write the halfwords returned from memory into
the S WAN’s register file beg inning wit h regist er rd and c ontinu-
ing with rd+1, rd+2, etc. until the designated number of half-
words have been transferred. Thus, the LMFM instruction
allows the SWAN processor to transfer up to 16 halfwords1 from
the Fast Memory into the register file in a single instruction.
Memory update
protocol I f the LNK instr uction field option is sp ecified, th e fast memory
interface control ler links t h e l oade d r egi st ers to the locations i n
Fast Memory from which their contents we re read. ALU in struc-
tions which modify these registers can force the modifications to
be written back to Fast Memory by specifying the update mem-
ory (UM) optio n. Thus, the UM function allows the SWAN pro-
cessor to update the data structure in Fast Memory without
executing a dedicated Store instruction. In addition, use of the
LNK option causes the first halfword read from memory to be
read into the Fast Memory Shadow Register (R58), where it can
be used by BF/BFL instructions.
Once a linking relationship has been set up by an LMFM
instru ction, subs equent LMFM in structions d o not need to s pec-
ify a linking optio n, as the links re main in p lace. When it is
desired that the links be changed, a new LMFM with linking
option enab led ca n chan ge the links . An LMFM u sed to change
links does not have to specify a data transfer (#HW can be zero).
1. Since the number of halfwords that can be transferred ra nge from 0 to 16
halfwords, t here are 17 possible values for the #HW field. Therefore, the
#HW field is 5 bits wide.
50 Version 4.1 MXT3010 Reference Ma nual
The Fast Memory Interface
Additional information on the LNK option and memory updat-
ing, including restrictions, appears in “Linking (the LNK bit)”
on page 299 and following pages.
Further
information Further inf ormati on about the LMFM ins truct ion is provi ded in
“Load and Store Fast Memory Instructions” on page 293. Exam-
ples of LMFM instruction usage are provided in that chapter and
in “Swan Instruction Reference Examples” on page 325.
Storing
Fast M emory wr it es can be ac complished ut il i zing the memory
update function described above or by utilizing the Store Half-
word to Fast Me mory (SHFM) instruct ion. A sim plified ve rsion
of the SHFM instruction is shown below.
FIGURE 13.Store Fast Memory instruction
SHFM @rsa/rsb
Execution of the SHFM instruction causes the Fast Memory
interface controller to w rite the halfword contained in the Fast
Memory Dat a regist er (R56) in to the hal fword address ed by th e
byte addr ess contained in registers rsa a nd rsb. A more power ful
store instruction, Store Register Halfword (SRH) is also avail-
able. The SRH instruction is especially useful for accelerating
CRC operations. See “Cyclical Redundancy Check operation
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Op Code 000000000 rsa #HW rsb
MXT3010 Reference Manua l Version 4.1 51
Cell Scheduling System accesses to Fast Memory
acceleration” on page 104 and “Instructions for accelerating
CRC operations” on page 305.
Further
Information Further information about the SHFM and SRH instructions is
provided in “Load and Store Fast Memory Instructions” on
page 293. Examples of SHFM and SRH instruction usage are
provided in that chapter and in “Swan Instruction Reference
Examples” on page 325.
Cell Scheduling System accesses to Fast Memory
The Cell Sche duling System maint ains one or more Conne ction
ID tab les in Fast Memory. The Cell Scheduling System access es
Fast Memory wit h PUSHC and POPC instructi ons issued by th e
SWAN processor . PUSHC instructions cause a halfword write to
a Connection I D table, and POPC ins tructions c ause a halfword
read to a Connection ID table.
Cell Scheduling System operations are a lower priority than
LMFM burst data rea ds. I f a Cell Sc heduling Sys te m opera ti on
is in pro gress when a LM FM is issue d, the Cell Sc heduling Sys -
tem operation finishes but the LMFM is serviced before the next
Cell Scheduling System operation proceeds.
SWAN executable fetches from Fast Memory
The SWAN processor fetches all instructions from the Fast
Memory using 32-bit word read accesses. These accesses are
higher priority than any other access to the Fast Memory. If an
LMFM or Cell Scheduling System operation is in progress when
the SWAN processor makes a Fast Memory read request, the
LMFM or Cell Scheduling System operation finishes but the
read re quest i s ser viced be fore t he next LMFM or Cel l Sche dul-
ing System operation proceeds.
52 Version 4.1 MXT3010 Reference Ma nual
The Fast Memory Interface
Fast Memory configurations
This section describes these configuration features:
• Memory sizes supported
• RAM selection and configuration
• Mode 0 operation for chips with single or multiple Chip
Enable inputs
• Mode 1 operation for chips with multiple Chip Enable
inputs only, allowing 512K banks
• Bus contention avoidance
Memory sizes suppor te d
The Fast Memory interface supports memory sizes from 128
Kbytes t o 1 Mby te in config ura ti ons of one or two banks. I n a ll
configurations Fast Memory is 32 bits wide.
FIGURE 14.Fast Memory SRAM options
CLK
CLK CLK
64K x 16
CLK
Control
Address
Data
512K Bytes, 2 Banks
64K x 16
CLK
64K x 1 6 64K x 1 6
32K x 32
256K Bytes 128K Byt es
(1 MB wit h 128Kx16 RA M s) (512KB with 128Kx16R AMs)
MXT3010
MXT3010 Reference Manua l Version 4.1 53
Fast Memory configurations
RAM selection and configuration
The MXT3010 supports the following RAM configurations:
Mode 0 operation
The MXT3010 provides two operation modes for the Fast Mem-
ory. Table 8 compares t he two mode s, which c an be sel ecte d by
modifying target bit 4 in the Mode Configuration Register
(R42):
In Mode 0 the MXT3010 drives 16 address bits and four inde-
pendent byte enables to permit direct addressing of 64K 32-bit
words in each of two memory banks. T wo chip select signals and
two output enable signals provide independent bank selection
and output drive enable signals for the two memory banks.
Address bit F ADRS[18] internally generates the select signal for
the active bank. Physical memory appears as two contiguous
64Kx32 banks starting in address space at 0x00000, going to
0x7FFFF.
Memory Size RAM Banks Mode
128K Bytes 32Kx32 1 – 32Kx32 1 0
256K Bytes 64Kx32 2 – 64Kx16 1 0
512K Byte s 128Kx32 4 – 64Kx16 2 0
512K Byte s 128Kx32 2 – 128Kx16 1 1
1M Byte 256Kx32 4 – 128Kx16 2 1
TABLE 8. Comparison of Mode 0 and Mode 1 operation
Attribute Mode 0 Mode 1
Types of access supported Byte or hal f word Byte or halfword
Device Chi p Enable configu ratio ns Single or multip le Multiple only
Maximum addressable memory 512 Kbytes 1 Mbyte
54 Version 4.1 MXT3010 Reference Ma nual
The Fast Memory Interface
FIGURE 15.Mode 0 design example
Mode 1 operation
In Mode 1 the MXT3010 drives 18 address bits and four inde-
pendent byte enables to directly address 256K 32-bit words in
each of two memory banks. Two output enable signals provide
independent output drive enable signals for the two memory
banks. No ch ip ena ble signals are us ed; add ress b it FADRS[19]
select s the acti ve bank. Physic al memory appea rs as two cont ig-
uous 128Kx32 banks starting in address space at 0x00000 and
ending at 0xFFFFF. One of the two banks is always enabled
since no independent chip enable signals are used.
In a single bank configuration, Mode 1 can configure only 512
Kbytes of Fas t Memory using 128 Kx16 RAMs. In t hi s c onf igu -
ration, physical memory appears as a single 128Kx32 bank in
address space from 0x00000 to 0x7FFFF.
The Connection ID table and the executable code space (as set
by the Segment ID field in the Instruction Base Address register)
can only reside in the first 512K bytes of Fast Memory.
FADRS[17:2]
FDAT[31:0]
Control
D[31:16]
A[17:2]
FCS1_
A15-A0
D15-D0
CS_
OE_
BW1_
BW0_
FOE1_
FWE0_
FWE1_
D[15:0]
A[17:2]
FCS1_
A15-A0
D15-D0
CS_
OE_
BW1_
BW0_
FOE1_
FWE2_
FWE3_
D[31:16]
A[17:2]
FCS0_
A15-A0
D15-D0
CS_
OE_
BW1_
BW0_
FOE0_
FWE0_
FWE1_
D[15:0]
A[17:2]
FCS0_
A15-A0
D15-D0
CS_
OE_
BW1_
BW0_
FOE0_
FWE2_
FWE3_
64K x 16 64K x 16
64K x 16
64K x 16
0x00000-0x3FFFF
0x40000-0x7FFFF
MXT3010
Bank 0
Bank 1
MXT3010 Reference Manua l Version 4.1 55
Fast Memory configurations
FIGURE 16.Mode 1 design example
Bus contention avoidance
The timing of the two output enable signals (FOE1_ and
FOE0_) is skewed when the addresses of consecutive memory
accesses cross bank boundaries to prevent bus contention on
back-to-back read cycles . The MXT3010 guarantees a window1
between disabling one bank and enabling an alternate bank. This
allows both banks to be directly wired to the data bus without
external buffers or transceivers.
1. Please refer to “Timing” in Section 3 for further information.
FADRS[19:2]
FDAT[31:0]
Control
D[31:16]
A[18:2]
A[19]
A16-A0
D15-D0
CS_
CS+
OE_
BW1_
VDD
FOE0_
FWE0_
128K x 16
0x00000-0x7FFFF 0x80000-0xFFFFF
MXT3010
BW0_
FWE1_
D[15:0]
A[18:2]
A[19]
A16-A0
D15-D0
CS_
CS+
OE_
BW1_
VDD
FOE0_
FWE2_
128K x 16
BW0_
FWE3_
D[31:16]
A[18:2]
A[19]
A16-A0
D15-D0
CS_
CS+
OE_
BW1_
VSS
FOE1_
FWE0_
128K x 16
BW0_
FWE1_
D[15:0]
A[18:2]
A[19]
A16-A0
D15-D0
CS_
CS+
OE_
BW1_
VSS
FOE1_
FWE2_
128K x 16
BW0_
FWE3_
When operating in Mode 1, the Chip Select pins are used as Fast Memory Address lines 19 and 18.
FCS1_ = FADRS[19]. FCS0_ = FADRS[18]
56 Version 4.1 MXT3010 Reference Ma nual
The Fast Memory Interface
Fast Memory sequence diagrams
This section shows sequence diagrams for the following Fast
Memory operations:
• Read operations, single bank (Figure 17 on page 56)
• Write operations, single bank (Figure 18 on page 57)
• Read a nd write opera tions, back- to-back oper ation and d ual
bank (Figure 19 on page 57)
Set-up times, propagation times, and other timing information
for the Fast Memory interface are provided in “Timing” on
page 343.
FIGURE 17.Fast Memory read operations - single bank
CLK
FCS0_
FADRS[17:2] A0 A1 A2
D0 D1 D2
FDATin[31:0]
F
DATout[31:0] high impeda nce high imped a nce
FOE0_ low
0xF WE0 WE1 WE2 0xF
FWE[3:0]_
MXT3010 Reference Manua l Version 4.1 57
Fast Memory sequence diagra ms
FIGURE 18.Fast Memory write opera tions - single bank
FIGURE 19.Fast Memory reads and writes - b ack-to-back and du al bank
CLK
FCS0_
FADRS[17:2] A0 A1 A2
FDATin[31:0]
F
DATout[31:0]
FOE0_
0xF WE0 WE1 WE2 0xF
FWE[3:0]_
D0 D1 D2
CLK
FCS0_
FADRS[17:2] A0 A1 A2
FDATin[31:0]
FDATout[31:0]
FOE0_
FWE[3:0]_
D4
Read
Bank 1
A3
Read
Bank 0
Read
Bank 0
Read
Bank 0 A4 A5 A6
Write
Bank 1 Read
Bank 0 Write
Bank 1
D6
D2
D0 D1
FDATin[31:0]
Driven by Bank 0
Driven by Bank 1
D3 D5
FOE1_
FCS1_
0xF 0xF 0xF 0xF WE4 0xF
WE6
0xF 0xF
58 Version 4.1 MXT3010 Reference Ma nual
The Fast Memory Interface
MXT3010 Reference Manua l Version 4. 1 59
CHAPTER 5 The Cell Buffer RAM
The MXT3010’s internal Cell Buffer RAM buffers cells in both
the transmit and receive directions. The CPU and the DMA unit
can access the Cell Buffer RAM through memory access proto-
cols. This chapter describes the Cell Buffer RAM and the memory
access protocols.
Data
Stream
Cell
Stream
Multi-purpose
DMA (P ort2)
UTOPIA
Port
Cell Buffer RAM High
Performance
DMA (Port1)
Data
Stream
Instruction Cache
SWANTM Processor
Fast Memory
Controller
Cell Scheduling
System
Control
Memory
SRAM
Inter-chip
Signalling
60 Version 4.1 MXT3010 Reference Ma nual
The Cell Buffer RAM
Internal cell storage in the Cell Buffer RAM
To store cells, the Cell Buff er RAM is configured int o a number
of 64 byte blocks referred to as cell holders. During reception,
cel ls are written into cell holders as they are received from the
physical layer. During transmission, cells are built in cell hold-
ers before being transmitted to the physical layer.
At device i nitiali zation, th e Cell Buff er RAM is segment ed into
sections for receive cell stor age, trans m it cel l constru ction, and
general purpose s cratch pad use. As shown in Table 9, bi ts [6:1]
of the UTOPIA Configuration register(R62) control the seg-
mentation of the Cell Buffer RAM.
TABLE 9. UTOPIA Configuration control of the Cell Buffer RAM
Bits Description
3:1 Receive Cell Buffer Size in the Cell Buffer RAM
000
001
010
----
110
111
UTOPIA Port Receiver in Reset Mode. All Rx outputs are
tristated. This includes RXDATA (a bidirectional signal), but
does not include RXCLK. All inputs are pulled to their inac-
tive states by the MXT3010.
Receiver Buffer Size in the Cell Buffer RAM = 2 cells
Receiver Buffer Size in the Cell Buffer RAM = 3 cells
Receiver Buffer Size in the Cell Buffer RAM = 7 cells
Receiver Buffer Size in the Cell Buffer RAM = 8 cells
6:4 Transmit Cell Buffer Size in the Cell Buffer RAM
000
001
010
----
110
111
UTOPIA Port Transmitter in Reset Mode. All Tx outputs are
tristated except T XC LK. All i nput s are pull ed to th eir in active
states by t he M X T3010.
Transmitter Buffer Size in the Cell Buffer RAM = 2 cells
Transmitter Buffer Size in the Cell Buffer RAM = 3 cells
Transmitter Buffer Size in the Cell Buffer RAM = 7 cells
Transmitter Buffer Size in the Cell Buffer RAM = 8 cells
MXT3010 Reference Manua l Version 4.1 61
Internal cell storage in the Cell Buffer RAM
The minimum allocation for receive cell holders is two, the
maximum is e ight, and receive r cell h older add ressing begins at
location 0x0000. The minimum allocation for transmit cell hold-
ers is two, the maximum is eight, and trans mit cell holder
addressing begins at locati on 0x0200. As an example, Figure 20
shows a Cell Buffer RAM organization with eight receive cell
holders, four transmit cell holders, and the remaining space
available as scratch pad space.
FIGURE 20.Cell Buffer RAM organization
Rx Cell 64 bytes
Rx Cell 64 bytes
Rx Cell 64 bytes
Rx Cell 64 bytes
Rx Cell 64 bytes
Rx Cell 64 bytes
Rx Cell 64 bytes
Rx Cell 64 bytes
Tx Cell 64 bytes
Tx Cell 64 bytes
Tx Cell 64 bytes
Tx Cell 64 bytes
0x0000
0x0040
0x0080
0x00C0
0x0100
0x0140
0x0180
0x01C0
0x0200
0x0240
0x0280
0x02c0
0x0300
0x0340
0x0380
0x03C0
64 bytes
64 bytes
64 bytes
64 bytes
62 Version 4.1 MXT3010 Reference Ma nual
The Cell Buffer RAM
Cell fields Independent of the specific cell format used, certain fields (if
provided) occupy certain positions. Figure 21 shows these
fields, and Table 10 summarizes their functions.
FIGURE 21.Cell fields defined
TABLE 10. Cell field functions
Cell formats The format of the information in the cell holders is a function of
the sel ection of 52-byt e or 56-b yte cell operati on via bi t 1 of the
“R42-write Mode Configuration register” on page 201.
Field Function
User
Header The User Header is a four-byte field that can be inserted before
the ATM header, adding four bytes to the front of a cell.
ATM
Header The ATM Header is a four-byte field s peci fied by relevant
ATM standards and consists of GFC, VPI, VCI, and PTI sub-
fields. It is generally present in all but a few proprietary
schemes. The VPI and VCI sub-fields are interpreted by
UTOPIA Receive Header Reducti on hardware in the
MXT3010 to form the Channel Identifier for the cell. See
“Receive Header Reduction hardware ” on page 91.
HEC The Header Error Control (HEC) is a one-byte CRC accumu-
lated ac ross the ATM Header. The MXT3010 can be confi g-
ured to transmit and receive cells with or without HEC.
SAR PDU The SAR PDU is a 48-byte field that is present in every cell.
User Header
ATM Header
HEC
SAR PDU
Present in proprietary 56-byte cells only
Present in all cells
Optionally present in cells
Present in all cells
4 bytes
4 bytes
1 byte
48 bytes
Bit Bit State and Function
1Cell Length Con tro l
052 byte cells
156 byte cells
MXT3010 Reference Manua l Version 4.1 63
Internal cell storage in the Cell Buffer RAM
Figure 22 compares the 52-byte and 56-byte cell formats.
FIGURE 22. Receive cell organization: 52-byte and 56-byt e cells
Figure 22 does not show the HEC byte, because the HEC byte
(if e nabled) is never w ritten to or read from the Cell Buffer
RAM. Rather, HEC generation/insertion on transmission and
HEC checking/removal on reception are performed at the
UTOPIA port1. The result of HEC verification is available in the
Receive C ell Status Wo rd. See Figu re 22 and “Re ceive cell
flow” on page 77.
Receive Cell
Status location While th e ATM Header bytes and the SAR PDU byte s are fix ed
with respect to the cell holder in both the 52-byte and 56-byte
mode, the location of the Receive Cell Status W ord does change.
1. The MXT3010 also provides HEC gen eration and checking logic for
devices not using th e UTOPIA port.
Unused
Receive Cell Status Word
ATM Header bytes 0, 1
ATM Header bytes 2, 3
SAR PDU bytes 0, 1
SAR PDU bytes 2, 3
SAR PDU bytes 4, 5
SAR PDU bytes 6, 7
SAR PDU bytes 44, 45
0x0000
0x0002
0x0004
0x0006
0x0008
0x000A
0x000C
0x000E
0x0010
0x0034
0x0036
0x0038
0x003A
0x003C
0x003E
Unused
Unused
Unused
Unused
SAR PDU bytes 7, 8
SAR PDU bytes 46, 47
User Header bytes 0, 1
Receive Cell Status Word
AT M Header bytes 0, 1
ATM Header bytes 2, 3
SAR PDU bytes 0, 1
SAR PDU bytes 2, 3
SAR PDU bytes 4, 5
SAR PDU bytes 6, 7
SAR PDU bytes 44, 45
Unused
Unused
Unused
SAR PDU bytes 7, 8
SAR PDU bytes 46, 47
User Header bytes 2, 3
52-byte cell 56-byte cell
64 Version 4.1 MXT3010 Reference Ma nual
The Cell Buffer RAM
In 52-b yte mode , it prece des the ATM Header fie ld, while in 56-
byte mode, the four-byte User Header precedes the ATM
Header, and the Receive Cell Status Word follows the last byte
of the SAR PDU. The placement of the Receive Cell Status
Word beyond the last byte of the SAR PDU in 56-byte mode
conflicts with the concept of Cell Buffer RAM memory gather-
ing as d escribed in “Gather method accesses” on page 65. Mem-
ory gathering is st ill a valid means of addressing the unused Cell
Buffer RAM space, however the presence of the Receive Cell
Status Wo rd within each receive cell holder must be accommo-
dated.
Cell Buffer RAM memory construction
As shown in Figure 20, “Cell Buffer RAM organization,” on
page 61, the Cell Buffer RAM is logically constructed as sixteen
64-byte c ell holders. As shown in Figure 22, “Receive cell or ga-
nizati on: 52-byte and 56-byte c ells,” on page 63, a cell occupies
no more tha n the t op 56 or 58 by tes of a c ell ho lder. This leave s
approximately eight bytes of RAM at the bottom of each cell
holder location. This space is discontinuous and therefore diffi-
cult to use. So that the CPU can regain access to this unused
memory as a s ingle li near spac e, the Cell Buffer RAM interf ace
supports both a linear access and a memory gathering protocol.
Select ing an
access method Both the CPU and the DMA controllers can access the Cell
Buffer RAM by using either linear or gather access methods.
The CPU uses register rla and the Index field (IDX) in the LD
(Load), LDD (Load Double), ST (Store), and STD (Store Dou-
ble) instructions to form an address in the Cell Buffer RAM. See
“Register load address (rla field)” on page 314 and “The index
field (IDX)” on page 315. DMA controllers use register rla in
the DMA1 or DMA2 instruction to form an address in the Cell
Buffer RAM. See “Direct Memory Access Instructions” on
page 283.
MXT3010 Reference Manua l Version 4.1 65
Cell Buffer RAM memory construction
Whether generated by a CPU instruction or a DMA controller,
Bit [10] of the local address selects the access method of the Cell
Buffer RAM.
Linear method
accesses In linear method accesses, the Cell Buffer RAM is treated as a
simple contiguous memory 1024 bytes in length. Bits [9:1] of
the target address select the 16-bit halfword within this space.
Gather method
accesses In gather method accesses, the last eight bytes of each 64-byte
section appear as a contiguous 128-byte block of memory. The
first 16-bit halfword of this block is at address 0x0400 of the
gather address method. The last 16-bit halfword is at address
0x047E. Thus, gather access recovers discontinuous regions of
Cell Buffer RAM memory into one continuous address space.
This is not additional space, but rather a method of making use
of small pieces of existing space. Figure 23 illustrates this
addressing method.
Bit 10 Cell Buffer RAM method selected
0Linear
1Gather
66 Version 4.1 MXT3010 Reference Ma nual
The Cell Buffer RAM
FIGURE 23.Gather method accesses
Please note the restrictions on gather access in 56-byte mode
(see “Receive Cell Status location” on page 63). For additional
information, please see “Cell Buffer RAM accesses” on
page 317.
Cell Store 0
Cell Store 1
Cell Store 15
0x0000
0x0038
0x0040
0x0078
0x0080
0x03C0
0x03B8
0x0400
0x03F8
0x0400
0x0408
0x0410
0x0480
0x047E
MXT3010 Reference Manua l Version 4.1 67
Cell Buffer RAM access
Cell Buffer RAM access
The MXT3010EP Cell Buf fer RAM has five independent 16-bit
ports, each capable of moving data at the internal clock fre-
quency. The arrangement of data ports is shown in Figure 24.
FIGURE 24.Cell Buffer RAM access
On a 100 MHz devic e, t he three re ad ports ca n de li ver data at a
total rate of 600 MB per second, and the two write ports can
accept a total of 400 MB per second.
Making optimum use of this high performance design requires
some programming care, however. While Load and Store
instructions from the SWAN processor are guaranteed to be
ordered with respect to one another, ordering is not guaranteed
between L oad/Store instructions and DMA operations to Port1
or Port 2. Consider the following example:
STD R0/R1 @R48
STD R2/R3 @R49
STD R4/R5 @R50
DMA1W rsa/rsb R50
Cell Buffer
RAM 512 x 16
A
B
C
D
E
Port1 Read
UTOPIA Tx/
Port2 Read
CPU Read
Port1/CPU Write
Port2/UTOPIA RX/
CPU Write
SW AN Processor
Load/S tore Pip e
Port C Port D/E
CPU rd ad dr CPU write addr
68 Version 4.1 MXT3010 Reference Ma nual
The Cell Buffer RAM
The Port1 write operation is not guaranteed to see the new val-
ues of R4/R5. This is true because Store Double (STD) instruc-
tions are retired in the Cell Buffer RAM at half the rate they can
be issued by the SWAN, and the SWAN does not have a dedicate
write pipe into the Cell Buffer RAM.
To guarantee correct behavior, the program must do one of the
following:
1. Guarantee that at least one of the write ports is always available to
ensure that the DMA from Port1 or Port2 can never fetch stale
data. The pipelining of the DMA operation guarantees th at it will
not fetch data bef ore it is flushed from the S WAN Load/S tore p ipe
into Cell Buffer RAM.
2. Follow all stores by a dummy read prior to issuing a DMA com-
mand. The read ensures that all preceding writes are flushed in the
pipe. Note that since the Load Double (LD) is offloaded from the
host, it must be followed by an instruction that uses the destination
of the load to invoke the hardware register scoreboarding mecha-
nism.
3. Use successive writes to ensure that preceding writes are flushed
through th e pipe into the Cell Buffer RAM.
MXT3010 Reference Manua l Version 4. 1 69
CHAPTER 6 The UTOPIA port
The UT OPIA por t impleme nts the ATM Forum’s UTOPI A Level
1 and Level 2 protocol for interfacing ATM Layer devices, such
as the MXT3010, to PHY Layer devices, such as SONET framers.
The UTOPIA port supports the direct attachment of up to 16 sin-
gle PHY or multiple logical PHY devices. In addition, the UTO-
PIA port supports the direct attachment of a Level 2-compliant
Data
Stream
Cell
Stream
Multi-purpose
DMA
UTOPIA
Port
Cell Buffer RAM High
Performance
DMA
Data
Stream
Instruction Cache
SWANTM Processor
Fast Memory
Controller
Cell Scheduling
System
Control
Memory
SRAM
Inter-chip
Signalling
70 Version 4.1 MXT3010 Reference Ma nual
The UTOPIA port
Multi-PHY device with up to 16 ports. In compliance with the
ATM Forum specificatio n, the UT OPIA c onnecti on oper ates a s
the Master device.
This chapte r incl ude s:
• UTOPIA port interface overview
• Receive cell flow
• Transmit cel l flow
• The control byte and special operations
• Multi-PHY support
• Receive Header Reduction hardware
• UTOPIA por t configuration summary
UTOPIA port interface overview
Features
The UTO PIA port interf ace includes the follo wing features:
• Two modes of operation are supported, 8-bit bi-directional
mode and 16-bit unidirectional mode (either transmit or
receive).
• The UTOPIA port supports up to 16 physical ports in 8-bit
bi-directional mode. The UTOPIA port complies with the
ATM Forum’s Level 2 Specification for Multi-PHY Opera-
tions.
• Cell-level handshaking is supported. No wait states are
inserted, and no wait states are expected.
• 56-byte cell mode over the UTOPIA interface is supported
for applications w here a fi eld is prepended to an ATM cell.
• HEC insertion and checking can be enabled.
MXT3010 Reference Manua l Version 4.1 71
UTOPIA port int erface overvi ew
Operating modes
The UTOPIA port can be configured to operate in bi-directional mode
with an 8-bit Receive (Rx) data path and an 8-bit Transmit (Tx) data
path, or in uni direc tiona l mode as eithe r a 16-bi t T r ansmit ter or a 16-bit
Receiver. The 16-bit mode supports 622 Mb/s data rates.
Selecting 8-bit or
16-bit mode Bit [8] of t he UT OPIA Con figurati on regi ster (R62) co ntrol s the ope rat-
ing mode.
In 16-bit transmit mode, the TxData pins carry data [7:0]. The RxData
pins are configured as outputs and carry data [15:8]. In 16-bit receive
mode, the RxData pi ns car ry data [ 7:0]. Th e TxData pins a re configu red
as inputs and carry data [15:8].
Resetting the
transmitter and
receiver
Bits [6:4] of the UTOPIA Configuration register (R62) control the
T ransmit Cel l Buf fer size in the Cell Buf fer RAM, and bits [3:1 ] control
the Receive Cell Buffer size. Definitions for these bits appear in T able 9,
“UT OPIA Conf ig ura ti on c ontrol of the Cell Buffer RAM,” on page 60.
While t hes e bi ts prima ri ly affect the o per ation of the Cell Buff er RAM,
a buffer size selection of 0 cells places the corresponding transmit or
receive UTOPIA interface in reset mode. In reset mode the correspond-
ing output signals are placed into their inactive states.
TABLE 11. UTOPIA port data bus width selection
Bit Description
8 UTOPIA Port Data Bus Width
0
116 Bit s Wide
8 Bits Wide
TABLE 12. UTOPIA port Tx and Rx pin utilization in 16-bit mode
Mode Tx Data Pins Rx Data Pins
16-bit transmit Data [7:0] Data (outputs) [15:8]
16-bit receive Data (inputs) [15:8] Data [7:0]
72 Version 4.1 MXT3010 Reference Ma nual
The UTOPIA port
Selecting transmit
or receive mode Transmit-only operation is selected by setting bi ts [3:1] of the
UTOPIA Configuration register (R62) to zeroes, thus placing
the UTOPIA port rec eiver in reset mode . Receive-o nly opera-
tion is sel ected by setting bits [6:4] of th e UTOPIA C onfigura-
tion (R62) to zeroes, thus placing the UTOPIA port transmitter
in reset mode. Figure 25 shows a UTOPIA port using 8/8- and
16-bit modes.
FIGURE 25.The UTOPIA port: 8/8 and 16-b it modes
Selecting cel l
length and HEC
operation
The UT OPIA configur ation operat ion u ses R42 , bits 0 and 1, to
select HEC operation and cell length.
UTOPIA speed
select The MXT3010 can operate each UT OPI A interfa ce (t ran smit
and receive) either at the input clock frequency or at one-half
that frequency . Since the SWAN processor in ternal clock runs at
Tx Control Rx
MXT3010
8-bit transmit
8-bit receive
Rx Control Rx
MXT3010
16-bit receive
Tx Control Tx
MXT3010
16-bit transmit
SONET Framer
OC3 SONET Framer
OC12
8888
8
8
TABLE 13. Cell length and HEC control
Bit Description
0 HEC Control
0 HEC is generate d (Tx), inser ted (Tx), and checked (Rx)
1 HEC is omitted
1 Cell Leng th Con tro l
0 52-byt e cells
1 56-byt e cells
MXT3010 Reference Manua l Version 4.1 73
UTOPIA port int erface overvi ew
twice the input clock frequency, these selections correspond to
one-half or one-quarter of the internal clock frequency. The
MXT3010 generates a UTOPIA output clock for each of the
transmi t and r eceive inter face s based on the s etti ng of th e clock
selection bit in the UTOPIA Configuration register (R62). All
PHY to ATM layer transfers should be controlled from the rising
edge of these clocks.
UTOPIA Port
clock phases Fi gure 26 and F igure 27 sh ow the rela tionship between the chip
input clock, the internal clock, and TXCLK and RXCLK oper-
ating at 1/2 and 1/4 of the inter nal clock frequency, respectivel y.
FIGURE 26.Clock phases for RX/TX CLK = 1/2 Internal Clock
FIGURE 27.Clock phases for RX/TX CLK = 1/4 Internal Clock
TABLE 14. UTOPIA port clock selection
Bit Description
7 UTOPIA Port operational/output clock selection
0 TXCLK and RXCLK operate at 1/2 of internal clock frequency.
1 TXCLK and RXCLK operate at 1/4 of internal clock frequency.
INTERNAL CLK
INPU T C LK
RX CLK
TX CLK
INTERNAL CLK
INPU T C LK
RX CLK
TX CLK
74 Version 4.1 MXT3010 Reference Ma nual
The UTOPIA port
UTOPIA cell formats
Two standard formats for cells are defined for UTOPIA inter-
faces depending on the width of the data bus in use. Addition-
ally, proprietary schemes may define arbitrary cell lengths and
formats as long as the format is commonly understood by the
components on the bus. Figure 28 shows the standard cell for-
mats fo r UTOPIA int erfaces.
FIGURE 28.UTOPIA 8-bit and 16-bit cell formats
In th e ca se of cell s r eceived through a 16-b it UTOPIA port, the
PHY inserts an additional byte after the HEC to ensure that the
SAR PDU data structure presented to the UTOPIA port is 16-bit
aligned . Aft er the HEC has bee n che cke d by t he UTOPI A port ,
both the HEC and the extra byte are deleted before the cell is
stored in the Cell Buffer RAM. In the case of cells transmitted
through a 16-bit UTOPIA port, the UTOPIA port inserts an
additional byte after the HEC to ensure that the data structure
presented to the PHY is 16-bit aligned. The PHY transmits the
HEC over the SONET interface, but discards the extra byte.
Cell format
examples The fol lo wing f igures show exa mple s of HEC-enabled 52-by te
mode, HEC-disabled 52-byte mode, HEC-enabled 56-byte
mode, and HEC-disabled 56-byte mode.
1
2
3
4
5
6
7
8
--
51
52
53
8-bit UTOPIA
ATM Header
HEC
SAR PDU
16-bit UTO PIA
ATM Head er
HEC
SAR PDU
1
3
5
6
8
10
--
50
52
2
4
xxx
7
9
11
--
51
53
MXT3010 Reference Manua l Version 4.1 75
UTOPIA port int erface overvi ew
FIGURE 29.HEC-enabled 52-byte mode
FIGURE 30.HEC-disabled 52-byte mode
1
2
3
4
5
6
7
8
--
51
52
8-bit UTOPIA
ATM Header
SAR PDU
Unused
Receive Cell Status Word
ATM Header bytes 0, 1
ATM Header bytes 2, 3
SAR PDU bytes 0, 1
SAR PDU bytes 2, 3
SAR PDU bytes 4, 5
SAR PDU bytes 6, 7
0x0000
0x0002
0x0004
0x0006
0x0008
0x000A
0x000C
0x000E
0x0010
0x0036
0x0038
0x003A
0x003C
0x003E
Unused
Unused
Unused
Unused
SAR PDU bytes 7, 8
SAR PDU bytes 46, 47
52-byte cell
HEC
53
16-bit UTOPIA
ATM Header
HEC
SAR PDU
1
3
5
6
8
10
--
50
52
2
4
xxx
7
9
11
--
51
53
1
2
3
4
5
6
7
--
50
51
52
8-bit UTOPIA
ATM Header
SAR PDU
Unused
Receive Cell Status Word
ATM Header bytes 0, 1
ATM Header bytes 2, 3
SAR PDU bytes 0, 1
SAR PDU bytes 2, 3
SAR PDU bytes 4, 5
SAR PDU bytes 6, 7
0x0000
0x0002
0x0004
0x0006
0x0008
0x000A
0x000C
0x000E
0x0010
0x0036
0x0038
0x003A
0x003C
0x003E
Unused
Unused
Unused
Unused
SAR PDU bytes 7, 8
SAR PDU bytes 46, 47
52-byte cell
16-bit UTO PIA
ATM Head er
SAR PDU
1
3
5
7
9
11
--
49
51
2
4
6
8
10
12
--
50
52
76 Version 4.1 MXT3010 Reference Ma nual
The UTOPIA port
FIGURE 31.HEC-enabled 56-byte mode
FIGURE 32.HEC-disabled 56-byte mode
2
3
4
5
6
7
8
9
10
11
8-bit UTOPIA
User Header
SAR PDU
16-bit UTOPIA
1
5
7
9
10
12
14
2
13
15
User Header
HEC
SAR PDU
User Header bytes 0, 1
ATM Header bytes 0, 1
ATM Header bytes 2, 3
SAR PDU bytes 0, 1
SAR PDU bytes 2, 3
SAR PDU bytes 4, 5
SAR PDU bytes 6, 7
0x0000
0x0002
0x0004
0x0006
0x0008
0x000A
0x000C
0x000E
0x0010
0x0036
0x0038
0x003A
0x003C
0x003E Unused
Unused
Unused
SAR PDU bytes 7, 8
SAR PDU bytes 46, 47
56-byte cell
User Header bytes 2, 3
Receive Cell Status Word
1
ATM Header
12
--
55
56
57
HEC
4
3
ATM Header
6
8
xxx
11
-- --
54 55
56 57
2
3
4
5
6
7
8
9
10
11
8-bit UTOPIA
User Header
SAR PDU
16-bit UTOPIA
1
5
7
9
11
13
2
12
14
User Header
SAR PDU
User Header bytes 0, 1
ATM Header bytes 0, 1
ATM Header bytes 2, 3
SAR PDU bytes 0, 1
SAR PDU bytes 2, 3
SAR PDU bytes 4, 5
SAR PDU bytes 6, 7
0x0000
0x0002
0x0004
0x0006
0x0008
0x000A
0x000C
0x000E
0x0010
0x0036
0x0038
0x003A
0x003C
0x003E Unused
Unused
Unused
SAR PDU bytes 7, 8
SAR PDU bytes 46, 47
56-byte cell
User Header bytes 2, 3
Receive Cell Status Word
1
ATM Header
--
54
55
56
4
3
ATM Header
6
8
10
-- --
53 54
55 56
MXT3010 Reference Manua l Version 4.1 77
Receive cell flow
Receive cell flow
The UTOPIA Receiver transfers cells from an external framing
devic e into th e Cell Buffer RAM. All cells received from the
phys ical layer device are w ritten into the Cell Buffer RAM. If
HEC insertion and checking is enabled in the Mode Configura-
tion Register (R42), the validity of the cell’ s HEC byte is marked
in bit 9 of the Receive Cell Status field. If HEC insertion and
checking is disabled, bit 9 should be ignored.
Since Head er Error Contr ol (HEC) genera tion and check ing is a
PHY Layer function1, the MXT3010 discards the HEC field
before copyin g the ce ll into th e Cell Buf fer RAM. As a resu lt, a
cell in the Cell Buffer RAM consists of 52 contiguous bytes with
no gap existing between the ATM Header and the SAR PDU.
The UTOPIA port writes receive cells into the Cell Buffer RAM
beginning at location 0x0000. The UTOPIA Receiver writes
successive cells into successive cell buffers in the Cell Buffer
RAM. During de vice initia lization, the pro grammer can spe cify
how many cells the UTOPIA Receiver can use. If the Receiver
buffer size is set to six cells, for example, the Receiver loops
around af ter t he si xth cel l and b egins wr iti ng cell s agai n at loca -
tion 0x00 00 in the Cell Buf fer RAM. If the Receiver buf fer size
is set to eight cells, the receiver loops around after the eighth cell
and begins writing cells again at location 0x0000 in the Cell
Buffer RAM.
1. Fo r applic ations whi c h do not us e the UTOPIA port, HEC generation and
checkin g is provided in the SWAN processo r. See “HEC gen eration and
check circuit” on page 25.
78 Version 4.1 MXT3010 Reference Ma nual
The UTOPIA port
A Receive Cell St atus word is stored in Cell Buffer RAM at the
completi on of each receive cell. The format of the Receive Cell
Status word is :
The location of the Receive Cell Statu s word in the Cell Buffe r
RAM is dependent on the configured cell length, 52 or 56 bytes.
For more information, see “Receive Cell Status location” on
page 63.
UTOPIA receiver counters
The UTOPIA Receiver contains two counters, RXBUSY and
RXFULL, that track cells received from the PHY layer and
stored in the Cell Buffer RAM. Figure 33 on page 79 and
Figure 34 on page 81 show how these counters are used in the
reception process. A written description follows in “The
RXBUSY counter” on pag e 79 and in “The RXFULL counter”
on page 81.
15 14 13 12 11 10 9876543210
Reserved HE CE PTI Copy PHY Addr
Bits Name Function
4:0 PHY Addr ess The address of the PHY from which this ce ll was
received.
7:5 PTI Copy A copy of the Payload Type Indicator field f rom the
received cell header.
8 CE CRC10 Error
When set to one (1), this bit indicates an erroneous
CRC was received. Otherwise, this bit is zero (0).
This bit sho uld b e ignored when C RC10 is no t in use.
9HE HEC Error
When set to one (1), this bit indicates an erroneous
HEC was received. Otherwise, this bit is zero (0).
This bit should be ignored when HEC is not in use.
15:10 Reserved These bits should be ignored on reads.
MXT3010 Reference Manua l Version 4.1 79
Receive cell flow
FIGURE 33.The RXBUSY counter
The RXBUSY counter
Function The RXBUSY counter tracks the arriv al of ne w cells in the Ce ll
Buffer RAM awaiting CPU servicing. The device initialization
process clears the RXBUSY counter to zero.
Incrementing As the UTOPIA receiver places the last byte of a cell into the
receive section of the Cell Buffer RAM, it increments the
RXBUSY counter.
Signals driven The RXBUSY signal of the RXBUSY counter drives bit 9 of the
External Stat e Signals (ES S) registe r (R42). The SWAN proces-
sor tests ESS9 to determine when one or more cells are awaiting
processing by the CPU in the Cell Buffer RAM:
• If ESS9 = 0, no cells are awaiting processing.
• If ESS9 = 1, one or more cells are awaiting processing.
The CPU can use the ESS9 signal to conditionally branch to a
receive cell service routine. For example, a Branch Immediate
Decrement Increment
UTOPIA Cell
Received
Receiver Busy Counter
(Cells in Cell Buffer RAM
awaiting CPU Rx servicing)
Decrement Increment
UTOPIA Cell
Received
Receiver Full Counter
(Cells in Cell Buffer RAM
awaiting DMA transfer)
CPU CPU
Port1
Done
Port2
Done
Control Logic
CPU
RXCLAV ESS3 Rx Attention
ESS9 Rx Busy
to RXENB_
80 Version 4.1 MXT3010 Reference Ma nual
The UTOPIA port
instru ction (“BI Br anch Immedia te” on page 272) can spe cify a
conditional branch to $RECV_CELL if ESS9 is a 1:
BI $RECV_CELL ESS9/1
In addition to the RXBUSY indication on ESS9, a receiver
attent ion out put o f the RXBUSY cou nter d rives ESS3. Thi s sig -
nal indicates that the receive buffer is almost full:
• If ESS3 = 0, the Cell Buffer RAM receive buffer contains
less than 4 cells.
• If ESS3 = 1, the Cell Buf fer RAM receiv e buff er contai ns 4
or more cells.
Decrementing As the CPU services the newly arrived cell, the CPU decrements
the RXBUSY counter. The CPU decrements the RXBUSY
counter using the Counter System Operation feature of the
Branch instructions. For example, a Branch Immediate (BI)
instruction can specify an unconditional branch to $MAIN and
decrement the RXBUSY counter using a counter system opera-
tion option. See “Counter system operation” on page 269.
BI $MAIN DRXBUSY
MXT3010 Reference Manua l Version 4.1 81
Receive cell flow
FIGURE 34.The RXFULL counter
The RXFULL counter
Function The RXFULL counter indicates to the DMA engines and the
CPU that cells are in the Cell Buffer RAM awaiting transfer . The
RXFULL counter also drives the RXENB_ signal to the PHY
devices. The device initialization process:
• Partitions the Cell Buffer RAM.
• Establishes a value for the number of cells that can be
stored in the Cell Buffer RAM receive section.
• Clears the RXFULL counter to zero.
Incrementing As the last byte of a cell is placed into the receive section of the
Cell Buffer RAM by the UTOPIA receiver, it increments the
RXFULL counter.
When the MXT3010 recei ves a cell , it tests the RXCLAV sign al
from the PHY d evice, which si gnals the pre sence of a cell r eady
for transfer . The UTOPIA Port controller tests the availability of
space in the Cell Buffer RAM by examining the count kept by
Decrement Increment
UTOPIA Cell
Received
Receiver Busy Counter
(Cells in Cell Buffer RAM
awaiting CPU Rx servicing)
Decrement Increment
UTOPIA Cell
Received
Receiver Full Counter
(Cells in Cell Buffer RAM
awaiting DMA transfer)
CPU CPU
Port1
Done
Port2
Done
Control Lo gic
CPU
RXCLAV ESS3 Rx Attention
ESS9 Rx Busy
to RXENB_
82 Version 4.1 MXT3010 Reference Ma nual
The UTOPIA port
the RXFULL count er . If t he MXT3010 can accept a cell and th e
PHY has a cell to send, t he UTOPIA port enables t he transfer by
asserting the ATM layer Receiver Enable (RXENB_) output.
Decrementing The Port 1/Po rt 2 DMA controllers can de crement the RXFULL
counter at the completion of a data transfer operation if the
DMA command specifies the UTOPIA post-DMA operative
direct ive (POD) option in a memory write operation. For fu rther
information on POD and other DMA instruction options, see
“The Control instruction field option” on page 287.
Alternatively, the CPU can decrement the RXFULL counter
after the received cell has been processed. As with the RXBUSY
counter, the CPU decrements the RXFULL counter by specify-
ing a Bra nch instr uct i on wi th an opti on. For exa mp le, a Branch
Immediate (BI) ins tructio n can speci fy an uncon ditional branch
to $MAIN and decre ment the RXFULL coun ter using the DRX-
FULL counter system operation option.
BI $MAIN DRXFULL
Whether RXFULL is decremented by use of a Branch instruc-
tion or by use of a DMA instruction, the CPU must decrement
the RXBUSY counter whenever it finishes handling a cell.
Transmit cell flow
The UTO PIA transmitt er transfers cells fro m the Cell Buffer
RAM to an external framing device. All cells to be transmitted
must reside in the Cell Buffer RAM before transmission. As part
of the transmit operation when HEC generation is enabled, the
UTOPIA transmitte r inserts a valid HEC between the last byte
of the ATM Header and the first byte of the SAR-PDU. In 8-bit
mode, only the 8-bit HEC is inserted; in 16-bit mode, the 8-bit
HEC plus an 8-bit stuffer are inserted.
MXT3010 Reference Manua l Version 4.1 83
Transmit cell flow
The UTOPIA port transfers cells from the Cell Buffer RAM
beginning at location 0x0200. The UTOPIA transmitter reads
successive cells from the Cell Buffer RAM. During device ini-
tialization, the programmer can specify how many cells the
UT OPIA transmi tter shoul d use. I f the tra nsmitter buf fer si ze is
set to two cells, the transmitter loops around after the second cell
and begins reading cells again at location 0x0200 in the Cell
Buf fer RAM. For example , if t he trans mitter buff er size i s set to
six cells, the transmitter loops around after the sixth cell and
begins rea d i ng cel ls a gai n a t lo cat ion 0x0200 i n t he Cel l Buffer
RAM.
Each transmit cell buffer is associated with an 16-bit control
word. The transmi t contr ol word is wri tten thr ough a FIFO- like
internal memory mapped into R43. Writes to R43 push control
words onto the control byte FIFO for use when the transmit
operation is executed.
The format of the transmit control word is:
The UT OPIA Control FIFO regist er recircu lates it s output ba ck
to its i nput . For applicat io ns t hat only tr an smit one t ype of cel l,
the 8 locations in R43 c an be loaded at initialization time and
need not be written again.
15 14 13 12 11 10 9876543210
Reserved I CG TXPHY
Bits Name Function
4:0 TXPHY Select the address of the target PHY in a multi-PHY
system
5 CG Generate and insert a CRC10 for this cell
6 I Insert unassigned cell
15:7 Reserved Programs should write a zero to these bits.
84 Version 4.1 MXT3010 Reference Ma nual
The UTOPIA port
UTOPIA transmitter counters
The UT OPI A transmi tt er contai ns t wo count er s, TXBUSY and
TXF ULL, that track cells in the transmit section of the Cell
Buffer RAM. Figure 35 on page 84 and Figure 36 on page 85
show how these counters are used in the transmission process. A
written description follows in “The TXBUSY counter” on
page 84 and in “The TXFULL counter” on page 86.
FIGURE 35.The TXBUSY counter
The TXBUSY counter
Function The CPU uses the TXBUSY counter to inform the UTOPIA
transmitte r that a new cell in the Cell Buffer R AM is ready fo r
transmission. When the TXBUSY counter is non-zero, the
MXT3010 generates the ATM layer Transmit Enable
(TXENB_) output signal that informs the PHY device that the
MXT3010 is ready to send a cell.
Decrement Increment
UTOPIA Cell
Tx begins
Transmitter Full Counter
Decrement Increment
UTOPIA Cell
Tx begins
Transmitter Busy Counter
(Cells in Cell Buffer RAM
loaded by DMA transfer)
CPU CPU
Port1
Done
Port2
Done
Control Logic
CPU
TXCLAV ESS2 Tx Attention
ESS10 Tx Full
to TXENB_
MXT3010 Reference Manua l Version 4.1 85
Transmit cell flow
Incrementing Program execution can be accelerated if the DMA controller
increments the TXBUSY counter after it reads data. This tech-
nique requires the DMA command to specify a memory read
operation with the POD option (see “Post-DMA Operation
Directives (PODs)” on page 109). For example:
DMA1R rsa/rsb, rla[BC/#, CRC{X Y}, POD, ST]
DMA2R rsa/rsb, rla[BC/#, POD, ST]
Alterna ti vel y, the CPU can increment t he TXBUSY counter by
specif ying a Branch i nstructio n with a count er system oper ation
option. For example:
BI $MAIN ITXBUSY
Decrementing As the UTOPIA transmitter processes the first byte of a cell, the
transmitter decrements the TXBUSY counter.
FIGURE 36.The TXFULL counter
Decrement Increment
UTOPIA Cell
Tx begins
Transmitter FullCounter
Decrement Increment
UTOPIA Cell
Tx begins
Transmitter Busy Counter
(Cells in Cell Buffer RAM
loaded by DMA transfer)
CPU CPU
Port1
Done
Port2
Done
Control Logic
CPU
TXCLAV ESS2 Tx Attention
ESS10 Tx Full
to TXENB_
86 Version 4.1 MXT3010 Reference Ma nual
The UTOPIA port
The TXFULL counter
Function The TXFULL counter tracks the number of cells that are avail-
able in the Cell Buffer RAM for transmission. The CPU uses
this counter to determine if space is available in the Cell Buffer
RAM to assemble a cell via DMA transfers.
Signals driven The TXFULL output of the TXFULL counter is connected to
ESS 10.
• If ESS 10 = 0, the Cell Buffer RAM transmit buffer has
space available.
• If ESS 10 = 1, the Cell Buffer RAM transmit buffer queue
is full, and the CPU does not build a cell.
The CPU can use the ESS 10 sig nal to condi tionall y branch to a
transmit cell routine, since available space allows cell building
to begin. For example, a Branch Immediate instruction (“BI
Branch Immediate” on page 272) can specify a conditional
branch to $TRANSMIT_CELL if ESS10 is a 0:
BI $TRANSMIT_CELL ESS10/0
The Tx Attention output of the TXFULL counter is connected to
ESS 2. This signa l indicates that the transmit buf fer is approach -
ing a drained state.
• If ESS 2 = 0, t he Cell Buf fe r RAM transmi t buf f er cont ains
more then 2 cells.
• If ESS 2 = 1, t he Cell Buf fe r RAM transmi t buf f er cont ains
2 or fewer cells.
Incrementing As the CPU begins processing a new cell, the CPU increments
the TXFULL counte r . Now, the CPU can queue the next cel l for
transmission as a background task. The CPU increments the
TXFULL counter by specifying a branch instruction with an
option. For example:
BI $MAIN ITXFULL
MXT3010 Reference Manua l Version 4.1 87
Transmit cell flow
Decrementing As the UT OPIA t ransmi tter proces ses t he las t byte of a cell, the
transmitter decrements the TXFULL counter.
CRC10 generation and che cking support
The UTOPIA port can perform CRC10 generation and checking
in suppor t of AAL3/4, OAM cells, and RM cells. Generation of
CRC10 is controlled on a cell-by-cell basis for transmission.
CRC10 checking is performed on all receive cells.
The UTOPIA transmitter generates and inserts a CRC10 for a
cell i f a 1 was wri tt en in to the CG b it of t he c ont rol byte f or the
cell buffer (see “R43-write UT OPIA Control FIFO regis ter” on
page 205). If CG = 1, the UTOPIA transmitter generates and
insert s a CRC10 fiel d int o the cell. If CG = 0, the CPU does not
insert a CRC10 field into the cell. The CG bit should be set when
queuing an AAL3/4, OAM cell, or RM cell for transmission.
The SWAN processor can determine if a CRC10 error exists for
a receiv ed cell by checki ng the CE bit in the se cond halfword of
the received cell. If CE = 1, a C RC10 error exists in the cell. If
CE = 0, no CRC10 e rror exist s in the cel l. If a ce ll is fr om a con-
nection that does not use a CRC10 fi el d, t he state of CE is i rr el -
evant and should not be checked.
88 Version 4.1 MXT3010 Reference Ma nual
The UTOPIA port
Multi-PHY support
The MXT3010 supports the connection of up to 16 physical
ports t o a single UTOPIA port. The UT OPIA port is compli ant1
with the ATM Forum’s Level 2 specification for Multi-PHY
operations, but can also support Level 1 devices. Bits [15:9] of
the UTOPIA Configuration register (R62) are used to support
multi-PHY operation. The bit assignments are as follows:
1. While the MXT3010 is compliant with the ATM Level 2 specification, it
uses a three-clock polling cycle rather than the two-clock polling cycle
shown in the specification diag rams. In addition, the MXT3010 does not
provide an idle address of 1F between addresses. The three clock polling
cycle redu ces the number of PHY devices that can be pol led during a 52-
clock cell time from 26 to 14. Thus, if 16 PHY devices are used, more than
one cell time is needed to poll them all. Refer to Applica tion Note 20,
“MXT3010EP UT OPIA Le vel 1 and Leve l 2 Interfac e Operation” for further
infomration.
TABLE 15. Bit assignments for multi-PHY operation
Bits Description
13:9 UTOPIA Port Most Significant PHY Address
The UTOPIA Po rt Receiver polls PHY devices searching for an
RXCLAV by increme nt ing the polled address accordin g t o t he
UTOPIA Level 2 specification. The UTOPIA Port Receiver
knows that it has reached the last address and should begin at
zero again when it reaches this address. For examples of the use
of thes e bits, see Figure 37 on page 89 and Figure 38 on
page 90.
15:14 Num ber of Physi cal PHY devices present
This value tells th e UTOPIA Po rt Receiv er th e numb er of p hys i-
cal PHY devices present. This in turn determines the number of
RXCLAV/TXCLAV and RXENB_/TXENB_ signals that should
be used.
00
01
10
11
Reserved
1-PHY mode
2-PHY mode
Reserved
MXT3010 Reference Manua l Version 4.1 89
Multi-PHY support
The use of bits [15: 9] is bes t understood b y consider ing the con -
figura ti ons shown in Figure 37 and Figure 38.
FIGURE 37.Level 2 PHY configurations
The two implementa tions sh own ar e logic all y e qui valent Le vel
2 configurations. Since there is only one logical PHY, bits
[15:14] sh oul d be 01 t o s el ect 1 -PHY mod e. Since the most sig-
nificant PHY address is 15, bits [13:9] should be 1111.
MXT3010 16-port
device 15
0
.
.
.
MXT3010 4-port
device 3
0
4-port
device 7
4
4-port
device 11
8
4-port
device 15
12
TXCTRL[3:1]
TXCTRL[3:1]
Address control (i.e. which device
is 0-3, which is 4-7, etc.) provided
by host or other external device
Note: While only transmit control
signals (TX) signals are shown, a
corresponding set of receive (RX)
signals is also used.
90 Version 4.1 MXT3010 Reference Ma nual
The UTOPIA port
FIGURE 38.Mixed Level 1 and Level 2 PHY configuration
Notes:1.While only transmit control signals (TX) are shown, a corre-
sponding set of receive (RX) signals is also used.
2. In this configuration, the Level 1 device must tri-state the
RXDATA/RXSOC lead s when its RXENB_ pin is de-asserted .
The implementation shown has two logical PHYs. In this con-
figuration, TX/RXCTRL[3] is used as TX/RXCLAV for the sec -
ond PHY, an d TX/RXCTRL[ 2] is use d as TX/RXENB_ f or the
second PHY. Since there are two logical PHYs, bits [15:14]
should be 10 to select 2-PHY mode. Since the most significant
PHY address is 7, bits [13:9] should be 0111.
Mode TX/RX CLAV TX/RX ENB ADRS
1 PHY TX/RX_CLAV TX/RX_ENB_ TX/RX CTRL [3:0]
2 PHY
PHY 0 TX/RX_CLAV TX/RX_ENB_ TX/RX CTRL [1:0]
PHY 1 TX/RX CTRL [3] TX/RX CTRL [2] TX/RX CTRL [1:0]
MXT3010
Level 1
device 3
0
Level 2
device 7
4
TXCTRL[1:0]
TXCLAV
TXENAB_
TXCTRL[3]/TXCLAV[1]
TXCTRL[2]/TXENAB[1]
MXT3010 Reference Manua l Version 4.1 91
Receive Header Reduction hardware
Receive Header Reduction hardware
The MXT3010 provides receive header reduction via bits [6:0]
of the System register (R63). The results of this reduction can be
used as a Channel ID. The bit definitions are as follows:
TABLE 16. Receive Header Reduction control
Bits Name Function
6:0 VPI/VCI Utopia Receiver Reduction Mask
Setting Value written into ATM Header lower
halfword in CBR
0000 001
0000 011
0000 111
0001111
{0,0,0,0,0,0, vpi(0), vci(7:0), clp}
{0,0,0,0,0, vpi(1:0), vci(7:0), clp}
{0,0,0,0, vpi(2:0), vc i(7:0 ), clp}
{0,0, 0, vp i(3:0), vci(7 : 0 ), clp }
0000 010
0000 110
0001110
0011110
{0,0,0,0,0, vpi(0), vci(8:0), clp}
{0,0,0,0, vpi(1:0), vc i(8:0 ), clp}
{0,0, 0, vp i(2:0), vci(8 : 0 ), clp }
{0,0, vpi(3:0), vci(8:0), clp}
0000 100
0001100
0011100
0111100
{0,0,0,0, vpi(0), vci(9:0), clp}
{0,0, 0, vp i(1:0), vci(9 : 0 ), clp }
{0,0, vpi(2:0), vci(9:0), clp}
{0, vpi(3:0), vci(9:0), clp}
0001000
0011000
0111000
1111000
{0,0,0, vpi(0), vci(10:0), clp}
{0,0, vpi(1:0), vci(10:0), clp}
{0, vpi(2:0), vci(10:0) , clp}
{vpi (3:0), vci(10: 0), clp}
0010000
0110000
1110000
{0,0,vpi(0), vci(11: 0), clp}
{0,vpi(1:0), vci(11:0), clp}
{vpi(2:0), vci(11:0), clp}
0100000
110000 0 {0,vpi(0), vci(12:0), clp}
{vpi (1:0), vci(12: 0), clp}
1000 000 {vpi(0), vci(13:0), clp}
0000000 {vci(14:0), clp}
92 Version 4.1 MXT3010 Reference Ma nual
The UTOPIA port
Receive header reduction mode is enabled by bit 0 of the
UTOPIA Configuration register (R62).
TABLE 17. Receive Header Reduction enable bit
Bits Description
0 UTOPIA Receiver Redu ction Mode Enable Bit
0
1
Reductio n Function Disable d (ATM Header bytes [2:3] writte n
into the Cell Buffer RAM unchanged)
Reduction Function Enabled (ATM header bytes [2:3] written
into the Cell Buffer RAM after reduction function performed
according to Reduction Mask Setting selected by R63[6:0]).
MXT3010 Reference Manua l Version 4.1 93
UTOPIA port configuration summary
UTOPIA port configuration summary
UTOPIA configuration information is stored in the UTOPIA
Configuration register, R62. The SWAN processor passes this
information to the UTOPIA Por t at system initialization. Two
bits ( 0,1) in th e ESS regis ter (R42) are als o used in t he progra m-
ming of the UTOPIA port. Descriptions of these bits appear in
the tables referenced in Table 18. For a co mplete listing and
description of all of the bits in these registers, see “R42-read
External St ate Signals (ESS) register” on page 200 and “R62
The UTOPIA Configuration register” on page 219.
TABLE 18. UTOPIA configuration information
Bits Function Reference
R42 [0] HEC control Tabl e 13 on page 72
R42 [1 ] Cell length control Table 13 on page 72
R62 [0] UTOPIA Receiver Reduction mode
enable bit Table 17 on page 92
R62 [3:1] Receive Cell Buffer size in the Cell
Buffer RAM (000 = Receiver Reset) Table 9 on page 60
R62 [6:4] Transmit Cell Buffer size in the Cell
Buffer RAM (000 = Transmitter Reset) Table 9 on page 60
R62 [7] UTOPIA Port operational / output
cloc k fr e quenc y se le c tion Table 14 on page 73
R62 [8] UTO PI A Port dat a bu s wid t h Table 11 on page 71
R62 [13:9] UTOPI A Port most significant PHY
address Table 15 on page 88
R62 [15:14] Number of physical PHY devices
present Table 15 on pa ge 8 8
R63 [6:0] Receiver Header Reduc ti on control Table 16 on page 91
94 Version 4.1 MXT3010 Reference Ma nual
The UTOPIA port
UTOPIA port sequence diagr ams
This section shows sequence diagrams for the following
UTOPIA Port operations:
• Receive timing for single PHY, 8-bit mode (Figure 39 on
page 94)
• Transmit timing for single PHY, 8-bit mode (Figure 40 on
page 95)
• Receive full timing for single PHY, 8-bit mode (Figure 41
on page 95)
• Transmit full timing for single PHY, 8- bit mode (Figure 4 2
on page 95)
Set-up times, propagation times, and other timing information
for the UTOPIA Port interface are provided in “Timing” on
page 343.
FIGURE 39.UTOPIA Port receive timing - single PHY, 8-bit mode
Notes for Figure 39, Figure 40, Figure 41, Figure 42:
1. RXSOC must not be asserted outside the scope of a valid cell. That
is, it can only be asserted while RXENB_ is asserted (low).
2. RX CLAV/TXCLAV must be stable during octets 45 throug h 48.
RXCLK
RXSOC
RXDATA[7:0]
RXENB_
H1
RxPeriod
P48
H2 P47 P48 H1 H2
RXCLAV
Note 1
Note 2
MXT3010 Reference Manua l Version 4.1 95
UTOPIA port sequence diagrams
FIGURE 40.UTOPIA Port transmit timing - single PHY, 8-bit mode
FIGURE 41.UTOPIA Port receive full timing - single PHY, 8-bit mode
FIGURE 42.UTOPIA Port transmit full timing - single PHY, 8-bit mode
TXCLK
TXSOC
TXDATA[7:0]
TXENB_
H1
TxPeriod
P48
H2 P47 P48 H1 H2
TXCLAV
Note 1
Note 2
RXCLK
RXSOC
RXDATA[7:0]
RXENB_
H1
RxPeriod
H2
P47 P48
RXCLAV
H3 H4 HEC
Note 1
Note 2
TXCLK
TXSOC
TXDATA[7:0]
TXENB_
H1
TxPeriod
H2
P47 P48
TXCLAV
H3 H4 HEC
Note 1
Note 2
96 Version 4.1 MXT3010 Reference Ma nual
The UTOPIA port
MXT3010 Reference Manua l Version 4. 1 97
CHAPTER 7 The Port1 and Port2 Interfaces
Port1 and Port2 are high-spe ed interf ace port s. For each port, thi s
chapter includes:
Multi-purpose
DMA (Port2)
UTOPIA
Port
Cell Buffer RAM High
Performance
DMA (Port1)
Instruction Cache
Processor
Fast Memory
Controller
Cell Scheduling
System
Inter-chip
Signalling
Fast Memory
Instructions &
Data S tructures
Main Memory
Msg Buffers
& Other
Information
Host
PHY or
Switch
Fabric
Application
Specific
Devices
Mem Controller
DRAM
SRAM
• Port interface overview • Control signals
• Port operations • Burst and non-burst operations
• Port DMA controllers • Data flow to Cell Buffer RAM
98 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
Port interface overview
Both Port1 and Port2 provide high speed transfer paths to and
from the MXT3010 Cell Buffer RAM. The characteristics of the
two ports differ, however, and are shown in Table 19.
SWAN processor
memory access The SWAN processor does not access Port1 or Port2 address
space directly. The processor programs the Port DMA Control-
lers to perform a DMA read or write operation to move the data
between the Cell Buffer RAM and Port1/Port2 address space.
The SWAN proces sor initiates all port o perations. It initiates a
port transfer by executing a DMA instruction that writes a DMA
command into the port’s command queue.
DMA commands A typical DMA command format is shown below:
DMA1R rsa/rsb rla [BC/#] [CRCX|CRCY] [POD] [ST]
A single DMA command can transfer of up to 255 bytes of
information. The DMA command specifies:
TABLE 19. Characteristics of Port1 and Port2
Port1 Port2
Supports only burst mode opera-
tions. Suppor t s bo th bu r st an d non -burst
mode operations.
Provides a 32-bit, multiplexed
address an d data bus. Provides a 16-bit, mu ltiplexed addre ss
and d a ta bus
Provides access for COMMIN
and COMMOUT register I/O
transfers.
Provi des a mechanism for me mory-
mapp ed I/O via non- burst mod e . This
can be used to access the program-
ming interface of a PHY device or a
CAM.
Provides CRC-32 generation
and che cking.
MXT3010 Reference Manua l Version 4.1 99
Port interface overview
• The transfer’s starting address in memory (from registers
rsa and rsb)
• The transfer’s starting address in the Cell Buffer RAM
(from register rla)
• The size of the transfer (from BC/#, or if no BC/# value is
specified, from the Alternate Byte Count/ID register, R52)
• The direction of the transfer (Read or Write) (from the
choice of DMA1R or DMA1W, for example)
• A series of instruction field options (IFOs) that control cer-
tain aspects of the transfer (BC/#, CRCX|CRCY, ST, POD)
For more in formation about the DMA commands , see page 283.
Instruction field
options supported
with the DMA
instruction
The Port1 instruction field options supported within the DMA
instruction include Byte Count (BC/#), Cyclical Redundancy
Check (CRCX or CRCY), Silent Tr ansfer (ST), and Post -DMA
Operation Directive (POD). If no BC/# is specified in the com-
mand line, the command executes using a subset of the options
(BC/#, CRX/CRY) from the Alternate Byte Count/ID register,
R52.
The Port2 instruction field options supported within the DMA
instruction include Byte Count (BC/#) and Post-DMA Opera-
tion D irective (POD). If no BC/# is specified in the command
line, the command executes using the byte count (BC/#) field
from the Alterna te Byte Count/ID register, R52.
Detailed descriptions for instruction field options supported
with Port1 and Po rt2 DMA instructions app ear in the sections
cited in the following table.
IFO For Further Information, See
BC “The Byte Count inst r uc tio n f ie ld option (BC ) ” on page 286
CRCX,
CRCY “CRC partial result registers and the CRCX/CRCY instruction
field option” on page 103 (Port1 only)
ST “Silent transfers” on page 105
POD “Post-DMA Operation Directives (PODs)” on page 109
100 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
The Port DMA command queues
The Port1 and Port 2 DMA Controlle rs eac h conta in a two-dee p
command queue. The MXT3010 processor contains an addi-
tional single-entry command queue for each Port1 and Port2
interface. With these queues, software can have up to three
DMA Controller commands outstanding to each port simulta-
neously.
Port1 and Port2 DMA command queues
The Port1 and Port2 command queues each have two stages
referred to as the queue stage and the active stage. Figure 43
shows the DMA command queues for the MXT3010.
FIGURE 43.DMA command q ueu es for the MXT3010 E P
Port2 Active
Stage
Port1 Active
Stage
Port2 Command
Queue Stage
Port1 Command
Queue Stage
MXT3010 Processor
P1RQ_
P2QRQ_
P1QRQ_
P2RQ_
Port1 Port2
Processor Com mand
Queue Processor Command
Queue
MXT3010 Reference Manua l Version 4.1 101
The Port DMA command queues
The DMA command information generated by a DMA read or
write instr uction is written into the sele cted SWAN comm and
queue. The command is transferred into the associated DMA
control ler’s command queue a s soon as the queue is ava ilable. If
the DMA controller’s active stage is not busy, the DMA com-
mand is transferred from the command queue stage to the active
stage and a port bus DMA operation begins.
If, however, the DMA active stage is busy, the operation remains
in either the SWAN or port DMA Controller queue stage until
the active operation completes. One cycle after the active oper-
ation completes, the DMA command queue operation is trans-
ferred into the active st age, and a n ew operation begins. If a port
DMA Controller command is issued while the SWAN command
queue is full, the processor stalls until the active operation fin-
ishes.
Bus pa rking The QRQ_ output signal is asserted whenever a command is
present a port’ s DMA queue. An exter nal arbiter can use this sig-
nal to all ow the MXT3 010 to maint ain owner ship of a bus until
all co mmands are d rained from bot h the acti ve and queue s tages
of the port DMA Controller. The arbiter does this by not
responding to requests from other devices as long as there is a
QRQ_ asserti on on th e port cur re ntl y bei ng se rvi ce d . Allo wing
the MXT3010 to maintain bus ownership in this fashion is
referred to as “bus parking”. See “Port2 bus parking” on
page 158.
Testing DMA Controller queues with the ESS bits
Software can monitor the status of the DMA Controller com-
mand queues by tes ti ng Extern al St at e Signals (ESS) 13 an d 11
for Port1 and ESS12 and 14 for Port2. Table 20 and Table 21
show how ESS stat us bi ts are used t o in dicate DMA Controlle r
status.
102 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
Branch instructions can be used to control program flow based
on the status of these bits. For more information, see “Branch
Instructions” on page 261.
TABLE 20. ESS Bits for DMA Controller status
ESS bit State Functio n
11 0 Port1 DMA Controller queue stage and active stage empty
1 Port1 DMA Controll er queue stage or ac tive stage busy
12 0 Port2 DMA Controller queue stag e and active stage empty
1 Port2 DMA Controll er queue stage or ac tive stage busy
13 0 Port1 DMA Controller queue stag e empty
1 Port1 DMA Controller queue stage busy
14 0 Port2 DMA Controller queue stag e empty
1 Port2 DMA Controller queue stage busy
TABLE 21. Example of DMA Controller status bit utilization
ESS 13 & 11 Port1 queue status
00 Controller queue stage and active stage empty
01 Controller queue stage empty; acti ve stage busy
10 Invalid combination
11 Controll er queue stage busy; active stage busy
MXT3010 Reference Manua l Version 4.1 103
Port Controller features
Port Controller features
The Cyclical Redundancy Check 32 generator for
Port1
A CRC32 generator is provided in the Port1 DMA Controller to
generate and to check AAL5 CRC32 polynomials during seg-
mentation and reassembly operations. The CRC32 ci rcuit gener-
ates a CRC32 for a Convergence Sublayer (CS) Protocol Data
Unit (PDU) as it is transferred between the host memory and the
Cell Buffer RAM. The CRC32 generator operates on data 16-
bits at a time.
CRC partial resul t
registers and the
CRCX/CRCY
instruction field
option
To support pipelined DMA operations, the MXT3010 imple-
ments two CRC32 partial result registers, CRC32PRX (R44,
R45), and CRC32PRY (R46, R47). Each DMA instruction spec -
ifies, via an instruction field option (IFO), whether a CRC32 cal-
culati on occurs and if so , which of t he two CRC32 pa rtial r esult
registers to use. Specification of the CRCX/CRCY IFO is sum-
marized in Table 22.
Using partial
result registers To generate CRC32, a program must ini tialize the CRC32 logi c
with any prior pa rtial r esult befor e the DMA data transfer
begins. For th e first cell of a CS-PDU, initialize the selected par-
tial result register to 0xFFFFFFFF. At the completion of the
TABLE 22. Specification of the CRCX/CRCY instruction field option
IFO Action
none CRC32 partial result registers are not modified
CRCX A CRC32 partial result is generated based on the CRC32PRX
register’s value and the result is deposited into CRC32PRX
(R44/R45).
CRCY A CRC32 partial result is generated based on the CRC32PRY
register’s value and the result is deposited into CRC32PRY
(R46/R47).
104 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
DMA transfer, read the CRC32 partial result from the selected
partial result register and save those results in the Channel
Descriptor to use the next time that a cell arrives. On transmits,
for the last cell of an AAL5 CS-PDU, invert the partial result
before pl acing it int o the last four byt es of the cell . On receives,
the program can test for a CRC32 error by testing the appropri-
ate CRC32 error bit in the Sparse Event Register (R57) when the
final DMA transfer operation finishes.
Pipelined
operation Although the use of command queueing and pipelined DMA
operations requires that care be taken with CRC32 partial gen-
eration, these operations greatly enhance system performance.
Using dual part ial re sult reg isters, fi rmware can kee p the DMA
command queu e full by managing th e CRC32 partia l resul t reg-
ister s and the CRC32 X/CRC32Y instr uction fiel d option b its of
the DMA command.
Cyclical Redu nd ancy Check operation acc eleration
The registers for the Cyclical Redundancy Check (CRC) and the
MXT3010 instruction Store Register Halfword (SRH) acceler-
ate the h andl ing of CRC resul t s dur ing AAL5 pack et segmen ta -
tion or reassembly. Direct Memory Access operations function
independently of MXT3010 code execution once they have been
started. Because of this functional independence, firmware can
process the next channel descriptor in parallel with the DMA
transfer (and CRC accumulation) of the previous channel as
soon as the DMA operation has been committed for that previ-
ous channel. This parallelism provides processing time to the
SWAN that might otherwise be wasted waiting for the transfer
to complete. However , the program must still save the results of
the part ial CRC accum ulation at the c onclusion of a DMA trans-
fer in the previously serviced Channel Descriptor.
MXT3010 Reference Manua l Version 4.1 105
Port Controller features
CRCX and CRCY
address holding
registers
At the time that a DMA read or write operation with CRCX or
CRCY indicated is initiated to Port1, the MXT3010 automati-
cally stores the address contained in the internal Fast Memory
Link Address register into one of two temporary holding regis-
ters – either that for CRCX operations or that for CRCY opera-
tions. Typically, the address stored is the current Channel
Descriptor address.
Upon completion of the DMA transfer, the SWAN instruction,
SRH, writes the contents of the CRC partial result registers
(R44/ R45 o r R4 6/ R4 7) to Fast Memor y us ing the addre ss con -
tained in either the CRCX holding register or the CRCY holding
register as the base address for the transfer. The programmer
must specify an offset with the SRH instruction to place the par-
tial results at the appropriate field within the Channel Descrip-
tor.
Silent transfers
On some occ asions , it is de sira ble to pe rform CRC cal culatio ns
on data that did not traverse Port1.
• For LAN emulatio n pur pose s, th e MXT30 10 pro gram may
need to add a header to a message from Port1 memory
before trans mitting the messa ge.
• In AAL5, the MXT3010 program may nee d t o ad d a trai ler
to a m essage from Port1 memo ry befor e transmitti ng the
message.
The MXT3010 provides this capability via the silent transfer
instruction field option. When a Port1 DMA instruction is issued
with the silent transfer (ST) option specified in the command
line, data is trans ferred into the Port1 CRC logic, and the CRCX
or CRCY partial result is updated, as selected by the CRCX/
CRCY instruction field option. During a silent transfer, the
Port1 state machine operates with the same timing as an ordi-
106 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
nary Port1 DMA transfer (see Figure 45 on page 119), but no
P1QRQ_ or P1RQ_ signals are generated, the external arbiter
does not manipulate P1ASEL_ or P1TRDY_, and data is not
transferred on the Port1 bus.
Example 1 of
silent transfer use Transmission of a typical AAL5 end of message cell typically
involve s at lea st thre e DMA instr uctions, represent ed by th e fol-
lowing pseudocode:
DMA1R, 40 bytes, CRCX ; This moves 40 bytes of data into the Cell
; Buffer RAM in preparation for transmission.
; A CRC is accumulated on this data.
DMA1W, 4 bytes, CRCX, ST; This instruction uses an rla value that points
; to the UU, CPI, and length bytes at byte 40.
; This instruction incorporates previously
; written UU, CPI, and length information
; into the CRC without modifyi ng the contents
; of the Cell Buffer RAM.
DMA1R, CRCX, ST, POD ; This instruction complements the CRC and
; writes the result to the location specified in
; rla (typically byte 44 of the cell). The POD
; option increments TXBUSY, informing the
; UTOPIA transmitter that a new cell in the
; Cell Buffer RAM is ready for transmission.
;(See “The TXBUSY counter” on page 84 .)
Example 2 of
silent transfer use It is occasionally useful to provide a silent transfer without CRC
so that the queue state can be predicted. It may be desirable
under some circumstances to fill the SWAN processor’s DMA
command queue and intentionally stall the processor . If the com-
mand queue is full, a processor stall can be achieved by intro-
ducing an additional DMA request. In this case, since a stall is
desired rather than a real DMA action, a zero byte silent transfer
should be specified, as such a request reaches the command
queue, but does not reach the designated port queue.
MXT3010 Reference Manua l Version 4.1 107
Port Controller features
Post-increment option on rla operations
The target rla register ca n automatically increm ent wh en the
DMA transfer is completed with the DMA Plus instruction. The
increment is 64 modulo 512. If eight 64-byte Cell Buffer regis-
ters a re used, th is saves t he SWAN proce ssor the co de needed to
advance the rla register to the next cell buffer in Cell Buffer
RAM following each DMA transfer.
DMA Plus
instructions Two steps are necessary to utilize the rla increment option:
1. To enable the rla increment option, set mode bit 5 in the
Configur ati on Regi st er (R42) .
2. Create a DMA Plus instructio n by adding a plus sign to any
DMA instruction for which the rla increment option is
desired. The DMA Plus instructions are DMA1R+,
DMA1W+, DMA2R+, and DMA2W+.
If the rla increment mode is not enabled, do not use the DMA
Plus instructions. For more information on the DMA Plus
instructions, see “The RLA increment bit (i-bit)” on page 285.
Data alignment
The port DMA Controller operates on halfword-aligned data
located locally, such as in the Cell Buffer RAM, and in host
memory. On memory reads and writes, the local halfword
address is spe cified in the chosen local address re gister , rla. The
DMA controller programs the external halfword address into the
DMA instruction. The DMA controller performs data alignment
dynamically in those cases where the starting address of the
source and destination locations are not halfword aligned.
108 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
Byte manipulations on Port1
The Port1 bus supports only word and halfword DMA writes,
with P1HWE [1:0] being used as selects for the half-words.
However, the P1 address leads (P1AD [31:0]) provide a byte
address, and the P1 bus supports byte DMA reads. The DMA
read oper ations can tr ansfer even or odd byt e counts and sta rt or
end transfers on even or odd boundaries in system memory or in
Cell Buffer RAM.
Transfers that end on odd byte boundaries in the Cell Buffer
RAM result in the single byt e of the last half word address bei ng
stored as id e in antici pat io n of the next tr ans fe r. This byt e is not
accumulated in CRC calculations until the subsequent transfer is
initiated. Multiple trans fers must be certain to end with a hal f-
word-aligned boundary to properly complete the CRC calcula-
tion. Therefore, the beginning and ending of any multi-burst cell
accumulation process must occur on even byte boundaries. New
CRC accumulati ons that do not begin on an odd byte add ress in
Fast Memory might include some arbitrary stale byte in the
transfer.
T able 23 shows the valid and invalid transfers to use for the first,
mid-cell, and last transfer for any given cell during cell con-
struction from system memory. Follow the rules in Table 23 to
ensure that the cell accumulation begins and ends on proper
boundaries.
TABLE 23. Valid and invalid first, mid-cell, and last transfers.
rla Start Byte Use of this start address and byte count is valid for:
Address Count First Transfer Mid-Cell T ransfer L ast Transfer
Even Even Yes Yes Yes
Even Odd Yes Yes Noa
a. Causes cell to end on odd boundary
Odd Even Nob
b. Causes cell to start on odd boundary
Yes Noa
Odd Odd NobYes Yes
MXT3010 Reference Manua l Version 4.1 109
Burst an d no n- b ur s t op er ation ( Por t2 )
Post-DMA Operation Directives (PODs)
The port DMA Con tro l ler s sup por t a fea ture re fe rr ed to as Post-
DMA Operation Directives, or PODs. PODs instruct the DMA
controller to perform UTOPIA port counter manipulations when
the operation ends. For instance, during reassembly, firmware
can instruct the DMA controller to decrement the RXFULL
counter by specifying the POD instruction field option in the
DMA1W command.
When a POD is specified with a DMA write operation, the DMA
controller decrements the UTOPIA port’s RXFULL counter.
(See “UTOPIA receiver counters” on page 78.) The RXFULL
counter is used for UTOPIA RxENB_ assertion at the conclu-
sion of the DMA operation. The CPU is finished with a received
cell once the DMA command requir ed to transfer the cell's SAR
SDU to memory is written into the DMA queue. CRC32 partial
results might still need handling.
If the POD directive is specified with a DMA read operation, the
DMA controller increments the TXBUSY counter when the
DMA o peration fin ishes. (See “UTOPIA tran smitte r count ers”
on page 84.) The CPU is fini shed with a tran smit cell once it i ni-
tiates the data transfer from memory . The CPU must be sure that
the appropriate command byte, ATM headers, and AAL Head-
ers/Trailers (if any) are written into the cell holder before the
data transfer completes.
Burst and non-burst operation (Port2)
A burst mode transfer includes an address cycle and one or more
data cycles. Burst mode is used with high-speed synchronous
transfer devices such as SRAMs. In contrast, a non-burst trans-
fer in cludes an add ress cycle a nd a single data cycle th at models
110 Version 4.1 MXT3010 Reference Manual
The Port1 and Port2 Interfaces
transf ers on a typi cal a synchr onous mul tiplexe d bus. Non- burst
mode is used with low- speed no n-sync hronous trans fer dev ices
such as PHYs, CAMs, and FLASH memories.
While Port1 supports only burst mode operations, Port2 sup-
ports both burst mode and non-burst mode operations. Port2
burst mode DMA operations proceed similarly to Port1 DMA
burst operations. During non-burst transfers, the Port2 DMA
control ler can insert a programmable numbe r of wait st ates and
can also gen erate cont rol signal s that allow dire ct connecti on to
external devices.
Selection of burst mode or non-burst mode operation is accom-
plished vi a t h e Por t2 bas ic pr otocol. Se e “ P ort 2 b asi c protoc ol”
on page 137.
Port Operations
Port1 basic protoco l
The Port1 DMA interface supports two transfer mechanisms:
DMA burst-mode t ransfer s init iate d by the MXT3010 and com-
munication register I/O transf ers initiated by an external device.
For information on DMA burst-mode transfers, see “Burst and
non-burst operation (Port2)” on page 109. For information on
communication register transfers, see “Communications” on
page 177.
Figure 44 and Table 24 illustrate the correspondence between
rsa/rsb register values and the Port1 bus signals for Port1 DMA
transfers.
MXT3010 Reference Manua l Version 4.1 111
Port Operations
FIGURE 44.Diagram of Port1 DMA instruction bits
Port1 control signals
Ta ble 25 describes the signals that control Port1 transfers. Two
additional status signals, CIN_BUSY and COUT_RDY, allow
both an external device and the SWAN processor to determine
the state of the COMMIN/COMMOUT register set.
Restrictions on Port1 Addressing
The address counter for Port1 does not increment across the
boundary between P1AD[15] (rsb[15]) and P1AD[16] (rsa
[00]). Therefore, firmware running on the MXT3010 must
ensure that DMA transfer s to/from Port1 do not cross 64K
boundaries.
15 14 13 12 11 10 9876543 2 1 0
rsa P1AD[31:16]
15 14 13 12 11 10 9876543210
rsb P1AD[15:0]
TABLE 24. Port 1 DMA instruction bit mapping
Reg Bits Function Port2 Bus
rsa 15:0 Address P1AD[31:16]
rsb 15:0 Address P1AD[15:0]
112 Version 4.1 MXT3010 Reference Manual
The Port1 and Port2 Interfaces
TABLE 25. Signals to control Port1 transfers
Signal Purpose
P1QRQ_ When the Port1 state machine detects the pres ence of a command in the queue stage
of the Port1 DMA command queue, the state machine asserts this signal to an external
device. Th is provides an advance indic ation that P1RQ_ will soon be asserted.
P1RQ_ When the Po rt1 state machine is in the Idle state and detects the presence of a com-
mand in the active stage of the Port1 DMA command queue, the state machine asserts
this signal to an exte rn al device. The external de vice responds by manipulati ng
P1ASEL_ and P1TRDY_ to control a DMA transfer.
P1ASEL_ This signal is an input to the MXT3010 and is driven by an external device. The
external device uses thi s signal to select between address and data cycles. The exter-
nal devi ce can also use this sig nal in conjun ction with P1TRDY_ to desele ct (tri-state)
the Port1 DMA engine.
P1TRDY_ This signal is an input to the MXT3010 and is driven by an external device. The
external device uses thi s signal to insert wait states. The external device can al so use
this signal in with P1ASEL_ to deselect (tri-state) the Port1 DMA engine.
P1RD During a DMA transfer, this signal is an output driven by the MXT3010. During a
communica tio n registe r transfer, this signal is an inp u t to th e MXT3010 and is driv en
by an external device. In either use, this signal indicates whether the transfer is a read
(1) or a write (0) transfer.
P1END_ This signal in dicates the last cycl e of a DMA operation.
P1AD[31:0] This is a multiplexed, bi-directional 32-bit bus. Data is read into and out of the
MXT3010 during DMA transfers and du r ing communication register I/O transfers.
P1AD [31] is the most significant bit, and P1AD[0] is the least significant bit.
P1HWE[1:0] During data cycles, P1HWE[1] and P1H WE[ 0] act as Half Word Enabl es. If
P1HWE[1] is asserted, P1AD[15:0] should contain valid data. If P1HWE[0] is
asserted, P1AD[31:16] sho uld contain valid data.
P1IRDY_ During DMA write data cycles, the MXT301 0 asserts P1IRDY while it is sourcing
valid data on P1AD[31:0]. During DMA read data operations, the MXT3010 asserts
P1IRDY_ if it is able to sample P1AD[31:0] on the next rising edge of clock.
COMMSEL This signal is an input to the MXT3010 and is driven by an external device. The
external device uses thi s signal to perform communication register I/O.
P1ABORT_ This input signal causes the termination of the data transfer at the completion of the
next da ta ph a se. I t is use d on ly by th e P1 DMA en gin e , an d th e SWAN process or ha s
no knowledge of P1ABORT_ signal indications.
CIN_Busy Driven high when host writes COMMIN; cleared when MXT3010 reads COMMIN.
COUT_Ready Driven high when MXT3010 writes COMMOUT; cleared when host reads COM-
MOUT.
LTN This is an intern al signal indi catin g tha t the Last Transfer will occur Next (LTN).
MXT3010 Reference Manua l Version 4.1 113
Port Operations
The Port1 control state machine
General information concerning DMA transfers
As indicated in “The Port DMA command queues” on page 100,
the MXT3010EP asserts a port’s RQ_ signal if that port has a
DMA command active. Additionally, it asserts the associated
QRQ_ signal if there is an additiona l DMA command enqueued
behind the active command. The port’s RD signal indicates
whether the requested DMA transfer is to be a read or a write.
Arbitration logic external to the MXT3010EP monitors these
signals and, in the case of a share d bus, other requesto rs to deter-
mine whether to start a DMA transfer. Upon deciding to start a
transfer, the external logic steps ASEL_ and TRDY_ through the
various st ates of a DM A tr ansfer, conclud ing wi th a Last Trans -
fer during which the MXT3010EP dismisses the current RQ_
request, and during which the arbitration logic again determines
subseque nt bus util iz ation. The MXT301 0EP re -a sserts RQ_ a t
the conclusion o f the “Clean U p” state (which follows Last
Transfer) if a queued command exists at that time.
Port1 DMA read
transfers T able 26 shows the state table for Port1 DMA read transfers, and
Figure 45 shows a sequence diagram for a DMA read transfer.
The table and the figur e ar e bes t unde rs tood by considering the
functi on of th e variou s inputs , outp uts, and stat es for rea d trans -
fers.
Inputs
• ASEL_ and TRDY_
These inputs are manipula ted by an external device to step
the state machine thro ugh various states .
•LTN
This input (Last Transfer Next) is an internal MXT3010EP
signal based on the byte count. When asserted, it indicates
that the next DMA transfer state will be the last.
114 Version 4.1 MXT3010 Reference Manual
The Port1 and Port2 Interfaces
Outputs
•P1AD
This is a bi- directi onal add ress/ data bus . It has fou r possib le
states: Out-Address, In-Data, In-X (Don’t Care), and Tri-
state.
• IRDY_
When this output is asserted, the MXT3010EP will sample
data on the rising edge of clock. Thus, in Table 26, IRDY_
is asserted only when P1AD is presenting In-Data.
• END_
The END_ output is asserted b y the MXT3010EP duri ng the
Last Transfer state.
Although not shown in Table 26, the state machine also has a
COMMSEL input. Dur ing DMA tr ans fe rs, t he COMMSE L s ig-
nal is low for all states shown. Please see“Communication reg-
ister I/O transfers” on page 133 for COMMSEL high.
States
• Address 1, Automatic-turnaround, and Address 2
The state machine differentiates between two types of
Address state, Address 1 and Address 2.
-When a DMA transfer begins, and the MXT3010EP
sample s both ASEL_ a nd TRDY_ as assert ed (lo w), the
MXT3010EP drives address info rmation onto the P1AD
bus; this is referred to as an Address 1 state.
-At some point after the Address 1 state begins, the
external controller that drives the ASEL_ and TRDY_
leads will de-assert ASEL_ (high) while maintaining
TRDY_ in the asserted state (low). This step prepares
the MXT3010EP for data transfer. When the
MXT3010EP is thus switched, it will interject an
Automatic-turnaround state during which it will not
MXT3010 Reference Manua l Version 4.1 115
Port Operations
accept data (IRDY_ will be de-asserted (high)). The
Automatic-turnaround state provides time for the
MXT3010EP to turn off its bus drivers and for the
external device to turn on its bus drivers.
-If the system using the MXT3010EP requires that
address cycles be inserted during a DMA transfer at
some point after data reads have begun, i.e. after the
automatic -turnaround state, these are referred to as
Addre ss 2 states. Address 2 states differ from Address 1
states, as Address 2 states require that the external
controller manipulate ASEL_ and TRDY_
appropriately to insert Tri-state intervals between the
Address 2 states and any data read states to allow time
for the bus direction to be changed.
• Data Read
During a Data Read, an external device drives data onto the
P1AD bus and the MXT3010EP reads that data. Thus, the
P1AD column in the state table shows In-Data, and the
IRDY_ column shows assertion (low) indicating that the
MXT3010EP will read the data. There are three common
cases for what happens after a Data Read:
-If ASEL_ remains de-asserted (high) and TRDY_
remains asserted (low), the Data Read is followed by
another Data Read.
-If ASEL_ remains de-asserted (high) and TRDY_ is de-
asserted (high), the Data Read is followed by a Data
Wait.
-If ASEL_ remains de-asserted (high) and TRDY_
remains asserted (low), and LTN is asserted (high), the
Data Read is followed by a Last Transfer.
There are two other cases for what happens after a Data
Read, but these are used less often than the three listed
above.
-If the states of ASEL_ and TRDY_ are switched to
ASEL_ asserted (low) and TRDY_ de-asserted (high),
the D ata Rea d is followed b y Tri-state (Da ta)1 and all
outputs are tri-stated.
116 Version 4.1 MXT3010 Reference Manual
The Port1 and Port2 Interfaces
-If ASEL_ is asserted (low) and TRDY_ remains
asserte d (low), th e Data Read is followed by an Address
cycle. To avoid bus contention when inserting an
Address cycle, it is preferable that ASEL_ /TRDY_ be
low/high such that the Data Read is followed by a Tri-
state (Data) (see previous paragraph), and that the Tri-
state (Data) then be followed by an Address 2 state
(ASEL_/TRDY_ both low).
• Data Wait
During a Data Wait, an external device drives data onto the
P1AD bus, but the MXT3010EP i gnores that dat a. Thus, the
P1AD column in the state table shows In-X, and the IRDY_
column shows de-assertion (high) indicating that the
MXT3010EP will not read the data. There are three com-
mon cases for what happens after a Data Wait:
-If ASEL_ remains de-asserted (high) and TRDY_
remain s de-asserted ( high), the Data Wait is f ollowed by
another Data Wait.
-If TRDY_ is asserted (low) and LTN is de-asserted
(low), the Data Wait is followed by a Data Read.
-If TRDY_ is asserted (low) and LTN is asserted (high),
the Data Wait is followed by a Last Transfer.
There are two other cases for what happens after a Data
Wait, but these are used less often than the three listed
above.
-If the states of ASEL_ and TRDY_ are switched to
ASEL_ asserted (low) and TRDY_ de-asserted (high),
the Data Wait is followed by Tri-state (DW) and all
outputs are tri-stated.
-If ASEL_ is asserted (low) and TRDY_ remains
asserte d ( lo w), t he Data Wait is fol l owed b y an Addres s
cycle.
1. The state machine keeps track of several versions of the tri-state condition.
For example, Tri-state (Data) refers to a tri-state condition entered from
the Data Read state. See “Tri-state” on page 117.
MXT3010 Reference Manua l Version 4.1 117
Port Operations
• Tri-state
During a tri-state condition, all o utputs are tri-sta te. Th is
condition is always entered whenever ASEL_ is asserted
(low) and TRDY_ is de-asserted (high). The state machine
maintains se parate versions of the tri-state condition
depending upon the state from which the state machine
entered the tri-state condition. The versions are Tri-state
(Address 1), Tri-state (Add ress2) , T r i-st ate (Aut omatic -turn -
around), Tri-state (Data), Tri-state (Data Wait), Tri-state
(Last Transfer), Tri-state (Clean-up), and Tri-state (Turn-
around Wait). As shown in Table 26, four of t hes e st at es ar e
identical, transitioning to Data Read or Last Transfer
depending upon the state of the LTN input.
• Last Transfer
Last Transfer is a special case of Data Read. It differs from
Data Read in three ways:
-The END_ output is asserted (low) during Last Transfer
-During this state, external logic decides how to
condition the ASEL_ and TRDY_ leads during the
Clean Up state that follows. This, in turn, will determine
the state that follows the Cl ean Up state.
-It is follow ed by the Clea n Up state.
• Clean Up
During the Clean Up state, the IRDY_ and END_ outputs
are de- as ser te d ( hi gh) a nd P1RQ_ is de- ass er te d ( hi gh). The
state whi ch follows Clean Up is determined by t he condition
of ASEL_ and TRDY_. As in dicated above, the cond ition of
thes e inpu ts was determin ed by the external ar bitration lo gic
during the Last Transfer state.
118 Version 4.1 MXT3010 Reference Manual
The Port1 and Port2 Interfaces
TABLE 26. State table for the Port1 DMA burst read state machine
Table Line
Input
Signals
Current State Next State
Outputs in the
Next State
ASEL_
TRDY_
LTN
P1AD
IRDY_
END_
1 L H Xa
a. X = don’t care
Any Tri-state (current_state) Tri-state
2 L L X Any pre Auto-turna r oundb
b. A pre Auto-turnaround st ate is any state bet w een the most recent Last Transfer state and the
Auto-turnaround state of a DMA transfer . A post turnaround state is any state between the most
recent auto turnaround and th e next Last Transfer state.
Address 1 Out-Addr H H
3 L L X Any post Auto-turnaround Address 2 Out-Addr H H
4 H L X Address 1 Auto-turnaroundc
c. This Auto-turnaround will be Auto-turnaround Wait if there is no RQ_ assertion at this time.
Tri-state H H
5 H L L Address 2 Data Read In-Data L H
6 H L H Address 2 Last Transfer In-Data L L
7 H L L Auto-turnaround Data Read In-Data L H
8 H L H Auto-turnaround Last Transfer In-Data L L
9 H L L Data Read Data Read In-Data L H
10 H L H Data R ead Last Transfer In-Data L L
11 H L X Auto-turnaround Wait Auto-turnaroundbTri-state H H
12 H L L Data Wait Data Read In-Data L H
13 H L H Data Wait Last Transfer In-Data L L
14 H L X Last T ransfer Clean Up In-X H H
15 H L X Clean Up, Tri-state (Last Transfer) Auto-turnaround Wait Tri-state H H
16 H L X Tri-state (Address 1, Clean Up,
Auto-tu r na round Wait) Auto-turnaroundbTri-state H H
17 H L L Tri-state (Address 2, Auto-turn-
around, Data Read, or Data Wait) Data Read In-Data L H
18 H L H Tri-state (Address 2, Auto-turn-
around, or Data Wait) Last Transfer In-Data L L
19 H H X Addre ss 1, Auto-tu r na ro und Wait,
Tri-state (Address 1, Auto-turn-
around Wait)
Auto-turnaround Wait Tri-state H H
20 H H X Addre ss 2, Auto-tu r na ro und, Dat a
Read, Data Wait, Clean Up, Tri-
state (Auto-turnaround, Address2,
Data, Data Wait, Last Transfer, or
Clean Up)
Data Wait In-X H H
21 H H X Last Transfer Clean Up In-X H H
MXT3010 Reference Manua l Version 4.1 119
Port Operations
FIGURE 45.Port1 DMA Read tran sfer with a Wait state
Figure 45 shows the Last Transfer (LTX) and Clean Up (CU)
states of a previous DMA r ead or write t ransfer. During the Last
Transfer state, the external logic that controls the ASEL_ and
TRDY_ leads makes a decision as to whether it should:
1. Allow a COMM SEL tran sfer (havi ng dete cted a communi-
cation request)
2. Prepare for another DMA transfer (having detected
P1QRQ_ asserted)
3. Relinquish the bus by entering a tri-state condition
4. Perform some other type of bus operation
Having decided on the appropri ate course of action, the external
control logic conditi ons ASEL_ and TRDY_ at the beginning of
the Clean Up state so that the Port1 state machine will enter the
desired state after the Clean Up state.
CLK
P1END_
P1TRDY_
P1ASEL_
P1RQ_
COMMSEL
P1RD
14 2 4 7 9 20 12 9 9 10 14 1 1
P1QRQ_
P1IRDY_
D3
P1ADin[31:0]
ADR
D0 D1 D4
QRQ_ reasserts if another DMA enters port queue
P1ADout[31:0]
11
11 11
11
P1HWE[1:0] 10 or 1 1
Next state is determined by table line #
LTN (Internal )
State LTX CU AD1 ATA RD RD DW RD RD RD LTX CU TRI
D5
01 or 11
01 or 11
If read
If writ e If write
D2
120 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
In the example shown in Figure 45, the external logic elects to
perform a new DMA transfer, and drives both ASEL_ and
TRDY_ to the asserted (low) state during the Clean Up state.
With ASEL_ and TRDY_ low, the Clean Up state qualifies as
Any pre Auto-turnaround state in t he Table 26 st ate t able. Thus ,
when the state mac hin e samples t he ASEL_ a nd TRDY_ le ads ,
line 2 of the state table causes the next state to be Address 1
(AD1).
During Address 1, the MXT3010EP puts address information
onto the P1AD leads. IRDY_ and END_ are high. If, during
Address 1, the external logic drives ASEL_ high while leaving
TRDY_ low, the sta te machine sampl es that conditi on, and line
4 of the state table causes the next state to be Auto-turnaround.
During Auto-turnaround, the MXT3010EP prepares the P1AD
leads for data transfer. IRDY_ and END_ are still high. With
ASEL_ still high and TRDY still low during the Auto-turn-
around state, line 7 of the state table causes the next state to be
a Data Read state.
During Data Read, an external device places data on the P1AD
leads, a nd the MXT3010EP asserts t he IRDY_ l ea d l ow t o i ndi -
cate it is going to sample that data. Since ASEL_ is still high and
TRDY_ is low, the state machine samples that condition, and
line 9 of the state table causes the next state to be a Data Read
state.
The second Data Read in the above example is identical to the
previous D ata Read, ex cept that the external logic has driven
TRDY_ high. Since TRDY_ has gone high, line 20 of the state
table causes the next state to be a Data Wait state. The use of a
Data Wait state is optional. It is shown in this figure and subse-
quent figures only to illustrate the waveforms that occur during
a Data Wait.
MXT3010 Reference Manua l Version 4.1 121
Port Operations
During Data Wait, the incoming data is i gnored (“In-X”), and
the IRDY_ lead goes high to indicate that the MXT3010EP is
not go ing to sample the da ta. In the example , TRDY_ ret urns i s
returned to the low state, the state machine samples that condi-
tion, and line 12 of the state table causes the next state to be a
Data Read state.
During Data Read, an external device places data on the P1AD
leads, and the MXT3010EP asserts the IRDY_ lead (low) to
indicate it is going to sample that data. Since ASEL_ is still high
and TRDY_ is low, line 9 of the s tate table cause s the next state
to be a Data Read state.
This Data Read is similar to the previous Data Reads. Since
ASEL_ is still high and TRDY_ is low, line 9 of the state table
causes the next state to be a Data Read state.
During this Data Read, the LTN signal (generated by the byte
count l ogic within t he MXT3010EP) is a sserted. Ther efore, lin e
10 of the state table causes the next state to be a Last Transfer
(LTX).
Last Transfer is similar to a Data Read, except that the END_
output is asserted (low). Line 14 of the state table causes the next
state to be a Clean Up (CU) state. During the Last T ransfer state,
the external controller decides what to do with the ASEL_ and
TRDY_ inputs during t he Clean Up state. The stat e that fol lows
the Clea n Up stat e depe nds upon that d ecisi on. In t his ex ample,
the dec ision was to tri -stat e the bus. Thus, durin g Clean Up, the
external controller has driven ASEL_ low and TRDY high.
When the state machine samples that condition, line 1 of the
state table causes the next state to be Tri-state (CleanUp).
122 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
FIGURE 46.Port1 DMA Read tran sfer without a Wait state
Figure 46 is similar to Figure 45, but without a wait state. The
description of the figure is identical, except that there are no
transitions controlled by lines 20 or 12 of the state table, as
P1TRDY_ remains asserted (low) throughout the transfer.
Rather, the read proce ss continues to be det ermined by line 9 of
the state table until LTN is asserted and state table line 10
applies, causing the next state to be Last Transfer (LTX).
Port1 DMA write transfers
Ta ble 27 shows the state table for Port1 DMA write transfers,
and Figure 47 shows a sequence diagram for a DMA write trans -
fer. The t abl e and the f ig u re ar e best unde rst ood by con si dering
the function of the various inputs, outputs, and states for write
transfers.
CLK
P1END_
P1TRDY_
P1ASEL_
P1RQ_
COMMSEL
P1RD
14 2 4 7 9 9 9 9 10 14 1 1
P1QRQ_
P1IRDY_
P1ADin[31:0]
ADR
D0 D1 D4
QRQ_ reasserts if another DMA enters queue
P1ADout[31:0]
11
11 11
P1HWE[1:0] 10 or 11
Next state is determined by table line #
LTN (Internal )
State LTX CU AD1 ATA RD RD RD RD RD LTX CU TRI
D5
01 or 11
01 or 11
If read
If writ e If write
D2 D3
11
MXT3010 Reference Manua l Version 4.1 123
Port Operations
Inputs
• ASEL_, TRDY_, LTN
These inputs have the same definitions as shown page 113.
Outputs
•P1AD
This is a bi- directi onal add ress/ data bus . It has fou r possib le
states : Out-Add ress, Out -Data , Out-X (Don’t Care), and Tri-
state. In contrast to a DMA read, when the bus is changed
from an address mode (outward) to a write data mode (out-
ward), no intervening states are re quired.
• IRDY_
When this output is asserted, the MXT3010EP is sourcing
valid data. Thus, in Table 27, IRDY_ is asserted only when
the next state is Out-Data.
•END
The END_ output is asserted by the MXT3010EP du ring the
Last Transfer state. This output can be used by any external
logic that requires this information.
Although not shown in Table 27, the state machine also has a
COMMSEL input. Dur ing DMA tr ans fers, t he COMMSE L s ig-
nal is low for all states shown. Please see“Communication reg-
ister I/O transfers” on page 133 for COMMSEL high.
States
•Address
In contrast to a DMA read, the write state machine has only
one state for Address. When a DMA cycle begins, and the
MXT3010 EP samples both ASEL_ and TRDY_ as as serted
(low), t he MXT3010EP dri ves addr ess i nformatio n onto the
P1AD bus; this is referred to as an Address state.
124 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
• Data Write
During a Data Wr ite, the MXT3010EP drives data onto the
P1AD bus and an external device reads that data. Thus, the
P1AD column in the state table shows Out-Data, and the
IRDY_ column shows assertion (low) indicating that the
MXT3010EP is sourcing valid data. There are three com-
mon cases for what happens after a Data Write:
-If ASEL_ remains de-asserted (high) and TRDY_
remains asserted (low), the Data Write is followed by
another Data Write.
-If TRDY_ is de-asserted (high), the Data Write is
followed by a Data Wait.
-If LTN is asserted (high), the Data Write is followed by
a Last Transfer.
There are two other cases for what happens after a Data
Write, but these are used less often than the three listed
above.
-If the states of ASEL_ and TRDY_ are switched to
ASEL_ asserted (low) and TRDY_ de-asserted (high),
the Data Write is followed by Tri-state (Data)1.
-If ASEL_ is asserted (low) and TRDY_ remains
asserted (low), the Data Write is followed by an
Address cycle.
• Data Wait
During a Data Wait, the MXT3010EP drives data onto the
P1AD bus, but the external device ignores that data. Thus,
the P1AD column in the state table shows Out-X, and the
IRDY_ column s hows de-asser tion (high) indicating th at the
external device should not read the data. There are three
common cases for what happens after a Data Wait:
1. The state machine keeps track of several versions of the tri-state condition.
For example, Tri-state (Data) refers to a tri-state condition entered from
the Data Write state.
MXT3010 Reference Manua l Version 4.1 125
Port Operations
-If ASEL_ remains de-asserted (high) and TRDY_
remain s de-asserted ( high), the Data Wait is f ollowed by
another Data Wait.
-If TRDY_ is asserted (low) and LTN is de-asserted
(low), the Data Wait is followed by a Data Wr ite.
-If TRDY_ is asserted (low) and LTN is asserted (high),
the Data Wait is followed by a Last Transfer.
There are two other cases for what happens after a Data
Wait, but these are used less often than the three listed
above.
-If the states of ASEL_ and TRDY_ are switched to
ASEL_ asserted (low) and TRDY_ de-asserted (high),
the Data Wait is followed by Tri-state (Data Wait) and
all outputs are tri-st ated.
-If ASEL_ is asserted (low) and TRDY_ remains
asserte d ( low), the Data Wait is fol l owed by an Addr ess
cycle.
• Tri-state
During a tri-state condition, all o utputs are tri-sta te. Th is
condition is always entered whenever ASEL_ is asserted
(low) and TRDY_ is de-asserted (high). The state machine
maintains se parate versions of the tri-state condition
depending upon the state from which the state machine
entered the tri-state condition. The versions are Tri-state
(Address), Tri-state (Data), Tri-state (Data Wait), Tri-state
(Last Transfer), and T ri-stat e (Clean-up ). As shown in Table
27, three of these states are identical, transitioning to Data
Read or Last Tr ansfer depending upon the state of the LTN
input.
126 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
TABLE 27. State table for the Port1 DMA burst write state machine
Table Line
Input
Signals
Current State Next State
Outputs in the
Next State
ASEL_
TRDY_
LTN
P1AD
IRDY_
END_
1 L H X Any Tri-state (current_state) Tri-state
2 L L X Any Address Out-Addr HH
3 H L L Address Data Write Out-Data L H
4 H L H Address Last Transfer Out-Data L L
5 H L L Data Write Data Write Out-Data L H
6H L H Data Write Last Transfer Out-Data L L
7H L L Data Wait Data Write Out-Data L H
8H L H Data Wait Last Trans f er Out-Data L L
9 H L X Last Transfer Clean Up Out-X HH
10 H L X Clean Up Idlea
a. The Idle state will be maintained indefinitely if there is no RQ_ assertion.
Tri-state HH
11 H L L Idle, Tri-state (Address, Data
Write, or Data Wait) Data Write Out-Data L H
12 H L H Tri-state (Address, Data Write, or
Data Wait) Last Transfer Out-Data LL
13 H L X Tri-state (Last Transfer, Clean Up) Data Write Out-X HH
14 H H X Address, Data Write, Data Wait,
Clean Up, Tri-state (Address, Data
W rite, Data Wait, Last T ransfer, or
Clean Up)
Data Wait Out-X HH
15 H H X Last T ransfer Clean Up Out-X HH
MXT3010 Reference Manua l Version 4.1 127
Port Operations
FIGURE 47.Port1 DMA Write transfer with a Wait state
Figure 47 shows the Last Transfer (LTX) and Clean Up (CU)
states of a previous DMA r ead or write t ransfer. During the Last
Transfer state, the external logic that controls the ASEL_ and
TRDY_ leads makes a decision as to whether it should:
1. Allow a COMM SEL transfer (having detected communi-
cation request)
2. Prepare for another DMA transfer (having detected
P1QRQ_ asserted)
3. Relinquish the bus by entering a tri-state condition
4. Perform some other type of bus operation
CLK
P1END_
P1TRDY_
P1ASEL_
P1RQ_
COMMSEL
P1RD
9 2 3 5 14 7 5 5 6 9 1 1
P1QRQ_
P1IRDY_
D3
P1ADin[31:0]
ADR
D0 D1 D4
QRQ_ reasserts if another DMA enters queue
P1ADout[31:0]
11
11 11
11
P1HWE[1:0] 10 or 11
Next state is determined by table line #
LTN (Internal)
State LTX CU ADR WD WD WDW WD WD WD LTX CU TRI
D5
01 or 11
01 or 11
If read
If wr ite If wr i te
D2
128 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
Having decided on the appropri ate course of action, the external
control logic conditi ons ASEL_ and TRDY_ at the beginning of
the Clean Up state so that the Port1 state machine will enter the
desired state after the Clean Up state.
In the example shown in Figure 47, the external logic elects to
perform a new DMA transfer, and drives both ASEL_ and
TRDY_ to the asserted (low) state during the Clean Up state.
With ASEL_ and TRDY_ low, the Clean Up state qualifies as
Any state in the Table 27 state table. Thus, when the state
machine samples the ASEL_ and TRDY_ leads, line 2 of the
state table causes the next state to be Address (ADR).
During the Address state, the MXT3010EP puts address infor-
mation onto the P1AD leads. IRDY_ and END_ are high. If,
during the Address state, the external logic drives ASEL_ high
while leaving TRDY_ low, the state machine samples that con-
dition, and line 3 of the state table causes the next state to be
Data Write.
During Data Write, the MXT3010EP places data on the P1AD
leads, a nd the MXT3010EP asserts t he IRDY_ l ea d l ow t o i ndi -
cate that it has done so. Si nce ASEL_ is still high and TRDY_ is
low, the state machine samples that condition, and line 5 of the
sta te tabl e causes the next state t o be a Da ta Write state .
The second Data Write in the above example is identical to the
previous Data Write, except that the external logic has driven
TRDY_ high. Since TRDY_ has gone high, line 14 of the state
table causes the next state to be a Data Wait state. The use of a
Data Wait state is optional. It is shown in this figure and subse-
quent figures only to illustrate the waveforms that occur during
a Data Wait.
During Data Wait, the outgoing data should be ignored (“Out-
X”), and the IRDY_ lead goes high to indicate that the
MXT3010EP does not guarantee the data. In the example,
MXT3010 Reference Manua l Version 4.1 129
Port Operations
TRDY_ returns is returned to the low state, the state machine
samples that condition, and line 7 of the state table causes the
next state to be a Data Write state.
During Data Write, the MXT3010EP places data on the P1AD
leads, a nd the MXT3010EP asser ts t he I RDY_ l ead low t o i ndi -
cate that it has done so. Si nce ASEL_ is still high and TRDY_ is
low, the state machine samples that condition, and line 5 of the
state table causes the next state to be a Data Write state.
This Data Write is similar to the previous Data Writes. Since
ASEL_ is still high and TRDY_ is low, line 5 of the state table
causes the next state to be a Data Write state.
During this Data Write, the LTN signal (generated by the byte
count l ogic within t he MXT3010EP) is a sserted. Ther efore, lin e
6 of the state table causes the next state to be a Last Transfer
(LTX).
Last Transfer is similar to a Data Write, except that the END_
output i s assert ed (low). Line 9 of t he state table ca uses the next
state to be a Clean Up (CU) state. During the Last T ransfer state,
the external controller decides what to do with the ASEL_ and
TRDY_ inputs during t he Clean Up state. The stat e that fol lows
the Clea n Up stat e depe nds upon that d ecisi on. In t his ex ample,
the dec ision was to tri -stat e the bus. Thus, durin g Clean Up, the
external controller has driven ASEL_ low and TRDY high.
When the state machine samples that condition, line 1 of the
state table causes the next state to be Tri-state (CleanUp).
130 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
FIGURE 48.Port1 DMA Write transfer without a Wait state
Figure 48 is similar to Figure 47, but without a wait state. The
description of the figure is identical, except that there are no
transitions controlled by lines 14 or 7 of the state table, as
P1TRDY_ remains asserted (low) throughout the transfer.
Rather , the wri te process continues to be determined by li ne 5 of
the state table until LTN is asserted and state table line 6 applies,
caus ing t he next state to be Last Transfer ( LTX).
Multiple Port1 Read and Write Transfers
Figure 45 and Figure 47 each show the conclusion of a DMA
transfer followed by the read or write DMA transfer being
descri bed. In each case, th e commenc ement of a DMA transfer
depends upon the states of QRQ_, RQ_, ASEL_ and TRDY_
during the Clean Up phase of the preceding bus cycle. Thus, to
CLK
P1END_
P1TRDY_
P1ASEL_
P1RQ_
COMMSEL
P1RD
9 2 3 5 5 5 5 6 9 1 1
P1QRQ_
P1IRDY_
D3
P1ADin[31:0]
ADR D0 D1 D4
QRQ_ reasserts if another DMA enters queue
P1ADout[31:0]
11
11 11
P1HWE[1:0] 10 or 11
Next state is determined by table line #
LTN (Internal)
State LTX CU ADR WD WD WD WD WD LTX CU TRI
D5
01 or 11
01 or 11
If read
If writ e If write D2
11
MXT3010 Reference Manua l Version 4.1 131
Port Operations
create timing diagrams representing an arbitrary sequence of
Port1 reads and writes, photocopy Figure 49 and Figure 50
below, and cut them on the heavy lines shown. Paste them
together to create the desired diagram.
FIGURE 49.Cut-and- Paste Version of Port1 Read
CLK
P1END_
P1TRDY_
P1ASEL_
P1RQ_
COMMSEL
P1RD
14 2 4 7 9 20 12 9 9 10 14 1 1
P1QRQ_
P1IRDY_
D3
P1ADin[31:0]
ADR
D0 D1 D4
QRQ_ reasserts if another DMA enters port queue
P1ADout[31:0]
11
11 11
11
P1HWE[1:0] 10 or 11
Next state is determined by table line #
LTN (Internal )
State LTX CU ADR1 ATA RD RD DW RD RD RD LTX CU TRI
D5
01 or 11
01 or 11
If read
If writ e If write
D2
132 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
FIGURE 50. Cut-and-Paste Version of Port1 Write
CLK
P1END_
P1TRDY_
P1ASEL_
P1RQ_
COMMSEL
P1RD
9 2 3 5 14 7 5 5 6 9 1 1
P1QRQ_
P1IRDY_
D3
P1ADin[31:0]
ADR D0 D1 D4
QRQ_ reasserts if another DMA enters queue
P1ADout[31:0]
11
11 11
11
P1HWE[1:0] 10 or 11
Next state is determined by table line #
LTN (Internal)
State LTX CU ADR WD WD WDW WD WD WD LTX CU TRI
D5
01 or 11
01 or 11
If read
If writ e If write D2
MXT3010 Reference Manua l Version 4.1 133
Port Operations
Communication register I/O transfers
In addition to monitoring bus request signals from the
MXT3010EP and oth er devices, ar bitration logi c external t o the
MXT3010EP monitors external requests for Communication
Registe r I/O transfe rs. Upon decid ing to star t a Communication
Register I/O transfer , the external logic asserts ASEL_ (low) and
de-asserts TRDY_ (high) to bring the Port1 bus into a tri-state
conditi on. The exter nal logic then asserts the COMMSEL input
of the MXT3010EP. The P1RD signal, driven by the external
devic e, determines whether the I/O tran sfer is a read o r write.
Since the state tables for COMMSEL reads and COMMSEL
writes a re so br ief, Table 28 shows th e combi n e d st at e ta ble for
both reads and writes. Figure 51 shows a sequence diagram for
a typical COMMIN write followed by a COMMOUT read.
TABLE 28. S tate table for Port1 communication I/O state machine
Table Line
Input Signals
Current State Next State
Outputs in the
Next State
ASEL_
TRDY_
COMMSEL
P1RDa
a. During Comm unications I/O, P1RD is driven b y an external device
P1AD
1 L H L X Any Tri-state (current_state) Tri-state
2 L H H H Tri-state (current_state) Comm Out Read 1 Tri-state
3 L H H H Comm Out Read 1 Comm Out Read 2 Tri-state
4 L H H H Comm Out Read 2 Comm Out Data Valid Data
5 L H H H Comm Out Data Valid Comm Out Data Valid Data
6 L H H L Tri-state (current_state) Comm In Write Tri-stateb
b. During this and the next state, the MXT3010 tristates the bus. The external device drives data
onto the bus.
7 L H H L Comm In Write Comm In Write Tri-state
8 L H L L Comm In Write Co mm In Data Strobe Data from external
device
134 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
FIGURE 51.COMMIN write1 followed by COMMOUT read
Figure 51 shows the Last Transfer (LTX) and Clean Up (CU)
states of a previous DMA r ead or write t ransfer. During the Last
Transfer state, the external logic that controls the ASEL_ and
TRDY_ leads makes a decision as to whether it should:
1. Allow a COMM SEL tran sfer (havi ng dete cted a communi-
cation request)
2. Prepare for another DMA transfer (having detected
P1QRQ_ asserted)
3. Relinquish the bus by entering a tri-state condition
4. Perform some other type of bus operation
Having decided on the appropri ate course of action, the external
control logic conditi ons ASEL_ and TRDY_ at the beginning of
the Clean Up state so that the Port1 state machine will enter the
desired state after the Clean Up state.
1. In a COMMIN write, data is written from an external device into the MXT3010EP. In a COM-
MOUT read, data is read from the MXT3010EP by an external device.
CLK
P1END_
P1TRDY_
P1ASEL_
P1RQ_
COMMSEL
P1RD
---- ---- 6 8 1 2 3 4 10 1
P1QRQ_
P1IRDY_
Data
P1ADin[31:0] Data
P1ADout[31:0]
Next state is determined by table line #
State LTX CU TRI CIW CIS TRI RD1 RD2 DV TRI
If read
If write If write
QRQ_ reasserts if another DMA enters port queue
MXT3010 Reference Manua l Version 4.1 135
Port Operations
In the example shown in Figure 51, the external logic elects to
perform COMMIN and COMMOUT transfers. To do this, it
drives ASEL_ low an d TRDY_ high dur ing the Clean Up st ate.
Sampling ASEL_ low and TRDY_ high, the MXT3010EP
places the P1 bus in the Tri-state condition (see line 1 of Table
26, Table 27, and Table 28).
During the Tri-state condition, the external logic asserts the
COMMSEL input and drives P1RD to select a read or write
transfer. Detecting the assertion of COMMSEL, the
MXT3010EP prepa res an int ernal data path for the read or write
of R40/41, the Host Communication registers.
In Figure 51, the MXT3010EP samples the assertion of COM-
MSEL high and P1RD low, and line 6 of the state table causes
the next s tate t o be Comm In Write. During t he Comm In Write
state, the external logic de-asserts COMMSEL while retaining
P1RD low. The MXT3010EP sampl es these conditi ons and line
8 of the state table causes the next state to be Comm In Data
Strobe.
During Comm In Data Strobe, data supplied by an external
device is written into the 32-bit register formed by the concate-
nation of R40 and R41 within the MXT3010EP. Also during
Comm In Data Strobe, the states of ASEL_ (low), TRDY_
(high), and COMMSEL (low) are such that line 1 of the state
table causes the next state to be Tri-state.
During this Tri-state condition, the external logic asserts the
COMMSEL input and drives P1RD high to select either a read
transfer . In Figure 51, the MXT3010EP sampl es the assertion of
COMMSEL high and P1RD high, and line 2 of the state table
causes the next state to be Comm Out Read 1. If the COMMSEL
and P1RD leads are mai ntained in their high states during
Comm Out Read 1, lin e 3 of the stat e tabl e cau ses t he next state
to be Comm Out Read 2.
136 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
If the COMMSEL and P1RD leads are maintained i n their high
states dur in g Comm Out Rea d 2, line 4 of th e state ta ble ca use s
the next state to be Comm Out Data Valid. During Comm Out
Data Valid, data supplied by the concatenation of R40 and R41
within the MXT3010EP is supplied to the external device.
If the externa l device can sample the data quickly during Comm
Out Data Valid, the external logic can condition the states of
ASEL_ (low), TRDY_ (h igh ), a nd COMMSEL (low) such tha t
line 1 of the state table causes the next state to be Tri-state. If the
exte rnal devic e require s more ti me to sample the data , the exter -
nal logic can condition the states of ASEL_ (low), TRDY_
(high), and COMMSEL (high) such that line 5 of the s tate table
causes the next state to be an additional period of Comm Out
Data Valid.
MXT3010 Reference Manua l Version 4.1 137
Port Operations
Port2 basic protoco l
The Port2 interface supports two transfer mechanisms:
MXT3010-initiated DMA burst mode transfers and non-burst
transfers. Each command issued to the DMA command queue is
tagged as either burst or non-burst, via rsa bit 7. If rsa[7] is 1, the
transfer is a burst transfer. If rsa[7] is 0, the transfer is a non-
burst transfer. Non-burst transfers can insert a programmable
number of wait states.
Figure 52 and Table 29 illustrate the correspondence between
rsa/rsb register values, the Port2 bus signals, and a logical half-
word address for Port2 burst DMA transfers.
FIGURE 52.Diagram of Port2 burst DMA instruction bits
15 14 13 12 11 10 9876543 2 1 0
rsa Unused Burst Unused P2AD [15:11]
A19 A18 A17 A16 A15
15 14 13 12 11 10 9876543210
rsb P2AD[10:0] P2AI [3:0] 0
A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
TABLE 29. Port2 burst DMA instruction bit mapping
Reg Bits Function Port2 Bus Logical
Halfword Bit
rsa 15:08 Not used - -
07 Burst bit = 1 (selects mode) -
06:05 Not used - -
04:00 Address P2AD[15:11] 19:15
rsb 15:05 Address P2AD[10:0] 14:04
04:01 Address P2AI[3:0] 3:0
00 Discarded - -
138 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
The information in Table 29 can also be expressed as shown in
Ta ble 30.
TABLE 30. Another view of Port2 burst DMA instruction bit mapping
Since th e Port2 bur st DMA instructi on bit mapping per mits the
use of 2 0-b it ha lfword addres sing, one mill ion ( 1M) 16-b it ha lf-
words can be addressed.
Firmware Byte
Address Bit
MXT3010
Internal Register
Bit
Memory
Halfword
Address Bit MXT3010 Port2
Pin
A00 (lsb) RSB[0] -- NC
A01 RSB[1] A00 (lsb) HW P2AI[0]
A02 RSB[2] A01 P2AI[1]
A03 RSB[3] A02 P2AI[2]
A04 RSB[4] A03 P2AI[3]
A05 RSB[5] A04 P2AD[0]
A06 RSB[6] A05 P2AD[1]
A07 RSB[7] A06 P2AD[2]
A08 RSB[8] A07 P2AD[3]
A09 RSB[9] A08 P2AD[4]
A10 RSB[10] A09 P2AD[5]
A11 RSB[11] A10 P2AD[6]
A12 RSB[12] A11 P2AD[7]
A13 RSB[13] A12 P2AD[8]
A14 RSB[14] A13 P2AD[9]
A15 RSB[15] A14 P2AD[10]
A16 RSA[0] A15 (msb) HW P2AD[11]
A17 RSA[1] A16 P2AD[12]
A18 RSA[2] A17 P2AD[13]
A19 RSA[3] A18 P2AD[14]
A20 RSA[4] A19 P2AD[15]
MXT3010 Reference Manua l Version 4.1 139
Port Operations
Figure 53 and Table 31 illustrate the correspondence between
rsa/rsb register values, the Port2 bus signals, and a logical half-
word address for Port2 non-burst DMA transfers.
FIGURE 53.Diagram of Port2 non-burst DMA instruction bits
.
15 14 13 12 11 10 9876543 2 1 0
rsa Unused # of Waits Burst P2A[3:2] P2AD [15:11]
A17 A16 A15 A14 A13 A12 A11
15 14 13 12 11 10 9876543210
rsb P2AD[10:0] Unused
A1 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0
TABLE 31. Port2 non-burst DMA instruction bit mapping
Reg Bits Function Port2 Bus Logical
Halfword Bit
rsa 15:11 Not used - -
10:08 #waits [2:0] (selects number of wait states) -
07 Burst bit = 0 (selects mode) -
06:05 Address P2AI[3:2] 17:16
04:00 Address P2AD[15:11] 15:11
rsb 15:05 Address P2AD[10:0] 10:0
04:00 Discarded - -
140 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
The information in Table 31 can also be expressed as shown in
Ta ble 32.
TABLE 32. Another view of Port2 non-burst DMA instruction bit
mapping
Since the Port2 non-burst DMA inst ruction bit mappi ng permits
the use of 18-bit halfword addressing, 256K 16-bit halfwords
can be addressed.
Firmware Byte
Address Bit
MXT3010
Internal Register
Bit
Memory
Halfword
Address Bit MXT3010 Port2
Pin
A00 (lsb) RSB[0] -- NC
A01 RSB[1] -- NC
A02 RSB[2] -- NC
A03 RSB[3] -- NC
A04 RSB[4] -- NC
A05 RSB[5] A00 (lsb) HW P2AD[0]
A06 RSB[6] A01 P2AD[1]
A07 RSB[7] A02 P2AD[2]
A08 RSB[8] A03 P2AD[3]
A09 RSB[9] A04 P2AD[4]
A10 RSB[10] A05 P2AD[5]
A11 RSB[11] A06 P2AD[6]
A12 RSB[12] A07 P2AD[7]
A13 RSB[13] A08 P2AD[8]
A14 RSB[14] A09 P2AD[9]
A15 RSB[15] A10 P2AD[10]
A16 RSA[0] A11 P2AD[11]
A17 RSA[1] A12 P2AD[12]
A18 RSA[2] A13 P2AD[13]
A19 RSA[3] A14 P2AD[14]
A20 RSA[4] A15 (msb) HW P2AD[15]
A21 RSA[5] A16 P2AI[2]
A22 RSA[6] A17 P2AI[3]
MXT3010 Reference Manua l Version 4.1 141
Port Operations
Multi-function AI pins (P2AI[3:0])
In burst mode, P2AI [3:0] provide an address index consisting
of the l ower fo ur bits of an add res s ( see Table 29). I n non -bu rst
mode, P2AI[3:2] provide the most significant address bits (see
Table 31) . Also in non-burst mode, P2AI [1] repres ents P2RD_,
and P2AI[0] represents Address Latch Enable. These signals
can b e us ed to provide a glueles s i n te rf ace to non-bu rs t devices.
Port2 control signals
Ta ble 33 describes the signals that control Port2 transfers
TABLE 33. Signals to control Port2 transfers
Signal Purpose
P2QRQ_ When the Port2 state ma chine detect s th e presence of a command in the queue
stage of the Port2 DMA command queue, the state machine asserts this signal to an
external device; this provides advance indication that P2RQ_ will soon be asserted.
P2RQ_ When the Port2 sta te machine is in the Idle stat e and detects the presence of a com-
mand in the active stage of the Port2 DMA command queue, the state machine
asserts thi s signal to an external device. Th e external devi ce responds by manipu-
lating P2ASEL_ and P2TRDY_ to control a DMA transfer.
P2TRDY_ This signal is an input to the MXT3010 and is dr iven by an external device. The
externa l device uses this signal to insert wait states. The extern al device can also
use this signal in conjunct ion with P2ASEL_ to dese le ct (tri-state) the Port2 DMA
engine.
P2IRDY_ During DMA write data cycles, the MXT3010 asserts P2IRDY while it is sourcing
valid data on P 2AD[15:0]. During DMA read data operations, the MXT3010
asserts P2IRDY_ if it is able to sample P2AD[15:0] on the next rising edge of
clock.
P2ASEL_ This signal is an input to the MXT3010 and is driven by an external device. The
externa l device uses this signal to select b etween address and data cycles. The
external device can also use this signal in conjunction with P2TRDY_ to deselect
(tri-state) the Port2 DMA engine.
P2QBRST This sign a l is a n o u tpu t d r ive n by th e MXT3 01 0. Th e M X T3 01 0 u s e s this sig n al to
indicat e the transfer mode, such as burst or non-burst, of the active command.
P2RD During a DMA transfer, this signal is an output driven by the MXT3010. This sig-
nal indicates whether the transfer is a read (1) or a write (0) transfer.
P2END_ This signal indicates the last cycle of a DMA o peration.
P2AD[15:0] This is a multiplexed, bi-directional 16-bit bus. Data is read into and out of the
MXT3010 during DMA transfers.
LTN This is an internal signal indicating that the Last Transfer will occur Nex t (LTN).
142 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
The Port2 control state machine
Port2 DMA transfers originate and terminate as discussed in
“General information concerning DMA transfers” on page 113.
Port2 DMA burst-mode read transfers
Ta ble 34shows the state table for Port2 DMA burst-mode read
transfers and Figure 56 shows a sequence diagram for a Port2
DMA burst-mode read transfer . T able 34 is identical to T able 26,
“State table for the Port1 D MA burst read sta te mac hine,” on
page 118. The inputs, outputs, and states are the same as those
descri bed i n “In put s” on pa ge 1 13, “Ou tpu ts” on page 1 1 4, and
“States” on page 114, with four exceptions:
1. All signal name s bear a P2 prefix instea d of P1.
2. The P2AD bus is 16 bits; the P1AD bus is 32 bits (and has
HalfWord Enable signals).
3. Only Port1 has a COMMSEL input.
4. Only Port2 has a P2QBRST output.
MXT3010 Reference Manua l Version 4.1 143
Port Operations
TABLE 34. State table for the Port2 DMA burst-mode read state machine
Table Line
Input
Signals
Current State Next State
Outputs in the
Next State
ASEL_
TRDY_
LTN
P2AD
IRDY_
END_
1 L H X Any Tri-state (current_state) Tri-state
2 L L X Any pre Auto-turna r ound Address 1 Out-Addr H H
3 L L X Any post Auto-turnaround Address 2 Out-Addr H H
4 H L X Address 1 Auto-turnaround Tri-state H H
5 H L L Address 2 Data Read In-Data L H
6 H L H Address 2 Last Transfer In-Data L L
7 H L L Auto-turnaround Data Read In-Data L H
8 H L H Auto-turnaround Last Transfer In-Data L L
9 H L L Data Read Data Read In-Data L H
10 H L H Data R ead Last Transfer In-Data L L
11 H L X Auto-turnaround Wait Auto-turnaround Tri-state H H
12 H L L Data Wait Data Read In-Data L H
13 H L H Data Wait Last Transfer In-Data L L
14 H L X Last T ransfer Clean Up In-X H H
15 H L X Clean Up Data Read In-X H H
16 H L X Tri-state (Address 1) Auto-turnaround Tri-state H H
17 H L L Tri-state (Address 2, Auto-turn-
around, Data Read, or Data Wait) Data Read In-Data L H
18 H L H Tri-state (Address 2, Auto-turn-
around, or Data Wait) Last Transfer In-Data L L
19 H L X Tri-state (Last Transfer, Clean Up) Data Read In-X H H
20 H L X Tri-state (Auto-turnaround Wait) Auto-turnaround Tri-state H H
21 H H X Addre ss 1, Tri-sta t e (Add r e s s 1,
Auto-turnaround Wait) Auto-t urnaround Wait In -X H H
22 H H X Addre ss 2, Auto-tu r na ro und, Dat a
Read, Data Wait, Clean Up, Tri-
state (Auto-turnaround, Address2,
Data, Data Wait, Last Tra nsfer, or
Clean Up)
Data Wait In-X H H
23 H H X Last Transfer Clean Up In-X H H
144 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
A sequence diagram for a typical DMA burst-mode read transfer
using th e Port2 read state table (T able 34) is shown in Figure 54.
This diagram includes a wait state.
FIGURE 54.Port2 DMA burst-mod e Read transfer with a Wa it st ate
Figure 54 is ident ical to F igure 45 on p age 119 , with the follo w-
ing exceptions:
1. All signal name s bear a P2 prefix instea d of P1.
2. The P2AD bus is only16 bits.
3. There are no HalfWord Enable signals, but there are P2AI
[3:0] signals.
4. Port2 has a P2QBRST output and has no COMMSEL
input.
The seque nce of st ate s i s i de nti ca l t o t hat s hown i n c onj unct io n
with Figure 45 on page 119, and the same explanatory text
applies.
CLK
P2END_
P2TRDY_
P2ASEL_
P2RQ_
P2QBRST
P2RD
14 2 4 7 9 22 12 9 9 10 14 1 1
P2QRQ_
P2IRDY_
D3
P2ADin[15:0]
ADR
D0 D1 D4
QRQ_ reasserts if another DMA enters port queue
P2ADout[15:0]
Next state is determined by table line #
LTN (Internal)
State LTX CU ADR1 ATA RD RD RDW RD RD RD LTX CU TRI
D5
If read
If write If write
D2
P2AI[3:0] If read A[3:0] A+1 A[3:0] + 2 A+3 A+4 A[3:0] + 2
MXT3010 Reference Manua l Version 4.1 145
Port Operations
A second sequence diagram for a typical DMA burst-mode read
transfer using the Port2 read state table (Table 34) is shown in
Figure 55. This diagram does not include a wait state.
FIGURE 55.Port2 DMA burst-mod e Read transfer without a Wait state
Figure 55 i s identical to Fi gure 46 on page 122, with the follo w-
ing exceptions:
1. All signal name s bear a P2 prefix instea d of P1.
2. The P2AD bus is only16 bits.
3. There are no HalfWord Enable signals, but there are P2AI
[3:0] signals.
4. Port2 has a P2QBRST output and has no COMMSEL
input.
The seque nce of st ate s i s i de nti ca l t o t hat s hown i n c onj unct io n
with Figure 46 on page 122, and the same explanatory text
applies.
CLK
P2END_
P2TRDY_
P2ASEL_
P2RQ_
P2QBRST
P2RD
14 2 4 7 9 9 9 9 10 14 1 1
P2QRQ_
P2IRDY_
D3
P2ADin[15:0]
ADR
D0 D1 D4
QRQ_ reasserts if another DMA enters port queue
P2ADout[15:0]
Next state is determined by table line #
LTN (Internal)
State LTX CU ADR1 ATA RD RD RD RD RD LTX CU TRI
D5
If read
If writ e If write
D2
P2AI[3:0] If read A[3:0] A+1 A+2 A+3 A+4 A[3:0] + 2
146 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
Port2 DMA burst-mode write transfers
Table 35 shows the state table for Port2 DMA burst-mode write
transfers and Figure 56 shows a sequence diagram for a Port2
DMA burst-mode write transfer. Table 35 is identical to
Table 27 on page 126. The inputs, outputs, and states are the
same as those described in “Inputs” on page 113, “Outputs” on
page 114, and “States” on page 114, with four exceptions:
1. All signal name s bear a P2 prefix instea d of P1.
2. The P2AD bus is 16 bits; the P1AD bus is 32 bits (and has
HalfWord Enable signals).
3. Only Port1 has a COMMSEL input.
4. Only Port2 has a P2QBRST output.
MXT3010 Reference Manua l Version 4.1 147
Port Operations
TABLE 35. State table for the Port2 DMA burst write state machine
A sequence di agram for a t ypi cal DMA burst-mod e wri te tr ans -
fer using Table 35 is sh own in Figur e 56. This diagr am includes
a wait state.
Table Line
Input
Signals
Current State Next State
Outputs in the
Next State
ASEL_
TRDY_
LTN
P1AD
IRDY_
END_
1 L H X Any Tri-state (current_state) Tri-state
2 L L X Any Address Out-Addr H H
3 H L L Address Data Write Out-Data L H
4 H L H Address Last Transfer Out-Data L L
5 H L L Data Write Data Write Out-Data L H
6H L H Data Write Last Transfer Out-Data L L
7 H L L Data Wai t Data Write Out-Data L H
8 H L H Data Wai t Last Transfer Out-Data L L
9 H L X Last Transfer Clean Up Out-X H H
10 H L X Clean Up Idlea
a. The Idle state will be maintained indefinitely if there is no RQ_ assertion.
Tri-state H H
11 H L L Idle, Tri-state (Address, Data
Write, or Data Wait) Data Write Out-Data L H
12 H L H Tri-state (Address, Data Write, or
Data Wait) Last Transfer Out-Data L L
13 H L X Tri-state (Last Transfer, Clean Up) Data Write Out-X H H
14 H H X Address, Data Write, Data Wait,
Clean Up, Tri-state (Address, Data
W rite, Data Wait, Last T ransfer, or
Clean Up)
Data Wait Out-X H H
15 H H X Last T ransfer Clean Up Out-X H H
148 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
FIGURE 56.Port2 DMA burst-mod e write transfer with a Wait state
The seque nce of states in Figu re 56 is the same as that for
Figure 47, “Port1 DMA Write transfer with a Wait st ate,” on
page 127, and the same explanatory text applies.
CLK
P2END_
P2TRDY_
P2ASEL_
P2RQ_
P2QBRST
P2RD
9 2 3 5 14 7 5 5 6 9 1 1
P2QRQ_
P2IRDY_
D3
P2ADin[15:0]
A[19:4] D0 D1 D4
QRQ_ reasserts if another DMA enters queue
P2ADout[15:0]
A+3
A+1 A+4
A[3:0]+2
P2AI[3:0]
Next state is determined by table line #
LTN (Internal)
State LTX CU ADR WD WD WDW WD WD WD LTX CU TRI
D5
A+5
If read
If writ e If write D2
A[3:0]
MXT3010 Reference Manua l Version 4.1 149
Port Operations
A sequence di agram for a t ypi cal DMA burst-mod e wri te tr ans -
fer usi ng Table 3 5 is shown in Figure 56. This dia gram does not
include a wait state.
FIGURE 57.Port2 DMA burst-mod e write transfer without a Wa it state
The seque nce of states in Figu re 57 is the same as that for
Figure 48, “Port1 DM A W rite t ransfer without a Wait state,” o n
page 130, and the same explanatory text applies.
CLK
P2END_
P2TRDY_
P2ASEL_
P2RQ_
P2QBRST
P2RD
9 2 3 5 5 5 5 6 9 1 1
P2QRQ_
P2IRDY_
D3
P2ADin[15:0]
A[19:4] D0 D1 D4
QRQ_ reasserts if another DMA enters queue
P2ADout[15:0]
A+3
A+1 A+4
A+2
P2AI[3:0]
Next state is determined by table line #
LTN (Internal)
State LTX CU ADR WD WD WD WD WD LTX CU TRI
D5
A+5
If read
If write If write D2
A[3:0]
150 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
Port2 DMA non-burst-mod e read transfers
Ta ble 36shows the state table for Port2 DMA non-burst-mode
read transfers and Figure 59 shows a sequence diagram for a
Port2 DMA non-burst-mode read transfer.
TABLE 36. State table for the Port2 DMA non-burst-mode read state machine
Table Line
Input
Signals
Current State Next State
Outputs in the Next State
ASEL_
TRDY_
LTNa
a. For non-burst-mode operation, the LTN (Last Transfer Next) signal is asserted when the pro-
grammable wait-timer expires. See “#waits [2:0]” in Table 31, “Port2 non-burst DMA instruc-
tion bit mapping,” on page 139.
P2AD
IRDY_
P2AI[3:2]
P2RD_
P2ALE_
END_
1 L H X Any Tri-state (current_state) Tri-state
2 L L X Any Address1 Out-Addr H Vb
b. The P 2A I [3:2] o u t pu ts ha ve va lid ( V ) addr e ss info rm ation on them thro ug ho ut all s t a te s m a rke d
“V”. These outputs can be decoded to form four chip selects if desired.
LHH
3 H L X Address1 Address2 Out-Addr L V L H H
4 H L X Address2 Address Hold Out-Addr L V L L H
5 H L X Address Hold Data Wait In-X L V L L H
6H L L Data Wait Data Wait In-X L V L L H
7 H L H Data Wai t Last Transfer In-Data L V L L L
8 H L X Last Transfer Clean Up In-X H V L L H
9 H L X Clean Up Idlec
c. The Idle state will be maintained indefinitely if there is no RQ_ assertion.
Tri-stateHVLLH
10 H H XData Wait Data Wait In-X HXXXH
MXT3010 Reference Manua l Version 4.1 151
Port Operations
A sequence diagram for a DMA non-burst-mode read transfer
using Table 36 is shown in Figure 58.
FIGURE 58.Port2 DMA non-burst-mode Read transfer.
Note:Dur ing a Port2 Non-Burs t DM A Read, an external devi ce places
data on the P2AD l eads. The Port2 DMA Read command can spec-
ify, vi a bits [10:8] of th e rsa register, the number of wait states that
occur before the MXT3010EP samples the data. In the example
shown above, 5 wait states have been inserted.
Figure 58 shows the Last Transfer (LTX) and Clean Up (CU)
states of a previous DMA r ead or write t ransfer. During the Last
Transfer state, the external logic that controls the ASEL_ and
TRDY_ leads makes a decision as to whether it should:
CLK
P2END_
P2TRDY_
P2ASEL_
P2RQ_
P2QBRST
P2RD
--- 2 3 4 5 6 6 6 6 7 9 1 1
P2QRQ_
P2IRDY_
P2ADin[15:0]
QRQ_ reasserts if another DMA enters port queue
P2ADout[15:0]
Next state is determined by table line #
LTN (Internal)
State LTX CU AD1 AD2 ADH RDW RDW RDW RDW RDW LTX CU TRI
If read
If write If write
P2AI[3:2] If read ADR[17:16]
ADR[15:0]
P2AI[1]/P2RD_
P2AI[0]/P2ALE_
Data
152 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
1. Prepare for another DMA transfer (having detected
P2QRQ_ asserted)
2. Relinquish the bus by entering a tri-state condition
3. Perform some other type of bus operation
Having decided on the appropri ate course of action, the external
control logic conditi ons ASEL_ and TRDY_ at the beginning of
the Clean Up state so that the Port2 state machine will enter the
desired state after the Clean Up state.
In this example, a non-burst read transfer is performed. During
the Clean Up st ate, both ASEL_ and TRDY_ are lo w , and li ne 2
of the state table indicates that the next state is Address 1 (AD1).
During Addr ess 1, t he ASEL_ lead is driven high, and l ine 3 of
the state table indicates that the next state is Address 2 (AD2).
In the Address 2 state, the ASEL_ lead is still high and the
TRDY_ lead is still low. Line 4 of the state table indicates that
the next state is Address Hold (ADH). At this time, the P2AI [0]
output, functioning as Address Latch En able (ALE_) transitions
from high t o low , perf orming the addr ess latching func tion char-
acteristic of asynchronous, multiplexed busses.
During Address 1, Address 2, and Address Hold, the
P2AD[15: 0] leads carri ed the lowest order 16 bits of the desired
address. P2AI[3:2]carried bits A[17:16] during the three address
states and also carry those bits throughout the DMA transfer.
Thus, they can used as chip selects if desired. P2AI[1] creates an
inverted version of P2RD (P2RD_) to provide a glueless inter-
face on the P2 bus.
During the Address Hold state, the ASEL_ lead is still high and
the TRDY_ lead is still low , and line 5 of the state table indicates
that t he next s tat e is Data Wait. As indi cat ed by line s 6 and 7 of
the state table, the Data Wait condition persists until the wait
MXT3010 Reference Manua l Version 4.1 153
Port Operations
timer (set by rsa[10:08]) e xpires. Expiration of the wait timer
assert s LTN, and line 7 of the sta te table i ndicat es the ne xt stat e
is Last Transfer (LTX).
As with all of the other DMA transfer types discussed, Last
Transfer is followed by Clean Up; during Last Transfer the
external arbiter selects conditions for ASEL_ and TRDY_ that
determin e the bus activity after the Cle an Up state. In Figure 58,
ASEL_ is low and TRDY_ is high during the Clean Up state,
and line 1 of the state table indicates the next state is Tri-state.
It is also possible that ASEL_ could be retained high and
TRDY_ could be reta ined low. In th at case, the bus would enter
an Idle state during which the data leads would be tri-state, but
the control leads would still be in their previous state.
154 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
Port2 DMA non-burst-mode write transfers
Table 37s hows the state ta ble for Port2 DMA burs t- mode wr it e
transfers and Figure 60 shows a sequence diagram for a Port2
DMA burst-mode read transfer.
TABLE 37. State table for the Port2 DMA non-burst-mode write state machine
Table Line
Input
Signals
Current State Next State
Outputs in the Next State
ASEL_
TRDY_
LTNa
a. For non-burst-mode operation, the LTN (Last Transfer Next) signal is asserted when the pro-
grammable wait-timer expires. See “#waits [2:0]” in Table 31, “Port2 non-burst DMA
instruction bit mapping,” on page 139.
P2AD
IRDY_
P2AI[3:2]
P2RD_
P2ALE_
END_
1L H X Any Tri-state (current_state) Tri-state
2L L X Any Address1 Out-Addr H Vb
b. The P 2AI [3:2] outputs have valid (V) address informa tion on them thr oughout a ll states
marked “V”. These outputs can be decoded to for m f our chip selec ts if desired.
HHH
3H L X Address1 Address2 Out-Addr L VHHH
4H L X Address2 Address Hold Out-Addr L V H L H
5H L X Address Hold Data Wait Out-Data L V H L H
6H L L Data Wait Data Wait Out-Data L V H L H
7H L H Data Wait Last Transfer Out-Data L V H L L
8H L X Last T ransfer Clean Up Out-X H V H L H
9H L X Clean Up Idlec
c. The Idle state will be maintained indefinitely if there is no RQ_ assertion.
Tri-state HVHLH
10 H H XData Wait Data Wait Out-DataHXXXH
MXT3010 Reference Manua l Version 4.1 155
Port Operations
A sequence diagram for a DMA non-burst-mode read transfer
using Table 37 is shown in Figure 59.
FIGURE 59.Port2 DMA non-burst-mode Write transfer.
Note:During a Port2 Non-Burst DMA Write , the MXT3010EP pla ces data
on the P2AD leads for at least one clock cycle. The Port2 DMA
Write command can specify, via bits [10:8] of t he rsa register, the
number of additional cy cles (wait states) du ring which the
MXT3010 holds the data on the bus. In the example shown above, 5
wait states have be en inserted in add ition to the minimum data asser-
tion period of one clock cycle.
The sequence of states shown in Figure 59 is exactly the same
as that s hown in Fig ure 58, excep t that this i s a writ e. The same
description applies, substituting writes for reads as necessary.
CLK
P2END_
P2TRDY_
P2ASEL_
P2RQ_
P2QBRST
P2RD
--- 2 3 4 5 6 6 6 6 7 9 1 1
P2QRQ_
P2IRDY_
P2ADin[15:0]
QRQ_ reasserts if another DMA enters port queue
P2ADout[15:0]
Next state is determined by table line #
LTN (Internal)
State LTX CU AD1 AD2 ADH WDW WDW WDW WDW WDW LTX CU TRI
If read
If writ e If write
P2AI[3:2] If read ADR[17:16]
ADR[15:0]
Write Data (See Note)
P2AI[1]/P2RD_
P2AI[0]/P2ALE_
156 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
Additional Port1 and Port2 Design Information
Arbitrating access to Port1
System configurations utilizing the MXT3010 often have a Host
processor installed on Port1. This allows the Host processor to
access the MXT3010 Communication I/O registers and to
access the SRAM. For example, consider the system shown in
Figure 60.
FIGURE 60.System exam ple for Port1 bus.
The functions of the Bus Controller are as follows:
1. In response to P1QRQ_ and P1RQ_,grant the MXT3010
access to the Memory, manipulating P1ASEL_ and
P1TRDY_ to step th e MXT3010 t hrough rea d (P1RD hi gh)
or write (P1RD low) DMA transfers as described in F igure
45 and Figure 47 respectively.
2. In response to bus request signals from the Host, grant the
Host access to the Memory or to the MXT3010 Communi-
cations I/O register, performing a read or write transfer as
requested by the Host.
MXT3010 Memory
Host
Bus
Controller
Port1
MXT3010 Reference Manua l Version 4.1 157
Additional Port1 and Port2 Design Information
3. An existing DMA transfer should not be interrupted. The
maximum MXT3010/Memor y trans fer is 255 bytes ( 64 bus
data cycles). It is recommended that the maximum Host/
Memory transfer also be 64 bus data cycles.
4. The Bus Controller may also include a Port1 to PCI bus
adapter if desired. Also, the Bus Controller may also
include M emory i nterface logic.
Simplified Port2 interfaces
When the MXT3010 is the only Port2 master, no arbitration
function is required. The following simplified interfaces can be
implemented:
A single master
burst-mode
interface
Logic t o manipu la te P2 AS EL_ a nd P2TRDY_ can be buil t into
the slave device attached to Port2. In this configuration,
P2TRDY_ may be tied low if generation of Data Wait states is
not required. When there is no bus activity, P2ASEL_ should
also be held low. Once the slave device samples RQ_ as low, it
samples the DMA address from P2AD and P2AI and drives
P2ASEL_ high on the same or any subsequent clock edge.
Once P2 ASEL_ is high, t he subsequent cycl es follow the Table
34 or Table 35 sequenc es as determined by the state of RD (r ead/
write). As with multi-master bus configurations, P2END_ low
delineates the last halfword transfer . P2ASEL_ should be driven
low when P2END_ is sampled low . P2ASEL_ must be held low
until the next DMA.
A non-burst-only
interface P2ASEL_ can be tied high and P2TRDY_ can be tied low . Once
RQ_ is low, the state machine begins operation and the slave
device receives the DMA address from P2AD and P2AI. The
slave de vice sample s the addr ess on the falling edge of P2AI[0] /
P2ALE_. Subsequent bus cycles follow the T able 36 or T able 37
sequences as determined by the state of RD (read/write).
158 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
Bus driving , turn around, and bu s parki ng
The port i nterfac es c an op erate in a shar ed bu s e nvi ron me nt. In
such an environment, the following port interface signals are
shared between all devices on their respective busses:
To prevent bus cont ention on shared por t int er fa ce signal s, port
interface controllers should create a tri-state cycle between the
times the MXT3010EP and another device drive the bus. In
addition, to prevent the bus from floating indefinitely , port inter-
face controllers must ensure the bus is driven when there is no
device performing transfers on the bus. This can be done, for
example, by placing the MXT3010EP into address mode. The
MXT3010 enters address mode on the rising edge of clock when
ASEL_ is low, TRDY_ is low, and (for Port1) COMMSEL is
low.
Speeding up
transfers Many of the timing diagrams for Port1 and Port2 interfaces
show PxASEL_ switching one clock period after PxRQ_ is
assert ed t o s el ect th e data phas e. I f t he MXT30 10 i s being use d
in a system tha t does not need to tri-state the bus, PxASEL_ can
be negated at the same time PxRQ_ is asserted if PxTRDY_ is
asserted (bus parked). This speeds up Port cycles by one clock
period. This process is described in more detail in “Port2 bus
parking” on page 158.
Port2 bus parking While the following text describes bus parking on Port2, Port1
bus parking oper at es si mi la rl y.
Port 1 Port 2
P1AD[31:0] P2AD[15:0]
P1END_ P2END_
P1RD P2RD
P1IRDY_ P2IRDY_
P1HWE[1:0]
MXT3010 Reference Manua l Version 4.1 159
Additional Port1 and Port2 Design Information
When the MXT3010 is the only Port2 Master , the device may be
parked on the bus. Parking minimizes bus handshaking over-
head. While the MXT3010 is parked, it actively drives the
P2AD pins.
In a bus parking configuration, P2TRDY_ may be tied low.
During p eriods of no bus acti vity, P2ASEL_ s hould also be held
low. Once the P2 Slave dev ice sa mples P2RQ_ lo w, it sa mple s
the DMA address from P2AD and P2AI and drives P2ASEL_
high on the same or any subsequent clock edge.
Once ASEL_ is deasserted, the MXT3010 drives valid data on
subsequent cycles. As with non-parked bus configurations,
P2END_ low delineates the last halfword transfer. P2ASEL_
should be dr iven low when P2END_ is sampl ed low. P2ASEL_
Data Alignment
The MXT3010 can begin Port1 reads on odd byte boundaries
and can begin Port1 writes on odd halfword boundaries. The
reads always appear (on the bus) to be word reads where the
internal Port1 hardware shifts the data appropriately for the byte
address. Although A1 and A0 represent the byte address, they
can be, and usually are, ignored by external hardware. On
writes, the P1HWE1 and P1HWE0 signals determine which half
of the word is being written on 32-bit boundaries, halfword
enabled. The MXT3010 takes care of any shifting/swapping.
DMA transfers i n bur st mode cause one or mo re data cyc le s on
the bus . Each cycle can t ransf er fo ur byt es (Po rt1) or t wo bytes
(Port2) . On r ea ds, t he MXT3 010 c an s ta rt at an odd b yte (o r i n
the case of Port1, an odd halfword) where it internally deter-
mines which bytes are important and performs lane switching
(shift ing). On wri tes, the MXT3010 can only wri te on half word
boundaries and an even number of bytes due to the halfword-ori-
ented writ e enable s. The last byt e written for an odd byte tr ans-
160 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
fer may be ignored if the transfer desired an odd byte size, but
the last byte transfer will be written. Thus, the number of data
cycles for fo ur byte s may be one o r two bu s data cycles depend -
ing on the byte alignment.
MXT3010 Reference Manua l Version 4.1 161
Transfer complete
Transfer complete
A DMA transfer can conclude for either of two reasons:
• The byte count (BC/#) has reached zero
• The P1ABORT_ signal has been asserted (Port1 only)
Byte Count zero
Standard end
timing For both Port1 and Port2, END_ is asserted during the data cycle
that presents the final data on the bus. The DMA cycle con-
cludes with a “cleanup” cycle.
FIGURE 61.DMA Read transfer with standard END_ signal
CLK
P1END_
P1TRDY_
P1ASEL_
P1RQ_
COMMSEL
P1RD
14 2 4 7 9 9 9 9 10 14 1 1
P1QRQ_
P1IRDY_
P1ADin[31:0]
ADR
D0 D1 D4
QRQ_ reasserts if another DMA enters queue
P1ADout[31:0]
11
11
11
P1HWE[1:0]
1
0 or 1 1
Next state is determined by table line #
LTN (Internal )
State LTX CU AD1 ATA RD RD RD RD RD LTX CU TRI
D5
01 or 11
01 or 11
If read
If write If write
D2 D3
11
162 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
Early end option Mode bits (bit 6 and bit 7) in the Mode Configuration register
(R42) enable an early end option for each port. When enabled,
the End signal asserts concurrent with the request for the next-
to-last data cycle. External circuitry must qualify this signal with
the appropriate control signals (ASEL_ and TRDY_) to deter-
mine that a data cycle is present on th e bus. This ensures that the
external controller recognizes the actual end condition and not
that the current clock cycle is a wait state.
FIGURE 62.DMA Read transfer with Early END
Note: External logic must ensure that ASEL_ is high and TRDY_ is low
when END_ is asserted (low). If TRDY_ is high (shown by dash ed
lines), a Wait st ate is indicated and the last data cycle of the DMA
transfer cycle is extended beyond the length indicated. For normal end
conditio ns th is is un im po rta n t, b ut if a de sign is re lyin g up on a n “e arl y
end”, this condition is important.
CLK
P1END_
P1TRDY_
P1ASEL_
P1RQ_
COMMSEL
P1RD
14 2 4 7 9 9 9 9* 10 14 1 1
P1QRQ_
P1IRDY_
P1ADin[31:0]
ADR
D0 D1 D4
QRQ_ reasserts if another DMA enters queue
P1ADout[31:0]
11
11
11
P1HWE[1:0]
1
0 or 1 1
Next state is determined by table line #
LTN (Internal )
State LTX CU AD1 ATA RD RD RD RD RD LTX CU TRI
D5
01 or 11
01 or 11
If read
If write If write
D2 D3
11
Note
*While line 9 of the state table indicates the END_ output is high in the next state, enabling the Early End option
allows the LTN signal to assert P1END_ immediately.
MXT3010 Reference Manua l Version 4.1 163
Transfer complete
External DMA cycle abort (P1ABORT_)
The MXT3010 has an input signal (P1ABOR T_) that permits an
external device to indicate an early termination of a DMA read
operation from Port1 memory. During a DMA Read operation
on Port1, assertion of the P1ABORT_ signal termina tes the read
with the data in th e following cycle. For example, asserting
P1ABORT_ during the fifth data phase of a DMA burst termi-
nates the operation after the sixth data phase has completed. The
action of P1ABORT_ is similar to that of the internal signal
LTN, except that when a tr ans fe r is term ina te d by P1ABORT_,
no P1END_ assertion occurs.
FIGURE 63.DMA Read transfer terminated by P1ABORT_
During a DMA Write operation on Port1, assertion of the
P1ABOR T_ signal terminates the write of the data in the follow-
ing cycle.
CLK
P1END_
P1TRDY_
P1ASEL_
P1RQ_
COMMSEL
P1RD
14 2 4 7 9 9 9 9 10* 14* 1 1
P1QRQ_
P1IRDY_
P1ADin[31:0]
ADR
D4
QRQ_ reasserts if another DMA enters queue
P1ADout[31:0]
11
11
11
P1HWE[1:0]
1
0 or 11
Next state is determined by table line #
P1ABORT_
State LTX CU AD1 ATA RD RD RD RD RD LT X* CU TRI
D5
01 or 11
01 or 11
If read
If write If write
D2 D3
11
*The state table does not show the effects of P1ABORT_. The effects are equivalent to LTN, which is shown in the
state table (with the line numbers cited here), with the exception that no END_ assertion occurs.
D0 D1
164 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
Endian-ness
Within modern computer systems, there are two ways of
addressing a multi-byte data value such as (hex) ABCD:
FIGURE 64.Most Significant Byte is the Lowest Address (“Big-endian”)
FIGURE 65. Least Significant Byte is the Lowest Address (“Little-
endian”)
The mapping i n Figure 64 stor es the most signi ficant byte in t he
lowest numeric byte address. The mapping in Figure 65 stores
the least significant byte in the lowest numeric byte address;
These methods are commonly referred to as “big-endian” and
“little-endian” respectively.
If a processor that uses big-endian or little-endian addressing
accesses the data shown Figure 64 and Figure 65 on a word
basis, t he entire 32 -bit quanti ty ABCD is accesse d, and no prob -
lems result. However, processsors that use big-endian address-
ing receive different results than those using little-endian
addressing when making word or byte accesses. See Table 38.
Data: A B C D
Address: 0123
Data: A B C D
Address: 3210
MXT3010 Reference Manua l Version 4.1 165
Endian-ness
TABLE 38. Comparison of Big-endian and Little-endian Read
Operations
A convenient method of dealing with this problem is to use the
swapping instructions available in little-endian processors in
combination with a hardware byte-swapper. A byte-swapper,
imple ment ed in hardwa re, in shown in Figure 66.
FIGURE 66.Hardwa re Byte-swapping Circuit
Figure 67 shows what happens when the hardware byte-swapper
is used i n conjunction with a softwar e instructi on that swaps the
bytes on a word basis within the little-endian processor.
Access Bi g-Endian Result Lit tle-Endia n Result
32-bit ABCD ABCD
16-bit xxx0 AB CD
16-bit xxx2 CD AB
byte xxx0 A D
byte xxx1 B C
byte xxx2 C B
byte xxx3 D A
Big-endian processor
AB CD
0
A
B
CD
0
Little-endian processo r
Hardware
123
321
166 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
FIGURE 67.Word Access
The combina ti on of hardware a nd so ft ware shown in Figure 67
produces the s ame res ult as sh own in Table 38 on page 165, th e
first line of which (in an expande d form) is repro duced in Table
39.
TABLE 39. Accesse s With Hardware and Software Swaps, 32-bit
At first glance, this appears to be a waste of hardware and soft-
ware. However , the results for halfword (16-bit) and byte (8-bit)
operations are more interesting.
Big-endian processor
AB CD
0
A
B
CD
0
Little-endian processo r
Hardware
CD
0
Software
123
321
1
2
3
B
A
Access Big-Endian
Result Little-Endian
Result Result after H/W-S/W
Swaps
32-bit ABCD ABCD ABCD
MXT3010 Reference Manua l Version 4.1 167
Endian-ness
FIGURE 68.16-bi t xxx0 Access
FIGURE 69. 16-bit xxx2 Access
The combinations of hardware and software shown in Figures
68 and 69 produce Table 40.
Big-endian processor
AB CD
0
A
B
CD
0
Little-endian processo r
Hardware
AB
0
Software
123
321
1
2
3
Big-endian processor
AB CD
0
A
B
CD
0
Little-endian processo r
Hardware
CD
0
Software
123
321
1
2
3
168 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
TABLE 40. Accesses With Hardware and Software Swaps, 32-bit and 16-bit
FIGURE 70.Byte Access
The combina ti on of hardware a nd so ft ware shown in Figure 70
produces Table 41.
TABLE 41. Accesses With Hardware and Software Swaps, 32-bit, 16-bit, and 8-bit
As indicat ed in Table 41, the combina tion of the hardware byte -
swapper and byt e swapping ins tructio ns within the l ittle-endi an
processor allow the little-endian processor to access information
in the big-endian system and receive consistent results.
Access Big-Endian Result Little-Endian Result
Per Table 38 Result after H/W-S/W Swaps
32-bit ABCD ABCD ABCD
16-bit xxx0 AB CD AB
16-bit xxx2 CD AB CD
Big-endian processor
AB CD
0
A
B
CD
0
Little-endian processo r
Hardware
123
321
Access Big-Endian Result Little-Endian Result
(Per Table 38) Result after H/W-S/W Swaps
32-bit ABCD ABCD ABCD
16-bit xxx0 AB CD AB
16-bit xxx2 CD AB CD
byt e xx x0 A D A
byt e xx x1 B C B
byt e xx x2 C B C
byt e xx x3 D A D
MXT3010 Reference Manua l Version 4.1 169
Port1 and Port2 Reference Designs
See “Endian Implementation in P1MemMaker” on page 171
and “Endian Implement ation in P2MemMaker” on page 174 for
examples of endian treatment in reference designs.
Port1 and Port2 Reference Designs
P1MemMaker
The MXT3010EP Por t1 inter fa ce re quires a me mory con tr oller
function to support bus arbitration, bus selection, bus driving,
bus turnaround, and bus holding operations. In Maker’s
MXT3025 evaluation Board and similar designs, Maker uses
P1MemMaker, a device that is a in tegrated memory system con -
troll er , inte grated PCI in terface , COMMIN/COMMOUT Regis-
ter, and MXT3010EP Port 1 inte rface . It pe rforms the f ollowi ng
functions:
• Memory System Controller
The Memory System Controller (MSC) provides the bus
arbitration and selection functions for the PCI or Port1
acces s for tra nfers to shared memory. It control s up to 4
Mbytes of shared DRAM. The typical memory system is
organized as 1Mx32 and implemented with two (2) 1Mx16
EDO DRAMs. The memory system is usually mapped into
the PCI memory sp ace and mapped i nto the lowe r 4 Mbytes
of the MXT3010EP Port1 address space. The MSC sup-
ports full speed burst transfers of up to 256 bytes to the
memory system, but transfers must not cross 4-Kbyte
boundaries. Also, the MSC controls the resetting and boot
loading of the MXT3010EP through a 128 Kbyte boot
PROM.
170 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
• PCI Interface
The PCI bus interface is a 32-bit, 33 Mhz PCI Version 2.1
implementation supporting the PCI configura tion registers, a
slave-onl y interface, and no support for initiating trans fers
from the host processor to shared memory or the
MXT3010EP device.
• COMMIN/COMMOUT Register
The P1MemMaker also controls communications between
the MXT3010EP COMMIN/COMMOUT register and the
PCI host. The CINBUSY, COUTRDY, and COMMSEL sig-
nals are connected to the P1MemMaker. Typically the PCI
host communicates to code running in the MXT3010EP via
commands passed through the MXT3010EP’s COMMIN
register. The code running in the MXT3010EP communi-
cates to the PCI host via commands passed through the
MXT3010EP’s COMMOUT register, writing to command
responses and to indication queues. The COMMIN/COM-
MOUT register (32-bits) thus provides the two-way com-
munications. Details of CINBUSY and COUTRDY
operation are provided in Chapter 8 of the MXT3010 Refer-
ence Manual .
• MXT3010EP Port1 interface
The Port1 Controller is a 32-bit multiplexed address and
data bus operating at 50 Mhz supporting MXT3010EP
accesses to shared memory.
Maker’s P1MemMaker reference design is available through the
WEB under the "Hardware Development Tools" page and pro-
vides the following verilog files:
•arbiter.v
This module defines the memory arbiter.
MXT3010 Reference Manua l Version 4.1 171
Port1 and Port2 Reference Designs
•dp.v
This module defines the data paths.
• dram_cntrl.v
This module defines the DRAM controller.
•p1orca.v
This module defines the top level of P1MemMaker
• p1ctrl.v
This module defines the Port 1 A/B controller.
•pci_be.v
This module defines the PCI back end controller with CSR.
Endian
Implementation in
P1MemMaker
Several Maker products utilize the Port1 MemMaker FPGA to
allow the MXT3010 and a PCI bus to share a Port1 memory.
Within Port1 MemMaker, the address and data information on
the time-multiplexed Port1 and PCI busses are registered, and
the data leads are transposed as shown in Figure 72. No lead
transpositions are performed on the address information.
FIGURE 71.The Port1 MemMaker FPGA
D C B A
P1
MemMaker
A B C D
A B C D
Host (Little-endian)
MXT3010 (Big-endian)
PCI Bus
Port1 Bus
Shared Memory
(Big-endian)
172 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
FIGURE 72.Data Path Connections - Shared Memory to PCI
FIGURE 73.Data Path Connections - Shared Memory to MXT3010
P2MemMaker
The MXT3010EP Por t2 inter fa ce re quires a memory contr oll er
function to support bus arbitration, bus selection, bus driving,
bus turnaround, and bus holding operations. In Maker’s
MXT3025 evaluation Board and similar designs, Maker uses
P2MemMaker, a device that is a in tegrated memory system con -
troll er, a PCI interf ace , and an MXT3010EP Port2 int er fac e. It
performs the following functions:
• Memory System Controller
The Memory System Controller (MSC) provides the bus
arbitration and selection functions for the PCI or Port2
acces s for tra nfers to shared memory. It controls up to 2
Mbytes of shared SRAM. The typical memory system is
organized as two (2) 64kx16 SRAMs. The memory system
is typi call y mapped into the PCI memory s pace a nd ma pped
AB C D
A
B
CD
Port1 Shared Memory
(Big-endian)
PCI Bus
(Little-endian)
P1 MemMaker
0
0
31
31
ABCD
D
C
BA
Port1 Shared Memory
(Big-endian)
MXT3010 Port1 Pins
(Big-endian)
P1 MemMaker
P1AD[31
]
P1AD[0
]
31 0
MXT3010 Reference Manua l Version 4.1 173
Port1 and Port2 Reference Designs
into the lower 256Kbyte s of the MXT3010 EP Port2 add ress
space. The MSC supports ful l speed burst tranfer s up to 256
bytes to the memory system, but transfers must not cross 4-
Kbyte boundaries. The MSC also controls transfers to the
non-burst memory space.
• PCI Interface
The PCI Bus interface is a 32-bit, 33 Mhz PCI Version 2.1
Implementation supporting the PCI configuration registers,
a slave onl y interf ace , and no s uppor t for in it ia ti ng t ra nsf er s
from the host p rocessor to shared memory or the
MXT3010EP device.
• Port2 Interface
The Port 2 Controller is a 16-b it multipli ed Address a nd Data
bus operating at 50 Mhz supporting MXT3010EP accesses
to shared memory.
Maker’s P2MemMaker reference design is available through the
WEB under the "Hardware Development Tools" page and pro-
vides the following verilog files:
• mem_cntrl.v
This module defines the SRAM controller.
•p2_arbiter.v
This module defines the memory arbiter.
• p2_dp.v
This module defines the data paths.
• p2_ORCA.v
• p2_pci_be.v
This module defines the PCI back end controller.
• p2ctrl.v
174 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
This module defines the Port 2 Rx/Tx controller.
Endian
Implementation in
P2MemMaker
Several Maker products utilize the Port2 MemMaker FPGA to
allow the MXT3010 and a PCI bus to share a Port2 memory.
Within the Port 2 MemMaker, the address and data informatio n
on the time-multiplexed Port2 and PCI busses are registered,
and the d ata leads are transposed as shown in Figure 75. No lead
transpositions are performed on the address information.
FIGURE 74.The Port2 MemMaker FPGA
FIGURE 75.Data Path Connections - Shared Memory to PCI
B A
P2
MemMaker
A B
A B
Host (Little-endian)
MXT3010 (Big-endian)
PCI Bus
Port2 Bus
Shared Memory
(Big-endian)
AB
A
B
Port2 Shared Memory
(Big-endian)
PCI Bus
(Little-endian)
P2 MemMaker
31
31 0
0
MXT3010 Reference Manua l Version 4.1 175
Port1 and Port2 Reference Designs
FIGURE 76.Data Path Connections - Shared Memory to MXT3010
AB
B
A
Port2 Shared Memory
(Big-endian)
MXT3010 Port2 Pins
(Big-endian)
P2 MemMaker
P2AD[15
]
P2AD[0
]
31 0
176 Version 4.1 MXT3010 Reference Ma nual
The Port1 and Port2 Interfaces
MXT3010 Reference Manua l Version 4. 1 177
CHAPTER 8 Communications
Host/MXT3010 communications include the COMMIN/COM-
MOUT regist er and t he eight pins the MXT3010 as signs fo r inter -
chip communications. This chapter describes the communications
functions of the COMMIN/COMMOUT register and inter-chip
signalling pins.
Data
Stream
Cell
Stream
Multi-purpose
DMA (Port2)
UTOPIA
Port
Cell Buffer RAM High
Performance
DMA (Port
Data
Stream
Instruction Cache
SWANTM Processor
Fast Memory
Controller
Cell Scheduling
System
Control
Memory
SRAM
Inter-chip
Signalling
178 Version 4.1 MXT3010 Reference Ma nual
Communications
The COMMIN/COMMOUT register
The MXT3010 device implements a two-way communications
channel with the host processor. The communication channel
consists of a 32-bit COMMIN/COMMOUT register imple-
mented as a set of two 16-bit registers, R40 [31:16] and R41
[15:0]. Accessing the COMMIN/COMMOUT register via
Port1, the host processor uses the register as a COMMIN regis-
ter to write information (commands/status/addresses) into the
device, an d as a COMMOUT regist er to read in for m at ion fro m
the device.
CIN_BUSY and
COUT_RDY The MXT30 10 device implements two output si gnals that allow
both the hos t and t he SWAN p rocess or to deter mine the st ate of
the COMMIN/COMMOUT register set. Definitions for these
signals ar e provided in Table 42, and ti ming for the se signals i s
shown in Figure 77 on page 180.
Register Function
COMMIN Host to MXT3010 communic ations
COMMOUT MXT301 0 to ho s t com m un ic a tio ns
TABLE 42. Definitions of CIN_BUSY and COUT_RDY
Signal Function
CIN_BUSY The CI N_BUSY sign al is used for host to MXT3010
communications (R40/R41 used as COMMIN).
1 T he host has written information into R40/R41
that has not yet been read by the SWAN processor .
0 The SWAN has read the information in R40.
COUT_RDY The COUT_RDY signal is used for MXT3010 to host
communications (R 40/R41 used as C O MMOUT).
1 The SWAN processor has written informa tion into
R40 that has not yet been re ad by the host.
0 T he host has read the information in R40/R41.
MXT3010 Reference Manua l Version 4.1 179
The COMMIN/COMMOUT register
As shown above, when the host processor writes to COMMIN
(R40/R41), CIN_BUSY is asserted until the SWAN processor
reads R40. Before writing the next word into the register R40/
R41, the host must be sure that the SWAN processor has pro-
cessed t he previ ous word. The host does this by t esting t he stat e
of CIN_BUSY. The state of CIN_BUSY is accessible to the
SWAN as ESS6.
When the SWAN processor writes to COMMOUT _HIGH
(R40), the COUT_RDY output is asserted until the host reads
the COMMOUT register . The COUT_RDY output is accessible
to the SWAN processor as ESS7. Therefore, the SWAN can
check that the host has read COMMOUT by testing ESS7.
Restrict ions o n
CIN_BSY and
COUT_RDY
Since reads and writes to R40 affect the CIN_BUSY and
COUT_RDY signals, the SWAN program should read or write
R41 before reading or writing R40 when performing 32-bit
communication. No such restriction applies to the host, as it uses
32-bit transfers that access R40 and R41 simultaneously. Since
R40 controls the flags, COMMOUT_LOW (R41) can be used
during debugging to pass data without affecting the flags.
The CIN_BSY flag is cleared when a nullified instruction
accesses the COMMIN_HIGH register (R40). Therefore, do not
place an instruction that accesses COMMIN_HIGH in a slot that
may be nullified. For more information on the nullify operator,
see “The Nullify operator” on page 265.
180 Version 4.1 MXT3010 Reference Ma nual
Communications
FIGURE 77.Timing of CIN_BUSY and COUT_RDY
Interchip communications
Besides the COMMIN/COMMOUT register, the MXT3010
dedicates eight pins for interchip communication: four input
pins, ICSI_[D:A], and four output pins, ICSO_[D:A].
The ICSI pins The input pins are listed in Table 43.
The appe ara n ce s of I CSI_A and I C SI_ B i n the ESS r egi st er a re
synchron ize d to th e MXT30 10 inpu t cl ock, but are not latched.
STATE
CLK
P1TRDY_
P1AD[31:0]
P1ASEL_
P1RQ_
COMMSEL
P1RD
DMA transfer COMMIN Write COMMOUT Read
OUT OUT
IN
DMA LAST DATA DATA
RQ_asserts if a DMA command enters the port active stage
Idle CIW CIS Idle CO1 CO2 CODV Idle
CIW = Comm In Write; CIS = Comm In Data Strobe; C01,2 = Comm Out Read1,2; CODV = Comm Out Data Valid
COUTRDY
CIN_BUSY
TABLE 43. ICSI pins
Pin I/O Connected to
ICSI_A Input Sparse Event/ICS register (R57) bit 12 (read)
External State Signals (ESS) register (R42) bit 0
ICSI_B Input Sparse Event/ICS register (R57) bit 13 (read)
External State Signals (ESS) register (R42) bit 1
ICSI_C Input Sparse Event/ICS register (R57) bit 14 (read)
ICSI_D Input Sparse Event/ICS register (R57) bit 15 (read)
MXT3010 Reference Manua l Version 4.1 181
Interchip communications
In contrast, the appearances of these bits in the Sparse Events/
ICS regist er (R57) includ e both a masking feature and la tching.
The appearances of ICSI[D:A] in the Sparse Events/ICS register
(R57) a re en abled by masking condi tions in t he Sys tem regist er
(R63). If enabled, e ach input is sampled by t he clock. I f t he s ig -
nal is asse rt ed for t wo s u cc ess iv e clock c ycl es , this c ondi tion is
latched until cleared by the SWAN processor.
The ICSO pins The output pins are listed in Table 44.
The output pins are sourced from four Sparse Event/ICS register
(R57) ou tputs. The SWAN processor can change the st ate of any
one of th e out put pi ns by chang ing t he st ate of the Sparse Event
register output bit associated with the pin.
Enabling the
ICSO pins The SWAN processor reads configuration information from
ICSO_(D:A) during reset. To ensure that the SWAN processor
does not drive these pins at reset, the pins are reset in input
mode. The SWAN processor senses configuration information
from them as it exits res et. To use th ese pin s as outputs, th e soft-
ware must enable these pins by setti ng the EN bit in the System
register (R63).
For more information on the Sparse Event/ICS register, see
“R57-read Spar se Event/ICS register” on page 213 . For more
informat ion on the Syst em r egi st er, see “R63 The System reg is -
ter” on page 221.
TABLE 44. ICSO pins
Pin I/O Connected to
ICSO_A Output Sparse Event/ICS register (R57) bit 12 (set/clear)
ICSO_B Output Sparse Event/ICS register (R57) bit 13 (set/clear)
ICSO_C Output Sparse Event/ICS register (R57) bit 14 (set/clear)
ICSO_D Output Sparse Event/ICS register (R57) bit 15 (set/clear)
182 Version 4.1 MXT3010 Reference Ma nual
Communications
MXT3010 Reference Manua l Version 4.1 183
Section 2 Register and
Instruction
Reference
This secti on includes regis ter description s and the SWAN instruc-
tion set.
Registers
The register descriptions are organized by location, starting with
the regi ster file in loca tions R(31:0) a nd continuing with reg isters
R32 through R63. A table is provided that includes the register
location, name, size, and whether it’s a read or write register.
Each register description includes the register location, bit map,
description, reset value, bit definitions, and notes.
Table 45 lists the registers.
184 Version 4.1 MXT3010 Reference Ma nual
TABLE 45. Hardware registers
Location Name Read/Write
R32 General Purpose - 0000 R/W
R33 General Purpos e - FF FF R/W
R34 General Purpos e - FF 00 R/W
R35 General Purpose - 0040 R/W
R36-Write The Bit Bucket W
R37 General Purpos e R/W
R38 General Purpos e R/W
R39 General Purpos e R/W
R40 COMMOUT/COMMIN(31:16) R/W
R41 COMMOUT/COMMIN(15:0) R/W
R42-Read ESS register R
R42-Write Mode Config uratio n re giste r Set/Clear
R43-Read Fast Memory Bit Swap register R
R43-Write UTOPIA TX Control FIFO register W
R44 CRC32PRX (15:0) R/W
R45 CRC32PRX (31:16) R/W
R46 CRC32PRY (15:0) R/W
R47 CRC32PRY (31:16) R/W
R48 rla Address register R/W
R49 rla Address register R/W
R50 rla Address register R/W
R51 rla Address register R/W
R52 Alternate Byte Count /ID register R/W
R53 Instruction Base Address register R/W
R54 Programmab l e Interval Timer (PIT0) R/W
R55 Programmab l e Interval Timer (PIT1) R/W
R56 The Fast Memory Data register R/W
R57-Read Sparse Event/ICS register R
R57-Write Sparse Event/ICS register Set/Clear
R58 Fast Memory Shadow register R/W
R59 Branch register R/W
R60 CSS Configuration register R/W
R61-Read Scheduled Address register R
R62 UTOPIA Configuration register R/W
R63 System reg i ster R/W
MXT3010 Reference Manua l Version 4.1 185
Instructions
Instructions
The SWAN instruction set is orga nized functionally. The
instructions are described in alphabetical order within each
functional area. Also included in this section is a list of the
functional groups and an alphabetical list of the instructions.
The specific instruction reference inclu des the instruction’s full
name, mnemoni c, the layout of the 32-bit instructio n word, format,
purpose, description, fields, restrictions and any information
specific to a functional area.
The functional groups of the instructions are:
•ALU instructions
•Branch instructions
•Cell Scheduling instructions
•DMA instructions
•Load and Store internal RAM and Fast Memory instructions
Table 46 lists the instructions alphabetically.
186 Version 4.1 MXT3010 Reference Ma nual
TABLE 46. Alphabetical list of instructions
Instruction
Mnemonic Instruction Functional Group Page
ADD Add Registers ALU 234
ADDI Add R e gister and Immediate ALU 235
AND And Registers ALU 236
ANDI And R e gister and Immediate ALU 237
BF Branch Fast Memory First Word
Shadow Register Branch 270
BFL Branch Fast Memory First Word
Shadow Regi s t er an d L ink Branch 271
BI Branch Immediate Branch 272
BIL Branch Immedi ate and Link Branch 273
BR Branch Register Branch 274
BRL Branc h Regi ster an d Link Branch 275
CMP Compare two Registers ALU 238
CMPI Compare Register and Immediate ALU 239
CMPP Compare two Registers with Previ-
ous ALU 240
CMPPI Compare Register and Immediate
with Previous ALU 241
DMA1R,
DMA1W,
DMA2R,
DMA2W
DMA Operations DMA 289,
290,
291,
292
FLS Find Last Set ALU 242
LIMD Load Immediate ALU 243
LD Load Register Lo a d and Store
Internal RAM 321
LDD Load Double Register Load and Store
Internal RAM 322
LMFM Load Mul tipl e from Fast Memory Load and Store Fas t
Memory 308
MAX Maximum of two Registers ALU 244
MAXI Maximum of Register and Immedi-
ate ALU 245
MIN Minim u m of tw o Re g is te r s ALU 246
MXT3010 Reference Manua l Version 4.1 187
Instructions
Instruction
Mnemonic Instruction Functional Group Page
MINI Minim u m of Reg i s te r and Imm e di-
ate ALU 247
OR Or Registers ALU 248
ORI Or Register and Immediate ALU 249
POPC Servic e Sc he d ule Cell Schedulin g 278
PUSHC Schedule Cell Scheduling 280
SFT Shift Right or Left based on Signed
Shift Amount ALU 250
SFTA Shift Right Arithm e tic ALU 251
SFTAI Shift Right Arithmetic Immediate ALU 252
SFTC Shift Right Circular ALU 253
SFTCI Shift Circular Immediate ALU 254
SFTRI/
SFTLI Shift Right or Left Immediate ALU 255
SHFM Store Halfword to Fast Memory Loa d an d St ore F ast
Memory Instructions 311
SRH Store Register Halfword Load an d St ore F ast
Memory Instructions 312
ST Store Register Load an d St ore
Internal RAM 323
STD Store Doubl e Register Load and Store
Internal RAM 324
SUB Subtract Registers ALU 256
SUBI Subtract Register and Immediate ALU 257
XOR Exclusive-or Registers ALU 258
XORI Exclusive-or Regist er and Immedi-
ate ALU 259
188 Version 4.1 MXT3010 Reference Ma nual
Instruction description notations
The follo wing table lists the abbre viations used in the SW AN
processor, describes them briefly, and indicates the functional
instruction group(s) within which that abbreviation is used.
TABLE 47. Abbreviations used in SWAN instructions
Abbreviation Description Usage
rsa Sou rce register, software or hardware ALU, DMA
rsb Sou rce register, software ALU, DMA
rd Destination register, software or hardware ALU, Load/
Store
abc ALU branch condition IFOa
a. IFO = Instruction Field Option
ALU
UM Automatic update memory IFO ALU
MODx Modulo ar ithm etic IFO ALU
AE Always execute IFO ALU
usi Unsigned immediate value ALU
si Sign-extended 10-bit immediate value ALU
usa Unsigned shift amount ALU
tcsa Two’s-complement shift amount ALU
li Long immediate value ALU
ESS# External State Sig nals registe r bit po sitio n Branch
s State of ESS bit for comparison Branch
C Conditional execution operator Branch
cso Counter system operation IFO Branch
wadr Target word address Branch
rla Load address register Load/Store
IDX/# Load address index Load/ Store
LNK Linking IFO Load/Store
#HW Ha lf word count Load/Store
BC/# By t e count DMA
CRCX,
CRCY CRC generation control DMA
POD DMA post-operation directive DMA
MXT3010 Reference Manua l Version 4. 1 189
CHAPTER 9 Registers
This chapter describes the registers associated with the SWAN
processor.
Regis ter types
The two types of registers in the SWAN processor are general-
purpose and control/status. The general-purpose registers are
classi fied as softwar e r egisters becau se th eir usag e and con tent is
firmware depende nt. The regi st er s t h at con tr ol functions and pro-
vide status information are classified as hardware registers.
Software registers
The SWAN processor has 32 general-purpose software registers,
R0-R31, each 16-bits wide. The software registers have no man-
datory implicit hardware or software usage conventions. How-
ever, restrictions apply when software registers are used with the
Load Multiple Fast Memory (LM FM) instruction. The specified
190 Version 4.1 MXT3010 Reference Ma nual
Registers
register is restricted based on the use of the Link instruction field
option and the length of the transfer . For further information, see
“General information for Load and Store Fast Memory instruc-
tions” on page 294.
Hardware registers
The SWAN processor has 32 control and status hardware regis-
ters, R32-R63. In certain cases the MXT3010 mode configura-
tion affects the regi ster function. For more information on
modes, see “R42-write Mode Configuration register” on
page 201.
Specifying registers in SWAN instructions
Most of the SWAN instructions include register read or write
operations. In those instructions, fields are provided to specify
which registers are used. T he fields are identified by abb r evia-
tions that indicate whether the register is used as a source or as
a desti nation, and whet her any rest rictions appl y to that reg ister .
The following table lists the field abbreviations used, their
descriptions, and the permitted registers for that field.
TABLE 48. Field abbreviations
Abbrev
iation Description Permitted
Registers Instruction
Type
rsa Source register, software or
hardware R0-R63 ALU, DMA
rsb Source register, software R0-R31 ALU, DMA
rd Destination register , software
or hardware R0-R63 ALU, Load/
Store
rla Load address register R48-R51
GA, GB, GC, GD Load/Store
MXT3010 Reference Manua l Version 4.1 191
Regi ster t y pes
Initializing softw a re and hardware registe rs
The software registers R0-R31 are unchanged by device initial-
ization and therefore are indeterminate at power up. Initializa-
tion software should clear these registers before use. The
hardware register descriptions (R32-R63) indicate which regis-
ters are unchanged by device initialization and which are initial-
ized to specific values.
TABLE 49. Hardware registers
Location Name Read/Write
R32 General Purpose - 0000 R/W
R33 General Purpos e - FF FF R/W
R34 General Purpos e - FF 00 R/W
R35 General Purpose - 0040 R/W
R36-write The Bit Bucket W
R37 General Purpos e R/W
R38 General Purpos e R/W
R39 General Purpos e R/W
R40 COMMOUT/COMMIN(31:16) R/W
R41 COMMOUT/COMMIN(15:0) R/W
R42-read ESS register R
R42-w rite Mode Configuratio n r e gist e r Set/Cl ear
R43-read Fast Memory Bit Swap register R
R43-write UTOPIA TX Control FIFO register W
R44 CRC32PRX (15:0) R/W
R45 CRC32PRX (31:16) R/W
R46 CRC32PRY (15:0) R/W
R47 CRC32PRY (31:16) R/W
R48 rla Address register R/W
R49 rla Address register R/W
R50 rla Address register R/W
R51 rla Address register R/W
R52 Alternate Byte Count /ID register R/W
R53 Instruction Base Address register R/W
192 Version 4.1 MXT3010 Reference Ma nual
Registers
R54 Programmab l e Interval Timer (PIT0) R/W
R55 Programmab l e Interval Timer (PIT1) R/W
R56 The Fast Memory Data register R/W
R57-read Sparse Event/ICS register R
R57-write Sparse Event/ICS register Set/Clear
R58 Fast Memory Shadow register R/W
R59 Branch register R/W
R60 CSS Configuration register R/W
R61-read Scheduled Address register R
R62 UTOPIA Configuration register R/W
R63 System reg i ster R/W
TABLE 49. Hardware registers
Location Name Read/Write
MXT3010 Reference Manua l Version 4.1 193
R32 Gene ral Purpose - 0000
Registers
R32 General Purp ose - 0000
Description: This is a general purpose read/write register that is initialized to
0x0000. This register is also used during HEC generation (see
“HEC generation and check circuit” on page 25.)
Reset value: 0x0000
Bit definitions: N/A
Note: Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9876543210
General Purpose register
194 Version 4.1 MXT3010 Reference Ma nual
Registers
R33 General Purp ose - FFFF
Description: This is a general purpose read/write register that is initialized to
0xFFFF. This register is also used during HEC generation (see
“HEC generation and check circuit” on page 25.)
Reset value: 0xFFFF
Bit definitions: N/A
Note: Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9876543210
General Purpose register
MXT3010 Reference Manua l Version 4.1 195
R34 General Purpose - FF00
Registers
R34 General Purp ose - FF00
Description: This is a general purpose read/write register that is initialized to
FF00.
Reset value: 0xFF00
Bit definitions: N/A
Note: Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9876543210
General Purpose register
196 Version 4.1 MXT3010 Reference Ma nual
Registers
R35 General Purp ose - 0040
Description: This is a general purpose read/write register that is initialized to
0040.
Reset value: 0x0040
Bit definitions: N/A
Note: Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9876543210
General Purpose register
MXT3010 Reference Manua l Version 4.1 197
R36-write Bit Bucket register
Registers
R36-write Bit Bucket register
Description: The Bi t Bucke t register pr ovides the SWAN pro cessor with a
location that can be wri tten without an y possibility of functi onal
side e f fect s. Inf orm ation writ ten t o R36 is d iscar ded. Thus, soft -
ware can specify R36 a s a de stinati on a nd discard t he re sults of
any operation. R36 is used to emulate a no-op, as well as to
implement testing pseudo-ops, such as TSET and TCLR.
Reset value: N/A
Bit definitions: N/A
Notes: The Bit Bucket register should not be read or otherwise speci-
fied as a sou rce register. Because of the spec ial treatment of th is
regist er locatio n, a read ope ration can sta ll the SWAN proces sor
indefinitely.
Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9876543210
Bit Bucket register
198 Version 4.1 MXT3010 Reference Ma nual
Registers
R37-R 39 General Purpose registers
Description: Registers R37, R38, and R39 are 16-bit read/write general pur-
pose reg isters. T hey are unc hanged by dev ice init ializat ion, and
therefore the contents are indeterminate at power-up.
Reset value: Indeterminate
Bit definitions: N/A
Note: Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9876543210
General Purpose register
MXT3010 Reference Manua l Version 4.1 199
R40-R 41 Host Com munica tio n register s
Registers
R40-R41 Host Communication registers
R40 COMMIN_HIGH/COMMOUT_HIGH
R41 COMMIN_LOW/COMM OUT_LOW
Description: The Host Communication registers provide a 32-bit data transfer
path bet ween the SWAN proces sor and the external host pro ces-
sor. These re giste rs, combi ned with th eir assoc iated statu s f lags
and pins, form a bi-directional command and response mecha-
nism for host communications.
Reset value: Indeterminate
Bit definitions: N/A
Notes: 1. When the SWAN processor reads location R40, CIN_BUSY
(ESS6) is cleared. When the SWAN processor writes location
R40, COUT_RDY (ESS7) is set. Since reads or writes to R40
affect the flags, the programmer should read or write R41 before
reading or writi ng R40 to perform 32-bit communications with a
host processor.
2. For more infor mation on the Host Communication s reg isters op er-
ation, see CHAPTER 8 "Communications" on page 177.
3. Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMMIN/COMMOUT bits [31:16]
15 14 13 12 11 10 9876543210
COMMIN/COMMOUT bits [15:0]
200 Version 4.1 MXT3010 Reference Ma nual
Registers
R42-read External State Signals (ESS) register
Description: The SWAN processor can examine the state of certain internal
conditions and pins by e xamining the Exter nal State Signals reg-
ister.
Reset value: See “I niti alizi ng the Mode Con figur ation r egister ” on page 408.
Bit definitions:
Note: Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9876543210
See “Bit Definitions” below
Bit Read Definition Bit Read Definition
15 Unconditional bran ch a
a. ESS15 is hardwired to th e asserted state. If a Branch instru ction does
not con tain a specified value for th e ESS field, th e assembler co des that
field as 1111, and an unconditio nal branch is taken.
7 COUT_RDYb
b. After the SWAN processor writes the COMMOUT register, there is a
5-6 instruc tio n dela y be for e the COUT_RDY bit is set.
14 DMA2 queue stage busy 6 CIN_BUSYc
c. After the SWAN processor reads the COMMIN regi ster, there is a 5-6
instruction delay before the CIN_BUSY bit is cleared.
13 DM A1 queue stage busy 5 CSS operation in progress
12 DMA2 out or queue stage busy 4 Assigned Cell flag register
11 DMA1 out or queue stage busy 3 RXBUSY Counter > 4
10 TXFULL Counter = full 2 TXFULL Counter < 2
9 RXBUSY Counter = /0 1 ICSI_Ba
8 Sparse Event register bit ORd
d. When an external event occurs that is being monitored by the Sparse
Events regi ster, there is a 3-4 instruction delay betw een the external
event and th e Sparse Events OR indication of that ev ent.
0 ICSI_Ae
e. When an external event occurs t hat is being moni tored by an ICSI bit ,
there is a 3-4 instru ction de lay betwe en the extern al event and the ICSI
indica ti on of that ev ent.
MXT3010 Reference Manua l Version 4.1 201
R42-write Mode Configuration register
Registers
R42-write Mode Configuration register
Description: The Mod e Configuratio n register inclu des provision f or mode 0
and mode 1 oper at io ns. Th e SWAN processor does not write to
the Mode Configuration register directly. Instead, it writes a
control byt e to the Mo de Co nfi gur ation re gis te r t o set and cl ear
certain bits. If bit 7 of the contro l byte is 0, the ta rget bit is
cleared (unless it is triggered simultaneously). If bit 7 is 1, the
target bit is s et.
Reset value: See “Initiali zing th e Mode Configur ation r egist er” on pa ge 408.
Bit definitions:
15 14 13 12 11 10 9876543210
Reserved SF Set Reserved Targ et Bit
Selector
Bit Name Function
15:9 Reserved Programs shoul d write zeroes to these bits.
8Special Features This bit enables specia l fea tu r es i n R43-write
and R43-read. (See page 204 and page 205)
0 Special features di sabled (normal operation)
1 Speci al features enabl ed
7Set The state of this bit determines whether the bit
selected by the Target Bit Selector is set or
cleared
0 The target bit is cleared
1 The target bit is set
6:4 Reserved Programs should write zeroes to these bits.
3:0 Tar get Bit Selector These bits select which bit is set or cleared.
R42
Bit Target Bit
Selected B it State and Function
00000 HEC Control
0HEC is generated and i nser ted
1HEC is omitted
10001 Cell Length Control
052 byte cells
156 byte cells
202 Version 4.1 MXT3010 Reference Ma nual
Registers
Notes: Register access rules apply. See Table 4 on page 24.
Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
20010 Programs should write zeroes to these bits.
30011 Programs should write zeroes to these bits.
40100 Fast Memory Mode Control
0Fast Memory is in Mode 0
1Fast Memory is in Mode 1
50101 DMA Plus Control
0DMA Plus disabled
1DMA Plus performs automatic rla
60110 Port1 Operation Control
0Port1 normal operation
1Port1 Early End enabled
70111 Port2 Operation Control
0Port2 normal operation
1Port2 Early End enabled
81000 Reserved
0Reserved
1Reserved for PLL test mode
91001 R32 Control
0R32 in no r ma l oper ation
1HEC8 circuit enabled on R32
10 1010 R55 Control
0PIT1 is d isable d ; R5 5 is a 16 -bit R/W re gi st er
1PIT1 is en abled; R55 operates as a time r
11 1011 R54 Control
0PIT0 is d isable d ; R5 4 is a 16 -bit R/W re gi st er
1PIT0 is en abled; R54 operates as a time r
13,12 1100, 1101 Programs should write zeroes to these bits.
14,15 111 0, 1111 Reserved
R42
Bit Target Bit
Selected B it State and Function
MXT3010 Reference Manua l Version 4.1 203
R43-re ad Fast Memory Bit Swap register (R42w[8]=0)
Registers
R43-read Fast Memory Bit Swap reg ister (R42w[8]=0)
Description When bit [8] of R42-write is zero ( 0), this register con tains th e
same data as the Fast Memory Byte register (R56) with the bit
order reversed.
Reset value: Indeterminate
Bit definitions: N/A
Notes: R43 can be used to implement a Find First Set instruction by
loading a value into R56 and applying the Find Last Set (FLS)
instruction (page 242) to R43.
Register access rules apply. See Table 4 on page 24.
Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
012345678910 11 12 13 14 15
Fast Memory Bit Swap register (Note bit order)
204 Version 4.1 MXT3010 Reference Ma nual
Registers
R43-read Specia l Features register (R42w[8]=1 )
Description When bit [8] of R42-write is one (1), this register implements
special configuration features.
Reset value: Indeterminate
Bit definitions:
Notes: Register access rules apply. See Table 4 on page 24.
Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9876543210
Reserved Port2 DMAs Reserved URX Count UTX Count
Bit Name Function
15:14 Reserved Programs shoul d write zeroes to these bits.
13:11 Port2 DMAs Port2 DMAs comp leted . Thi s three-b it coun ter
is incremented on the last transfer of a DMA2
operation. I t i s decreme nted in soft ware by a
branch instruction with the following syntax:
bi$label DMA count.
10:8 Reserved Programs shoul d write zeroes to these bits.
7:4 URX Count This four -bit counter can read either the current
state of the UTOPIA Receiver’s Busy or Full
Counter, depending upon R4 3-write [ 9].
3:0 UTX Count This four-bit counter can read either the current
state of the UTOPIA T ransmitter’ s Busy or Full
Counter, depending upon R4 3-write [ 8].
MXT3010 Reference Manua l Version 4.1 205
R43-write UTOPIA Control FIFO register
Registers
R43-write UTOPIA Control FIFO register
Description: Data written to the UTOPIA Control FIF O regist er provides cer-
tain charac teristics for cells s cheduled for transm ission from
Cell Buf fer RAM through the UTOPIA port. The data written to
this register is stored in a FIFO-like internal memory until an
actual cell transmiss ion by the UT OPIA po rt controller removes
it. Up to eight control entries can be stored in the FIFO.
The upper byte of this register implements sp ecial configuration
features controlled by bit [8] of “R42-write Mode Configuration
register” on page 201.
Reset value: Indeterminate
Bit definitions
(Lower byte):
15 14 13 12 11 10 9876543210
Reserved Configuratio n Op tio ns Rsv I CG TXPHY
Bit Name Function
7 Reserved Programs should write zero to this bit.
6 I Insert unassigned cell
5 CG Generate and insert a CRC10 for this cell
4:0 TXPHY Select the address of the target PHY in a multi-
PHY system
206 Version 4.1 MXT3010 Reference Ma nual
Registers
Bit definitions
(Upper byte): If R42w [8] = 0, these bits are reserved, and programs should
write zeroes to them. If R42w [8] = 1, these definitions apply:
Notes: 1. Software should write the control entry into the UTOPIA Control
FIFO before incrementin g TXBUSY. Fo r mo re information on
UTOPIA port operatio n, see CHAPTER 6 "The UTOPIA por t" on
page 69.
2. The FIFO is a hardware-managed 8-deep circular list. Entries can
be re-used without writing new data.
3. CRC10 overwrites the last ten bits of the cell with th e computed
CRC value.
4. When bit I is set, t he MXT3010 hardware stuf fs an unassigned cell
into the UTOPIA Control Byte FIFO without accessing the Cell
Buffer RAM.
5. Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
Bit Name Function
15:14 Reserved Programs should write zeroes to theses bits
13 PIT1 Sel PIT1 External Select Pin
0 = URX_CTRL4
1 = ICSI_C
12 PIT0 Sel PIT0 External Select Pin
0 = UTX_CTRL4
1 = ICSI_D
11 PIT1 Mode PIT1 External Mode
0 = Disabled
1 = PIT1 is clocked by the rising edge of the exter-
nal bit selected by bit [13]
10 PIT0 Mode PIT0 External Mode
0 = Disabled
1 = PIT0 is clocked by the rising edge of the exter-
nal bit selected by bit [12]
9 URX Count
Select UTOPIA Receiver Count Select
0 = URX Count in R43read is Receiver Busy
1 = URX Count in R43read is Receiver Full
8UTX Count
Select UTOPIA Receiver Count Select
0 = UTX Count in R43read is Transmitter Busy
1 = UTX Count in R43read is Transmitter Full
MXT3010 Reference Manua l Version 4.1 207
R44-R47 CR C32 PRX an d CRC32 PRY registers
Registers
R44-R47 CRC32PRX and CRC32PRY registers
R44 CRC32PRX [15:0], R46 CRC32PRY [15:0]
R45 CRC32PRX [31:16], R47 CRC32PRY [31:16] ]
Description: These registers contain the partial results of CRC32 calcula-
tions. The CRCX and CRCY bits in the DMA instr uction or the
X and Y bits in the Alternate Byte Count/ID register (R52)
determine which, if any, register set is used. Use of CRCX/
CRCY control or X/Y control depends on whether the DMA
instruction contains a BC/# instruction field option.
Reset value: 0x0000
Bit definitions: N/A
Notes: If R44-R47 ar e not used fo r CRC calculat ions, they ca n be used
as gener al pur pose r egist ers. Whe n used a s gene ral pu rpose reg-
isters, register access rules apply. See Table 3 on page 23.
Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9876543210
CRC Partial Result registers (bits [15:0])
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC Partial Result registers (bits [31:16])
208 Version 4.1 MXT3010 Reference Ma nual
Registers
R48-R51 Local Address registers (rla)
Description: The Local Address registers provide four hardware registers that
are used as address registers by local (internal) memory loads
and stores.
Reset value: Indeterminate
Bit definitions:
Notes: 1. The MXT3010 implemen ts four fixed va lue registers that can also
be used as address registers. These rla constants are GA, GB, GC,
and GD that are fixed at 0x400, 0x420, 0x440, and 0x460, respec-
tively.
2. For more information on the Load and Store instructions, see
“General information for Load and Store internal RAM instruc-
tions” on page 314.
3. Register access rules apply. See Table 3 on page 23.
4. Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9876543210
Reserved S G MEM
Bit Name Function
15:12 Reserved Read, and shou ld be written, as zeroes.
11 SScoreboard/Cell Buffer selection
0
1Cell Buffer RAM access
Scoreboard access
For Cell Buffer RAM access, the following bit definitions apply:
10 GCell Buffer RAM Address Method
0
1Linear Address
Gather Address
9:0 MEM These 10 bits provide byte addressing for the 512
16-bit halfwords in the Cell Buffer RAM.
For Scoreboard access, the following bit definitions apply.
10:0 MEM These 11 bits provid e byte addressing for the 51 2
32-bit words in the Scoreboard.
MXT3010 Reference Manua l Version 4.1 209
R52 Alternate Byte Count/ID register
Registers
R52 Alternate Byte Count/ID register
Description: Software can use the Alternate Byte Count/ID register to pro-
vide DMA instruction information to ei ther the Port1 or Por t2
interface when executing a DMA instruction. DMA operations
use the contents of R52 if a DMA instruction is executed without
a BC/# instruction field option.
Reset value: 0x0000
Bit definitions:
Note: Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9876543210
REV Reserved X Y Count
Bits Name Function
15:13 REV Device ID field . On reads, retur ns a value of 000xb for
MXT3010 revision A, 001xb for MXT3010 revision B/
C.
12:10 Reserved Read, and should be written, as zeroes.
9 X CRCX bit
If set, a CRC32 partial result is generated based on
CRC32PRX register’s initial value and the result is
deposited into CRC32PRX
8 Y CRCY bit
If set, a CRC32 Partial Result is generated based on
CRC32PRY register’s initial value and the result is
deposited into CRC32PRY
7:0 Count DMA Byte Count
00 = Zero byte ope ratio n
FF = 255 byte operation
210 Version 4.1 MXT3010 Reference Ma nual
Registers
R53 Instruc tion Base Address register
Description: The SWAN processor su pports an i nstructio n space of 1 28K 32-
bit instructions, organized as 32 segments of 4K words each.
The lowest order 5 bits of this register provide the ability to
select any of the 32 segments for user code.
Reset value: The Reset value i s ini tially 0x0 040, and th en is depende nt upo n
the starting address of the bootstrap loader.
Bit definitions:
Note: Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved Boot NC Segment ID
Bits Name Function
15:7 Reserved Read , and should be writ ten, as zeroes.
6Boot This flag is set by the SWAN processor during its
power-up initialization routine, and disables the exe-
cution of user instructions until the boot process is
finished. This bit is cle ared by the SWAN processor at
the conclusion of po wer-up initial iz ation .
5NC Non-Cached. Instructions executed while this bit is
set will not be cached.
4:0 Segment ID These bits are used as Fast Memory Address bits
[18:14] during instruction fetches from the Fast Mem-
ory, and thus select which of 32 segments of 4K
words will be addressed .
MXT3010 Reference Manua l Version 4.1 211
R54-R55 Programmable Interval Timer registers
Registers
R54-R 55 Progra m mable Interval Timer registers
R54 PIT0 [15:0], R55 PIT1 [15:0]
Description: The MXT3010 contains two 16-bit programmable interval tim-
ers (PITs), PIT0, and PIT1.
The pres ent values of the PI Ts are mappe d i nt o t he Programma -
ble Interval Timer registers R54 (PIT0) and R55 (PIT1). The
SWAN processor ca n read t he pre sent val ue of a PIT by sp ecify-
ing either R54 or R55 in an ALU operation.
Firmware sets an initial value by writing into R54 (PIT0) or R55
(PIT1 ). When firmware wri tes an init ializati on value, that val ue
is immediately transferred into the PIT . PIT0 decrements by one
on each rising edge of the external clock. PIT1 decrements by
one on each rising edge of the CPU clock, which operates at
twice t he frequenc y of the ext ernal clock. When PIT0 ti mes out,
Bit 4 of the Sparse Events register (R57) is set. When PIT1 times
out, Bit 5 of the Sparse Events register (R57) is set. Upon time-
out of a P IT, it i s automati cally reloa ded with it s count init ializa-
tion value and the count down process begins anew.
Reset value: 0x0000
Bit definitions: N/A
Notes: Firmware en ables/disables a PIT from counting, timing out, and
set ting its bit in th e Sparse Event register via enable bits in
“R42-write Mode Configuration register” on page 201.
Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9876543210
Programmable Interval Timer registers
212 Version 4.1 MXT3010 Reference Ma nual
Registers
R56 Fast Memory Data register
Description: The Store Halfword to Fast Memory (SHFM) instruction writes
the contents of R56, the Fast Memory Data register, into the Fast
Memory location specified by registers rsa and rsb. The contents
of R56 are first entered into the Fast Memory Controller’ s write
buffer before being written out to memory.
Reset value: Indeterminate
Bit definitions: N/A
Notes: An SHFM can immediately follow an instruction that modifies
R56.
Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9876543210
Fast Memory Data register
MXT3010 Reference Manua l Version 4.1 213
R57-read Sparse Event/ICS register
Registers
R57-read Sparse Event/ICS register
Description: This register records events that occur infrequ ently. Hardware
performs a logical OR opera tion on bits (5 :0) of this register a nd
provides the resul t in ESS8. Hardwar e clears bits [9:6]w hen the
condition causing the bit to be set is no longer true. Other bits
(marked R/W) are cleared by the software via the “R57-write
Sparse Event/ICS register (Set/Clear)” on page 214.
Reset value: N/A
Bit definitions:
15 14 13 12 11 10 9876543210
See “Bit Definitions” below
Bits Description R/W
15:12 ICSO_(D:A)a
These bits control the ICSO_(D:A) pins if the ICSO Out-
put Enable bit of the System register is set. The SWAN
can set an d clear these bit s to signal extern al devices.
a. When the SWAN processor changes the state an ICSO bit, there is a 3-
4 instru ction delay before the new state appears at the ICSO pin.
R/W
11 ICSO_A Select: 0 = ICSO_A_SEL; 1 = TX_IDLE_SOC R/W
10 ICSO_B_SEL: 0 = ICSO_B; 1 = STALL_DLY. R/W
9TXBUSY state indicator R
8RXFULL state indica tor R
7CRC32X Error Indicator from Port1
Test only at the compl etion of a DMA operation. R
6CRC32Y Error Indicator from Port1
Test only at the compl etion of a DMA operation. R
5PIT1 Time Out
Set when PIT1 counts down to 0. R/W
4PIT0 Time Out
Set when PIT0 counts down to 0. R/W
3:0 ICSI_(D:A)b
Set if corresponding MXT3010 input is set and corre-
sponding SER enable bit is set in the System register.
b. When an external event occurs, there is a 3-4 in struction delay
between the external event and the ICSI indication of that event.
c. LD, LDD restrictions apply. See “Register access rules” on page 22.
R/W
214 Version 4.1 MXT3010 Reference Ma nual
Registers
R57-write Sparse Event/ICS register (Set/Clear)
Description: The SWAN processor does not write to the Sparse Event register
direct ly. Inste ad, it writ es a control by te to th e Sparse Eve nt reg-
ister to set and clear certain bits. If bit 7 of the control byte is 0,
the target bit is cleared (unless held set by hardware conditions).
If bit 7 is 1, the target bit is set (unless held clear by hardware
conditions).
Reset value: N/A
Bit definitions:
Examples:
Notes: 1. Bits [9:6] are read only.
2. Register access rules apply. See Table 3 on page 23.
3. Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9876543210
Reserved Set Reserved Target Bit Selector
Bit Name Function
15:8 Reserved Programs should write zeroes to these bits.
7Set The state of this bit determines whe the r the bit
selected by the Target Bit Selector is set or cleared
0 The target bit is cleared
1 The target bit is set
6:4 Reserved Programs should write zeroes to these bits.
3:0 Target Bit
Selector These bits select which bit is set or cleared. The tar-
get bits are listed in “R5 7-r ead Spar se Even t/ICS
regist e r” on pa g e 213.
Bit To Set, Write To Clear, Write Bit To Set, Write To Clear, Write
00x80 0x00 10 0x8A 0x0A
10x81 0x01 11 0x8B 0x0B
20x82 0x02 12 0x8C 0x0C
30x83 0x03 13 0x8D 0x0D
40x84 0x04 14 0x8E 0x0E
50x85 0x05 15 0x8F 0x0F
MXT3010 Reference Manua l Version 4.1 215
R58 Fast Memory Sh adow register
Registers
R58 Fast Memory Shadow register
Description: The Fas t Memory Sh adow register is automat ically loaded wit h
the first 16 -bit word return ed from Fast Memory during a read
operation (LMFM instruc tion) th at specifies the Link (LNK)
instruction field option. The Branch Fast Memory instructions,
BF and BFL, use the contents of this register as the target
address of the branch operation.
Reset value: Indeterminate
Bit definitions: The Branch Target Field specifies the absolute word address
within the current code segment (4096 words) at which execu-
tion is to continue when using th e Branch Fast Memory in struc -
tions, BF and BFL. The reserved bits (15:12) are read, and
should be written, as zeroes.
Notes: 1. Software can read and write the Fast Memory Shadow register in
the same fashion as the Branch register (R59). To avoid accessing
a stale value, separate the BF or B F L instruction fro m a p receding
write to R58 by at least one instruction. See Table 3 on page 23
2. Software can use BF/BFL to gain fast access to a service address
contained in the first halfword of a Channel Descriptor. Execution
of a BF/BFL following execution of an LMFM instru ction with
LNK causes a CPU stall until the first halfword is read from mem-
ory. Wh en the first halfword is returned, the stall conditi on termi-
nates. Software can avoid a stall by separating the LMFM from
the BF/BFL by at least five instructions.
3. Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9876543210
Reserved Branch Target Field
216 Version 4.1 MXT3010 Reference Ma nual
Registers
R59 Branch register
Description: The Branch register instructions, BR and BRL, use the content
of thi s register as the tar get addre ss of the b ranch operat ion. The
address in R59 represents an absolute address to branch to
within the active segment.
Reset value: Indeterminate
Bit definitions: The Branch Target Field specifies the absolute word address
within the current code segment (4096 words) at which execu-
tion i s to c ontin ue when u sing t he Bra nch Regist er i nstruc tions,
BR and BRL. The reser ved bits (1 5:12) ar e r ead, and s hould be
written, as zeroes.
Notes: Software can read and write the Branch register. To avoid
accessing a stale value, separate the BR or BRL instruction from
a prece ding writ e to R59 by at leas t one ins tructi on. See Table 3
on page 23
Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9876543210
Reserved Branch Target Field
MXT3010 Reference Manua l Version 4.1 217
R60 The Cell Scheduling System (CSS) Configuration register
Registers
R60 The Cell Scheduling System (CSS)
Configuration register
Description: The CSS Configuration register indicates the base address in
memory of the Connect ion ID ta ble . It al so indi cates the si ze of
the Scoreboard to be used.
Reset value: 0x00FF
Bit definitions:
Notes: 1. Software must initialize the CSS Configuration register before
using the Cell Scheduling System.
2. Register access rules apply. See Table 4 on page 24.
3. Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9876543210
E CR SZ CID Reserved
Bits Name Description
15 ECSS error flag
14 CR 0 = No CCS Reset
1 = CSS Reset
13:12 SZ Scoreboard Section Size
00 = 2,048 bits/entries per section; up to 8 sections
01 = 4,096 bits/entries per section; up to 4 sections
10 = 8,192 bits/entries per section; up to 2 sections
11 = 16,384 bits/entries per section; 1 section
11:8 CID C onnection I D Table Base Address:
Used as FADR S(18:1 5) on Connection ID Table
accesses for PUSHC and POPC.
7:0 Reserved Reserved. The bits are undefined on reads and should
be written as zeroes.
218 Version 4.1 MXT3010 Reference Ma nual
Registers
R61-read Scheduled Address register
Description: At the completion of a PUSHC operation (as indicated by the
clearing of ESS5 in R42), the SWAN processor can read the
selected Connection ID Table address (FADRS [18:1]). The
numb er pre sented in this r egister is the 14-bi t halfword addres s
offset (FADRS [14:1]) within the table, and the table base
address (FADRS [18:15]) is obtai ned from the CID bits in “R60
The Cell Scheduling System (CSS) Configuration register” on
page 217.
Reset value: Indeterminate
Bit definitions: Bits 13:0 are automatically loaded with the Connection ID T able
address selected by the Cell Scheduling System at the comple-
tion of a scheduled write operation, PUSHC and PUSHF . Bits 15
and 14 are reserved. They should be ignored.
Notes: For more information on the Cell Scheduling System (CSS), see
“The Cell Scheduling System” on page 27. For more informa-
tion on the PUSHC operation, see “PUSHC Schedule” on page
280.
Software must not check this register until an outstanding
PUSHC/PUSHF is complete. See “Scheduling” on page 32.
Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
15 14 13 12 11 10 9876543210
Reserved Connection ID Table Address
MXT3010 Reference Manua l Version 4.1 219
R62 The UTOPIA Configuration register
Registers
R62 The UTOPIA Configuration register
Description: The UTOPIA Configuration register determines the operating
characteristics of the UTOPIA port. In addition to the R62 reg-
ister, two tar ge t bit s ([ 0] an d [1]) fro m R42 (the Mo de Conf igu-
ration register) are used to program the UTOPIA port.
Reset value: 0x0000
Bit definitions:
15 14 13 12 11 10 9876543210
See “Bit Definitions” below
Bits Description
15:14 Number of Physical PHY devices present
00
01
10
11
This value te lls the UT OPIA Port Re ceiver the n umber of p hys-
ical PHY devices present. This in turn determines the number
of RXCLAV/TXCLAV and RXENB_/TXENB_ signals that
should be used. Please see the UTOPIA port chapter in Section
1 and Table 50 below.
Reserved
1-PHY mode
2-PHY mode
Reserved
13:9 UTOPIA Port Most Significant PHY Address
.The UTOPIA Port Receiver polls PHY devices searching for
an RXCLAV by increm enting the polled address accord ing to
the UTOPIA Level 2 specification. The UTOPIA Port Trans-
mitter kno ws th at it has reached the last address and should
begin at zero again when it reaches this address. For examples
of th e us e of th ese bit s, see Figu re 37 on page 89 and Fi gur e 38
on page 90.
8UTOPIA Port Data Bus Width
0
116 Bits Wide
8 Bits Wide
Direct ion is determined by which device is not in Reset
Mode. (See “Selecting transmit or receive mode” on page 72.)
220 Version 4.1 MXT3010 Reference Ma nual
Registers
Note: See “Register access rules” on page 22.
Bits Description
7UTOPIA Port Operational / Output Clock Freq uency Selection
0
1TXCLK and RXCLK operate at 1/2 of internal CLK frequency .
TXCLK and RXCLK operate at 1/4 of internal CLK frequency.
Note: 1/ 2 the internal CLK frequency is on t he FN pin.
6:4 Transmit Cell Buffer Size in the Cell Buffer RAM
001
010
011
100
101
110
111
Transmitter Buffer Size in the Cell Buffer RAM = 2 cells
Transmitter Buffer Size in the Cell Buffer RAM = 3 cells
Transmitter Buffer Size in the Cell Buffer RAM = 4 cells
Transmitter Buffer Size in the Cell Buffer RAM = 5 cells
Transmitter Buffer Size in the Cell Buffer RAM = 6 cells
Transmitter Buffer Size in the Cell Buffer RAM = 7 cells
Transmitter Buffer Size in the Cell Buffer RAM = 8 cells
3:1 Receive Cell Buffer Size in the Cell Buffer RAM
000
001
010
011
100
101
110
111
UTOPIA Port Receiver in Reset Mode. All Rx outputs are
tristated. This includes RXDATA (a bidirectional signal), but
does not in clude RXCLK. Al l inputs are pu lled to their ina ctive
states by the MXT3010.
Receiver Buffer Size in the Cell Buffer RAM = 2 cells
Receiver Buffer Size in the Cell Buffer RAM = 3 cells
Receiver Buffer Size in the Cell Buffer RAM = 4 cells
Receiver Buffer Size in the Cell Buffer RAM = 5 cells
Receiver Buffer Size in the Cell Buffer RAM = 6 cells
Receiver Buffer Size in the Cell Buffer RAM = 7 cells
Receiver Buffer Size in the Cell Buffer RAM = 8 cells
0UTOPIA Receiver Reduction Mode E nable Bit
0
1
Reductio n Function Di sable d (ATM Hea der bytes [2 :3 ] writ te n
into the Cell Buffer RAM unchanged)
Reduction Function Enabled (ATM header bytes [2:3] written
into the Cell Buffer RAM after reduction function performed
according to Reduction Mask Setting selected by R63[6:0]).
TABLE 50. Signal utilization for 1-PHY and 2-PHY modes
Mode TX/RX CLAV TX/RX ENB ADRS
1 PHY TX/RX_CLAV TX/RX_ENB_ TX/RX CTRL [3:0]
2 PHY
PHY 0 TX/RX_CLAV TX/RX_ENB_ TX/RX CTRL [1:0]
PHY 1 TX/RX CTRL [3] TX/RX CTRL [2] TX/RX CTRL [1:0]
MXT3010 Reference Manua l Version 4.1 221
R63 The System register
Registers
R63 The System register
Description: The System register determines the operating characteristics of
the MXT3010.
Reset value: 0x0000
Bit definitions:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OD OC BS IMASK EN VPI/VCI
Bits Name Function
15:14 OD, OC Reflect the state of ICSO_(D:C) at reset
removal.
13:12 BS Boot
Source These bits indicate the source that was used
to boot the MXT3 010
00
01
10
11
Via Fast Memory (used only in simulation)
Via Port 1
Via Port 2
Via COMMIN register
11:8 IMASK ICSI_(D:A) Sparse Event register enable
0
1
Bit in Sparse Event register is not set when
ICSI_x is high.
Bit in Sparse Event register is set when
ICSI_x is high.
7EN ICSO_(D:A) Output Enable
0
1Outputs Tristates (default at reset)
Outputs Actively Driving
Note:
The MXT3 010 reads configuration i nforma-
tion from ICSO_(D:A) during reset. To
ensure that the MXT3010 does not drive
these pin s at re se t, th e pins are re set in in pu t
mode. The MXT3010 senses configuration
informati on from the m as it e xits reset. So ft-
ware can enable these pins as outputs by set-
ting this bit to one.
222 Version 4.1 MXT3010 Reference Ma nual
Registers
Note: Register access rules apply. See Table 4 on page 24.
Restrictions apply to the use of LD, LDD instructions with this
register. See “Register access rules” on page 22.
Bits Name Function
6:0 VPI/VCI UTOPIA Receiver Reduction Mask
Setting Va lue written into ATM Header lower
halfword in CBR
0000 00 1
0000 011
0000111
0001111
{0,0,0,0,0,0, vpi(0), vci(7:0), clp}
{0,0,0,0,0, vpi(1:0), vci(7:0), clp}
{0,0,0,0, vpi(2:0), vci( 7:0), clp}
{0,0,0, vpi(3:0), vci(7:0), clp}
0000 01 0
0000 110
0001110
0011110
{0,0,0,0,0, vpi(0), vci(8:0), clp}
{0,0,0,0, vpi(1:0), vci( 8:0), clp}
{0,0,0, vpi(2:0), vci(8:0), clp}
{0,0, vpi(3:0), vci(8:0), clp}
0000 10 0
0001100
0011100
0111100
{0,0,0,0, vpi(0), vci(9:0), clp}
{0,0,0, vpi(1:0), vci(9:0), clp}
{0,0, vpi(2:0), vci(9:0), clp}
{0, vpi(3:0) , vci(9:0), clp}
0001000
0011000
0111000
1111000
{0,0,0, vpi(0), vci(10:0), clp}
{0,0, vpi(1:0), vci(10:0), clp}
{0, vpi(2:0), vci(10:0), clp}
{vpi(3:0), vci(10:0), cl p}
0010000
0110000
111 0000
{0,0,vpi(0), vci(11:0), clp}
{0,vpi(1:0), vci(11:0), clp}
{vpi(2:0), vci(11 :0), clp}
0100000
1100000 {0,vpi(0), vci(12:0), clp}
{vpi(1:0), vci(12:0), cl p}
1000 00 0 {vpi(0), vci(13:0), clp}
0000000 {vci(14:0), clp}
MXT3010 Reference Manua l Version 4. 1 223
CHAPTER 10 Arithmetic Logic Unit
Instructions
The arithmetic and logical instructions of the SWAN processor
manipulate data c ontain ed in the register set.
Addressing modes
Two addressing modes are supported for arithmetic and logical
instructions: triadic register and immediate.
Triadic register
Triadic register addressing mode uses three fields in the instruc-
tion t o specif y two sou rce regi sters (rsa and rsb) a nd a dest ination
regist er (rd). The r sa and rd regist ers might be any o f the softwar e
registers (R0-R31) or any of the hardware registers (R32-R63).
The rsb register can only be one of the software registers.
224 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
FIGURE 78.Triadic register operation
FIGURE 79.Triadic instruction format
Immediate
Immediate addressing mode uses two bit fields in the instruction
to specify one source register (rsa) and a destination register
(rd). The second operand is provided as an immediate value in
the instruc tion word.
The width of the immediate value and its format (signed,
unsigned) is instruction dependent. Arithmetic instructions
(ADDI, SUBI) use a 6-bit unsigned immediate value. Logical
instructions (ANDI, CMPI, CMPPI, MAXI, MINI, ORI, XORI)
use a 10-bit sign-extended immediate value. Shift instructions
(SFTAI, SFTCI, SFTRI, SFTLI) use instruction-specific for-
mats similar to the 6-bit immediate fi eld used in arithmetic oper-
ations.
15
15
15
00
0
ALU Operation
rsa
rd
rsb
31 26 25 20 19 16 15 10 9 5 4 0
opcode rd - - - - rsa - - - - - rsb
- - - Instruction specific fields
MXT3010 Reference Manua l Version 4.1 225
Overflo w flag
FIGURE 80.Immediate 10-bit instruction format
FIGURE 81.Immediate 6-bit instruction format
Over flow fl ag
Signed arithmetic is supported by an Overflow flag. During
addition operations, the Overflow flag is set when both source
operands have the sa me si gn, and the si gn of th e result i s d iffer -
ent. During subtraction operations, the Overflow flag is set
when the sig ns of the sour ce operands differ, and the si gn of the
result matches the sign of the second operand.
Instructions that
use this flag Only add and subtract operations affect the Overflow flag. None
of the other ALU instructions can change the state of this flag,
nor can add and subt rac t ope ra ti ons t h at s pec if y the u se of mod -
15
15
0n
0
ALU Operation
rsa
rd
rsb
31 26 25 20 19 16 15 10 9 0
opcode rd - - - - rsa 10-bit signed immediate
- - - Instruction specific fields
31 26 25 20 19 16 15 10 9 6 5 0
opcode rd - - - - rsa - - - - 6-bit unsigned im.
- - - Instruction specific fields
226 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
ulo arithmetic. Other ALU instructions can test the state of this
flag th at res ulted fr om the l ast arit hmetic oper ation by using th e
Branch No Overflow ALU branching option.
Instruction options
Certain options are common to many of the ALU instructions.
These options include modulo arithmetic, automatic memory
updating, and ALU branching.
Modulo arithmetic
The ALU in the SWAN processor supports modulo arithmetic.
W i th modul o arit hmetic , the ope rati on of an ALU in struc tion is
constrained to the number of bit positions specified in the
instruction word. Bits outside the specified operation width are
not affected. Source bits from rsa are simply copied to the cor-
responding destination bits in rd.
Modulo arithmetic can be specified for any field width, from
one bit to fifteen bits. The width of the desired modulo arith-
metic is specified in ALU instructions with an instruction field
option. Full 16-bit operation is the default width for ALU
instructions where no modulo arithmetic instruction field option
is specified. Table 51 on page 227 lists the modulo arithmetic
options.
MXT3010 Reference Manua l Version 4.1 227
Instruction op tio ns
TABLE 51. Modulo arithmetic options
A modulo arithmetic operation does not affect the ALU flag reg-
isters or Overflow.
Using modulo
arithmetic and
branch conditions
The Branc h On Zero and the Br anch On Non- Zero ALU bra nch
conditions are evaluated based on the bits within the modulo
field only. This al lows one to test, for example, for the occu r-
rence of a boundary crossing by a memory pointer that has a
non-zero base address.
Modulo arithmetic
example In the following example, two Load Immediate (LIMD) instruc-
tions are used to load the hex numbers 1234 and 1111 into reg-
isters r0 and r1 respectively . A modulo 16 addition of these two
registers is then performe d, and the resu lt is placed in r2. Note
that due to the modulo 16 addition, only bits [3:0] have been
affect ed by the addition process.
IFO Width rd IFO Width rd
MOD2 1rsa[15:1] |
alu[0] MOD512 9rsa[15:9] |
alu[8:0]
MOD4 2rsa[15:2] |
alu[1:0] MOD1K 10 rsa[15:10] |
alu[9:0]
MOD8 3rsa[15:3] |
alu[2:0] MOD2K 11 rsa[15:11] |
alu[10:0]
MOD16 4rsa[15:4] |
alu[3:0] MOD4K 12 rsa[15:12] |
alu[11:0]
MOD32 5rsa[15:5] |
alu[4:0] MOD8K 13 rsa[15:13] |
alu[12:0]
MOD64 6rsa[15:6] |
alu[5:0] MOD16K 14 rsa[15:14] |
alu[13:0]
MOD128 7rsa[15:7] |
alu[6:0] MOD32K 15 rsa[15] |
alu[14:0]
MOD256 8rsa[15:8] |
alu[7:0] blank 16 alu[15:0]
Address Instruction Result
0x0000 LIMD r0, 0x 1234 r0 <- 0x1234
0x0001 LIMD r1, 0x1111 r 1 <- 0x1111
0x0002 ADD r0, r1, r2 MOD16 r2 <- 0x1235
228 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
Automatic memory updates
When th e automa tic memo ry update feature is en abled, t he Fast
Memory controller writes the results of the ALU operation back
into the linked Fast Memory location associated with the desti-
nation r eg ist er, rd. Thi s f eat ur e eliminat es the need f or separat e
store instru ctions to write results back to memo ry, thus saving
machine cycles and reducing latency.
The Update Memory field (UM)
All ALU instructions except the compare instructions (CMP,
CMPI, CMPP, CMPPI) can specify the automatic memory
update opt ion by incl udi ng th e letter s UM in the command lin e.
For co mplete details on th e opera ti on of the auto ma tic memo r y
update feature, see “Memory update protocol” on page 49 and
“Linking (the LNK bit)” on page 299.
ALU branching
The ALU in th e SWAN processor provides all ALU instructions
with an integrated conditional branching capability. In one
instruction executing in a single machine cycle, the program can
modify a register, test the results of that operation, and use the
results to affect program flow.
The target ad dress of a n ALU bra nch operat ion is fi xed in hard-
ware at four instructions past th e ALU instruc tion. If the spe ci-
fied condition code evaluates as true, the SWAN executes the
instruction immediately following the ALU instruction (the
IFO Result
UM Cause automatic memory update
blank No memory update
MXT3010 Reference Manua l Version 4.1 229
Instruction op tio ns
“committe d slo t”) and then branches t o the targe t address. If the
specified condition code evaluates as false, the SWAN continues
with sequential program flow.
Note 1:See “Example” on page 231 and “The Always Execute field (AE)”
on pag e 231 for further details on program flow when the branch con-
dition evaluates as false.
The SWAN core is optimized to take the ALU branch. Where
the results of an ALU branch operation can be predicted, the
programmer s houl d wr it e the code s uch that br anc hes are ta ken
more often than not.
The ALU Branch Condition field (abc)
The abc instructi on field option (IFO) s pecifies t he ALU branch
condition to be tested during an ALU instruction. The absence
of an abc IFO results in normal sequential program flow.
Instruction Sequence
Address Contents Branch
Condition True Branch
Condition False
NALU Instruction with
branch Executed Executed
N+1 Committed slot, always
executed Executed Executed
N+2 Instruction executed if
branc h cond iti on not met Skipped Executed
(Note 1)
N+3 Instruction executed if
branc h cond iti on not met Skipped Executed
(Note 1)
N+4 Branch target instruction Executed Executed
(Note 1)
N+5 Sequentia l flow contin ues Executed Executed
(Note 1)
230 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
TABLE 52. ALU Branch Conditions for all instructions except
Compare and Min/Max instructions
TABLE 53. ALU Branch Conditions for Compare and Min/Max
instructions
IFO Condition
(branch if…) IFO Condition
(branch if…)
Blank No branch BLZ Less-than zero
BGEZ Greater-than or equal
zero BNZ Not equal zero
BZ Equal zero BNO No overflow flag set
BLEZ Less-than or equal
zero
IFO Condition
(branch if…) IFO Condition
(branch if…)
Blank No branch BALEB rsa < or = rsb
BAGB rsa > rsb BALB rsa < rsb
BAGEB rsa > or = rsb BANEB rsa not equal to rsb
BAEB rsa = rsb
MXT3010 Reference Manua l Version 4.1 231
Instruction op tio ns
Example Consider the following program:
Notes: 1. Locations N+1 and N+3 are the committed slots for the ADD and
BIL instructions respectively. Any instruction can be placed here
except a Branch instruction or any instruction that could generate a
branch (for exam ple, an instruction containin g a non-blank abc fi eld).
2. The L IMD instru ctions are s hown only for convenience in di scuss-
ing possible rearrangement of the program. See “The Always Execute
field ( A E)” on page 231 .
In this pr ogr am , th e ADD inst ruction res ult is predic te d to eval-
uate to no n-zero more oft en than zero. Thus, a majority of ti mes
through the ADD instruction, the SWAN executes the instruc-
tion at the committed slot (N+1), skips over the instructions at
locations N+2 and N+3, and goes directly to the LIMD R4, 0
instruction at location N+4. If the ADD instruction result is zero,
the S WAN executes t he ins tru ction at th e commi tted sl ot (N+1)
and then executes the BIL instruction at location N+2 and the
instruction in its committed slot (N+3).
The Always Execute field (AE)
In the previous example, the ADD instruction result was pre-
dicted to evaluate to non-zero more often than zero. The result-
ing code sequence (N, N+1, N+4, N+5) executes with maximum
ef ficienc y. If th e result of the ADD inst ruct ion evalua tes to zer o
however, the SWAN processor instruction pipeline still fetches
the instructions at N+4 and N+5, but discards the instructions
before they are executed. Discarding these instructions (and
Address Instruction
N-2 LIMD R2, 0
N-1 LIMD R3, 0
NADD r0, r1 BNZ
N+1 (Not e 1)
N+2 BIL $SERVICE_CMD1
N+3 (Note 1)
N+4 LIMD R4, 0
N+5 BIL $SERVICE_CMD2
232 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
fetching the instructions at N+2 and N+3 instead) causes the
equivalent of a two-cycle pipeline stall for the SWAN. The
resulting code sequence is N, N+1, stall, stall, N+2, N+3.
To improve throughput, the MXT3010 provides an “Always
Execute” option. When this option i s enable d (by setting the AE
bit in the branch instruction to 1), the SWAN processor always
executes the instructions gathered by the instruction pipeline,
rather than disc arding them when the bra nch is not taken. If the
AE option is specified, the instructions at N+4 and N+5 are
always ex ecuted followin g the i nstruct ion in the committ ed slot
(N+1) of the ALU branc h. Thus, when us ing t he AE opt ion, the
instru ct ions plac ed a t N+ 4 a nd N+5 must be instruc ti ons whic h
the programmer wants executed regardless of whether the
branch is taken.
To demonstrate use of the AE option, the previous example is
presented again, but with these two minor changes:
• The ADD instruction now has its Always Execute (AE) bit
set.
• The LIMD instructions for R2 and R3 have been moved
down into positions N+4 and N+5 respectively.
The changes are shown in italics for emphasis.
Address Instruction
NADD r0, r1, BNZ, AE
N+1 (See Note 1 in “Example” on page 231)
N+2 BIL $SERVICE_CMD1
N+3 (See Note 1 in “Example” on page 231)
N+4 LIMD R2, 0
N+5 LIMD R3, 0
N+6 BIL $SERVICE_CMD2
N+7 LIMD R4, 0
MXT3010 Reference Manua l Version 4.1 233
Instruction op tio ns
With the Always Execute option enabled, and the ALU branch
condition code evaluated as true, the branch is taken normally.
The sequ ence is: N, N+1, N+4, N+ 5, which is the same as it was
without the Always Execute option enabled.
With the Always Execute option enabled, and the ALU branch
condition code evaluated as false, the branch is not taken, but the
instructions fetched by the pipeline process are executed rather
than being discarded, and no stalls occur. The sequence is: N,
N+1, N+4, N+5, N+2, N+3.
In summary, by using the Always Exec ute opti on and using the
fourth and fifth locations beyond the branch instruction for
instru ction s that are needed reg ardle ss of the branch res ults, the
programmer can enjoy the performance advantages of the
SWAN instruction pipeline without paying a performance pen-
alty when the branch is not taken.
Committed slot
restrictions The ALU branch committed slot (N+1 in the example above)
should not con tain ano ther ALU branch instru ction nor a condi-
tional branch instruction. ALU instructions without branch
options and unconditional branch instructions can be placed in
the co mmitted s lot.
If the Always Execute instruction field option is specified, the
instruction at the branch target address (N+4 in the example
above) and its following instruction should not contain another
ALU branch instruction nor a conditional Branch instruction.
ALU instructions without branch options and unconditional
Branch instructions can be placed in these slots.
234 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
ADD Add Registers
Format ADD (rsa, rsb) rd [MODx] [abc] [AE] [UM]
Purpose • To add two registers together using modulo arithmetic.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eration result (UM field).
Description The ADD i nstruction adds the c ontents of register rsa to the con -
tents of register rsb, placing the result in register rd.
Flags If the source operands have the same sign, and the sign of the
result is different, the Overflow flag is set. Operations specify-
ing the modulo arithmetic option do not affect this flag.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 0 0 0 0 0 rd U
Mabc rsa MODx A
Ersb
Field For Further Information, See
MODx “Modulo arithmetic” on page 226
abc “The ALU Branch Condition field (abc)” on page 229
AE “The Always Execute field (AE) ” on page 231
UM “The Update Memory f ield (UM) ” on page 228
MXT3010 Reference Manua l Version 4.1 235
ADDI Add Register and Immediate
ALU
Instructions
ADDI Add Register and Immediate
Format ADDI (rsa, usi) rd [MODx] [abc] [UM]
Purpose • To add a register and a zero extended 6-bit immediate
together using modulo arithmetic.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eratio n result (U M field).
Description The 6-bit unsigned immedi at e (usi) is ze ro ext en ded and added
to the contents of register rsa using modulo arithmetic. The
result is placed in register rd.
Flags If the source operands have the same sign, and the sign of the
result is different, the Overflow flag is set. Operations specify-
ing the modulo arithmetic option do not affect this flag.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 0 0 1 0 0 rd U
Mabc rsa MODx usi
Field For Further Information, See
MODx “Modulo arithmetic” on page 226
abc “The ALU Branch Condition field (abc)” on page 229
UM “The Update Memory f ield (UM) ” on page 228
236 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
AND And Registers
Format AND (rsa, rsb) rd [MODx] [abc] [AE] [UM]
Purpose • To perform a Boolean AND fu nction on tw o register s using
modulo arithmetic.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eratio n result (U M field).
Description The contents of rsa are AND’ed together with contents of rsb
using modulo arithmetic. The result is placed in register rd.
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 1 0 0 0 0 rd U
Mabc rsa MODx A
Ersb
Field For Further Information, See
MODx “Modulo arithmetic” on page 226
abc “The ALU Branch Condition field (abc)” on page 229
AE “The Always Execute field (AE) ” on page 231
UM “The Update Memory f ield (UM) ” on page 228
MXT3010 Reference Manua l Version 4.1 237
ANDI And Register and Immediate
ALU
Instructions
ANDI And Register and Immediate
Format ANDI (rsa, si) rd [abc] [UM]
Purpose • To perform a Boolean AND function on a register and an
immediate.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eratio n result (U M field).
Description The 10-bit immediate operand (si) is sign extended and AND’ed
with the contents of register rsa, bit for bit. The result is placed
in register rd.
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or ea ch f ie ld a ppea r i n the sec -
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 1 0 1 0 0 rd U
Mabc rsa si
Field For Further Information, See
abc “The ALU Branch Condition field (abc)” on page 229
UM “The Update Memory f ield (UM) ” on page 228
238 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
CMP Compare Two Registers
Format CMP (rsa, rsb) [abc] [AE]
Purpose • To compare the contents of two registers.
• To alter program flow based on the result of the ALU oper-
ation (abc field).
Description The cont ents of register rsa are co mpared to t he conten ts of reg-
ister rsb. B oth registers are treated as unsigned integers. The
result can be used to alter program flow.
The result s of the CMP instru ction are pro duced without regard
for previous compare results.
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or ea ch f ie ld a ppea r i n the sec -
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 110100000000 abc rsa 1111A
Ersb
Field For Further Information, See
abc “The ALU Branch Condition field (abc)” on page 229
Note: This instruction uses Table 53 rather than Table 52
AE “The Always Execute field (AE) ” on page 231
MXT3010 Reference Manua l Version 4.1 239
CMPI Compare Register and Immediate
ALU
Instructions
CMPI Compare Register and Immed iate
Format CMPI (rsa, usi) [abc]
Purpose • To compare the contents of a register and a 10-bit sign
extended immediate.
• To alt er pro gram flo w based on th e resul t of the ALU oper-
ation (abc field).
Description The 10-bit unsigned immediate (usi) has the value of bit 9
extended through bits [31:10] and is compared to the contents of
the rsa register. Both operands are treated as unsigned integers.
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 111100000000 abc rsa usi
Field For Further Information, See
abc “The ALU Branch Condition field (abc)” on page 229
Note: This instruction uses Table 53 rather than Table 52
240 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
CMPP Compare Two Registers with Previous
Format CMPP (r sa, rsb ) [abc] [AE]
Purpose • To compare the contents of two registers.
• To alter program flow based on the result of the ALU oper-
ation (abc field).
Description The cont ents of register rsa are co mpared to t he conten ts of reg-
ister rsb. B oth registers are treated as unsigned integers. The
result can be used to alter program flow.
The Compare with Previous instruction can be used to accom-
plish the compare operation on integers that are larger than 16
bits. With this instruction, the compare should begin with the
most significant halfwords and the simple CMP instruction.
Only use th e abc IFO with the l ast CMPP. For example, to det er-
mine whether a 32-bi t number stored in [R16, R17] is equa l to a
32-bit number stored in [R18,R19]:
CMP r16, r18
CMPP r17, r19, BAEB
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or ea ch f ie ld a ppea r i n the sec -
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 110101000000 abc rsa 1111A
Ersb
Field For Further Information, See
abc “The ALU Branch Condition field (abc)” on page 229
Note: This instruction uses Table 53 rather than Table 52
AE “The Always Execute field (AE) ” on page 231
MXT3010 Reference Manua l Version 4.1 241
CMPPI Compare Register and Immediate with Previous
ALU
Instructions
CMPPI Compare Register and Immediate with
Previous
Format CMPPI (rsa, usi) [abc]
Purpose • To compare the contents of a register and a 10-bit sign
extended immediate
• To alter program flow based on the result of the ALU oper-
ation (abc field).
Description The 10-bit unsigned immediate (usi) has the value of bit 9
extended through bits [31:10] and is compared to the contents of
the rsa register. Both operands are treated as unsigned integers.
This instruction can be used to accomplish the compare opera-
tion on integers that are la rger than 16 bits. W ith th is instruction,
the compare should begin with the most significant halfwords
and the simple CMPI instruction. Only use the abc IFO with the
CMPPI. For example, to determine whether a 32-bit number
stored in (R16, R17) is equa l to 0x012301FF:
CMPI r16, 0x0123
CMPPI r17, 0x01FF BAEB
Since usi is a 10- bit fiel d, 1FF i s th e la rges t number tha t ca n be
used there, unless extension of bit 9 through bits [15:10] is
desired.
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 111101000000 abc rsa usi
Field For Further Information, See
abc “The ALU Branch Condition field (abc)” on page 229
Note: This instruction uses Table 53 rather than Table 52
242 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
FLS Find Last Set
Format FLS rsa, rd [abc] [AE] [UM]
Purpose • To determine the bit position of the MSB bit of a 16-bit
halfword that is set to one.
• To alter program flow based on the result of the ALU oper-
ation (abc field).
Description The contents of register rsa are examined. The bit position of the
most significant bit that is set is placed into rd. If bit 0 is the last
bit set, the value 0x0000 is placed into rd. If bit position 15 is the
last bit set, the value 0x000F is written into rd. If no bit is set, the
value 0x8000 is placed into rd.
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table.
Note A “Find First Set” instruction can be implemented by loading
the halfword to be examined into “R56 Fas t Mem ory Data reg-
ister” on page 212 and performing an FLS instruction specifying
“R43-read Fast Memory Bit Swap register (R42w[8]=0)” on
page 203 as rsa.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 1 1 0 1 1 rd U
Mabc rsa 1111A
E00000
Field For Further Information, See
abc “The ALU Branch Condition field (abc)” on page 229
AE “The Always Execute field (AE) ” on page 231
UM “The Update Memory f ield (UM) ” on page 228
MXT3010 Reference Manua l Version 4.1 243
LIMD Load Immediate
ALU
Instructions
LIMD Load Immediate
Format LIMD rd, li [UM]
Purpose • To initialize a 16-bit register in a single instruction.
• To update a linked locat io n in Fast Memory with the ope ra -
tion result (UM field).
Description The contents of register r d are loaded with th e 16-bit long imme-
diate (li) value.
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or ea ch f ie ld a ppea r i n the sec -
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 1 1 1 1 1 rd U
M0 0 0 li
Field For Further Information, See
UM “The Update Memory f ield (UM) ” on page 228
244 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
MAX Maximum of Two Registers
Format MAX (rs a, rsb) rd [MOD x] [abc] [AE] [UM]
Purpose • To choose the maximum of two registers.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eration result (UM field).
Description The con ten ts of regis ter r sa a re compa red to the con ten ts of reg-
ister rsb. B oth registers are treated as unsigned integers. The
maximum of the two registers is placed into rd.
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 1 1 0 0 0 rd U
Mabc rsa MODx A
Ersb
Field For Further Information, See
MODx “Modulo arithmetic” on page 226
abc “The ALU Branch Condition field (abc)” on page 229
Note: This instruction uses Table 53 rather than Table 52
AE “The Always Execute field (AE)” on page 231
UM “The Update Memory field (UM)” on page 228
MXT3010 Reference Manua l Version 4.1 245
MAXI Maximum of Register and Immed iat e
ALU
Instructions
MAXI Maximum of Register and Immediate
Format MAXI (rsa, usi) rd [abc] [UM]
Purpose • To choose the maximum of a register and an immediate
value.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eratio n result (U M field).
Description The cont ents of regist er rsa are compa red to the 10-bit unsigned
immedia te (usi ) after b it 9 of usi has been e xtended thr ough bits
[31:10]. Both values are treated as unsigned integers. The max-
imum of the t wo registers is pl aced into rd.
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or ea ch f ie ld a ppea r i n the sec -
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 1 1 1 0 0 rd U
Mabc rsa usi
Field For Further Information, See
abc “The ALU Branch Condition field (abc)” on page 229
Note: This instruction uses Table 53 rather than Table 52
UM “The Update Memory field (UM)” on page 228
246 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
MIN Minimum of Two Registers
Format MIN (rsa , rsb) rd [MODx] [ abc] [AE ] [UM]
Purpose • To choose the minimum of two registers.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eration result (UM field).
Description The con ten ts of regis ter r sa a re compa red to the con ten ts of reg-
ister rsb. B oth registers are treated as unsigned integers. The
minimum of the two registers is placed into rd.
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or ea ch f ie ld a ppea r i n the sec -
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 1 1 0 0 1 rd U
Mabc rsa MODx A
Ersb
Field For Further Information, See
MODx “Modulo arithmetic” on page 226
abc “The ALU Branch Condition field (a bc)” on page 229
Note: This instruction uses Table 53 rather than Table 52
AE “The Always Execute field (AE)” on page 231
UM “The Update Memory field (UM)” on page 228
MXT3010 Reference Manua l Version 4.1 247
MINI Minimum of Register and Immediate
ALU
Instructions
MINI Minimum of Register and Immediate
Format MINI (rsa, usi) rd [abc] [UM]
Purpose • To choose the minimum of a register and an immediate
value.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eratio n result (U M field).
Description The cont ents of regist er rsa are compa red to the 10-bit unsigned
immedia te (usi ) after b it 9 of usi has been e xtended thr ough bits
[31:10]. Both values are treated as unsigned integers. The mini-
mum of the two registers is placed into rd.
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 1 1 1 0 1 rd U
Mabc rsa usi
Field For Further Information, See
abc “The ALU Branch Condition field (abc)” on page 229
Note: This instruction uses Table 53 rather than Table 52
UM “The Update Memory field (UM)” on page 228
248 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
OR Or Registers
Format OR (rsa, rsb) rd [MODx] [abc] [AE] [UM]
Purpose • To perform a Boolean OR function on two registers using
modulo arithmetic.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eration result (UM field).
Description The contents of rsa and rsb are OR’ed together using modulo
arit hmetic. The result is placed in register rd .
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or ea ch f ie ld a ppea r i n the sec -
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 1 0 0 0 1 rd U
Mabc rsa MODx A
Ersb
Field For Further Information, See
MODx “Modulo arithmetic” on page 226
abc “The ALU Branch Condition field (abc)” on page 229
AE “The Always Execute field (AE)” on page 231
UM “The Update Memory field (UM)” on page 228
MXT3010 Reference Manua l Version 4.1 249
ORI Or Register and Immediate
ALU
Instructions
ORI Or Register and Immediate
Format ORI (rsa, si) rd [abc] [UM]
Purpose • To perform a Boolean OR function on a register and an
immediate.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eratio n result (U M field).
Description The 10- bit immedia te operan d is sign e xtended an d OR’ed with
the contents of register rsa, bit for bit .
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or ea ch f ie ld a ppea r i n the sec -
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 1 0 1 0 1 rd U
Mabc rsa si
Field For Further Information, See
abc “The ALU Branch Condition field (abc)” on page 229
UM “The Update Memory field (UM)” on page 228
250 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
SFT Shift Signed Amount
Format SFT (rsa, rsb) rd [MODx] [abc] [UM]
Purpose • To shift a register to the right or left based on the sign and
magnitude of the shift amount contained in a second regis-
ter.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eration result (UM field).
Description The co ntent s of r egist er rs a shif t to the right or lef t base d on th e
content s of regi st er bit s rsb(4:0) using modulo ari t hmeti c. The
result is placed in regi ster rd. On a right shift, high-order bits are
zero-filled. On a left shift, low-order bits are zero-filled.
The value of rsb(4:0) is interpreted as a signed shift amount. A
negative number (bit 4=1) causes a shift to the right. A positive
number (bit 4=0) causes a shift to the left. If the number is neg-
ative, the shift amount to the right is represented in two’s com-
plement form. See “Shift amount chart for SFT, SFTLI, and
SFTRI” on page 414.
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or ea ch f ie ld a ppea r i n the sec -
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 0 1 0 0 1 rd U
Mabc rsa MODx 0rsb
Field For Further Information, See
MODx “Modulo arithmetic” on page 226
abc “The ALU Branch Conditi on field ( abc)” on page 229
AE “The Always Execute fi eld (AE)” on page 231
UM “The Update Memory field (UM)” on page 228
MXT3010 Reference Manua l Version 4.1 251
SFTA Shift Right Arithmetic
ALU
Instructions
SFTA Shift Right Arithmetic
Format SFTA (rsa, rsb) rd [MODx] [abc] [UM]
Purpose • To shift a re gister t o the r ight in a n arithm etic fa shion base d
on the shift amount contained in a second register.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eratio n result (U M field).
Description The contents of register rsa shift to the right by the number of bit
positions specified in bits rsb(3:0). See “Shift amount chart for
SFTA” on page 415. The original value of bit rsa(15) is copied
into all MSBs made vacant by the sh ift ope ration, thus accom-
plishing a sign extension/arithmetic shift. The result is placed in
register rd.
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 0 1 0 1 1 rd U
Mabc rsa MODx 0rsb
Field For Further Information, See
MODx “Modulo arithmetic” on page 226
abc “The ALU Branch Conditi on field ( a bc)” on page 229
UM “The Update Memory field (UM)” on page 228
252 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
SFTAI Shift Right Arithmetic Immediate
Format SFTAI (rsa, usa) rd [MODx] [abc] [UM]
Purpose • To shift a re gister t o the r ight in a n arithm etic fa shion base d
on the shift amount in an immediate value.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eration result (UM field).
Description The contents of register rsa shift to the right by the number of bit
positions as specified in the usa field. See “Shift amount chart
for SFTAI” on pa ge 415. The o riginal value of rsa(15 ) is cop ied
into all MSBs made vacant by the sh ift ope ration, thus accom-
plishing a sign extension/arithmetic shift. The result is placed in
register rd.
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 0 1 1 1 1 rd U
Mabc rsa MODx 0 1 usa
Field For Further Information, See
MODx “Modulo arithmetic” on page 226
abc “The ALU Branch Condition field (a bc)” on page 229
UM “The Update Memory field (UM)” on page 228
MXT3010 Reference Manua l Version 4.1 253
SFTC Shift Le ft Circ u lar
ALU
Instructions
SFTC Shift Left Circular
Format SFTC (rsa, rsb) rd [MODx] [abc] [UM]
Purpose • To shift a register to the left in a circular fashion based on
the shift amount contained in a second register.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eratio n result (U M field).
Description The contents of regist er rsa shif t t o the l ef t in a ci rc ul ar f ashi on
based on the value in register rsb(3:0). See “Shift amount chart
for SFTC and SFTCI” on page 414. Bits shifted out of bit posi-
tion 15 are shifted into bit positio n 0.
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or ea ch f ie ld a ppea r i n the sec -
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 0 1 0 1 0 rd U
Mabc rsa MODx A
Ersb
Field For Further Information, See
MODx “Modulo arithmetic” on page 226
abc “The ALU Branch Condition field (abc)” on page 229
AE “The Always Execute field (AE)” on page 231
UM “The Update Memory field (UM)” on page 228
254 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
SFTCI Shift Circular Immediate
Format SFTCI (rsa, usa) rd [MODx] [abc] [UM]
Purpose • To shift a register to the left in a circular fashion based on
an immediate shift amount.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eration result (UM field).
Description The cont ent s of regi st er rsa shif t t o the l ef t in a ci rcular f ash ion
based on the value in the usa field, using modulo a rithmetic. See
“Shift amount chart for SFTC and SFTCI” on page 414. For
example, if MOD16 is specified, bits rd(15:4) are taken from
bits rsa(15:4) while bit rd(3:0), the modulo field, is taken from
the Arit hmetic Logic Unit re sult. Bits shi fted out o f bit p osi tion
15 are shifted into bit position 0.
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 0 1 1 1 0 rd U
Mabc rsa MODx A
E1usa
Field For Further Information, See
MODx “Modulo arithmetic” on page 226
abc “The ALU Branch Condition field (abc)” on page 229
AE “The Always Execute field (AE)” on page 231
UM “The Update Memory field (UM)” on page 228
MXT3010 Reference Manua l Version 4.1 255
SFTRI/SFTLI Shift Right or Left Immediate
ALU
Instructions
SFTRI/SFTLI Shift Right or Left Immediate
Format SFTRI (rsa, usa) rd [MODx] [abc] [UM]
SFTLI (rsa, usa) rd [MODx] [abc] [UM]
Purpose • To shift the contents of register rsa to the right (SFTRI) or
to the l eft (SFTLI) by t he amount specifie d in the uns igned
shift amount (usa). The assembler converts the unsigned
shift amount provided in the command line into a two’s
complement shift amount (tcsa) for compatibility with the
hardware.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eratio n result (U M field).
Description The co ntent s of r egister rs a shif t to the ri ght or lef t base d on th e
contents of the usa field. See “Shift amount chart for SFT,
SFTLI, and SFTRI” on page 414. Bits made vacant by the shift
operation are filled with 0’s.
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 0 1 1 0 1 rd U
Mabc rsa MODx A
Etcsa
Field For Further Information, See
MODx “Modulo arithmetic” on page 226
abc “The ALU Branch Conditi on field ( a bc)” on page 229
AE “The Al ways Execute fi eld (AE)” on page 231
UM “The Update Memory field (UM)” on page 228
256 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
SUB Subtract Registers
Format SUB (rsa, rsb) rd [MODx] [abc] [AE] [UM]
Purpose • To subtract one register from another using modulo arith-
metic.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eration result (UM field).
Description The contents of register rsb are subtracted from the contents of
register rsa. The result is placed in register rd.
Flags The Overflow flag is set when the signs of the source operands
differ, and the sign of the result matches the sign of the second
operand. Operations specifying the modulo arithmetic option do
not affect this flag.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 0 0 0 1 0 rd U
Mabc rsa MODx A
Ersb
Field For Further Information, See
MODx “Modulo arithmetic” on page 226
abc “The ALU Branch Condition field (abc)” on page 229
AE “The Always Execute field (AE)” on page 231
UM “The Update Memory field (UM)” on page 228
MXT3010 Reference Manua l Version 4.1 257
SUBI Subtract Register and Immedia te
ALU
Instructions
SUBI Subtract Register and Immediate
Format SUBI (rsa, usi) rd [M ODx] [abc] [UM ]
Purpose • To subtract an immediate value from a register using mod-
ulo arithmetic.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eratio n result (U M field).
Description The 6-bit unsigned immediate (usi) operand is zero extended
and subtracted from the contents of register rsa, using modulo
arit hmetic. The result is placed in regi ster rd.
Flags The Overflow flag is set when the signs of the source operands
differ, and the sign of the result matches the sign of the second
operand. Operations specifying the modulo arithmetic option do
not affect this flag.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 0 0 1 1 0 rd U
Mabc rsa MODx usi
Field For Further Information, See
MODx “Modulo arithmetic” on page 226
abc “The ALU Branch Condition field (a bc)” on page 229
UM “The Update Memory field (UM)” on page 228
258 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
XOR XOR Registers
Format XOR (rsa, rsb) rd [MODx] [abc] [AE] [UM]
Purpose • To perform a Boolean exclusive-OR function on two regis-
ters using modulo arithmetic.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eration result (UM field).
Description The contents of register rsa are logicall y XOR’ ed with the con-
tents of register rsb, bit for bit using modulo arithmetic. The
result is placed in register rd. For example, if MOD16 is speci-
fied, bits rd(15: 4) are taken from bits r sa(15:4) while bit rd(3:0 ),
the modulo field, is taken from the Arithmetic Logic Unit result .
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 1 0 0 1 0 rd U
Mabc rsa MODx A
Ersb
Field For Further Information, See
MODx “Modulo arithmetic” on page 226
abc “The ALU Branch Condition field (abc)” on page 229
AE “The Always Execute field (AE)” on page 231
UM “The Update Memory field (UM)” on page 228
MXT3010 Reference Manua l Version 4.1 259
XORI XOR Register and Immediate
ALU
Instructions
XORI XOR Register and Immediate
Format XORI (rsa, si) rd [abc] [UM]
Purpose • To perform a Boolean XOR function on a register and an
immediate operand.
• To alter program flow based on the result of the ALU oper-
ation (abc field) and to update a linked location in Fast
Memory w ith the op eratio n result (U M field).
Description The 10-bit i mmediate operand ( si) is sign extended and XOR’ed
with the contents of register rsa, bit for bit. The results are placed
in register rd.
Flags The Overflow flag is not affected by this operation.
Fields A summary of all fields for ALU instructions appears on
page 413. Detailed des cri pt io ns f or ea ch f ie ld a ppea r i n the sec -
tions cite d in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
1 1 0 1 1 0 rd U
Mabc rsa si
Field For Further Information, See
MODx “Modulo arithmetic” on page 226
abc “The ALU Branch Conditi on field ( a bc)” on page 229
UM “The Update Memory field (UM)” on page 228
260 Version 4.1 MXT3010 Reference Ma nual
Arithmetic Logic Unit Instructions
MXT3010 Reference Manua l Version 4. 1 261
CHAPTER 11 Branch Instructions
This chapter describes the suite of Branch instructions provided in
the MXT3010. Branch instructions are one of two methods pro-
vided in the MXT3010 for altering the sequential execution
stream of the SWAN processor. The other method uses branch
condition fields in the ALU instructions to modify instruction
execution flow. For details on ALU branching, see “Arithmetic
Logic Unit Instructions” on page 223.
The first part of this chap ter presents i nformation common to all
branch instructions. This information includes target address,
condition codes, committed slot execution, subroutine linking,
and counter system operations. Following the general branch
information is a list of specific branch instructions, organized by
name. For each br an ch instr uct ion, ther e is a des cr ipt ion, its mne -
monic, purpose, and any information specific to that instruction.
262 Version 4.1 MXT3010 Reference Ma nual
Branch Instructions
Genera l Branch instruction information
Introduction
A simplified version of the basic MXT3010 Branch instruction
format is shown below:
FIGURE 82.Branch instruction format (simplified)
Basic Branc h instruct ions allow th e programmer to speci fy con-
ditional branching decisions which will alter the instruction exe-
cution sequence based on the state of the MXT3010’s internal
subsystems and certain external subsystems. The point to be
tested is speci f ied by the ESS field, a nd t he state ( 1 o r 0) which
will ca use a bra nch is spe cified by the s- bit. Branc h instru ctions
can also be used to manipulate the UTOPIA port’s control
counters via the counter system operation (cso) field.
Target address
The branch tar get addr ess is the address at which execution con-
tinues if the specified branch condition is satisfied. The full
branch target address within Fast Memory is formed from the
Segment ID in the Instruction Base Address register (R53) and
the branch target field.
FIGURE 83.Target address format in Fast Memory
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
Op Code ESS# s C cso -
18 17 16 15 14 13 12 11 10 9876543210
Segment ID Branch Target Field 0 0
MXT3010 Reference Manua l Version 4.1 263
General Branch instruction information
Segment ID The SWAN processor supports an instruction space of 128K
instructions. This 128K instruction space consists of 32 seg-
ments of 4K instructions each. A typical user code set fits within
one segment . The c urrent segment ID (5 bits to represent on e of
32 segments) is changed by writing a new segment number to
the Instruction Base Address register (R53).
Target Field The branch target field is a 12-bit field that specifies the absolute
word address within the current code segment (4096 words) at
which execution is to continue. The branch target field may be
specified in one of three manners, as indicated in the following
table:
Note 1:The Fast Memory shadow register is loaded with the first halfword
returned from memory during a Fast Memory read operation that
specifies the LNK Instruction Field Option. The target field in R58
represents an absolute address to branch to within the active segment.
Condition code (ESS Field)
When using a conditional branch, the programmer can specify
which bit in the External State Signals register (R42) is tested to
determin e the outcome of the branch instruction. If no condi tion
code is sp ecified, the asse mbler codes the ESS fi eld as 1 1 1 1, the
unconditional branch.
TABLE 54. Methods of specifying the Branch target field
Method Instructions Using This Method
As bits [11:0] of the instruction “BI Branch Immed iate” on pag e 272
and “BIL Branch Immediate and Link”
on page 273
As bits [11:0] of the Fast Mem-
ory Sh ad ow r eg is te r (R5 8) .
(Note 1)
“BF Branch Fast Memory Shadow
Register” on page 270 and “BFL
Branch Fast Memory Shadow Register
and Link” on pa ge 27 1
As bits [11:0] of the Branch
register (R59) “BR Branch Register” on page 274 and
“BRL Branch Regi ster and Link” on
page 275
264 Version 4.1 MXT3010 Reference Ma nual
Branch Instructions
TABLE 55. External State Signals register (R42) bits
The logical state identifier (S-Bit)
In addition to specifying the condition code tested via the ESS
field, the programmer uses the logical state identifier, S, to indi-
cate which state of the specified condition code results in the
branch being taken.
TABLE 56. Use of the S-bit
If the programmer knows that a bit will usually be asserted or
will usu all y be de-ass er te d, he or she ca n opt imi ze softwar e fo r
the expec ted br anch con dit ion by c areful ly se lecti ng the l ogica l
sta te that will cause the branch to b e take n.
Committed slot instructions
Execution The SWAN processor implements a delayed branching tech-
nique in order to prevent pipeline delays during branch opera-
tions. When the SWAN processor encounters a branch
ESS Condition ESS Condition
ESS0 ICSI_A ESS8 Sparse event register, bit OR
ESS1 ICSI_B ESS9 RXBUS Y counter > 0
ESS2 TXFULL counter ≤ 2 ESS10 TXFULL counter = full
ESS3 RXBUSY counter ≥ 4 ESS11 DMA1 Outpu t or Queue
stage busy
ESS4 Assigned Cell Flag ESS12 DMA2 Output or Queue
stage busy
ESS5 CSS opera tio n in pro gress ESS13 DMA1 Queue stage busy
ESS6 CIN_BSY ESS14 DMA2 Queue stage busy
ESS7 COUT_RDY blank Unconditional Branch
SBranch Result
0Branch is taken if cond ition = 0
1Branch is taken if cond ition = 1
MXT3010 Reference Manua l Version 4.1 265
General Branch instruction information
instruction, the instruction immediately following the branch,
referred to as the commi tted slot instr uction, is alway s fetched
and entered into the execution pipeline. The programmer can
control whether the committed slot instruction is executed or not
by specifying options in the branch instruction.
The Conditional operator (C-bit)
If a conditional br anch operation is specifie d, and the tested con -
dition code is satisfied (branch is taken), the committed slot
instruction is executed, and the instruction at the branch target
address fo llows the committed slo t instruction.
If a conditional br anch operation is specifie d, and the tested con -
dition code is not satisfied (branch is not taken), the execution
of the committed slot instructi on is determined by the presence
of the Conditional operator, C, in the branch instruction. If the
Conditional operator is absent, the committed slot instruction is
executed. If the Conditional ope rator is prese nt, the commit ted
slot instru ction is not executed , that is , the committed slot
becomes “conditional” as well. In essence, this operator makes
the committed slot instruction part of the targeted branch code,
rather than part of the locally sequenced code.
The Nullify
operator If no ESS condition code is specified, the assembler codes the
ESS field as 1 1 11 (the uncondi tional branch) and codes the S-bit
as zero (0). In this case, the execution of the committed slot
instruction is determined by the presence of the Nullify operator,
N, in th e branch ins truction. Th e absence or presence o f the Nul-
lify op erato r codes the Condition al operat or (C-b it) as a bsent o r
present respectively. If the Nullify/Conditional operator is
absent, the committed slot instruction is executed. If the Nullify/
Conditional operator is present, the committed slot instruction is
not executed. Table 57 on page 266 summarizes the use of the
conditional and nullify operators.
266 Version 4.1 MXT3010 Reference Ma nual
Branch Instructions
TABLE 57. Use of the Conditional and Nullify operators
Committed slot
restrictions for
Branch
instructions
The committed slot instruction of a branch should not be another
branch unless the Nullify operator is specified with the first
branch. In addition, the committed slot instruction of a branch
should not contain an ALU instruction with an abc field.
Examples TABLE 58. Example - conditional branch, condition satisfied
Type of
Branch
Condition
Code
Satisfied? Applicable
Operator Operator
Existence
Committed
Slot
Instruction
Executed?
Conditional Yes None N/A Yes
Conditional No Conditional Absent Yes
Conditional No Conditional Present No
Unconditional N/A Nullify Absent Yes
Unconditional N/A Nullify Present No
Address Instruction Flow Description
0010 ADD r0,r1,r2 0010
0011 BI 0x045 ESS1/1 0011 Branch to 0x045 if condition ESS1
= 1, assume success
0012 ADD r3,r4,r5 0012 Com mi tte d slot instru c tio n is exe-
cuted
0013 ADD r6,r7,r8
… …
0045 ADD r9,r10,r11 0045 Executio n continues at branch tar-
get address
MXT3010 Reference Manua l Version 4.1 267
General Branch instruction information
TABLE 59. Example - conditional branch, condition not met
TABLE 60. Example - unconditional branch
TABLE 61. Example - conditional operator, conditional branch,
cond ition s atisfied
Address Instruction Flow Description
0010 ADD r0,r1,r2 0010
0011 B I 0x045 ESS 1/1 0011 Branch to 0x045 if condition
ESS1 = 1, assume failure
0012 ADD r3,r4,r5 0012 Committed slot instruc tio n is
executed
0013 ADD r6,r7,r8 0013 No branch occurs, sequential
execution continues
… … …
0045 ADD r9,r10,r11
Address Instruction Flow Description
0010 ADD r0,r1,r2 0010
0011 B I 0x 045 0011 Bran ch to 0x04 5, no co ndition c ode
specified
0012 ADD r3,r4,r5 0012 Committed slot instruction is exe-
cuted
0013 ADD r6,r7,r8
… …
0045 ADD r9,r10,r11 0045 Execution continues at branch tar-
get ad dress
Address Instruction Flow Description
0010 ADD r0,r1,r2 0010
0011 BI 0x045 ESS1/1/C 0011 Branch to 0x045 if condition
ESS1 = 1, assume success
0012 ADD r3,r4,r5 0012 Committed sl ot instru ctio n is
executed
0013 ADD r6,r7,r8
… …
0045 ADD r9,r10,r11 0045 Sequential execution continues
at branch target ad dress
268 Version 4.1 MXT3010 Reference Ma nual
Branch Instructions
TABLE 62. Example - conditional operator, conditional branch,
cond ition not satisfied
Subrouti ne linking
The Branch Fast Memory (BF), Branch Immediate (BI), and
Branch Register (BR) instructions are each available with a
return address linking option. If the linking form of the branch
instructi on is specified (BF L, BIL, and BRL instructions), the
address of the instruction immediately following the branch’s
comm itted slot is saved in the Branch register (R59). To return
from the subroutine at a later time, the SWAN processor can
execute a Branch Regist er (BR) instruct ion that re turns the fl ow
of exec ution to continu e from th e point where the linked branch
occurred.
The Branc h regi ster (R59) is onl y writ ten if th e bra nch is taken ,
and is always written with the branch address instruction plus
two, even if the branch was an unconditional branch with the
nullify operator.
Restrictions for
BFL,BIL, BR,
BRL, and the
Branch register
(R59)
Whenever the Branch register (R59) is modified, whether by a
load instruction directed to that register or by a branch instruc-
tion with linking, the modified value is not immediately avail-
able for use. Thus, any instruction which follows the
modification must have at least one intervening instruction
(aft er the modifier) to avoid u sing a stale Branch register value.
Address Instruction Flow Description
0010 ADD r0,r1,r2 0010
0011 BI 0x045 ESS1/1/
C0011 Bran c h to 0x 04 5 if cond itio n
ESS1 = 1, assume failure
0012 ADD r3,r4,r5 Committed slot is nullified due to
C operator
0013 ADD r6,r7,r8 0013 Branch not taken, sequential exe-
cution con tinu e s
… … …
0045 ADD r9,r10,r11
MXT3010 Reference Manua l Version 4.1 269
General Branch instruction information
TABLE 63. Example - Branch with link, and return
Counter system operation
Branch instructions are used to implement all counter system
operations (CSO). These operations are used to increment and
decrement the UTOPIA port control counters TXBUSY,
TXFULL, RXBUSY, and RXFULL. A CSO can be specifie d as
an optional operator on any branch instruction.
If a c onditional branch instr uction is executed, any CSO speci-
fied is unconditional. That is, the counter manipulation is per-
forme d without rega rd to wheth er the cond ition code is satis fied
and the branch is taken.
TABLE 64. The CSO field
Address Instruction Flow Description
0010 ADD r0,r1,r2 0010
0011 BIL 0x04 5 ESS1/1 0011 Branc h to 0x 04 5 if cond itio n
ESS1 = 1, assume success
0012 ADD r3,r4,r5 0012 Committed slot is executed,
0x013=>R59
0013 ADD r6,r7,r8
… …
0045 ADD r9,r10,r11 0045 R59=0x013
0046 BR N 0046 Branch register specified return to
saved address
0047 FOO Committed slot not executed due
to N oper at or
0013 Sequential execu tio n return s to
saved link address
CSO Hex / Binary Value Operation
DRXBUSY E0 / 1110 0000 Decrement RXBUSY counter
DRXFULL E1 / 1110 0001 Decrement RXFULL counter
ITXBUSY C2 / 1100 0010 Increment TXBUSY counter
ITXFULL C3 / 1100 0011 Increment TXFULL counter
270 Version 4.1 MXT3010 Reference Ma nual
Branch Instructions
BF Branch Fast Memory Shadow
Register
Format BF [ESS#/(0|1)/[C]] [cso] [N]
Purpose • To allow for changes in program flow using conditional
branching that tests the MXT3010’s external state signals,
and to increment and decrement UTOPIA control counters
• To provide a service routine address as the first word in a
channel descriptor, and then branch to this service address.
Description Based on the result of a specified condition code, this instruction
can modify the SWAN processor’s sequential flow resulting in a
branch to the target address in the Fast Memory Shadow register .
Subsequent BF instr uctions wi ll stal l the SWAN proces sor until
the first wo rd is read from Fast Memory and copied into the Fast
Memory Shadow (FMSR) register. If an LMFM instruction is
executed, the FMSR is loa ded only if the L M FM specified the
LNK IFO with a non-zero halfword field. After the FMSR has
been loaded by the LMFM, software can read and write the
FMSR and use it as a second Branch register.
Fields A summary of all fields for Branch instructions appears on
page 416. Detailed des cri pt io ns f or ea ch f ie ld a ppea r i n the sec -
tions cite d in the following table
Restrictions See “Committed slot restrictions for Branch instructions” on
page 266.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 0 0 1 0 0 ESS# s C cso 0 00000000000
Field For Further Information, See
ESS# “External State Signals register ( R42) bit s ” on page 264
s“The logical state identifier (S-Bit)” on page 264
C“The Conditional operator (C-bit)” on page 265
cso “Counter system operation ” on page 269
MXT3010 Reference Manua l Version 4.1 271
BFL Branch Fast Memory Shadow Register and Link
Branch
Instructions
BFL Branch Fast Memory Shadow
Register and Link
Format BFL [ESS#/(0|1)/[C]] [cso] [N]
Purpose • To allow for changes in program flow using conditional
branching that tests the MXT3010’s external state signals,
and to increment and decrement UTOPIA control counters.
• To provide a service routine address as the first word in a
channel descriptor, and then branch to this service address.
• To provide subroutine linking capability. (See “Subroutine
linking” on page 268.)
Description The BFL instruction is identical to the BF instruction, except
that the address of the instruction immediately following the
branch’s committed slot is saved in the Branch register (R59).
To return from t he subrout ine at a l ate r time, the SWAN proces-
sor can execute a Bran ch Register (BR) in stru ction that returns
the flow of execution to continue from the point where the
linked branch occurred.
Fields A summary of all fields for Branch instructions appears on
page 416. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table
Restrictions See “Committed slot restrictions for Branch instructions” on
page 266 and “Restrictions for BFL,BIL, BR, BRL, and the
Branch register (R59)” on page 268.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 0 0 1 0 1 ESS# s C cso 0 00000000000
Field For Further Information, See
ESS# “External State Signals register (R42) bits” on page 264
s“The logical state identifier (S-Bit)” on page 264
C“The Conditional operator (C-bit)” on page 265
cso “Counter system operation ” on page 269
272 Version 4.1 MXT3010 Reference Ma nual
Branch Instructions
BI Branch Immedia te
Format BI wadr [ESS#/(0|1)/[C]] [cso] [N]
Purpose • To allow for changes in program flow using conditional
branching that tests the MXT3010’s external state signals,
and to increment and decrement UTOPIA control counters.
Description Based on the results of the specified condition code, the BI
instruction can modify the SWAN processor ’s sequential flow
resulting in a branch to the tar get address in the wadr field [1 1:0]
of the BI instruction.
Fields A summary of all fields for Branch instructions appears on
page 416. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table
Restrictions See “Committed slot restrictions for Branch instructions” on
page 266.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 0 0 0 0 0 ESS# s C cso word addre ss (w adr)
Field For Further Information, See
ESS# “External State Signals register ( R42) bit s ” on page 264
s“The logical state identifier (S-Bit)” on page 264
C“The Conditional operator (C-bit)” on page 265
cso “Counter system operation ” on page 269
wadr “Target address” on page 262
MXT3010 Reference Manua l Version 4.1 273
BIL Branch Immediate and Link
Branch
Instructions
BIL Branch Immediate and Link
Format BIL wadr [ESS#/(0|1)/[C]] [cso] [N]
Purpose • To allow for changes in program flow using conditional
branching that tests the MXT3010’s external state signals,
and to increment and decrement UTOPIA control counters.
• To provide subroutine linking capability. (See “Subroutine
linking” on page 268.)
Description The BIL instruction is identi cal to the BI instruction, excep t that
the address of the instruction immediately following the
branch’s committed slot is saved in the Branch register (R59).
To return from t he subrout ine at a l ate r time, the SWAN proces-
sor can execute a Bran ch Register (BR) in stru ction that returns
the flow of execution to continue from the point where the
linked branch occurred.
Fields A summary of all fields for Branch instructions appears on
page 416. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table
Restrictions See “Committed slot restrictions for Branch instructions” on
page 266 and “Restrictions for BFL,BIL, BR, BRL, and the
Branch register (R59)” on page 268.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 0 0 0 0 1 ESS# s C cso word addre ss (w adr)
Field For Further Information, See
ESS# “External State Signals register (R42) bits” on page 264
s“The logical state identifier (S-Bit)” on page 264
C“The Conditional operator (C-bit)” on page 265
cso “Counter system operation ” on page 269
wadr “Target address” on page 262
274 Version 4.1 MXT3010 Reference Ma nual
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BR Branch Register
Format BR [ESS#/(0|1)/[C]] [cso] [N]
Purpose • To allow for changes in program flow using conditional
branching that tests the MXT3010’s external state signals,
and to increment and decrement UTOPIA control counters.
• To branch to and return from subroutine operations.
Description Based on the results of the specified condition code, the BR
instruction can modify the SWAN processor ’s sequential flow
resulting i n a bra n ch to the t arget address in the Branch register
(R59).
Fields A summary of all fields for Branch instructions appears on
page 416. Detailed des cri pt io ns f or ea ch f ie ld a ppea r i n the sec -
tions cite d in the following table
Restrictions See “Committed slot restrictions for Branch instructions” on
page 266 and “Restrictions for BFL,BIL, BR, BRL, and the
Branch register (R59)” on page 268.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 0 0 0 1 0 ESS# s C cso 0 00000000000
Field For Further Information, See
ESS# “External State Signals register ( R42) bit s ” on page 264
s“The logical state identifier (S-Bit)” on page 264
C“The Conditional operator (C-bit)” on page 265
cso “Counter system operation ” on page 269
wadr “Target address” on page 262
MXT3010 Reference Manua l Version 4.1 275
BRL Branch Register and Link
Branch
Instructions
BRL Branch Register and Link
Format BRL [ESS#/(0|1)/[C]] [cso] [N]
Purpose • To allow for changes in program flow using conditional
branching that tests the MXT3010’s external state signals,
and to increment and decrement UTOPIA control counters.
• To branch to and return from subroutine operations.
• To provide subroutine linking capability. (See “Subroutine
linking” on page 268.)
Description The BR L instr uction is identical to the BR instruc tion, e xcept
that the address of the instruction immediately following the
branch’s committed slot is saved in the Branch register (R59).
To return from t he subrout ine at a l ate r time, the SWAN proces-
sor can execute a Bran ch Register (BR) in stru ction that returns
the flow of execution to continue from the point where the
linked branch occurred.
Fields A summary of all fields for Branch instructions appears on
page 416. Detailed des cri pt io ns f or each fie ld a ppea r i n the sec-
tions cite d in the following table
Restrictions See “Committed slot restrictions for Branch instructions” on
page 266 and “Restrictions for BFL,BIL, BR, BRL, and the
Branch register (R59)” on page 268.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 0 0 0 1 1 ESS# s C cso 0 00000000000
Field For Further Information, See
ESS# “External State Signals register (R42) bits” on page 264
s“The logical state identifier (S-Bit)” on page 264
C“The Conditional operator (C-bit)” on page 265
cso “Counter system operation ” on page 269
wadr “Target address” on page 262
276 Version 4.1 MXT3010 Reference Ma nual
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MXT3010 Reference Manua l Version 4. 1 277
CHAPTER 12 Cell Scheduling Instructions
This chapter describes the Cell Scheduling instructions, POP C,
POPF, PUSHC, and PUSHF. Each command reference page
includes the instruction name, its mnemonic, format, purpose,
descriptions, fields, and restrictions.
Cell Scheduling System ta rget address
All Cell Scheduling instructions utilize the rsb field to specify a
register that contains a 14-bit target address for the Cell Schedul-
ing operation. The target address specifies a location within the
Connecti on ID table, and vi a logic withi n th e MXT3010, a cor re -
sponding b it posit ion in the S coreboard. The comple te Fast Mem-
ory halfword address (FADRS [19:1]) used to access the
Connection ID table is formed using FADRS [19] hardwired to
zero (0), the base address information from bits [1 1:8] of the Cell
Scheduling System Configuration register(R60) as FADRS
[18:15] and the target address from rsb [13:0] as FADRS [14:1].
See Table 6 on page 44.
278 Version 4.1 MXT3010 Reference Ma nual
Cell Scheduling Instructions
POPC Service Schedule
Format POPC rd @rsb
Purpose To identify the Connection ID associated with a specified loca-
tion in the Cell Scheduling System Sc oreboard and to de termine
whether a connecti on i s s che duled for ser vi ci ng at that l ocat i on.
Description The target address specified by register rsb is tra nslat ed into a
Cell Scheduling System Scoreboard bit position. The state of
that bit is copied into the Assigned Cell flag (see below), and the
bit location is cleared. In addition, the Connection ID table is
accessed in Fast Memory, and the associated Connection ID is
read into the destination register, rd.
Assigned Cell flag The Assigned Cell flag output is connected to ESS4 (R42). The
SWAN processor can test to see if a connection was scheduled
to become active i n the curr ent cel l slot t ime by testi ng ESS4. If
ESS4 is se t to 1, then a conn ection was schedul ed for the current
cell time and the processor uses the Connection ID returned
from the Connection ID table to access the Channel Descriptor
for the connection. If the ESS4 is set to 0, no cell is scheduled
for tr ans m is si on at the cell c u r ren t time , and the Connect ion ID
shown in rd is stale information and should be ignored. For more
information on the Cell Scheduling System, see CHAPTER 3
"The Cell Scheduling System" on page 27.
Restrictions The instruction immediately following POPC must not access
the destination register, rd. If a subsequent instruction accesses
rd, the corr ect value is rea d, but a stall may occ ur . See “Register
access rules” on page 22.
The MXT3010 does not support hardware registers (R32-R63)
as the destination of a POPC instruction.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 0 1 0 0 1 rd 0 000 000000 00000 rsb
MXT3010 Reference Manua l Version 4.1 279
POPF POP Fast
CSS
Instructions
POPF POP Fast
Format POPF rd @rsb
Purpose To manipulate the Cell Scheduling System. This instruction
manipulates the internal Scoreboards without accessing the
Connection ID Table in Fast Memory. POPF can improve the
speed of scheduling algorithms that scan multiple Scoreboard
entrie s before co nnecting. By e liminati ng unnecessa ry access es
to Fas t Memory, memory read/write late ncies are avoided.
Description The t arget address specified by register rsb is translated into a
Cell Scheduling System Scoreboard bit position. The state of
that bit is copied into the Assigned Cell flag (see below), and the
bit location is cleared. The Fast Memory is not accessed, and
location rd is not mo dified.
Assigned Cell flag The Assigned Cel l flag o utput is co nnecte d to ES S4 (R42) . The
SWAN processor can test to see if a connection was scheduled
to become active i n the curr ent cel l slot time by testi ng ESS4. If
ESS4 is se t to 1, then a conn ection was scheduled for the curr ent
cell time. If the ESS4 is set to 0, no cell is scheduled for trans-
mission at th e cell current time. For more i nformation on the
Cell Scheduling System, see CHAP TER 3 "The Cell Scheduling
System" on page 27.
Restrictions There must be at least three instructions between one POPF
instruction and another POPF instruction.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 0 1 0 0 1 rd 0 001 000000 00000 rsb
280 Version 4.1 MXT3010 Reference Ma nual
Cell Scheduling Instructions
PUSHC Schedule
Format PUSHC rsa @rsb
Purpose T o dispatch a scheduling request to the Cell Scheduling System.
Description The target address specified by register rsb is tra nslat ed into a
Cell Scheduling System Scoreboard bit position. The Cell
Scheduling System searches for the first available location in the
Scoreboard at or after that bit position and sets the bit for that
location to reserve it. It also writes the 16-bit user-defined Con-
nection ID from the rsa register into the Connection ID table
location corresponding to the reserved Scoreboard bit. The
address contained in rsb is the earliest that the connection can
become activ e.
During a P USHC instruction, if the Scoreboard i s full, the Cell
Scheduli ng Syste m returns an erro r by se ttin g bit 15 in the CSS
Configur ati on regis te r ( R60) . For more infor m at ion on t he Cell
Scheduling System, see CHAP TER 3 "The Cell Scheduling Sys-
tem" on page 27.
Note Execution of this instruction updates the Scheduled Address
register (R61).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 0 1 0 0 0 000000 0000 rsa 00000 rsb
MXT3010 Reference Manua l Version 4.1 281
PUSHF Push Fast
CSS
Instructions
PUSHF Push Fast
Format PUSHF rsa @rsb
Purpose To manipulate the Cell Scheduling System. This instruction
manipulates the internal Scoreboards without accessing the
Connection ID table in Fast Memory. PUSHF can improve the
speed of scheduling algorithms that rely on reserved Scoreboard
locations when fixing bandwidth connections. By eliminating
unnecess ary accesses to Fast Memory, memory read/write laten-
cies are avoided.
Description The t arget address specified by register rsb is translated into a
Cell Scheduling System Scoreboard bit position. The Cell
Scheduling System searches for the first available location in the
Scoreboard at or after that bit position and sets the bit for that
location to reserve it. No new Connection ID is written into the
Connection ID table location corresponding to the reserved
Scoreboard bit. Rather, the existing Connection ID at that loca-
tion wil l be scheduled . The a ddr ess contai ned in r sb i s t h e e arl i -
est that the connection can become active.
Duri ng a PUSHF instructi on, if the Score board i s full, t he Cell
Scheduli ng Syste m returns an error by sett in g bit 15 in the CSS
Configur ati on regis te r ( R60) . For more infor m at ion on t he Cell
Scheduling System, see CHAP TER 3 "The Cell Scheduling Sys-
tem" on page 27.
Note Execution of this instruction updates the Scheduled Address
register (R61).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 0 1 0 0 0 000000 0001 rsa 00000 rsb
282 Version 4.1 MXT3010 Reference Ma nual
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MXT3010 Reference Manua l Version 4. 1 283
CHAPTER 13 Dir ect Memory Access
Instructions
This chapter describes the Direct Memory Ac cess (DMA) instruc-
tions, beginning with information common to all DMA instruc-
tions. This information includes op codes, byte counts, and
control fields. Following the general information is a list of spe-
cific DMA instr uctions, or ganized by name. For each instr uction,
there is a description, its mnemonic, purpose, and any information
specific to that instruction.
284 Version 4.1 MXT3010 Reference Ma nual
Direct Memory Access Instructions
Genera l DMA instruction information
Introduction
A simplified version of the basic MXT3010 DMA instruction
format is shown below:
FIGURE 84.DMA instruction format (simplified)
Basic DMA instructions allow t he programmer to add re ad or
write DMA transfer requests to either the Port1 or Port2 com-
mand queue by selecting the appropriate Op Code. The length of
the transfer and various control features are determined by the
Byte Count ( BC) Instructi on Field Option and th e Control fiel d.
In addition, a feature is provided whic h perm its the Alternate
Byte Count register (R52) to provide control of the transfer
length a nd other feat ures. The rla , rsa, and rsb f ields identif y the
registers used in the transfer.
Op codes for DMA instructions
The following table applies:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
Op Code i BC rla rsa Control rsb
TABLE 65. Op codes for DMA instructions
Bits [31:29] B its [28:27] Description
011 00 DMA Read, Port1 (DMA1R instruction)
011 01 DMA Write , Po rt1 (DMA 1 W instruc ti on )
011 10 DMA Read, Port2 (DMA2R instruction)
011 11 DMA Write , Po rt2 (DMA 2 W instruc ti on )
MXT3010 Reference Manua l Version 4.1 285
General DMA instruction information
The RLA increment bit (i-bit)
The MXT3010 DMA instructions include an option that pro-
vides an automatic in crement to th e target rl a register upon dis-
patch of the DMA instruct ion. The inc rement i s 64 modulo 512
and saves t he SWAN process or t he cod e nee ded t o adva nce the
rla register to the next cell buffer in the Cell Buffer RAM follow-
ing each DMA transfer . T o make this option available, T arget Bit
0101 (“DMA Plus Control”) in the Mode Configuration Regis-
ter (R42 ) must be set to 1. (See “R42-wri te Mode Configu ration
register” on page 201.)
Use of bit 26 The instruction used and the status of the DMA Plus Control
af fect how bit 26 is coded by the assembler . The possibilities are
shown in the table.
Timing
considerations for
access ing rla
If the instruction immediately following a DMA operation with
rla increment accesses the rla register, it will see the non-incre-
mented value. If the second following instruction accesses the
rla register, it will see the incremented or the non-incremented
TABLE 66. Use of Bit 26
Instruction
Used DMA Plus
Control Bits [26] Description
DMA1R
DMA1W
DMA2R
DMA2W
Disabled x This bit is available as the highest
order bit of the byte count field
DMA1R
DMA1W
DMA2R
DMA2W
Enabled 0 Do not increment the rla regist er
DMA1R+
DMA1W+
DMA2R+
DMA2W+
Enabled 1 Increment rl a register upon com-
pletion of DMA operation
286 Version 4.1 MXT3010 Reference Ma nual
Direct Memory Access Instructions
value depending on the correlation of pipeline stalls and the
DMA commitment. After the second following instruction, all
further instructions will see the incremented rla value.
Note: The informatio n in this table d iffe rs from that in Table 3 on page 23
and “Avoiding stale rla values” on page 315 be cause those refer to
simple read/write opera tio n, wh ereas th is ta ble refers to DMA o per-
ation.
The Byte Count instruction field option (BC)
The Byte Count f ie ld i ndicates t he length1 of the DMA t ransf er
in accordance with the following table:
TABLE 67. Timing chart for accessing rla after a DMA
Instruction rla value
DMA instruction non-incremented value
Instruction following the DMA non-incremented value
Second instruction following the DMA indeterminate
Third instruction following the DMA incremented value
Subse quent instr uctions f ollowing the DMA incremented value
1. See “Use of odd BC values” on page 287.
TABLE 68. Use of the BC field
Without DMA Plus Enabled With DMA Plus Enabled
Bits [26:19] Description Bits [25:19] Description
0 Transfer 0 bytes. 0 Transfer 0 bytes.
1 Transfer 1 byte 1 Transfer 1 byte
2 Transfer 2 byt es 2 Transfer 2 bytes
3 Transfer 3 byt es 3 Transfer 3 bytes
-- --
127 Tr a nsfer 12 7 bytes 127 Transfer 127 byte s
-- T ransfers larger than 127 bytes are
not available when the DMA Plus
Control is en abled.
255 Transfer 255 bytes
T ransfers larger than 255 bytes are
not available.
MXT3010 Reference Manua l Version 4.1 287
General DMA instruction information
The “Use Alternate Byte Count Register (R52)” Feature
If the programmer does not specify the BC/# Instruction Field
Option, t he length of th e transfer and the CRC t reatment will be
control led by t he Alte rnate Byte Count /ID re giste r (R52) rathe r
than by the BC field, CRCX, and CRCY bits in the instruction.
Use of odd BC values
The following restrictions apply to DMA operations using odd
BC values:
• DMA1R using BC = odd# transfers BC bytes
• DMA1W, DMA2R, DMA2W using BC = odd# transfers
BC-1 bytes.
The Port1 bu s supports byte operations onl y on read operatio ns.
The Port2 bus does not support byte operations at all, and will
always round down the BC field.
The Control instruction field option
Bits [9: 5] of ea ch DMA ins tructio n are the Cont rol fiel d, which
has th e following format:
FIGURE 85.Control field format)
Note:The CRCX, CRCY, and ST bits apply only to the DMA1R,
DMA1R+, DMA1W, and DMA1W+ instructions.
98765
IBI CRCX CRCY POD ST
288 Version 4.1 MXT3010 Reference Ma nual
Direct Memory Access Instructions
The bit definitions for the Control byte are given in the follow-
ing table:
TABLE 69. Use of the Control byte
Bit Name Function
9 IBI The Instruction Byte coun t Indicato r is an internal
flag used by the MXT301 0. If the programmer has
specified a BC/# value, the MXT3010 sets IBI and
uses the BC/# and CRCX/CRCY values to control
the transfer. If the programmer has not specified a
BC/# value, the MXT3010 clears IBI and uses the
values in R52 to control the transfer.
8 CRCX If clear, CRC32 Partial Result registers are not modi-
fied. If set, a CRC32 Partial Result is generat ed based
on CRC32PRX register’s value and the resu lt is
deposited into CRC32PRX (R44/R45).
7 CRCY If clear, CRC32 Partial Result registers are not modi-
fied. If set, a CRC32 Partial Result is generat ed based
on CRC32PRY register’s value and the result is
deposited into CRC32PRY (R46/R47)
6 POD If clear, no UTOPIA Port Post Operative Directive
(POD) is performed. If set, TXBUSY is incremented
upon th e co mpletion o f DMA read s, an d RXFULL is
decremented upon completion of DMA writes.
5 S T If clear , the DMA is performed in normal fashion. If
set , a “Sile nt Transfer” is per f o r med. I n a Si l e n t
T ransfer, a DMA is performed which includes CRC
calculatio n, but do es not require data from the host or
other host intervention.
MXT3010 Reference Manua l Version 4.1 289
DMA1R Direct Memory Operat ion - Po rt1 Read
DMA
Instructions
DMA1R Direct Memory Operation - Port1 Read
DMA1R+ Direct Memory+ Operation - Po rt1 Read
Formats DMA1R rsa/rsb, rla [BC/#][CRC {X,Y}][POD][ST]
DMA1R+ rsa/rsb, rla [BC/#][CRC {X,Y}][POD][ST]
Purpose To initiate direct memory read operations on Port1
Description Executio n of this instruction causes a DMA read operation t o be
written into the Port1 DMA command queue.
Fields The register selected by the rla field contains the Cell Buffer
RAM address. See “R egi st er load address (rla fiel d)” on
page 314. The rsa and rsb fields determine the Port1 memory
address as shown in Table 24 on page 111. A summary of all
fields for DMA instructions appears on page 417. Detailed
descri ptions for each fiel d appear in the sections ci ted in the fol-
lowing tab l e.
Notes: For use of bit 26, see “Use of bit 26” on page 285.
To make the DMA1R+ instruction available, Ta rget Bit 5
(“DMA Plus Control”) in the Mode Configuration Register
(R42) must be set to 1.
For timing considerations concerning accesses to the rla register,
see “Timing considerations for accessing rla” on page 285.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 1 1 0 0 BC rla rsa Control rsb
Field For Further Information, See
i“The RLA increment bit (i-bit)” on page 2 85
BC “The Byte Count instruction field option (BC)” on page 286
Control “The Control instruction field option” on page 287
290 Version 4.1 MXT3010 Reference Ma nual
Direct Memory Access Instructions
DMA1W Direct Memory Operation - Port1 Write
DMA1W+ Direct Memory+ Operation - Port1 Wr ite
Format DMA1W rsa/rsb, rla [BC/#][CRC {X,Y}][POD][ST]
DMA1W rsa/rsb, rla [BC/#][CRC {X,Y}][POD][ST]
Purpose To initiate direct memory write operations on Port1
Description Execution of this instruction causes a DMA write operation to
be written into the Port1 DMA command queue.
Fields The register selected by the rla field contains the Cell Buffer
RAM address. See “R egi st er load addre ss (r la fi el d)” on
page 314. The rsa and rsb fields determine the Port1 memory
address as shown in Table 24 on page 111. A summary of all
fields for DMA instructions appears on page 417. Detailed
descri ptions for each field appe ar in the sectio ns cited in the fol-
lowing tab l e.
Notes: For use of bit 26, see “Use of bit 26” on page 285.
To make the DMA1W+ instruction available, Target Bit 5
(“DMA Plus Control”) in the Mode Configuration Register
(R42) must be set to 1.
For timing considerations concerning accesses to the rla register,
see “Timing considerations for accessing rla” on page 285.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 1 1 0 1 BC rla rsa Control rsb
Field For Further Information, See
i“The RLA increment bit (i-bit)” on page 2 85
BC “The Byte Count instruction field option (BC)” on page 286
Control “The Control instruction field option” on page 287
MXT3010 Reference Manua l Version 4.1 291
DMA2R Direct Memory Operat ion - Po rt2 Read
DMA
Instructions
DMA2R Direct Memory Operation - Port2 Read
DMA2R+ Direct Memory+ Operation - Po rt2 Read
Format DMA2R rsa/rsb, rla [BC/#][POD]
DMA2R+ rsa/rsb, rla [BC/#][POD]
Purpose To initiate direct memory read operations on Port2
Description Executio n of this instruction causes a DMA read operation t o be
written into the Port2 DMA command queue.
Fields The register selected by the rla field contains the Cell Buffer
RAM address. See “R egi st er load address (rla fiel d)” on
page 314. The rsa and rsb fields determine the Port2 memory
address as shown in Table 29 on page 137 and Table 31 on
page 139. A summary of all fields for DMA instructions appears
on page 417. Detailed descriptions for each field appear in the
sect ions cited in the follow ing table.
Notes: For use of bit 26, see “Use of bit 26” on page 285.
To make the DMA2R+ instruction available, Ta rget Bit 5
(“DMA Plus Control”) in the Mode Configuration Register
(R42) must be set to 1.
For timing considerations concerning accesses to the rla register,
see “Timing considerations for accessing rla” on page 285.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 1 1 1 0 BC rla rsa Control rsb
Field For Further Information, See
i“The RLA increment bit (i-bit)” on page 2 85
BC “The Byte Count instruction field option (BC)” on page 286
Control “The Control instruction field option” on page 287
292 Version 4.1 MXT3010 Reference Ma nual
Direct Memory Access Instructions
DMA2W Direct Memory Operation - Port2 Write
DMA2W+ Direct Memory+ Operation - Port2 Write
Format DMA2W rsa/rsb, rla [BC/#][POD]
DMA2W rsa/rsb, rla [BC/#][POD]
Purpose To initiate direct memory write operations on Port2
Description Execution of this instruction causes a DMA write operation to
be written into the Port2 DMA command queue.
Fields The register selected by the rla field contains the Cell Buffer
RAM address. See “R egi st er load addre ss (r la fi el d)” on
page 314. The rsa and rsb fields determine the Port2 memory
address as shown in Table 29 on page 137 and Table 31 on
page 139. A summary of all fields for DMA instructions appears
on page 417. Detailed descriptions for each field appear in the
sect ions cited in the follow ing table.
Notes: For use of bit 26, see “Use of bit 26” on page 285.
To make the DMA2W+ instruction available, Target Bit 5
(“DMA Plus Control”) in the Mode Configuration Register
(R42) must be set to 1.
For timing considerations concerning accesses to the rla register,
see “Timing considerations for accessing rla” on page 285.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 1 1 1 1 BC rla rsa Control rsb
Field For Further Information, See
i“The RLA increment bit (i-bit)” on page 2 85
BC “The Byte Count instruction field option (BC)” on page 286
Control “The Control instruction field option” on page 287
MXT3010 Reference Manua l Version 4. 1 293
CHAPTER 14 Load and Stor e Fast Memory
Instructions
This chapter describes the Load and instructions for Fast Memory .
Each command reference page includes the ins truction name , its
mnemonic, purpose, and any information specific to that instruc-
tion. The common information includes descriptions, fields, and
notes.
294 Version 4.1 MXT3010 Reference Ma nual
Load and Store Fast Memory Instructions
General information for Load and Store Fast Memory
instructions
Introduction
Simplified versions of the MXT3010 Load and Store instruction
formats for Fast Memory operations are shown below.
TABLE 70. Load Fast Memory instruction format
TABLE 71. Store Fast Memory instruction format
Loading The software tables and data structures stored in Fast Memory
are ac cessed by the SWAN proce ssor th rough the LMFM (Load
Multiple from Fast Memory) instruction. The SWAN processor
uses the #HW field to specify the number of halfwords to be
fetched and the rsa and rsb fields to specify the Fast Memory
byte addr es s at whi ch t he trans fe r wi ll beg in. I n r es pons e t o th e
LMFM instruction, the Fast Memory interface controller will
write the halfwords returne d from memory into the SWAN’s
register file beginning with register rd and continuing with rd+1,
rd+2, etc. until the designated number of halfwords have been
transf erred . Th us, th e LMFM ins tructio n a llows the S WAN pro-
cessor to transfer up to 16 halfwords from the Fast Memory into
the regist er file in a single instruction.
If the LNK instructi on field option is specifi ed, the fast memory
interface control ler links t h e l oade d r egi st ers to the locat ions in
Fast Memory from which their contents we re read. ALU in struc-
tions which modify these registers can force the modifications to
be written back to Fast Memory by specifying the UM (update
memory) option. Thus, the UM funct ion allows the SWAN pro-
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Op Code rd LNK 00 Z rsa #HW rsb
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Op Code 000000000 rsa #HW rsb
MXT3010 Reference Manua l Version 4.1 295
General information for Load and Store Fast Memory instructions
cessor to update the data st ructure in Fast Me mo ry wi thout exe-
cuting a de dicated Store instru ction. In addition , use of the LNK
optio n also causes the first halfword read fro m memory to be
read into the Fast Memory Shadow Register (R58), where it can
be used by BF/BFL instructions. (See “BF Branch Fast Memory
Shadow Regi ster” on page 270 and “BFL Branch F ast Memor y
Shadow Register and Link” on page 271.)
Storing Fast M emory wr ites can be accompl is hed utili zin g t he memory
update function described above or by utilizing the Store half-
word to Fast Memory (SH FM) instruction. Execution of the
SHFM instruction causes the Fast Memory interface controller
to write the halfword contained in the Fast Memory Data regis-
ter (R56) into the halfword addressed by the byte address con-
tained in registers rs a and rsb. A more pow erful store
instruction, Store Register Halfword (SRH) is also available.
Further details are provided in “SRH Store Register Halfword”
on page 312.
Transfer size (the #HW field)
The #HW field specifies the number of 16-bit halfwords to load
from, or store to, Fast Memory.
Restrictions If the LNK instruction field option is enabled, there are some
restri ctions to the va lues that can be us ed in this field . See “Lim-
itations on #HW when linki ng” on page 300. If the LNK instruc -
tion field option is not enabled, any 0-16 halfword transfer is
permitt ed, but the pr ogr ammer must ens ure th at a multi ple ha lf -
word entity is aligned on a 4-byte boundary.
296 Version 4.1 MXT3010 Reference Ma nual
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Fast Memory address (the rsa and rsb fields)
Bits [3:0] of the register specified in the rsa field contain bits
[19:16] of the Fast Memory Byte Address at which transfers
begin. Bits [15:0] of the register specified in the rsb field contain
bits [15 :0] o f the Fast Memo ry Byte Addre ss at which tr ansfe rs
begin. This information is summarized in the following table:
Address masking (the Z-bit)
A masking option, the Z-bit, provides improved access for
aligned data structures. When set, this bit causes the least signif-
icant bits of the indicated rsb register to be masked out during
the Fast Memory accesses, effectively forcing the transfer to
start on an aligned structure boundary. When the Z-bit is clear,
no masking is done.
The nu mber of bits mask ed to zero is determined b y the choice
of destination register rd, as shown in the following table.
TABLE 72. Use of the rsa and rsb fields
Field Register Bits Used Function
rsa [3:0] Fast Memory Address (FADRS) [19:16]
rsb [15:0] Fast Memory Address (FADRS ) [15:0]
TABLE 73. Use of the Z-bit
Z-bit Function
0 Data rea d from Fast Memory at rsa [3:0] | rsb [15:0]
1 Data rea d from Fast Memory at rsa [3:0] | rsb [15:n+1] | 0[n:0]
rd = 16 masks rsb [4:0]
rd = 24 masks rsb [3:0]
rd = 28 masks rsb [2:0]
rd = 30 masks rsb [1:0]
rd = 31 masks rsb [0]
MXT3010 Reference Manua l Version 4.1 297
General information for Load and Store Fast Memory instructions
The Z-bit option permits an optimization to SWAN code for
accessi ng the Conn ectio n ID (CID )Table wherein CIDs may be
stored in such a manner that the retri eved CID value can be used
for bot h high an d low Fa st Memor y addre ss as rsa and rs b. T his
enhancemen t ca n save se veral ins truct ions i n the cr itic al PUSH/
POP code segme nts. Two examples are giv en to clari fy the con -
cept.
Z-bit usage
example 1 Assume it is desired to access Fast Memory location 0x50000.
Normally, this would require that rsa contain 0x0005 and rsb
contain 0x0000. However, performing:
LMFM rd @ rsa/rsa 16HW Z
will produce the following address:
Use of the Z-bit option causes masking of [4:0], producing:
This is the desired address. Thus, this is a simplified example of
“CIDs may be stored in such a manner that the retrieved CID
value can be used for both high and low Fast Memory address
as rsa and rsb.”
Z-bit usage
example 2 Channel descriptors are organized in Fast Memory in 32-byte
aligned data structures starting at 0x20000 and ending at
0x7FFE0. Due to the 32-byte alignment, bits [4:0] of the first
18 17 16 15 14 13 12 11 10 9876543210
101 0000 0000 0000 0000
rsa rsb
18 17 16 15 14 13 12 11 10 9876543210
101 0000 0000 0000 0101
rsa rsa
18 17 16 15 14 13 12 11 10 9876543210
101 0000 0000 0000 0000
rsa rsa with [4:0] masked
298 Version 4.1 MXT3010 Reference Ma nual
Load and Store Fast Memory Instructions
entry i n a chan nel descript or ar e always zero. Thus, sixte en bit s
[20:5] un iquely define the first entr y of each chann el descriptor.
The MXT3010 constructs a Connection ID (CID) for each
descriptor by using bits [15:5] from the descriptor address as
CID bits [15:5] and using bits [20:16] from the descriptor
address as CID bits [4:0]. This creation of a unique 16-bit Con-
nection ID is important fo r use wi th the POPC instructi on.
When a POPC instruction is used to determine whether a con-
nection has been scheduled at a particular scoreboard location,
and a conn ection has be en scheduled, the Connectio n ID will be
returned in the rd regist er specified in the POPC inst ruction.
A typical channel descriptor address, the Connection ID created
from it, and the results of a POPC instruction are shown in Fig-
ure 86.
FIGURE 86.Z-bit usage example
Channel Descriptor Address in Fast Memory
Example: 0x3CAE0
0000 0000 0000 0011 1100 1010 1110 0000
1100 1010 1110 0011
1100 1010 111 0 0011
xxxx xxxx xxx0 0011 1100 1010 1110 0000
0 0000
mask
MXT3010 hardware creates the
address [15:5]|[20:16]
POPC rd@rsb
This instruction loads rd with the
LMFM r16@rd/rd 16HW Z
This instruction uses rd for both rsa and rsb
Connecti on ID by concatenating
but Z option zeroes the lower five bits
Connection ID from the table
MXT3010 Reference Manua l Version 4.1 299
General information for Load and Store Fast Memory instructions
When an LMFM instruction is issued with the Z option enabled,
the cont ent s of rd can be use d for both t he r sa and r sb r egi st er s.
As shown in the figure, specifying rd for both rsa and rsb, in con-
juncti on with the mas king a ction cause d by the Z option , re-c re-
ates the original channel descriptor address.
Destination register (the rd field)
The rd field specifies the destination register for the initial half-
word transfer . Subsequent halfwords will be transferred to rd+1,
rd+2, etc. The register specified in the rd field can be any regis-
ter, subject to the restrictions in “Choice of rd register” on
page 300 and “Limitations on #HW when linking” on page 300
Linking (the LNK bit)
If this bit i s set, the linking o ption is enabled. As indicated
above, if the LNK option is enabled, the fast memory interface
controller links the loaded registers to the locations in F ast
Memory from which their contents were read. ALU instructions
which modify these registers can force the modifications to be
written back to Fast Memory by specifying the UM (update
memory) option. In add ition, use of the LNK option als o causes
the first halfword re ad from me mory to be read into the Fast
Memory Shadow Register (R58), where it can be used by BF/
BFL instructions.
Example of LNK
usage T wo very simplified channel descriptors are shown in Figure 87.
In this example, P1_HI and P1_LO f o r m a poi nt er to where th e
next received cell on that VC should go, and CRC_HI and
CRC_LO are the accumulated CRC. Upon arrival of a cell for
this particular VC (VC0 for example), the program performs a
Load Multiple Fast Memory (LMFM) instruction, loading four
halfwords into four locations starting at rd= R28. If the LNK
300 Version 4.1 MXT3010 Reference Ma nual
Load and Store Fast Memory Instructions
instruction field option is specified in the LMFM instruction,
and the contents of R29 are subsequently changed using an
instr uction with an Update Memory (UM ) option, the value of
P1_LO will be changed. This provides a convenient way to
update the pointer in response to arrival of a new cell.
Choice of rd
register While the linking option can be used with any register desig-
nated as the destination register rd, registers R16, R24, R28,
R30, and R31 ar e most c ommonly used, as the MXT3010 log ic
is optimized for memory updates using these registers. When a
hardware register (R32-R63) is used as the destination of an
LMFM inst ruction, load ing take s an addit ion al cycle compar ed
to loading a software register (R0-R31).
Limi tatio ns on
#HW when linking The choic e of rd has an effect on t he number of su bsequent loca -
tions that can be linked, and hence places a limit on the size of
the transfer (#HW). The following table applies:
Note 1: 0 HW is a legal transfer size. An LMFM operatio n spec ifying 0
HW can establish a link without actually loading information
from memory.
FIGURE 87.Simplified Chan ne l De scriptors
Addre ss Contents Loaded to VC
xxx00 P1_HI R28
0
xxx02 P1_LO R29
xxx04 CRC_HI R30
xxx06 CRC_LO R31
xxx08 P1_HI
1
xxx0A P1_LO
xxx0C CRC_HI
xxx0E CRC_LO
TABLE 74. Limits on #HW when linking to rd
rd Permissible Values of #HW
R16 16 or less
R24 8 or less
R28 4 or less
R30 2 or less
R31 1 or less (Note 1)
MXT3010 Reference Manua l Version 4.1 301
General information for Load and Store Fast Memory instructions
As an aid to understanding the Update Memory feature when
used in conjunction with the LMFM instruction, and to under-
stand t he da ta s truct ure a lignmen ts r equired to make be st u se of
this feature, the following section provides a detailed explana-
tion of th e l ogi c us ed by t he MXT3010 to a ccompl i sh t he mem-
ory update function.
Generation of UM
addresses I n order to do a memory upda te to a linke d locati on in the chan -
nel des criptor ta ble1 in Fast Memory , the MXT3010 logic needs
to know t he location of the desired channel de scriptor with in the
table, and the offset of the location to be updated within the
desired channel descriptor.
The leas t signif icant fou r bits of th e destina tion regi ster number
(in binary) are inverted and saved in hardware as a mask,
“lfm_adrs_mask [3:0]”. In addition to the mask, the linked
address is also saved in hardware as “lfm_linked_adrs [19:1]”.
Masking i s per formed on t he li nked a ddress to ensure tha t it fol -
lows the memor y alignment requ irements shown in T able 75 on
page 304. The masking equation is as follows:
lfm_linked_adr s [19:1] = {rsa [3:0], rs b [15:5 ], (rsb [4:1] & rd [3:0] )}
When a subsequent instruction with the UM option enabled is
performed, the MXT3010 computes the address linked to the
register “exe_reg_dest[5:0]” as follows:
lfm_write_adrs[19:0] ={[lfm_linked_adrs [19:5],
(lfm_linked_adrs[4:1]|(exe_reg_dest[3:0]&lfm_adrs_mask)),0
}
UM update
example Let us assume that a channel descriptor has been stored in Fast
Memory beginning at location 0x08010, and let us further
assume that an LMFM instruction has been issued to transfer
1. While this section specifically describes the channel descriptor table, the
princip les in vo lv ed a pp ly to a l ink e d l oca tio n in any ta b le in Fast Mem ory.
302 Version 4.1 MXT3010 Reference Ma nual
Load and Store Fast Memory Instructions
four ha lf words, with r d = R24. Exampl e code t o s et up this situ -
ation is:
LIMD rsa, 0x000O
LIMD rsb, 0x8010
LMFM R24, rsa/rsb 6HW LNK
Presented as a figure, the result is:
Bits [19:0] for 0x8010 are 0000 1000 0000 0001 0000, so
“lfm_linked_adrs [19:1]” is 0000 1000 0000 0001 000-. The
destination register (rd) is R24, which in binary is 11000. The
least significant four bits (1000) invert to be 0111 or 0x0007,
which is stored as “lfm_adrs_mask [3:0]”. With these numbers
saved in hardware, the MXT3010 is ready for subsequent
instructions that manipulate any of these registers and specify
the Update memory (UM) option. An example of such an
instruction is the following:
ADDI R27, 1, R27 UM
In response to this instruction, the MXT3010 must not only
increment the value in R27, it must also update the correspond-
ing Fast Memory location with the new incremented value.
FIGURE 88.Channel Descriptor for LMFM and UM example
Address Contents Loaded to
8010 STATUS_A R24
8012 STATUS_B R25
8014 P1_HI R26
8016 P1_LO R27
8018 CRC_HI R28
801A CRC_LO R29
MXT3010 Reference Manua l Version 4.1 303
General information for Load and Store Fast Memory instructions
The register that was update d is referre d to in the hard ware as
“exe_reg_dest[5:0]”. F or R27, the bina ry value [5:0] is: 01 101 1.
Bits [3:0] are 1011. The equation to be solved is:
lfm_write_adrs[19:0} = [lfm_linked_adrs [19:05],
(lfm_linked_adrs[4:1]|(exe_reg_dest[3:0]&lfm_adrs_mask)),0
}
The information known is:
And-ing exe _reg_de st[3: 0] with l fm_adrs _mask give s 0011; or-
ing that with lfm_linked_address [4:1] gives 1011; concatenat-
ing that result with lfm_linked_address [19:5] and concatenat-
ing an LSB of 0 gives 0000 1000 0000 0001 0110 = 0x8016.
Reference to Figure 88 on page 302 will confirm that the Fast
Memory location to updated when R27 is updated is indeed at
address 0x8016.
Memory
alignment
requirements
The various and-ing, or-ing, inverting, and masking functions
performed by the MXT3010 hardware to correctly generate
addresses for the Update Memory function place requirements
on the alignment of da ta str uctures c onstruct ed in F ast Memory.
Specifically, to use the LMFM instruction with the LNK option
enabl ed, the fo llowin g memor y alig nment requi re ment s are r ec-
ommended:
lfm_linked_address [19:0] 0000 1000 0000 0001 0000
lfm_linked_address [19:1] 0000 1000 0000 0001 000
lfm_linked_address [19:5] 0000 1000 0000 000
lfm_lin ke d_ a ddr e ss [4:1 ] 1000
exe_reg_dest[3:0] 1011
lfm_adrs_mask 0111
304 Version 4.1 MXT3010 Reference Ma nual
Load and Store Fast Memory Instructions
Memory
alignment
example
If the LMFM instruction is to be used with the LNK option
enabled, and th e size of the tr ansfe r (#HW) is to b e greater than
8 half-words, rd must be R16 (see “Limits on #HW when linking
to rd” on page 300). If R16 is used, and subsequent use of the
UM feature i s desired, the data st ructure being copi ed from Fast
Memory should be aligned to a 32-byte boundary.
TABLE 75. Memory alignment requirements
rd FADRS [4:0]
R16 00000
R24 X0000
R28 XX000
R30 XXX00
R31 XXXX0
MXT3010 Reference Manua l Version 4.1 305
Instructions for accelerating CRC operations
Instructions for accelerating CRC operations
The Store Register Halfword (SRH) instruction greatly acceler-
ates the handling of partial CRC results during AAL5 packet
segmentation or reass embly. Because DMA operations func tion
independently of SWAN code execution once they have been
started, firmware is able to start processing the next channel
descri ptor in paral lel with the DMA transf er (and CRC accumu-
lation) of the previous channel as soon as the DMA operation
has be en committed for that previous channel. Th is parallelism
provides pr oce ssi ng t ime to t he SWAN that might o therwi se be
wasted waiting for the transfer to complete. However, it is still
necessary to save the results of the partial CRC accumulation at
the concl usion o f a DMA transf er. These pa rtia l resu lts must be
saved in what is now the previously serviced channel descriptor .
If the SRH instruction is not used, the SWAN processor must
save the address of the channel descriptor in which the partial
result s wer e to be store d, re cover that addr es s upon completi on
of the DMA ope ration, and finally s tore the part ial resul ts at the
appropriate offset within the channel descriptor . This saving and
recovering process requires seven instructions per cell time in
each direction. Hence, use of the SRH instruction is highly rec-
ommended, as it eliminates the need for saving and recovering
the partial CRC address information.
At the time that a DMA read or write operation with CRCX or
CRCY indicated is initiated to Port 1, the MXT3010 automati-
cally stores t he addre ss contai ned in t he inte rnal FAST Memory
Link Address register into a temporary holding register. There
are two holding registers – one for CRCX operations and one for
CRCY operations. Typically the FAST Memory Link Address
regist er (withi n the MXT30 10 logic) will have t he curren t Chan-
nel Descriptor address. Thus, as a DMA1R with CRC or a
DMA1W with CRC is executed, the address of the current
Channel De scriptor is automatically se t aside.
306 Version 4.1 MXT3010 Reference Ma nual
Load and Store Fast Memory Instructions
Upon completion of the DMA transfer, the SRH instruction is
used to write the contents of the partial CRC registers (R44/ R45
or R46/ R47) to FAST Memory using the address contained in
either the CRCX hol ding r egist er or t he CRCY ho lding regis ter
as the base address for the transfer. An offset can be specified
with the SRH instruction, allowing the partial results to be
placed at the appropriate field within the Channel Descriptor.
The SRH instruction is based on the Store Halfword to Fast
Memory (SHFM) instruction, and the SHFM instruction is now
a valid subset of the more flexible SRH instruction. In addition
to the rsa and rsb fields found in the SHFM instruction, the SRH
instructi on has three special fields:
Alternate address (the adr field)
The adr field (bits [20:19] of the SRH instruction) specifies the
location from which the Fast Memory address is obtained. The
following table applies:
The valid entries for this field are CRCX and CRCY. If neither
is specified, the assembler codes bits [20:19] as 00 if no lsbs
field is specified, or as 01 if an lsbs field is specified. The lsbs
field is described on page 307.
TABLE 76. Use of the adr field
Bits [20:19] Function (Target Fast Memory Address is:)
00 rsa/rsb (same as SHFM instruction)
01 rsa/rsb with lsbs field substituted for address bits [4:0]
10 CRCX holding register with lsbs field appended
11 CRCY holding register with lsbs field appended
MXT3010 Reference Manua l Version 4.1 307
Instructions for accelerating CRC operations
Hardware register (reg field)
The reg f i eld selects one of e igh t h ardware r egi st ers that ca n be
written to Fast Memory. This is in contrast to the more limited
SHFM, where onl y the con tents of the Fas t Memory Data regis -
ter (R56) can be written to Fast Memory. The following table
applies:
Least significant bits (the lsbs field)
In adr mode 00 (SH FM compatibilit y mode), this field is
unused. I n the other ad r modes (01,10,11), lsbs c ontains the f ive
least significant bits of the target Fast Memory address. This is
not an index field; rather, it is a bit sub stitution fie ld.
TABLE 77. Use of the reg field
Bits [20:19] Function (Register to be Written to Fast Memory)
000 Register R56 (same as SHFM instruction)
001 Register R37
010 Register R38
011 Register R39
100 Register R44
101 Register R45
110 Register R46
111 Register R47
308 Version 4.1 MXT3010 Reference Ma nual
Load and Store Fast Memory Instructions
LMFM Load Multiple from Fast Memory
Format: LMFM r d @rsa/rsb #HW [LNK]
Purpose • To initiate a burst transfer of data from Fast Memory
directly into the SWAN processor’s register file.
• To automatically link the data structure and the registers to
reflect register modifications back to memory through the
Update Me mory options with ALU instructi ons that modify
the loaded registers.
Description W ith the LMFM instruction, the Fast Memory interface control-
ler can initiate a block fetch operation to transfer #HW half-
words from Fast Memory directly into the CPU’s regis ter file.
The transfer begins at the address specified in register s rsa a nd
rsb.
Restrictions When an LMFM instruction is executed, a sequential update to
registers rd, rd+1, and subsequent registers, takes place. As a
result, instructions following an LMFM must not access regis-
ters t hat are i n the proce ss of bein g updated. Table 78 sho ws the
register updating process for the following LMFM instruction:
LMFM r2 r15/r16 4HW
In the example, move instructions are shown as typical instruc-
tions that might be used to access registers R2, R3, R4, and R5.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 1 0 1 0 1 rd LNK 00 Zrsa #HW 0rsb
MXT3010 Reference Manua l Version 4.1 309
LMFM Load Mu ltip le from Fast Memory
Fast Memory
Instructions
For registers R0:R15, the programmer must follow the sequen-
tial order shown or undefined results will occur. For example,
attempt ing to access regis ter rd+1 immedia tely after t he LMFM
will produce erroneous results.
For regis ters R16:R31, a re gister con trol scoreboa rding syste m,
implemented in hardware, protects registers rd+1 and beyond.
This system introduces stalls if the access restrictions are not
followed. Since registers R16:R31 are intended for the manipu-
lation of cha nnel desc ripto rs, the r egist er con tro l sco rebo ardin g
system simplifies the programming model.
Without LNK, any 0-16 halfword transfer is legal, but make sure
the burst transfer does not cross a 32-byte boundary.
Stalls Hardw are interlocks stall the CPU if it tries to access a register
the Fast Memo ry Interface Contro ller is changing. Th e CPU
remain s stalled until the Fast Memory Interface Contr oller
writes a new value into the register.
TABLE 78. Restrictions on access to rd registers after LMFM
Address
St atu s at time of instruction executio n
Instruction rd (R2) r d+1 (R3) rd+2 (R4) rd+3 (R5)
000 0 LMFM r2 r16/r17 4HW Ch a nging Undefined Undefined Unde fined
0004 MV r2 r17 NewaChanging Undefined Undefined
0008 MV r3 r18 New NewbChanging Undefined
000C MV r4 r19 New NewbNewbChanging
0010 MV r5 r20 New NewbNewbNewb
a. The MXT301 0EP stalls for four in ternal clock cycles before execu ting the MV r2 r17 instruc-
tion to ensure th at register rd has valid data . If desired, four instructions that do not acces s r2
through r5 can be inserted between the LMFM and the MV r2 r17 instruction.
b. Availability of new data at this time requires that access to rd has occurred since the LMFM.
310 Version 4.1 MXT3010 Reference Ma nual
Load and Store Fast Memory Instructions
Fields Detailed descriptions for each field appear in the sections cited
in the following table.
Field For Further Information, See
#HW “Transfer size (the #HW field)” on page 295
rsa “Fast Memory address (the rsa and rsb fields)” on page 296
rsb “Fast Memory address (the rsa and rsb fields)” on page 296
Z-bit “Address masking (the Z-bit)” on page 296
rd “Destination r e gister (the rd field)” on page 299
LNK-bit “Linking (the LNK bit)” on page 299
MXT3010 Reference Manua l Version 4.1 311
SHFM S to re Halfword to Fast Memory
Fast Memory
Instructions
SHFM Store Halfword to Fast Memory
Format SHFM @rsa/rsb
Purpose • To sto re a halfword to Fast Memory.
Description SHFM causes the Fast Memory interface controller to write the
halfword contain ed in the Fast Me mory Data reg iste r(R56) into
the halfword addressed by the byte address contained in regis-
ters rsa and rsb.
The Fast Memory interface controller writes the halfword into a
write buffer first so the SWAN processor can continue execut-
ing.
Stalls A write buffer full stall occurs if the four deep write buffer is full
when the SHFM instruction is executed.
Fields Detailed descriptions for each field appear in the sections cited
in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 1 0 1 1 1 000000000 rsa 00000 rsb
Field For Further Information, See
#HW “Transfer size (the #HW field)” on page 295
rsa “Fast Memory address (the rsa and rsb fields)” on page 296
rsb “Fast Memory address (the rsa and rsb fields)” on page 296
312 Version 4.1 MXT3010 Reference Ma nual
Load and Store Fast Memory Instructions
SRH Store Register Halfword
Format: SRH @reg [CRCXADR, CRCYADR, rsa/rsb] [lsbs/#]
Purpose: • To store a halfword to Fast Memory, using any of several
registers as a direct source.
• To greatly accelerates the handling of partial CRC results
during AAL5 packet segmentation or reassembly.
Description: In typical use, upon completion of the DMA transfer, the SRH
instruction is used to write the contents of the partial CRC reg-
isters (R44/ R45 or R46/ R47) to FAST Memory using the
address contained in either the CRCX holding register or the
CRCY holding register as the base address for the transfer. An
offset can be specified with the SRH instruction, allowing the
partial results to be placed at the appropriate field within the
Channel Descriptor.
Fields Detailed descriptions for each field appear in the sections cited
in the following table.
Note By setting adr=00 and reg=000, the SRH instruction becomes
the original SHF M instruction.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 1 0 1 1 1 00000 adr reg rsa lsbs rsb
Field For Further Information, See
adr “Alternate address (the adr field ) ” on page 306
reg “Hardware register (reg field)” on page 307
rsa “Fast Memory address (the rsa and rsb fields)” on page 296
lsbs “Least significant bits (the lsbs field)” on page 307
rsb “Fast Memory address (the rsa and rsb fields)” on page 296
MXT3010 Reference Manua l Version 4. 1 313
CHAPTER 15 Load and Stor e Internal RAM
Instructions
This chapter describes the Load and Store instructions for internal
RAM, beginnin g with inf ormation common t o all Load a nd S tore
instructions. Following the general information is a list of specific
Load and S tore instruct ions, orga nized by name. For each inst ruc-
tion, the re i s a des cri pt ion, its mnemoni c, purpose, and any inf or-
mation specific to that instruction.
314 Version 4.1 MXT3010 Reference Ma nual
Load and Store Internal RAM Instructions
General information for Load and Store internal RAM
instructions
Introduction
Simplified versions of the MXT3010 Load and Store instruction
formats for internal RAM operations are shown below.
TABLE 79. Load internal RAM instruction format
TABLE 80. Store internal RAM instruction format
The Load and Store internal RAM instructions move data
between the SWAN register set and memory internal to the
MXT3010. The int ernal memorie s addre ssabl e by th ese in struc -
tions are the Cell Buffer RAM and the Cell Scheduling System
Scoreboa rd. The load and store (LD, ST) instruc tions move on e
16-bit halfword between a sp ecifie d register and a target half -
word address. The load and store double (LDD, STD) instruc-
tions move two 16-bit halfwords between two consecutive
registers and two consecutive target addresses. Load and Store
instructions that swap bytes and/or half-words are also avail-
able.
Register load address (rla field)
Choices for the
rla register Four hardware registers and four fixed value registers can be
specified as the rla register. The hardware registers are R48,
R49, R50, and R51. The fixed value re gisters are GA, GB, GC,
and GD. The compiler codes the choice of rla into the 3-bit rla
field. The G regi sters poin t to di f fer ent 6 4-byte bloc ks in gath er
space (page 317). In many instances, this allows software to
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
Op Code rd 0rla 0000 Swap IDX 00000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
Op Code 0000 Swap 0rla rsa IDX 00000
MXT3010 Reference Manua l Version 4.1 315
General information for Load and Store internal RAM instructions
access g ather space wi thou t modify ing one o f the ha rdware reg -
isters.
TABLE 81. Use of the rla field
Avoiding stale rla
values To prevent a stale value of the rla register from being used to
gene rate the internal RAM address, separate a load o r store
instruction that uses R48, R49, R50, or R51 from a preceding
instruction that modifi es the regi ster by at least one instruct ion.
This intervening instruction cannot be an LD or LDD instruction
to a hardware register - see “Register access rules” on page 22.
The index field (IDX)
This field can be used to index into a table from a base address.
Using IDX to calculate the target address
The target address is formed from the content of the specified rla
register and an immediate index value contained in the index
field of the instru ction. The inde x field, IDX, is excl usive-or -ed
with the rla content; see Figure 89.
rla value Register selected Regi s ter co nt e nt
000 R48 Variable
001 R49 Variable
010 R50 Variable
011 R51 Variable
100 GA 0x0400
101 GB 0x0420
110 GC 0x0440
111 GD 0x0460
316 Version 4.1 MXT3010 Reference Ma nual
Load and Store Internal RAM Instructions
FIGURE 89.XOR operation betwee n IDX and rla
The upper bit s [15:06 ] of the rla content are unc hanged, an d bit
0 is fo rce d to z ero. As a resu lt of this XOR funct ion, t he loa d or
store instruction can access any 16-bit halfword within the 64-
byte bl ock addres sed by the rla regi ster by ch anging the value in
the IDX field and leaving the contents of the rla register
unchanged.
Note that although the index field is treated as a five-bit half-
word index, the value used in the SWAN assembler (IDX/#) is
always specified as a byte index and is transformed into a word
by the assembler. The IDX/# field can take even values from
IDX/0 to IDX/ 62. The assembler inserts the appr opriate fi ve-bit
value into the instruction field.
Selecting the Cell Buffer RAM or the Scoreboard
The tar get address s elects t he 16-bit h alfword f or a load or store
instruction, or the first of two consecutive 16-bit halfwords for
a load or store double instruction. The two internal RAMs that
can be accessed with these instructions are the Cell Buffer RAM
and the Cell Scheduling System Scoreboard. Bit 11 of the rla
register selects the RAM to be accessed.
Bit 11 Internal RAM selected
0Cell Buffer RAM
1Cell Schedul ing System Scoreboard
15 14 13 12 11 10 09 08 07 06 05 04 0 3 02 01 00
0
rla
IDX/#
Target
0
MXT3010 Reference Manua l Version 4.1 317
General information for Load and Store internal RAM instructions
Cell Buffer RAM accesses
Select ing an
access method The Cell Buffer RAM can be accessed with linear or gather
access methods. Bit 10 of the rla register selects the access
method of the Cell Buffer RAM; it does not affect the access
method for the Cell Scheduling System Scoreboard.
Linear method
accesses In linear method accesses, the Cell Buffer RAM is treated as a
simple contiguous memory 1024 bytes in length. Bits [9:1] of
the target address select the 16-bit halfword within this space.
Gather method
accesses Since the ce lls stored in th e Cell Buffe r RAM are 52 or 56 bytes
in lengt h, the last e ight bytes of each 64-byt e sectio n of the Cell
Buffer RAM are normally unused. In gather method accesses,
the last eight bytes of each 64-byte section appear as a contigu-
ous 128-byt e block of memory. The first 16-bi t halfword of this
block is at address 0x0400 of the gather address method. The
last 16-bit halfword is at address 0x047E. Figure 90 illustrates
this addressing method. Thus, gather access recovers discontin-
uous regions of Cell Buffer RAM memory into one continuous
address space. This is not ad dit ional spa ce, bu t rather a met hod
of making use of small pieces of existing space.
Bit 10 Cell Buffer RAM method selected
0Linear
1Gather
318 Version 4.1 MXT3010 Reference Ma nual
Load and Store Internal RAM Instructions
FIGURE 90.Gather method accesses
Cell Scheduling System Scoreboard accesses
The Cell Scheduling System Scoreboard is a 16Kbit memory
accessed as 512, 32-bit words. With two exceptions, do not
modify the Scorebo ard con tent wi th these instru ctions. Rather,
use the Cell Scheduling System instructions (PUSHC, POPC,
PUSHF, POPF) to maintain coherency of the Scoreboard con-
tent with other Cell Scheduling System mechanisms. The two
excepti ons when l oad (LD, LDD) an d store (STD1) inst ructions
can be used are:
1. When initially clearing the scoreboard
1. There is no support for 16-bit writes to the Scoreboard. Use only STD
instructions when writing to the Scoreboard. Do not use ST.
Cell Store 0
Cell Store 1
Cell Store 15
0x0000
0x0038
0x0040
0x0078
0x0080
0x03C0
0x03B8
0x0400
0x03F8
0x0400
0x0408
0x0410
0x0480
0x047E
MXT3010 Reference Manua l Version 4.1 319
Byte swap support
2. When using portions the scoreboard space for applications
other than cal l sche dul ing
Byte swap support
The load and store instructions provide a programmable func-
tion for swapping bytes in half-word and word data structures
for systems with mixed big-endian and little-endian entities. The
instructions perform byte swapping on either half-words (16-
bit) or words (32-bit) as the data is read from Cell Buffer RAM
memory (load) or written to Cell B uffer RAM memo ry (store).
The Swap field
Bits [11:10] of Load instructions and bits [21:20] of Store
instru ctions provi de a Swap fiel d. Two swap b yte and swap ha lf-
word functions can be asserted for any LD, LDD, ST, or STD
instru ction t hat accesse s the Cell Buff er RAM . T hese func ti ons
are not defined for the internal Scoreboard memory. Although
all combinations of swap byte and swap halfword functions are
valid in the SWAN core, not all combinations are useful. The
syntax a nd instruc tion field s are the s ame for the byte swappi ng
instructions as for the ordinary load and store instructions.
320 Version 4.1 MXT3010 Reference Ma nual
Load and Store Internal RAM Instructions
The following tables list the most useful byte-swapping load and
store instructions.
TABLE 82. Byte-swapping Load instructions
TABLE 83. Byte-swa pping Store instructions
Instruction Bits
[11:10] Source
addr Dest
addr Source
data Dest
data Function
LD r0 GA 00 0x400 r0 aa55 aa55 Normal regis-
ter load
LDSB r0 GA 01 0x400 r0 aa55 55aa Byte swap 16-
bit operand and
load regi ster
LDD r0 GA 00 0x400
0x402 r0
r1 aa55
bb66 aa55
bb66 Normal double
register load
LDDSBH r0 GA 11 0x400
0x402 r1
r0 aa55
bb66 66bb
55aa Byte swap 32-
bit operand and
load regi ster
LDDSB r0 GA 01 0x400
0x402 r0
r1 aa55
bb66 55aa
66bb Byte swap two
16-bit operands
and load regis-
ters
Instruction Bits
[21:20] Source
addr Dest
addr Source
data Dest
data Function
ST r0 GA 00 r0 0x400 aa55 aa55 Normal register
store
STSB r0 GA 01 r0 0x400 aa55 55aa By te swap 16-bit
opera nd and r e g-
ister store
STD r0 GA 00 r0
r1 0x400
0x402 aa55
bb66 aa55
bb66 Normal doubl e
register store
STDSBH r0 GA 11 r1
r0 0x400
0x402 aa55
bb66 66bb
55aa Byte swap 32-bit
operand and store
register
STDSB r0 GA 01 r0
r1 0x400
0x402 aa55
bb66 55aa
66bb Byte swap two
16-bit operands
and st or e re g i s -
ters
MXT3010 Reference Manua l Version 4.1 321
LD Load Register
Internal RAM
Instructions
LD Load Register
Format LD rd @rla [IDX/#]
Purpose Use LD to read a 16-bit halfword from an internal memory.
Description The co ntent of registe r rla and t he Index field ar e used t o form a
target source address in internal memory. The memory is read
and register rd is loaded with the result.
Notes IDX/# must be specified as a byt e index value eve n though bit 0
is ignored.
LD instructions which perform byte-swaps and/or half-word-
swaps ar e also avai lable . See “Byt e swap supp ort” on pa ge 319.
Restrictions apply to the use of LD instructions with hardware
registers. See “Register access rules” on page 22.
Stalls If the Cell Bu ffe r RAM is unavailable due to concurre nt Port1,
UTOPIA Port, and Port2 Cell Buffer RAM accesses, the CPU
stall s if it tries to acces s the destination register of the LD before
its data is returned. The C PU can continue executing instruc-
tion s as l ong as i t does no t tr y to access rd before rd is ret urned
from the Cell Buffer RAM. To guarantee the best overall
throughput, separate Cell Buffer RAM loads and instructions
that access the loaded data by two or more instruction slots.
Fields Detailed descriptions for each field appear in the sections cited
in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 1 0 0 0 0 rd 0 rla 0000 Swap IDX 00000
Field For Further Information, See
Swap “The Swap field” on page 319
IDX “The inde x fi e ld ( ID X ) ” on pag e 315
322 Version 4.1 MXT3010 Reference Ma nual
Load and Store Internal RAM Instructions
LDD Load Double Register
Format LDD rd @rla [IDX/#]
Purpose Use LD D to rea d two 16-bit ha lfword s from internal memory.
Description The co ntent of registe r rla a nd the In dex fiel d are use d to form a
target source address in internal memory. The memory is read
and register rd is loaded with the result. Register rd+1 is also
loaded with a 16-bit halfw ord rea d from internal memory. The
internal memory address for this halfword is obtained by exclu-
sive-or-ing 0x0002 with the calculated target address.
Notes IDX/# must be specified as a byte i ndex value even tho ugh bit 0
is ignored.
Instructions that perform byte-swaps and/or half-word-swaps
are also available. See “Byte swap support” on page 319.
Restrictions apply to the use of LDD instructions with hardwa re
registers. See “Register access rules” on page 22.
Stalls If the Cell Bu ffe r RAM is unavailable due to concurre nt Port1,
UTOPIA Port, and Port2 Cell Buffer RAM accesses, the CPU
stall s if it tries to access the destination regi ster of the LD before
its data is returned. The C PU can continue executing instruc-
tions as l ong as i t does not try to acce ss rd befor e rd is ret ur n ed
from the Cell Buffer RAM. To guarantee the best overall
throughput, separate Cell Buffer RAM loads and instructions
that access the loaded data by two or more instruction slots.
Fields Detailed descriptions for each field appear in the sections cited
in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 1 0 0 0 1 rd 0 rla 0000 Swap IDX 00000
Field For Further Information, See
Swap “The Swap field” on page 319
IDX “The inde x fi e ld ( ID X ) ” on pag e 315
MXT3010 Reference Manua l Version 4.1 323
ST Store Register
Internal RAM
Instructions
ST Store Register
Format ST rsa @rla [IDX/# ]
Purpose Use ST to write a 16-bit halfword to intern al memory.
Description The co ntent of registe r rla and t he Index field ar e used t o form a
tar get addr es s i n i n te rna l me mory. The content of re gi st er rsa i s
written to this memory location.
Notes IDX/# must be specified as a byt e index value eve n though bit 0
is ignored.
ST instructions which perform byte-swaps and/or half-word-
swaps ar e also avai lable . See “Byt e swap supp ort” on pa ge 319.
Stalls All Cell Buf fer RAM writes are written into a write buf fer . If the
Cell Buffer RAM is unavailable due to concurrent Port1, UTO-
PIA port, and Port2 Cell Buffer RAM accesses, the CPU stalls
if it tries to write to the Cell Buffer RAM while the write buffer
is busy. The CPU can e xecute inst ructi ons as long as it do es not
try to write to the Cell Buffer RAM while the write buffer is
busy. The write buffer can hold a single ST or STD instruction.
Fields Detailed descriptions for each field appear in the sections cited
in the following table.
Restrict ions Since this is a 16-bit i nst ruction , it shoul d no t be used to access
space in the Scor eb oard RAM unle ss the pro gram perfor ms t he
save and restore operations necessary to access a 32-bit quantity .
Use STD instead.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 1 0 0 1 0 000000 Swap 0rla rsa IDX 00000
Field For Further Information, See
Swap “The Swap field” on page 319
IDX “The inde x fi e ld ( ID X ) ” on pag e 315
324 Version 4.1 MXT3010 Reference Ma nual
Load and Store Internal RAM Instructions
STD Store Double Register
Format STD rsa/rsb @rla [IDX/#]
Purpose Use ST D to write two 1 6-bit h alfwor ds into internal memory.
Description The co ntent of registe r rla a nd the In dex fiel d are use d to form a
tar get addr es s i n i n te rna l me mory. The content of re gi st er rsa i s
written to this memory location. The content of register rsb is
also written to internal memory. The memory address for this
halfword is obtained by exclusive-or ring 0x0002 with the cal-
culated target address.
Notes IDX/# must be specified as a byte i ndex value even tho ugh bit 0
is ignored.
Versions of this instruction which perform byte-swaps and/or
half-word-swaps are also available. See “Byte swap support” on
page 319.
Stalls All Cell Buf fer RAM writes are written into a write buf fer . If the
Cell Buffer RAM is unavailable due to concurrent Port1, UTO-
PIA port, and Port2 Cell Buffer RAM accesses, the CPU stalls
if it tries to write to the Cell Buffer RAM while the write buffer
is busy. The CPU can e xecute inst ructi ons a s long as it do es not
try to write to the Cell Buffer RAM while the write buffer is
busy. The write buffer can hold a single ST or STD instruction.
Fields Detailed descriptions for each field appear in the sections cited
in the following table.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0 1 0 0 1 1 0000 Swap 0rla rsa IDX rsb
Field For Further Information, See
Swap “The Swap field” on page 319
IDX “The inde x fi e ld ( ID X ) ” on pag e 315
MXT3010 Reference Manua l Version 4. 1 325
CHAPTER 16 Swan Instruction Refer ence
Examples
This chapter provides examples for the following instructions:
• Add and Subtract
•Branch
•Logical
• Load and Store
•Shift
Also provided is a section of miscellaneous examples.
326 Version 4.1 MXT3010 Reference Ma nual
Swan Instruction Reference Examples
Add and Subtract examples
The Add and Subtract examples include:
Formats The exa mples in this sect ion use the ADD, ADDI, OR and SUB
instructions, which have the following formats:
ADD (rsa, rsb) rd [MODx][abc][UM]
ADDI (rsa, usi) rd [MODx][abc][UM]
OR (rsa, rsb) rd [MODx][abc][UM]
SUB (rsa, rsb) rd [MODx][abc][UM]
16-bit arithmeti c ADDI (R12, 23) R4
The unsigned immediate, 23 decimal, is zero extended and
added to the contents of R12. The result is placed into R4. The
Overflow flag register is set if an overflow results from the oper-
ation.
Modulo arithmetic ADD (R8, R9) R10 MOD64, UM
The conte nts of R8 are added to the contents of R9. The result i s
placed into R10. Since MOD64 arithmetic is specified, the
result s are a co mb ina ti on o f t he ALU r es ult and R8 so urce bit s.
R10(15:6) are taken from R8(15:6) while R10(5:0) are taken
from the ALU result bits(5:0). The final result of the operation
updates Fas t Memory because t he update memory (UM) opt ion
is specified. The Overflow flag register remains unchanged
when modulo arithmetic is used.
• 16-bi t ari t h meti c •ALU branching
• Modulo arithmetic
MXT3010 Reference Manua l Version 4.1 327
Add and Subtrac t examples
ALU branching .loc 0x0000
ADDI (R11, 0x001A) R18 MOD32, BZ
OR (R0, R1) R2
BI $RECOVER
NOP
OR (R5, R6) R7
OR (R5, R6) R7
The constant 0x001A is added to the contents of R11. Since
MOD32 arithmetic is specified, the result is a combination of
the ALU result and R11 source bits. R18(15:5) are taken from
R11(15:5) while R18(4:0) are taken from the ALU result (4:0).
If bits (4:0) of R18 are zero, the branch is taken, regardless of
the state of R18(15:5). The branch results in program flow of
0x0000, 0x0001, 0x0004, 0x0005. If bits (4:0) of R18 are not
zero, the branch is not taken and program flow proceeds as
0x0000, 0x0001, 0x0002, 0x0003. The instructions at 0x0004
and 0x0005 are fetched but not executed. The Overflow flag reg-
ister remain s uncha nged when modulo a rith metic is use d. If the
always execute (AE) instruction field option (IFO) was included
with the ADDI instruction, 0x0004 and 0x0005 are executed
even if the branch condition is false.
328 Version 4.1 MXT3010 Reference Ma nual
Swan Instruction Reference Examples
Branch examples
The Branch examples include:
Formats The exa mples in thi s section use th e ADD, BFL, BI, BIL, BRL,
LIMD, and OR instructions, which have the following formats:
ADD (rsa, rsb) rd [MODx][abc][UM]
BFL [ESS#/(0|1)/[C]][(cso)][N]
BI wadr [ESS#/(0|1)/[C]][(cso)][N]
BIL wadr [ESS#/(0|1)/[C]][(cso)][N]
BRL [ESS#/(0|1)/[C]][(cso)][N]
LIMD rd, li [UM]
OR (rsa, rsb) rd [MODx][abc][UM]
Branching and
the committed
slot
BI 0x024A ESS10/1/C
ADD R0, R1, R2
Branch t o addr ess 0 x024A if Ex terna l S tat e Sign al ESS10 i s set
to “1.” Execute the committed slot instruction (ADD) only if the
branch is taken (/C).
Branch with link BIL $SCHEDULE ESS10/1/C
ADD R0, R1, R2
OR R2, R3, R4
• Branching and the c ommit-
ted slot • Branch with counter
control
• Branch with link • Branch with shadow
address
MXT3010 Reference Manua l Version 4.1 329
Branch examples
Branch to the sub routine $SCHEDULE if Exte rnal S tate Signal
ESS10 is s et to “1.” Exe cute the commit ted slot inst ruction onl y
if the branch is taken. Save the return address (the address of the
OR instruction) in register R59, but only if the branch is taken.
Branch with
counter control BI 0x0333 ITXBUSY
ADD R0, R1, R2
Branch to address 0x0333. Execute the committed slot instruc-
tion. The ITXBUSY operation increments the UTOPIA Port's
TXBUSY counter.
Branch with
shadow addre ss BFL
ADD R0, R1, R2
OR R2, R3, R4
Branch to the address contained in the Fast Memory Shadow
Registe r , unconditiona lly following execution of the commi tted
slot ins tructio n. Stal l if a LMFM with th e LNK IFO specifie d is
active or pendi ng but has yet to r eturn the first word to t he Firs t
Word Shadow Register. Save the return address (the address of
the O R instruction) in reg ister R5 9.
BIL $SERVICE ESS1/0 DRXFULL
ADD R0, R1, R2
OR R2, R3, R4
Branch to the subroutine $SERVICE if External State Signal
ESS1 is set to “0.” Execute the committed slot instruction
whether or not t he branch is ta ken . Save t he re tur n address (t he
address of the OR instruction) in register R59, but only if the
branch is taken. Decrement the UTOPIA Port’s RXFULL
counter.
.loc 0x0000
LIMD R59, 0x0010
LIMD R59, 0x0020
BRL
NOP
330 Version 4.1 MXT3010 Reference Ma nual
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.loc 0x0004
MV R59, R1
.loc 0x0010
BRL
MV R59, R0
The first BRL branches to address 0x0010 because the second
LIMD has not updated R59 by the time the branch accesses R59.
Consecuti ve LIMD and BRL in structions must be sep arated by
one instruction for the modification to take effect in time. The
BRL at loc ation 0x0010 caus es R59 to be load ed with the r eturn
address, which is location 0x0004. therefore, the BRL at loca-
tion 0x0 010 b ran ches to loca tions 0x00 04. R0 contains 0x000 4
because the second BRL has not updated R59 by the time the
MV is executed. R1 contains 0x0012 because R59 has been
updated by the BRL by the time the MV instruction at 0x0004 is
executed.
MXT3010 Reference Manua l Version 4.1 331
Load and Store Fast Memory examples
Load and Store Fast Me mory examples
Formats The examples in this section use the LMFM, SHFM, and SRH
instructions, which have the following formats:
LMFM rd @ras/rsb #HW [LNK]
SHFM @ rsa/rsb
SRH @rsa/rsb [adr] [reg] [l sbs]
Loading from
Fast Memory LMFM R16 @R10/R11 16HW LNK
Sixteen 16-bi t hal fwords are copie d from Fa st Memory to regis -
ters R16 t hrough R31 . Bits [1 9:1 6] of th e Fast Memor y addres s
come from R10 bits [3:0], and bits [15:0] come from R11 [15:0].
Links are cre at ed su ch that any c hange to one of the se reg ist er s
is subsequently replicated in the corresponding Fast Memory
location if the change was made by an instruction utilizing the
Update Memory (UM) option.
Storing into Fast
Memory SHFM @ R16/R17
The Fast Memory controller writes the halfword contained in
the Fast Memory byte register (R56) into the halfword
addressed by the byte address contained in registers R16 and
R17.
SRH R44 CRCXADR LSBS/10
The Fast Memory controller writes the CRC partial result half-
word contained in R44 into the halfword 10 bytes beyond the
address contained in the CRCX address holding register.
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Load and Store Internal RAM examples
Formats The examples in this section use the LD, LDD, ST, and STD
instructions, which have the following formats:
LD rd @rla [IDX /#]
LDD rd @rla [IDX/#]
ST rsa @rla [IDX/#]
STD rsa/rsb @rla [IDX/#]
Loading from
Internal RAM LD R13 @R48 IDX/10
The conte nts of re gister R48 an d the I ndex f ield (in th is ca se 10
bytes) are used to form the source address in internal memory.
R13 is loaded with the contents of the memory location pointed
to by R48, offset by 10.
IDX/# must be sp ecified as a byt e index value even tho ugh bit 0
is ignored. Register rd must be a software register (R0-R31).
LDD R13 @R48 IDX/10
The conte nts of re gister R48 an d the I ndex f ield (in th is ca se 10
bytes) are used to form the source address in internal memory.
The memory is read and register R13 is loaded with the result.
Register R14 is also loaded with a 16-bit halfword read from
internal memory because this is a Load double instruct ion. The
internal memory address for this halfword is obtained by exclu-
sive-or-ing 0x0002 with the calculated target address.
ST R10 @R49 IDX/20
The content of register R49 and the Index field (in this case 20
bytes) are used to fo rm a tar get ad dress in inte rnal memory. The
content of register R10 i s written to this memory locatio n.
MXT3010 Reference Manua l Version 4.1 333
Load and Store Internal RAM examples
STD R10/R11 @R49 IDX/20
Description The co ntent of registe r rla and t he Index field ar e used t o form a
target address in internal memor y . The content of register R10 is
written to this memory location. The content of register R11 is
also written to internal memory b ecause this is a Store Double
instruction. The memory address for this halfword is obtained
by exclusive-or ring 0x0002 with the calculated target address.
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Logical examples
Formats The examples in this section use the AND, OR, and XORI
instructions, which have the following formats:
AND (rsa, rsb) rd [MODx][abc][AE][UM]
OR (rsa, rsb) rd [MODx][abc][AE][UM]
XORI (rsa, si) rd [abc] [UM]
Using the AND
Instruction AND R8, R9, R16 UM
The contents if R8 are AND’ed with the contents of R9. The
result is placed i nto R16. The resu lt is also writ ten back in to the
Fast Memory location linked to R16.
Using the OR
instruction OR R12, R13, R4
The contents if R12 are OR’ed with the contents of R13. The
result is placed into R4.
Using the XORI
instruction XORI R12, 0x007F, R4 BZ
The contents if R12 are XOR’ed with 0x007F. The result is
placed into R4. If the result is zero, program control is passed to
the instruc tion four instruction slots away. If the re sult is n ot
zero, se quential program f low occurs although a stall penalt y of
two cycles is incurred due to the incorrect branch prediction.
Using the AND
instruction with
MOD and abc
fields
AND R8, R9, R16 MOD64 BZ
The contents if R8 are AND’ed with the contents of R9. The
result, MOD64, is placed into R16. This implies that R8[15:5] is
combined with the ALU result bits [5:0] and written into R16.
More importantly, the conditional branch is then only based on
bits[5:0] of the result rather than on the entire result.
MXT3010 Reference Manua l Version 4.1 335
Shift examples
Shift example s
The Shift examples inclu de:
Formats The exampl es in this section use the SFT, SFTA, SFTC, SFTCI,
SFTLI, and SFTRI instructions, which have the following for-
mats:
SFT (rsa, rsb) rd [MODx][abc] [UM]
SFTA (rsa, rsb) rd [MODx][abc][UM]
SFTC (rsa, rsb) rd [MODx][abc][UM]
SFTCI (rsa, usa) rd [MODx][abc][UM]
SFTLI (rsa, usa) rd [MODx][abc][UM]
SFTRI (rsa, usa) rd [MODx][abc][UM]
General case SFT R8, R9, R10
The conte nts of R8 sh ifts to the eith er the ri ght or t he left, b ased
on the valu e of R9[4:0]. The res ult is placed in R10. Al l vacated
bit positions are filled with 0’s. The Overflow flag registers is
not modified.
Shift right if R9[4:0] = 10011xb, R8 is shifted to the right by 13 positions.
Right shift amount calculation:
Absolute Value of 10011 is: 01100xb + 1 = 1101xb = 13
Shift left if R9[4:0] = 0001 1 xb, R8 is shifted to the left by three pos itions.
Circular shifts SFTC R8, R9, R10
• Shift right
• Shift left
336 Version 4.1 MXT3010 Reference Ma nual
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The contents of R8 shifts in a circular/rotational fashion to the
left b y the amount s pecif ied i n R9[3: 0]. The shi ft d irect ion/s ign
bit R9[4] is ignored because the SFTC and SFTCI instructions
shift only to the left. Bits shifted out of R8[15] are shifted into
bit position 0, and so on. The result is placed into R10.
Arithmetic shifts SFTA R8, R9, R10
The contents of R8 shifts to the right, based on the contents of
bits [3:0] of R9. The shift direction/sign bit R9[4] is ignored
because the SFTA and SFTAI instructions shift only to the ri ght.
The beginning value of R8[15], the sign bit, is copied into all
vacated positions.
Immediate shifts SFTLI R16, 7, R17
The conte nts of R1 6 shif t to th e left by seve n posit ions, wi th al l
vacated bits are filled with 0’s. To accomplish a left shift by
seven positions, the assembler places 00111xb into the SSA
field.
Shift Amount = 7 = 00111xb
The assembler places 00111xb into the SSA field
SFTRI R16, 7, R17
The contents of R16 shift to the right by seven positions, with all
vacated bits are filled with 0’s. However, to accomplish a right
shift by seven positions, the assembler must place the two’s
complement representation into the SSA field. Therefore, the
assembler converts seven into its two’s complement value and
places that value in the SSA field as follows:
Shift Amount = 7 = 00111xb
Two’s complement representation is 11000xb + 1 = 11001xb.
11001xb is placed by the assembler into the SSA field
MXT3010 Reference Manua l Version 4.1 337
Shift examples
SFTCI R9, 7, R10
The contents of R8 shifts in a circular/rotational fashion to the
left by th e seve n positions. Bits shi fted out of bit posit ion 15 are
shifted into bit position 0, and so on. The result is placed into
R10.
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Miscellaneous examples
Formats The ex ampl es i n t hi s s ect i on us e t he CMP, CMPP, FLS, LIMD,
MAX, and MIN inst ructions , which have th e followi ng formats:
CMP (rsa, rsb) [abc][AE]
CMPP (rsa, rsb) [abc][AE]
FLS rd [abc][UM]
LIMD rd, li [UM]
MAX (rsa, rsb) rd [MODx][abc][AE][UM]
MIN (rsa, rsb) rd [MODx][abc][A E][UM]
Using CMP and
CMPP CMPP R6, R7, BAGB
The contents of R6 are compared to the contents of R7. The
results from the previous compare (CMPP) are also factored into
the A>B? dec ision. If the previo us compare ope ration in dicated
A>B, the branch is taken regardless of the results of the present
compare o peration . If the previou s compare operatio n indica ted
A < B, the branch is not taken regardless of the results of the
present compare operation. If the previous compare operation
indicated A=B, the decision to branch is made based on the
results of the current compare operation.
CMP R4, R5
The conte nts of R4 are compared to the conten ts of R5. Since no
Branch Condition was specified, the results are logged for future
use.
32-bit compare
operation example CMP #RARRIVAL_TIME_HI, #REARLIEST_ALLOWD_HI
CMPP #RARRIVAL_TIME_LO, #REARLIEST_ALLOWD_LO BAGEB
BI $DISCARD_CELL
NOP
MXT3010 Reference Manua l Version 4.1 339
Miscellaneous examples
64-bit compare
operation example CMP #RARRIVAL_TIME_64, #REARLIEST_ALLOWD_64
CMPP #RARRIVAL_TIME_48, #REARLIEST_ALLOWD_48
CMPP #RARRIVAL_TIME_32, #REARLIEST_ALLOWD_32
CMPP #RARRIVAL_TIME_16, #REARLIEST_ALLOWD_16 BAGEB
Using FLS FLS R9, R10, BGEZ
The 2^e (e xponentia l) posit ion of th e last bit set in R9 i s writte n
into R10. For example, if bit 15 of R9 is set (the MSB), FLS
writes 0x000F into R10. In the example above, the state of bits
14:0 does n ot affect the result. If bit0 of R9 is the only bit set,
0x0000 is written into R10. If no bit is set, 0x8000 is written into
R10 allowing for a test of a negative result to determine whether
or not a bit was set. The test is performed by the BGEZ, which
branches only if the result is greater or equal to zero.
Using LIMD LIMD R8, 0x67FC
Load Register R8 with the 16-bit value 0x67FC.
Using MAX and
MIN MAX R8, R9, R17
For the purpose of the MAX and MIN instructions, R8 and R9
are treated as unsigne d numbers. The maximum of R8 and R9 is
placed into R17.
MIN R8, R9, R17, UM
For the purpose of the MAX and MIN instructions, R8 and R9
are tr eated as unsigned n umbers. The min imum of R8 and R9 is
placed into R1 7 and is w ritten bac k into the memory lo cation
linked to R17 by a previous LMFM instruction.
340 Version 4.1 MXT3010 Reference Ma nual
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MXT3010 Reference Manua l Version 4. 1 341
Section 3 Signal Descriptions and
Electrical
Characteristics
This section of the manual describes the signal descriptions and
electr ical chara cteri sti cs of the MXT3010. The chapt ers i nclude d
in this chapter are:
•Timing
• Pin information
• Ele ctrical parameters
• Mechanical and thermal characteristics
342 Version 4.1 MXT3010 Reference Ma nual
MXT3010 Reference Manua l Version 4. 1 343
CHAPTER 17 Timing
MXT3010EP timing - general information
Definition of switching levels
FIGURE 91.Switching level voltages
The following switching level information has been used in the
generation of the MXT3010EP device timing.
• For a low-to-high transition, a signal is considered to no
longer be low when it reaches 0.8 V and is considered to be
high upon reachi ng 2.0 V.
• For a high-to-low transition, a signal is considered to no
longer be high when it reaches 2.0 V and is considered to be
low upon reaching 0.8 V.
VH
2.0V
0.8V
VL
344 Version 4.1 MXT3010 Reference Ma nual
Timing
Input clock details
FIGURE 92.Input clock waveform (pin FN)
TABLE 84. Input clock timing parameters
1. With the exception of the PLL circuit, the MXT3010 is a
fully static design and can operate with 1/TC(FN) = 0. The
device i s chara cter ized f or opera tion a pproac hing 0 Hz, bu t
is not tested under this condition.
2. In ord er to main tain low jitt er, pay close atte ntion to the
input clock edge rate. One primary component of jitter
occurs only during the input clock state transition. To
reduce this jitter component, Maker recommends that the
FN pin be drive n dir ectly from the output of a part designed
for clock tree distribution. Maker’s reference design uses
an FCT3807 device from IDT. Other designs that require a
clock dri ve r wit h an i nte gr ate d PLL use the CDC586 cl ock
driver from Texas Instruments.
100MHz
Parameter Min Max Description
TC(FN) 19.98 (1) Input clock period
TH(FN) .4 TC .6 TC Input clock high duration
TL(FN) .4 TC .6 TC Inp ut clock low duration
TR(FN) -1.5 Input cloc k rise time (2)
TF(FN) -1.5 Input clock fall time (2)
TC(FN) TH(FN)
TL(FN)
TR(FN) TF(FN)
2.0V
0.8V
MXT3010 Reference Manua l Version 4.1 345
MXT3010EP Fast Memory interfa c e timing
MXT3010EP Fast Memory interface timing
This section includes a Fast Memory timing table and abbrevi-
ated timi ng dia gra ms that show only eno ugh si gnals to iden ti fy
all of the timing parameters. For a more complete explanation of
the signalling used in various transfers, see “Fast Memory
sequence diagrams” on page 56.
Thes e notes relate to Fast Memory timing issue s:
• During cycles in which Fast Memory is IDLE, the
MXT3010EP sources the CPU’s Instruction fetch address
onto FADRS(17:2) so that one can view the SWAN proces-
sor’s instruction execution flo w on a logic analyzer. The
MXT3010EP performs Fast Memory reads during these
cycles but discards the data read from the SRAMs.
• In a dual bank system, the bank accessed by the Fast Mem-
ory controller during IDLE cycles is determined by the
ICACHE address. If the ICACHE address maps to bank 0,
bank 0 is read during IDLE cycles. If it maps to bank 1,
bank 1 is read during IDLE cycles.
• All address and control lines should be series terminated.
• At the boundary of the chip, the MXT3010EP guarantees
that FOE0_ is de-asserted before asserting FOE1_, and
similarly that FOE1_ is de-asserted before asserting
FOE0_.
346 Version 4.1 MXT3010 Reference Ma nual
Timing
TABLE 85. Fast Memory timing for the Maker MXT3010EP
100 MHz Fast Memory timing (in nanoseconds)
Par Min Max Pins Description
T117.0 FADRS[17:2] Clk to address output valid
T211.3 FADRS[17:2] Hold time provid e d by MXT3010
T33.8 FDAT[31:0] Input setup time to rising clk
T41.0 FDAT[31:0] Input hold time from rising clock
T517.0 FCS0_, FCS1_,
FWE[0:3]_ Cl k to output valid
T611.3 FCS0_, FCS1_,
FWE[0:3]_ Hold time provided by MXT3010
T71.3 2.5 FOE0_, FOE1_ CLK to FOE
T87.0 10.0 FOE0 _, FOE1_ CLK to FOEx_
T95.8 15.0 FDAT[31:0] CLK to outp ut in low Z state
T10 1.8 8.0 FDAT[31:0] CLK to output in high Z state
T11 8.5a
a. For the first word of data, T9 is the critic al timin g pa rame ter.
FDAT[31:0] CL K to FDAT[31:0] ou tp ut va lid
T12 1.8 FDAT[31:0] Hold time provided by MXT3010
MXT3010 Reference Manua l Version 4.1 347
MXT3010EP Fast Memory interfa c e timing
FIGURE 93.Timing for Fast Memory reads
FIGURE 94.Timing for Fast Memory writes
CLK
FCS0_
T1
T2
FDAT in [31:0]
T3
T4
T6
FADRS [17:2] A0 A1 A2
D0 D1
T5
CLK
FCS0_
T1
T2
FDAT Out [31:0]
T9
T6
FADRS [17:2] A0 A1
D0 D1
T5
T11 T12
T10
FOE0_
T8
T7
348 Version 4.1 MXT3010 Reference Ma nual
Timing
MXT3010EP UTOPIA interface timing
This section includes a UTOPIA timing table and abbreviated
timing di agrams that show onl y enough signal s to identif y all of
the timing parameters. For a more complete explanation of the
signalling used in various transfers, see “UTOPIA port sequence
diagrams” on page 94.
All timing shown in Table 86 is relative to either RX_CLK or
TX_CLK as shown in Figure 97 or Figur e 98 respectively. The
relationship between the MXT3010EP input clock (FN) and a
half-speed RX_CLK/TX_CLK is shown in Figure 95 (also see
Figure 26 on page 73). The relationship between the
MXT3010EP input clock (FN) and a quarter-speed RX_CLK/
TX_CLK is s hown in Figure 96 (als o see Figure 27 on page 73).
The values of T9 and T10 are s hown in Table 87.
FIGURE 95.FN and half-spee d RX_ CLK/TX_CLK
FIGURE 96.FN and quarter-speed RX_CLK/TX_CLK
½TC(FN) +T9
FN (Input Clock)
RX_CLK
T10
TX_CLK
T10
FN (Input Clock)
RX_CLK
T9
T9
T10
TX_CLK
MXT3010 Reference Manua l Version 4.1 349
MXT3010EP UTOPIA inte rfac e timing
Notes:1. Adrs/ C hip Select s/Wr ite Enables are driving at 100 M Hz edge cor-
responding with falling edge of 50 MHz chip clock.
2. All maximum timing is specified with 30 pF loads (Adrs/Ctrl), 25
pF (Data). All minimum timing is specified with 5 pF loads.
3. A circuit stretches the minimum time-on time of the data on read
followed by write cycles.
4. Currently the FOE of one bank is guaranteed to be de-asserted
before the second bank is asser ted. This is not actually required
since the RAMs are designed to allow back-to-back bank operation.
TABLE 86. UTOPIA timing for Maker MXT3010EP
100 MHz UTOPIA timing (in nanoseconds)
Par Min Max Pins Description
T1 6.0 TXSOC, TXENB_,
RXENB_,
TXCTRL,
RXCTRL
TX_CLK to ou tpu t valid
T21.3 TXSOC, TXENB_,
RXENB_,
TXCTRL,
RXCTRL
Hold time provided by
MXT3010
T37.0 TXDATA[7:0] TX_CLK to output valid
T41.3 TXDATA[7:0] Hold time provided by
MXT3010
T54.0 RXSOC, RXCLAV Input setup time to TX_CLK/
RX_CLK
4.0 TXCLAV Input setup time to TX_CLK/
RX_CLK
T61.3 RXSOC, RXCLAV Input hold time from TX_CLK/
RX_CLK
1.3 TXCLAV Input hold tim e from TX_CLK/
RX_CLK
T74.0 RXDATA[7:0] Input setup time to RX_CLK
T81.3 RXDATA[7:0] Input ho ld time from RX_CLK
350 Version 4.1 MXT3010 Reference Ma nual
Timing
Notes:1. The hold tim e for da ta d n co ntro l is reduced on th e M XT3 01 0EP at
the expense of the setup time. This was done to allow an easier
interface to PHY devices when guaranteeing hol d t ime.
2. Multi-PHY designs must ensure that no bus fight exists on the
CLAV lines.
3. All maximum timing is specified with 15 pF loads. All minimum
timing is specified with 5 pF loads.
FIGURE 97.UTOPIA port receive timing
TABLE 87. Delay of UTOPIA clocks relative to MXT3010EP internal
clock (CLK)
100 MHz UTOPIA TIMING
Par Min Max Pins Description
T9
T10
1.3
1.3 5.5
6.0 RX_CLK/TX_CLK
RX_CLK/TX_CLK Rise time (r-min/r-max)
Fall time (f-min/f-max)
RXCLK
RXDATA [7:0] P48
RXSOC
T6
T1
T2
T1
T2
RXENB_
H1 H2
RXCLAV
T5T6
T5
T8
T7
MXT3010 Reference Manua l Version 4.1 351
MXT3010EP UTOPIA inte rfac e timing
FIGURE 98.UTOPIA port transmit timing
TXCLK
TXDATA [7:0] P48
TXSOC
T6
T1
T2
T1
T2
TXENB_
H1 H2
TXCLAV
T5T6
T5
T4
T3
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MXT3010EP Port1 timing
This section includes a Port1 timing table and abbreviated tim-
ing diagrams that show only enough signals to id entify all of the
timing parameters. For a more complete explanation of the sig-
nalling used in various transfers, see “Port1 basic protocol” on
page 110.
Thes e notes relate to Port1 timing issues:
• If th e external con troller req uires the MXT301 0EP to drive
the P1AD(31 :0) and P 1 contr ol buses when no oth er master
owns the bus, the external controller should select address
cycles.
• For exact timing numbers for CIN_BSY and COUT_RDY
assert ion and deass ertion, see “MXT3010EP miscel laneous
control signal timing” on page 359.
• Add Wait States during COMMIN register writes and
COMMOUT register reads by extending COMMSEL and
P1RD for one or more additional cycles (beyond those
shown). For COMMIN register writes, COMMIN data
MXT3010EP samples the f inal wri te clock cyc le (the cycle
in which COMMSEL is sampled low at the end of the
cycle). For COMMOUT register reads, MXT3010EP
sources the contents of the COMMOUT register through-
out the extended cycle.
MXT3010 Reference Manua l Version 4.1 353
MXT3010EP Port1 timing
Note: All maximum timing is specified with 15 pF loads. All minimum
timing is specified with 5 pF loads.
TABLE 88. Port1 timing table
100 MHz Port1 read and write timing (in nanoseco nd s)
Par Min Max Pins Description
T17.0 P1QRQ_, P1RQ_,
P1RD, P1END_,
P1IRDY_,
P1HWE[0:1]
P1AD[31:0]
CLK to output valid
T21.3 P1QRQ_, P1RQ_,
P1RD, P1END_,
P1IRDY_,
P1HWE[0:1],
P1AD[31:0]
Hold tim e prov ide d by
MXT3010
T37.0 P1TRDY_,
P1ASEL_ Input setu p time to risin g cl oc k
T41.0 P1TRDY_,
P1ASEL_ Input hold time from rising
clock
T51.3 7.5 P1RD, P1END_,
P1HWE[0:1],
P1IRDY_
Clock to output in low Z s tate
T61.3 10.5 P1RD, P1END_,
P1HWE[0:1],
P1IRDY_
Clock to output in high Z state
T71.3 7.3 P1AD[31:0] Clock to output in low Z state
T81.3 10.5 P1AD[ 31 :0 ] Clock to output in high Z state
T91.3 8.8 P1AD[31:0] Clock to P1AD(31: 0) valid
T10 4.0 P1AD[31:0] Input setup time to risin g cl oc k
T11 1.0 P1AD[31:0] I nput hold time from risin g
clock
T12 6.0 COMM SEL, P1RD Input setu p tim e to risin g cl oc k
T13 1.0 COMMSEL, P1RD Input hold time from rising
clock
354 Version 4.1 MXT3010 Reference Ma nual
Timing
FIGURE 99.Port1 read timing
FIGURE 100.Port1 write timing
CLK
P1AD Out [31 :0] A
P1RQ_
T2
T1
T1
T2
P1END_
DI 0
P1AD in [31:0]
P1TRDY_
T4
T4
T3T3
T1
T5T2
T1
T2
T1
T2
T6
T7
T9
T2
T8T10
T11
CLK
P1AD Out [31 :0] A
P1RQ_
T2
T1
T2
T1
P1END_
DO 0
P1TRDY_
T4
T4
T3T3
T1
T5T2
T1
T2
T1
T1
T6
T7
T9
T2
T8
DO 1
MXT3010 Reference Manua l Version 4.1 355
MXT3010EP Port1 timing
FIGURE 101.COMMIN register write, COMMOUT register read timing
CLK
P1AD Out [31: 0]
P1RD in T12
T10
T11
COMM IN
DATA
P1AD in [31:0]
T13
T12
T13
T2
COMM OUT
DATA
T8
T5
T9
356 Version 4.1 MXT3010 Reference Ma nual
Timing
MXT3010EP Port2 timing
This section includes a Port2 timing table and abbreviated tim-
ing diagrams that show only enough signals to id entify all of the
timing parameters. For a more complete explanation of the sig-
nalling used in various transfers, see “Port2 basic protocol” on
page 137.
This note relates to Port2 timing issues:
• If the external controller requires the MXT3010EP to
actively drive the P2AD(15:0) and P2 control buses when
no other master owns the bus, it should do so by selecting
address cycles.
MXT3010 Reference Manua l Version 4.1 357
MXT3010EP Port2 timing
TABLE 89. Port2 timing table
Note: All maximum timing is specified with 15 pF loads. All minimum
timing is specified with 5 pF loads.
100 MHz Port2 read and write timing (in nanoseconds)
Par Min Max Pins Description
T18.0 P 2QRQ_ P2QBRST,
P2RQ_, P2RD,
P2END_, P2IRDY_
P2AD[15:0]
CLK t o output valid
T21.3 P2QRQ_, P2QBRST,
P2RQ_, P2RD,
P2END_, P2IRDY_,
P2AD[15:0]
Hold time provided by
MXT3010
T38.0 P2TRDY_, P2ASEL_ Input setup time to rising
clock
T41.0 P2TRDY_, P2ASEL_ Input hold time from rising
clock
T52.0 8.0 P2RD, P2END_,
P2AI[3:0], P2IRDY_ Clock to output in low Z
state
T62.0 11.0 P2RD P2END_,
P2AI[3:0], P2IRDY_ Clock to output in hi gh Z
state
T71.3 8.0 P2AD[15:0] Clock to out put in low Z
state
T82.0 10.0 P2AD[15:0] Clock to out put in high Z
state
T91.3 8.0 P2AD[15:0] Clock to P2AD(15:0) valid
T10 4.0 P2AD[15:0] Input setup time to rising
clock
T11 1.0 P2AD[15:0] Input hold time from rising
clock
358 Version 4.1 MXT3010 Reference Ma nual
Timing
FIGURE 102.Port2 read timing
FIGURE 103.Port2 write timing
CLK
P2AD Out [15 :0] A
P2RQ_
T2
T1
T1
T2
P2END_
DI 0
P2AD in [15:0]
P2TRDY_
T4
T4
T3T3
T1
T5T2
T1
T2
T1
T2
T6
T7
T9
T2
T8T10
T11
CLK
P2AD Out [15 :0] A
P2RQ_
T2
T1
T2
T1
P2END_
DO 0
P2TRDY_
T4
T4
T3T3
T1
T5T2
T1
T2
T1
T1
T6
T7
T9
T2
T8
DO 1
MXT3010 Reference Manua l Version 4.1 359
MXT3010EP miscellane ous control signal ti ming
MXT3010EP miscellaneous control signal timing
This section includes a miscellaneous control signal timing table
and a miscellaneous control signal timing diagram.
Note that the MXT3010EP drives CIN_BUSY withi n two clock
cycles of a COMMIN Register write operation. Therefore, the
host should wait at least two system clock cycles from the com-
pletio n of a COMMIN regis ter write befor e testing CIN_BUSY.
TABLE 90. Miscellaneous control signal timing
FIGURE 104.Timing of CIN_BUSY and COUT_RDY
100 MHz Misc. control signal timing (in nanoseconds)
Par Min Max Pins Description
T18.0 ICSO_(D:A) CLK to output valid
T21.3 ICSO_(D:A) Hold time provided by
MXT3010
T33.5 ICSI_(D:A) Input setup time to rising
clock
T41.0 ICSI_(D:A) Input hold time from rising
clock
T58.5 CINBUSY, COUTRDY CLK to output valid
T61.3 CINBUSY, COUTRDY Hold time provided by
MXT3010
CLK
COUT_RDY
CIN_BUSY
ISCI_[D:A]
ISCO_[D:A]
T5
T6
T5
T6
T1
T2T3
T4
T5
T6
T5
T6
360 Version 4.1 MXT3010 Reference Ma nual
Timing
MXT3010EP Reset timing
This sect io n includes a MXT3010EP r ese t t imi ng ta ble and dia -
gram.
These notes relate to MXT3010EP reset timing issues:
1. When RESET_ is de-asserted, two events occur: a) the
MXT3010EP fetches boot code from the designated port,
and b) the MXT3010EP begins a cache initialization rou-
tine which takes 1028 input clock cycles.
2. The MXT3010EP d oes not a ct ively drive I CSO_(D: A) dur -
ing reset. Therefore, these pins float unless actively driven
or pulled up or down ext ernally. The values sen sed on these
pins at RESET_ removal provide configuration information
to th e MXT30 10EP. For mo re in form ation, see “Device I ni-
tialization” on page 401.
MXT3010 Reference Manua l Version 4.1 361
MXT3010EP miscellane ous control signal ti ming
TABLE 91. MXT3010EP reset timing
FIGURE 105.MXT3010EP reset timing
100 MHz Reset timing (in nanoseconds)
Par Min Max Pins Description
T110,000 clock
cycles CLK, also
called FN Minimum number of clock cycles that
reset must be held low for to allow
internal PLL to lock.
T213.0 RESET Input setup time to rising CLK for
removal of reset signal. Reset may be
asserted asynchronously but must be
deasserted synchronous to CLK.
T2a 1.5 RESET RESET hold time
T35 ICSO_[D:A] Input setup time to rising CLK. This
setup requirement need only be met for
the rising edge of CLK for which
RESET is sampled high for the first
time.
T43 ICSO_[D:A] Input hold time from rising CLK. This
hold requirement need only be met for
the rising edge of CLK following the
rising edge of CLK for which RESET
is sampled high for the first time.
INPUT CLK
Configuration
RESET_
T2
T1
T3
T4
Asynchronous
Assertion
ISCO_[D:A] out Hig h impedance (see Note 1 above)
information
ISCO_ [D:A] i n
362 Version 4.1 MXT3010 Reference Ma nual
Timing
As indica ted in Figure 105, the de-assertion of RESET_ must be
done withi n certai n t imin g constraints. These ti ming constr ai ns
occur because the MXT3010EP samples the RESET_ pin with
an internal clock that operates at twice the rate of the input clock.
This is done to establish a phase relationship with the input
clock. For example, if the input clock operates at 50 MHz, the
MXT3010EP samples RESET_ with a 100 MHz int ernal clock.
The syst em designe r must meet t h e t imin g r equirement s sho wn
in Figure 106 and Table 92.
FIGURE 106.Reset trailing edge timing
TABLE 92. MXT3010EP RESET_ timing parameters
Notes: 1.Parameter T5 in Table 92 is the same as parameter T2 in Table 91.
2. Unless otherwise specified, all times in this table are relative to
the input clock.
100 MHz Reset timing (in nanoseconds)
Par Min Max Description
T120 Input clock period
T210 Internal clock period
T33Set u p to internal clock edge
T41.5 Hold from internal clock edge
T513 Setup to inp ut clock ed g e (N ote 1)
T1
T4
T2T2
T3
T5
INPUT CLK
INTERNAL
RESET_
CLK
MXT3010 Reference Manua l Version 4.1 363
MXT3010EP miscellane ous control signal ti ming
Given the 20ns period of the 50Mhz input clock, this leaves a
5.5ns (20-13-1.5=5.5) window in which RESET_ can be
removed. Although care must be taken to meet these require-
ments, it can be routinely accomplished.
Several methods of achieving this timing are possible. Current
ASIC technology meets this timing. FPGA implement ations ar e
more dif ficult, but po ssible. On the MXT3 015 Evaluation Card,
Maker use s a fast e xternal fl ip-flop to constrain t iming to wit hin
this window. Figure 107 shows this circuit.
FIGURE 107.Reset timing circuit
50 MHz
FPGA FCT823C MXT3010
RST_ RESET_
364 Version 4.1 MXT3010 Reference Ma nual
Timing
MXT3010EP Fast Memory interface operation
This exampl e shows a Fa st Memory connect ion using Samsung
KM718B90 Synchronous SRAMs. Connections are shown for a
single bank system using two SRAM.
MXT3010EP
SRAM with bit s
(31:16) of Fast
Data. SRAM with bits
(15:0) of Fast Data. Comments
FADRS(17:2) A(15:0) A(15:0) The MXT3010EP provides a word address
and individual byte write enable lines. For a
64Kx32 Control Memory, FADRS(17:2)
are con nected to A(15:0) of each of the
SRAMS. For a 32Kx32 Control Memory,
FADRS(17) is unconnected and
FADRS(16:2) are connected to A(14:0) of
each of the SRAMs.
FDAT(15:0) N/C I/O(15:0)
FDAT(31:16) I/O(15:0) N/C
Tied to GND
through 10K
Oh m r e sist or s
I/O(17:16) I/O(17:16) If x1 8 devices are used, tie I/O(17:1 6) to
grou nd through dedicated 10K Ohm resis-
tors.
FCS0_ CS_, ADSC_ CS_, ADSC_ In a single bank system , FCS0_ is tied to
the CS_ an d A DS C_ of each of the SRA M
devices.
FOE0_ OE_ OE_ In a single bank system, FOE0_ is tied to
the output enable of each of the SRAM
devices.
Tied to PWR ADV_, ADSP_ ADV_, ADSP_ Th e MXT3010EP does not use these con-
trol signals.
FWE0_ UW_ FWE0_ control s byte FDAT(31:24)
FWE1_ LW_ FWE1_ controls byt e FDAT (23:16)
FWE2_ UW_ FWE2_ controls byte FDAT(15:8)
FWE3_ LW_ FWE3_ controls byte FDAT(7:0)
FN (CLK) K K T ied to system clo ck. This is the same clock
that is connected to the MXT30 1 0EP ’s
clock input (FN).
MXT3010 Reference Manua l Version 4.1 365
MXT3010EP JTAG operation
MXT3010EP JTAG operation
For JTAG SCAN chain connection information contact Maker
Communications.
The MXT3010EP provides a pin, TRI_, that places all output
drivers in the high impedance state except RXCLK, TXCLK,
and the outputs associated with the PLL.
366 Version 4.1 MXT3010 Reference Ma nual
Timing
MXT3010 Reference Manua l Version 4. 1 367
CHAPTER 18 Pin Information
This chapter provides information on the MXT3010EP pinouts.
The information includes pin diagrams, signal descriptions, and
pin listings.
368 Version 4.1 MXT3010 Reference Ma nual
Pin Information
MXT3010EP pinout
Figure 108 provides a diagram of the MXT3010EP pinout.
FIGURE 108.MXT3010EP package/pin diagram
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
P1AD1
GND
P1AD9
P1AD0
P1AD2
P1ABRT_
P1RD
VDD
P1AD8
P1QRQ_
P1END_
GND
P1HWE1
P1IRDY_
P1RQ_
P1HWE0
FDAT0
RESET_
FDAT1
GND
P1AD26
GND
P1AD16
P1AD23
P1AD14
P1AD20
GND
P1AD22
P1AD12
P1AD10
P1AD6
VDD
P1AD13
P1AD17
P1AD7
GND
P1AD11
P1AD5
P1AD3
P1AD4
VDD
P1AD31
P1AD30
COUTRDY
P2ASEL_
GND
P1AD29
P1AD28
P2TRDY_
P1AD27
P1AD25
VDD
P1AD24
CINBUSY
P1AD21
GND
P1AD19
P1AD15
COMMSEL
P1AD18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
GND
P2QBRST
P2QRQ_
P2IRDY
P2AD15
P2RQ_
P2AD14
P2END_
GND
P2AD8
P2RD
P2AD12
VDD
P2AD11
P2AD4
P2AD13
P2AD10
P2AI13
GND
P2AD1
P2AD9
P2AI0
P2AD5
P2AD7
GND
P2AD6
TMS
P2AD0
VDD
P2AD3
P2AI2
P2AD2
TRI_
GND
TRS
P2AI1
OSC_EN_
TXDATA0
GND
TXCTRL0
TXDATA1
TXSOC
TXENB_
TXCLAV
GND
TX_CLK
TDO
RESRVD
VDD
TXDATA2
TXDATA3
TXCTRL2
TXDATA4
TXDATA6
GND
ICSO_C
TXDATA7
TXCTRL1
TXCTRL3
VDD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VDD
ICSI_D
GND
FDAT31
GND
FDAT30
ICSI_C
FDAT28
VDD
FDAT29
FDAT27
FDAT26
FDAT25
FDAT24
GND
FDAT20
FDAT23
FDAT22
FDAT21
VDD
RXDATA5
ICSO_A
RXDATA4
RXCTRL1
GND
RXCTRL3
TCK
ICSO_B
VDD
RXDATA1
ICSO_D
RESRVD
TDI
RANGE
ICSI_B
GND
VAA
BP_
GND
FN
GND
TXDATA5
RXCTRL2
RXDATA0
RESRVD
ICSI_A
GND
RX_CLK
GND
RESRVD
RXSOC
RXDATA3
VDD
RXDATA2
RXENB_
RXDATA6
RXDATA7
RXCTRL0
GND
RXCLAV
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
VDD
FDAT2
FDAT3
FDAT5
P1TRDY_
GND
FDAT4
FDAT7
P1ASEL_
FDAT6
FDAT8
VDD
FDAT10
FDAT9
FDAT11
GND
FDAT15
FDAT12
FDAT14
RESRVD
FDAT13
GND
FADRS15
FADRS10
VDD
FADRS9
FADRS12
FADRS11
GND
FADRS13
FADRS16
VDD
FWE3_
FADRS14
FOE1_
GND
FCS0_
FWE2_
FCS1_
FWE0_
FADRS17
GND
FOE0_
FWE1_
FADRS3
FADRS2
FADRS5
VDD
FADRS6
FADRS4
FADRS8
GND
FDAT16
FDAT18
FADRS7
VDD
FDAT17
LSSD_TES
T
FDAT19
GND
MXT3010EP
top view
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
MXT3010 Reference Manua l Version 4.1 369
MXT3010EP signal descriptions
MXT3010EP signal descriptions
•Port1
•Port2
•UTOPIA port
• Fast Memory controller
• Inter-chip and communication registers
• Miscellaneous signals, such as clock, control and test
• Power and ground pins
370 Version 4.1 MXT3010 Reference Ma nual
Pin Information
TABLE 93. MXT3010EP Port1 signal descriptions
Pin #aSymbol I/O Name Description
179, 178, 174,
173, 171, 160,
170, 168, 157,
153, 166, 155,
164, 161, 147,
158, 163, 156,
148, 152, 144,
151, 138, 132,
146, 150, 143,
141, 142, 136,
140, 137
P1AD[31:0] I/O Port1
Address/Data
[31:0]
This is a multiple xed, bi-dire ct ional 32- bit bus.
Data is read into and out of the MXT3010EP dur-
ing DMA and COMM operations; see “The Port1
and Port2 Int erfaces” on page 97. and see “ Com-
municat ion s” on page 177.
126 P1RQ_ O Port1
Request T his signa l indicates that c o mmand s are in the
active stage of the Port1 DMA command queue.
131 P1QRQ_ O Port1 DMA
Queue Request This s ignal in dicates that comman ds are in th e
queue stage of the Port1 DMA command queue.
134 P1RD I/O Port1 Read /
Write select The MXT3010EP drives this signal during a
DMA transfer, and the host drives the signal dur-
ing a communication registe r tra nsfer. In either
case, this signal indicates a read (1) or a write (0)
transfer.
130 P1END_ O Port1
End T his signa l indicates the last cycl e of a DMA
operation.
128
125 P1HWE1
P1HWE0 O
OPort1
Halfword Enable
[1:0]
During data cycles, P1HWE[1:0] act as Half
Word E na ble s. If P1HW E[ 0] is asserted,
P1AD[31:16] should conta i n valid data. If
P1HWE[1] is asserted, P1AD[15:0] should con-
tain valid data.
127 P1IRDY_ O Port1
Interface
Initiator
Ready
During DMA write data cycles, the MXT3010EP
asserts P1IRDY_ w hil e i t is sour cing valid data
on P1AD[31:0]. During DMA read data cycles,
the MXT3010EP asserts P1IRDY_ if it can sam-
ple P1AD[31:0] on the next rising edge of clock.
135 P1ABRT_ I Port1 Transfer
Abort The host drives this signal to abort burst DMA
operation.
1 16 P1TRDY_ I Port1
Target
Ready
The host drives this signal and the host inserts
wait st ates. With P1AS EL_, the host des elects
(i.e., tri-st ate) MX T3010EPs .
112 P1ASEL _ I Port1
Address
Select
The ho st dri ve s th is sign al and th e host se lects an
address or data cycle. With P1TRDY_ th e host
desel ects ( tr i-s t ate) MX T3010EP s .
a. Pin numbers in this table, and in all subsequent tables, are listed in descending order (for
example, P1AD3 1 to P1 AD0).
MXT3010 Reference Manua l Version 4.1 371
MXT3010EP signal descriptions
TABLE 94. MXT3010EP Port2 signal descriptions
Pin # Symbol I/O Name Description
185, 187,
196, 192,
194, 197,
201, 190,
204, 206,
203, 195,
210, 212,
200, 208
P2AD
[15:0] I/O Port2
Address/Data
[15:0]
This is a multiplexe d, bi-d irec tio na l 16 -bit bu s.
Data is read into and out of the MXT3010E P during
DMA operations. For operational details see “The
Port1 an d Port2 Inte r fa c es ” on pa g e 97 .
198, 211,
216, 202 P2AI[3:0] O Port2 Address
Index Bus Th ese signals are multi- purpose. In burst mode
P2AI[3:0] rep res ent an address index consisting of
the lower four bits of an address. In non-burst mode
P2AI[3:2] represent the two most significant
address bits. P2AI[1] represents P2RD_. P2AI[0]
represents Address Latch Enable.
186 P2RQ_ O Port2
Request This signal indicates that commands are in the
active st age of the Port2 DMA command queue.
183 P2QRQ_ O Port2
DMA Queue
Request
This sig nal indicates tha t co mmands are in th e
queue stage of the Port2 DMA command queue.
191 P2RD O Port2
Read / Write
Select
The MXT3010EP drives this signal during a DMA
transfer. This signal indi cates a write (0) transfer or
a read (1) transfer.
188 P2END_ O Port2
End On DMA operations, the MXT3010EP asserts
P2END_ to indicate the last cycle of the transfer .
182 P2QBRST O Port2
Burst This signal ind icates burst (1) or non-burst (0 )
transfer mode. For operational details see “The
Port1 an d Port2 Inte r fa c es ” on pa g e 97 .
184 P2IRDY_ O Port2
Interface
Initiator
Ready
During DMA write data cycles, the MXT3 010EP
asserts P2IRDY_ while it is sourcing valid data on
P2AD[15:0]. During DMA read data cyc les, the
MXT3010EP asserts P2IRDY_ if it can sample
P2AD[15:0] on the next rising edge of clock.
172 P2TRDY_ I Port2
Target
Ready
The host drives this signal and inserts wait states.
With P2ASEL_ the host can deselect [i.e., tri-state]
MXT3010EPs.
176 P2ASEL_ I Port2 A ddress
Select The host dr iv es this signal and selects address or
data cy cle. With P2TRDY_ the host can deselect
(tri-state) MXT3010EPs.
372 Version 4.1 MXT3010 Reference Ma nual
Pin Information
TABLE 95. UTOPIA port signal description
Pin # Symbol I/O Name Description
237, 234,
2, 233,
231, 230,
221, 218
TXDATA
[7:0] I/O UTOPIA Trans-
mit Data
[7:0]
In 8-bit bi-directional mode, these pins send
data to the PHY device. In 16-bit uni-direc-
tional mode, these pins are byte 0 or byte 1 of
the bus. For operational details see “The UTO-
PIA port” on page 69.
239, 232,
238, 220 TXCTRL
[3:0] I/O UTOPIA Trans-
mit Control These signals provide multi-PHY control infor-
mation. For operational details see “The UTO-
PIA port” on page 69.
224 TXCLAV I T ransmit Cell
Available This signal indicates to the MXT3 010EP that
the PHY is ready to accept a cell .
223 TXENB_ O T r ansmit Ena b le This signal indicates to th e PHY that va lid dat a
is on the bus.
222 TXSOC O T rans mit S tart of
Cell This sign al indicates to th e PHY the start of a
cell.
226 TX_CLK O Transmit Clock The MXT3010EP provides the transmit clock.
17, 16,
21, 23,
12, 14,
30, 4
RXDATA
[7:0] I/O UTOPIA
Receive Data
[7:0]
In 8-bit bi-directio nal mode, these p ins are use d
to receive data from the PHY device. In 16-bit
uni-directio nal mode, these pins are byte 0 or
byte 1 of the bus. For operational details see
“The UTOPIA port” on page 69.
26, 3, 24,
18 RXCTRL
[3:0] I/O UTOPIA
Receive Control These signals provide multi -PHY control
information. For operational details see “The
UTOPIA port” on page 69.
20 RXCLAV I Receive Cell
Available This signal indicates to the MXT3 010EP that
the PHY has a cell ready to send to the
MXT3010EP.
15 RXENB_ O Receive Enable This signal in dicates to the P HY that the
MXT3010EP is ready to receive data.
11 RXSOC I Receive Start of
Cell This signal indi cate s to the MXT3010EP the
start of a cell.
8 RX_CLK O Receive Clock The MXT3010EP provides the receive cl ock.
MXT3010 Reference Manua l Version 4.1 373
MXT3010EP signal descriptions
TABLE 96. MXT3010EP Fast Memory controller signal description
Pin # Symbol I/O Name Description
80, 90, 98,
87, 91, 94,
93, 97, 95,
70, 66, 72,
74, 71, 76,
75
FADRS
[17:2] O Fast Memory
Address Bus
[17:2]
Byte address.
44, 46, 50,
48, 51-54,
57-59, 56,
62, 67, 64,
68, 1 04,
102, 100,
103, 106,
108, 107,
110, 113,
111, 117,
114, 118,
119, 122,
124,
FDAT
[31:0] I/O Fast Memory
Data Bus
[31:0]
Fast Memory data bus.
82
84 FCS1_
FCS0_ O Fast Memory
Control Signals
[1:0]
These signals select the bank of SRAM
addressed during Fast Memory operations.
FCS0_ low = ba n k 1
FCS1_ low = ba n k 2
When operating in Mode 1, these Chip
Select pins are used as Fast Memory
Address lines 18 and 19.
FCS1_ = FADRS[19]
FCS0_ = FADRS[1 8]
See Figure 16 on page 55.
86
78 FOE1_
FOE0_ O Fast Memory
Output En able
[1:0]
These signals enable bank 1 and bank 2 of
SRAM.
FOE0_ low = bank 1
FOE1_ low = bank 2
88
83
77
81
FWE3_
FWE2_
FWE1_
FWE0_
O Fast Memory
Write Enable
[3:0]
These signals select the byte target during a
Fast Memory write operation:
FWE0_ low = byte 0 FDAT[31:24]
FWE1_ low = byte 1 FDAT[23:16]
FWE2_ low = byte 2 FDAT[15:8]
FWE3_ low = byte 3 FDAT[7:0]
374 Version 4.1 MXT3010 Reference Ma nual
Pin Information
TABLE 97. MXT3010EP inter-chip and communication registers signal description
Pin # Symbol I/O Name Description
167 CINBUSY O COMMIN Busy COMM I N Busy sign als the status of the COM-
MIN Re gister. The MX T3010EP drives t his pin
high when the Host writes to the COMMIN
Register. The MXT30 10EP clears the signal
when it reads the COMMIN Register . As long as
CINBUSY is high, the COMMIN Register is
full.
177 COUTRDY O COMMOUT
Ready This signal signals the status of the COMMOUT
Register. The MXT3010EP asserts this signal
(1) when it writes to the COMMOUT Register.
When the host reads the COMMOUT register,
the MXT3010EP clears the signal (0). As long
as COUTRDY is 1, the COMMOUT Register is
full.
162 COMMS EL I Comm Select When the Comm Select sign al is asserted (1)
and the P1RD signal is low (0), the COMMIN
register is a target of a write operation (Host to
MXT3010E P). Wh en t he Co m m Se le ct sig n al is
asserted (1) and the P1RD signal is high (1), the
COMMOUT register is the source of a read
oper ation (MXT3010EP to Host ).
42
47
35
6
ICSI_D
ICSI_C
ICSI_B
ICSI_A
I ICS Input
[D:A] The MXT3010EP uses these signals to poll the
state of external devices. They also control the
Sparse Event Register.
31
236
28
22
ICSO_D
ICSO_C
ICSO_B
ICSO_A
O ICS Output
[A:D] These signals are used by the MXT3010EP to
signal the state of the MXT3010EP to external
devices. The SWAN processor sets the state of
these signals by setting or clearing bits in the
Sparse Even t Register. These sign als are also
used during device initialization.
MXT3010 Reference Manua l Version 4.1 375
MXT3010EP signal descriptions
TABLE 98. MXT3010EP miscellaneous clock, control, and test signal descriptions
Pin # Symbol I/O Name Description
40 FN I Input Clock This signal provides the MXT3010EP device
clock.
123 RESET_ I Reset Device reset.
217 OSC_EN I Oscillator Enable Oscillato r enable is used for te sting of ring oscil-
lator.
63 LSSD_TEST I This pin is used for scan test.
34 RANGE I Operation Range
select The RANGE pin affects the ope rating rang e of
the PLL VCO:
Hig h = Ou tp ut f r e qu ency 50 - 10 0 mH z
Low = Outp ut frequency 100-4 00 mHz
This pin is customarily left floating, thus allow-
ing th e internal pull u p to keep t he pin in the h igh
state.
38 BP_ Bypass Pin This pin is used during production test ing of the
PLL.
213 TRI_ I T ri-State T est This signal places all of the tri-state and bi-direc-
tional I/Os into tri-state.
27 TCK I Test Clock JTAG Test Clock input
33 TDI I Test Data In JTAG Test Data input
227 TDO O Test Data Ou t JTAG Test Data outp ut
207 TMS I Test Mode Select JTAG Test Mode Select input
215 TRS I Test Rese t JTAG Reset input
5, 10,
32, 101,
228
RESRVD I/O Reserved These pins are reserved for future functionality
and shou ld be left fl oating.
376 Version 4.1 MXT3010 Reference Ma nual
Pin Information
TABLE 99. Power and ground pin descriptions
Pin # Symbol I/O Name Description
13, 29, 41,
49, 60, 65,
73, 89, 96,
109, 120,
133, 149,
169, 180,
193, 209,
229, 240
VDD I 3.3 volt
power supply These pins each require a +3.3 VDC (± 5%)
power supply input. They supply current to the
3.3-volt output buffers and the core logic of the
device.
37 VAA PLL power
supply This pin requires a +3.3 VDC (± 5%) power sup-
ply inpu t. It is us ed to sup ply curren t to the PL L.
Please refer to the section on the PLL for proper
decoupling strategy.
1, 7, 9, 1 9,
25, 36, 39,
43, 45, 55,
61, 69, 79,
85, 92, 99,
105, 115,
121, 129,
139, 145,
154, 159,
165, 175,
181, 189,
199, 205,
214, 219,
225, 235
GND - Ground These pins provide ground return paths for the
various power supply inputs.
MXT3010 Reference Manua l Version 4.1 377
MXT3010EP JTAG/PLL pin termination
MXT3010EP JTAG/PLL pin termination
Ta ble 100 indicates how test and reserved pins on the
MXT3010EP should be terminated for normal operation.
TABLE 100.MXT3010EP pin terminations
Pin Name Pin # Termination
BP_ 38 Exter na l pu ll up (1 K ohm s) to +3.3 V
RANGE 34
External pull up (4.7K ohms) to +3.3V
OSC_EN_ 217
TRI_ 213
TCK 27
TDI 33
TMS 207
LSSD_TEST 63 External pull down (120 ohms) to GND
TRS 215
RESERVE D 5, 10, 32,
101, 228 Leave floating
378 Version 4.1 MXT3010 Reference Ma nual
Pin Information
MXT3010EP pin listing
This section provides the pin listings for the MXT3010EP. T able
102 provides descriptions of the pin types listed in Table 101.
TABLE 101.MXT3010EP pin listing
Pin Pin Label Pad Pin Pin Pin Label Pad Pin Pin Pin Label Pad Pin
1 GND 30 RXDATA1 IO2 I/O 59 FDAT21 IO4 I/O
2 TXDATA5 IO2 I/O 31 ICSO_D IO4 I/O 60 VDD
3 RXCTRL2aIO3 OUT 32 RESRVD 61 GND
4 RXDATA0 IO2 I/O 33 TDI IN1 IN 62 FDAT19 IO4 I/O
5 RESRVD 34 RANGE IO4 PLL 63 LSSD_TEST IN2 IN
6 ICSI_A IN1 IN 35 ICSI_B IN1 IN 64 FDAT17 IO4 I/O
7 GND 36 GND 65 VDD
8 RX_CLK IO2 I/O 37 VAA 66 FADRS7 IO6 OUT
9 GND 38 BP_ 67 FDAT18 IO4 I/O
10 RESRVD 39 GND 68 FDAT16 IO4 I/O
11 RXSOC IO3 IN 40 FN 69 GND
12 RXDATA3 IO2 I/O 41 VDD 70 FADRS8 IO6 OUT
13 VDD 42 ICSI_D IN1 IN 71 FADRS4 IO6 OUT
14 RXDATA2 IO2 I/O 43 GND 72 FADRS6 IO6 OUT
15 RXENB IO3 OUT 44 FDAT31 IO4 I/O 73 VDD
16 RXDATA6 IO2 I/O 45 GND 74 FADRS5 IO6 OUT
17 RXDATA7 IO2 I/O 46 FDAT30 IO4 I/O 75 FADRS2 IO6 OUT
18 RXCTRL0 IO3 OUT 47 ICSI_C IN1 IN 76 FADRS3 IO6 OUT
19 GND 48 FDAT28 IO4 I/O 77 FWE1_ IO6 OUT
20 RXCLAV IO3 IN 49 VDD 78 FOE0_ IO6 OUT
21 RXDATA5 IO2 I/O 50 FDAT29 IO4 I/O 79 GND
22 ICSO_A IO4 I/O 51 FDAT27 IO4 I/O 80 FADRS17 IO6 OUT
23 RXDATA4 IO2 I/O 52 FDAT26 IO4 I/O 81 FWE0_ IO6 OUT
24 RXCTRL1 IO1 OUT 53 FDAT25 IO4 I/O 82 FCS1_ IO6 OUT
25 GND 54 FDAT24 IO4 I/O 83 FWE2_ IO6 OUT
26 RXCTRL3 IO2 OUT 55 GND 84 FCS0_ IO6 OUT
27 TCK IN1 IN 56 FDAT20 IO4 I/O 85 GND
28 ICSO_B IO4 I/O 57 FDAT23 IO4 I/O 86 FOE1_ IO6 OUT
29 VDD 58 FDAT22 IO4 I/O 87 FADRS14 IO6 OUT
MXT3010 Reference Manua l Version 4.1 379
MXT3010EP pin listing
88 FWE3_ IO6 OUT 126 P1RQ_ IO4 OUT 164 P1AD19 IO4 I/O
89 VDD 127 P1IRDY_ IO4 OUT 165 GND
90 FADRS16 IO6 OUT 128 P1HWE1 IO4 OUT 166 P1AD21 IO4 I/O
91 FADRS13 IO6 OUT 129 GND 167 CINBUSY IO5 OUT
92 GND 130 P1END_ IO4 OUT 168 P1AD24 IO4 I/O
93 FADRS11 IO6 OUT 131 P1QRQ_ IO4 OUT 169 VDD
94 FADRS12 IO6 OUT 132 P1AD8 IO4 I/O 170 P1AD25 IO4 I/O
95 FADRS9 IO6 OUT 133 VDD 171 P1AD27 IO4 I/O
96 VDD 134 P1RD IO4 I/O 172 P2TRDY_ IO2 IN
97 FADRS10 IO6 OUT 135 P1ABRT_ IO4 IN 173 P1AD28 IO4 I/O
98 FADRS15 IO6 OUT 136 P1AD2 IO4 I/O 174 P1AD29 IO4 I/O
99 GND 137 P1AD0 IO4 I/O 175 GND
100 FDAT13 IO4 I/O 138 P1AD9 IO4 I/O 176 P2ASEL_ IO2 IN
101 RESRVD 139 GND 177 COUTRDY IO5 OUT
102 FDAT14 IO4 I/O 140 P1AD1 IO4 I/O 178 P1AD30 IO4 I/O
103 FDAT12 IO4 I/O 141 P1AD4 IO4 I/O 179 P1AD31 IO4 I/O
104 FDAT15 IO4 I/O 142 P1AD3 IO4 I/O 180 VDD
105 GND 143 P1AD5 IO4 I/O 181 GND
106 FDAT11 IO4 I/O 144 P1AD11 IO4 I/O 182 P2QBRST IO4 OUT
107 FDAT9 IO4 I/O 145 GND 183 P2QRQ_ IO4 OUT
108 FDAT10 IO4 I/O 146 P1AD7 IO4 I/O 184 P2IRDY_ IO4 OUT
109 VDD 147 P1AD17 IO4 I/O 185 P2AD15 IO4 I/O
110 FDAT8 IO4 I/O 148 P1AD13 IO4 I/O 186 P2RQ_ IO4 OUT
111 FDAT6 IO4 I/O 149 VDD 187 P2AD14 IO4 I/O
112 P1ASEL_ IO4 IN 150 P1AD6 IO4 I/O 188 P2END_ IO4 OUT
113 FDAT7 IO4 I/O 151 P1AD10 IO4 I/O 189 GND
114 FDAT4 IO4 I/O 152 P1AD12 IO4 I/O 190 P2AD8 IO4 I/O
115 GND 153 P1AD22 IO4 I/O 191 P2RD IO4 OUT
116 P1TRDY_ IO4 IN 154 GND 192 P2AD12 IO4 I/O
117 FDAT5 IO4 I/O 155 P1AD20 IO4 I/O 193 VDD
118 FDAT3 IO4 I/O 156 P1AD14 IO4 I/O 194 P2AD11 IO4 I/O
119 FDAT2 IO4 I/O 157 P1AD23 IO4 I/O 195 P2AD4 IO4 I/O
120 VDD IO4 158 P1AD16 IO4 I/O 196 P2AD13 IO4 I/O
121 GND 159 GND 197 P2AD10 IO4 I/O
122 FDAT1 IO4 I/O 160 P1AD26 IO4 I/O 198 P2AI3 IO4 OUT
123 RESET_ IN1 IN 161 P1AD18 IO4 I/O 199 GND
124 FDAT0 IO4 I/O 162 COMMSEL IO5 IN 200 P2AD1 IO4 I/O
125 P1HWE0 IO4 OUT 163 P1AD15 IO4 I/O 201 P2AD9 IO4 I/O
TABLE 101.MXT3010EP pin listing
380 Version 4.1 MXT3010 Reference Ma nual
Pin Information
202 P2AI0 IO4 OUT 215 TRS IN2 IN 228 RESRVD
203 P2AD5 IO4 I/O 216 P2AI1 IO4 OUT 229 VDD
204 P2AD7 IO4 I/O 217 OSC_EN_ IN1 IN 230 TXDATA2 IO2 I/O
205 GND 218 TXDATA0 IO2 I/O 231 TXDATA3 IO2 I/O
206 P2AD6 IO4 I/O 219 GND 232 TXCTRL2 IO3 OUT
207 TMS IN1 IN 220 TXCTRL0bIO2 OUT 233 TXDATA4 IO2 I/O
208 P2AD0 IO4 I/O 221 TXDATA1 IO2 I/O 234 TXDATA6 IO2 I/O
209 VDD 222 TXSOC IO2 OUT 235 GND
210 P2AD3 IO4 I/O 223 TXENB_ IO2 OUT 236 ICSO_C IO4 I/O
211 P2AI2 IO4 OUT 224 TXCLAV IO3 IN 237 TXDATA7 IO2 I/O
212 P2AD2 IO4 I/O 225 GND 238 TXCTRL1 IO3 OUT
213 TRI_ IN1 IN 226 TX_CLK IO2 OUT 239 TXCTRL3 IO3 OUT
214 GND 227 TDO IO2 OUT 240 VDD
a. The RXCTRL signals use differing pad types due to their varying use in multi-PHY configura-
tions. RXCTRL [3:0] are IO2, IO3, IO1, and IO3 respectively.
b. The TXCTRL signals use dif f ering pad typ es due to their va rying use in multi-P HY config ura-
tions. TXCTRL [3:0] are IO3, IO3, IO3, and IO2 respectively.
TABLE 101.MXT3010EP pin listing
MXT3010 Reference Manua l Version 4.1 381
MXT3010EP pin listing
I/O pad referen ce
The table be low cross-map s an I/O pin to the actua l CMOS5S
I/O pad. SPICE models for these devices can be obtained by
contacting support@maker.com.
TABLE 102.I/O pad types
TYPE PAD DESCRIPTION
IO1 BT520PU_A_G 5V Tolerant Bi-direct buffer, A-slew, 20 ohm, 3-
state IO with pullup resistor.
IO2 BT520PU_B_G 5V Tolerant Bi-direct buffer, B-slew, 20 ohm, 3-
state IO with pullup resistor.
IO3 BT520PD_B_G 5V Tolerant Bi-direct buffer, B-slew, 20 ohm, 3-
state IO with pulldown resistor.
IO4 BT520PU_C_G 5V Tolerant Bi-direct buffer, C-slew, 20 ohm, 3-
state IO with pullup resistor.
IO5 BT520PD_C_G 5V Tolerant Bi-direct buffer, C-slew, 20 ohm, 3-
state IO with pulldown resistor.
IO6 BT 520_C_G 5V Tole rant Bi-direct buffer, C-slew, 20 Ohm, 3
state IO.
IN1 IT5PUT_G 5V Tolerant LVTTL Input, with internal pull up.
IN2 IT5PDT_G 5V Tolerant LVTTL Input, with internal pull
down.
382 Version 4.1 MXT3010 Reference Ma nual
Pin Information
MXT3010 Reference Manua l Version 4. 1 383
CHAPTER 19 Electrical Parameters
This chapter provides information about the electrical parameters
of the MXT3010EP. The following topics are included:
• MXT3010EP Operating conditions and maximum ratings
• MXT3010EP Power sequencing
• MXT3010EP Phase Lock Loop (PLL) implementation
384 Version 4.1 MXT3010 Reference Ma nual
Electrical Parameters
MXT3010EP maximum ratings and operating conditions
TABLE 103.Absolute maximum ratings (VSS = 0V)
Notes 1: Stresses beyond the “Absolute maximum ratings” may cause per-
manent damage to the device. These are stress ratings only.
Operation at condi tions beyond the indicated “Recomme nded
operating conditions” is not recommended and may adversely
affect device reliability.
2: Refer to Application Note 27, MXT3010EP Thermal Test Report
TABLE 104.Recommended operating conditions
Notes 1: See “Adjustments to Idc” on page 388.
2. Refer to Application Note 27, MXT3010EP Thermal Test Report
Symbol Parameter Min Max Units
VDD 3.3 volt supply -0.3 7.0 V
VIN Input voltage -0.3 7.0 V
TAOperating free-air temperature
range 0See Note 2 °C
TSTG Storage temperature range -65 150 °C
Symbol Parameter Min Max Units
VDD 3.3 volt supply 3.14 3.47 V
VIH High-level inp ut voltag e 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current 011.41mA
IOL Low-level output current 11.41mA
TJOperating junction temperature 01102°C
MXT3010 Reference Manua l Version 4.1 385
MXT3010EP maximum ratings and operating conditions
DC electrical characteristics
TABLE 105.DC Electrical characteristics
AC electrical characteristics
I/O performance levels
With the exception of the TDO scan output, all MXT3010EP
outputs uti l ize ei th er a medium or fa st spe ed I /O pa d. Th e t abl e
below summarizes the sl ew rate of ea ch pad at nominal p rocess,
25°C and 3.3V supply. For more accurate analysis, SPICE mod-
els of the I/O pads are available.
Symbol Parameter Min Max Units
ICC 3.3 vol t supply curr ent (100
MHz) 970 mA
VOH VDD = min, IOH = max 2.4 V
VOL VDD = min, IOH = max 0.4 V
CIO Typ 7pF
RIO I/O Output I mpedance (n ominal) 20 Ohms
Pd Power Dissipation @3.3/3.47V
@ 66 MHz
@ 80 Mhz
@ 100 Mhz
1.9/2.1
2.3/2.6
2.9/3.2
W
W
W
Performance L evel Slew Rate (di/dt) Drive r Sp eed
A30 mA/ns Slow
B60 mA/ns Medium
C100 mA/ns Fast
386 Version 4.1 MXT3010 Reference Ma nual
Electrical Parameters
MXT3010EP power sequencing
Overview
The MXT3010EP us es a single vol tage, +3.3 VDC ± 5%. There-
fore, there is no need to follow multiple voltage power sequenc-
ing rules. There are, however, two concerns regarding the
application of power to CMOS devices such as the
MXT3010EP. Both concer ns rela te to current flowing fr om an I/
O pin int o the chip’s VDD rai l when the I/O pi n of t he devi ce is
powered, and VDD to the device is not present.
• Dam age to I/O pad meta l
When cur re nt flows int o t he I/O pad of the unp ower ed chip,
the current flows from the I/O pad to the ESD diod es and
from there to the VDD pad. This metal is rather thin and can
be damaged from a high ins tantaneous i nrush curren t. In this
case, the metal co nnection fuse s. Another way t he metal can
be damaged is through electromigration. When electromi-
gration occurs, the metal erodes due to a moderate current
flowing for an extended period of time.
•Latch-up
The second major concern during power sequencing is a
conditi on known as lat ch-up. Lat ch-up is a des tructive e vent
that can be induced in CMOS devices. The term refers to the
'turning on' of the parasitic PNPN structure that exists as a
normal part of the CMOS gate structure. The PNPN struc-
ture is 'connected' between VDD and ground and has posi-
tive feedback. As this structure begins to conduct current
from VDD to ground, it is turned on harder, presenting a
lower impedance. The lower impedance causes more cur-
rent to flow, and the process r einforce s itself unt il the de vice
overheats and is destroyed.
MXT3010 Reference Manua l Version 4.1 387
MXT3010EP power sequencing
Current can flow from the I/O pin to the VDD rail through
the I/O pad’s ESD structure. The existence and magnitude
of the current (Ipad) generally depends on the I/O type and
the electro-static discharge (ESD) protection device it
contains. The ESD structure is a set of series diodes from
the I/O pin to VDD. In the case of the BT520 I/O pad used
in the M XT3010EP, the ESD st ructu re con sis ts of a chai n of
5 series diode s.
The two pr oblems out lined abo ve are an alyzed in greater detail ,
with specific application to the MXT3010EP, in the sections
which follow.
Damage to I/O pad metal
To determine whether damage to the I/O pad metal will occur
from fusing or metal migration, one must first analyze how
much current will flow into the pad. When powered down, the
large capacitance associated with VDD (chip, package, card,
other card components) could be modeled as a short circuit to
ground (GND). Thus, the maximum current from a pad
through the ESD diode(s) to VDD would be determined by the
voltage and output resistance of the source supplying the pad
voltage, the number and forward voltage drops of the ESD
diodes, and the series resistance of the diodes a nd interconnects.
The following equation applies:
Ipad = (Vsource-(N*0.7)) / (Rsource+2)
N = the number of diodes (1,3,5) between the pad and VDD
Vsource = source voltage applied to the pad (volts)
Rsource = output resistance of the Vsource supply (ohms)
Ipad = current into the pad (amps)
There are two limits to the acceptable pad current (Ipad). Both
are associated with current required to cause failures in the
Metal-1 (M1) wiring connecting from the pad to the ESD device
388 Version 4.1 MXT3010 Reference Ma nual
Electrical Parameters
and from the ESD de vice to VDD. The first li mit is called Ifu se.
Currents above Ifuse may immediately destroy the met al layer 1
connecti ons. All MXT3010EP I/ O pads are 5V toler ant and can
withstand an Ifuse cur rent of 129ma. The second current limit is
Idc. Currents below Idc can be safely applied for extended peri-
ods of time without causing M1 electromigration (wear-out)
failures.
Adjustments to
Idc Idc is a strong function of both temperature and the number of
power-on hours (POH) over which the current is applied All
MXT3010EP I/O pads are rated for 1 1.4ma under the conditions
of 110K POH and 100°C. Idc may be adjusted for othe r condi-
tions using the following multipliers:
Idc(POH) = Idc(table value) * (110000/POH)**0.588
Idc(temp) = Idc(table value) * exp((5459/(temp+273)-14.64))
Sample
calculation Assume all 5V tolerant inputs are being driven prior to the
MXT3010EP’s VDD rail being powered. Assume further that
VDD on the hot -plug ged ASIC part co mes up 1 s econd af ter i ts
I/O's pad receives the signal net voltage. Finally, assume that
this sc enario occ urs 10,000 t imes over t he life of th e product, i n
a system runnin g at 100 °C. A further assumption is made the
signal dr iving the I/O pa d has a 5V nomi nal sup ply volt age and
has a 20ohm nominal output impedance. Thus, Vsource = 2.5
volts and Rsource = 20 oh ms. Sinc e the BT520* I /O pad uses 5
series ESD diodes from a pad to VDD, N=5. Calculating Ipad
yields:
Ipad = (Vsource- (N*0.7)) / (Rsource+2)
= (5-(5*0.7)/(20+2)
= 0.0681
= 68.1 mA
MXT3010 Reference Manua l Version 4.1 389
MXT3010EP power sequencing
The calculated value Ipad is well below the 129 mA limit for
Ifuse, s o pa d dama ge f rom f usi ng does not occ ur. Howeve r, the
calcul ated value of Ip ad is well above the 1 1.4 mA limi t for Idc,
so this amount of cur rent can not be appl ied indef initely wit hout
affecti ng reliabi li ty.
Since we assumed that the Ipad current was being applied for 2.7
hours (10000 times for 1 seconds/time = 10000 seconds = 166
minutes = 2.7 hours) over the life of a product, Idc should be
adjusted for time:
Idc(POH) = I dc(Pad) * (110000/POH)** 0.588
Idc(2.7 ho urs) = 1 1.4 mA * (1 10000/2. 7)**0.588
= 11.4 * 513.7
= 5856 mA
This number is nearly two orders of magnitude above Ipad, so
we could stop here and conclude that the described application
will not effect reliability. Clearly , most cases of this type will be
limited by Ifuse well before Idc, but both Ifuse and Idc limits
should be checked.
I/O pad latch-up
I/O pad latch-up occurs when free charge in the semiconductor
substra te get s to th e wrong pl ace. Troublesome amou nts of f ree
char ge can be introduced by very l arge currents flo wing thr ough
the ESD diodes or other paths. Latchup is generally prevented
by isolating and protecting the parasitic PNPN structure from
collecting free charge.
It is difficult or impossible to induce latch-up in the device dur-
ing power up. As the device is conducting current from the I/O
pin to the VDD rail, there may be some free charge introduced
into the substrate. There is no power applied to the device at this
point, so latch up cannot occur.
390 Version 4.1 MXT3010 Reference Ma nual
Electrical Parameters
As the device VDD is applied, the current flowing through the
ESD diodes is sharply re duced. This is because the forwar d volt-
age drop of the ES D di ode s is about 3.5 vo lt s, so for an I/O pad
voltage of 5V, the ESD current drops to zero when the chip’s
VDD reaches 1.5V. Before the VDD level of the chip attains suf-
fici ent voltage to sustain latch-up, the ESD current has b een
neutralized due to the forward drop of the 5 series connected
ESD diodes.
Additionally, the CMOS device is generally designed to with-
stand several hundred milliamperes of ESD diode current with-
out having latchup problems. This level of current is never
attained du ring th is power up situ ation, furthe r reinforcing the
latch up protection.
MXT3010EP PLL considerations
Overview
The MXT3010EP has an internal Phase Lock Loop (PLL) which
it uses to generate the on-chip clock. This PLL allows the on-
chip clock tree delay to be neutralized, and optimum perfor-
mance of the IC to be obtained. The on-chip PLL can be affected
by external circuit noise, so careful circuit design must be
employed to optimize the performance of the PLL.
Degradation of the PLL performance manifests itself as jitter.
This jitter is measured as the timing variation of the chip’ s inter-
nal clock to a stable reference clock supplied to the chip on the
FN pin (pin 40). The i nternal c lock cannot be o bserve d directly,
but any jitter on the internal clock will show up as jitter on the
UT OPIA transmit clock , TX_CLK (pin 226 ). Jit ter will c ause a
MXT3010 Reference Manua l Version 4.1 391
MXT3010EP PLL considerations
variation in the timing of the chip relative to the board clock.
The timi ng variatio n will aff ect setup and h old timing an d erode
timing margins at the chip interface.
The following sections cover circuit design issues which affect
the opera tion of t he PLL. Key areas of inter est are de- coupli ng,
creating a quiet PLL VDD, and ensuring a good PCB layout of
the PLL a rea. The foll owing s ecti ons al so dis cuss th e use of ref -
erence clocks, which may have jitter , and a method to bypass the
internal PLL of the MXT3010 in special applications.
VAA decoup li ng
The PLL has a separate power pin labeled VAA (pin 37). This
pin must be s upplied with a ve ry stable voltag e level and shoul d
be well decou pled. The cur rent dr aw of this pin is ver y low, 2.5
mA nomina l. The l ow cur rent draw al lows t he vol tage t o be i so-
lated from the 3.3V power plane with a resistor. The use of a
resistor instead of an inductor provides very good isolation from
lower fr equency nois e such as power supply switc hing noise. A
ferrite bead or inductor will not introduce a DC voltage drop, but
it will also not filter low frequency noise. Due to the low current
draw, use of a resistor is the recommended solution. The VAA
pin shoul d al so be bypassed wit h a c o mbi nat ion of a 10µF tanta-
lum cap and a 0.01µF ceramic cap as shown in Figure 109 on
page 392.
If the VAA pin is supplied voltage from a linear regulator, the
designer must ensure t hat enough current is being dr awn to keep
the regulator in regulation. The output of a linear regulator is
essentially noise free.
392 Version 4.1 MXT3010 Reference Ma nual
Electrical Parameters
FIGURE 109.Gener at ing a quie t VA A
General decoupling
The MXT3010EP must be properly decoupled to ensure clean
PLL operat io n. The PLL i s most se nsi t ive to noise on t he VDD
supply. VDD noise contains both low frequency and high fre-
quency components. Power supply switching noise or insuffi-
cient bulk decoupling causes low frequency VDD noise. The
switching of the digital logic drivers causes high frequency
noise. Bot h of thes e noise s ources must be taken into acc ount to
ensure optimum performance.
The MXT3010EP ha s ni net een 3.3V supply pin s. The re should
be ninete en high fre quency decoup ling caps on th e 3.3V supply
surrounding the chip. Additionally, there should be a minimum
20µF of bulk decoupling on the supply voltage (VDD) nearby to
the chip. This can be a single 22µF tantalum capacitor, or pref-
erably a pair of 10µF tant alum capacitors.
In a switching power supply environment, it is beneficial to fil-
ter the swit ching noise. This can be accomplished by fi ltering
the MXT3010EP’s VDD with a ferrite bead. The ferrite bead
works in conjunction with the bulk decoupling capacitors to
effectively filter the power supply switching noise. The ferrite
bead must be siz ed to ha ndle the current draw of the en tire ch ip.
An appropriate part is the FairRite 2743021446 surface mount
ferrite bead.
VDD Plane
27 ohm
VAA (Pin 37)
10 µF.01 µF
Locate close to
pin 37 of the
MXT3010EP
MXT3010 Reference Manua l Version 4.1 393
MXT3010EP PLL considerations
FIGURE 110.MXT3010EP decoupling capaci tor location
Figure 110 shows the optimal loca ti on of th e decoupling ca pac-
itors around the MXT3010EP. This di agram depicts the locati on
of 0805 size 0.01µF capacitors under the chip pin pads on the
bottom si de of the board. The capaci tors are l ocated cl ose to th e
associated power pins. The capacitor should share a common via
with the power pin of the ch ip with a minimum length et ch. The
same should be done with the ground connections.
Reference clock jitter
The PLL of the MXT3010EP locks the i nternal chip clock to the
reference clock supplied to the device. The PLL will not neces-
sarily be able to track jitter which is on the reference clock. If
there is significant jitter on the reference, and the chip clock
does not track it, the jitter will cause a reduction in timing mar-
gin at the chip interface.
Jitter on the reference clock can be caused by power supply
noise af fecti ng components o f the clock generation a nd distribu-
tion c ir cui t. One pot ent ia l sour ce of j it te r is power supply noi se
or poor decouplin g of crys tal osci llator s. Noise o n the osci llator
power pin, whet her fr om the boa rd or s elf-i nduced , can conv ert
to timing jitter at the oscillator output. Some devices are better
3.3 V Bypass
22 µF Cap
22µF Cap
MXT3010EP
.01 µF Cap
394 Version 4.1 MXT3010 Reference Ma nual
Electrical Parameters
than others in this aspect of operation. To reduce this noise
source, ensure th at th e osci llat or is well decoupl ed acc ordin g to
the manufacturer’s specifications.
The distr ibuti on of the ref erenc e clock can also introdu ce clock
jitte r. Designs t hat us e d ividers in th e r eference cloc k path must
avoid the possibility of simultaneous switch ing jitter , which can
occur in sy nchrono us cou nters . PLL clock buf f ers can als o be a
source of jitter, as these devices are generally susceptible to
power supply noise, and can convert this noise to timing jitter.
Circuit design goals
It is desirable to keep VDD noise as low as possible. The PLL
performance may start to degrade for high frequency noise
greater than 40mV p-p and low frequency noise greater than
20mV p-p. The low frequency noise is defined as the noise
below 20 MHz. The high frequency noise is defined as the full
bandwidth noise measurement minus the low frequency noise.
To ensure accuracy, measurements should be performed with a
coaxial probe terminated in 50 ohms.
The PLL is sensi tive to the frequ ency of the noise on VDD. The
above guidelines may be conservative depending upon the
application. Low frequency noise in the 100kHz to 500kHz
range is the most critical.
The recommended VAA decoupl ing shoul d gua rantee l ess tha n
2mV p-p noise on the VAA voltage.
The jitter on the reference clock should be kept to less than
500pS peak to peak. The PLL is sensitive to the frequency of this
jitter and may track or filter this jitter based on the jitter fre-
quency a nd the PLL bandwidth. If the PLL doe s not trac k the jit-
ter closely, the board level timing will be affected.
MXT3010 Reference Manua l Version 4.1 395
CHAPTER 20 Mechanical and Thermal
Information
This chap ter provides inf ormation on the MXT3010EP mec han-
ical and thermal properties.
396 Version 4.1 MXT3010 Reference Ma nual
Mechanical and Thermal Information
MXT3010EP mechanical/thermal information
The MXT3010EP is p ackaged in a 240- pin th ermall y enhanc ed
quad flat-pack.
FIGURE 111.MXT301 0E P package/pin diagram - top view
MXT3010EP
top view
32.0±0.2
34.6±0.2
32.0
±0.2
34.
6
±0.
2
1.25
TYP
1.25
TYP 0.5 0.22±0.05
160
61
120
121
180
181
240
MXT3010 Reference Manua l Version 4.1 397
MXT3010EP mechan ic al/ the rmal informa tio n
FIGURE 112.MXT3010EP package/ pin diagram - side view
TABLE 106.MXT3010EP package summary
* These numbers will vary depending on the board stack-up and orientation. All airflow numbers
are quoted with 1m/sec of air flow over the device.
The MXT3010EP is a level 3 IAW IPC-SM-786A or JESD 22-
A112 device. The MXT3010’s safe floor life (out of bag) prior
to solder reflow is 1 we ek at ≤ 30°C/60% RH.
Package θ
jc
(×C/W) θ
ja
(×C/W)
Package Type Body size (mm) Lead pitch (mm) *Still Air *Air Flow
MHS PQFP 240 32.0 x 32.0 x 3.0 0.5 2.0 20 14
33.6±0.2
4.1
MAX
3.4
REF
0.25
MIN
0°~7°
0.5 ~ 0.75
0.09 ~ 0.20
398 Version 4.1 MXT3010 Reference Ma nual
Mechanical and Thermal Information
MXT3010 Reference Manual Vers ion 4.1 399
APPENDIX A Acronyms
Acronym Definition
AAL ATM Adaptation Layer
ABR Available Bit Rate
ACR Available Cell Rate
ATM Asynchronous T ransfer Mode
CAM Con tent Addressable Memor y
CBR Constant Bit Rate
CDV Cell Delay Variation
CDVT Cell Delay Variatio n Tolerance
CI Congestion Indicator
CLP Cell Loss Priority
CPCS Common Part Convergence Sublayer
CPI Common Part Identifier
CRC Cyclic Redundancy Check
CSS Cell Schedu lin g Sy stem
DMA Direct Memory Access
E1 European 2.048 Mbps rat e TDM system
EFCI Explicit Forward Conges tio n Ind ica tor
ESS External State Signals
FIFO First In First Out
GCRA Generic Cell Rate Algorithm
GFC G eneral Flow Control
400 Version 4.1 MXT3 01 0 Reference Manua l
HEC Header Error Control
ICS Interchip Communication System
IFO Instruction Field Option
JT2 96-c h an ne l TD M sy s te m us e d by Japa n Telephone
MIB Management Information Base
MVIP Multi-Vendor Integration ProtocolTM
OAM Operations and Management
PCR Peak Cell Rate
PDU Physi cal Data Unit
PHY Physical Layer
PIT Pr ogram m a bl e In t e r v al Timer
PTI Payload Type Identifier
RAM Random Access Memory
RM Resource Management
RX Receive
SAR Segmentation and Reassembly
SCSA Signal Computing System Architecture, ANSI standard
SDU Service Data Unit
SHFM Store Halfword to Fast Memory
SRAM Static Random Access Memory
SRTS Synchronous Residual Time Stamp
SWAN Soft-Wired ATM Network
TDM Time Division Multiplexing
T1 24-channel TDM system used in North America
TX Transmit
UBR Undefined Bit Rate
UDT Unstructured Data Transfer
UU User-to-User
VBR Variable Bit Rate
VC Virtual Channel
VCI Virtual Channel Identifier
VP Virtual Path
VPI Virtual Path Identifier
Acronym Definition
MXT3010 Reference Manual Version 4.1 401
APPENDIX B Device Initialization
This append ix describ es the proced ures for ini tiali zing and down-
loading fir mware to the MXT3010. The fo llowing information
appears in this appendix:
• Initializing the MXT3010
• Downloading firmware
• Initializing the Mode Configuration register
402 Version 4.1 MXT3 01 0 Reference Manua l
Initializing the MXT3010EP
To initialize the MXT3010EP:
1. Assert RESET_ asynchronously to the input clock, FN.
2. Hold the RESET_ pin low for a period of time to allow the
PLL to lock. For power-up, hold RESET_ as indicated in
“T imi ng” on page 343. For reset during po wered oper ation,
hold RESET_ for 16 clock ticks.
3. Remove RESET_ synchronously with respect to the input
clock. The reset stat e continue s fo r 2056 cl ock ti cks follo w-
ing the removal of RESET_. The MXT3010EP will not
read or write the COMMIN/COMMOUT registers during
this time, nor will the CIN_BUSY or COUT_RDY flags
function during this time. Maker recommends that a host
software timer be used between the removal of RESET_
and the beginning of boot download.
Downloading firmware
This secti on desc ri bes:
• How the system determines the boot path
• How the application program uses the output pins
• How the code set is structured
• How to boot the firmware
• Limitations on the size of boot code
How the system determines the boot path
Firmware struc tured as a sin gle-us er c ode se t for the MXT3010
can be loaded through one of three paths:
MXT3010 Reference Manual Version 4.1 403
Downl oading firmware
• Through Port1, from a byte-wide device.
• Through Port2, from a byte-wide device.
• Through the COMMIN register.
The system signals the choice of boot path to the MXT3010 as
the devi ce exits r es et mode. Dur ing rese t, t he M XT3010 place s
the ICSO_A and ICSO_B pins into tri-state mode. The
MXT3010 sens es th e state of these pins as RESE T_ is removed
to determine the boot method. Each of these pins is pulled either
high or low to signal the appropriate boot pat h to the MXT3010.
During normal device operation, the ICSO_A and ICSO_B pins
function as outputs.
How the application uses the output pins
After the MXT3010 initialization routine is completed, control
of the devi ce passes to t he application pr ogram. The applica tion
program c an t hen use t he I C SO_A an d I C SO_B pi ns b y settin g
the appropriate bits in the system register.
TABLE 107.Selecting boot mode with ISCO_A and ICSO_B
ICSO_A ICSO_B Boot MODE
0 0 Reserved
0 1 Port1 Memory
1 0 Port2 Memory
1 1 COMMIN Register
404 Version 4.1 MXT3 01 0 Reference Manua l
How the code set is structured
The output of the SWAN Processor’s assembler is one or more
user -co de set s. The u ser -c ode set incl udes f our f ields; see Table
108. The MXT3010 loads a single user -code set at device initial-
izati on. Support for loa ding multip le user -code sets comes from
an intermediate boot loader routine.
As the code set is loaded, the MXT3010 computes a 16-bit
checksum. This checksum is a running 16-bit sum of each half-
word of t he user co de set. All carrie s are d iscarded and not use d
as part of the checksum routine. Upon completion of the trans-
fer, the c hecksum is wr itten to the COMMOUT register. The
host must read the COMMOUT register to clear the COM-
MOUT Busy flag. The host can then compare the checksum to
the checksum contained in the tail of the image block. The
MXT3010 does n ot read th e checksum fi eld of the u ser-code set
when loading a .ld file from Port1 or Port2 memory. The
MXT3010 firmware does read the checksum field when down-
loading a .ubf file.
As the code set is loaded into Fast Memory , the MXT3010 stores
the starting addr ess location. A t the co mpletion of the loadi ng
operati on, the MXT3010 branc hes to this lo catio n in Fa st Mem-
ory to execute the program.
TABLE 108.User code set’s four fields
Field Description Size
1. The starting word address (cod e address) in Fast
Memory to which the user code set is to be stored. 2 byte s
2. The number of half words i n the user code set . 2 byte s
3. The user code. variab le
4. The che cksum cal c ulat ed by the host f or code se t
containing all four fields. 2 bytes
MXT3010 Reference Manual Version 4.1 405
Downl oading firmware
How to boot
This section describes how to boot from Port1, Port2, and the
COMMIN register.
Booting from Port1
When the Port1 memory boot mode is selected, the MXT3010
reads the user-code set from a Port1-based memory device
(RAM or ROM) begi nning at location 0x FFF00000. To support
byte-wide boot ROMs, the MXT3010 reads a single byte from
each 32-bit word location. Therefore, for the host processor to
copy the MXT3010’s boot image into RAM located at
0xFFF00000, i t must place a single byte of code into each 3 2-bit
word location. Align bits (7:0) of the byte-wide boot device with
PIAD (31:24) of the MXT3010.
The MXT3010 issues single-word Port1 memory read opera-
tions until all of the fields shown in Table 108, except field #4,
the checksum field, are read from Port1 memory. Once these
fields are read and placed into the specified location in Fast
Memory, the MXT3010 wr it es t he resul t of i ts c hec ksu m opera-
tion into COMMOUT register[31:16], or the Port1 memory
address location specified, and jumps to the first word of user
code.
Address Byte 0 Byte 1 Byte 2 Byte 3
31 0
0x0000 Not used Not us ed Not used
0x0004 Not used Not us ed Not used
0x0008 Not used Not us ed Not used
0x000C Not used Not us ed Not used
0x00010 Not used Not used Not used
.Not used Not used Not used
.Not used Not used Not used
.Not used Not used Not used
406 Version 4.1 MXT3 01 0 Reference Manua l
Booting from Port2
When the Port2 memory boot mode is selected, the MXT3010
reads the user-code set from a Port2-based memory device, such
as a f la sh RAM or EEPROM devi ce. The Port2 bo ot address of
0x0000 maps in non-burst space. Using this mapping, the
MXT3010 can use a slow flash device as the initialization
device. The MXT3010 inserts seven wait states for each Port2
read operation. To support byte-wide boot ROMs, the
MXT3010 reads a single byte from each 16 bit word of Port2
memory.
The MXT3010 iss ues Port2 memory r ead opera tions until all of
the fields shown in Table 108, except field #4, the checksum
field, are read from Port2 memory. Once these fields are read
and placed into the specified location in Fast Memory, the
MXT3010 writes the result of its checksum operation into the
COMMOUT reg ister[31:16], or the Po rt2 memory address l oca-
tion specified, and jumps to the first word of user code.
Booting from the COMMIN Register
A boot from the COMMIN register is performed 16 bits at a
time. The host writes the block into the COMMIN register using
COMM I/O. The first 16 bits are written from bits (31:16) of the
firs t image block wor d, the sec ond 16 bits are written from bit s
Address Byte 0 Byte 1
15 0
0x0000 Not used
0x0002 Not used
0x0004 Not used
0x0006 Not used
0x0008 Not used
.Not used
.Not used
.Not used
MXT3010 Reference Manual Version 4.1 407
Downl oading firmware
(15:0) of the first image block word, and so on. The following
diagram shows this process, arbitrarily assigning the letters A,
B, C, and D to represent successive 16-bit quantities.
.
The host must write all of the fields shown in Table 108 on
page 404, except fie ld #4, the checksum f ield. Onc e these fields
are read and placed into the specified location in Fas t Memory,
the MXT3010 writes the result of its checksum operation into
the COMMOUT register[31:16], and jumps to the first word of
user code.
Limitation s on the size of boot code
Due to address calculation carry limitations, the MXT3010EP
has restrictions on the maximum size of the code it can boot
from the boot image. The rest rictions depend upon the boot pat h
used:
Boot Path Restriction
Port1 4K instructions
Port2 512 instr u c tio ns
COMMIN register No restrictions
31 16 15 0
AB
CD
EF
Host Memory 31 16
A
B
C
D
COMMIN_HIGH (R40)
First write
Second write
Third write
Fourth write
31 16
31 16
31 16
408 Version 4.1 MXT3 01 0 Reference Manua l
For thos e boot paths that have restrictions, speciali zed bootstrap
code can be written. For example, using Port2, the code could
load 512 instruction s starting a t a 512 word boundary. That code
could include a secondary bootstrap program to perform address
calculations and load the remainder of the application indepen-
dent of code size restrictions.
Initializing the Mode Configuration register
The Mode Co nfigurat ion Regis ter(R42) is af fect ed by t hree pro -
cesses i n the MXT30 10. The se proce sses pr oceed se rially, start-
ing at hardware reset.
1. Hard ware re set
Hard ware re set initializes R42 to all ze ros.
2. Operation at boot time
The Mode Configuration register (R42) must be initialized
at boot time since some system aspects of the MXT3010’s
operati on are contr olled by thi s register. At boot t ime as the
executable image is loaded into the MXT3010, the first 32-
bit word of t h e loa d ed i ma ge sets the leas t- signifi cant ei ght
mode bits in R42 with t he indicate d va lues. For an explana -
tion of these bits, see “R42-write Mode Configuration reg-
ister” on page 201.
The format of this boot word is a bit-mapped 8-bit field.
The state of each of the relevant bits indicates the desired
state of the associated mode bit. Although writes to R42
can only set or clea r one bit at a ti me, the boot word af fec ts
the state of bits [7:0] simultaneously. The micro-boot
sequence parses the boot word and creates the individual
R42 writes needed to affect each bit.
The syntax for the assembler is:
MXT3010 Reference Manual Version 4.1 409
Initializing the Mode Configuration register
#define #boot_value 0x000000zz;‘zz is the
;desired value
....
LIMD R36, #boot_value ;‘zz programmed
;to R42
;automatically by
;microboot
....
The LIMD instruct ion must be the first ins truction in the
executab le image . The regis ter u sed for this operat ion must
be the bit bucket (R36).
3. Firmware changes to register value
Although t his regis ter is aut omatically i nitialize d, firmware c an
stil l change the v alue of this register thr ough the set/clear oper-
ations.
Restrictions on startin g add resses
All syste ms operating in Fast Memory mode 1 have res trictions
on the values that can be used for bootstrap starting addresses.
Systems operating in Fast Memory mode 1 should use starting
addresses from the following table:
For applications that must run at a different starting address,
these res trictions can be avoided by using a se condary bootstrap
program.
TABLE 109.Bootstrap starting addresses for Fast Memory mode 1
MXT3010EP - mo dulo 32K
0x00000
0x08000
0x10000
410 Version 4.1 MXT3 01 0 Reference Manua l
MXT3010 Reference Manua l Version 4. 1 411
APPENDIX C Quick Refer ence
This appendix contains duplicate copies of useful charts which
appear elsewhere in this book, plus a summary of the MXT3010
SWAN processor instruction set.
412 Version 4.1 MXT3010 Reference Ma nual
Hardware register summary
TABLE 11 0. Hardware registers
Location Name Read/Write
R32 General Purpose - 0000 R/W
R33 General Purpos e - FF FF R/W
R34 General Purpos e - FF 00 R/W
R35 General Purpose - 0040 R/W
R36-Write The Bit Bucket W
R37 General Purpos e R/W
R38 General Purpos e R/W
R39 General Purpos e R/W
R40 COMMOUT/COMMIN(31:16) R/W
R41 COMMOUT/COMMIN(15:0) R/W
R42-Read ESS register R
R42-Write Mode Config uratio n re giste r Set/Clear
R43-Read Fast Memory Bit Swap register R
R43-Write UTOPIA TX Control FIFO register W
R44 CRC32PRX (15:0) R/W
R45 CRC32PRX (31:16) R/W
R46 CRC32PRY (15:0) R/W
R47 CRC32PRY (31:16) R/W
R48 rla Address register R/W
R49 rla Address register R/W
R50 rla Address register R/W
R51 rla Address register R/W
R52 Alternate Byte Count /ID register R/W
R53 Instruction Base Address register R/W
R54 Programmab l e Interval Timer (PIT0) R/W
R55 Programmab l e Interval Timer (PIT1) R/W
R56 The Fast Memory Data register R/W
R57-Read Sparse Event/ICS register R
R57-Write Sparse Event/ICS register Set/Clear
R58 Fast Memory Shadow register R/W
R59 Branch register R/W
R60 CSS Configuration register R/W
R61-Read Scheduled Address register R
R62 UTOPIA Configuration register R/W
R63 System reg i ster R/W
MXT3010 Reference Manua l Version 4.1 413
ALU instruction fie ld summary
ALU in s t r uctio n field summar y
TABLE 111. MODx fields
TABLE 112. abc fields
TABLE 113. AE field
TABLE 114. UM field
Value Modulo Operation Value Modulo Operation
0000 MOD2 1000 MOD512
0001 MOD4 1001 MOD1K
0010 MOD8 1010 MOD2K
0011 MOD16 1011 MOD4K
0100 MOD32 1100 MOD8K
0101 MOD64 1101 MOD16K
0110 MOD128 1110 MOD32K
0111 MOD256 1111 Default
Value Branch Code Description
000 default No branch
001 BGEZ Bra nch if greater than or equal to zero
010 ----- ------
011 BZ Branch if zero
100 BLEZ Branch if less than or equal to zero
101 BLZ Branch if less than zero
110 BNZ Branch if not zero
111 BNO Branch if no overflow
Value Action
0 Conditional execution
1 Always execute target instructions
Value Action
0Don’t update memory
1 Update memory
414 Version 4.1 MXT3010 Reference Ma nual
Shift amou nt summary
TABLE 115. Shift amount chart for SFT, SFTLI, and SFTRI
TABLE 116. Shift amount chart for SFTC and SFTCI
SFT/SFTLI SFT/SFTRI
(4:0) Shift Left by (4:0) Shift Right by
00000 0 10000 16
00001 1 10001 15
00010 2 10010 14
00011 3 10011 13
00100 4 10100 12
00101 5 10101 11
00110 6 10110 10
00111 7 10111 9
01000 8 11000 8
01001 9 11001 7
01010 10 11010 6
01011 11 11011 5
01100 12 11100 4
01101 13 11101 3
01110 14 11110 2
01111 15 11111 1
(3:0) Shift left circular by (3:0) Shift left circular by
0000 0 1000 8
0001 1 1001 9
0010 2 1010 10
0011 3 1011 11
0100 4 1100 12
0101 5 1101 13
0110 6 1110 14
0111 7 1111 15
MXT3010 Reference Manua l Version 4.1 415
Shift amount summary
TABLE 117. Shift amount chart for SFTA
TABLE 118. Shift amount chart for SFTAI
(4:0) Shift right arit hmetic by (4:0) Shi ft right arithmetic by
00000 0 10000 16
00001 1 10001 15
00010 2 10010 14
00011 3 10011 13
00100 4 10100 12
00101 5 10101 11
00110 6 10110 10
00111 710111 9
01000 8 11000 8
01001 9 11001 7
01010 10 11010 6
01011 11 11011 5
01100 12 11100 4
01101 13 11101 3
01110 14 11110 2
01111 15 11111 1
(3:0) Shift right
arithmetic by (3:0) Shift right
arithmetic by
0000 0 1000 8
0001 1 1001 9
0010 2 1010 10
0011 3 1011 11
0100 4 1100 12
0101 5 1101 13
0110 6 1110 14
0111 7 1111 15
416 Version 4.1 MXT3010 Reference Ma nual
Branch instruction field summary
TABLE 122.The CSO field
TABLE 119. The ESS field (condition codes)
ESS Condition ESS Condition
ESS0 ICSI_A ESS8 Sparse even t register, bit OR
ESS1 ICSI_B ESS9 RXBUSY counter > 0
ESS2 TXFULL counter ≤ 2 ESS10 TXFULL counter = full
ESS3 RXBUSY counter ≥ 4 ESS11 DMA1 Output or Queue
stage busy
ESS4 Assigned Cell Flag ESS12 DMA2 Output or Queue
stage busy
ESS5 CSS operation in progress ESS13 DMA1 Queu e stage busy
ESS6 COMMIN_BSY ESS14 DMA2 Queu e stage busy
ESS7 COMMOUT_BSY blank Unconditional Branch
TABLE 120.The S-bit field
S Branch Result
0 Branch is taken if condition = 0
1 Branch is taken if condition = 1
TABLE 121.The C-bit field
Type of
Branch
Condition
Code
Satisfied?
Conditional
Operator
(C-bit)
Never
Execute
Operator
Committed
Slot
Instruction
Executed?
Conditional Yes Note 1 Note 2 Yes
Conditional No Absent Note 2 Yes
Conditional No Present Note 2 No
Unconditional Note 1 Absent Yes
Unconditional Note 1 Present No
CSO Hex / Binary Value Operation
DRXBUSY E0 / 1110 0000 Decrement RXBUSY counter
DRXFULL E1 / 1110 0001 Decrement RXFULL counter
ITXBUSY C2 / 1100 0010 Increment TXBUSY counter
ITXFULL C3 / 1100 0011 Increment TXFULL counter
MXT3010 Reference Manua l Version 4.1 417
DMA instruction field summary
DMA instruction field summary
TABLE 123.Use of the I-bit
Bits [26] Description
0 Do not in crement the rla regist er
1 Increment rla register upon completion of DMA operation
TABLE 124.Use of the BC field
DMA Instructions
Bits [26:19]
DMA+
Instructions
Bit s [25:1 9] Descriptiona
a. See “Use of odd BC values” on page 287.
0 0 Transfer 0 Bytes.
2 2 Transfer 2 bytes
4 4 Transfer 4 bytes
6 6 Transfer 6 bytes
---
126 126 Transfer 1 26 bytes
128 N ot Avail able Transfer 128 bytes
- Not Available -
254 Not Available Transfer 254 b ytes
TABLE 125.Use of the Control byte
Bit Name Function
9 IBI Internal flag. Not used by programmers.
8 CRCX CRC32 Partial Result is generated b ased on CRC3 2PRX
register’s value and the result is deposited into
CRC32PRX (R44/R45).
7 CRCY If set, a CRC32 Partial Result is generated based on
CRC32PRY register’s value and the result is deposited
into CRC32PRY (R46/R47)
6 POD If set, TXBUSY is incremented upon the completion of
DMA reads, and RXFULL is decremented upon comple-
tion of DMA writes.
5 ST If set, a “Silent Transfer” is performed.
418 Version 4.1 MXT3010 Reference Ma nual
Instruction summary
TABLE 126.Instruction summary
Instruction Function & Format Pg.
ADD Add registers
ADD (rsa,rsb) rd [MODx][abc][AE][UM] page
234
ADDI Add register and intermediate
ADDCI (rsa,usi) rd [MODx][abc][UM] page
235
AND AND registers
AND (rsa,rsb) rd [MODx][abc][AE][UM] page
236
ANDI AND register and immediate
ANDI (rsa,si) rd [abc][UM] page
237
BF Branch Fast Memory Shadow Register
BF [ESS#/(0| 1)/[C]][(cso)][ N] page
270
BFL Branch Fast Memory Shadow Register and link
BFL [ESS#/(0|1)/[C]][(cso)][N] page
271
BI Branch immediate
BI wadr [ESS#/(0|1)/[C]][(cso)][N] page
272
BIL Branch immediate and link
BIL wadr [ESS#/(0|1)/[C]][(cso)][N] page
273
BR Branch register
BR wadr [ESS#/(0|1)/[C]][(cso)][N] page
274
BRL Branch register and link
BRL wadr [ESS#/(0|1) / [C] ][(cs o) ][N] page
275
CMP Compare two registers
CMP (rsa,rsb) [abc] [AE] page
238
CMPI Compare register and immediate
CMPI (rsa,si) [abc] page
239
CMPP Compare two registers with previous
CMPP (rsa,rsb) [abc][AE] page
240
CMPPI Compare register and immediate with previous
CMPPI (rsa,si) [abc] page
241
DMA1R Direct memory operation - Port 1 read
DMA1R rsa/rsb, rla [BC/#][CRC {X,Y}][POD]
[ST]
page
289
MXT3010 Reference Manua l Version 4.1 419
Instruction summary
DMA1R+ Direct memory operation - Port 1 read
DMA1R+ rsa/rsb, rla [BC/#][CRC {X,Y}][POD]
[ST]
page
289
DMA1W Direct memory o peration - Port 1 write
DMA1W rsa/rsb, rla [BC/#][CRC {X,Y}][POD]
[ST]
page
290
DMA1W+ Direct memory operation - Port 1write
DMA1W+ rsa/rsb, rla [BC/#][CRC {X,Y}][POD]
[ST]
page
290
DMA2R Direct memory operation - Port 2 read
DMA2R rsa/rsb, rla [BC/#][POD] page
291
DMA2R+ Direct memory operation - Port 2 read
DMA2R+ rsa/rsb, rla [BC/#][POD] page
291
DMA2W Direct memory o peration - Port 2 write
DMA2W rsa/rsb, rla [BC/#][POD] page
292
DMA2W+ Direct memory operation - Port 2write
DMA2W+ rsa/rsb, rla [BC/#][POD] page
292
FLS Find last set
FLS (rsa,rsb) rd [abc][AE][UM] page
242
LD Load register
LD rd @rla [IDX/#] page
321
LDD Load double register
LDD rd @rla [IDX/#] page
322
LIMD Load immediate
LIMD rd,li [UM] page
243
LMFM Load multiple from Fast Memory
LMFM rd @rsa/rsb #HW [LNK] page
308
MAX Maximum of two registers
MAX (rsa,rsb) rd [MODx][abc][AE][UM] page
244
MAXI Maximum of register and intermediate
MAXI (rsa,si) rd [abc][UM] page
245
MIN Minimum of two regis ters
MIN (rsa,rsb) rd [MODx][abc][AE][UM] page
246
MINI Minimum of register and intermediate
MINI (rsa,si) rd [abc][UM] page
247
Instruction Function & Format Pg.
420 Version 4.1 MXT3010 Reference Ma nual
OR OR registers
OR (rsa,rsb) rd [MODx][abc][AE][UM] page
248
ORI OR register and immediate
ORI (rsa,si) rd [abc][UM] page
249
POPC Ser vice schedule
POPC rd@rsb page
278
POPF POP fast
POPC rd@rsb page
279
PUSHC Schedule
PUSHC rsa@rs b page
280
PUSHF PUSH Fast
PUSHF rsa@rs b page
281
SFT Shift sign ed amoun t
SFT (rsa,rsb) rd [MODx][abc][UM] page
250
SFTA Shift right arithmetic
SFTA (rsa,rsb) rd [MODx][abc][UM] page
251
SFTAI Shift right arithmetic immediate
SFTAI (rsa,usa) rd [MODx][abc][UM] page
252
SFTC Shift left circular
SFTC (rsa,rsb) rd [MO Dx][abc][UM] page
253
SFTCI Shift circular immediate
SFTCI (rsa,usa) rd [MODx][abc][UM] page
254
SFTLI Shift left immediate
SFTLI (rsa,usa) rd [MODx][abc][UM] page
255
SFTRI Shift right immediate
SFTRI (rsa,usa) rd [MODx][abc][UM] page
255
SHFM Store halfword to Fast Memory
SHFM @rsa/rsb page
311
SRH Store register halfword
SRH @rsa/rsb [adr][r eg][ lsbs ] page
312
ST Store register
ST rsa @rla [IDX/#] page
323
STD Store double register
STD rsa/rsb @rla [IDX/#] page
324
Instruction Function & Format Pg.
MXT3010 Reference Manua l Version 4.1 421
Instruction summary
SUB Subtract registers
SUB (rsa,rsb) rd [MODx][abc][AE][UM] page
256
SUBI Subtract register and intermediate
SUBI (rsa,usi) rd [MODx][abc][UM] page
257
XOR XOR registers
XOR (rsa,rsb) rd [MODx][abc][AE][UM] page
258
XORI XOR register and intermediate
XORI (rsa,usi) rd [abc][UM] page
259
Instruction Function & Format Pg.
422 Version 4.1 MXT3010 Reference Ma nual
MXT3010 Reference Manual Versio n 4.1 423
A
AC Electrical Characteristics 385
Acronyms 399
Address 123
Address index 141
Address masking (Z-bit) 296
Address spaces 11
AI pins 141
Alternate address field (adr) in SRH 306
Alternate Byte Count/ID register (R52) 207, 209,
287
ALU branch operations 228, 327
ALU instructions 19, 223
Assigned Cell flag 31, 200, 278
ATM Header 62
Automatic memory update 228
Automatic-turnaround 114
Available Bit Rate (ABR) 35
B
Big-endian design 11
Bit 26 usage in DMA instructions 285
Bit Bucket register (R36) 197
Boot bit 210
Boot path 402
Booting
From Port1 405
From Port2 406
From the COMMIN Register 406
Branch Fast Memory instructions, use of R58 215
Branch instructions 19 , 261
Basic Branch instructions 19
Target address 20
Branch register (R59) 216, 268
Branch with counter control 329
Branch with shadow address 329
Bus driving , turnaround, and hold ing 158
Bus parking 101
Byte Count (in R52) 209
Byte Count field (BC) 286
Byte manipu lations on Port1 108
Byte swap support, load and store instructions 319
Index
424 Versi on 4.1 MXT3010 Re ference Ma nual
C
C bit 265
Cell Buffe r RAM 59
Access methods 64
Gather 65, 317
Linear 65, 317
Accessing 316
Internal cell storage 60
Receive cell buffer size 220
Segmentation 60
Transmit cell buffer size 220
UTOPIA Configuration register 60
Cell Buffer RAM Address Method
selection 208
Cell delay variati on (CDV) 34
Cell fields 62
Cell formats 62
52-byte 63
56-byte 63
Cell length control 201
Cell Scheduling System 27
Accessing Fast Memory 51
Assigned Cell flag 31
Calculating time slots 34
Cell-scheduling process 30
Channel Des criptor 32, 40
Connect ion ID tabl e 28
CSS Configuration register (R60) 41, 217
Error flag 217
GCRA 35
Initializing R 60 217
POPC instruction 31
Programming 38
PUSHC instru ction 32 , 40
Scheduling a connection 32
Schedul ing Erro r 41
Scoreboard 28
Accessing 316, 318
Initializing 318
Servicing a connection 31
CellMaker-155
description xxi
CellMaker-622
description xxi
Channel Des criptor 32, 40
CIN_BUSY 178, 199–20 0, 359
CircuitMaker
description xxi
Clean Up 117, 119, 127
Code set struct ure 404
Comm In Data Strob e 135
COMM SEL transfer 119, 127
COMMIN/COMMOUT register 178
Commi tted slot 229, 231, 264
Restrictions 233, 26 6
Communication Register I/O transfers 133
Comparing 32-bit numbers 240
Condition code (ES S field) 263
Conditional operato r (C-bit) 265
Configuration information, reading during
reset 181
Connection ID 298
Connection ID table 28
Address bit s 44
Address gener at ion 44
Address in R61 218
Base address 217
Control field (DMA instructio ns) 287
Control signal timing 359
Counter system operations (CSO) 269
COUT_RDY 178, 199–200, 359
CRC acceleration
Using SR M 305
CRC32P R X and CRC32 PRY regist ers (R44-
R47) 207
CRC32X Error Indicator 213
CRC32Y Error Indicator 213
CRCX bit 209, 288
CRCY bit 209, 288
CSO option 269
CSS Configuration register (R60) 217, 280
CSS error flag 217
CSS operation in progress 200
D
Data alignment
DMA operations 107
Data Read 115, 120
Data Wait 1 1 6, 12 1, 124, 128
Data Write 124, 128
MXT3010 Reference Manua l Version 4.1 425
Decoupling
General 392
VAA 391
Device ID field 209
Device initialization 401
Direct Memory Operation - Port1 Read (DMA1R
and DMA1R+) 289
Direct Memory Operation - Port1 Write (DMA1W
and DMA1W+) 290
Direct Memory Operation - Port2 Read (DMA2R
and DMA2R+) 291
Direct Memory Operation - Port2 Write (DMA2W
and DMA2W+) 292
Dispatched instructions 13
DMA instructions 284
Instr uct i on fi eld opt io ns 99
DMA Plus control 202, 285
DMA Plus instruction 107
DMA1 out or queue stage busy 200
DMA1 queue stage busy 200
DMA2 out or queue stage busy 200
DMA2 queue stage busy 200
Downloading firmware 402
E
Early end 202
Electrical parameters 383
ESS field 263
Examples
Add and Subtract 326
And, Or, Exclusive-or 334
Branching 328
Compare, Load Immediate, Max, Min 338
Load and Store Fast Memory 331
Load and Store Internal RAM 332
Shifts 335
External State Signals register (R42) 200
F
Fast Memory
Bus contention avoidance 55
Byte Swap register (R43) 203
Cell Scheduling System access 51
Chip Enable in puts 52
Configurations suppo rt ed 52
Interface operation 364
Loading 48
Memory sizes 52
Mode control 202
Operating modes 52–53
Priority of various accesses 51
Processor access 48
RAM selection 52
Sequence diagrams 56
SHFM instr uction 50
SRH instructio n 50
Storing 50
SWAN processor access 51
Fast Memory Byte Address generation 296
Fast Memory Byte Swap register (R43) 203
Fast Memory Data register (R56) 50, 212
Fast Memory port 47
Fast Memory Shadow register (R58) 215, 270
Fast Memory timing 345
Find First Set instructi on using R43 203
Flags
Overflow Flag 225
G
GA, GB, GC, and GD registers 208, 314
Gather access 65, 317
General Purpose registers
(R32) 193
(R33) 194
(R34) 195
(R35) 196
(R37-R39) 198
Generic Cell Rate Algorithm (GCR A) 35
Glossary 399
H
Hardware registers (reg field) in SRH 307
HEC 62
Control 201
Generation
Use of R32 193, 202
Use of R 33 194
Generation and checking 25
Host Communication registers (R40-R41) 199
HW field 295
426 Versi on 4.1 MXT3010 Re ference Ma nual
HW field limitations when linkin g 295
I
I bit 285
I/O Performance Levels 385
IBI bit 288
ICSI 180, 200, 213, 359
Input enables 221
ICSO 180, 213, 359
Output enables 221
Index field (IDX) 315
Inpu t clo c k det a il s 344
Inpu t pins 180
Instruction Base Address register (R53) 210,
262
Instruction cache 15
Cache organization and mapping 15
Instruction prefetch 17
Observing cached program flow 18
Using the Cache 17
Instruction classes 18
Instruction features 10
Instruction reference examples 325
Instr uc t ion se t summa ry 411
Instructi on spa ce 14, 263
Instructions
Abbreviations used in 188, 190
Add Register and Immediate (ADDI) 235
Add Registers (ADD) 234
And Register and Immediate (ANDI) 237
And Registers (AND) 236
Branch Fast Memory Shadow Register
(BF) 270
Branch Fast Memory Shadow Register and
Link (BFL) 271
Branch Immediate (BI) 272
Branch Immediate and Link (BIL) 273
Branch Register (BR) 274
Branch Register and Link (BRL) 275
Compare Register and Immediate with
Previous (CMPPI ) 241
Compare Two Registers (CMP) 238
Compare Two Registers and Immediate
(CMPI) 239
Compare Two Registers with Previous
(CMPP) 239–240
Find First Set (How to implem ent) 242
Find Last Set (FLS) 242
Load Double Register (LDD) 322
Load Immediate (LIMD) 243
Load Multiple from Fast Memory
(LMFM) 308
Load Register (LD) 321
Maximum of Register and Immediate
(MAXI) 245
Maximum of Two Registers (MAX) 244
Minimum of Register and Immediate
(MINI) 247
Mini mum of Two Registe rs (MI N) 246
OR Register and Immediate (ORI) 249
OR Registers (OR) 248
Schedule - Fast (PUSHF) 281
Schedule (PUSHC) 280
Service Schedule - Fast (POPF) 279
Servi ce Schedu le (P OPC ) 278
Shift Circular Immediate (SFTCI) 254
Shift Left Circular (SFTC) 253
Shift Left Immediate (SFTLI) 255
Shift Right Arithmetic (SFTA) 251
Shift Right Arithmetic Immediate
(SFTAI) 252
Shift Right Imm edia te (S FT RI) 255
Shift Signed Amount (SFT) 250
Store Double Register (STD ) 324
Store Halfword to Fast Memory (SHFM) 311
Store Register (ST) 323
Store Register Halfword (SRH) 312
Subtract Register and Immediate (SUBI) 257
Subtract Registers (SUB) 256
XOR Register and Immediate (XORI) 259
XOR Registers (XOR) 258
Instructions, list of 185
Interchip commu nication 180
J
JTAG and PLL pin termi nat ions 377
JTAG scan 365
L
Last Transfer 117, 119, 121, 1 27, 129
MXT3010 Reference Manua l Version 4.1 427
Least significan t bits (lsbs) field in SRH 307
Linear access 65, 317
Linking option and the Branch Register (R59) 268
LMFM instruction 48–49
#HW f i eld 49
LNK option 49, 294, 299
LNK option, usage example 299
Load and Store Fast Memory instructions 293
Load and Store Internal RAM Instructions 313
Local Address registers (rla) (R48-R51) 208
Logical state identifier (S-bit) 264
M
Maximum Burst Size 35
Maximum ratings 384
Mechanical and thermal information 395
Memory alignment requirements for LMFM and
LNK 303
Memory update, automatic 228
Mode Configuration register (R42) 201, 285, 408
Modulo arithmetic 226, 326
MXT3010
description xxi
MXT3020
description xxi
N
N bit 265
NC bit 16 , 210
Nullify operator (N-bit) 265
O
Operating cond itions 384
Output pins 180, 403
Overflow flag 225, 234–235
P
P1ABORT_ signal 163
Pacing the transmission rate of cells 37
Back pressure 37
External clock 37
Package 396
Peak Cell Rate 35
Pin diagram 397
Pin information 367
Pin lis tings 378
Pin types 381
Pinout 368
PIT0
Control 202
Time out indication 213
Timer operation 211
Use of R54 211
PIT1
Control 202
Time out indication 213
Timer operation 211
Use of R55 211
PLL considerations 390
POD bit 288
PODs 109
POPC instruction
Timing 42
POPF instr uction
Timing 42
Port interface
Command queues 100
Active stage 101
Queue stage 101
Testing status 101
DMA command format 98
Instruction field options 99
Overview 98
Port1 DMA Controller
Basic protocol 110
Byte mani pulations 108
Contro l si gnals 111
CRC32 generator 103
Acceleration 104
Address holding registers 105
Byte bo undar ie s 108
Pipelined operations 104
Silent tr ansfers 105
Mapping rsa and rsb to address bits 110
PODs 109
Sequence diagrams
Comm I/O transfers 133
State tables
Comm I/O transfers 133
Port1 Operation Control 202
428 Versi on 4.1 MXT3010 Re ference Ma nual
Port1 timing 352
Port2 DMA Controller
Address index 141
Basic protocol 137
Burst and non-burst operation 109
Control signals 141
Mapping rsa and rsb to address bits
(burst) 137
Mapping rsa and rsb to address bits (non-
burst) 139
Sequence diagrams
Non-burst read t ransfer 144, 151, 155
Write transfers 147
State tables
Read transfers 142, 146, 150, 154
Port2 Operation 202
Port2 timing 356
Post-DMA Operation Directives (PODs) 109
Post-increment option on rla operations 107
Power sequencing 386
Program Counter 11
Programmable Interval Timer registers (R54-
R55) 211
PUSHC instru ction 40
Scheduled Address register 218
Timing 42
PUSHC/POPC instruction buffer 42
PUSHF instru ction
Timing 42
Q
Quick reference 411
R
R54 contro l 202
R55 contro l 202
RD register choices for LMFM 299–300
Receive Cell Buffer Size 220
Receive Cell Status word 63, 78
Receive header reduction 91
Reference clock jitter 393
Registers
Access rules 22
Alternate Byte Count/ID register (R52) 209
Assigned Cell flag register 24
Bit Bucket register (R36) 197
Branch register (R59) 216
CRC32P R X and CRC32 PRY regist ers (R44-
R47) 207
CSS Configuration register (R60) 217
External State Signals register (R42) 200
Fast Memory Byte Swap Register (R43) 203
Fast Memory Data register (R56) 212
Fast Memory Shadow register (R58) 215
Flag registers 24
GA, GB, GC, GD 314
General purpose (R32) 193
General purpose (R33) 194
General purpose (R34) 195
General purpose (R35) 196
General purpose (R37-R3 9) 198
Host Communication registers (R40-
R41) 199
Initializing 191
Inst ruction Base Ad dress registe r (R53) 210
Lis t of 184, 191
Local Address registers (rla) (R48-R51) 208
Mode Configuration register (R42) 201
Overflow flag register 24
Pipeline feedback 21
Programmable Interval Timer registers (R54-
R55) 211
Register types 21
Scheduled Address register (R61) 218
Sparse Event/ICS register (R57) 213
Specifying in SWAN instructions 190
System register (R63) 221
Types 189
UTOPIA Configuration register (R62) 219
UTOPIA Control FIFO register (R43) 205
Reset 402
Reset timing 360
Restrictions
Access to rla register 285, 315
Accessing destination of PO PC 278
Choice of destination for POPC 278
CIN_BSY and COUT_RDY 179
Commi tted slot 233
LMFM instruct ion timing 309
Port1 Addressing 111
MXT3010 Reference Manua l Version 4.1 429
RLA Increment bit (i-bit) 285
RLA increment option 107
RLA registe r
Choices for rla register 208, 314
RXBUSY count er 79, 200
RXFULL
Counter 81
Decrementing 109
State indicator 213
S
S bit 264
SAR PDU 62
Scheduled Address register (R61) 33, 218
Scoreboard 28
Address bits 44
Addr ess generation 44
Initialization 45
Section size selection 217
Sections 46
Size 45
Scoreboard/Cell Buffer selection 208
Segment ID 262
Segment ID bits 210
Sequence diagrams
CIN_BUSY and COUT_RDY 179
Comm I/O transfer 133
Fast Memory 56
Port2 14 4, 147, 151, 155
UTOPIA Port 94
SHFM instruction 50
SHFM inst ruction, us e of R56 212
Signal descript ions 369
Clock, control, and test signals 375
Fast Memory controller 373
Inter-chi p and commu nicat i on regi s ter 374
Port1 370
Port2 371
Power and ground pins 376
UTOPIA Port 372
Signed arithmetic 225
Silent transfers 105, 288
Sparse Event register bit OR 200
Sparse Event register enables 221
Sparse Event/ICS register (R57) 18 0, 213
SPICE models 381
SRH instructio n 50
ST bit 288
ST option 105
Stalls
Load Double Register 322
Load Register 321
Store Double Register 324
Store Register 323
With LMFM instruction 309
With SHFM instruction 311
Subrout i ne linking 268
Sustained Cell Rate 35
SWAN instruction set 185
Swap field 319
System r e gister (R63) 91, 221
T
Target address
Branch instructions 262
Cell sche duling 277
Load and Store Internal RAM 315
Target field 263
Timing 343
Contro l si gnals 359
Definition of switching levels 343
Fast Memory interface 345
Port1 352
Port2 356
Reset 360
UTOPIA interface 348
Timing restrictions
LMFM instruction 309
Transfer complete
Byte count zero
Early end 162
Standard end 161
External abort (P1ABORT_) 163
Transmit Cell Buffer Size 220
TXBUSY
Incrementing 109, 2 06
State indicator 213
TXFULL Counter 200
430 Versi on 4.1 MXT3010 Re ference Ma nual
U
UM address generation 301
UM option 49, 228, 294
UM option, usage example 301
Unconditional branch 200
Unspecified Bit Rate (UBR) 35
User Header 62
UTOPIA Configuration re gister (R62) 60, 71,
88, 92–93, 2 19
UTOPIA Control FIFO register (R43) 205
UTOPI A port 69
Cell formats 74
Clock frequency selection 220
Clock phases 73
Configur ation information sum mary 93
Control FIFO register 83
CRC10 generation and checking 87
Data bus width select ion 219
Generating and inserting CRC 10 205
Inserting an unassigned cell 205
Level 1 and 2 configurations 90
Level 2 config urations 89
Most significant PHY address selection 219
Multi-PHY support 88
Number of PHYs selection 219
Operating modes
16-bit 71
8-bit 71
Overview 70
Post-DMA operative directive (POD) 82
Receive cell flow 77
Receive Cell Status word 78
Receiver counters (RXBUSY, RXFULL) 78
Receiver Enable (RXENB_) 82
Receiver reduction mask 222
Resetting 71
Selecti ng addres s of target PHY 205
Selecting cell length 72
Selecting HEC operation 72
Selecting operating speed 72
Selecting transmit/receive m odes 72
Sequence diagrams 94
Transmit cell flow 82
Transmit Enable (TXENB_) 84
Transmitter counters (TXBUSY,
TXFULL) 84
TXBU SY counter 84
TXFULL counter 86
UTOPIA Port Post Operative Directive
(POD) 288
UTOPIA Receiver Reduction Mode Enable
Bit 220
V
Va riable Bit Rate (VBR 35
VPI/VCI 222
Z
Z-bit 296
