STM32F427xx STM32F429xx 32b Arm(R) Cortex(R)-M4 MCU+FPU, 225DMIPS, up to 2MB Flash/256+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 com. interfaces, camera & LCD-TFT Datasheet - production data Features * Core: Arm(R) 32-bit Cortex(R)-M4 CPU with FPU, Adaptive real-time accelerator (ART AcceleratorTM) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions * Memories - Up to 2 MB of Flash memory organized into two banks allowing read-while-write - Up to 256+4 KB of SRAM including 64-KB of CCM (core coupled memory) data RAM - Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, Compact Flash/NOR/NAND memories * LCD parallel interface, 8080/6800 modes * LCD-TFT controller with fully programmable resolution (total width up to 4096 pixels, total height up to 2048 lines and pixel clock up to 83 MHz) * Chrom-ART AcceleratorTM for enhanced graphic content creation (DMA2D) * Clock, reset and supply management - 1.7 V to 3.6 V application supply and I/Os - POR, PDR, PVD and BOR - 4-to-26 MHz crystal oscillator - Internal 16 MHz factory-trimmed RC (1% accuracy) - 32 kHz oscillator for RTC with calibration - Internal 32 kHz RC with calibration * Low power - Sleep, Stop and Standby modes - VBAT supply for RTC, 20x32 bit backup registers + optional 4 KB backup SRAM * 3x12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode * 2x12-bit D/A converters * General-purpose DMA: 16-stream DMA controller with FIFOs and burst support * Up to 17 timers: up to twelve 16-bit and two 32bit timers up to 180 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input January 2018 This is information on a product in full production. &"'! LQFP100 (14 x 14 mm) UFBGA176 (10 x 10 mm) LQFP144 (20 x 20 mm) UFBGA169 (7 x 7 mm) LQFP176 (24 x 24 mm) TFBGA216 (13 x 13 mm) LQFP208 (28 x 28 mm) WLCSP143 * Debug mode - SWD & JTAG interfaces - Cortex-M4 Trace MacrocellTM * Up to 168 I/O ports with interrupt capability - Up to 164 fast I/Os up to 90 MHz - Up to 166 5 V-tolerant I/Os * Up to 21 communication interfaces - Up to 3 x I2C interfaces (SMBus/PMBus) - Up to 4 USARTs/4 UARTs (11.25 Mbit/s, ISO7816 interface, LIN, IrDA, modem control) - Up to 6 SPIs (45 Mbits/s), 2 with muxed full-duplex I2S for audio class accuracy via internal audio PLL or external clock - 1 x SAI (serial audio interface) - 2 x CAN (2.0B Active) and SDIO interface * Advanced connectivity - USB 2.0 full-speed device/host/OTG controller with on-chip PHY - USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI - 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII * 8- to 14-bit parallel camera interface up to 54 Mbytes/s * True random number generator * CRC calculation unit * RTC: subsecond accuracy, hardware calendar * 96-bit unique ID DocID024030 Rev 10 1/239 www.st.com STM32F427xx STM32F429xx Table 1. Device summary Reference Part number STM32F427xx STM32F427VG, STM32F427ZG, STM32F427IG, STM32F427AG, STM32F427VI, STM32F427ZI, STM32F427II, STM32F427AI STM32F429VG, STM32F429ZG, STM32F429IG, STM32F429BG, STM32F429NG, STM32F429AG, STM32F429VI, STM32F429ZI, STM32F429II,, STM32F429BI, STM32F429xx STM32F429NI,STM32F429AI, STM32F429VE, STM32F429ZE, STM32F429IE, STM32F429BE, STM32F429NE 2/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 3 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 Arm(R) Cortex(R)-M4 with FPU and embedded Flash and SRAM . . . . . . . . 21 3.2 Adaptive real-time memory accelerator (ART AcceleratorTM) . . . . . . . . . 21 3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 22 3.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.9 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10 LCD-TFT controller (available only on STM32F429xx) . . . . . . . . . . . . . . 24 3.11 Chrom-ART AcceleratorTM (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 25 3.13 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.14 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.15 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.16 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.17 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.18 3.17.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.17.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.18.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.18.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.18.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 32 3.19 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 32 3.20 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.21 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DocID024030 Rev 10 3/239 6 Contents STM32F427xx STM32F429xx 3.22 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.22.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.22.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.22.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.23 Inter-integrated circuit interface ( I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.24 Universal synchronous/asynchronous receiver transmitters (USART) . . 37 3.25 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.26 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.27 Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.28 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.29 Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.30 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 40 3.31 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 40 3.32 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.33 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 41 3.34 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 41 3.35 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.36 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.37 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.38 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.39 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.40 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.41 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.42 Embedded Trace MacrocellTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.1 4/239 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 DocID024030 Rev 10 STM32F427xx STM32F429xx Contents 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 98 6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 98 6.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 99 6.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 127 6.3.13 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.3.15 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 133 6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.3.19 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.3.20 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.3.21 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 6.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6.3.24 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6.3.25 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 6.3.26 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.3.27 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 193 6.3.28 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 194 6.3.29 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 196 DocID024030 Rev 10 5/239 6 Contents STM32F427xx STM32F429xx 6.3.30 7 8 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 7.2 WLCSP143 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 7.3 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 7.4 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 7.5 LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 7.6 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 7.7 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 7.8 TFBGA216 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 7.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 227 A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 9 6/239 B.1 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 228 B.2 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 230 B.3 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 DocID024030 Rev 10 STM32F427xx STM32F429xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32F427xx and STM32F429xx features and peripheral counts . . . . . . . . . . . . . . . . . . 16 Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 29 Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 32 Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 STM32F427xx and STM32F429xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . 53 FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 STM32F427xx and STM32F429xx alternate function mapping . . . . . . . . . . . . . . . . . . . . . 75 STM32F427xx and STM32F429xx register boundary addresses. . . . . . . . . . . . . . . . . . . . 87 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 97 VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 98 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 98 reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled except prefetch) or RAM . . . . . . 102 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . 103 Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . 104 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 105 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 106 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 106 Typical current consumption in Run mode, code with data processing running from Flash memory or RAM, regulator ON (ART accelerator enabled except prefetch), VDD=1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Typical current consumption in Run mode, code with data processing running from Flash memory, regulator OFF (ART accelerator enabled except prefetch). . . . . . . 109 Typical current consumption in Sleep mode, regulator ON, VDD=1.7 V . . . . . . . . . . . . . 110 Tyical current consumption in Sleep mode, regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . 111 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 DocID024030 Rev 10 7/239 9 List of tables Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. 8/239 STM32F427xx STM32F429xx PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 PLLISAI (audio and LCD-TFT PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 154 Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 155 Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 156 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 159 ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 159 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Asynchronous non-multiplexed SRAM/PSRAM/NOR read NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 171 Asynchronous non-multiplexed SRAM/PSRAM/NOR write NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 173 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 174 DocID024030 Rev 10 STM32F427xx STM32F429xx Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. List of tables Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 175 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 179 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Switching characteristics for PC Card/CF read and write cycles in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 189 SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 LQPF100 100-pin, 14 x 14 mm low-profile quad flat package mechanical data. . . . . . . . 199 WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 WLCSP143 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 204 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 UFBGA169 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 218 UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 220 UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 221 TFBGA216 - 216 ball 13 x 13 mm 0.8 mm pitch thin fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 227 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 DocID024030 Rev 10 9/239 9 List of figures STM32F427xx STM32F429xx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. 10/239 Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and UFBGA176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 STM32F427xx and STM32F429xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STM32F427xx and STM32F429xx Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 27 PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 31 Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 31 STM32F42x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 STM32F42x WLCSP143 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 STM32F42x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 STM32F42x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 STM32F42x LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 STM32F42x UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 STM32F42x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 STM32F42x TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . 107 Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . 107 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 ACCHSI accuracy versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 DocID024030 Rev 10 STM32F427xx STM32F429xx Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. List of figures SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 151 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 162 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 163 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 169 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 171 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 172 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 174 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 179 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 182 PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 182 PC Card/CompactFlash controller waveforms for attribute memory read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 PC Card/CompactFlash controller waveforms for attribute memory write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 184 PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 185 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 188 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 188 SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 LQFP100 -100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . 198 LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 WLCSP143 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 LQFP144-144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . . 205 LQPF144- 144-pin,20 x 20 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package outline . . . . . . . . . . . . . . 209 DocID024030 Rev 10 11/239 12 List of figures Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. Figure 108. Figure 109. 12/239 STM32F427xx STM32F429xx LQFP176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint. . . . . . . . . 211 LQFP176 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline . . . . . . . . . . . . . . 213 LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 UFBGA169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 UFBGA176+25 - ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 UFBGA176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 TFBGA216 - 216 ball 13 x 13 mm 0.8 mm pitch thin fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 TFBGA176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 228 USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 229 USB controller configured as peripheral, host, or dual-mode and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 DocID024030 Rev 10 STM32F427xx STM32F429xx 1 Introduction Introduction This datasheet provides the description of the STM32F427xx and STM32F429xx line of microcontrollers. For more details on the whole STMicroelectronics STM32 family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F427xx and STM32F429xx datasheet should be read in conjunction with the STM32F4xx reference manual. For information on the Cortex(R)-M4 core, please refer to the Cortex(R)-M4 programming manual (PM0214), available from www.st.com. DocID024030 Rev 10 13/239 44 Description 2 STM32F427xx STM32F429xx Description The STM32F427xx and STM32F429xx devices are based on the high-performance Arm(R) Cortex(R)-M4 32-bit RISC core operating at a frequency of up to 180 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all Arm(R) singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The STM32F427xx and STM32F429xx devices incorporate high-speed embedded memories (Flash memory up to 2 Mbyte, up to 256 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. They also feature standard and advanced communication interfaces. * Up to three I2Cs * Six SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. * Four USARTs plus four UARTs * An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI), * Two CANs * One SAI serial audio interface * An SDIO/MMC interface * Ethernet and camera interface * LCD-TFT display controller * Chrom-ART AcceleratorTM. Advanced peripherals include an SDIO, a flexible memory control (FMC) interface, a camera interface for CMOS sensors. Refer to Table 2: STM32F427xx and STM32F429xx features and peripheral counts for the list of peripherals available on each part number. The STM32F427xx and STM32F429xx devices operates in the -40 to +105 C temperature range from a 1.7 to 3.6 V power supply. The supply voltage can drop to 1.7 V with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F427xx and STM32F429xx devices offer devices in 8 packages ranging from 100 pins to 216 pins. The set of included peripherals changes with the device chosen. 14/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Description These features make the STM32F427xx and STM32F429xx microcontrollers suitable for a wide range of applications: * Motor drive and application control * Medical equipment * Industrial applications: PLC, inverters, circuit breakers * Printers, and scanners * Alarm systems, video intercom, and HVAC * Home audio appliances Figure 4 shows the general block diagram of the device family. DocID024030 Rev 10 15/239 44 STM32F427 Vx Peripherals Flash memory in Kbytes SRAM in Kbytes 1024 2048 STM32F429Vx 512 1024 2048 STM32F427 Zx 1024 2048 STM32F429Zx STM32F427 STM32F429 STM32F427 Ax Ax Ix 512 1024 2048 1024 2048 System 2048 1024 2048 512 1024 2048 STM32F429Bx STM32F429Nx 512 1024 2048 512 1024 2048 256(112+16+64+64) Backup 4 Yes(1) FMC memory controller Ethernet Timers 1024 STM32F429Ix Description 16/239 Table 2. STM32F427xx and STM32F429xx features and peripheral counts Yes Generalpurpose 10 Advanced -control 2 Basic 2 DocID024030 Rev 10 Random number generator 2 SPI / I S Yes 4/2 (full duplex) (2) 6/2 (full duplex)(2) I2C 3 USART/ UART 4/4 USB OTG Communication FS interfaces USB OTG HS Yes Yes 2 SAI 1 SDIO Yes Camera interface LCD-TFT (STM32F429xx only) Yes No Yes No Yes Chrom-ART AcceleratorTM GPIOs 12-bit ADC Number of channels No Yes No Yes Yes 82 114 130 140 3 16 24 168 STM32F427xx STM32F429xx CAN Peripherals STM32F427 Vx STM32F429Vx STM32F427 Zx STM32F429Zx 12-bit DAC Number of channels STM32F429Ix STM32F429Bx STM32F429Nx LQFP208 TFBGA216 Yes 2 Maximum CPU frequency 180 MHz 1.8 to 3.6 V(3) Operating voltage Ambient temperatures: -40 to +85 C /-40 to +105 C Operating temperatures Packages STM32F427 STM32F429 STM32F427 Ax Ax Ix Junction temperature: -40 to + 125 C LQFP100 WLCSP143 LQFP144 UFBGA169 UFBGA176 LQFP176 DocID024030 Rev 10 1. For the LQFP100 package, only FMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. For UFBGA169 package, only SDRAM, NAND and multiplexed static memories are supported. 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). STM32F427xx STM32F429xx Table 2. STM32F427xx and STM32F429xx features and peripheral counts (continued) Description 17/239 Description 2.1 STM32F427xx STM32F429xx Full compatibility throughout the family The STM32F427xx and STM32F429xx devices are part of the STM32F4 family. They are fully pin-to-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle. The STM32F427xx and STM32F429xx devices maintain a close compatibility with the whole STM32F10xx family. All functional pins are pin-to-pin compatible. The STM32F427xx and STM32F429xx, however, are not drop-in replacements for the STM32F10xx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xx to the STM32F42x family remains simple as only a few pins are impacted. Figure 1, Figure 2, and Figure 3, give compatible board designs between the STM32F4xx, STM32F2xx, and STM32F10xx families. Figure 1. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package 966 966 966 966 UHVLVWRURUVROGHULQJEULGJH SUHVHQWIRUWKH670)[[[ FRQILJXUDWLRQQRWSUHVHQWLQWKH 670)[[FRQILJXUDWLRQ 966 966 966IRU670)[[ 7ZRUHVLVWRUVFRQQHFWHGWR 9''IRU670)[[ 9'' 966 966IRUWKH670)[[ 966IRUWKH670)[[ 966RU1&IRUWKH670)[[ DLG 18/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Description Figure 2. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package 966 UHVLVWRURUVROGHULQJEULGJH SUHVHQWIRUWKH670)[[ FRQILJXUDWLRQQRWSUHVHQWLQWKH 670)[[FRQILJXUDWLRQ 966 966 6LJQDOIURP H[WHUQDOSRZHU VXSSO\ VXSHUYLVRU 1RWSRSXODWHGZKHQ UHVLVWRURUVROGHULQJ EULGJHSUHVHQW 3'5B21 966 9'' 966 1RWSRSXODWHGIRU670)[[ 7ZRUHVLVWRUVFRQQHFWHGWR 966IRU670)[[ 966IRUWKH670)[[ 9'' 966 9''IRU670)[[ 9669''RU1&IRUWKH670)[[ 9''RUVLJQDOIURPH[WHUQDOSRZHUVXSSO\VXSHUYLVRUIRUWKH670)[[ DLG Figure 3. Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and UFBGA176 packages *1'IRU670)[[ %<3$66B5(*IRU670)[[ 6LJQDOIURPH[WHUQDO SRZHUVXSSO\ VXSHUYLVRU 3'5B21 9'' 966 7ZRUHVLVWRUVFRQQHFWHGWR 9669''RU1&IRUWKH670)[[ 9''RUVLJQDOIURPH[WHUQDOSRZHUVXSSO\VXSHUYLVRUIRUWKH670)[[ 069 DocID024030 Rev 10 19/239 44 Description STM32F427xx STM32F429xx Figure 4. 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The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 2. The LCD-TFT is available only on STM32F429xx devices. 20/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Functional overview 3 Functional overview 3.1 Arm(R) Cortex(R)-M4 with FPU and embedded Flash and SRAM The Arm(R) Cortex(R)-M4 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm(R) Cortex(R)-M4 with FPU core is a 32-bit RISC processor that features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. The STM32F42x family is compatible with all Arm tools and software. Figure 4 shows the general block diagram of the STM32F42x family. Note: Cortex-M4 with FPU core is binary compatible with the Cortex-M3 core. 3.2 Adaptive real-time memory accelerator (ART AcceleratorTM) The ART AcceleratorTM is a memory accelerator which is optimized for STM32 industrystandard Arm(R) Cortex(R)-M4 with FPU processors. It balances the inherent performance advantage of the Arm(R) Cortex(R)-M4 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor full 225 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 180 MHz. 3.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. DocID024030 Rev 10 21/239 44 Functional overview 3.4 STM32F427xx STM32F429xx Embedded Flash memory The devices embed a Flash memory of up to 2 Mbytes available for storing programs and data. 3.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 3.6 Embedded SRAM All devices embed: * Up to 256Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory) data RAM RAM memory is accessed (read/write) at CPU clock speed with 0 wait states. * 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 3.7 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. 22/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Functional overview Figure 5. STM32F427xx and STM32F429xx Multi-AHB matrix &KURP$57$FFHOHUDWRU '0$' ,&2'( '&2'( $&&(/ '0$' /&'7)7B0 86%B+6B0 0$& 86%27* /&'7)7 (WKHUQHW +6 (7+(51(7B0 '0$B3 *3 '0$ '0$B0(0 '0$B0(0 *3 '0$ '0$B3, 6EXV 'EXV $50 &RUWH[0 ,EXV .E\WH &&0GDWD5$0 )ODVK PHPRU\ 65$0 .E\WH 65$0 .E\WH 65$0 .E\WH $+% SHULSKHUDOV $3% $+% SHULSKHUDOV )0&H[WHUQDO 0HP&WO $3% %XVPDWUL[6 -36 3.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. DocID024030 Rev 10 23/239 44 Functional overview STM32F427xx STM32F429xx The DMA can be used with the main peripherals: 3.9 * SPI and I2S * I2C * USART * General-purpose, basic and advanced-control timers TIMx * DAC * SDIO * Camera interface (DCMI) * ADC * SAI1. Flexible memory controller (FMC) All devices embed an FMC. It has four Chip Select outputs supporting the following modes: PCCard/Compact Flash, SDRAM/LPSDR SDRAM, SRAM, PSRAM, NOR Flash and NAND Flash. Functionality overview: * 8-,16-, 32-bit data bus width * Read FIFO for SDRAM controller * Write FIFO * Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is 90 MHz. LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.10 LCD-TFT controller (available only on STM32F429xx) The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following features: 24/239 * 2 displays layers with dedicated FIFO (64x32-bit) * Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer * Up to 8 Input color formats selectable per layer * Flexible blending between two layers using alpha value (per pixel or constant) * Flexible programmable parameters for each layer * Color keying (transparency color) * Up to 4 programmable interrupt events. DocID024030 Rev 10 STM32F427xx STM32F429xx 3.11 Functional overview Chrom-ART AcceleratorTM (DMA2D) The Chrom-Art AcceleratorTM (DMA2D) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conversion. It supports the following functions: * Rectangle filling with a fixed color * Rectangle copy * Rectangle copy with pixel format conversion * Rectangle composition with blending and pixel format conversion. Various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds dedicated memory to store color lookup tables. An interrupt can be generated when an operation is complete or at a programmed watermark. All the operations are fully automatized and are running independently from the CPU or the DMAs. 3.12 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 91 maskable interrupt channels plus the 16 interrupt lines of the Cortex(R)M4 with FPU core. * Closely coupled NVIC gives low-latency interrupt processing * Interrupt entry vector table address passed directly to the core * Allows early processing of interrupts * Processing of late arriving, higher-priority interrupts * Support tail chaining * Processor state automatically saved * Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 3.13 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 168 GPIOs can be connected to the 16 external interrupt lines. 3.14 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is DocID024030 Rev 10 25/239 44 Functional overview STM32F427xx STM32F429xx detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the two AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 180 MHz while the maximum frequency of the high-speed APB domains is 90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz. The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 3.15 Boot modes At startup, boot pins are used to select one out of three boot options: * Boot from user Flash * Boot from system memory * Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial interface. Refer to application note AN2606 for details. 3.16 Power supply schemes * VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. * VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. * VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Note: VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode versus device operating mode to identify the packages supporting this option. 3.17 Power supply supervisor 3.17.1 Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other package, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is 26/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Functional overview reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.17.2 Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin. An external power supply supervisor should monitor VDD and should maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to this external power supply supervisor. Refer to Figure 6: Power supply supervisor interconnection with internal reset OFF. Figure 6. Power supply supervisor interconnection with internal reset OFF 9'' ([WHUQDO9''SRZHUVXSSO\VXSHUYLVRU ([WUHVHWFRQWUROOHUDFWLYHZKHQ 9''9 3'5B21 1567 $SSOLFDWLRQUHVHW VLJQDO RSWLRQDO 9'' 069 The VDD specified threshold, below which the device must be maintained under reset, is 1.7 V (see Figure 7). A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no more supported: * The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled * The brownout reset (BOR) circuitry must be disabled * The embedded programmable voltage detector (PVD) is disabled * VBAT functionality is no more available and VBAT pin should be connected to VDD. All packages, except for the LQFP100, allow to disable the internal reset through the PDR_ON signal. DocID024030 Rev 10 27/239 44 Functional overview STM32F427xx STM32F429xx Figure 7. PDR_ON control with internal reset OFF 9 '' 3'5 9 WLPH 5HVHWE\RWKHUVRXUFHWKDQ SRZHUVXSSO\VXSHUYLVRU 1567 3'5B21 3'5B21 WLPH 069 3.18 Voltage regulator The regulator has four operating modes: * * 3.18.1 Regulator ON - Main regulator mode (MR) - Low power regulator (LPR) - Power-down Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled. There are three power modes configured by software when the regulator is ON: * MR mode used in Run/sleep modes or in Stop modes - In Run/Sleep mode The MR mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). Different voltages scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. 28/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Functional overview The over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling. - In Stop modes The MR can be configured in two ways during stop mode: MR operates in normal mode (default mode of MR in stop mode) MR operates in under-drive mode (reduced leakage mode). * LPR is used in the Stop modes: The LP regulator mode is configured by software when entering Stop mode. Like the MR mode, the LPR can be configured in two ways during stop mode: * - LPR operates in normal mode (default mode when LPR is ON) - LPR operates in under-drive mode (reduced leakage mode). Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost. Refer to Table 3 for a summary of voltage regulator modes versus device operating modes. Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin. Refer to Figure 22: Power supply scheme and Table 19: VCAP1/VCAP2 operating conditions. All packages have the regulator ON feature. Table 3. Voltage regulator configuration mode versus device operating mode(1) Voltage regulator configuration Run mode Sleep mode Stop mode Standby mode Normal mode MR MR MR or LPR - Over-drive mode(2) MR MR - - Under-drive mode - - MR or LPR - Power-down mode - - - Yes 1. `-' means that the corresponding configuration is not available. 2. The over-drive mode is not available when VDD = 1.7 to 2.1 V. 3.18.2 Regulator OFF This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency. Refer to Table 17: General operating conditions.The two 2.2 F ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer to Figure 22: Power supply scheme. When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. DocID024030 Rev 10 29/239 44 Functional overview STM32F427xx STM32F429xx In regulator OFF mode, the following features are no more supported: * PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. * As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required. * The over-drive and under-drive modes are not available. * The Standby mode is not available. Figure 8. Regulator OFF 9 ([WHUQDO9&$3BSRZHU $SSOLFDWLRQUHVHW VXSSO\VXSHUYLVRU ([WUHVHWFRQWUROOHUDFWLYH VLJQDO RSWLRQDO ZKHQ9&$3B0LQ9 9'' 3$ 9'' 1567 %<3$66B5(* 9 9&$3B 9&$3B DL9 The following conditions must be respected: Note: 30/239 * VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. * If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 9). * Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see Figure 10). * If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a reset must be asserted on PA0 pin. The minimum value of V12 depends on the maximum frequency targeted in the application (see Table 17: General operating conditions). DocID024030 Rev 10 STM32F427xx STM32F429xx Functional overview Figure 9. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization 9'' 3'5 9RU9 9 0LQ9 9&$3B9&$3B WLPH 1567 WLPH DLI 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 10. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization 9'' 3'5 9RU9 9&$3B9&$3B 9 0LQ9 1567 WLPH 3$DVVHUWHGH[WHUQDOO\ WLPH DLH 1. This figure is valid whatever the internal reset mode (ON or OFF). DocID024030 Rev 10 31/239 44 Functional overview 3.18.3 STM32F427xx STM32F429xx Regulator ON/OFF and internal reset ON/OFF availability Table 4. Regulator ON/OFF and internal reset ON/OFF availability Package Regulator ON Regulator OFF LQFP100 Yes LQFP144, LQFP208 WLCSP143, LQFP176, UFBGA169, UFBGA176, TFBGA216 3.19 Internal reset ON Internal reset OFF Yes No Yes PDR_ON set to VDD Yes PDR_ON connected to an external power supply supervisor No Yes Yes BYPASS_REG set BYPASS_REG set to VDD to VSS Real-time clock (RTC), backup SRAM and backup registers The backup domain includes: * The real-time clock (RTC) * 4 Kbytes of backup SRAM * 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 s to every 36 hours. A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in VBAT and standby mode. This memory area is disabled by default to minimize power consumption (see Section 3.20: Low-power modes). It can be enabled by software. The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 3.20: Low-power modes). 32/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Functional overview Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin. 3.20 Low-power modes The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: * Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. * Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can be put either in main regulator mode (MR) or in low-power mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator modes in stop mode): - Normal mode (default mode when MR or LPR is enabled) - Under-drive mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup). Table 5. Voltage regulator modes in stop mode * Voltage regulator configuration Main regulator (MR) Low-power regulator (LPR) Normal mode MR ON LPR ON Under-drive mode MR in under-drive mode LPR in under-drive mode Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. The standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power. DocID024030 Rev 10 33/239 44 Functional overview 3.21 STM32F427xx STM32F429xx VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When PDR_ON pin is not connected to VDD (Internal Reset OFF), the VBAT functionality is no more available and VBAT pin should be connected to VDD. 3.22 Timers and watchdogs The devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 6 compares the features of the advanced-control, general-purpose and basic timers. 34/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Functional overview Table 6. Timer feature comparison Timer type Max Max DMA Capture/ timer Counter Counter Prescaler Complementary interface Timer request compare clock resolution type factor output clock generation channels (MHz) (MHz) (1) Advanced TIM1, -control TIM8 TIM2, TIM5 TIM3, TIM4 TIM9 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 Yes 90 180 32-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 45 90/180 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 45 90/180 16-bit Up Any integer between 1 and 65536 No 2 No 90 180 Up Any integer between 1 and 65536 No 1 No 90 180 Up Any integer between 1 and 65536 No 2 No 45 90/180 Up Any integer between 1 and 65536 No 1 No 45 90/180 Up Any integer between 1 and 65536 Yes 0 No 45 90/180 General purpose TIM10 , TIM11 TIM12 TIM13 , TIM14 Basic TIM6, TIM7 16-bit 16-bit 16-bit 16-bit 1. The maximum timer clock is either 90 or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. DocID024030 Rev 10 35/239 44 Functional overview 3.22.1 STM32F427xx STM32F429xx Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: * Input capture * Output compare * PWM generation (edge- or center-aligned modes) * One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. 3.22.2 General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F42x devices (see Table 6 for differences). * TIM2, TIM3, TIM4, TIM5 The STM32F42x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. * TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. 3.22.3 Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. 36/239 DocID024030 Rev 10 STM32F427xx STM32F429xx 3.22.4 Functional overview Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. 3.22.5 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.22.6 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 3.23 * A 24-bit downcounter * Autoreload capability * Maskable system interrupt generation when the counter reaches 0 * Programmable clock source. Inter-integrated circuit interface ( I2C) Up to three IC bus interfaces can operate in multimaster and slave modes. They can support the standard (up to 100 KHz), and fast (up to 400 KHz) modes. They support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. The devices also include programmable analog and digital noise filters (see Table 7). Table 7. Comparison of I2C analog and digital filters Analog filter Pulse width of suppressed spikes 3.24 50 ns Digital filter Programmable length from 1 to 15 I2C peripheral clocks Universal synchronous/asynchronous receiver transmitters (USART) The devices embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and four universal asynchronous receiver transmitters (UART4, UART5, UART7, and UART8). These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to DocID024030 Rev 10 37/239 44 Functional overview STM32F427xx STM32F429xx communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate at up to 5.62 bit/s. USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller. Table 8. USART feature comparison(1) USART name Standard Modem SPI LIN irDA features (RTS/CTS) master Smartcard (ISO 7816) Max. baud Max. baud rate in Mbit/s rate in Mbit/s (oversampling (oversampling by 16) by 8) APB mapping USART1 X X X X X X 5.62 11.25 APB2 (max. 90 MHz) USART2 X X X X X X 2.81 5.62 APB1 (max. 45 MHz) USART3 X X X X X X 2.81 5.62 APB1 (max. 45 MHz) UART4 X - X - X - 2.81 5.62 APB1 (max. 45 MHz) UART5 X - X - X - 2.81 5.62 APB1 (max. 45 MHz) USART6 X X X X X X 5.62 11.25 APB2 (max. 90 MHz) UART7 X - X - X - 2.81 5.62 APB1 (max. 45 MHz) UART8 X - X - X - 2.81 5.62 APB1 (max. 45 MHz) 1. X = feature supported. 3.25 Serial peripheral interface (SPI) The devices feature up to six SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 45 Mbits/s, SPI2 and SPI3 can communicate at up to 22.5 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode. 38/239 DocID024030 Rev 10 STM32F427xx STM32F429xx 3.26 Functional overview Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be operated in master or slave mode, in full duplex and simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx can be served by the DMA controller. Note: For I2S2 full-duplex mode, I2S2_CK and I2S2_WS signals can be used only on GPIO Port B and GPIO Port D. 3.27 Serial Audio interface (SAI1) The serial audio interface (SAI1) is based on two independent audio sub-blocks which can operate as transmitter or receiver with their FIFO. Many audio protocols are supported by each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC'97 and SPDIF output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub-blocks can be configured in master or in slave mode. In master mode, the master clock can be output to the external DAC/CODEC at 256 times of the sampling frequency. The two sub-blocks can be configured in synchronous mode when full-duplex mode is required. SAI1 can be served by the DMA controller. 3.28 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S/SAI flow with an external PLL (or Codec output). 3.29 Audio and LCD PLL(PLLSAI) An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or 11.2896 MHz) and the audio application requires both sampling frequencies simultaneously. The PLLSAI is also used to generate the LCD-TFT clock. DocID024030 Rev 10 39/239 44 Functional overview 3.30 STM32F427xx STM32F429xx Secure digital input/output interface (SDIO) An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1. 3.31 Ethernet MAC interface with dedicated DMA and IEEE 1588 support The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard medium-independent interface (MII) or a reduced medium-independent interface (RMII). The microcontroller requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller. The devices include the following features: 3.32 * Supports 10 and 100 Mbit/s rates * Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F4xx reference manual for details) * Tagged MAC frame support (VLAN support) * Half-duplex (CSMA/CD) and full-duplex operation * MAC control sublayer (control frames) support * 32-bit CRC generation and removal * Several address filtering modes for physical and multicast address (multicast and group addresses) * 32-bit status code for each transmitted or received frame * Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes. * Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input * Triggers interrupt when system time becomes greater than target time Controller area network (bxCAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive 40/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Functional overview FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for each CAN. 3.33 Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: 3.34 * Combined Rx and Tx FIFO size of 320 x 35 bits with dynamic FIFO sizing * Supports the session request protocol (SRP) and host negotiation protocol (HNP) * 4 bidirectional endpoints * 8 host channels with periodic OUT support * HNP/SNP/IP inside (no need for any external resistor) * For OTG/Host modes, a power switch is needed in case bus-powered devices are connected Universal serial bus on-the-go high-speed (OTG_HS) The devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: * Combined Rx and Tx FIFO size of 1 Kbit x 35 with dynamic FIFO sizing * Supports the session request protocol (SRP) and host negotiation protocol (HNP) * 6 bidirectional endpoints * 12 host channels with periodic OUT support * Internal FS OTG PHY support * External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. * Internal USB DMA * HNP/SNP/IP inside (no need for any external resistor) * for OTG/Host modes, a power switch is needed in case bus-powered devices are connected DocID024030 Rev 10 41/239 44 Functional overview 3.35 STM32F427xx STM32F429xx Digital camera interface (DCMI) The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features: 3.36 * Programmable polarity for the input pixel clock and synchronization signals * Parallel data communication can be 8-, 10-, 12- or 14-bit * Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) * Supports continuous mode or snapshot (a single frame) mode * Capability to automatically crop the image Random number generator (RNG) All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.37 General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allowing maximum I/O toggling up to 90 MHz. 3.38 Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: * Simultaneous sample and hold * Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer. 42/239 DocID024030 Rev 10 STM32F427xx STM32F429xx 3.39 Functional overview Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the sensor output voltage into a digital value. When the temperature sensor and VBAT conversion are enabled at the same time, only VBAT conversion is performed. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 3.40 Digital-to-analog converter (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features: * two DAC converters: one for each output channel * 8-bit or 10-bit monotonic output * left or right data alignment in 12-bit mode * synchronized update capability * noise-wave generation * triangular-wave generation * dual DAC channel independent or simultaneous conversions * DMA capability for each channel * external triggers for conversion * input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 3.41 Serial wire JTAG debug port (SWJ-DP) The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. DocID024030 Rev 10 43/239 44 Functional overview 3.42 STM32F427xx STM32F429xx Embedded Trace MacrocellTM The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F42x through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. 44/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Pinouts and pin description 6$$ 633 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 11. STM32F42x LQFP100 pinout ,1&0 6$$ 633 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 0% 0% 0% 0% 0% 6"!4 0# 0# 0# 633 6$$ 0( 0( .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0! 0! 0! 0! 633 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0% 0% 0% 0% 0% 0% 0% 0% 0% 0" 0" 6#!0? 6$$ 4 Pinouts and pin description AIC 1. The above figure shows the package top view. DocID024030 Rev 10 45/239 85 Pinouts and pin description STM32F427xx STM32F429xx Figure 12. STM32F42x WLCSP143 ballout $ 3'5 B21 3( 3% 3% 3* 3* 3' 3' % 3( 3( 3% 3% 3% 3* 3' & 9%$7 3( %227 3% 3% 3* ' 3& 3& 3( 3( 9'' ( 3& 9'' 3) 3( ) 3) 3) 3) * 3) 3) + 3) - 3' 3& 9'' 3' 3' 3& 3$ 9'' 3' 3& 3$ 9'' 3* 3$ 3$ 3$ 966 9&$3 B 966 9'' 3* 3& 3& 3$ 3$ 3) 3) 3* 966 3' 3& 3& 3$ 3) 3) 9'' 3* 3* 3* 3* 3* 9'' 3+ 1567 3& 966 3' 3' 3' 966 966 3+ 3& 3& 9'' 9'' 9'' 9'' 3( 3% 3' 3* . 3& 966$ 3$ 3$ 3% 3) 3* 3( 3% 3' 3' / 95() 9''$ 3$ 3$ 3% 3) 3( 3( 3( 3' 9'' 0 3$ 3$ 3$ 3& 3) 3) 3( 3% 3% 3' 1 %<3$66B 5(* 3$ 3& 3% 3) 3* 3( 3% 9&$3 B 3% 3( 3( 3* 069 1. The above figure shows the package bump view. 46/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Pinouts and pin description 6$$ 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 13. STM32F42x LQFP144 pinout ,1&0 6$$ 633 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 6$$ 633 0' 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 6#!0? 6$$ 0! 633 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 633 6$$ 0& 0& 0& 0' 0' 0% 0% 0% 633 6$$ 0% 0% 0% 0% 0% 0% 0" 0" 0% 0% 0% 0% 0% 6"!4 0# 0# 0# 0& 0& 0& 0& 0& 0& 633 6$$ 0& 0& 0& 0& 0& 0( 0( .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0! 0! 0! AIB 1. The above figure shows the package top view. DocID024030 Rev 10 47/239 85 Pinouts and pin description STM32F427xx STM32F429xx 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 6$$ 633 0) 0) 0) 0) 0) 0) 6 $$ Figure 14. STM32F42x LQFP176 pinout ,1&0 0) 0) 0( 0( 0( 6$$ 633 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 6$$ 633 0' 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 6$$ 633 0( 6#!0? 6$$ 0( 0( 0( 0( 0( 0( 633 6$$ 0& 0& 0& 0' 0' 0% 0% 0% 633 6$$ 0% 0% 0% 0% 0% 0% 0" 0" 0( 0( 0! "90!33?2%' 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 0% 0% 0% 0% 0% 6"!4 0) 0# 0# 0# 0) 0) 0) 633 6$$ 0& 0& 0& 0& 0& 0& 633 6$$ 0& 0& 0& 0& 0& 0( 0( .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0! 0! 0! 0( 0( -36 1. The above figure shows the package top view. 48/239 DocID024030 Rev 10 0) 0) 0) 0) 6$$ 0$2?/. 633 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 0+ 0+ 0+ 0+ 0+ 6$$ 633 0' 0' 0' 0' 0' 0' 0* 0* 0* 0* 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 6$$ 0) STM32F427xx STM32F429xx Figure 15. STM32F42x LQFP208 pinout 0) 0) 0) 0( 0( 0( 6$$ 633 6#!0 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 6$$ 633 0& 0& 0& 0' 0' 0' 0' 0' 0' 0' 0+ 0+ 0+ 633 6$$ 0* 0* 0* 0* 0* 0* 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 633 6$$ 0& 0& 0& 0& 0& 0( 0( .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0! 0! 0! 0( 0( 0( 0( 0! 633 6$$ ,1&0 0! 0! 0! 0! 0# 0# 6$$ 633 0" 0" 0" 0) 0* 0* 0* 0* 0* 0& 0& 633 6$$ 0& 0& 0& 0' 0' 0% 0% 0% 633 6$$ 0% 0% 0% 0% 0% 0% 0" 0" 6#!0 633 6$$ 0* 0( 0( 0( 0( 0( 0( 0( 6$$ 0" 49/239 1. The above figure shows the package top view. -36 Pinouts and pin description DocID024030 Rev 10 0% 0% 0% 0% 0% 6"!4 0) 0# 0# 0# 0) 0) 0) 633 6$$ 0& 0& 0& 0) 0) 0) Pinouts and pin description STM32F427xx STM32F429xx Figure 16. STM32F42x UFBGA169 ballout 0) 0) 0% "//4 0" 0' 0$ 0$ 0# 0! 0) 0) 0% 0) 0% 0" 0" 0' 0$ 0$ 0# 0! 0) 0) 0% 0% 0$2 ?/. 0" 0" 0' 0' 0$ 0$ 0# 0) 0( 0( $ 0% 0% 6$$ 0" 0" 6$$ 633 0$ 0$ 6$$ 633 6#!0 ? 0( % 0# 0) 0) 0# 6"!4 6$$ 633 0! 0! 0! 0! 0! 0! & 0# 0& 0& 6$$ 633 633 6$$ 6$$ 0# 0# 0# 0# 0' ' 0( 0( 0& 0& 0& 0# 633 6$$ 633 6$$ 0' 0' 0' 0& .234 0& 6$$ 0# 0# 0# 6$$ 0% 0$ 0$ 0' 0' * 633! 62%& 62%& 6$$! 0! 633 633 0% 0% 633 6$$ 0$ 0$ + 0! 0! 0! 0! 0" 6$$ 0& 0% 0% 0( 0$ 0$ 0$ , 0( 0( 0( 0# 0" 6$$ 0& 0% 0" 0( 0( 0$ 0" - "90!33 ?2%' 0( 0! 0# 0& 0& 0' 0% 0" 0( 0( 0" 0" 0! 0! 0" 0& 0' 0% 0% 6#!0 ? 0( 0( 0" ! " # ( . -36 1. The above figure shows the package top view. 2. The 4 corners balls, A1,A13, N1 and N13, are not bonded internally and should be left not connected on the PCB. 50/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Pinouts and pin description Figure 17. STM32F42x UFBGA176 ballout ! 0% 0% " 0% # 0% 0% 0" 0" 0' 0' 0" 0% 0% 0" 0" 0" 0' 0' 6"!4 0) 0) 0) 6$$ 0$2?/. 6$$ $ 0# 0) 0) 0) 633 633 % 0# 0& 0) 0) & 0# 633 6$$ 0( 633 633 633 633 ' 0( 633 6$$ 0( 633 633 633 ( 0( 0& 0& 0( 633 633 * .234 0& 0& 0( 633 + 0& 0& 0& 6$$ 633 , 0& 0& 0& "90!33? 2%' - 633! 0# 0# 0# 0# 0" 0' 633 633 . 62%& 0! 0! 0! 0# 0& 0' 6$$ 6$$ 0 62%& 0! 0! 0! 0# 0& 0& 0% 2 6$$! 0! 0! 0" 0" 0& 0& 0% "//4 0" 0$ 0# 0! 0! 0! 0' 0' 0$ 0$ 0# 0# 0! 6$$ 6$$ 0' 0$ 0$ 0) 0) 0! 633 633 0$ 0$ 0$ 0( 0) 0! 0( 0( 0) 0! 633 633 6#!0 0# 0! 633 633 633 6$$ 0# 0# 633 633 633 633 6$$ 0' 0# 633 633 633 633 6$$ 6$$ 0' 0' 633 633 633 633 0( 0' 0' 0' 0( 0( 0$ 0' 0( 0( 0( 0$ 0$ 6$$ 0% 0( 0$ 0$ 0$ 0% 0% 0% 0" 0" 0$ 0$ 0% 0% 0% 0" 0" 0" 0" 6#!0? AIC 1. The above figure shows the package top view. DocID024030 Rev 10 51/239 85 Pinouts and pin description STM32F427xx STM32F429xx Figure 18. STM32F42x TFBGA216 ballout ! 0% 0% 0% 0' 0% 0% 0" 0" 0" 0" 0$ " 0% 0% 0' 0" 0" 0" 0' 0' 0* 0* # 6"!4 0) 0) 0+ 0+ 0+ 0' 0' 0* $ 0# 0& 0) 0) 0) 0) 0+ 0+ % 0# 0& 0) 0) 0$2? /. "//4 6$$ & 0# 633 0) 6$$ 6$$ 633 633 ' 0( 0& 0) 0) 6$$ ( 0( 0& 0) 0( * .234 0& 0( + 0& 0& 0# 0! 0! 0! 0$ 0$ 0# 0# 0! 0$ 0$ 0$ 0) 0) 0! 0' 0* 0$ 0$ 0( 0) 0! 6$$ 6$$ 6$$ 6#!0 0( 0( 0) 0! 633 633 633 6$$ 0+ 0+ 0# 0! 633 633 6$$ 0* 0+ 0# 0# 6$$ 633 633 6$$ 0* 0* 0' 0# 0( 6$$ 633 633 6$$ 0* 0* 0' 0' 0& 0( 6$$ 633 633 633 633 633 6$$ 0* 0$ 0" 0$ 0& 0& 0& 0# "90!33 2%' 633 6$$ 6$$ 6$$ 6$$ 6#!0 0$ 0" 0$ 0$ - 633! 0# 0# 0# 0" 0& 0' 0& 0* 0$ 0$ 0' 0' 0* 0( . 62%& 0! 0! 0! 0# 0& 0' 0* 0% 0$ 0' 0' 0( 0( 0( 0 62%& 0! 0! 0! 0# 0& 0* 0& 0% 0% 0% 0" 0( 0( 0( 2 6$$! 0! 0! 0" 0" 0* 0* 0% 0% 0% 0% 0% 0" 0" 0" , -36 1. The above figure shows the package top view. 52/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Pinouts and pin description Table 9. Legend/abbreviations used in the pinout table Name Pin name Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TTa 3.3 V tolerant I/O directly connected to ADC B Dedicated BOOT0 pin RST Bidirectional reset pin with weak pull-up resistor Pin type I/O structure Notes Definition Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers Table 10. STM32F427xx and STM32F429xx pin and ball definitions B2 A2 1 D8 1 A3 PE2 I/O FT - 2 2 C1 A1 2 C10 2 A2 PE3 I/O FT - TRACED0, SAI1_SD_B, FMC_A19, EVENTOUT - - TRACED1, SPI4_NSS, SAI1_FS_A, FMC_A20, DCMI_D4, LCD_B0, EVENTOUT - 3 3 C2 B1 3 B11 LQFP208 1 LQFP176 1 TRACECLK, SPI4_SCK, SAI1_MCLK_A, ETH_MII_TXD3, FMC_A23, EVENTOUT LQFP144 Alternate functions LQFP100 Notes I / O structure Pin name (function after reset)(1) Pin type TFBGA216 WLCSP143 UFBGA176 UFBGA169 Pin number 3 A1 PE4 I/O FT DocID024030 Rev 10 Additional functions - 53/239 85 Pinouts and pin description STM32F427xx STM32F429xx Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) 4 D1 4 D9 4 B1 PE5 I / O structure Pin type TFBGA216 LQFP208 WLCSP143 LQFP176 UFBGA176 B2 Pin name (function after reset)(1) I/O FT Alternate functions Additional functions - TRACED2, TIM9_CH1, SPI4_MISO, SAI1_SCK_A, FMC_A21, DCMI_D6, LCD_G0, EVENTOUT - - TRACED3, TIM9_CH2, SPI4_MOSI, SAI1_SD_A, FMC_A22, DCMI_D7, LCD_G1, EVENTOUT - 5 5 D2 B3 5 E8 5 B2 PE6 - - - - - - - G6 VSS S - - - - - - - - - - - F5 VDD S - - - - 6 6 E5 C1 6 C11 6 C1 VBAT S - - - - EVENTOUT TAMP_2 EVENTOUT TAMP_1 NC I/O FT Notes 4 UFBGA169 LQFP144 LQFP100 Pin number (3) (2) D2 7 - 7 C2 PI8 I/O FT (4) 7 E4 D1 8 D10 8 D1 PC13 I/O FT (4) 8 8 E1 E1 9 D11 9 E1 PC14OSC32_IN (PC14) I/O FT (4) 9 9 F1 F1 10 E11 10 F1 PC15OSC32_OUT (PC15) I/O FT (4) - - - - - - - G5 VDD - - E2 D3 11 - 11 E4 PI9 - - 7 (3) EVENTOUT (3) S - I/O FT OSC32_IN (5) EVENTOUT OSC32_ OUT(5) - - - - CAN1_RX, FMC_D30, LCD_VSYNC, EVENTOUT - - E3 12 - 12 D5 PI10 I/O FT - ETH_MII_RX_ER, FMC_D31, LCD_HSYNC, EVENTOUT (2) E4 13 - 13 F3 PI11 I/O FT - OTG_HS_ULPI_DIR, EVENTOUT - - F6 F2 14 E7 14 F2 VSS S - - - - - F4 F3 15 E10 15 F4 VDD S - - - - - - - - - 54/239 (3) E3 NC DocID024030 Rev 10 STM32F427xx STM32F429xx Pinouts and pin description Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin name (function after reset)(1) Notes I / O structure LQFP100 Pin type Pin number Alternate functions - 10 F2 E2 16 F11 16 D2 PF0 I/O FT - I2C2_SDA, FMC_A0, EVENTOUT - - 11 F3 H3 17 E9 17 E2 PF1 I/O FT - I2C2_SCL, FMC_A1, EVENTOUT - - 12 G5 H2 18 F10 18 G2 PF2 I/O FT - I2C2_SMBA, FMC_A2, EVENTOUT - - - - - - - 19 E3 PI12 I/O FT - LCD_HSYNC, EVENTOUT - - - - - - - 20 G3 PI13 I/O FT - LCD_VSYNC, EVENTOUT - - - - - - - 21 H3 PI14 I/O FT Additional functions LCD_CLK, EVENTOUT - (5) FMC_A3, EVENTOUT ADC3_IN9 - 13 G4 J2 19 G11 22 H2 PF3 I/O FT - 14 G3 J3 20 F9 23 J2 PF4 I/O FT (5) FMC_A4, EVENTOUT ADC3_ IN14 - 15 H3 K3 21 F8 24 K3 PF5 I/O FT (5) FMC_A5, EVENTOUT ADC3_ IN15 10 16 G7 G2 22 H7 25 H6 VSS S - - - - 11 17 G8 G3 23 - 26 H5 VDD S - - - - I/O FT (5) TIM10_CH1, SPI5_NSS, SAI1_SD_B, UART7_Rx, FMC_NIORD, EVENTOUT ADC3_IN4 I/O FT (5) TIM11_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_Tx, FMC_NREG, EVENTOUT ADC3_IN5 I/O FT (5) SPI5_MISO, SAI1_SCK_B, TIM13_CH1, FMC_NIOWR, EVENTOUT ADC3_IN6 - - - 18 19 20 NC (2) NC (2) NC (2) K2 K1 L3 24 25 26 G10 F7 H11 27 28 29 K2 K1 L3 PF6 PF7 PF8 DocID024030 Rev 10 55/239 85 Pinouts and pin description STM32F427xx STM32F429xx Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) - 21 - NC Notes I / O structure Pin name (function after reset)(1) Pin type TFBGA216 LQFP208 WLCSP143 LQFP176 UFBGA176 UFBGA169 LQFP144 LQFP100 Pin number (5) (2) L2 27 G8 30 L2 PF9 I/O FT 22 H1 L1 28 G9 31 L1 PF10 I/O FT (5) 12 23 G2 G1 29 J11 32 G1 PH0-OSC_IN (PH0) I/O FT 13 24 G1 H1 30 H10 33 H1 PH1OSC_OUT (PH1) 14 25 H2 J1 31 H9 34 J1 NRST 15 26 G6 M2 32 H8 35 M2 PC0 16 27 H5 M3 33 K11 36 M3 PC1 17 28 H6 M4 34 J10 37 M4 PC2 Alternate functions Additional functions SPI5_MOSI, SAI1_FS_B, ADC3_IN7 TIM14_CH1, FMC_CD, EVENTOUT FMC_INTR, DCMI_D11, LCD_DE, EVENTOUT ADC3_IN8 - EVENTOUT OSC_IN(5) I/O FT - EVENTOUT RS T - - - I/O FT (5) OTG_HS_ULPI_STP, FMC_SDNWE, EVENTOUT ADC123_ IN10 I/O FT (5) ETH_MDC, EVENTOUT ADC123_ IN11 I/O FT (5) SPI2_MISO, I2S2ext_SD, OTG_HS_ULPI_DIR, ETH_MII_TXD2, FMC_SDNE0, EVENTOUT ADC123_ IN12 I/O FT (5) SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK, FMC_SDCKE0, EVENTOUT ADC123_ IN13 I/O OSC_OUT (5) 18 29 H7 M5 35 J9 38 L4 PC3 19 30 - - 36 G7 39 J5 VDD S - - - - - - - - - - - J6 VSS S - - - - 20 31 J1 M1 37 K10 40 M1 VSSA S - - - - - - J2 N1 - - - N1 VREF- S - - - - 21 32 J3 P1 38 L11 41 P1 VREF+ S - - - - 56/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Pinouts and pin description Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 33 J4 R1 39 L10 42 R1 VDDA 23 24 34 35 J5 K1 N3 N2 40 41 K9 K8 43 44 N3 N2 PA0-WKUP (PA0) S - Notes UFBGA169 22 I / O structure LQFP144 Pin name (function after reset)(1) Pin type LQFP100 Pin number Alternate functions Additional functions - - - TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, ADC123_ USART2_CTS, I/O FT (6) IN0/WKUP UART4_TX, (5) ETH_MII_CRS, EVENTOUT PA1 TIM2_CH2, TIM5_CH2, USART2_RTS, UART4_RX, (5) I/O FT ETH_MII_RX_CLK/ETH _RMII_REF_CLK, EVENTOUT ADC123_ IN1 ADC123_ IN2 25 36 K2 P2 42 L9 45 P2 PA2 TIM2_CH3, TIM5_CH3, TIM9_CH1, I/O FT (5) USART2_TX, ETH_MDIO, EVENTOUT - - L2 F4 43 - 46 K4 PH2 I/O FT - ETH_MII_CRS, FMC_SDCKE0, LCD_R0, EVENTOUT - - - L1 G4 44 - 47 J4 PH3 I/O FT - ETH_MII_COL, FMC_SDNE0, LCD_R1, EVENTOUT - - - M2 H4 45 - 48 H4 PH4 I/O FT - I2C2_SCL, OTG_HS_ULPI_NXT, EVENTOUT - - - L3 J4 46 - 49 J3 PH5 I/O FT - I2C2_SDA, SPI5_NSS, FMC_SDNWE, EVENTOUT - TIM2_CH4, TIM5_CH4, TIM9_CH2, USART2_RX, I/O FT (5) OTG_HS_ULPI_D0, ETH_MII_COL, LCD_B5, EVENTOUT 26 37 K3 R2 27 38 - - 47 M11 50 R2 PA3 - 51 K6 VSS S DocID024030 Rev 10 - - - ADC123_ IN3 - 57/239 85 Pinouts and pin description STM32F427xx STM32F429xx Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes Pin number Alternate functions - - M1 L4 48 N11 - L5 BYPASS_ REG I FT - - - 28 39 J11 K4 49 J8 52 K5 VDD S - - - - SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK, OTG_HS_SOF, DCMI_HSYNC, LCD_VSYNC, EVENTOUT ADC12_ IN4 /DAC_ OUT1 29 30 31 40 41 42 N2 M3 N3 N4 P4 P3 50 51 52 M10 53 M9 N10 54 55 N4 P4 P3 Pin name (function after reset)(1) PA4 I/O TTa (5) PA5 TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK, I/O TTa (5) OTG_HS_ULPI_CK, EVENTOUT PA6 I/O FT (5) TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, TIM13_CH1, DCMI_PIXCLK, LCD_G2, EVENTOUT Additional functions ADC12_ IN5/DAC_ OUT2 ADC12_ IN6 32 43 K4 R3 53 L8 56 R3 PA7 TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI, I/O FT (5) TIM14_CH1, ETH_MII_RX_DV/ETH_ RMII_CRS_DV, EVENTOUT 33 44 L4 N5 54 M8 57 N5 PC4 I/O FT (5) ETH_MII_RXD0/ETH_ RMII_RXD0, EVENTOUT ADC12_ IN14 34 45 M4 P5 55 N9 58 P5 PC5 I/O FT (5) ETH_MII_RXD1/ETH_ RMII_RXD1, EVENTOUT ADC12_ IN15 - - - - - J7 59 L7 VDD S - - - - - - - - - - 60 L6 VSS S - - - - 58/239 DocID024030 Rev 10 ADC12_ IN7 STM32F427xx STM32F429xx Pinouts and pin description Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) 35 46 N4 R5 56 N8 61 R5 Notes I / O structure Pin name (function after reset)(1) Pin type TFBGA216 LQFP208 WLCSP143 LQFP176 UFBGA176 UFBGA169 LQFP144 LQFP100 Pin number Alternate functions Additional functions PB0 TIM1_CH2N, TIM3_CH3, TIM8_CH2N, LCD_R3, (5) I/O FT OTG_HS_ULPI_D1, ETH_MII_RXD2, EVENTOUT ADC12_ IN8 TIM1_CH3N, TIM3_CH4, TIM8_CH3N, LCD_R6, (5) I/O FT OTG_HS_ULPI_D2, ETH_MII_RXD3, EVENTOUT ADC12_ IN9 36 47 K5 R4 57 K7 62 R4 PB1 37 48 L5 M6 58 L7 63 M5 PB2-BOOT1 (PB2) I/O FT - EVENTOUT - - - - - - - 64 G4 PI15 I/O FT - LCD_R0, EVENTOUT - - - - - - - 65 R6 PJ0 I/O FT - LCD_R1, EVENTOUT - - - - - - - 66 R7 PJ1 I/O FT - LCD_R2, EVENTOUT - - - - - - - 67 P7 PJ2 I/O FT - LCD_R3, EVENTOUT - - - - - - - 68 N8 PJ3 I/O FT - LCD_R4, EVENTOUT - - - - - - - 69 M9 PJ4 I/O FT - LCD_R5, EVENTOUT - - - 49 M5 R6 59 M7 70 P8 PF11 I/O FT - SPI5_MOSI, FMC_SDNRAS, DCMI_D12, EVENTOUT - 50 N5 P6 60 N7 71 M6 PF12 I/O FT - FMC_A6, EVENTOUT - - 51 G9 M8 61 - 72 K7 VSS S - - - - 52 D10 N8 62 - 73 L8 VDD S - - - - 53 M6 N6 63 K6 74 N6 PF13 I/O FT - FMC_A7, EVENTOUT - - 54 K7 R7 64 L6 75 P6 PF14 I/O FT - FMC_A8, EVENTOUT - - 55 L7 P7 65 M6 76 M8 PF15 I/O FT - FMC_A9, EVENTOUT - - 56 N6 N7 66 N6 77 N7 PG0 I/O FT - FMC_A10, EVENTOUT - - 57 M7 M7 67 K5 78 M7 PG1 I/O FT - FMC_A11, EVENTOUT - DocID024030 Rev 10 59/239 85 Pinouts and pin description STM32F427xx STM32F429xx Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin name (function after reset)(1) Notes I / O structure LQFP100 Pin type Pin number Alternate functions 38 58 N7 R8 68 L5 79 R8 PE7 I/O FT - TIM1_ETR, UART7_Rx, FMC_D4, EVENTOUT - 39 59 J8 P8 69 M5 80 N9 PE8 I/O FT - TIM1_CH1N, UART7_Tx, FMC_D5, EVENTOUT - 40 60 K8 P9 70 N5 81 P9 PE9 I/O FT - TIM1_CH1, FMC_D6, EVENTOUT - - 61 J6 M9 71 H3 82 K8 VSS S - - - 62 G10 N9 72 J5 83 L9 VDD S - - 41 63 L8 R9 73 J4 84 R9 PE10 I/O FT - TIM1_CH2N, FMC_D7, EVENTOUT - 42 64 M8 P10 74 K4 85 P10 PE11 I/O FT - TIM1_CH2, SPI4_NSS, FMC_D8, LCD_G3, EVENTOUT - 43 65 N8 R10 75 L4 86 R10 PE12 I/O FT - TIM1_CH3N, SPI4_SCK, FMC_D9, LCD_B4, EVENTOUT - 44 66 H9 N11 76 N4 87 R12 PE13 I/O FT - TIM1_CH3, SPI4_MISO, FMC_D10, LCD_DE, EVENTOUT - 45 67 J9 P11 77 M4 88 P11 PE14 I/O FT - TIM1_CH4, SPI4_MOSI, FMC_D11, LCD_CLK, EVENTOUT - 46 68 K9 R11 78 L3 89 R11 PE15 I/O FT - TIM1_BKIN, FMC_D12, LCD_R7, EVENTOUT - - TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER, LCD_G4, EVENTOUT - - TIM2_CH4, I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, ETH_MII_TX_EN/ETH_ RMII_TX_EN, LCD_G5, EVENTOUT - 47 48 69 70 60/239 L9 M9 R12 R13 79 80 M3 N3 90 91 P12 R13 PB10 PB11 I/O FT I/O FT DocID024030 Rev 10 Additional functions STM32F427xx STM32F429xx Pinouts and pin description Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin name (function after reset)(1) Pin type I / O structure Notes Pin number Alternate functions 49 71 N9 M10 81 N2 92 L11 VCAP_1 S - - - - - - - - - H2 93 K9 VSS S - - - - 50 72 F8 N10 82 J6 94 L10 VDD S - - - - - - - - - - 95 M14 PJ5 I/O - - LCD_R6, EVENTOUT - - I2C2_SMBA, SPI5_SCK, TIM12_CH1, ETH_MII_RXD2, FMC_SDNE1, DCMI_D8, EVENTOUT - - - - N10 M11 83 - 96 P13 PH6 I/O FT Additional functions - - M10 N12 84 - 97 N13 PH7 I/O FT - I2C3_SCL, SPI5_MISO, ETH_MII_RXD3, FMC_SDCKE1, DCMI_D9, EVENTOUT - - L10 85 - 98 P14 PH8 I/O FT - I2C3_SDA, FMC_D16, DCMI_HSYNC, LCD_R2, EVENTOUT - - M12 - - K10 M13 86 - 99 N14 PH9 I/O FT - I2C3_SMBA, TIM12_CH2, FMC_D17, DCMI_D0, LCD_R3, EVENTOUT - - N11 L13 87 - 100 P15 PH10 I/O FT - TIM5_CH1, FMC_D18, DCMI_D1, LCD_R4, EVENTOUT - - - M11 L12 88 - 101 N15 PH11 I/O FT - TIM5_CH2, FMC_D19, DCMI_D2, LCD_R5, EVENTOUT - - - L11 K12 89 - 102 M15 PH12 I/O FT - TIM5_CH3, FMC_D20, DCMI_D3, LCD_R6, EVENTOUT - - - E7 H12 90 - - - H8 J12 91 - K10 VSS S - - - - 103 K11 VDD S - - - - - DocID024030 Rev 10 61/239 85 Pinouts and pin description STM32F427xx STM32F429xx Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) 52 53 73 74 75 M12 P12 P13 M13 R14 92 93 94 M2 104 L13 N1 K3 105 K14 106 R14 PB12 PB13 PB14 I / O structure Pin type TFBGA216 LQFP208 WLCSP143 LQFP176 UFBGA176 UFBGA169 N12 Pin name (function after reset)(1) I/O FT I/O FT I/O FT Notes 51 LQFP144 LQFP100 Pin number Alternate functions Additional functions - TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, USART3_CK, CAN2_RX, OTG_HS_ULPI_D5, ETH_MII_TXD0/ETH_R MII_TXD0, OTG_HS_ID, EVENTOUT - - TIM1_CH1N, SPI2_SCK/I2S2_CK, USART3_CTS, OTG_HS_ CAN2_TX, VBUS OTG_HS_ULPI_D6, ETH_MII_TXD1/ETH_R MII_TXD1, EVENTOUT - TIM1_CH2N, TIM8_CH2N, SPI2_MISO, I2S2ext_SD, USART3_RTS, TIM12_CH1, OTG_HS_DM, EVENTOUT - - 54 76 L13 R15 95 J3 107 R15 PB15 I/O FT - RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI/I2S2_SD, TIM12_CH2, OTG_HS_DP, EVENTOUT 55 77 L12 P15 96 L2 108 L15 PD8 I/O FT - USART3_TX, FMC_D13, EVENTOUT - 56 78 K13 P14 97 M1 109 L14 PD9 I/O FT - USART3_RX, FMC_D14, EVENTOUT - 57 79 K11 N15 98 H4 PD10 I/O FT - USART3_CK, FMC_D15, LCD_B3, EVENTOUT - 62/239 110 K15 DocID024030 Rev 10 STM32F427xx STM32F429xx Pinouts and pin description Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 Notes I / O structure LQFP144 Alternate functions 58 80 H10 N14 99 K2 111 N10 PD11 I/O FT - USART3_CTS, FMC_A16, EVENTOUT - 59 81 J13 N13 100 H6 112 M10 PD12 I/O FT - TIM4_CH1, USART3_RTS, FMC_A17, EVENTOUT - 60 82 K12 M15 101 H5 113 M11 PD13 I/O FT - TIM4_CH2, FMC_A18, EVENTOUT - - 83 - - 102 - 114 J10 VSS S - - - - 84 F7 J13 103 L1 115 J11 VDD S - - - 61 85 H11 M14 104 J2 116 L12 PD14 I/O FT - TIM4_CH3, FMC_D0, EVENTOUT - 62 86 J12 L14 105 K1 117 K13 PD15 I/O FT - TIM4_CH4, FMC_D1, EVENTOUT - - - - - - - 118 K12 PJ6 I/O FT - LCD_R7, EVENTOUT - - - - - - - 119 J12 PJ7 I/O FT - LCD_G0, EVENTOUT - - - - - - - 120 H12 PJ8 I/O FT - LCD_G1, EVENTOUT - - - - - - - 121 J13 PJ9 I/O FT - LCD_G2, EVENTOUT - - - - - - - 122 H13 PJ10 I/O FT - LCD_G3, EVENTOUT - - - - - - - 123 G12 PJ11 I/O FT - LCD_G4, EVENTOUT - - - - - - - 124 H11 VDD I/O FT - - - - - - - - - 125 H10 VSS I/O FT - - - - - - - - - 126 G13 PK0 I/O FT - LCD_G5, EVENTOUT - - - - - - - 127 F12 PK1 I/O FT - LCD_G6, EVENTOUT - - - - - - - 128 F13 PK2 I/O FT - LCD_G7, EVENTOUT - - 87 H13 L15 106 J1 129 M13 PG2 I/O FT - FMC_A12, EVENTOUT - - 88 (2) K15 107 G3 130 M12 PG3 I/O FT - FMC_A13, EVENTOUT - - 89 H12 K14 108 G5 131 N12 PG4 I/O FT - FMC_A14/FMC_BA0, EVENTOUT - - 90 G13 K13 109 G6 132 N11 PG5 I/O FT - FMC_A15/FMC_BA1, EVENTOUT - NC TFBGA216 LQFP100 Pin name (function after reset)(1) Pin type Pin number DocID024030 Rev 10 Additional functions 63/239 85 Pinouts and pin description STM32F427xx STM32F429xx Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin name (function after reset)(1) Notes I / O structure LQFP100 Pin type Pin number Alternate functions - 91 G11 J15 110 G4 133 J15 PG6 I/O FT - FMC_INT2, DCMI_D12, LCD_R7, EVENTOUT - - 92 G12 J14 111 H1 134 J14 PG7 I/O FT - USART6_CK, FMC_INT3, DCMI_D13, LCD_CLK, EVENTOUT - - SPI6_NSS, USART6_RTS, ETH_PPS_OUT, FMC_SDCLK, EVENTOUT - - 93 F13 H14 112 G2 135 H14 PG8 - 94 J7 G12 113 D2 136 G10 VSS S - - - - 95 E6 H13 114 G1 137 G11 VDD S - - - - TIM3_CH1, TIM8_CH1, I2S2_MCK, USART6_TX, SDIO_D6, DCMI_D0, LCD_HSYNC, EVENTOUT - - TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, SDIO_D7, DCMI_D1, LCD_G6, EVENTOUT - - TIM3_CH3, TIM8_CH3, USART6_CK, SDIO_D0, DCMI_D2, EVENTOUT - - MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, SDIO_D1, DCMI_D3, EVENTOUT - - MCO1, TIM1_CH1, I2C3_SCL, USART1_CK, OTG_FS_SOF, LCD_R6, EVENTOUT - 63 64 65 66 67 96 97 98 99 F9 F10 F11 F12 100 E13 64/239 H15 115 G15 116 G14 117 F14 F15 118 119 F2 F3 E4 E3 F1 138 H15 139 G15 140 G14 141 F14 142 F15 PC6 PC7 PC8 PC9 PA8 I/O FT Additional functions I/O FT I/O FT I/O FT I/O FT I/O FT DocID024030 Rev 10 STM32F427xx STM32F429xx Pinouts and pin description Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) 69 70 101 102 E9 103 E10 E15 120 D15 121 C15 122 E2 D5 D4 143 E15 144 D15 145 C15 PA9 PA10 PA11 I / O structure Pin type TFBGA216 LQFP208 WLCSP143 LQFP176 UFBGA176 UFBGA169 E8 Pin name (function after reset)(1) I/O FT I/O FT I/O FT Notes 68 LQFP144 LQFP100 Pin number Alternate functions Additional functions - TIM1_CH2, I2C3_SMBA, USART1_TX, DCMI_D0, EVENTOUT OTG_FS_ VBUS - TIM1_CH3, USART1_RX, OTG_FS_ID, DCMI_D1, EVENTOUT - - TIM1_CH4, USART1_CTS, CAN1_RX, LCD_R4, OTG_FS_DM, EVENTOUT - - 71 104 E11 B15 123 E1 146 B15 PA12 I/O FT - TIM1_ETR, USART1_RTS, CAN1_TX, LCD_R5, OTG_FS_DP, EVENTOUT 72 105 E12 A15 124 D3 147 A15 PA13 (JTMSSWDIO) I/O FT - JTMS-SWDIO, EVENTOUT - 73 106 D12 F13 125 D1 148 E11 VCAP_2 S - - - 74 107 J10 F12 126 D2 149 F10 VSS S - - - 75 108 H4 G13 127 C1 150 F11 VDD S - - - - - D13 E12 128 - 151 E12 PH13 I/O FT - TIM8_CH1N, CAN1_TX, FMC_D21, LCD_G2, EVENTOUT - - - C13 E13 129 - 152 E13 PH14 I/O FT - TIM8_CH2N, FMC_D22, DCMI_D4, LCD_G3, EVENTOUT - - - C12 D13 130 - 153 D13 PH15 I/O FT - TIM8_CH3N, FMC_D23, DCMI_D11, LCD_G4, EVENTOUT - - TIM5_CH4, SPI2_NSS/I2S2_WS(7), FMC_D24, DCMI_D13, LCD_G5, EVENTOUT - - - B13 E14 131 - 154 E14 PI0 I/O FT DocID024030 Rev 10 65/239 85 Pinouts and pin description STM32F427xx STM32F429xx Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) - - - C11 B12 C14 133 - - - - A12 C13 134 - - D11 D9 135 F5 - - D3 C9 136 A1 A14 137 B1 76 77 78 79 109 A11 110 B11 111 C10 112 B10 A13 138 B14 139 B13 140 - C2 A2 B2 155 D14 156 C14 157 C13 PI1 PI2 PI3 I / O structure Pin type TFBGA216 LQFP208 WLCSP143 LQFP176 UFBGA176 D14 132 Pin name (function after reset)(1) I/O FT I/O FT I/O FT Notes - UFBGA169 LQFP144 LQFP100 Pin number Alternate functions Additional functions - SPI2_SCK/I2S2_CK(7), FMC_D25, DCMI_D8, LCD_G6, EVENTOUT - - TIM8_CH4, SPI2_MISO, I2S2ext_SD, FMC_D26, DCMI_D9, LCD_G7, EVENTOUT - - TIM8_ETR, SPI2_MOSI/I2S2_SD, FMC_D27, DCMI_D10, EVENTOUT - VSS S - - - 158 E10 VDD S - - - 159 A14 PA14 (JTCKSWCLK) - JTCK-SWCLK/ EVENTOUT - - JTDI, TIM2_CH1/TIM2_ETR, SPI1_NSS, SPI3_NSS/I2S3_WS, EVENTOUT - - SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, SDIO_D2, DCMI_D8, LCD_R2, EVENTOUT - - I2S3ext_SD, SPI3_MISO, USART3_RX, UART4_RX, SDIO_D3, DCMI_D4, EVENTOUT - - - - F9 160 A13 161 B14 162 B13 PA15 (JTDI) PC10 PC11 I/O FT I/O FT I/O FT I/O FT 80 113 A10 A12 141 C3 163 A12 PC12 I/O FT - SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX, SDIO_CK, DCMI_D9, EVENTOUT 81 114 B12 142 B3 164 B12 PD0 I/O FT - CAN1_RX, FMC_D2, EVENTOUT 66/239 D9 DocID024030 Rev 10 STM32F427xx STM32F429xx Pinouts and pin description Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) 116 B9 D12 144 A3 166 D12 PD1 PD2 I / O structure 165 C12 I/O FT I/O FT Notes 83 C4 Pin name (function after reset)(1) Pin type C12 143 TFBGA216 UFBGA176 C9 LQFP208 UFBGA169 115 WLCSP143 LQFP144 82 LQFP176 LQFP100 Pin number Alternate functions Additional functions - CAN1_TX, FMC_D3, EVENTOUT - - TIM3_ETR, UART5_RX, SDIO_CMD, DCMI_D11, EVENTOUT - - 84 117 A9 D11 145 B4 167 C11 PD3 I/O FT - SPI2_SCK/I2S2_CK, USART2_CTS, FMC_CLK, DCMI_D5, LCD_G7, EVENTOUT 85 118 D8 D10 146 B5 168 D11 PD4 I/O FT - USART2_RTS, FMC_NOE, EVENTOUT - 86 119 C8 C11 147 A4 169 C10 PD5 I/O FT - USART2_TX, FMC_NWE, EVENTOUT - - 120 - D8 148 - 170 F8 VSS S - - - - 121 D6 C8 149 C5 171 E9 VDD S - - - - 87 122 B8 B11 150 F4 172 B11 PD6 I/O FT - SPI3_MOSI/I2S3_SD, SAI1_SD_A, USART2_RX, FMC_NWAIT, DCMI_D10, LCD_B2, EVENTOUT 88 123 A8 A11 151 A5 173 A11 PD7 I/O FT - USART2_CK, FMC_NE1/FMC_NCE2, EVENTOUT - - - - - - - 174 B10 PJ12 I/O FT - LCD_B0, EVENTOUT - - - - - - - 175 B9 PJ13 I/O FT - LCD_B1, EVENTOUT - - - - - - - 176 C9 PJ14 I/O FT - LCD_B2, EVENTOUT - - - - - - - 177 D10 PJ15 I/O FT - LCD_B3, EVENTOUT - - USART6_RX, FMC_NE2/FMC_NCE3, DCMI_VSYNC(8), EVENTOUT - - 124 NC (2) C10 152 E5 178 D9 PG9 I/O FT DocID024030 Rev 10 67/239 85 Pinouts and pin description STM32F427xx STM32F429xx Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) - - - 125 126 127 128 - 129 - B7 A7 NC (2) NC B10 153 B9 B8 A8 154 155 156 C6 B6 A6 D6 179 180 181 182 C8 B8 C7 B3 PG10 PG11 PG12 PG13 I / O structure Pin type TFBGA216 LQFP208 WLCSP143 LQFP176 UFBGA176 UFBGA169 C7 Pin name (function after reset)(1) I/O FT I/O FT I/O FT I/O FT Alternate functions Additional functions - LCD_G3, FMC_NCE4_1/FMC_N E3, DCMI_D2, LCD_B2, EVENTOUT - - ETH_MII_TX_EN/ETH_ RMII_TX_EN, FMC_NCE4_2, DCMI_D3, LCD_B3, EVENTOUT - - SPI6_MISO, USART6_RTS, LCD_B4, FMC_NE4, LCD_B1, EVENTOUT - - SPI6_SCK, USART6_CTS, ETH_MII_TXD0/ETH_R MII_TXD0, FMC_A24, EVENTOUT - - SPI6_MOSI, USART6_TX, ETH_MII_TXD1/ETH_R MII_TXD1, FMC_A25, EVENTOUT - (2) A7 157 F6 183 A4 PG14 130 D7 D7 158 - 184 F7 VSS S - - - - 131 L6 C7 159 E6 185 E8 VDD S - - - - - - - - - 186 D8 PK3 I/O FT - LCD_B4, EVENTOUT - - - - - - - 187 D7 PK4 I/O FT - LCD_B5, EVENTOUT - - - - - - - 188 C6 PK5 I/O FT - LCD_B6, EVENTOUT - - - - - - - 189 C5 PK6 I/O FT - LCD_B7, EVENTOUT - - - - - - - 190 C4 PK7 I/O FT - LCD_DE, EVENTOUT - - USART6_CTS, FMC_SDNCAS, DCMI_D13, EVENTOUT - - 132 68/239 C6 B7 160 A7 191 B7 PG15 I/O FT Notes - LQFP144 LQFP100 Pin number I/O FT DocID024030 Rev 10 STM32F427xx STM32F429xx Pinouts and pin description Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) 91 92 134 135 136 A6 D5 C5 A10 161 A9 A6 B6 162 163 164 C7 C8 A8 193 194 195 A9 A8 B6 PB4 (NJTRST) PB5 PB6 93 137 B5 B5 165 B8 196 B5 PB7 94 138 A5 D6 166 C9 197 E6 BOOT0 95 139 D4 A5 167 I / O structure Pin type B7 TFBGA216 LQFP208 LQFP176 UFBGA176 UFBGA169 B6 PB3 192 A10 (JTDO/TRACE I/O FT SWO) A9 198 A7 PB8 I/O FT I/O FT I/O FT I/O FT I B I/O FT DocID024030 Rev 10 Notes 90 133 Pin name (function after reset)(1) WLCSP143 89 LQFP144 LQFP100 Pin number Alternate functions Additional functions - JTDO/TRACESWO, TIM2_CH2, SPI1_SCK, SPI3_SCK/I2S3_CK, EVENTOUT - - NJTRST, TIM3_CH1, SPI1_MISO, SPI3_MISO, I2S3ext_SD, EVENTOUT - - TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI/I2S3_SD, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, FMC_SDCKE1, DCMI_D10, EVENTOUT - - TIM4_CH1, I2C1_SCL, USART1_TX, CAN2_TX, FMC_SDNE1, DCMI_D5, EVENTOUT - - TIM4_CH2, I2C1_SDA, USART1_RX, FMC_NL, DCMI_VSYNC, EVENTOUT - - - VPP TIM4_CH3, TIM10_CH1, I2C1_SCL, CAN1_RX, ETH_MII_TXD3, SDIO_D4, DCMI_D6, LCD_B6, EVENTOUT - 69/239 85 Pinouts and pin description STM32F427xx STM32F429xx Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) 140 B4 168 B9 199 B4 PB9 I / O structure Pin type TFBGA216 LQFP208 WLCSP143 LQFP176 UFBGA176 UFBGA169 C4 Pin name (function after reset)(1) I/O FT Notes 96 LQFP144 LQFP100 Pin number Alternate functions Additional functions - TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, CAN1_TX, SDIO_D5, DCMI_D7, LCD_B7, EVENTOUT - - - 97 141 B4 A4 169 B10 200 A6 PE0 I/O FT - TIM4_ETR, UART8_RX, FMC_NBL0, DCMI_D2, EVENTOUT 98 142 A4 A3 170 A10 201 A5 PE1 I/O FT - UART8_Tx, FMC_NBL1, DCMI_D3, EVENTOUT 99 - F5 D5 202 F6 VSS S - - - 143 C3 C6 171 A11 203 E5 PDR_ON S - - 100 144 K6 C5 172 D7 204 E7 VDD S - - B3 D4 173 - 205 C3 PI4 - - - - I/O FT - TIM8_BKIN, FMC_NBL2, DCMI_D5, LCD_B4, EVENTOUT - - - - A3 C4 174 - 206 D3 PI5 I/O FT - TIM8_CH1, FMC_NBL3, DCMI_VSYNC, LCD_B5, EVENTOUT - - A2 C3 175 - 207 D6 PI6 I/O FT - TIM8_CH2, FMC_D28, DCMI_D6, LCD_B6, EVENTOUT - - - B1 C2 176 - 208 D4 PI7 I/O FT - TIM8_CH3, FMC_D29, DCMI_D7, LCD_B7, EVENTOUT - 1. Function availability depends on the chosen device. 2. NC (not-connected) pins are not bonded. They must be configured by software to output push-pull and forced to 0 in the output data register to avoid extra current consumption in low power modes. 3. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED). 70/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Pinouts and pin description 4. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website: www.st.com. 5. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 6. If the device is delivered in an WLCSP143, UFBGA169, UFBGA176, LQFP176 or TFBGA216 package, and the BYPASS_REG pin is set to VDD (Regulator OFF/internal reset ON mode), then PA0 is used as an internal Reset (active low). 7. PI0 and PI1 cannot be used for I2S2 full-duplex mode. 8. The DCMI_VSYNC alternate function on PG9 is only available on silicon revision 3. DocID024030 Rev 10 71/239 85 Pinouts and pin description STM32F427xx STM32F429xx Table 11. FMC pin definition 72/239 Pin name CF NOR/PSRAM/ SRAM NOR/PSRAM Mux PF0 A0 A0 A0 PF1 A1 A1 A1 PF2 A2 A2 A2 PF3 A3 A3 A3 PF4 A4 A4 A4 PF5 A5 A5 A5 PF12 A6 A6 A6 PF13 A7 A7 A7 PF14 A8 A8 A8 PF15 A9 A9 A9 PG0 A10 A10 A10 PG1 A11 A11 PG2 A12 A12 PG3 A13 PG4 A14 BA0 PG5 A15 BA1 PD11 A16 A16 CLE PD12 A17 A17 ALE PD13 A18 A18 PE3 A19 A19 PE4 A20 A20 PE5 A21 A21 PE6 A22 A22 PE2 A23 A23 PG13 A24 A24 PG14 A25 A25 NAND16 SDRAM PD14 D0 D0 DA0 D0 D0 PD15 D1 D1 DA1 D1 D1 PD0 D2 D2 DA2 D2 D2 PD1 D3 D3 DA3 D3 D3 PE7 D4 D4 DA4 D4 D4 PE8 D5 D5 DA5 D5 D5 PE9 D6 D6 DA6 D6 D6 PE10 D7 D7 DA7 D7 D7 DocID024030 Rev 10 STM32F427xx STM32F429xx Pinouts and pin description Table 11. FMC pin definition (continued) Pin name CF NOR/PSRAM/ SRAM NOR/PSRAM Mux NAND16 SDRAM PE11 D8 D8 DA8 D8 D8 PE12 D9 D9 DA9 D9 D9 PE13 D10 D10 DA10 D10 D10 PE14 D11 D11 DA11 D11 D11 PE15 D12 D12 DA12 D12 D12 PD8 D13 D13 DA13 D13 D13 PD9 D14 D14 DA14 D14 D14 PD10 D15 D15 DA15 D15 D15 PH8 D16 D16 PH9 D17 D17 PH10 D18 D18 PH11 D19 D19 PH12 D20 D20 PH13 D21 D21 PH14 D22 D22 PH15 D23 D23 PI0 D24 D24 PI1 D25 D25 PI2 D26 D26 PI3 D27 D27 PI6 D28 D28 PI7 D29 D29 PI9 D30 D30 PI10 D31 D31 PD7 NE1 NE1 NCE2 PG9 NE2 NE2 NCE3 NE3 NE3 PG12 NE4 NE4 PD3 CLK CLK PG10 NCE4_1 PG11 NCE4_2 PD4 NOE NOE NOE NOE PD5 NWE NWE NWE NWE PD6 NWAIT NWAIT NWAIT NWAIT NL(NADV) NL(NADV) PB7 DocID024030 Rev 10 73/239 85 Pinouts and pin description STM32F427xx STM32F429xx Table 11. FMC pin definition (continued) 74/239 Pin name CF PF6 NIORD PF7 NREG PF8 NIOWR PF9 CD PF10 INTR NOR/PSRAM/ SRAM NOR/PSRAM Mux NAND16 PG6 INT2 PG7 INT3 SDRAM PE0 NBL0 NBL0 NBL0 PE1 NBL1 NBL1 NBL1 PI4 NBL2 NBL2 PI5 NBL3 NBL3 PG8 SDCLK PC0 SDNWE PF11 SDNRAS PG15 SDNCAS PH2 SDCKE0 PH3 SDNE0 PH6 SDNE1 PH7 SDCKE1 PH5 SDNWE PC2 SDNE0 PC3 SDCKE0 PB5 SDCKE1 PB6 SDNE1 DocID024030 Rev 10 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART1/ 2/3 ETH FMC/SDIO /OTG2_FS DCMI LCD SYS PA0 - TIM2_ CH1/TIM2 _ETR TIM5_ CH1 TIM8_ ETR - - - USART2_ UART4_TX CTS - - ETH_MII_ CRS - - - EVEN TOUT PA1 - TIM2_ CH2 TIM5_ CH2 - - - - USART2_ UART4_RX RTS - - ETH_MII_ RX_CLK/E TH_RMII_ REF_CLK - - - EVEN TOUT PA2 - TIM2_ CH3 TIM5_ CH3 TIM9_ CH1 - - - USART2_ TX - - - ETH_ MDIO - - - EVEN TOUT PA3 - TIM2_ CH4 TIM5_ CH4 TIM9_ CH2 - - - USART2_ RX - - OTG_HS_ ULPI_D0 ETH_MII_ COL - - LCD_B5 EVEN TOUT PA4 - - - - - SPI1_ NSS SPI3_ USART2_ NSS/ CK I2S3_WS - - - - OTG_HS_ SOF DCMI_ HSYNC LCD_ VSYNC EVEN TOUT PA5 - TIM2_ CH1/TIM2 _ETR - TIM8_ CH1N - SPI1_ SCK - - - - OTG_HS_ ULPI_CK - - - - EVEN TOUT PA6 - TIM1_ BKIN TIM3_ CH1 TIM8_ BKIN - SPI1_ MISO - - - TIM13_CH1 - - - DCMI_ PIXCLK LCD_G2 EVEN TOUT PA7 - TIM1_ CH1N TIM3_ CH2 TIM8_ CH1N - SPI1_ MOSI - - - TIM14_CH1 - ETH_MII_ RX_DV/ ETH_RMII _CRS_DV - - - EVEN TOUT PA8 MCO1 TIM1_ CH1 - - I2C3_ SCL - - USART1_ CK - - OTG_FS_ SOF - - - LCD_R6 EVEN TOUT PA9 - TIM1_ CH2 - - I2C3_ SMBA - - USART1_ TX - - - - - DCMI_ D0 - EVEN TOUT PA10 - TIM1_ CH3 - - - - - USART1_ RX - - OTG_FS_ ID - - DCMI_ D1 - EVEN TOUT PA11 - TIM1_ CH4 - - - - - USART1_ CTS - CAN1_RX OTG_FS_ DM - - - LCD_R4 EVEN TOUT PA12 - TIM1_ ETR - - - - - USART1_ RTS - CAN1_TX OTG_FS_ DP - - - LCD_R5 EVEN TOUT Port DocID024030 Rev 10 Port A AF8 AF9 AF10 USART6/ CAN1/2/ OTG2_HS UART4/5/7 TIM12/13/14 /OTG1_ /8 /LCD FS 75/239 Pinouts and pin description AF0 STM32F427xx STM32F429xx Table 12. STM32F427xx and STM32F429xx alternate function mapping AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART1/ 2/3 ETH FMC/SDIO /OTG2_FS DCMI LCD SYS PA13 JTMSSWDI O - - - - - - - - - - - - - - EVEN TOUT PA14 JTCKSWCL K - - - - - - - - - - - - - - EVEN TOUT PA15 JTDI TIM2_ CH1/TIM2 _ETR - - - SPI1_ NSS SPI3_ NSS/ I2S3_WS - - - - - - - - EVEN TOUT PB0 - TIM1_ CH2N TIM3_ CH3 TIM8_ CH2N - - - - - LCD_R3 OTG_HS_ ULPI_D1 ETH_MII_ RXD2 - - - EVEN TOUT PB1 - TIM1_ CH3N TIM3_ CH4 TIM8_ CH3N - - - - - LCD_R6 OTG_HS_ ULPI_D2 ETH_MII_ RXD3 - - - EVEN TOUT PB2 - - - - - - - - - - - - - - - EVEN TOUT PB3 JTDO/ TRAC ESWO TIM2_ CH2 - - - SPI1_ SCK SPI3_ SCK/ I2S3_CK - - - - - - - - EVEN TOUT PB4 NJTR ST - TIM3_ CH1 - - SPI1_ MISO SPI3_ MISO I2S3ext_ SD - - - - - - - EVEN TOUT PB5 - - TIM3_ CH2 - I2C1_ SMBA SPI1_ MOSI SPI3_ MOSI/ I2S3_SD - - CAN2_RX OTG_HS_ ULPI_D7 ETH_PPS _OUT FMC_ SDCKE1 DCMI_ D10 - EVEN TOUT PB6 - - TIM4_ CH1 - I2C1_ SCL - - USART1_ TX - CAN2_TX - - FMC_ SDNE1 DCMI_ D5 - EVEN TOUT PB7 - - TIM4_ CH2 - I2C1_ SDA - - USART1_ RX - - - - FMC_NL DCMI_ VSYNC - EVEN TOUT PB8 - - TIM4_ CH3 TIM10_ CH1 I2C1_ SCL - - - - CAN1_RX - ETH_MII_ TXD3 SDIO_D4 DCMI_ D6 LCD_B6 EVEN TOUT PB9 - - TIM4_ CH4 TIM11_ CH1 I2C1_ SDA SPI2_ NSS/I2 S2_WS - - - CAN1_TX - - SDIO_D5 DCMI_ D7 LCD_B7 EVEN TOUT PB10 - TIM2_ CH3 - - I2C2_ SCL SPI2_ SCK/I2 S2_CK - USART3_ TX - - OTG_HS_ ULPI_D3 ETH_MII_ RX_ER - - LCD_G4 EVEN TOUT Port Port A DocID024030 Rev 10 Port B AF8 AF9 AF10 USART6/ CAN1/2/ OTG2_HS UART4/5/7 TIM12/13/14 /OTG1_ /8 /LCD FS STM32F427xx STM32F429xx AF0 Pinouts and pin description 76/239 Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART1/ 2/3 ETH FMC/SDIO /OTG2_FS DCMI LCD SYS PB11 - TIM2_ CH4 - - I2C2_ SDA - - USART3_ RX - - OTG_HS_ ULPI_D4 ETH_MII_ TX_EN/ ETH_RMII _TX_EN - - LCD_G5 EVEN TOUT PB12 - TIM1_ BKIN - - I2C2_ SMBA SPI2_ NSS/I2 S2_WS - USART3_ CK - CAN2_RX OTG_HS_ ULPI_D5 ETH_MII_ TXD0/ETH _RMII_ TXD0 OTG_HS_ ID - - EVEN TOUT PB13 - TIM1_ CH1N - - - SPI2_ SCK/I2 S2_CK - USART3_ CTS - CAN2_TX OTG_HS_ ULPI_D6 ETH_MII_ TXD1/ETH _RMII_TX D1 - - - EVEN TOUT PB14 - TIM1_ CH2N - TIM8_ CH2N - SPI2_ MISO I2S2ext_ SD USART3_ RTS - TIM12_CH1 - - OTG_HS_ DM - - EVEN TOUT PB15 RTC_ REFIN TIM1_ CH3N - TIM8_ CH3N - SPI2_ MOSI/I2 S2_SD - - - TIM12_CH2 - - OTG_HS_ DP - - EVEN TOUT PC0 - - - - - - - - - - OTG_HS_ ULPI_STP - FMC_SDN WE - - EVEN TOUT PC1 - - - - - - - - - - - ETH_MDC - - - EVEN TOUT PC2 - - - - - SPI2_ MISO I2S2ext_ SD - - - OTG_HS_ ULPI_DIR ETH_MII_ TXD2 FMC_ SDNE0 - - EVEN TOUT PC3 - - - - - SPI2_ MOSI/I2 S2_SD - - - - OTG_HS_ ULPI_NXT ETH_MII_ TX_CLK FMC_ SDCKE0 - - EVEN TOUT PC4 - - - - - - - - - - - ETH_MII_ RXD0/ETH _RMII_ RXD0 - - - EVEN TOUT PC5 - - - - - - - - - - - ETH_MII_ RXD1/ETH _RMII_ RXD1 - - - EVEN TOUT PC6 - - TIM3_ CH1 TIM8_ CH1 - I2S2_ MCK - - USART6_ TX - - - SDIO_D6 DCMI_ D0 LCD_ HSYNC EVEN TOUT PC7 - - TIM3_ CH2 TIM8_ CH2 - - I2S3_ MCK - USART6_ RX - - - SDIO_D7 DCMI_ D1 LCD_G6 EVEN TOUT Port Port B DocID024030 Rev 10 Port C AF8 AF9 AF10 USART6/ CAN1/2/ OTG2_HS UART4/5/7 TIM12/13/14 /OTG1_ /8 /LCD FS 77/239 Pinouts and pin description AF0 STM32F427xx STM32F429xx Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 Port C DocID024030 Rev 10 Port D AF9 SYS TIM1/2 TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART1/ 2/3 PC8 - - TIM3_ CH3 TIM8_ CH3 - - - - USART6_ CK - PC9 MCO2 - TIM3_ CH4 TIM8_ CH4 I2C3_ SDA I2S_ CKIN - - - PC10 - - - - - - SPI3_ SCK/I2S 3_CK PC11 - - - - - I2S3ext _SD PC12 - - - - - PC13 - - - - PC14 - - - PC15 - - PD0 - PD1 AF10 AF12 AF13 AF14 AF15 ETH FMC/SDIO /OTG2_FS DCMI LCD SYS - - SDIO_D0 DCMI_ D2 - EVEN TOUT - - - SDIO_D1 DCMI_ D3 - EVEN TOUT USART3_ UART4_TX TX - - - SDIO_D2 DCMI_ D8 LCD_R2 EVEN TOUT SPI3_ MISO USART3_ UART4_RX RX - - - SDIO_D3 DCMI_ D4 - EVEN TOUT - SPI3_ MOSI/I2 S3_SD USART3_ UART5_TX CK - - - SDIO_CK DCMI_ D9 - EVEN TOUT - - - - - - - - - - - EVEN TOUT - - - - - - - - - - - - EVEN TOUT - - - - - - - - - - - - - EVEN TOUT - - - - - - - - CAN1_RX - - FMC_D2 - - EVEN TOUT - - - - - - - - - CAN1_TX - - FMC_D3 - - EVEN TOUT PD2 - - TIM3_ ETR - - - - - UART5_RX - - - SDIO_ CMD DCMI_ D11 - EVEN TOUT PD3 - - - - - SPI2_S CK/I 2S2_CK - USART2_ CTS - - - - FMC_CLK DCMI_ D5 LCD_G7 EVEN TOUT PD4 - - - - - - - USART2_ RTS - - - - FMC_NOE - - EVEN TOUT PD5 - - - - - - - USART2_ TX - - - - FMC_NWE - - EVEN TOUT PD6 - - - - - SPI3_ MOSI/I2 S3_SD SAI1_ SD_A USART2_ RX - - - - FMC_ NWAIT DCMI_ D10 LCD_B2 EVEN TOUT USART6/ CAN1/2/ OTG2_HS UART4/5/7 TIM12/13/14 /OTG1_ /8 /LCD FS STM32F427xx STM32F429xx AF11 Port AF8 Pinouts and pin description 78/239 Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 Port D DocID024030 Rev 10 Port E AF9 SYS TIM1/2 TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART1/ 2/3 PD7 - - - - - - - USART2_ CK - - PD8 - - - - - - - USART3_ TX - PD9 - - - - - - - USART3_ RX PD10 - - - - - - - PD11 - - - - - - PD12 - - TIM4_ CH1 - - PD13 - - TIM4_ CH2 - PD14 - - TIM4_ CH3 PD15 - - PE0 - PE1 AF10 AF12 AF13 AF14 AF15 ETH FMC/SDIO /OTG2_FS DCMI LCD SYS - - FMC_NE1/ FMC_ NCE2 - - EVEN TOUT - - - FMC_D13 - - EVEN TOUT - - - - FMC_D14 - - EVEN TOUT USART3_ CK - - - - FMC_D15 - LCD_B3 EVEN TOUT - USART3_ CTS - - - - FMC_A16 - - EVEN TOUT - - USART3_ RTS - - - - FMC_A17 - - EVEN TOUT - - - - - - - - FMC_A18 - - EVEN TOUT - - - - - - - - - FMC_D0 - - EVEN TOUT TIM4_ CH4 - - - - - - - - - FMC_D1 - - EVEN TOUT - TIM4_ ETR - - - - - UART8_Rx - - - FMC_ NBL0 DCMI_ D2 - EVEN TOUT - - - - - - - - UART8_Tx - - - FMC_ NBL1 DCMI_ D3 - EVEN TOUT PE2 TRAC ECLK - - - - SPI4_ SCK SAI1_ MCLK_A - - - - ETH_MII_ TXD3 FMC_A23 - - EVEN TOUT PE3 TRAC ED0 - - - - - SAI1_ SD_B - - - - - FMC_A19 - - EVEN TOUT PE4 TRAC ED1 - - - - SPI4_ NSS SAI1_ FS_A - - - - - FMC_A20 DCMI_ D4 LCD_B0 EVEN TOUT PE5 TRAC ED2 - - TIM9_ CH1 - SPI4_M ISO SAI1_ SCK_A - - - - - FMC_A21 DCMI_ D6 LCD_G0 EVEN TOUT PE6 TRAC ED3 - - TIM9_ CH2 - SPI4_ MOSI SAI1_ SD_A - - - - - FMC_A22 DCMI_ D7 LCD_G1 EVEN TOUT USART6/ CAN1/2/ OTG2_HS UART4/5/7 TIM12/13/14 /OTG1_ /8 /LCD FS 79/239 Pinouts and pin description AF11 Port AF8 STM32F427xx STM32F429xx Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART1/ 2/3 ETH FMC/SDIO /OTG2_FS DCMI LCD SYS PE7 - TIM1_ ETR - - - - - - UART7_Rx - - - FMC_D4 - - EVEN TOUT PE8 - TIM1_ CH1N - - - - - - UART7_Tx - - - FMC_D5 - - EVEN TOUT PE9 - TIM1_ CH1 - - - - - - - - - - FMC_D6 - - EVEN TOUT PE10 - TIM1_ CH2N - - - - - - - - - - FMC_D7 - - EVEN TOUT PE11 - TIM1_ CH2 - - - SPI4_ NSS - - - - - - FMC_D8 - LCD_G3 EVEN TOUT PE12 - TIM1_ CH3N - - - SPI4_ SCK - - - - - - FMC_D9 - LCD_B4 EVEN TOUT PE13 - TIM1_ CH3 - - - SPI4_ MISO - - - - - - FMC_D10 - LCD_DE EVEN TOUT PE14 - TIM1_ CH4 - - - SPI4_ MOSI - - - - - - FMC_D11 - LCD_ CLK EVEN TOUT PE15 - TIM1_ BKIN - - - - - - - - - FMC_D12 - LCD_R7 EVEN TOUT PF0 - - - - I2C2_ SDA - - - - - - - FMC_A0 - - EVEN TOUT PF1 - I2C2_ SCL - - - - - - - FMC_A1 - - EVEN TOUT PF2 - - - - I2C2_ SMBA - - - - - - - FMC_A2 - - EVEN TOUT PF3 - - - - - - - - - - - FMC_A3 - - EVEN TOUT PF4 - - - - - - - - - - - FMC_A4 - - EVEN TOUT PF5 - - - - - - - - - - - FMC_A5 - - EVEN TOUT PF6 - - - TIM10_ CH1 - SPI5_ NSS SAI1_ SD_B - UART7_Rx - - - FMC_ NIORD - - EVEN TOUT PF7 - - - TIM11_ CH1 - SPI5_ SCK SAI1_ MCLK_B - UART7_Tx - - - FMC_ NREG - - EVEN TOUT Port Port E AF8 AF9 AF10 USART6/ CAN1/2/ OTG2_HS UART4/5/7 TIM12/13/14 /OTG1_ /8 /LCD FS DocID024030 Rev 10 Port F STM32F427xx STM32F429xx AF0 Pinouts and pin description 80/239 Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART1/ 2/3 ETH FMC/SDIO /OTG2_FS DCMI LCD SYS PF8 - - - - - SPI5_ MISO SAI1_ SCK_B - - TIM13_CH1 - - FMC_ NIOWR - - EVEN TOUT PF9 - - - - - SPI5_ MOSI SAI1_ FS_B - - TIM14_CH1 - - FMC_CD - - EVEN TOUT PF10 - - - - - - - - - - - - FMC_INTR DCMI_ D11 LCD_DE EVEN TOUT PF11 - - - - - SPI5_ MOSI - - - - - - FMC_ SDNRAS DCMI_ D12 - EVEN TOUT PF12 - - - - - - - - - - - - FMC_A6 - - EVEN TOUT PF13 - - - - - - - - - - - - FMC_A7 - - EVEN TOUT PF14 - - - - - - - - - - - - FMC_A8 - - EVEN TOUT PF15 - - - - - - - - - - - - FMC_A9 - - EVEN TOUT PG0 - - - - - - - - - - - - FMC_A10 - - EVEN TOUT PG1 - - - - - - - - - - - - FMC_A11 - - EVEN TOUT PG2 - - - - - - - - - - - - FMC_A12 - - EVEN TOUT PG3 - - - - - - - - - - - - FMC_A13 - - EVEN TOUT PG4 - - - - - - - - - - - - FMC_A14/ FMC_BA0 - - EVEN TOUT PG5 - - - - - - - - - - - - FMC_A15/ FMC_BA1 - - EVEN TOUT PG6 - - - - - - - - - - - - FMC_INT2 DCMI_ D12 LCD_R7 EVEN TOUT PG7 - - - - - - - - USART6_ CK - - - FMC_INT3 DCMI_ D13 LCD_ CLK EVEN TOUT PG8 - - - - - SPI6_ NSS - - USART6_ RTS - - ETH_PPS _OUT FMC_SDC LK - - EVEN TOUT Port F DocID024030 Rev 10 Port G AF9 AF10 USART6/ CAN1/2/ OTG2_HS UART4/5/7 TIM12/13/14 /OTG1_ /8 /LCD FS 81/239 Pinouts and pin description AF11 Port AF8 STM32F427xx STM32F429xx Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART1/ 2/3 ETH FMC/SDIO /OTG2_FS DCMI LCD SYS PG9 - - - - - - - - USART6_ RX - - - FMC_NE2/ FMC_ NCE3 DCMI_ VSYNC - EVEN TOUT PG10 - - - - - - - - - LCD_G3 - - FMC_ NCE4_1/ FMC_NE3 DCMI_ D2 LCD_B2 EVEN TOUT PG11 - - - - - - - - - - - ETH_MII_ TX_EN/ ETH_RMII _TX_EN FMC_ NCE4_2 DCMI_ D3 LCD_B3 EVEN TOUT PG12 - - - - - SPI6_ MISO - - USART6_ RTS LCD_B4 - - FMC_NE4 - LCD_B1 EVEN TOUT PG13 - - - - - SPI6_ SCK - - USART6_ CTS - - ETH_MII_ TXD0/ ETH_RMII _TXD0 FMC_A24 - - EVEN TOUT PG14 - - - - - SPI6_ MOSI - - USART6_ TX - - ETH_MII_ TXD1/ ETH_RMII _TXD1 FMC_A25 - - EVEN TOUT PG15 - - - - - - - - USART6_ CTS - - - FMC_ SDNCAS DCMI_ D13 - EVEN TOUT PH0 - - - - - - - - - - - - - - - EVEN TOUT PH1 - - - - - - - - - - - - - - - EVEN TOUT PH2 - - - - - - - - - - - ETH_MII_ CRS FMC_ SDCKE0 - LCD_R0 EVEN TOUT PH3 - - - - - - - - - - - ETH_MII_ COL FMC_SDN E0 - LCD_R1 EVEN TOUT PH4 - - - - I2C2_ SCL - - - - - OTG_HS_ ULPI_NXT - - - - EVEN TOUT PH5 - - - - I2C2_ SDA SPI5_N SS - - - - - - FMC_SDN WE - - EVEN TOUT PH6 - - - - I2C2_ SMBA SPI5_ SCK - - - TIM12_CH1 - - FMC_ SDNE1 DCMI_ D8 - - Port Port G DocID024030 Rev 10 Port H AF8 AF9 AF10 USART6/ CAN1/2/ OTG2_HS UART4/5/7 TIM12/13/14 /OTG1_ /8 /LCD FS (1) STM32F427xx STM32F429xx AF0 Pinouts and pin description 82/239 Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 Port H AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART1/ 2/3 ETH FMC/SDIO /OTG2_FS DCMI LCD SYS PH7 - - - - I2C3_ SCL SPI5_ MISO - - - - - ETH_MII_ RXD3 FMC_ SDCKE1 DCMI_ D9 - - PH8 - - - - I2C3_ SDA - - - - - - - FMC_D16 DCMI_ HSYNC LCD_R2 EVEN TOUT PH9 - - - - I2C3_ SMBA - - - - TIM12_CH2 - - FMC_D17 DCMI_ D0 LCD_R3 EVEN TOUT PH10 - - TIM5_ CH1 - - - - - - - - - FMC_D18 DCMI_ D1 LCD_R4 EVEN TOUT PH11 - - TIM5_ CH2 - - - - - - - - - FMC_D19 DCMI_ D2 LCD_R5 EVEN TOUT PH12 - - TIM5_ CH3 - - - - - - - - - FMC_D20 DCMI_ D3 LCD_R6 EVEN TOUT PH13 - - - TIM8_ CH1N - - - - - CAN1_TX - - FMC_D21 - LCD_G2 EVEN TOUT PH14 - - - TIM8_ CH2N - - - - - - - - FMC_D22 DCMI_ D4 LCD_G3 EVEN TOUT PH15 - - - TIM8_ CH3N - - - - - - - - FMC_D23 DCMI_ D11 LCD_G4 EVEN TOUT PI0 - - TIM5_ CH4 - - SPI2_ NSS/I2 S2_WS - - - - - - FMC_D24 DCMI_ D13 LCD_G5 EVEN TOUT PI1 - - - - - SPI2_ SCK/I2 S2_CK - - - - - - FMC_D25 DCMI_ D8 LCD_G6 EVEN TOUT PI2 - - - TIM8_ CH4 - SPI2_ MISO I2S2ext_ SD - - - - - FMC_D26 DCMI_ D9 LCD_G7 EVEN TOUT PI3 - - - TIM8_ ETR - SPI2_M OSI/I2S 2_SD FMC_D27 DCMI_D 10 PI4 - - - TIM8_ BKIN - - - - - - - - FMC_ NBL2 DCMI_D 5 LCD_B4 EVEN TOUT PI5 - - - TIM8_ CH1 - - - - - - - - FMC_ NBL3 DCMI_ VSYNC LCD_B5 EVEN TOUT PI6 - - - TIM8_ CH2 - - - - - - - - FMC_D28 DCMI_ D6 LCD_B6 EVEN TOUT DocID024030 Rev 10 Port I AF9 AF10 USART6/ CAN1/2/ OTG2_HS UART4/5/7 TIM12/13/14 /OTG1_ /8 /LCD FS EVEN TOUT 83/239 Pinouts and pin description AF11 Port AF8 STM32F427xx STM32F429xx Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 Port I AF9 SYS TIM1/2 TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART1/ 2/3 PI7 - - - TIM8_ CH3 - - - - - - PI8 - - - - - - - - - PI9 - - - - - - - - PI10 - - - - - - - PI11 - - - - - - PI12 - - - - - PI13 - - - - PI14 - - - PI15 - - PJ0 - PJ1 AF10 AF12 AF13 AF14 AF15 ETH FMC/SDIO /OTG2_FS DCMI LCD SYS - - FMC_D29 DCMI_ D7 LCD_B7 EVEN TOUT - - - - - - EVEN TOUT - CAN1_RX - - FMC_D30 - LCD_ VSYNC EVEN TOUT - - - - ETH_MII_ RX_ER FMC_D31 - LCD_ HSYNC EVEN TOUT - - - - OTG_HS_ ULPI_DIR - - - - EVEN TOUT - - - - - - - - - LCD_ HSYNC EVEN TOUT - - - - - - - - - - LCD_ VSYNC EVEN TOUT - - - - - - - - - - - LCD_ CLK EVEN TOUT - - - - - - - - - - - - LCD_R0 EVEN TOUT - - - - - - - - - - - - - LCD_R1 EVEN TOUT - - - - - - - - - - - - - - LCD_R2 EVEN TOUT PJ2 - - - - - - - - - - - - - - LCD_R3 EVEN TOUT PJ3 - - - - - - - - - - - - - - LCD_R4 EVEN TOUT PJ4 - - - - - - - - - - - - - - LCD_R5 EVEN TOUT PJ5 - - - - - - - - - - - - - - LCD_R6 EVEN TOUT PJ6 - - - - - - - - - - - - - - LCD_R7 EVEN TOUT PJ7 - - - - - - - - - - - - - - LCD_G0 EVEN TOUT USART6/ CAN1/2/ OTG2_HS UART4/5/7 TIM12/13/14 /OTG1_ /8 /LCD FS DocID024030 Rev 10 Port J STM32F427xx STM32F429xx AF11 Port AF8 Pinouts and pin description 84/239 Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF9 SYS TIM1/2 TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART1/ 2/3 PJ8 - - - - - - - - - - PJ9 - - - - - - - - - PJ10 - - - - - - - - PJ11 - - - - - - - PJ12 - - - - - - PJ13 - - - - - PJ14 - - - - PJ15 - - - PK0 - - PK1 - PK2 AF10 AF12 AF13 AF14 AF15 ETH FMC/SDIO /OTG2_FS DCMI LCD SYS - - - - LCD_G1 EVEN TOUT - - - - - LCD_G2 EVEN TOUT - - - - - - LCD_G3 EVEN TOUT - - - - - - - LCD_G4 EVEN TOUT - - - - - - - - LCD_B0 EVEN TOUT - - - - - - - - - LCD_B1 EVEN TOUT - - - - - - - - - - LCD_B2 EVEN TOUT - - - - - - - - - - - LCD_B3 EVEN TOUT - - - - - - - - - - - - LCD_G5 EVEN TOUT - - - - - - - - - - - - - LCD_G6 EVEN TOUT - - - - - - - - - - - - - - LCD_G7 EVEN TOUT PK3 - - - - - - - - - - - - - - LCD_B4 EVEN TOUT PK4 - - - - - - - - - - - - - - LCD_B5 EVEN TOUT PK5 - - - - - - - - - - - - - - LCD_B6 EVEN TOUT PK6 - - - - - - - - - - - - - - LCD_B7 EVEN TOUT PK7 - - - - - - - - - - - - - - LCD_DE EVEN TOUT USART6/ CAN1/2/ OTG2_HS UART4/5/7 TIM12/13/14 /OTG1_ /8 /LCD FS Port J DocID024030 Rev 10 Port K 85/239 1. The DCMI_VSYNC alternate function on PG9 is only available on silicon revision 3. Pinouts and pin description AF11 Port AF8 STM32F427xx STM32F429xx Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) Memory mapping 5 STM32F427xx STM32F429xx Memory mapping The memory map is shown in Figure 19. Figure 19. Memory map [)))))))) 5HVHUYHG [([)))))))) &RUWH[0LQWHUQDO SHULSKHUDOV [([())))) $+% [['))))))) 5HVHUYHG [&[))))))) [%)) $+% 0E\WH %ORFN &RUWH[0 ,QWHUQDO SHULSKHUDOV 5HVHUYHG [ [[))))))) [)))) [( ['))))))) 0E\WH %ORFN )0& [' [&))))))) $+% 0E\WH %ORFN )0& [$ [))))))) [ [))))))) 0E\WH %ORFN )0&EDQNWR EDQN [ 5HVHUYHG [&[)))) [%)) 0E\WH %ORFN )0&EDQNWR EDQN [ [))))))) $3% 0E\WH %ORFN 3HULSKHUDOV [ [))))))) 0E\WH %ORFN 65$0 [ [))))))) 0E\WH %ORFN 65$0 [ 5HVHUYHG 65$0 .%DOLDVHG %\ELWEDQGLQJ 65$0 .%DOLDVHG %\ELWEDQGLQJ 65$0 .%DOLDVHG %\ELWEDQGLQJ [[))))))) 5HVHUYHG [)))&)[))))))) 2SWLRQ%\WHV [)))&[)))& 5HVHUYHG 6\VWHPPHPRU\ 5HVHUYHG 2SWLRQE\WHV [)))$[)))))) [)))[)))$) [))(&)[))()))) [))(&[))(& 5HVHUYHG [&[)))) [ [[)))) [))) [[%))) 5HVHUYHG [[))(%))) &&0GDWD5$0 .%GDWD65$0 5HVHUYHG [[)))) [[))))))) )ODVKPHPRU\ [[))))) 5HVHUYHG $OLDVHGWR)ODVKV\VWHP PHPRU\RU65$0GHSHQGLQJ RQWKH%227SLQV 86/239 [[)))) $3% [[)))))) [ [[))))) DocID024030 Rev 10 069 STM32F427xx STM32F429xx Memory mapping Table 13. STM32F427xx and STM32F429xx register boundary addresses Bus Cortex-M4 AHB3 AHB2 Boundary address Peripheral 0xE00F FFFF - 0xFFFF FFFF Reserved 0xE000 0000 - 0xE00F FFFF Cortex-M4 internal peripherals 0xD000 0000 - 0xDFFF FFFF FMC bank 6 0xC000 0000 - 0xCFFF FFFF FMC bank 5 0xA000 1000 - 0xBFFF FFFF Reserved 0xA000 0000- 0xA000 0FFF FMC control register 0x9000 0000 - 0x9FFF FFFF FMC bank 4 0x8000 0000 - 0x8FFF FFFF FMC bank 3 0x7000 0000 - 0x7FFF FFFF FMC bank 2 0x6000 0000 - 0x6FFF FFFF FMC bank 1 0x5006 0C00- 0x5FFF FFFF Reserved 0x5006 0800 - 0X5006 0BFF RNG 0x5005 0400 - X5006 07FF Reserved 0x5005 0000 - 0X5005 03FF DCMI 0x5004 0000- 0x5004 FFFF Reserved 0x5000 0000 - 0X5003 FFFF USB OTG FS DocID024030 Rev 10 87/239 90 Memory mapping STM32F427xx STM32F429xx Table 13. STM32F427xx and STM32F429xx register boundary addresses (continued) Bus Boundary address Peripheral 0x4008 0000- 0x4FFF FFFF Reserved 0x4004 0000 - 0x4007 FFFF USB OTG HS 0x4002 BC00- 0x4003 FFFF Reserved 0x4002 B000 - 0x4002 BBFF DMA2D 0x4002 9400 - 0x4002 AFFF Reserved 0x4002 9000 - 0x4002 93FF 0x4002 8C00 - 0x4002 8FFF 0x4002 8800 - 0x4002 8BFF ETHERNET MAC 0x4002 8400 - 0x4002 87FF 0x4002 8000 - 0x4002 83FF AHB1 88/239 0x4002 6800 - 0x4002 7FFF Reserved 0x4002 6400 - 0x4002 67FF DMA2 0x4002 6000 - 0x4002 63FF DMA1 0X4002 5000 - 0X4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF BKPSRAM 0x4002 3C00 - 0x4002 3FFF Flash interface register 0x4002 3800 - 0x4002 3BFF RCC 0X4002 3400 - 0X4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2C00 - 0x4002 2FFF Reserved 0x4002 2800 - 0x4002 2BFF GPIOK 0x4002 2400 - 0x4002 27FF GPIOJ 0x4002 2000 - 0x4002 23FF GPIOI 0x4002 1C00 - 0x4002 1FFF GPIOH 0x4002 1800 - 0x4002 1BFF GPIOG 0x4002 1400 - 0x4002 17FF GPIOF 0x4002 1000 - 0x4002 13FF GPIOE 0X4002 0C00 - 0x4002 0FFF GPIOD 0x4002 0800 - 0x4002 0BFF GPIOC 0x4002 0400 - 0x4002 07FF GPIOB 0x4002 0000 - 0x4002 03FF GPIOA DocID024030 Rev 10 STM32F427xx STM32F429xx Memory mapping Table 13. STM32F427xx and STM32F429xx register boundary addresses (continued) Bus APB2 Boundary address Peripheral 0x4001 6C00- 0x4001 FFFF Reserved 0x4001 6800 - 0x4001 6BFF LCD-TFT 0x4001 5C00 - 0x4001 67FF Reserved 0x4001 5800 - 0x4001 5BFF SAI1 0x4001 5400 - 0x4001 57FF SPI6 0x4001 5000 - 0x4001 53FF SPI5 0x4001 5400 - 0x4001 57FF SPI6 0x4001 5000 - 0x4001 53FF SPI5 0x4001 4C00 - 0x4001 4FFF Reserved 0x4001 4800 - 0x4001 4BFF TIM11 0x4001 4400 - 0x4001 47FF TIM10 0x4001 4000 - 0x4001 43FF TIM9 0x4001 3C00 - 0x4001 3FFF EXTI 0x4001 3800 - 0x4001 3BFF SYSCFG 0x4001 3400 - 0x4001 37FF SPI4 0x4001 3000 - 0x4001 33FF SPI1 0x4001 2C00 - 0x4001 2FFF SDIO 0x4001 2400 - 0x4001 2BFF Reserved 0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3 0x4001 1800 - 0x4001 1FFF Reserved 0x4001 1400 - 0x4001 17FF USART6 0x4001 1000 - 0x4001 13FF USART1 0x4001 0800 - 0x4001 0FFF Reserved 0x4001 0400 - 0x4001 07FF TIM8 0x4001 0000 - 0x4001 03FF TIM1 DocID024030 Rev 10 89/239 90 Memory mapping STM32F427xx STM32F429xx Table 13. STM32F427xx and STM32F429xx register boundary addresses (continued) Bus APB1 90/239 Boundary address Peripheral 0x4000 8000- 0x4000 FFFF Reserved 0x4000 7C00 - 0x4000 7FFF UART8 0x4000 7800 - 0x4000 7BFF UART7 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PWR 0x4000 6C00 - 0x4000 6FFF Reserved 0x4000 6800 - 0x4000 6BFF CAN2 0x4000 6400 - 0x4000 67FF CAN1 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF I2C3 0x4000 5800 - 0x4000 5BFF I2C2 0x4000 5400 - 0x4000 57FF I2C1 0x4000 5000 - 0x4000 53FF UART5 0x4000 4C00 - 0x4000 4FFF UART4 0x4000 4800 - 0x4000 4BFF USART3 0x4000 4400 - 0x4000 47FF USART2 0x4000 4000 - 0x4000 43FF I2S3ext 0x4000 3C00 - 0x4000 3FFF SPI3 / I2S3 0x4000 3800 - 0x4000 3BFF SPI2 / I2S2 0x4000 3400 - 0x4000 37FF I2S2ext 0x4000 3000 - 0x4000 33FF IWDG 0x4000 2C00 - 0x4000 2FFF WWDG 0x4000 2800 - 0x4000 2BFF RTC & BKP Registers 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIM14 0x4000 1C00 - 0x4000 1FFF TIM13 0x4000 1800 - 0x4000 1BFF TIM12 0x4000 1400 - 0x4000 17FF TIM7 0x4000 1000 - 0x4000 13FF TIM6 0x4000 0C00 - 0x4000 0FFF TIM5 0x4000 0800 - 0x4000 0BFF TIM4 0x4000 0400 - 0x4000 07FF TIM3 0x4000 0000 - 0x4000 03FF TIM2 DocID024030 Rev 10 STM32F427xx STM32F429xx 6 6.1 Electrical characteristics Electrical characteristics Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 1.7 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 20. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 21. Figure 20. Pin loading conditions Figure 21. Pin input voltage -#5 PIN -#5 PIN # P& 6). -36 DocID024030 Rev 10 -36 91/239 198 Electrical characteristics 6.1.6 STM32F427xx STM32F429xx Power supply scheme Figure 22. Power supply scheme 9%$7 9%$7 WR9 *3,2V ,1 9&$3B 9&$3B i) 9'' iQ) i) 966 /HYHOVKLIWHU 287 9'' %DFNXSFLUFXLWU\ 26&.57& :DNHXSORJLF %DFNXSUHJLVWHUV EDFNXS5$0 3RZHU VZLWFK ,2 /RJLF .HUQHOORJLF &38GLJLWDO 5$0 9ROWDJH UHJXODWRU )ODVKPHPRU\ %<3$66B5(* 3'5B21 9'' 9''$ 95() Q) ) 5HVHW FRQWUROOHU Q) ) 95() 95() $'& $QDORJ 5&V 3// 966$ 069 1. To connect BYPASS_REG and PDR_ON pins, refer to Section 3.17: Power supply supervisor and Section 3.18: Voltage regulator 2. The two 2.2 F ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 3. The 4.7 F ceramic capacitor must be connected to one of the VDD pin. 4. VDDA=VDD and VSSA=VSS. Caution: 92/239 Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device. DocID024030 Rev 10 STM32F427xx STM32F429xx 6.1.7 Electrical characteristics Current consumption measurement Figure 23. Current consumption measurement scheme ,''B9%$7 9%$7 ,'' 9'' 9''$ DL 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics, Table 15: Current characteristics, and Table 16: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand. Table 14. Voltage characteristics Symbol Ratings Min Max VDD-VSS External main supply voltage (including VDDA, VDD and VBAT)(1) - 0.3 4.0 Input voltage on FT pins(2) VSS - 0.3 VDD+4.0 Input voltage on TTa pins VSS - 0.3 4.0 Input voltage on any other pin VSS - 0.3 4.0 VSS 9.0 Variations between different VDD power pins - 50 Variations between all the different ground pins including VREF- - 50 VIN Input voltage on BOOT0 pin |VDDx| |VSSX -VSS| VESD(HBM) Electrostatic discharge voltage (human body model) Unit V mV see Section 6.3.15: Absolute maximum ratings (electrical sensitivity) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum value must always be respected. Refer to Table 15 for the values of the maximum allowed injected current. DocID024030 Rev 10 93/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 15. Current characteristics Symbol Ratings Max. IVDD Total current into sum of all VDD_x power lines (source)(1) IVSS (1) Total current out of sum of all VSS_x ground lines (sink) Maximum current into each VDD_x power line (source) IVSS Maximum current out of each VSS_x ground line (sink)(1) IIO IIO IINJ(PIN)(5) - 270 100 - 100 Output current sunk by any I/O and control pin 25 - 25 Output current sourced by any I/Os and control pin Total output current sunk by sum of all I/O and control pins (2) mA 120 Total output current sourced by sum of all I/Os and control pins(2) Injected current on FT pins IINJ(PIN) (3) 270 (1) IVDD Unit - 120 (4) - 5/+0 Injected current on NRST and BOOT0 pins (4) Injected current on TTa pins(5) 5 Total injected current (sum of all I/O and control pins)(6) 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. 3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.21: 12-bit ADC characteristics. 4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 5. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 14 for the values of the maximum allowed input voltage. 6. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 16. Thermal characteristics Symbol TSTG TJ 94/239 Ratings Storage temperature range Maximum junction temperature DocID024030 Rev 10 Value Unit - 65 to +150 C 125 C STM32F427xx STM32F429xx Electrical characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 17. General operating conditions Symbol Parameter Conditions(1) Power Scale 3 (VOS[1:0] bits in PWR_CR register = 0x01), Regulator ON, over-drive OFF fHCLK Internal AHB clock frequency - 120 - 144 - 168 - 168 - 180 - 42 Over-drive ON 0 - 45 Over-drive OFF 0 - 84 Over-drive ON 0 - 90 Standard operating voltage 1.7(2) - 3.6 Analog operating voltage (ADC limited to 1.2 M samples) 1.7(2) - 2.4 2.4 - 3.6 1.65 - 3.6 Power Scale 3 ((VOS[1:0] bits in PWR_CR register = 0x01), 120 MHz HCLK max frequency 1.08 1.14 1.20 Power Scale 2 ((VOS[1:0] bits in PWR_CR register = 0x10), 144 MHz HCLK max frequency with over-drive OFF or 168 MHz with over-drive ON 1.20 1.26 1.32 Analog operating voltage (ADC limited to 2.4 M samples) Must be the same potential as VDD(5) Backup operating voltage Regulator ON: 1.2 V internal voltage on VCAP_1/VCAP_2 pins V12 Regulator OFF: 1.2 V external voltage must be supplied from external regulator on VCAP_1/VCAP_2 pins(6) MHz V V Power Scale 1 ((VOS[1:0] bits in PWR_CR register = 0x11), 168 MHz HCLK max frequency with over-drive OFF or 180 MHz with over-drive ON 1.26 1.32 1.40 Max frequency 120 MHz 1.10 1.14 1.20 Max frequency 144 MHz 1.20 1.26 1.32 Max frequency 168 MHz 1.26 1.32 1.38 DocID024030 Rev 10 Unit 0 0 Internal APB2 clock frequency VBAT 0 Over-drive OFF fPCLK2 (3)(4) Max 0 Internal APB1 clock frequency VDDA Typ OverPower Scale 1 (VOS[1:0] bits drive OFF in PWR_CR register= 0x11), OverRegulator ON drive ON fPCLK1 VDD OverPower Scale 2 (VOS[1:0] bits drive OFF in PWR_CR register = 0x10), OverRegulator ON drive ON Min 95/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 17. General operating conditions (continued) Symbol Input voltage on RST and FT pins(7) VIN Conditions(1) Parameter Min Typ Max 2 V VDD 3.6 V - 0.3 - 5.5 VDD 2 V - 0.3 - 5.2 - 0.3 - VDDA+ 0.3 0 - 9 LQFP100 - - 465 WLCSP143 - - 641 LQFP144 - - 500 UFBGA169 - - 385 LQFP176 - - 526 UFBGA176 - - 513 LQFP208 - - 1053 TFBGA216 - - 690 Input voltage on TTa pins Input voltage on BOOT0 pin PD TA TJ Power dissipation at TA = 85 C for suffix 6 or TA = 105 C for suffix 7(8) - 40 85 - 40 105 - 40 105 - 40 125 6 suffix version - 40 105 7 suffix version - 40 125 Ambient temperature for 6 suffix Maximum power dissipation version Low power dissipation(9) Ambient temperature for 7 suffix Maximum power dissipation version Low power dissipation(9) Junction temperature range Unit V mW C C C 1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V. 2. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). 3. When the ADC is used, refer to Table 74: ADC characteristics. 4. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V. 5. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and power-down operation. 6. The over-drive mode is not supported when the internal regulator is OFF. 7. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled 8. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. 9. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax. 96/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Table 18. Limitations depending on the operating power supply range Maximum Flash Maximum HCLK memory access frequency vs Flash frequency with memory wait states no wait states (1)(2) (fFlashmax) Possible Flash memory operations Operating power supply range ADC operation VDD =1.7 to 2.1 V(3) Conversion time up to 1.2 Msps 20 MHz(4) 168 MHz with 8 wait No I/O states and over-drive compensation OFF 8-bit erase and program operations only VDD = 2.1 to 2.4 V Conversion time up to 1.2 Msps 22 MHz 180 MHz with 8 wait No I/O states and over-drive compensation ON 16-bit erase and program operations VDD = 2.4 to 2.7 V Conversion time up to 2.4 Msps 24 MHz 180 MHz with 7 wait I/O compensation states and over-drive works ON 16-bit erase and program operations VDD = 2.7 to 3.6 V(5) Conversion time up to 2.4 Msps 30 MHz 180 MHz with 5 wait I/O compensation states and over-drive works ON 32-bit erase and program operations I/O operation 1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required. 2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state program execution. 3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). 4. Prefetch is not available. 5. The voltage range for USB full speed PHYs can drop down to 2.7 V. However the electrical characteristics of D- and D+ pins will be degraded between 2.7 and 3 V. 6.3.2 VCAP1/VCAP2 external capacitor Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to the VCAP1/VCAP2 pins. CEXT is specified in Table 19. Figure 24. External capacitor CEXT & (65 5/HDN 069 1. Legend: ESR is the equivalent series resistance. Table 19. VCAP1/VCAP2 operating conditions(1) Symbol Parameter Conditions CEXT Capacitance of external capacitor 2.2 F ESR ESR of external capacitor <2 1. When bypassing the voltage regulator, the two 2.2 F VCAP capacitors are not required and should be replaced by two 100 nF decoupling capacitors. DocID024030 Rev 10 97/239 198 Electrical characteristics 6.3.3 STM32F427xx STM32F429xx Operating conditions at power-up / power-down (regulator ON) Subject to general operating conditions for TA. Table 20. Operating conditions at power-up / power-down (regulator ON) Symbol tVDD 6.3.4 Parameter Min Max VDD rise time rate 20 VDD fall time rate 20 Unit s/V Operating conditions at power-up / power-down (regulator OFF) Subject to general operating conditions for TA. Table 21. Operating conditions at power-up / power-down (regulator OFF)(1) Symbol tVDD tVCAP Parameter Conditions Min Max VDD rise time rate Power-up 20 VDD fall time rate Power-down 20 VCAP_1 and VCAP_2 rise time rate Power-up 20 VCAP_1 and VCAP_2 fall time rate Power-down 20 1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below 1.08 V. 98/239 DocID024030 Rev 10 Unit s/V STM32F427xx STM32F429xx 6.3.5 Electrical characteristics Reset and power control block characteristics The parameters given in Table 22 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 17. Table 22. reset and power control block characteristics Symbol Parameter Conditions Programmable voltage detector level selection VPVD Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.09 2.14 2.19 V PLS[2:0]=000 (falling edge) 1.98 2.04 2.08 V PLS[2:0]=001 (rising edge) 2.23 2.30 2.37 V PLS[2:0]=001 (falling edge) 2.13 2.19 2.25 V PLS[2:0]=010 (rising edge) 2.39 2.45 2.51 V PLS[2:0]=010 (falling edge) 2.29 2.35 2.39 V PLS[2:0]=011 (rising edge) 2.54 2.60 2.65 V PLS[2:0]=011 (falling edge) 2.44 2.51 2.56 V PLS[2:0]=100 (rising edge) 2.70 2.76 2.82 V PLS[2:0]=100 (falling edge) 2.59 2.66 2.71 V PLS[2:0]=101 (rising edge) 2.86 2.93 2.99 V PLS[2:0]=101 (falling edge) 2.65 2.84 2.92 V PLS[2:0]=110 (rising edge) 2.96 3.03 3.10 V PLS[2:0]=110 (falling edge) 2.85 2.93 2.99 V PLS[2:0]=111 (rising edge) 3.07 3.14 3.21 V PLS[2:0]=111 (falling edge) 2.95 3.03 3.09 V - 100 - mV Falling edge 1.60 1.68 1.76 V Rising edge 1.64 1.72 1.80 V - 40 - mV VPVDhyst(1) PVD hysteresis VPOR/PDR VPDRhyst (1) Power-on/power-down reset threshold PDR hysteresis VBOR1 Brownout level 1 threshold Falling edge 2.13 2.19 2.24 V Rising edge 2.23 2.29 2.33 V VBOR2 Brownout level 2 threshold Falling edge 2.44 2.50 2.56 V Rising edge 2.53 2.59 2.63 V VBOR3 Brownout level 3 threshold Falling edge 2.75 2.83 2.88 V Rising edge 2.85 2.92 2.97 V VBORhyst(1) BOR hysteresis - 100 - mV TRSTTEMPO POR reset temporization 0.5 1.5 3.0 ms (1)(2) DocID024030 Rev 10 99/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 22. reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit IRUSH(1) InRush current on voltage regulator poweron (POR or wakeup from Standby) - 160 200 mA ERUSH(1) InRush energy on voltage regulator power- VDD = 1.7 V, TA = 105 C, IRUSH = 171 mA for 31 s on (POR or wakeup from Standby) - - 5.4 C 1. Guaranteed by design. 2. The reset temporization is measured from the power-on (POR reset or wakeup from VBAT) to the instant when first instruction is read by the user application code. 6.3.6 Over-drive switching characteristics When the over-drive mode switches from enabled to disabled or disabled to enabled, the system clock is stalled during the internal voltage set-up. The over-drive switching characteristics are given in Table 23. They are sbject to general operating conditions for TA. Table 23. Over-drive switching characteristics(1) Symbol Tod_swen Parameter Conditions Min Typ Max HSI - 45 - 45 - 100 - 40 - - 20 - 20 - 80 - 15 - HSE max for 4 MHz Over_drive switch and min for 26 MHz enable time External HSE 50 MHz HSI Tod_swdis HSE max for 4 MHz Over_drive switch and min for 26 MHz. disable time External HSE 50 MHz 1. Guaranteed by design. 100/239 DocID024030 Rev 10 Unit s STM32F427xx STM32F429xx 6.3.7 Electrical characteristics Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 23: Current consumption measurement scheme. All the run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code. Typical and maximum current consumption The MCU is placed under the following conditions: * All I/O pins are in input mode with a static value at VDD or VSS (no load). * All peripherals are disabled except if it is explicitly mentioned. * The Flash memory access time is adjusted both to fHCLK frequency and VDD range (see Table 18: Limitations depending on the operating power supply range). * Regulator ON * The voltage scaling and over-drive mode are adjusted to fHCLK frequency as follows: - Scale 3 for fHCLK 120 MHz - Scale 2 for 120 MHz < fHCLK 144 MHz - Scale 1 for 144 MHz < fHCLK 180 MHz. The over-drive is only ON at 180 MHz. * The system clock is HCLK, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2. * External clock frequency is 4 MHz and PLL is ON when fHCLK is higher than 25 MHz. * The maximum values are obtained for VDD = 3.6 V and a maximum ambient temperature (TA), and the typical values for TA= 25 C and VDD = 3.3 V unless otherwise specified. DocID024030 Rev 10 101/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 24. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled except prefetch) or RAM(1) Max(2) Symbol Parameter Conditions All Peripherals enabled(3)(4) IDD Supply current in RUN mode All Peripherals disabled(3) fHCLK (MHz) Typ 180 TA = 25 C TA = 85 C TA = 105 C 98 104(5) 123 141(5) 168 89 98(5) 116 133(5) 150 75 84 100 115 144 72 81 96 112 120 54 58 72 85 90 43 45 56 66 60 29 30 52 62 30 16 20 34 46 25 13 16 30 43 16 11 13 27 39 8 5 9 23 36 4 4 8 21 34 2 2 7 20 33 180 44 47(5) 69 87(5) 168 41 45(5) 66 83(5) 150 36 39 57 73 144 33 37 56 72 120 25 29 43 56 90 20 23 41 53 60 14 16 34 45 30 8 12 26 39 25 7 10 24 37 16 7 9 22 35 8 3 7 21 34 4 3 6 20 33 2 2 6 20 33 Unit mA 1. Code and data processing running from SRAM1 using boot pins. 2. Guaranteed by characterization. 3. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. 5. Guaranteed by test in production. 102/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Table 25. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) Max(1) Symbol Parameter Conditions All Peripherals enabled(2)(3) IDD Supply current in RUN mode All Peripherals disabled(3) fHCLK (MHz) Typ 180 103 112 140 151 168 98 107 126 144 150 87 95 112 128 144 85 92 108 124 120 66 71 85 99 90 54 58 69 80 60 37 39 47 55 30 20 24 39 51 25 17 21 35 48 16 12 16 30 42 8 7 11 24 37 4 5 8 22 35 2 3 7 21 34 180 57 62 87 106 168 50 54 76 93 150 46 50 70 86 144 45 49 68 84 120 36 41 56 69 90 29 34 46 57 60 21 24 33 41 30 13 17 31 44 25 11 15 28 41 16 8 12 25 38 8 5 9 23 35 4 4 7 21 34 2 3 6.5 20 33 TA= 25 C Unit TA=85 C TA=105 C mA 1. Guaranteed by characterization unless otherwise specified. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. DocID024030 Rev 10 103/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 26. Typical and maximum current consumption in Sleep mode Max(1) Symbol Parameter Conditions fHCLK (MHz) Typ 180 All Peripherals enabled(2) IDD Supply current in Sleep mode All Peripherals disabled TA = 25 C TA = 85 C TA = 105 C 78 89(3) 110 130(3) 168 66 75(3) 93 110(3) 150 56 61 80 96 144 54 58 78 94 120 40 44 59 72 90 32 34 46 56 60 22 23 31 45 30 10 16 30 43 25 9 14 28 40 16 5 12 25 40 8 3 8 22 35 4 3 7 21 34 2 2 6.5 20 33 (3) 54 76(3) 180 21 26 168 16 20(3) 41 58(3) 150 14 17 36 52 144 13 16.5 35 51 120 10 14 28 41 90 8 13 26 37 60 6 9 24 37 30 5 8 22 35 25 3 7 21 34 16 3 7 21 34 8 2 6 20 33 4 2 6 20 33 2 2 6 20 33 Unit mA 1. Guaranteed by characterization unless otherwise specified. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. Based on characterization, tested in production. 104/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Table 27. Typical and maximum current consumptions in Stop mode Max(1) Typ Symbol Parameter Unit TA = 25 C TA = 25 C TA = TA = 85 C 105 C 0.40 1.50 14.00 25.00 0.35 1.50 14.00 25.00 0.29 1.10 10.00 18.00 0.23 1.10 10.00 18.00 Flash memory in Deep power down mode, main regulator in under-drive mode, all oscillators OFF, no independent watchdog 0.19 0.50 6.00 9.00 Flash memory in Deep power down mode, Low Power regulator in under-drive mode, all oscillators OFF, no independent watchdog 0.10 0.40 4.00 7.00 Flash memory in Stop mode, all Supply current in Stop oscillators OFF, no independent watchdog mode with voltage regulator in main Flash memory in Deep power regulator mode down mode, all oscillators OFF, no IDD_STOP_NM (normal mode) VDD = 3.6 V Conditions independent watchdog Flash memory in Stop mode, all Supply current in Stop oscillators OFF, no independent watchdog mode with voltage regulator in Low Power Flash memory in Deep power regulator mode down mode, all oscillators OFF, no independent watchdog Supply current in Stop mode with voltage regulator in main regulator and underIDD_STOP_UDM drive mode (under-drive Supply current in Stop mode) mode with voltage regulator in Low Power regulator and underdrive mode mA 1. Data based on characterization, tested in production. DocID024030 Rev 10 105/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 28. Typical and maximum current consumptions in Standby mode Typ(1) Symbol Parameter Backup SRAM OFF, lowSupply current speed oscillator (LSE) and RTC ON IDD_STBY in Standby mode Backup SRAM ON, RTC and LSE OFF Backup SRAM OFF, RTC and LSE OFF TA = 25 C TA = 25 C Conditions Backup SRAM ON, low-speed oscillator (LSE) and RTC ON Max(2) TA = 85 C TA = 105 C VDD = 1.7 V VDD= 2.4 V VDD = 3.3 V 2.80 3.00 3.60 7.00 19.00 36.00 2.30 2.60 3.10 6.00 16.00 31.00 Unit VDD = 3.6 V A 2.30 2.50 2.90 6.00(3) 18.00(3) 35.00(3) 1.70 1.90 2.20 5.00(3) 15.00(3) 30.00(3) 1. The typical current consumption values are given with PDR OFF (internal reset OFF). When the PDR is OFF (internal reset OFF), the typical current consumption is reduced by additional 1.2 A. 2. Based on characterization, not tested in production unless otherwise specified. 3. Based on characterization, tested in production. Table 29. Typical and maximum current consumptions in VBAT mode Max(2) Typ Symbol Parameter TA = 25 C Conditions(1) TA = 85 C VBAT = VBAT= VBAT = 1.7 V 2.4 V 3.3 V Backup SRAM ON, low-speed oscillator (LSE) and RTC ON Backup SRAM OFF, low-speed Backup oscillator (LSE) and RTC ON IDD_VBAT domain supply Backup SRAM ON, RTC and current LSE OFF Backup SRAM OFF, RTC and LSE OFF Unit VBAT = 3.6 V 1.28 1.40 1.62 6 11 0.66 0.76 0.97 3 5 0.70 0.72 0.74 5 10 0.10 0.10 0.10 2 4 A 1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values. 2. Guaranteed by characterization results. 106/239 TA = 105 C DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Figure 25. Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) )$$?6"!4 ! 6 6 6 6 6 6 6 6 6 # # # # # 4EMPERATURE -36 Figure 26. Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) )$$?6"!4 ! 6 6 6 6 6 6 6 6 6 # # # 4EMPERATURE DocID024030 Rev 10 # # -36 107/239 198 Electrical characteristics STM32F427xx STM32F429xx Additional current consumption The MCU is placed under the following conditions: * All I/O pins are configured in analog mode. * The Flash memory access time is adjusted to fHCLK frequency. * The voltage scaling is adjusted to fHCLK frequency as follows: - Scale 3 for fHCLK 120 MHz, - Scale 2 for 120 MHz < fHCLK 144 MHz - Scale 1 for 144 MHz < fHCLK 180 MHz. The over-drive is only ON at 180 MHz. * The system clock is HCLK, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2. * HSE crystal clock frequency is 25 MHz. * When the regulator is OFF, V12 is provided externally as described in Table 17: General operating conditions * TA= 25 C . Table 30. Typical current consumption in Run mode, code with data processing running from Flash memory or RAM, regulator ON (ART accelerator enabled except prefetch), VDD=1.7 V(1) Symbol Parameter Conditions fHCLK (MHz) Typ 168 88.2 150 74.3 144 71.3 120 52.9 90 42.6 60 28.6 30 15.7 25 12.3 168 40.6 150 30.6 144 32.6 120 24.7 90 19.7 60 13.6 30 7.7 25 6.7 All Peripheral enabled IDD Supply current in RUN mode from VDD supply All Peripheral disabled Unit mA 1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherls (such as ADC, or DAC) is not included. 108/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Table 31. Electrical characteristics Typical current consumption in Run mode, code with data processing running from Flash memory, regulator OFF (ART accelerator enabled except prefetch)(1) Symbol Parameter Conditions All Peripherals enabled IDD12 / IDD Supply current in RUN mode from V12 and VDD supply All Peripherals disabled fHCLK (MHz) VDD=3.3 V VDD=1.7 V Unit IDD12 IDD IDD12 IDD 168 77.8 1.3 76.8 1.0 150 70.8 1.3 69.8 1.0 144 64.5 1.3 63.6 1.0 120 49.9 1.2 49.3 0.9 90 39.2 1.3 38.7 1.0 60 27.2 1.2 26.8 0.9 30 15.6 1.2 15.4 0.9 25 13.6 1.2 13.5 0.9 168 38.2 1.3 37.0 1.0 150 34.6 1.3 33.4 1.0 144 31.3 1.3 30.3 1.0 120 24.0 1.2 23.2 0.9 90 18.1 1.4 18.0 1.0 60 12.9 1.2 12.5 0.9 30 7.2 1.2 6.9 0.9 25 6.3 1.2 6.1 0.9 mA 1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC, or DAC) is not included. DocID024030 Rev 10 109/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 32. Typical current consumption in Sleep mode, regulator ON, VDD=1.7 V(1) Symbol Parameter Conditions All Peripherals enabled IDD Supply current in Sleep mode from VDD supply All Peripherals disabled fHCLK (MHz) Typ 168 65.5 150 55.5 144 53.5 120 39.0 90 31.6 60 21.7 30 9.8 25 8.8 168 15.7 150 13.7 144 12.7 120 9.7 90 7.7 60 5.7 30 4.7 25 2.8 Unit mA 1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC, or DAC) is not included. 110/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Table 33. Tyical current consumption in Sleep mode, regulator OFF(1) VDD=3.3 V Symbol Parameter Conditions fHCLK (MHz) All Peripherals enabled IDD12/IDD Supply current in Sleep mode from V12 and VDD supply All Peripherals disabled VDD=1.7 V IDD12 IDD IDD12 IDD 180 61.5 1.4 - - 168 59.4 1.3 59.4 1.0 150 53.9 1.3 53.9 1.0 144 49.0 1.3 49.0 1.0 120 38.0 1.2 38.0 0.9 90 29.3 1.4 29.3 1.1 60 20.2 1.2 20.2 0.9 30 11.9 1.2 11.9 0.9 25 10.4 1.2 10.4 0.9 180 14.9 1.4 - - 168 14.0 1.3 14.0 1.0 150 12.6 1.3 12.6 1.0 144 11.5 1.3 11.5 1.0 120 8.7 1.2 8.7 0.9 90 7.1 1.4 7.1 1.1 60 5.0 1.2 5.0 0.9 30 3.1 1.2 3.1 0.9 25 2.8 1.2 2.8 0.9 Unit mA 1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC, or DAC) is not included. DocID024030 Rev 10 111/239 198 Electrical characteristics STM32F427xx STM32F429xx I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 56: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption (see Table 35: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DD x f SW x C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the MCU supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. 112/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Table 34. Switching output I/O current consumption(1) I/O toggling Symbol Parameter Conditions VDD = 3.3 V C= CINT(2) IDDIO I/O switching Current VDD = 3.3 V CEXT = 0 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 10 pF C = CINT + CEXT + CS IDDIO I/O switching Current VDD = 3.3 V CEXT = 22 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 33 pF C = CINT + Cext + CS frequency (fsw) Typ 2 MHz 0.0 8 MHz 0.2 25 MHz 0.6 50 MHz 1.1 60 MHz 1.3 84 MHz 1.8 90 MHz 1.9 2 MHz 0.1 8 MHz 0.4 25 MHz 1.23 50 MHz 2.43 60 MHz 2.93 84 MHz 3.86 90 MHz 4.07 2 MHz 0.18 8 MHz 0.67 25 MHz 2.09 50 MHz 3.6 60 MHz 4.5 84 MHz 7.8 90 MHz 9.8 2 MHz 0.26 8 MHz 1.01 25 MHz 3.14 50 MHz 6.39 60 MHz 10.68 2 MHz 0.33 8 MHz 1.29 25 MHz 4.23 50 MHz 11.02 Unit mA mA 1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value). 2. This test is performed by cutting the LQFP176 package pin (pad removal). DocID024030 Rev 10 113/239 198 Electrical characteristics STM32F427xx STM32F429xx On-chip peripheral current consumption The MCU is placed under the following conditions: * At startup, all I/O pins are in analog input configuration. * All peripherals are disabled unless otherwise mentioned. * I/O compensation cell enabled. * The ART accelerator is ON. * Scale 1 mode selected, internal digital voltage V12 = 1.32 V. * HCLK is the system clock. fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2. The given value is calculated by measuring the difference of current consumption * - with all peripherals clocked off - with only one peripheral clocked on - fHCLK = 180 MHz (Scale1 + over-drive ON), fHCLK = 144 MHz (Scale 2), fHCLK = 120 MHz (Scale 3)" Ambient operating temperature is 25 C and VDD=3.3 V. Table 35. Peripheral current consumption IDD( Typ)(1) Peripheral AHB1 (up to 180 MHz) 114/239 Unit Scale 1 Scale 2 Scale 3 GPIOA 2.50 2.36 2.08 GPIOB 2.56 2.36 2.08 GPIOC 2.44 2.29 2.00 GPIOD 2.50 2.36 2.08 GPIOE 2.44 2.29 2.00 GPIOF 2.44 2.29 2.00 GPIOG 2.39 2.22 2.00 GPIOH 2.33 2.15 1.92 GPIOI 2.39 2.22 2.00 GPIOJ 2.33 2.15 1.92 GPIOK 2.33 2.15 1.92 OTG_HS+ULPI 27.00 24.86 21.92 CRC 0.44 0.42 0.33 BKPSRAM 0.78 0.69 0.58 DMA1 25.33 23.26 20.50 DMA2 24.72 22.71 20.00 DMA2D 28.50 26.32 23.33 ETH_MAC ETH_MAC_TX ETH_MAC_RX ETH_MAC_PTP 21.56 20.07 17.75 DocID024030 Rev 10 A/MHz STM32F427xx STM32F429xx Electrical characteristics Table 35. Peripheral current consumption (continued) IDD( Typ)(1) Peripheral AHB2 (up to 180 MHz) AHB3 (up to 180 MHz) Scale 2 Scale 3 OTG_FS 25.67 26.67 23.58 DCMI 3.72 3.40 3.00 RNG 2.28 2.36 2.17 FMC 21.39 19.79 17.50 A/MHz 14.06 13.19 11.75 A/MHz TIM2 17.56 16.42 14.47 TIM3 14.22 13.36 11.80 TIM4 14.89 13.64 12.13 TIM5 17.33 16.42 14.47 TIM6 2.89 2.53 2.47 TIM7 3.11 2.81 2.47 TIM12 7.33 6.97 6.13 TIM13 4.89 4.47 4.13 TIM14 5.56 5.31 4.80 PWR 11.11 10.31 9.13 USART2 4.22 3.92 3.47 USART3 4.44 4.19 3.80 UART4 4.00 3.92 3.47 UART5 4.00 3.92 3.47 UART7 4.00 3.92 3.47 UART8 3.78 3.92 3.47 I2C1 4.00 3.92 3.47 I2C2 4.00 3.92 3.47 I2C3 Bus matrix(2) APB1 (up to 45 MHz) Unit Scale 1 4.00 3.92 3.47 (3) 3.11 3.08 2.80 SPI3(3) 3.56 3.36 3.13 I2S2 2.89 2.81 2.47 I2S3 3.33 3.08 2.80 CAN1 6.89 6.42 5.80 CAN2 6.67 6.14 5.47 DAC(4) 2.89 2.25 2.13 WWDG 0.89 0.86 0.80 SPI2 DocID024030 Rev 10 A/MHz A/MHz 115/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 35. Peripheral current consumption (continued) IDD( Typ)(1) Peripheral APB2 (up to 90 MHz) Unit Scale 1 Scale 2 Scale 3 SDIO 8.11 8.75 7.83 TIM1 17.11 15.97 14.17 TIM8 17.33 16.11 14.33 TIM9 7.22 6.67 6.00 TIM10 4.56 4.31 3.83 TIM11 4.78 4.44 4.00 ADC1(5) 4.67 4.31 3.83 ADC2(5) 4.78 4.44 4.00 ADC3(5) 4.56 4.17 3.67 SPI1 1.44 1.39 1.17 USART1 4.00 3.75 3.33 USART6 4.00 3.75 3.33 SPI4 1.44 1.39 1.17 SPI5 1.44 1.39 1.17 SPI6 1.44 1.39 1.17 SYSCFG 0.78 0.69 0.67 LCD_TFT 39.89 37.22 33.17 SAI1 3.78 3.47 3.17 A/MHz 1. When the I/O compensation cell is ON, IDD typical value increases by 0.22 mA. 2. The BusMatrix is automatically active when at least one master is ON. 3. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register. 4. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of 0.8 mA per DAC channel for the analog part. 5. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. 116/239 DocID024030 Rev 10 STM32F427xx STM32F429xx 6.3.8 Electrical characteristics Wakeup time from low-power modes The wakeup times given in Table 36 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: * For Stop or Sleep modes: the wakeup event is WFE. * WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD=3.3 V. Table 36. Low-power mode wakeup timings Symbol tWUSLEEP(2) Parameter Wakeup from Sleep Conditions Typ(1) Max(1) Unit - 6 - CPU clock cycle 13.6 - 93 111 22 32 103 126 105 128 125 155 318 412 Main regulator is ON Main regulator is ON and Flash memory in Deep power down mode tWUSTOP(2) Wakeup from Stop mode with MR/LP regulator in normal mode Low power regulator is ON Low power regulator is ON and Flash memory in Deep power down mode tWUSTOP(2) Main regulator in under-drive mode (Flash memory in Deep power-down Wakeup from Stop mode mode) with MR/LP regulator in Low power regulator in under-drive Under-drive mode mode (Flash memory in Deep power-down mode ) tWUSTDBY Wakeup from Standby (2)(3) mode s 1. Guaranteed by characterization results. 2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first 3. tWUSTDBY maximum value is given at -40 C. DocID024030 Rev 10 117/239 198 Electrical characteristics 6.3.9 STM32F427xx STM32F429xx External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 56: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 27. The characteristics given in Table 37 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 17. Table 37. High-speed external user clock characteristics Symbol Parameter Conditions Typ Max Unit 1 - 50 MHz fHSE_ext External user clock source frequency(1) VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) 5 - - tr(HSE) tf(HSE) Cin(HSE) IL V ns OSC_IN rise or fall time(1) OSC_IN input capacitance(1) DuCy(HSE) Duty cycle OSC_IN Input leakage current VSS VIN VDD 1. Guaranteed by design. 118/239 Min DocID024030 Rev 10 - - 10 - 5 - pF 45 - 55 % - - 1 A STM32F427xx STM32F429xx Electrical characteristics Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 56: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 28. The characteristics given in Table 38 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 17. Table 38. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit - 32.768 1000 kHz 0.7VDD - VDD fLSE_ext User External clock source frequency(1) VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage VSS - 0.3VDD tw(LSE) tf(LSE) OSC32_IN high or low time(1) 450 - - tr(LSE) tf(LSE) OSC32_IN rise or fall time(1) - - 50 OSC32_IN input capacitance(1) - 5 - pF 30 - 70 % - - 1 A Cin(LSE) DuCy(LSE) IL V ns Duty cycle VSS VIN VDD OSC32_IN Input leakage current 1. Guaranteed by design. Figure 27. High-speed external clock source AC timing diagram 6(3%( 6(3%, TR(3% TF(3% T7(3% /3#?). ), T7(3% T 4(3% %XTERNAL CLOCK SOURCE F(3%?EXT 34-& AI DocID024030 Rev 10 119/239 198 Electrical characteristics STM32F427xx STM32F429xx Figure 28. Low-speed external clock source AC timing diagram 9/6(+ 9/6(/ WU /6( WI /6( W W: /6( W: /6( 7/6( I/6(BH[W ([WHUQDO FORFNVRXUFH ,/ 26&B,1 670) DL High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 39. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 39. HSE 4-26 MHz oscillator characteristics (1) Symbol Parameter fOSC_IN RF IDD Min Typ Max Unit Oscillator frequency 4 - 26 MHz Feedback resistor - 200 - k VDD=3.3 V, ESR= 30 , CL=5 pF@25 MHz - 450 - VDD=3.3 V, ESR= 30 , CL=10 pF@25 MHz - 530 - - 500 - 500 ppm Startup - - 1 mA/V VDD is stabilized - 2 - ms HSE current consumption ACCHSE(2) Conditions HSE accuracy Gm_crit_max Maximum critical crystal gm tSU(HSE (3) Startup time A 1. Guaranteed by design. 2. This parameter depends on the crystal used in the application. The minimum and maximum values must be respected to comply with USB standard specifications. 3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is based on characterization and not tested in production. It is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. 120/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 29). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 29. Typical application with an 8 MHz crystal 5HVRQDWRUZLWK LQWHJUDWHGFDSDFLWRUV &/ I+6( 26&B,1 0+] UHVRQDWRU 5(;7 &/ 5) %LDV FRQWUROOHG JDLQ 26&B28 7 670) DL 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 40. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) Symbol Parameter Conditions Min Typ Max Unit RF Feedback resistor - 18.4 - M IDD LSE current consumption - - 1 A - 500 - 500 ppm Startup - - 0.56 A/V VDD is stabilized - 2 - s ACCLSE(2) LSE accuracy Gm_crit_max Maximum critical crystal gm tSU(LSE)(3) startup time 1. Guaranteed by design. 2. This parameter depends on the crystal used in the application. Refer to application note AN2867. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is based on characterization and not tested in production. It is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. DocID024030 Rev 10 121/239 198 Electrical characteristics STM32F427xx STM32F429xx Figure 30. Typical application with a 32.768 kHz crystal 5HVRQDWRUZLWK LQWHJUDWHGFDSDFLWRUV &/ I/6( 26&B,1 %LDV 5) FRQWUROOHG JDLQ N+ ] UHVRQDWRU 26&B28 7 &/ 670) DL 6.3.10 Internal clock source characteristics The parameters given in Table 41 and Table 42 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 17. High-speed internal (HSI) RC oscillator Table 41. HSI oscillator characteristics (1) Symbol fHSI Parameter Min Typ Max Unit - - 16 - MHz Frequency HSI user-trimming step ACCHSI tsu(HSI) Conditions (2) IDD(HSI)(2) (2) - - 1 % TA = -40 to 105 C(3) -8 - 4.5 % TA = -10 to 85 C(3) -4 - 4 % TA = 25 C(4) -1 - 1 % HSI oscillator startup time - - 2.2 4 s HSI oscillator power consumption - - 60 80 A Accuracy of the HSI oscillator - 1. VDD = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Guaranteed by design. 3. Guaranteed by characterization results. 4. Factory calibrated, parts not soldered. 122/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Figure 31. ACCHSI accuracy versus temperature $&&+6, 7$ & 0LQ 0D[ 7\SLFDO 06Y9 1. Guaranteed by characterization results. Low-speed internal (LSI) RC oscillator Table 42. LSI oscillator characteristics (1) Symbol fLSI(2) tsu(LSI) Parameter Frequency Min Typ Max Unit 17 32 47 kHz (3) LSI oscillator startup time - 15 40 s (3) LSI oscillator power consumption - 0.4 0.6 A IDD(LSI) 1. VDD = 3 V, TA = -40 to 105 C unless otherwise specified. 2. Guaranteed by characterization results. 3. Guaranteed by design. DocID024030 Rev 10 123/239 198 Electrical characteristics STM32F427xx STM32F429xx Figure 32. ACCLSI versus temperature MAX AVG MIN .ORMALIZED DEVIATI ON 4EMPERAT URE # -36 6.3.11 PLL characteristics The parameters given in Table 43 and Table 44 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 17. Table 43. Main PLL characteristics Symbol Parameter fPLL_IN PLL input clock(1) fPLL_OUT PLL multiplier output clock fPLL48_OUT 48 MHz PLL multiplier output clock fVCO_OUT PLL VCO output tLOCK PLL lock time 124/239 Conditions Min Typ Max Unit 0.95(2) 1 2.10 MHz 24 - 180 MHz - 48 75 MHz 100 - 432 MHz VCO freq = 100 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 DocID024030 Rev 10 s STM32F427xx STM32F429xx Electrical characteristics Table 43. Main PLL characteristics (continued) Symbol Parameter Conditions RMS Cycle-to-cycle jitter System clock 120 MHz RMS peak to peak Period Jitter Jitter peak to peak (3) Min Typ Max - 25 - - 150 - - 15 - - 200 - Unit ps Main clock output (MCO) for RMII Ethernet Cycle to cycle at 50 MHz on 1000 samples - 32 - Main clock output (MCO) for MII Ethernet Cycle to cycle at 25 MHz on 1000 samples - 40 - Bit Time CAN jitter Cycle to cycle at 1 MHz on 1000 samples - 330 - IDD(PLL)(4) PLL power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLL)(4) PLL power consumption on VDDA VCO freq = 100 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design. 3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%. 4. Guaranteed by characterization results. Table 44. PLLI2S (audio PLL) characteristics Symbol Parameter fPLLI2S_IN PLLI2S input clock(1) fPLLI2S_OUT PLLI2S multiplier output clock fVCO_OUT PLLI2S VCO output tLOCK PLLI2S lock time Conditions Min Typ Max Unit 0.95(2) 1 2.10 MHz - - 216 MHz 100 - 432 MHz VCO freq = 100 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 RMS - 90 - peak to peak - 280 - ps Average frequency of 12.288 MHz N = 432, R = 5 on 1000 samples - 90 - ps Cycle to cycle at 48 KHz on 1000 samples - 400 - ps Cycle to cycle at 12.288 MHz on 48KHz period, N=432, R=5 Master I2S clock jitter (3) Jitter WS I2S clock jitter DocID024030 Rev 10 s 125/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 44. PLLI2S (audio PLL) characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit IDD(PLLI2S)(4) PLLI2S power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLLI2S)(4) PLLI2S power consumption on VDDA VCO freq = 100 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2. Guaranteed by design. 3. Value given with main PLL running. 4. Guaranteed by characterization results. Table 45. PLLISAI (audio and LCD-TFT PLL) characteristics Symbol Parameter Min Typ Max Unit 0.95(2) 1 2.10 MHz - - 216 MHz 100 - 432 MHz VCO freq = 100 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 RMS - 90 - peak to peak - 280 - ps Average frequency of 12.288 MHz N = 432, R = 5 on 1000 samples - 90 - ps FS clock jitter Cycle to cycle at 48 KHz on 1000 samples - 400 - ps IDD(PLLSAI)(4) PLLSAI power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLLSAI)(4) PLLSAI power consumption on VDDA VCO freq = 100 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA fPLLSAI_IN PLLSAI input clock(1) fPLLSAI_OUT PLLSAI multiplier output clock fVCO_OUT PLLSAI VCO output tLOCK PLLSAI lock time Conditions Cycle to cycle at 12.288 MHz on 48KHz period, N=432, R=5 Main SAI clock jitter (3) Jitter 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2. Guaranteed by design. 3. Value given with main PLL running. 4. Guaranteed by characterization results. 126/239 DocID024030 Rev 10 s STM32F427xx STM32F429xx 6.3.12 Electrical characteristics PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 52: EMI characteristics). It is available only on the main PLL. Table 46. SSCG parameters constraint Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 KHz md Peak modulation depth 0.25 - 2 % MODEPER * INCSTEP - - 215 -1 - 1. Guaranteed by design. Equation 1 The frequency modulation period (MODEPER) is given by the equation below: MODEPER = round [ f PLL_IN ( 4 x f Mod ) ] fPLL_IN and fMod must be expressed in Hz. As an example: If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by equation 1: 6 3 MODEPER = round [ 10 ( 4 x 10 ) ] = 250 Equation 2 Equation 2 allows to calculate the increment step (INCSTEP): INCSTEP = round [ ( ( 2 15 - 1 ) x md x PLLN ) ( 100 x 5 x MODEPER ) ] fVCO_OUT must be expressed in MHz. With a modulation depth (md) = 2 % (4 % peak to peak), and PLLN = 240 (in MHz): INCSTEP = round [ ( ( 2 15 - 1 ) x 2 x 240 ) ( 100 x 5 x 250 ) ] = 126md(quantitazed)% An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized % = ( MODEPER x INCSTEP x 100 x 5 ) ( ( 2 15 - 1 ) x PLLN ) As a result: md quantized % = ( 250 x 126 x 100 x 5 ) ( ( 2 DocID024030 Rev 10 15 - 1 ) x 240 ) = 2.002%(peak) 127/239 198 Electrical characteristics STM32F427xx STM32F429xx Figure 33 and Figure 34 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 33. PLL output clock waveforms in center spread mode &REQUENCY 0,,?/54 MD & MD TMODE 4IME XTMODE AI Figure 34. PLL output clock waveforms in down spread mode )UHTXHQF\ 3//B287 ) [PG WPRGH [WPRGH 7LPH DLE 128/239 DocID024030 Rev 10 STM32F427xx STM32F429xx 6.3.13 Electrical characteristics Memory characteristics Flash memory The characteristics are given at TA = -40 to 105 C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Table 47. Flash memory characteristics Symbol IDD Parameter Supply current Conditions Min Typ Max Write / Erase 8-bit mode, VDD = 1.7 V - 5 - Write / Erase 16-bit mode, VDD = 2.1 V - 8 - Write / Erase 32-bit mode, VDD = 3.3 V - 12 - Unit mA Table 48. Flash memory programming Symbol tprog Parameter Word programming time tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time tME Mass erase time Conditions Min(1) Typ Max(1) Unit Program/erase parallelism (PSIZE) = x 8/16/32 - 16 100(2) Program/erase parallelism (PSIZE) = x 8 - 400 800 Program/erase parallelism (PSIZE) = x 16 - 300 600 Program/erase parallelism (PSIZE) = x 32 - 250 500 Program/erase parallelism (PSIZE) = x 8 - 1200 2400 Program/erase parallelism (PSIZE) = x 16 - 700 1400 Program/erase parallelism (PSIZE) = x 32 - 550 1100 Program/erase parallelism (PSIZE) = x 8 - 2 4 Program/erase parallelism (PSIZE) = x 16 - 1.3 2.6 Program/erase parallelism (PSIZE) = x 32 - 1 2 Program/erase parallelism (PSIZE) = x 8 - 16 32 Program/erase parallelism (PSIZE) = x 16 - 11 22 Program/erase parallelism (PSIZE) = x 32 - 8 16 DocID024030 Rev 10 s ms ms s s 129/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 48. Flash memory programming (continued) Symbol tBE Vprog Parameter Bank erase time Programming voltage Conditions Min(1) Typ Max(1) Unit Program/erase parallelism (PSIZE) = x 8 - 16 32 Program/erase parallelism (PSIZE) = x 16 - 11 22 Program/erase parallelism (PSIZE) = x 32 - 8 16 32-bit program operation 2.7 - 3.6 V 16-bit program operation 2.1 - 3.6 V 8-bit program operation 1.7 - 3.6 V s 1. Guaranteed by characterization results. 2. The maximum programming time is measured after 100K erase operations. Table 49. Flash memory programming with VPP Symbol Parameter tprog Double word programming tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time Conditions Min(1) Typ Max(1) Unit - 16 100(2) s - 230 - - 490 - - 875 - TA = 0 to +40 C VDD = 3.3 V VPP = 8.5 V tME Mass erase time - 6.9 - s tBE Bank erase time - 6.9 - s 2.7 - 3.6 V Vprog Programming voltage VPP VPP voltage range 7 - 9 V IPP Minimum current sunk on the VPP pin 10 - - mA - - 1 hour tVPP(3) Cumulative time during which VPP is applied 1. Guaranteed by design. 2. The maximum programming time is measured after 100K erase operations. 3. VPP should only be connected during programming/erasing. 130/239 ms DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Table 50. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Data retention Conditions Min(1) TA = -40 to +85 C (6 suffix versions) TA = -40 to +105 C (7 suffix versions) 10 1 kcycle(2) at TA = 85 C 30 1 kcycle (2) 10 kcycles at TA = 105 C 10 (2) 20 at TA = 55 C Unit kcycles Years 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range. 6.3.14 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: * Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. * FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 51. They are based on the EMS levels and classes defined in application note AN1709. Table 51. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 3.3 V, LQFP176, TA = Voltage limits to be applied on any I/O pin to +25 C, fHCLK = 168 MHz, conforms induce a functional disturbance to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP176, TA =+25 C, fHCLK = 168 MHz, conforms to IEC 61000-4-2 4A When the application is exposed to a noisy environment, it is recommended to avoid pin exposition to disturbances. The pins showing a middle range robustness are: PA0, PA1, PA2, PH2, PH3, PH4, PH5, PA3, PA4, PA5, PA6, PA7, PC4, and PC5. As a consequence, it is recommended to add a serial resistor (1 k) located as close as possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm on PCB). DocID024030 Rev 10 131/239 198 Electrical characteristics STM32F427xx STM32F429xx Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: * Corrupted program counter * Unexpected reset * Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC? code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 52. EMI characteristics Symbol Parameter Conditions VDD = 3.3 V, TA = 25 C, LQFP176 package, conforming to SAE J1752/3 EEMBC, ART ON, all peripheral clocks enabled, clock dithering disabled. SEMI Peak level VDD = 3.3 V, TA = 25 C, LQFP176 package, conforming to SAE J1752/3 EEMBC, ART ON, all peripheral clocks enabled, clock dithering enabled 132/239 Max vs. Max vs. Monitored [fHSE/fCPU] [fHSE/fCPU] frequency band 25/168 MHz 25/180 MHz 0.1 to 30 MHz 16 19 30 to 130 MHz 23 23 130 MHz to 1GHz 25 22 SAE EMI Level 4 4 0.1 to 30 MHz 17 16 30 to 130 MHz 8 10 130 MHz to 1GHz 11 16 SAE EMI level 3.5 3.5 DocID024030 Rev 10 Unit dBV - dBV - STM32F427xx STM32F429xx 6.3.15 Electrical characteristics Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESD S5.3.1 standards. Table 53. ESD absolute maximum ratings Symbol Ratings Electrostatic discharge VESD(HBM) voltage (human body model) Electrostatic discharge VESD(CDM) voltage (charge device model) Class Maximum value(1) 2 2000 TA = +25 C conforming to ANSI/ESD S5.3.1, LQFP100/144/176, UFBGA169/176, TFBGA176 and WLCSP143 packages C3 250 TA = +25 C conforming to ANSI/ESD S5.3.1, LQFP208 package C3 250 Conditions TA = +25 C conforming to ANSI/ESDA/JEDEC JS-001 Unit V 1. Guaranteed by characterization results. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: * A supply overvoltage is applied to each power supply pin * A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latchup standard. Table 54. Electrical sensitivities Symbol LU Parameter Static latch-up class Conditions TA = +105 C conforming to JESD78A DocID024030 Rev 10 Class II level A 133/239 198 Electrical characteristics 6.3.16 STM32F427xx STM32F429xx I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of - 5 A/+0 A range), or other functional failure (for example reset, oscillator frequency deviation). Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. The test results are given in Table 55. Table 55. I/O current injection susceptibility(1) Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on BOOT0 pin -0 NA Injected current on NRST pin -0 NA Injected current on PA0, PA1, PA2, PA3, PA6, PA7, PB0, PC0, PC1, PC2, PC3, PC4, PC5, PH1, PH2, PH3, PH4, PH5 -0 NA Injected current on TTa pins: PA4 and PA5 -0 +5 Injected current on any other FT pin -5 NA 1. NA = not applicable. Note: 134/239 It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. DocID024030 Rev 10 Unit mA STM32F427xx STM32F429xx 6.3.17 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 56: I/O static characteristics are derived from tests performed under the conditions summarized in Table 17. All I/Os are CMOS and TTL compliant. Table 56. I/O static characteristics Symbol Parameter Conditions 1.7 VVDD3.6 V BOOT0 I/O input low level voltage FT, TTa and NRST I/O input high level voltage(5) - 1.75 VVDD 3.6 V, - 40 CTA 105 C - 1.7 VVDD 3.6 V, 0 CTA 105 C - 1.7 VVDD3.6 V 1.75 VVDD 3.6 V, - 40 CTA 105 C BOOT0 I/O input high level voltage 1.7 VVDD 3.6 V, 0 CTA 105 C FT, TTa and NRST I/O input hysteresis Unit - (1) 0.45VDD+0.3(1) 0.7VDD(2) (5) - V - - 10%VDD(3) - V 0.1 - - VSS VIN VDD - - 1 VIN = 5 V - - 3 1.7 VVDD 3.6 V, 0 CTA 105 C I/O input leakage current (4) - 0.17VDD+0.7(1) 1.75 VVDD 3.6 V, - 40 CTA 105 C BOOT0 I/O input hysteresis V 0.1VDD+0.1(1) 1.7 VVDD3.6 V VHYS I/O FT input leakage current Max 0.3VDD(2) VIL Ilkg Typ 0.35VDD - 0.04 FT, TTa and NRST I/O input low level voltage VIH Min DocID024030 Rev 10 A 135/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 56. I/O static characteristics (continued) Symbol RPU RPD CIO(8) Parameter Weak pull-up equivalent resistor(6) Weak pulldown equivalent resistor(7) Min Typ Max 30 40 50 PA10/PB12 (OTG_FS_ID, OTG_HS_ID) 7 10 14 All pins except for PA10/PB12 (OTG_FS_ID, OTG_HS_ID) 30 40 50 7 10 14 - 5 - All pins except for PA10/PB12 (OTG_FS_ID, OTG_HS_ID) Conditions VIN = VSS k VIN = VDD PA10/PB12 (OTG_FS_ID, OTG_HS_ID) I/O pin capacitance Unit - 1. Guaranteed by design. 2. Tested in production. 3. With a minimum of 200 mV. 4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 55: I/O current injection susceptibility 5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 55: I/O current injection susceptibility 6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum (~10% order). 7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order). 8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results. All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in Figure 35. 136/239 DocID024030 Rev 10 pF STM32F427xx STM32F429xx Electrical characteristics Figure 35. FT I/O input characteristics 9,/9,+ 9 ' 9' L P ,+ Q 9 QW H P LUH 77/UHTXLUHPHQW U 9,+PLQ 9 26 0 & ' 9' Q R WL XF LQ RG +P , SU 9 LQ QV WLR HG VW XOD P L 7H V LJQ HV $UHDQRW Q' R G VH GHWHUPLQHG '' D % 9 D[ ,/P QV9 ODWLR X LP V VLJQ Q'H HGR 77/UHTXLUHPHQW9,/PD[ %DV 9 7HVWHGLQSURGXFWLRQ&026UHTXLUHPHQW9,/PD[ 9'' X HT 9'' 9 069 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or source up to 20 mA (with a relaxed VOL/VOH) except PC13, PC14, PC15 and PI8 which can sink or source up to 3mA. When using the PC13 to PC15 and PI8 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2. In particular: * The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 15). * The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 15). DocID024030 Rev 10 137/239 198 Electrical characteristics STM32F427xx STM32F429xx Output voltage levels Unless otherwise specified, the parameters given in Table 57 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 17. All I/Os are CMOS and TTL compliant. Table 57. Output voltage characteristics Symbol Parameter VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL (1) Output low level voltage for an I/O pin VOH (3) Output high level voltage for an I/O pin VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin Conditions (2) CMOS port IIO = +8 mA 2.7 V VDD 3.6 V TTL port(2) IIO =+ 8mA 2.7 V VDD 3.6 V IIO = +20 mA 2.7 V VDD 3.6 V IIO = +6 mA 1.8 V VDD 3.6 V IIO = +4 mA 1.7 V VDD 3.6V Min Max - 0.4 VDD - 0.4 - - 0.4 2.4 - - 1.3(4) VDD -1.3(4) - - 0.4(4) VDD -0.4(4) - - 0.4(5) VDD -0.4(5) - Unit V V V V V 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 15. and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 15 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Based on characterization data. 5. Guaranteed by design. 138/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 36 and Table 58, respectively. Unless otherwise specified, the parameters given in Table 58 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 17. Table 58. I/O AC characteristics(1)(2) OSPEEDRy [1:0] bit value(1) Symbol fmax(IO)out Parameter Maximum frequency(3) 00 tf(IO)out/ tr(IO)out fmax(IO)out Output high to low level fall time and output low to high level rise time Maximum frequency(3) 01 tf(IO)out/ tr(IO)out fmax(IO)out Output high to low level fall time and output low to high level rise time Maximum frequency(3) 10 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time Conditions Min Typ Max CL = 50 pF, VDD 2.7 V - - 4 CL = 50 pF, VDD 1.7 V - - 2 CL = 10 pF, VDD 2.7 V - - 8 CL = 10 pF, VDD 1.8 V - - 4 CL = 10 pF, VDD 1.7 V - - 3 CL = 50 pF, VDD = 1.7 V to 3.6 V - - 100 CL = 50 pF, VDD 2.7 V - - 25 CL = 50 pF, VDD 1.8 V - - 12.5 CL = 50 pF, VDD 1.7 V - - 10 CL = 10 pF, VDD 2.7 V - - 50 CL = 10 pF, VDD 1.8 V - - 20 CL = 10 pF, VDD 1.7 V - - 12.5 CL = 50 pF, VDD 2.7 V - - 10 CL = 10 pF, VDD 2.7 V - - 6 CL = 50 pF, VDD 1.7 V - - 20 CL = 10 pF, VDD 1.7 V - - 10 CL = 40 pF, VDD 2.7 V - - 50(4) CL = 10 pF, VDD 2.7 V - - 100(4) CL = 40 pF, VDD 1.7 V - - 25 CL = 10 pF, VDD 1.8 V - - 50 CL = 10 pF, VDD 1.7 V - - 42.5 CL = 40 pF, VDD 2.7 V - - 6 CL = 10 pF, VDD 2.7 V - - 4 CL = 40 pF, VDD 1.7 V - - 10 CL = 10 pF, VDD 1.7 V - - 6 DocID024030 Rev 10 Unit MHz ns MHz ns MHz ns 139/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 58. I/O AC characteristics(1)(2) (continued) OSPEEDRy [1:0] bit value(1) Symbol fmax(IO)out Parameter Conditions Maximum frequency(3) 11 tf(IO)out/ tr(IO)out - tEXTIpw Output high to low level fall time and output low to high level rise time Min Typ Max CL = 30 pF, VDD 2.7 V - - 100(4) CL = 30 pF, VDD 1.8 V - - 50 CL = 30 pF, VDD 1.7 V - - 42.5 CL = 10 pF, VDD 2.7 V - - 180(4) CL = 10 pF, VDD 1.8 V - - 100 CL = 10 pF, VDD 1.7 V - - 72.5 CL = 30 pF, VDD 2.7 V - - 4 CL = 30 pF, VDD 1.8 V - - 6 CL = 30 pF, VDD 1.7 V - - 7 CL = 10 pF, VDD 2.7 V - - 2.5 CL = 10 pF, VDD 1.8 V - - 3.5 CL = 10 pF, VDD 1.7 V - - 4 10 - - Pulse width of external signals detected by the EXTI controller Unit MHz ns ns 1. Guaranteed by design. 2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 3. The maximum frequency is defined in Figure 36. 4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used. Figure 36. I/O AC characteristics definition (;7(51$/ 287387 21&/ WU ,2 RXW WI ,2 RXW 7 0D[LPXPIUHTXHQF\LVDFKLHYHGLI WUWI 7DQGLIWKHGXW\F\FOHLV ZKHQORDGHGE\&/VSHFLILHGLQWKHWDEOH,2$&FKDUDFWHULVWLFV 140/239 DocID024030 Rev 10 DLG STM32F427xx STM32F429xx 6.3.18 Electrical characteristics NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 56: I/O static characteristics). Unless otherwise specified, the parameters given in Table 59 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 17. Table 59. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit RPU Weak pull-up equivalent resistor(1) VIN = VSS 30 40 50 k - - 100 ns VDD > 2.7 V 300 - - ns Internal Reset source 20 - - s VF(NRST) (2) NRST Input filtered pulse VNF(NRST)(2) NRST Input not filtered pulse TNRST_OUT Generated reset pulse duration 1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 2. Guaranteed by design. Figure 37. Recommended NRST pin protection 9'' ([WHUQDO UHVHWFLUFXLW 1567 538 ,QWHUQDO5HVHW )LOWHU ) 670) DLF 1. The reset network protects the device against parasitic resets. 2. The external capacitor must be placed as close as possible to the device. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 59. Otherwise the reset is not taken into account by the device. DocID024030 Rev 10 141/239 198 Electrical characteristics 6.3.19 STM32F427xx STM32F429xx TIM timer characteristics The parameters given in Table 60 are guaranteed by design. Refer to Section 6.3.17: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 60. TIMx characteristics(1)(2) Symbol tres(TIM) fEXT ResTIM tMAX_COUNT Conditions(3) Min Max Unit AHB/APBx prescaler=1 or 2 or 4, fTIMxCLK = 180 MHz 1 - tTIMxCLK AHB/APBx prescaler>4, fTIMxCLK = 90 MHz 1 - tTIMxCLK Timer external clock frequency on CH1 to CH4 f TIMxCLK = 180 MHz 0 fTIMxCLK/2 MHz Timer resolution - 16/32 bit Maximum possible count with 32-bit counter - 65536 x 65536 tTIMxCLK Parameter Timer resolution time 1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers. 2. Guaranteed by design. 3. The maximum timer frequency on APB1 or APB2 is up to 180 MHz, by setting the TIMPRE bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise TIMxCLK = 4x PCLKx. 6.3.20 Communications interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: * Standard-mode (Sm): with a bit rate up to 100 kbit/s * Fast-mode (Fm): with a bit rate up to 400 kbit/s. The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0090 reference manual). The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. Refer to Section 6.3.17: I/O port characteristics for more details on the I2C I/O characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics: 142/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Table 61. I2C analog filter characteristics(1) Symbol tAF Parameter Maximum pulse width of spikes that are suppressed by the analog filter Min Max Unit 50(2) 260(3) ns 1. Guaranteed by design. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered SPI interface characteristics Unless otherwise specified, the parameters given in Table 62 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). Table 62. SPI dynamic characteristics(1) Symbol Parameter Conditions Min Typ Master mode, SPI1/4/5/6, 2.7 VVDD3.6 V fSCK 1/tc(SCK) SPI clock frequency Slave mode, SPI1/4/5/6, 2.7 VVDD3.6 V Receiver Slave mode, SPI1/2/3/4/5/6, 1.7 VVDD3.6 V Duty(SCK) Duty cycle of SPI clock Slave mode frequency DocID024030 Rev 10 Unit 45 - - Transmitter/ full-duplex Master mode, SPI1/2/3/4/5/6, 1.7 VVDD3.6 V Max 45 38(2) MHz 22.5 - 22.5 30 50 70 % 143/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 62. SPI dynamic characteristics(1) (continued) Symbol Parameter tw(SCKH) SCK high and low time tw(SCKL) Conditions Min Typ Max Master mode, SPI presc = 2, 2.7 VVDD3.6 V TPCLK - 0.5 TPCLK TPCLK+0.5 Master mode, SPI presc = 2, 1.7 VVDD3.6 V TPCLK - 2 TPCLK TPCLK+2 - - tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4TPCLK th(NSS) NSS hold time Slave mode, SPI presc = 2 2TPCLK tsu(MI) tsu(SI) th(MI) th(SI) ta(SO) tdis(SO) tv(SO) th(SO) tv(MO) th(MO) Data input setup time Data input hold time Master mode 3 - - Slave mode 0 - - Master mode 0.5 - - Slave mode 2 - - 0 - 4TPCLK Slave mode, SPI1/4/5/6, 2.7 VVDD3.6 V 0 - 8.5 Slave mode, SPI1/2/3/4/5/6 and 1.7 VVDD3.6 V 0 - 16.5 Slave mode (after enable edge), SPI1/4/5/6 and 2.7V VDD 3.6V - 11 13 Slave mode (after enable edge), SPI2/3, 2.7 VVDD3.6 V - 14 15 Slave mode (after enable edge), SPI1/4/5/6, 1.7 VVDD3.6 V - 15.5 19 Slave mode (after enable edge), SPI2/3, 1.7 VVDD3.6 V - 15.5 17.5 Master mode (after enable edge), SPI1/4/5/6, 2.7 VVDD3.6 V - - 2.5 Master mode (after enable edge), SPI1/2/3/4/5/6, 1.7 VVDD3.6 V - - 4.5 Master mode (after enable edge) 0 - - Data output access time Slave mode, SPI presc = 2 Data output disable time Data output valid/hold time Data output valid time Data output hold time Unit ns ns 1. Guaranteed by characterization results. 2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50% 144/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Figure 38. SPI timing diagram - slave mode and CPHA = 0 Figure 39. SPI timing diagram - slave mode and CPHA = 1 166LQSXW 6&.LQSXW W68 166 &3+$ &32/ &3+$ &32/ WZ 6&.+ WZ 6&./ WK 62 WY 62 WD 62 0,62 287387 06%287 %,7287 WU 6&. WI 6&. WGLV 62 /6%287 WK 6, WVX 6, 026, ,1387 WK 166 WF 6&. 06%,1 %,7,1 /6%,1 DLE DocID024030 Rev 10 145/239 198 Electrical characteristics STM32F427xx STM32F429xx Figure 40. SPI timing diagram - master mode +LJK 166LQSXW 6&.2XWSXW &3+$ &32/ 6&.2XWSXW WF 6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WVX 0, 0,62 ,13 87 WZ 6&.+ WZ 6&./ WU 6&. WI 6&. %,7,1 06%,1 /6%,1 WK 0, 026, 287387 06%287 WY 02 % , 7287 /6%287 WK 02 DLF 146/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics I2S interface characteristics Unless otherwise specified, the parameters given in Table 63 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Table 63. I2S dynamic characteristics(1) Symbol Parameter fMCK I2S Main clock output fCK I2S clock frequency DCK Conditions Min Max Unit 256x8K 256xFs(2) MHz Master data: 32 bits - 64xFs Slave data: 32 bits - 64xFs 30 70 - I2S clock frequency duty cycle Slave receiver tv(WS) WS valid time Master mode 0 6 th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 1 - th(WS) WS hold time Slave mode 0 - Master receiver 7.5 - Slave receiver 2 - Master receiver 0 - Slave receiver 0 - Slave transmitter (after enable edge) - 27 Master transmitter (after enable edge) - 20 Master transmitter (after enable edge) 2.5 tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) tv(SD_ST) th(SD_ST) Data input setup time Data input hold time Data output valid time tv(SD_MT) th(SD_MT) Data output hold time MHz % ns - 1. Guaranteed by characterization results. 2. The maximum value of 256xFs is 45 MHz (APB1 maximum frequency). Note: Refer to the I2S section of RM0090 reference manual for more details on the sampling frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The values of these parameters might be slightly impacted by the source clock precision. DCK depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS maximum value is supported for each mode/condition. DocID024030 Rev 10 147/239 198 Electrical characteristics STM32F427xx STM32F429xx Figure 41. I2S slave timing diagram (Philips protocol)(1) 1. .LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 42. I2S master timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 148/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics SAI characteristics Unless otherwise specified, the parameters given in Table 64 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C=30 pF * Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate function characteristics (SCK,SD,WS). Table 64. SAI characteristics(1) Symbol Parameter Conditions Min Max Unit fMCKL SAI Main clock output - 256 x 8K 256xFs(2) MHz FSCK SAI clock frequency Master data: 32 bits - 64xFs Slave data: 32 bits - 64xFs DSCK SAI clock frequency duty cycle Slave receiver 30 70 tv(FS) FS valid time Master mode 8 22 tsu(FS) FS setup time Slave mode 2 - th(FS) FS hold time Master mode 8 - Slave mode 0 - Master receiver 5 - Slave receiver 3 - Master receiver 0 - Slave receiver 0 - Slave transmitter (after enable edge) - 22 Master transmitter (after enable edge) - 20 Master transmitter (after enable edge) 8 - tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) tv(SD_ST) th(SD_ST) Data input setup time Data input hold time Data output valid time tv(SD_MT) th(SD_MT) Data output hold time MHz % ns 1. Guaranteed by characterization results. 2. 256xFs maximum corresponds to 45 MHz (APB2 xaximum frequency) DocID024030 Rev 10 149/239 198 Electrical characteristics STM32F427xx STM32F429xx Figure 43. SAI master timing waveforms F3#+ 3!)?3#+?8 TH&3 3!)?&3?8 OUTPUT TV&3 TH3$?-4 TV3$?-4 3!)?3$?8 TRANSMIT 3LOT N 3LOT N TSU3$?-2 TH3$?-2 3!)?3$?8 RECEIVE 3LOT N -36 Figure 44. SAI slave timing waveforms F3#+ 3!)?3#+?8 TW#+(?8 3!)?&3?8 INPUT TW#+,?8 TH&3 TSU&3 3!)?3$?8 TRANSMIT 3LOT N TSU3$?32 3!)?3$?8 RECEIVE TH3$?34 TV3$?34 3LOT N TH3$?32 3LOT N -36 150/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics USB OTG full speed (FS) characteristics This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 65. USB OTG full speed startup time Symbol tSTARTUP(1) Parameter Max Unit USB OTG full speed transceiver startup time 1 s 1. Guaranteed by design. Table 66. USB OTG full speed DC electrical characteristics Symbol VDD Input levels Parameter Conditions USB OTG full speed transceiver operating voltage Min.(1) Typ. Max.(1) Unit 3.0(2) - 3.6 VDI(3) Differential input sensitivity I(USB_FS_DP/DM, USB_HS_DP/DM) 0.2 - - VCM(3) Differential common mode range Includes VDI range 0.8 - 2.5 VSE(3) Single ended receiver threshold 1.3 - 2.0 VOL Static output level low - - 0.3 2.8 - 3.6 17 21 24 0.65 1.1 2.0 Output levels RPD RPU VOH Static output level high PA11, PA12, PB14, PB15 (USB_FS_DP/DM, USB_HS_DP/DM) PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) RL of 1.5 k to 3.6 V(4) RL of 15 k to VSS(4) V V V VIN = VDD k PA12, PB15 (USB_FS_DP, USB_HS_DP) VIN = VSS 1.5 1.8 2.1 PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VIN = VSS 0.25 0.37 0.55 1. All the voltages are measured from the local ground potential. 2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 3. Guaranteed by design. 4. RL is the load connected on the USB OTG full speed drivers. Note: When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state (floating input), not as alternate function. A typical 200 A current consumption of the sensing block (current to voltage conversion to determine the different sessions) can be observed on PA9 and PB13 when the feature is enabled. DocID024030 Rev 10 151/239 198 Electrical characteristics STM32F427xx STM32F429xx Figure 45. USB OTG full speed timings: definition of data signal rise and fall time &URVVRYHU SRLQWV 'LIIHUHQWLDO GDWDOLQHV 9&56 966 WI WU DLE Table 67. USB OTG full speed electrical characteristics(1) Driver characteristics Symbol tr tf trfm Parameter Rise time(2) Fall time(2) Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V 28 44 Rise/ fall time matching VCRS Output signal crossover voltage ZDRV Output driver impedance(3) Driving high or low 1. Guaranteed by design. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching impedance is included in the embedded driver. USB high speed (HS) characteristics Unless otherwise specified, the parameters given in Table 70 for ULPI are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 69 and VDD supply voltage conditions summarized in Table 68, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10, unless otherwise specified * Capacitive load C = 30 pF, unless otherwise specified * Measurement points are done at CMOS levels: 0.5VDD. Refer to Section 6.3.17: I/O port characteristics for more details on the input/output characteristics. Table 68. USB HS DC electrical characteristics Symbol Input level Parameter VDD USB OTG HS operating voltage 1. All the voltages are measured from the local ground potential. 152/239 DocID024030 Rev 10 Min.(1) Max.(1) Unit 1.7 3.6 V STM32F427xx STM32F429xx Electrical characteristics Table 69. USB HS clock timing parameters(1) Symbol Parameter Min Typ Max Unit fHCLK value to guarantee proper operation of USB HS interface 30 - - MHz FSTART_8BIT Frequency (first transition) 54 60 66 MHz FSTEADY Frequency (steady state) 500 ppm 59.97 60 60.03 MHz DSTART_8BIT Duty cycle (first transition) 40 50 60 % DSTEADY Duty cycle (steady state) 500 ppm 49.975 50 50.025 % tSTEADY Time to reach the steady state frequency and duty cycle after the first transition - - 1.4 ms Peripheral - - 5.6 Host - - - - - - tSTART_DEV tSTART_HOST Clock startup time after the de-assertion of SuspendM 8-bit 10% 8-bit 10% PHY preparation time after the first transition of the input clock tPREP ms s 1. Guaranteed by design. Figure 46. ULPI timing diagram #LOCK #ONTROL )N 5,0)?$)2 5,0)?.84 T3# T(# T3$ T($ DATA )N BIT T$# #ONTROL OUT 5,0)?340 DATA OUT BIT T$# T$$ AIC DocID024030 Rev 10 153/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 70. Dynamic characteristics: USB ULPI(1) Symbol Parameter Conditions Min. Typ. Max. tSC Control in (ULPI_DIR, ULPI_NXT) setup time 2 - - tHC Control in (ULPI_DIR, ULPI_NXT) hold time 0.5 - - tSD Data in setup time 1.5 - - tHD Data in hold time 2 - - 2.7 V < VDD < 3.6 V, CL = 15 pF and OSPEEDRy[1:0] = 11 - 9 9.5 2.7 V < VDD < 3.6 V, CL = 20 pF and OSPEEDRy[1:0] = 10 - 1.7 V < VDD < 3.6 V, CL = 15 pF and OSPEEDRy[1:0] = 11 12 15 - tDC/tDD Data/control output delay 1. Guaranteed by characterization results. 154/239 DocID024030 Rev 10 Unit ns STM32F427xx STM32F429xx Electrical characteristics Ethernet characteristics Unless otherwise specified, the parameters given in Table 71, Table 72 and Table 73 for SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 17 with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30 pF for 2.7 V < VDD < 3.6 V * Capacitive load C = 20 pF for 1.71 V < VDD < 3.6 V * Measurement points are done at CMOS levels: 0.5VDD. Refer to Section 6.3.17: I/O port characteristics for more details on the input/output characteristics. Table 71 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 47 shows the corresponding timing diagram. Figure 47. Ethernet SMI timing diagram W0'& (7+B0'& WG 0',2 (7+B0',2 2 WVX 0',2 WK 0',2 (7+B0',2 , 069 Table 71. Dynamics characteristics: Ethernet MAC signals for SMI(1) Symbol tMDC Parameter MDC cycle time(2.38 MHz) Min Typ Max 411 420 425 Td(MDIO) Write data valid time 6 10 13 tsu(MDIO) Read data setup time 12 - - th(MDIO) Read data hold time 0 - - Unit ns 1. Guaranteed by characterization results. DocID024030 Rev 10 155/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 72 gives the list of Ethernet MAC signals for the RMII and Figure 48 shows the corresponding timing diagram. Figure 48. Ethernet RMII timing diagram 50,,B5()B&/. WG 7;(1 WG 7;' 50,,B7;B(1 50,,B7;'>@ WVX 5;' WVX &56 WLK 5;' WLK &56 50,,B5;'>@ 50,,B&56B'9 DLE Table 72. Dynamics characteristics: Ethernet MAC signals for RMII(1) Symbol Parameter tsu(RXD) Receive data setup time tih(RXD) Receive data hold time tsu(CRS) Carrier sense setup time tih(CRS) Carrier sense hold time td(TXEN) Transmit enable valid delay time td(TXD) Transmit data valid delay time Condition Min Typ Max 1.5 - - 0 - - 1 - - 1 - - 2.7 V < VDD < 3.6 V 8 10.5 12 1.71 V < VDD < 3.6 V 8 10.5 14 2.7 V < VDD < 3.6 V 8 11 12.5 1.71 V < VDD < 3.6 V 8 11 14.5 1.71 V < VDD < 3.6 V 1. Guaranteed by characterization results. Table 73 gives the list of Ethernet MAC signals for MII and Figure 48 shows the corresponding timing diagram. 156/239 DocID024030 Rev 10 Unit ns STM32F427xx STM32F429xx Electrical characteristics Figure 49. Ethernet MII timing diagram 0,,B5;B&/. WVX 5;' WVX (5 WVX '9 WLK 5;' WLK (5 WLK '9 0,,B5;'>@ 0,,B5;B'9 0,,B5;B(5 0,,B7;B&/. WG 7;(1 WG 7;' 0,,B7;B(1 0,,B7;'>@ AIB Table 73. Dynamics characteristics: Ethernet MAC signals for MII(1) Symbol Parameter Condition Min Typ Max tsu(RXD) Receive data setup time 9 - - tih(RXD) Receive data hold time 10 - - tsu(DV) Data valid setup time 9 - - tih(DV) Data valid hold time 8 - - tsu(ER) Error setup time 6 - - tih(ER) Error hold time 8 - - 2.7 V < VDD < 3.6 V 8 10 14 1.71 V < VDD < 3.6 V 8 10 16 2.7 V < VDD < 3.6 V 7.5 10 15 1.71 V < VDD < 3.6 V 7.5 10 17 td(TXEN) Transmit enable valid delay time td(TXD) Transmit data valid delay time 1.71 V < VDD < 3.6 V Unit ns 1. Guaranteed by characterization results. CAN (controller area network) interface Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate function characteristics (CANx_TX and CANx_RX). DocID024030 Rev 10 157/239 198 Electrical characteristics 6.3.21 STM32F427xx STM32F429xx 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 74 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 17. Table 74. ADC characteristics Symbol Parameter VDDA Power supply VREF+ Positive reference voltage VREF- Negative reference voltage Conditions Typ Max (1) 1.7 - 3.6 1.7(1) - VDDA - 0 - 0.6 15 18 MHz VDDA = 2.4 to 3.6 V 0.6 30 36 MHz fADC = 30 MHz, 12-bit resolution - - 1764 kHz - - 17 1/fADC 0 (VSSA or VREFtied to ground) - VREF+ V - - 50 k 1.5 - 6 k - 4 7 pF - - 0.100 s - - 3(5) 1/fADC - - 0.067 s - - 2(5) 1/fADC 0.100 - 16 s 3 - 480 1/fADC - 2 3 s fADC = 30 MHz 12-bit resolution 0.50 - 16.40 s fADC = 30 MHz 10-bit resolution 0.43 - 16.34 s fADC = 30 MHz 8-bit resolution 0.37 - 16.27 s fADC = 30 MHz 6-bit resolution 0.30 - 16.20 s VDDA - VREF+ < 1.2 V (1) fADC fTRIG(2) VAIN RAIN(2) ADC clock frequency External trigger frequency VDDA = 1.7 to 2.4 V Conversion voltage range(3) External input impedance See Equation 1 for details RADC(2)(4) Sampling switch resistance CADC(2) Internal sample and hold capacitor tlat(2) Injection trigger conversion latency fADC = 30 MHz tlatr(2) Regular trigger conversion latency fADC = 30 MHz tS(2) Sampling time tSTAB(2) Power-up time tCONV(2) Total conversion time (including sampling time) fADC = 30 MHz Min 9 to 492 (tS for sampling +n-bit resolution for successive approximation) 158/239 DocID024030 Rev 10 Unit V 1/fADC STM32F427xx STM32F429xx Electrical characteristics Table 74. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode - - 6 Msps Sampling rate fS(2) (fADC = 30 MHz, and tS = 3 ADC cycles) IVREF+(2) ADC VREF DC current consumption in conversion mode - 300 500 A IVDDA(2) ADC VDDA DC current consumption in conversion mode - 1.6 1.8 mA 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). 2. Guaranteed by characterization results. 3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V. 5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 74. Equation 1: RAIN max formula R AIN ( k - 0.5 ) - - R ADC = --------------------------------------------------------------N+2 f ADC x C ADC x ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. Table 75. ADC static accuracy at fADC = 18 MHz Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC =18 MHz VDDA = 1.7 to 3.6 V VREF = 1.7 to 3.6 V VDDA - VREF < 1.2 V Typ Max(1) 3 4 2 3 1 3 1 2 2 3 Unit LSB 1. Guaranteed by characterization results. DocID024030 Rev 10 159/239 198 Electrical characteristics a Table 76. ADC static accuracy at fADC = 30 MHz Symbol ET STM32F427xx STM32F429xx Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC = 30 MHz, RAIN < 10 k, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V, VDDA - VREF < 1.2 V Typ Max(1) 2 5 1.5 2.5 1.5 3 1 2 1.5 3 Unit LSB 1. Guaranteed by characterization results. Table 77. ADC static accuracy at fADC = 36 MHz Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC =36 MHz, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V VDDA - VREF < 1.2 V Typ Max(1) 4 7 2 3 3 6 2 3 3 6 Unit LSB 1. Guaranteed by characterization results. Table 78. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion fADC =18 MHz VDDA = VREF+= 1.7 V Input Frequency = 20 KHz Temperature = 25 C Min Typ Max Unit 10.3 10.4 - bits 64 64.2 - 64 65 - - 67 - 72 - dB 1. Guaranteed by characterization results. Table 79. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to noise and distortion ratio SNR Signal-to noise ratio THD Total harmonic distortion fADC =36 MHz VDDA = VREF+ = 3.3 V Input Frequency = 20 KHz Temperature = 25 C 1. Guaranteed by characterization results. 160/239 DocID024030 Rev 10 Min Typ Max Unit 10.6 10.8 - bits 66 67 - 64 68 - - 70 - 72 - dB STM32F427xx STM32F429xx Note: Electrical characteristics ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.17 does not affect the ADC accuracy. Figure 50. ADC accuracy characteristics ;,3" )$%!, 6 2%& OR 6 $$! DEPENDING ON PACKAGE = %' %4 %/ %, %$ , 3")$%!, 6 33! 6$$! AIC 1. See also Table 76. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. DocID024030 Rev 10 161/239 198 Electrical characteristics STM32F427xx STM32F429xx Figure 51. Typical connection diagram using the ADC 670) 9'' 5$,1 9$,1 6DPSOHDQGKROG$'& FRQYHUWHU 97 9 5$'& $,1[ &SDUDVLWLF 97 9 ,/$ ELW FRQYHUWHU & $'& DL 1. Refer to Table 74 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. 162/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 52 or Figure 53, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 52. Power supply and reference decoupling (VREF+ not connected to VDDA) 670) 95() )Q) 9''$ )Q) 966$95() DLE 1. VREF+ and VREF- inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA. DocID024030 Rev 10 163/239 198 Electrical characteristics STM32F427xx STM32F429xx Figure 53. Power supply and reference decoupling (VREF+ connected to VDDA) 670) 95()9''$ )Q) 95()966$ DLF 1. VREF+ and VREF- inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA. 6.3.22 Temperature sensor characteristics Table 80. Temperature sensor characteristics Symbol TL(1) Parameter Min Typ Max Unit - 1 2 C - 2.5 mV/C Voltage at 25 C - 0.76 V Startup time - 6 10 s 10 - - s VSENSE linearity with temperature Avg_Slope(1) Average slope V25(1) tSTART (2) TS_temp(2) ADC sampling time when reading the temperature (1 C accuracy) 1. Guaranteed by characterization results. 2. Guaranteed by design. Table 81. Temperature sensor calibration values Symbol Parameter Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 C, VDDA= 3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D TS_CAL2 TS ADC raw data acquired at temperature of 110 C, VDDA= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F 164/239 DocID024030 Rev 10 STM32F427xx STM32F429xx 6.3.23 Electrical characteristics VBAT monitoring characteristics Table 82. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit K R Resistor bridge for VBAT - 50 - Q Ratio on VBAT measurement - 4 - Error on Q -1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - s Er (1) TS_vbat(2)(2) 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 6.3.24 Reference voltage The parameters given in Table 83 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 17. Table 83. internal reference voltage Symbol VREFINT TS_vrefint(1) VRERINT_s(2) Parameter Internal reference voltage Conditions Min Typ Max Unit -40 C < TA < +105 C 1.18 1.21 1.24 V 10 - - s - 3 5 mV ADC sampling time when reading the internal reference voltage Internal reference voltage spread over the temperature range VDD = 3V 10mV TCoeff(2) Temperature coefficient - 30 50 ppm/C tSTART(2) Startup time - 6 10 s 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production Table 84. Internal reference voltage calibration values Symbol VREFIN_CAL Parameter Raw data acquired at temperature of 30 C VDDA = 3.3 V DocID024030 Rev 10 Memory address 0x1FFF 7A2A - 0x1FFF 7A2B 165/239 198 Electrical characteristics 6.3.25 STM32F427xx STM32F429xx DAC electrical characteristics Table 85. DAC characteristics Symbol Parameter Conditions Min Typ VDDA Analog supply voltage - 1.7(1) - 3.6 V - VREF+ Reference supply voltage - 1.7(1) - 3.6 V VREF+ VDDA VSSA Ground - 0 - 0 V - 5 - - RLOAD(2) Resistive load RLOAD connected DAC output to VSSA buffer ON R LOAD connected to VDDA Max Unit Comments k 25 - - - - 15 When the buffer is OFF, the Minimum resistive load k between DAC_OUT and VSS to have a 1% accuracy is 1.5 M CLOAD(2) Capacitive load - - - 50 Maximum capacitive load at pF DAC_OUT pin (when the buffer is ON). DAC_O Lower DAC_OUT UT (2) voltage with buffer ON min - 0.2 - - V DAC_O Higher DAC_OUT UT voltage with buffer ON (2) max - - - VDDA - 0.2 V DAC_O Lower DAC_OUT UT voltage with buffer min(2) OFF - - 0.5 - mV - VREF+ - 1LSB RO(2) Impedance output with buffer OFF DAC_O Higher DAC_OUT UT voltage with buffer max(2) OFF DAC DC VREF current consumption in IVREF+(4) quiescent mode (Standby mode) 166/239 - - - - 170 It gives the maximum output excursion of the DAC. V 240 A - - 50 DocID024030 Rev 10 75 It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.7 V With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs STM32F427xx STM32F429xx Electrical characteristics Table 85. DAC characteristics (continued) Symbol Parameter DAC DC VDDA IDDA(4) current consumption in quiescent mode(3) Conditions Min Typ Max Unit Comments - - 280 380 A 625 With no load, worst code (0xF1C) at VREF+ = 3.6 V in A terms of DC consumption on the inputs With no load, middle code (0x800) on the inputs - - 475 - - - - - - 2 LSB Given for the DAC in 12-bit configuration. - - - 1 LSB Given for the DAC in 10-bit configuration. - - - 4 LSB Given for the DAC in 12-bit configuration. - - - 10 mV Given for the DAC in 12-bit configuration - - - 3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - - 12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V Gain Gain error error(4) - - - 0.5 % Given for the DAC in 12-bit configuration Settling time (full scale: for a 10-bit input code transition tSETTLIN between the lowest (4) and the highest input G codes when DAC_OUT reaches final value 4LSB - - 3 6 s CLOAD 50 pF, RLOAD 5 k Total Harmonic THD(4) Distortion Buffer ON - - - - dB CLOAD 50 pF, RLOAD 5 k Max frequency for a correct DAC_OUT Update change when small rate(2) variation in the input code (from code i to i+1LSB) - - - 1 MS/ CLOAD 50 pF, s RLOAD 5 k Differential non linearity Difference DNL(4) between two consecutive code1LSB) INL(4) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) Offset error (difference between Offset(4) measured value at Code (0x800) and the ideal value = VREF+/2) DocID024030 Rev 10 0.5 LSB Given for the DAC in 10-bit configuration. 167/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 85. DAC characteristics (continued) Symbol Conditions Min Typ Wakeup time from off tWAKEUP( state (Setting the ENx 4) bit in the DAC Control register) - - 6.5 10 CLOAD 50 pF, RLOAD 5 k s input code between lowest and highest possible ones. Power supply rejection ratio (to VDDA) (static DC measurement) - - -67 -40 dB No RLOAD, CLOAD = 50 pF PSRR+ (2) Parameter Max Unit Comments 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). 2. Guaranteed by design. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization. Figure 54. 12-bit buffered /non-buffered DAC %XIIHUHGQRQEXIIHUHG'$& %XIIHU 5/2$' ELW GLJLWDOWR DQDORJ FRQYHUWHU '$&[B287 &/2$' DLD 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 168/239 DocID024030 Rev 10 STM32F427xx STM32F429xx 6.3.26 Electrical characteristics FMC characteristics Unless otherwise specified, the parameters given in Table 86 to Table 101 for the FMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 except at VDD range 1.7 to 2.1V where OSPEEDRy[1:0] = 11 * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.17: I/O port characteristics for more details on the input/output characteristics. Asynchronous waveforms and timings Figure 55 through Figure 58 represent asynchronous waveforms and Table 86 through Table 93 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: * AddressSetupTime = 0x1 * AddressHoldTime = 0x1 * DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5) * BusTurnAroundDuration = 0x0 * For SDRAM memories, VDD ranges from 2.7 to 3.6 V and maximum frequency FMC_SDCLK = 90 MHz * For Mobile LPSDR SDRAM memories, VDD ranges from 1.7 to 1.95 V and maximum frequency FMC_SDCLK = 84 MHz DocID024030 Rev 10 169/239 198 Electrical characteristics STM32F427xx STM32F429xx Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW.% &-#?.% TV./%?.% T W./% T H.%?./% &-#?./% &-#?.7% TV!?.% &-#?!;= T H!?./% !DDRESS TV",?.% T H",?./% &-#?.",;= T H$ATA?.% T SU$ATA?./% TH$ATA?./% T SU$ATA?.% $ATA &-#?$;= T V.!$6?.% TW.!$6 &-#?.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Min Max Unit 2THCLK - 0.5 2 THCLK+0.5 ns 0 1 ns 2THCLK 2THCLK+ 0.5 ns FMC_NOE high to FMC_NE high hold time 0 - ns FMC_NEx low to FMC_A valid - 2 ns th(A_NOE) Address hold time after FMC_NOE high 0 - ns tv(BL_NE) FMC_NEx low to FMC_BL valid - 2 ns th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 - ns tsu(Data_NE) Data to FMC_NEx high setup time THCLK + 2.5 - ns THCLK +2 - ns tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) tsu(Data_NOE) 170/239 Parameter FMC_NE low time FMC_NEx low to FMC_NOE low FMC_NOE low time Data to FMC_NOEx high setup time DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) (continued) Symbol Parameter Min Max Unit th(Data_NOE) Data hold time after FMC_NOE high 0 - ns th(Data_NE) Data hold time after FMC_NEx high 0 - ns tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0 ns FMC_NADV low time - THCLK +1 ns tw(NADV) 1. CL = 30 pF. 2. Guaranteed by characterization results. Table 87. Asynchronous non-multiplexed SRAM/PSRAM/NOR read NWAIT timings(1)(2) Symbol Min Max FMC_NE low time 7THCLK+0.5 7THCLK+1 FMC_NWE low time 5THCLK - 1.5 5THCLK +2 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK+1.5 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+1 - tw(NE) tw(NOE) Parameter Unit ns 1. CL = 30 pF. 2. Guaranteed by characterization results. DocID024030 Rev 10 171/239 198 Electrical characteristics STM32F427xx STM32F429xx Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms TW.% &-#?.%X &-#?./% TV.7%?.% TW.7% T H.%?.7% &-#?.7% TV!?.% &-#?!;= TH!?.7% !DDRESS TV",?.% &-#?.",;= TH",?.7% .", TV$ATA?.% TH$ATA?.7% $ATA &-#?$;= T V.!$6?.% &-#?.!$6 TW.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) Parameter FMC_NE low time FMC_NEx low to FMC_NWE low FMC_NWE low time FMC_NWE high to FMC_NE high hold time FMC_NEx low to FMC_A valid th(A_NWE) Address hold time after FMC_NWE high tv(BL_NE) FMC_NEx low to FMC_BL valid Max Unit 3THCLK 3THCLK+1 ns THCLK - 0.5 THCLK+ 0.5 ns THCLK THCLK+ 0.5 ns THCLK +1.5 - ns - 0 ns THCLK+0.5 - ns - 1.5 ns THCLK+0.5 - ns th(BL_NWE) FMC_BL hold time after FMC_NWE high tv(Data_NE) Data to FMC_NEx low to Data valid - THCLK+ 2 ns th(Data_NWE) Data hold time after FMC_NWE high THCLK+0.5 - ns tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0.5 ns FMC_NADV low time - THCLK+ 0.5 ns tw(NADV) 1. CL = 30 pF. 2. Guaranteed by characterization results. 172/239 Min DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR write NWAIT timings(1)(2) Symbol Parameter Min Max Unit FMC_NE low time 8THCLK+1 8THCLK+2 ns FMC_NWE low time 6THCLK - 1 6THCLK+2 ns tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK+1.5 - ns th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid tw(NE) tw(NWE) 4THCLK+1 ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms TW.% &-#? .% TV./%?.% T H.%?./% &-#?./% T W./% &-#?.7% TH!?./% TV!?.% &-#? !;= !DDRESS TV",?.% TH",?./% &-#? .",;= .", TH$ATA?.% TSU$ATA?.% T V!?.% &-#? !$;= T V.!$6?.% TSU$ATA?./% TH$ATA?./% $ATA !DDRESS TH!$?.!$6 TW.!$6 &-#?.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 DocID024030 Rev 10 173/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 90. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol tw(NE) tv(NOE_NE) ttw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) Parameter Min Max Unit 3THCLK - 1 3THCLK+0.5 ns 2THCLK - 0.5 2THCLK ns THCLK - 1 THCLK+1 ns FMC_NOE high to FMC_NE high hold time 1 - ns FMC_NEx low to FMC_A valid - 2 ns FMC_NEx low to FMC_NADV low 0 2 ns THCLK - 0.5 THCLK+0.5 ns FMC_NE low time FMC_NEx low to FMC_NOE low FMC_NOE low time FMC_NADV low time th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high) 0 - ns th(A_NOE) Address hold time after FMC_NOE high THCLK - 0.5 - ns th(BL_NOE) FMC_BL time after FMC_NOE high 0 - ns FMC_NEx low to FMC_BL valid - 2 ns tv(BL_NE) tsu(Data_NE) Data to FMC_NEx high setup time THCLK+1.5 - ns tsu(Data_NOE) Data to FMC_NOE high setup time THCLK+1 - ns th(Data_NE) Data hold time after FMC_NEx high 0 - ns th(Data_NOE) Data hold time after FMC_NOE high 0 - ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Table 91. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)(2) Symbol tw(NE) tw(NOE) Parameter Min Max Unit FMC_NE low time 8THCLK+0.5 8THCLK+2 ns FMC_NWE low time 5THCLK - 1 5THCLK +1.5 ns 5THCLK +1.5 - ns tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 1. CL = 30 pF. 2. Guaranteed by characterization results. 174/239 DocID024030 Rev 10 4THCLK+1 ns STM32F427xx STM32F429xx Electrical characteristics Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms TW.% &-#? .%X &-#?./% TW.7% TV.7%?.% T H.%?.7% &-#?.7% TH!?.7% TV!?.% &-#? !;= !DDRESS TV",?.% &-#? .",;= TH",?.7% .", T V!?.% T V$ATA?.!$6 !DDRESS &-#? !$;= TH$ATA?.7% $ATA TH!$?.!$6 T V.!$6?.% TW.!$6 &-#?.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 Table 92. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) Parameter Min Max Unit 4THCLK 4THCLK+0.5 ns THCLK - 1 THCLK+0.5 ns FMC_NWE low time 2THCLK 2THCLK+0.5 ns FMC_NWE high to FMC_NE high hold time THCLK - ns - 0 ns 0.5 1 ns THCLK - 0.5 THCLK+ 0.5 ns THCLK - 2 - ns FMC_NE low time FMC_NEx low to FMC_NWE low FMC_NEx low to FMC_A valid FMC_NEx low to FMC_NADV low FMC_NADV low time FMC_AD(adress) valid hold time after FMC_NADV high) th(A_NWE) Address hold time after FMC_NWE high THCLK - ns th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK - 2 - ns tv(BL_NE) FMC_NEx low to FMC_BL valid - 2 ns tv(Data_NADV) FMC_NADV high to Data valid - THCLK +1.5 ns th(Data_NWE) Data hold time after FMC_NWE high THCLK +0.5 - ns 1. CL = 30 pF. 2. Guaranteed by characterization results. DocID024030 Rev 10 175/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 93. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2) Symbol tw(NE) tw(NWE) Parameter Min Max Unit FMC_NE low time 9THCLK 9THCLK+0.5 ns FMC_NWE low time 7THCLK 7THCLK+2 ns 6THCLK+1.5 - ns 4THCLK-1 - ns tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 1. CL = 30 pF. 2. Guaranteed by characterization results. Synchronous waveforms and timings Figure 59 through Figure 62 represent synchronous waveforms and Table 94 through Table 97 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: * BurstAccessMode = FMC_BurstAccessMode_Enable; * MemoryType = FMC_MemoryType_CRAM; * WriteBurst = FMC_WriteBurst_Enable; * CLKDivision = 1; (0 is not supported, see the STM32F4xx reference manual : RM0090) * DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period (with maximum FMC_CLK = 90 MHz). 176/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Figure 59. Synchronous multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &-#?#,+ $ATA LATENCY TD#,+, .%X, &-#?.%X T D#,+, .!$6, TD#,+( .%X( TD#,+, .!$6( &-#?.!$6 TD#,+, !6 TD#,+( !)6 &-#?!;= TD#,+, ./%, TD#,+( ./%( &-#?./% T D#,+, !$6 &-#?!$;= TD#,+, !$)6 TSU!$6 #,+( !$;= TH#,+( !$6 TSU!$6 #,+( $ TSU.7!)46 #,+( &-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( &-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( !$6 $ TH#,+( .7!)46 TH#,+( .7!)46 TH#,+( .7!)46 -36 Table 94. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol tw(CLK) Parameter FMC_CLK period Min Max Unit 2THCLK - 1 - ns - 0 ns THCLK - ns td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0 ns td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - ns td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) - 0 ns td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) 0 - ns td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - THCLK+0.5 ns td(CLKH-NOEH) FMC_CLK high to FMC_NOE high THCLK - 0.5 - ns td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 0.5 ns td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - ns DocID024030 Rev 10 177/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 94. Synchronous multiplexed NOR/PSRAM read timings(1)(2) (continued) Symbol Parameter Min Max Unit tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 5 - ns th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 0 - ns tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 - ns th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 - ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Figure 60. Synchronous multiplexed PSRAM write timings "53452. TW#,+ TW#,+ &-#?#,+ $ATA LATENCY TD#,+, .%X, TD#,+( .%X( &-#?.%X TD#,+, .!$6, TD#,+, .!$6( &-#?.!$6 TD#,+( !)6 TD#,+, !6 &-#?!;= TD#,+( .7%( TD#,+, .7%, &-#?.7% TD#,+, !$)6 TD#,+, !$6 &-#?!$;= TD#,+, $ATA TD#,+, $ATA !$;= $ $ &-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 TD#,+( .",( &-#?.", -36 178/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Table 95. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Min Max Unit 2THCLK - 1 - ns - 1.5 ns THCLK - ns td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0 ns td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - ns - 0 ns THCLK - ns - 0 ns THCLK -0.5 - ns tw(CLK) Parameter FMC_CLK period, VDD range= 2.7 to 3.6 V td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) td(CLKL-NWEL) FMC_CLK low to FMC_NWE low t(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3 ns td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - ns td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3 ns td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 0 - ns td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK -0.5 - ns tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 - ns th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 - ns 1. CL = 30 pF. 2. Guaranteed by characterization results. DocID024030 Rev 10 179/239 198 Electrical characteristics STM32F427xx STM32F429xx Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings TW#,+ TW#,+ &-#?#,+ TD#,+, .%X, TD#,+( .%X( $ATA LATENCY &-#?.%X TD#,+, .!$6, TD#,+, .!$6( &-#?.!$6 TD#,+( !)6 TD#,+, !6 &-#?!;= TD#,+, ./%, TD#,+( ./%( &-#?./% TSU$6 #,+( TH#,+( $6 TSU$6 #,+( &-#?$;= TH#,+( $6 $ &-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 TSU.7!)46 #,+( &-#?.7!)4 7!)4#&' B 7!)40/, B $ TSU.7!)46 #,+( T H#,+( .7!)46 TH#,+( .7!)46 -36 Table 96. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Min Max Unit 2THCLK - 1 - ns - 0.5 ns THCLK - ns FMC_CLK low to FMC_NADV low - 0 ns FMC_CLK low to FMC_NADV high 0 - ns td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) - 0 ns td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) THCLK - 0.5 - ns - THCLK+2 ns THCLK - 0.5 - ns 5 - ns tw(CLK) t(CLKL-NExL) td(CLKHNExH) td(CLKLNADVL) td(CLKLNADVH) Parameter FMC_CLK period FMC_CLK low to FMC_NEx low (x=0..2) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-NOEL) FMC_CLK low to FMC_NOE low td(CLKHNOEH) FMC_CLK high to FMC_NOE high tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 180/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Table 96. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) (continued) Symbol Parameter th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH- Max Unit 0 - ns 4 FMC_NWAIT valid after FMC_CLK high NWAIT) Min 0 1. CL = 30 pF. 2. Guaranteed by characterization results. Figure 62. Synchronous non-multiplexed PSRAM write timings TW#,+ TW#,+ &-#?#,+ TD#,+, .%X, TD#,+( .%X( $ATA LATENCY &-#?.%X TD#,+, .!$6, TD#,+, .!$6( &-#?.!$6 TD#,+( !)6 TD#,+, !6 &-#?!;= TD#,+, .7%, TD#,+( .7%( &-#?.7% TD#,+, $ATA TD#,+, $ATA $ &-#?$;= $ &-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TD#,+( .",( TH#,+( .7!)46 &-#?.", -36 Table 97. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol Min Max Unit 2THCLK - 1 - ns - 0.5 ns THCLK - ns td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0 ns td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - ns - 0 ns t(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) DocID024030 Rev 10 181/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 97. Synchronous non-multiplexed PSRAM write timings(1)(2) (continued) Symbol td(CLKH-AIV) td(CLKL-NWEL) Parameter Min Max Unit FMC_CLK high to FMC_Ax invalid (x=16...25) 0 - ns FMC_CLK low to FMC_NWE low - 0 ns THCLK -0.5 - ns td(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 2.5 ns td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 0 - ns td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK -0.5 - ns tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 1. CL = 30 pF. 2. Guaranteed by characterization results. PC Card/CompactFlash controller waveforms and timings Figure 63 through Figure 68 represent synchronous waveforms, and Table 98 and Table 99 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: * COM.FMC_SetupTime = 0x04; * COM.FMC_WaitSetupTime = 0x07; * COM.FMC_HoldSetupTime = 0x04; * COM.FMC_HiZSetupTime = 0x00; * ATT.FMC_SetupTime = 0x04; * ATT.FMC_WaitSetupTime = 0x07; * ATT.FMC_HoldSetupTime = 0x04; * ATT.FMC_HiZSetupTime = 0x00; * IO.FMC_SetupTime = 0x04; * IO.FMC_WaitSetupTime = 0x07; * IO.FMC_HoldSetupTime = 0x04; * IO.FMC_HiZSetupTime = 0x00; * TCLRSetupTime = 0; * TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. 182/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Figure 63. PC Card/CompactFlash controller waveforms for common memory read access &-#?.#%? &-#?.#%? TH.#%X !) TV.#%X ! &-#?!;= TH.#%X .2%' TH.#%X .)/2$ TH.#%X .)/72 TD.2%' .#%X TD.)/2$ .#%X &-#?.2%' &-#?.)/72 &-#?.)/2$ &-#?.7% TD.#%? ./% &-#?./% TW./% TSU$ ./% TH./% $ &-#?$;= -36 1. FMC_NCE4_2 remains high (inactive during 8-bit access. Figure 64. PC Card/CompactFlash controller waveforms for common memory write access &-#?.#%? &-#?.#%? (IGH TV.#%? ! TH.#%? !) &-#?!;= TH.#%? .2%' TH.#%? .)/2$ TH.#%? .)/72 TD.2%' .#%? TD.)/2$ .#%? &-#?.2%' &-#?.)/72 &-#?.)/2$ TD.#%? .7% TW.7% TD.7% .#%? &-#?.7% &-#?./% -%-X(): TD$ .7% TV.7% $ TH.7% $ &-#?$;= -36 DocID024030 Rev 10 183/239 198 Electrical characteristics STM32F427xx STM32F429xx Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read access &-#?.#%? TV.#%? ! &-#?.#%? TH.#%? !) (IGH &-#?!;= &-#?.)/72 &-#?.)/2$ TD.2%' .#%? TH.#%? .2%' &-#?.2%' &-#?.7% TD.#%? ./% TW./% TD./% .#%? &-#?./% TSU$ ./% TH./% $ &-#?$;= -36 1. Only data bits 0...7 are read (bits 8...15 are disregarded). 184/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Figure 66. PC Card/CompactFlash controller waveforms for attribute memory write access &-#?.#%? &-#?.#%? (IGH TV.#%? ! TH.#%? !) &-#?!;= &-#?.)/72 &-#?.)/2$ TD.2%' .#%? TH.#%? .2%' &-#?.2%' TD.#%? .7% TW.7% &-#?.7% TD.7% .#%? &-#?./% TV.7% $ &-#?$;= -36 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access &-#?.#%? &-#?.#%? TH.#%? !) TV.#%X ! &-#?!;= &-#?.2%' &-#?.7% &-#?./% &-#?.)/72 TW.)/2$ TD.)/2$ .#%? &-#?.)/2$ TSU$ .)/2$ TD.)/2$ $ &-#?$;= -36 DocID024030 Rev 10 185/239 198 Electrical characteristics STM32F427xx STM32F429xx Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access &-#?.#%? &-#?.#%? TV.#%X ! TH.#%? !) &-#?!;= &-#?.2%' &-#?.7% &-#?./% &-#?.)/2$ T D.#%? .)/72 TW.)/72 &-#?.)/72 !44X(): TV.)/72 $ TH.)/72 $ &-#?$;= -36 Table 98. Switching characteristics for PC Card/CF read and write cycles in attribute/common space(1)(2) Symbol Parameter Min Max Unit tv(NCEx-A) FMC_Ncex low to FMC_Ay valid - 0 ns th(NCEx_AI) FMC_NCEx high to FMC_Ax invalid 0 - ns td(NREG-NCEx) FMC_NCEx low to FMC_NREG valid - 1 ns th(NCEx-NREG) FMC_NCEx high to FMC_NREG invalid THCLK - 2 - ns td(NCEx-NWE) FMC_NCEx low to FMC_NWE low - 5THCLK ns 8THCLK - 0.5 8THCLK+0.5 ns tw(NWE) FMC_NWE low width td(NWE_NCEx) FMC_NWE high to FMC_NCEx high 5THCLK+1 - ns tV(NWE-D) FMC_NWE low to FMC_D[15:0] valid - 0 ns th(NWE-D) FMC_NWE high to FMC_D[15:0] invalid 9THCLK - 0.5 - ns td(D-NWE) FMC_D[15:0] valid before FMC_NWE high 13THCLK - 3 td(NCEx-NOE) tw(NOE) td(NOE_NCEx) tsu (D-NOE) th(NOE-D) FMC_NCEx low to FMC_NOE low FMC_NOE low width FMC_NOE high to FMC_NCEx high FMC_D[15:0] valid data before FMC_NOE high FMC_NOE high to FMC_D[15:0] invalid 1. CL = 30 pF. 2. Guaranteed by characterization results. 186/239 DocID024030 Rev 10 ns - 5THCLK ns 8 THCLK - 0.5 8 THCLK+0.5 ns 5THCLK - 1 - ns THCLK - ns 0 - ns STM32F427xx STM32F429xx Electrical characteristics Table 99. Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2) Symbol Parameter tw(NIOWR) FMC_NIOWR low width tv(NIOWR-D) FMC_NIOWR low to FMC_D[15:0] valid th(NIOWR-D) FMC_NIOWR high to FMC_D[15:0] invalid Min Max Unit 8THCLK - 0.5 - ns - 0 ns 9THCLK - 2 - ns - 5THCLK ns 5THCLK - ns - 5THCLK ns 6THCLK+2 - ns 8THCLK - 0.5 8THCLK+0.5 ns THCLK - ns 0 - ns td(NCE4_1-NIOWR) FMC_NCE4_1 low to FMC_NIOWR valid th(NCEx-NIOWR) FMC_NCEx high to FMC_NIOWR invalid td(NIORD-NCEx) FMC_NCEx low to FMC_NIORD valid th(NCEx-NIORD) FMC_NCEx high to FMC_NIORD) valid tw(NIORD) FMC_NIORD low width tsu(D-NIORD) FMC_D[15:0] valid before FMC_NIORD high td(NIORD-D) FMC_D[15:0] valid after FMC_NIORD high 1. CL = 30 pF. 2. Guaranteed by characterization results. NAND controller waveforms and timings Figure 69 through Figure 72 represent synchronous waveforms, and Table 100 and Table 101 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: * COM.FMC_SetupTime = 0x01; * COM.FMC_WaitSetupTime = 0x03; * COM.FMC_HoldSetupTime = 0x02; * COM.FMC_HiZSetupTime = 0x01; * ATT.FMC_SetupTime = 0x01; * ATT.FMC_WaitSetupTime = 0x03; * ATT.FMC_HoldSetupTime = 0x02; * ATT.FMC_HiZSetupTime = 0x01; * Bank = FMC_Bank_NAND; * MemoryDataWidth = FMC_MemoryDataWidth_16b; * ECC = FMC_ECC_Enable; * ECCPageSize = FMC_ECCPageSize_512Bytes; * TCLRSetupTime = 0; * TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. DocID024030 Rev 10 187/239 198 Electrical characteristics STM32F427xx STM32F429xx Figure 69. NAND controller waveforms for read access &-#?.#%X !,% &-#?! #,% &-#?! &-#?.7% TD!,% ./% TH./% !,% &-#?./% .2% TSU$ ./% TH./% $ &-#?$;= -36 Figure 70. NAND controller waveforms for write access &-#?.#%X !,% &-#?! #,% &-#?! TH.7% !,% TD!,% .7% &-#?.7% &-#?./% .2% TV.7% $ TH.7% $ &-#?$;= -36 188/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Figure 71. NAND controller waveforms for common memory read access &-#?.#%X !,% &-#?! #,% &-#?! TH./% !,% TD!,% ./% &-#?.7% TW./% &-#?./% TSU$ ./% TH./% $ &-#?$;= -36 Figure 72. NAND controller waveforms for common memory write access &-#?.#%X !,% &-#?! #,% &-#?! TD!,% ./% TW.7% TH./% !,% &-#?.7% &-#?. /% TD$ .7% TV.7% $ TH.7% $ &-#?$;= -36 Table 100. Switching characteristics for NAND Flash read cycles(1) Symbol tw(N0E) Parameter FMC_NOE low width Min Max Unit 4THCLK - 0.5 4THCLK+0.5 ns tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 9 - ns th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - ns td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3THCLK - 0.5 ns th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 3THCLK - 2 - ns 1. CL = 30 pF. DocID024030 Rev 10 189/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 101. Switching characteristics for NAND Flash write cycles(1) Symbol tw(NWE) Parameter FMC_NWE low width Min Max Unit 4THCLK 4THCLK+1 ns 0 - ns tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 3THCLK - 1 - ns td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5THCLK - 3 - ns - 3THCLK -0.5 ns 3THCLK - 1 - ns td(ALE-NWE) FMC_ALE valid before FMC_NWE low th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 1. CL = 30 pF. SDRAM waveforms and timings Figure 73. SDRAM read access waveforms (CL = 1) &-#?3$#,+ TD3$#,+,?!DD# TH3$#,+,?!DD2 TD3$#,+,?!DD2 &-#?!>@ 2OW N #OL #OL #OLI #OLN TH3$#,+,?!DD# TH3$#,+,?3.$% TD3$#,+,?3.$% &-#?3$.%;= TD3$#,+,?.2!3 TH3$#,+,?.2!3 &-#?3$.2!3 TH3$#,+,?.#!3 TD3$#,+,?.#!3 &-#?3$.#!3 &-#?3$.7% TSU3$#,+(?$ATA &-#?$;= TH3$#,+(?$ATA $ATA $ATA $ATAI $ATAN -36 190/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Table 102. SDRAM read timings(1)(2) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK - 0.5 2THCLK+0.5 tsu(SDCLKH _Data) Data input setup time 2 - th(SDCLKH_Data) Data input hold time 0 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL- SDNE) Chip select valid time - 0.5 th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS) SDNRAS valid time - 0.5 th(SDCLKL_SDNRAS) SDNRAS hold time 0 - td(SDCLKL_SDNCAS) SDNCAS valid time - 0.5 th(SDCLKL_SDNCAS) SDNCAS hold time 0 - Unit ns 1. CL = 30 pF on data and address lines. CL=15pF on FMC_SDCLK. 2. Guaranteed by characterization results. Table 103. LPSDR SDRAM read timings(1)(2) Symbol Parameter Min Max tW(SDCLK) FMC_SDCLK period 2THCLK - 0.5 2THCLK+0.5 tsu(SDCLKH_Data) Data input setup time 2.5 - th(SDCLKH_Data) Data input hold time 0 - td(SDCLKL_Add) Address valid time - 1 td(SDCLKL_SDNE) Chip select valid time - 1 th(SDCLKL_SDNE) Chip select hold time 1 - td(SDCLKL_SDNRAS SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 1 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1 th(SDCLKL_SDNCAS) SDNCAS hold time 1 - Unit ns 1. CL = 10 pF. 2. Guaranteed by characterization results. DocID024030 Rev 10 191/239 198 Electrical characteristics STM32F427xx STM32F429xx Figure 74. SDRAM write access waveforms &-#?3$#,+ TD3$#,+,?!DD# TH3$#,+,?!DD2 TD3$#,+,?!DD2 &-#?!>@ 2OW N #OL #OL #OLI #OLN TH3$#,+,?!DD# TH3$#,+,?3.$% TD3$#,+,?3.$% &-#?3$.%;= TH3$#,+,?.2!3 TD3$#,+,?.2!3 &-#?3$.2!3 TD3$#,+,?.#!3 TH3$#,+,?.#!3 TD3$#,+,?.7% TH3$#,+,?.7% &-#?3$.#!3 &-#?3$.7% TD3$#,+,?$ATA &-#?$;= TD3$#,+,?.", $ATA $ATA $ATAI $ATAN TH3$#,+,?$ATA &-#?.",;= -36 192/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Electrical characteristics Table 104. SDRAM write timings(1)(2) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK - 0.5 2THCLK+0.5 td(SDCLKL _Data) Data output valid time - 3.5 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL_SDNWE) SDNWE valid time - 1 th(SDCLKL_SDNWE) SDNWE hold time 0 - td(SDCLKL_ SDNE) Chip select valid time - 0.5 th(SDCLKL-_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS) SDNRAS valid time - 2 th(SDCLKL_SDNRAS) SDNRAS hold time 0 - td(SDCLKL_SDNCAS) SDNCAS valid time - 0.5 td(SDCLKL_SDNCAS) SDNCAS hold time 0 - td(SDCLKL_NBL) NBL valid time - 0.5 th(SDCLKL_NBL) NBLoutput time 0 - Unit ns 1. CL = 30 pF on data and address lines. CL=15pF on FMC_SDCLK. 2. Guaranteed by characterization results. Table 105. LPSDR SDRAM write timings(1)(2) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK - 0.5 2THCLK+0.5 td(SDCLKL _Data) Data output valid time - 5 th(SDCLKL _Data) Data output hold time 2 - td(SDCLKL_Add) Address valid time - 2.8 td(SDCLKL-SDNWE) SDNWE valid time - 2 th(SDCLKL-SDNWE) SDNWE hold time 1 - td(SDCLKL- SDNE) Chip select valid time - 1.5 th(SDCLKL- SDNE) Chip select hold time 1 - td(SDCLKL-SDNRAS) SDNRAS valid time - 1.5 th(SDCLKL-SDNRAS) SDNRAS hold time 1.5 - td(SDCLKL-SDNCAS) SDNCAS valid time - 1.5 td(SDCLKL-SDNCAS) SDNCAS hold time 1.5 - td(SDCLKL_NBL) NBL valid time - 1.5 th(SDCLKL-NBL) NBL output time 1.5 - Unit ns 1. CL = 10 pF. 2. Guaranteed by characterization results. DocID024030 Rev 10 193/239 198 Electrical characteristics 6.3.27 STM32F427xx STM32F429xx Camera interface (DCMI) timing specifications Unless otherwise specified, the parameters given in Table 106 for DCMI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 17, with the following configuration: * DCMI_PIXCLK polarity: falling * DCMI_VSYNC and DCMI_HSYNC polarity: high * Data formats: 14 bits Table 106. DCMI characteristics Symbol Parameter Min Max - 0.4 - 54 MHz Pixel clock input duty cycle 30 70 % tsu(DATA) Data input setup time 2 - th(DATA) Data input hold time 2.5 - tsu(HSYNC) tsu(VSYNC) DCMI_HSYNC/DCMI_VSYNC input setup time 0.5 - th(HSYNC) th(VSYNC) DCMI_HSYNC/DCMI_VSYNC input hold time 1 - Frequency ratio DCMI_PIXCLK/fHCLK DCMI_PIXCLK Pixel clock input DPixel Unit ns Figure 75. DCMI timing diagram '&0,B3,;&/. '&0,B3,;&/. WVX +6<1& WK +6<1& '&0,B+6<1& WVX 96<1& WK +6<1& '&0,B96<1& WVX '$7$ WK '$7$ '$7$>@ 069 194/239 DocID024030 Rev 10 STM32F427xx STM32F429xx 6.3.28 Electrical characteristics LCD-TFT controller (LTDC) characteristics Unless otherwise specified, the parameters given in Table 107 for LCD-TFT are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 17, with the following configuration: * LCD_CLK polarity: high * LCD_DE polarity : low * LCD_VSYNC and LCD_HSYNC polarity: high * Pixel formats: 24 bits Table 107. LTDC characteristics Symbol Parameter Min Max Unit fCLK LTDC clock output frequency - 83 MHz DCLK LTDC clock output duty cycle 45 55 % tw(CLKH) tw(CLKL) Clock High time, low time tv(DATA) Data output valid time - 3.5 th(DATA) Data output hold time 1.5 - HSYNC/VSYNC/DE output valid time - 2.5 HSYNC/VSYNC/DE output hold time 2 - tv(HSYNC) tv(VSYNC) tw(CLK)/2 - 0.5 tw(CLK)/2+0.5 ns tv(DE) th(HSYNC) th(VSYNC) th(DE) DocID024030 Rev 10 195/239 198 Electrical characteristics STM32F427xx STM32F429xx Figure 76. LCD-TFT horizontal timing diagram W&/. /&'B&/. /&'B96<1& WY +6<1& WY +6<1& /&'B+6<1& WK '( WY '( /&'B'( WY '$7$ /&'B5>@ /&'B*>@ /&'B%>@ 1JYFM 1JYFM 1JYFM / WK '$7$ +6<1& +RUL]RQWDO ZLGWK EDFNSRUFK $FWLYHZLGWK +RUL]RQWDO EDFNSRUFK 2QHOLQH 069 Figure 77. LCD-TFT vertical timing diagram W&/. /&'B&/. WY 96<1& WY 96<1& /&'B96<1& /&'B5>@ /&'B*>@ /&'B%>@ - LINES DATA 96<1& 9HUWLFDO ZLGWK EDFNSRUFK $FWLYHZLGWK 9HUWLFDO EDFNSRUFK 2QHIUDPH 069 196/239 DocID024030 Rev 10 STM32F427xx STM32F429xx 6.3.29 Electrical characteristics SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 108 for the SDIO/MMC interface are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.17: I/O port characteristics for more details on the input/output characteristics. Figure 78. SDIO high-speed mode Figure 79. SD default mode DocID024030 Rev 10 197/239 198 Electrical characteristics STM32F427xx STM32F429xx Table 108. Dynamic characteristics: SD / MMC characteristics(1)(2) Symbol Parameter Conditions Min fPP Clock frequency in data transfer mode 0 - SDIO_CK/fPCLK2 frequency ratio - tW(CKL) Clock low time fpp =48 MHz tW(CKH) Clock high time fpp =48 MHz Typ Max Unit 48 MHz - 8/3 - 8.5 9 - 8.3 10 - ns CMD, D inputs (referenced to CK) in MMC and SD HS mode tISU Input setup time HS fpp =48 MHz 3.5 - - tIH Input hold time HS fpp =48 MHz 0 - - ns CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time HS fpp =48 MHz - 4.5 7 tOH Output hold time HS fpp =48 MHz 3 - - ns CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD fpp =24 MHz 1.5 - - tIHD Input hold time SD fpp =24 MHz 0.5 - - ns CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fpp =24 MHz - 4.5 6.5 tOHD Output hold default time SD fpp =24 MHz 3.5 - - ns 1. Guaranteed by characterization results. 2. VDD = 2.7 to 3.6 V. 6.3.30 RTC characteristics Table 109. RTC characteristics 198/239 Symbol Parameter - fPCLK1/RTCCLK frequency ratio Conditions Any read/write operation from/to an RTC register DocID024030 Rev 10 Min Max 4 - Package information 7 STM32F427xx STM32F429xx Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.1 LQFP100 package information Figure 80. LQFP100 -100-pin, 14 x 14 mm low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.% $ , $ ! + CCC # , $ 0). )$%.4)&)#!4)/. E 1. Drawing is not to scale. 198/239 % % % B DocID024030 Rev 10 ,?-%?6 STM32F427xx STM32F429xx Package information Table 110. LQPF100 100-pin, 14 x 14 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID024030 Rev 10 199/239 232 Package information STM32F427xx STM32F429xx Figure 81. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint AIC 1. Dimensions are expressed in millimeters. 200/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Package information Device marking for LQFP100 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below. Figure 82. LQFP100 marking example (package top view) 3URGXFWLGHQWLILFDWLRQ 45.' 5HYLVLRQFRGH 7*53 'DWHFRGH \HDUZHHN :88 3LQ LGHQWLILHU 67ORJR DLG 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. DocID024030 Rev 10 201/239 232 Package information 7.2 STM32F427xx STM32F429xx WLCSP143 package information Figure 83. WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package outline $EDOOORFDWLRQ H EEE ) * 'HWDLO$ H H H $ $ $ %RWWRPYLHZ %XPSVLGH 6LGHYLHZ ' %XPS $ HHH $ ( E FFF GGG $RULHQWDWLRQ UHIHUHQFH 7RSYLHZ :DIHUEDFNVLGH = ;< = 6HDWLQJ SODQH 'HWDLO$ 5RWDWHG DDD $:(B0(B9 1. Drawing is not to scale. 202/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Package information Table 111. WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 0.155 0.175 0.195 - 0.0069 - A2 - 0.380 - - 0.0150 - - 0.025 - - 0.0010 - b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 4.486 4.521 4.556 0.1766 0.1780 0.1794 E 5.512 5.547 5.582 0.2170 0.2184 0.2198 e - 0.400 - - 0.0157 - e1 - 4.000 - - 0.1575 - e2 - 4.800 - - 0.1890 - F - 0.2605 - - 0.0103 - G - 0.3735 - - 0.0147 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 A3 (2) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating. 3. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Figure 84. WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale recommended footprint 'SDG 'VP DocID024030 Rev 10 069 203/239 232 Package information STM32F427xx STM32F429xx Table 112. WLCSP143 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 260 m max. (circular) Dpad 220 m recommended Dsm 300 m min. (for 260 m diameter pad) PCB pad design Non-solder mask defined via underbump allowed. Device marking for WLCSP143 The following figure gives an example of topside marking orientation versus ball A 1 identifier location. Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below. Figure 85. WLCSP143 marking example (package top view) EDOO$ 3URGXFW LGHQWLILFDWLRQ 67)=,< 'DWHFRGH <HDU:HHN < :: 5 5HYLVLRQFRGH 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 204/239 DocID024030 Rev 10 STM32F427xx STM32F429xx LQFP144 package information Figure 86. LQFP144-144-pin, 20 x 20 mm low-profile quad flat package outline 6($7,1* 3/$1( F $ $ & $ PP *$8*(3/$1( ' / ' . $ FFF & / ' ( 3,1 ( ( E 7.3 Package information ,'(17,),&$7,21 H $B0(B9 1. Drawing is not to scale. DocID024030 Rev 10 205/239 232 Package information STM32F427xx STM32F429xx Table 113. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.874 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.689 - E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 206/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Package information Figure 87. LQPF144- 144-pin,20 x 20 mm low-profile quad flat package recommended footprint DLH 1. Dimensions are expressed in millimeters. DocID024030 Rev 10 207/239 232 Package information STM32F427xx STM32F429xx Device marking for LQFP144 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below. Figure 88. LQFP144 marking example (package top view) 5HYLVLRQFRGH 3URGXFW LGHQWLILFDWLRQ 5 )=(7 'DWHFRGH <HDU:HHN < :: 3LQ DLH 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 208/239 DocID024030 Rev 10 STM32F427xx STM32F429xx 7.4 Package information LQFP176 package information Figure 89. LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package outline C ! ! ! # 3EATING PLANE MM GAUGE PLANE K ! , ($ 0). )$%.4)&)#!4)/. , $ :% % (% E :$ B 4?-%?6 1. Drawing is not to scale. Table 114. LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 - 1.450 0.0531 - 0.0571 b 0.170 - 0.270 0.0067 - 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 23.900 - 24.100 0.9409 - 0.9488 HD 25.900 - 26.100 1.0197 - 1.0276 DocID024030 Rev 10 209/239 232 Package information STM32F427xx STM32F429xx Table 114. LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max ZD - 1.250 - - 0.0492 - E 23.900 - 24.100 0.9409 - 0.9488 HE 25.900 - 26.100 1.0197 - 1.0276 ZE - 1.250 - - 0.0492 - e - 0.500 - - 0.0197 - 0.450 - 0.750 0.0177 - 0.0295 L1 - 1.000 - - 0.0394 - k 0 - 7 0 - 7 ccc - - 0.080 - - 0.0031 (2) L 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. L dimension is measured at gauge plane at 0.25 mm above the seating plane. 210/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Package information Figure 90. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint 4?&0?6 1. Dimensions are expressed in millimeters. DocID024030 Rev 10 211/239 232 Package information STM32F427xx STM32F429xx Device marking for LQFP176 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below. Figure 91. LQFP176 marking (package top view) 3URGXFW LGHQWLILFDWLRQ 670),,7 5HYLVLRQFRGH <:: 'DWHFRGH <HDUZHHN 5 3LQ LGHQWLILHU DLG 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 212/239 DocID024030 Rev 10 STM32F427xx STM32F429xx LQFP208 package information Figure 92. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline 6($7,1* 3/$1( & F $ $ $ FFF & PP $ *$8*(3/$1( . / ' / ' ' 3,1 ,'(17,),&$7,21 ( ( ( E 7.5 Package information H 6)@.&@7 1. Drawing is not to scale. DocID024030 Rev 10 213/239 232 Package information STM32F427xx STM32F429xx Table 115. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 -- - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 29.800 30.000 30.200 1.1732 1.1811 1.1890 D1 27.800 28.000 28.200 1.0945 1.1024 1.1102 D3 - 25.500 - - 1.0039 - E 29.800 30.000 30.200 1.1732 1.1811 1.1890 E1 27.800 28.000 28.200 1.0945 1.1024 1.1102 E3 - 25.500 - - 1.0039 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7.0 0 3.5 7.0 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 214/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Package information Figure 93. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package recommended footprint 8+B)3B9 1. Dimensions are expressed in millimeters. DocID024030 Rev 10 215/239 232 Package information STM32F427xx STM32F429xx Device marking for LQFP208 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below. Figure 94. LQFP208 marking example (package top view) 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 5 670)%,7 3LQ LGHQWLILHU 'DWHFRGH \HDUZHHN <:: 069 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 216/239 DocID024030 Rev 10 STM32F427xx STM32F429xx 7.6 Package information UFBGA169 package information Figure 95. UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package outline = 6HDWLQJSODQH $ $ GGG = $ $ $ E 6,'(9,(: $EDOO LGHQWLILHU $EDOO LQGH[DUHD ; ( ( H ) $ ) ' ' H < 1 %277209,(: 7239,(: E EDOOV HHH 0 = ; < III 0 = $<9B0(B9 1. Drawing is not to scale. Table 116. UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 - 0.130 - - 0.0051 - A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 D 6.950 7.000 7.050 0.2736 0.2756 0.2776 D1 5.950 6.000 6.050 0.2343 0.2362 0.2382 E 6.950 7.000 7.050 0.2736 0.2756 0.2776 E1 5.950 6.000 6.050 0.2343 0.2362 0.2382 e - 0.500 - - 0.0197 - DocID024030 Rev 10 217/239 232 Package information STM32F427xx STM32F429xx Table 116. UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max F 0.450 0.500 0.550 0.0177 0.0197 0.0217 ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 96. UFBGA169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array recommended footprint 'SDG 'VP 069 Table 117. UFBGA169 recommended PCB design rules (0.5 mm pitch BGA) Dimension Note: Recommended values Pitch 0.5 Dpad 0.27 mm Dsm 0.35 mm typ. (depends on the soldermask registration tolerance) Solder paste 0.27 mm aperture diameter. Non-solder mask defined (NSMD) pads are recommended. 4 to 6 mils solder paste screen printing process. 218/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Package information Device marking for UFBGA169 The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below. Figure 97. UFBGA169 marking example (package top view) %DOO$ LGHQWLILHU 670) 3URGXFW LGHQWLILFDWLRQ $,+ 'DWHFRGH <HDUZHHN < :: 5HYLVLRQ FRGH 5 069 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. DocID024030 Rev 10 219/239 232 Package information 7.7 STM32F427xx STM32F429xx UFBGA176+25 package information Figure 98. UFBGA176+25 - ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch ball grid array package outline & ^ $ $EDOO LGHQWLILHU ( $EDOO LQGH[ DUHD $ ' Z KddKDs/t E EDOOV dKWs/t HHH 0 & $ III 0 & $(B0(B9 1. Drawing is not to scale. Table 118. UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data inches(1) millimeters Symbol 220/239 Min. Typ. Max. Min. Typ. Max. A - - 0.600 - - 0.0236 A1 - - 0.110 - - 0.0043 A2 - 0.130 - - 0.0051 - A3 - 0.450 - - 0.0177 - A4 - 0.320 - - 0.0126 - b 0.240 0.290 0.340 0.0094 0.0114 0.0134 D 9.850 10.000 10.150 0.3878 0.3937 0.3996 D1 - 9.100 - - 0.3583 - E 9.850 10.000 10.150 0.3878 0.3937 0.3996 E1 - 9.100 - - 0.3583 - e - 0.650 - - 0.0256 - Z - 0.450 - - 0.0177 - ddd - - 0.080 - - 0.0031 DocID024030 Rev 10 STM32F427xx STM32F429xx Package information Table 118. UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 99. UFBGA176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package recommended footprint 'SDG 'VP &Ws Table 119. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) Dimension Recommended values Pitch 0.65 mm Dpad 0.300 mm Dsm 0.400 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.300 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm DocID024030 Rev 10 221/239 232 Package information STM32F427xx STM32F429xx Device marking for UFBGA176+25 The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below. Figure 100. UFBGA176+25 marking example (package top view) 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 5 670) ,,+8 'DWHFRGH \HDUZHHN < :: %DOO LQGHQWLILHU 069 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 222/239 DocID024030 Rev 10 STM32F427xx STM32F429xx 7.8 Package information TFBGA216 package information Figure 101. TFBGA216 - 216 ball 13 x 13 mm 0.8 mm pitch thin fine pitch ball grid array package outline = 6HDWLQJSODQH GGG = $ $ $ ' H $EDOO $EDOO LGHQWLILHU LQGH[DUHD ) ; ' $ * ( H ( < 5 %277209,(: E EDOOV HHH 0 = < ; III 0 = 7239,(: $/B0(B9 1. Drawing is not to scale. Table 120. TFBGA216 - 216 ball 13 x 13 mm 0.8 mm pitch thin fine pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.100 - - 0.0433 A1 0.150 - - 0.0059 - - A2 - 0.760 - - 0.0299 - b 0.350 0.400 0.450 0.0138 0.0157 0.0177 D 12.850 13.000 13.150 0.5118 0.5118 0.5177 D1 - 11.200 - - 0.4409 - E 12.850 13.000 13.150 0.5118 0.5118 0.5177 E1 - 11.200 - - 0.4409 - e - 0.800 - - 0.0315 - F - 0.900 - - 0.0354 - ddd - - 0.100 - - 0.0039 DocID024030 Rev 10 223/239 232 Package information STM32F427xx STM32F429xx Table 120. TFBGA216 - 216 ball 13 x 13 mm 0.8 mm pitch thin fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Device marking for TFBGA176 The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below. Figure 102. TFBGA176 marking example (package top view) 3URGXFWLGHQWLILFDWLRQ 670) 5HYLVLRQFRGH 1,+ 5 %DOO$LGHQWLILHU 'DWHFRGH \HDUZHHN < :: 069 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 224/239 DocID024030 Rev 10 STM32F427xx STM32F429xx 7.9 Package information Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: * TA max is the maximum ambient temperature in C, * JA is the package junction-to-ambient thermal resistance, in C/W, * PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), * PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 121. Package thermal characteristics Symbol JA Parameter Value Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch 43 Thermal resistance junction-ambient WLCSP143 31.2 Thermal resistance junction-ambient LQFP144 - 20 x 20 mm / 0.5 mm pitch 40 Thermal resistance junction-ambient LQFP176 - 24 x 24 mm / 0.5 mm pitch 38 Thermal resistance junction-ambient LQFP208 - 28 x 28 mm / 0.5 mm pitch 19 Thermal resistance junction-ambient UFBGA169 - 7 x 7mm / 0.5 mm pitch 52 Thermal resistance junction-ambient UFBGA176 - 10x 10 mm / 0.5 mm pitch 39 Thermal resistance junction-ambient TFBGA216 - 13 x 13 mm / 0.8 mm pitch 29 Unit C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. DocID024030 Rev 10 225/239 232 Part numbering 8 STM32F427xx STM32F429xx Part numbering Table 122. Ordering information scheme Example: STM32 F 429 V I T 6 xxx Device family STM32 = Arm-based 32-bit microcontroller Product type F = general-purpose Device subfamily 427= STM32F427xx, USB OTG FS/HS, camera interface, Ethernet 429= STM32F429xx, USB OTG FS/HS, camera interface, Ethernet, LCD-TFT Pin count V = 100 pins Z = 143 and 144 pins A = 169 pins I = 176 pins B = 208 pins N = 216 pins Flash memory size E = 512 Kbytes of Flash memory G = 1024 Kbytes of Flash memory I = 2048 Kbytes of Flash memory Package T = LQFP H = BGA Y = WLCSP Temperature range 6 = Industrial temperature range, -40 to 85 C. 7 = Industrial temperature range, -40 to 105 C. Options xxx = programmed parts TR = tape and reel For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 226/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Appendix A Recommendations when using internal reset OFF Recommendations when using internal reset OFF When the internal reset is OFF, the following integrated features are no longer supported: A.1 * The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled. * The brownout reset (BOR) circuitry must be disabled. * The embedded programmable voltage detector (PVD) is disabled. * VBAT functionality is no more available and VBAT pin should be connected to VDD. * The over-drive mode is not supported. Operating conditions Table 123. Limitations depending on the operating power supply range Operating power supply range ADC operation Maximum Flash memory access frequency with no wait states (fFlashmax) VDD =1.7 to 2.1 V(3) Conversion time up to 1.2 Msps 20 MHz(4) Maximum Flash memory access frequency with wait states (1)(2) 168 MHz with 8 wait states and over-drive OFF I/O operation Possible Flash memory operations 8-bit erase and - No I/O program compensation operations only 1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required. 2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state program execution. 3. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 3.17.1: Internal reset ON). 4. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power. DocID024030 Rev 10 227/239 232 Application block diagrams Appendix B B.1 STM32F427xx STM32F429xx Application block diagrams USB OTG full speed (FS) interface solutions Figure 103. USB controller configured as peripheral-only and used in Full speed mode 6$$ 6 TO 6$$ 6OLATGE REGULATOR 6"53 $- /3#?). 0!0" $0 0!0" 633 /3#?/54 53" 3TD " CONNECTOR 34-&XX -36 1. External voltage regulator only needed when building a VBUS powered device. 2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. Figure 104. USB controller configured as host-only and used in full speed mode 6$$ %. '0)/ '0)/ )21 /VERCURRENT #URRENT LIMITER POWER SWITCH 6 0WR 6"53 /3#?). 0!0" 0!0" $$0 633 /3#?/54 53" 3TD ! CONNECTOR 34-&XX -36 1. The current limiter is required only if the application has to support a VBUS powered device. A basic power switch can be used if 5 V are available on the application board. 2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. 228/239 DocID024030 Rev 10 STM32F427xx STM32F429xx Application block diagrams Figure 105. USB controller configured in dual mode and used in full speed mode 6$$ 6 TO 6$$ VOLTAGE REGULATOR 6$$ '0)/ )21 /VERCURRENT #URRENT LIMITER POWER SWITCH 6 0WR 34-&XX 0!0" 0!0" /3#?). /3#?/54 0!0" 0!0" 6"53 $$0 )$ 633 53"MICRO !" CONNECTOR '0)/ %. -36 1. External voltage regulator only needed when building a VBUS powered device. 2. The current limiter is required only if the application has to support a VBUS powered device. A basic power switch can be used if 5 V are available on the application board. 3. The ID pin is required in dual role only. 4. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. DocID024030 Rev 10 229/239 232 Application block diagrams B.2 STM32F427xx STM32F429xx USB OTG high speed (HS) interface solutions Figure 106. USB controller configured as peripheral, host, or dual-mode and used in high speed mode 34-&XX &3 0(9 53" (3 /4' #TRL $0 $- NOT CONNECTED $0 5,0)?#,+ $- 5,0)?$;= 5,0) )$ 5,0)?$)2 6"53 5,0)?340 53" CONNECTOR 633 5,0)?.84 (IGH SPEED /4' 0(9 0,, 84 OR -(Z 84 -#/ OR -#/ 8) -36 1. It is possible to use MCO1 or MCO2 to save a crystal. It is however not mandatory to clock the STM32F42x with a 24 or 26 MHz crystal when using USB HS. The above figure only shows an example of a possible connection. 2. The ID pin is required in dual role only. 230/239 DocID024030 Rev 10 STM32F427xx STM32F429xx B.3 Application block diagrams Ethernet interface solutions Figure 107. MII mode using a 25 MHz crystal 34- -#5 -))?48?#,+ -))?48?%. -))?48$;= -))?#23 -))?#/, %THERNET -!# (#,+ )%%% 040 4IMER INPUT TRIGGER 4IMESTAMP 4)- COMPARATOR %THERNET 0(9 -)) PINS -))?28?#,+ -))?28$;= -))?28?$6 -))?28?%2 -)) -$# PINS -$)/ -$# 003?/54 84!, -(Z /3# 0,, (#,+ -#/-#/ 0(9?#,+ -(Z 84 -36 1. fHCLK must be greater than 25 MHz. 2. Pulse per second when using IEEE1588 PTP optional signal. Figure 108. RMII with a 50 MHz oscillator 34- -#5 %THERNET 0(9 2-))?48?%. %THERNET -!# 2-))?48$;= 2-))?28$;= (#,+ 2-))?#28?$6 2-))?2%&?#,+ )%%% 040 4IMER INPUT TRIGGER 4IMESTAMP 4)- COMPARATOR 2-)) PINS 2-)) -$# PINS -$)/ -$# OR OR -(Z SYNCHRONOUS -(Z /3# -(Z 0,, (#,+ 0(9?#,+ -(Z 84 -(Z -36 1. fHCLK must be greater than 25 MHz. DocID024030 Rev 10 231/239 232 Application block diagrams STM32F427xx STM32F429xx Figure 109. RMII with a 25 MHz crystal and PHY with PLL 34-& -#5 %THERNET 0(9 2-))?48?%. %THERNET -!# 2-))?48$;= 2-))?28$;= (#,+ )%%% 040 2-))?#28?$6 2-))?2%&?#,+ 2-)) PINS 2%&?#,+ -$)/ 4IMER INPUT TRIGGER 4IMESTAMP 4)- COMPARATOR 2-)) -$# PINS -$# OR OR -(Z SYNCHRONOUS -(Z 84!, -(Z /3# 0,, (#,+ 0,, -#/-#/ 0(9?#,+ -(Z 84 -36 1. fHCLK must be greater than 25 MHz. 2. The 25 MHz (PHY_CLK) must be derived directly from the HSE oscillator, before the PLL block. 232/239 DocID024030 Rev 10 STM32F427xx STM32F429xx 9 Revision history Revision history Table 124. Document revision history Date Revision 19-Mar-2013 1 Initial release. 2 Added STM32F429xx part numbers and related informations. STM32F427xx part numbers: Replaced FSMC by FMC added Chrom-ART Accelerator and SAI interface. Increased core, timer, GPIOs, SPI maximum frequencies Updated Figure 8.Updated Figure 9. Removed note in Section *: Standby mode. Updated Figure 18. Updated Table 10: STM32F427xx and STM32F429xx pin and ball definitions and Table 12: STM32F427xx and STM32F429xx alternate function mapping.. Modified Figure 19: Memory map. Updated Table 17: General operating conditions, Table 18: Limitations depending on the operating power supply range. Removed note 1 in Table 22: reset and power control block characteristics. Added Table 23: Over-drive switching characteristics. Updated Section : Typical and maximum current consumption, Table 34: Switching output I/O current consumption, Table 35: Peripheral current consumption and Section : On-chip peripheral current consumption. Updated Table 36: Low-power mode wakeup timings. Modified Section : High-speed external user clock generated from an external source, Section : Low-speed external user clock generated from an external source, and Section 6.3.10: Internal clock source characteristics. Updated Table 43: Main PLL characteristics and Table 45: PLLISAI (audio and LCD-TFT PLL) characteristics. Updated Table 52: EMI characteristics. Updated Table 57: Output voltage characteristics and Table 58: I/O AC characteristics. Updated Table 60: TIMx characteristics, Table 61: I2C characteristics, Table 62: SPI dynamic characteristics, Section : SAI characteristics. Updated Table 102: SDRAM read timings and Table 104: SDRAM write timings. 10-Sep-2013 Changes DocID024030 Rev 10 233/239 238 Revision history STM32F427xx STM32F429xx Table 124. Document revision history Date 24-Jan-2014 234/239 Revision Changes 3 Added STM32F429xE part numbers featuring 512 Mbytes of Flash memory and UFBGA169 package. Added LPSDR SDRAM. Changed INTN into INTR in Figure 4: STM32F427xx and STM32F429xx block diagram. Added note 4 in Table 2: STM32F427xx and STM32F429xx features and peripheral counts. Updated Section 3.15: Boot modes. Updated for PA4 and PA5 in Table 10: STM32F427xx and STM32F429xx pin and ball definitions. Added VIN for BOOT0 pins in Table 14: Voltage characteristics. Updated Note 6., added Note 1.,and updated maximum VIN for B pins in Table 17: General operating conditions. Updated maximum Flash memory access frequency with wait states for VDD =1.8 to 2.1 V in Table 18: Limitations depending on the operating power supply range. Updated Table 24: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled except prefetch) or RAM and Table 25: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled). Updated Table 30: Typical current consumption in Run mode, code with data processing running from Flash memory or RAM, regulator ON (ART accelerator enabled except prefetch), VDD=1.7 V, Table 31: Typical current consumption in Run mode, code with data processing running from Flash memory, regulator OFF (ART accelerator enabled except prefetch), and Table 32: Typical current consumption in Sleep mode, regulator ON, VDD=1.7 V. Updated Table 57: Output voltage characteristics. Updated Table 58: I/O AC characteristics. Added Figure 35. Updated th(SDA), tr(SDA) and tr(SCL) and added tSP in Table 61: I2C characteristics. Updated fSCK in Table 62: SPI dynamic characteristics. Updated Table 70: Dynamic characteristics: USB ULPI. Updated Section 6.3.26: FMC characteristics conditions. Updated Figure 73: SDRAM read access waveforms (CL = 1) and Figure 74: SDRAM write access waveforms. Added Table 103: LPSDR SDRAM read timings and Table 105: LPSDR SDRAM write timings. Updated Table 102: SDRAM read timings and Table 104: SDRAM write timings and added note 2.Table 108: Dynamic characteristics: SD / MMC characteristics. DocID024030 Rev 10 STM32F427xx STM32F429xx Revision history Table 124. Document revision history Date 24-Apr-2014 Revision Changes 4 In the whole document, minimum supply voltage changed to 1.7 V when external power supply supervisor is used. Added DCMI_VSYNC alternate function on PG9 and updated note 6. in Table 10: STM32F427xx and STM32F429xx pin and ball definitions and Table 12: STM32F427xx and STM32F429xx alternate function mapping. Added note 2.belowFigure 16: STM32F42x UFBGA169 ballout. Changed SVGA (800x600) into XGA1024x768) on cover page and in Section 3.10: LCD-TFT controller (available only on STM32F429xx). Updated Section 3.18.2: Regulator OFF. Updated signal corresponding to pin L5 in Figure 12: STM32F42x WLCSP143 ballout. Added ACCHSE in Table 39: HSE 4-26 MHz oscillator characteristics and ACCLSE in Table 40: LSE oscillator characteristics (fLSE = 32.768 kHz). Updated Table 53: ESD absolute maximum ratings. Updated VIH in Table 56: I/O static characteristics. Added condition VDD>1.7 V in Table 58: I/O AC characteristics. Updated conditions in Table 62: SPI dynamic characteristics. Added ZDRV in Table 67: USB OTG full speed electrical characteristics Removed note 3 in Table 80: Temperature sensor characteristics. Added Figure 82: LQFP100 marking example (package top view), Figure 85: WLCSP143 marking example (package top view), Figure 88: LQFP144 marking example (package top view), Figure 91: LQFP176 marking (package top view), Figure 94: LQFP208 marking example (package top view), Figure 97: UFBGA169 marking example (package top view) and Figure 100: UFBGA176+25 marking example (package top view). Added Appendix A: Recommendations when using internal reset OFF. Removed Internal reset OFF hardware connection appendix. DocID024030 Rev 10 235/239 238 Revision history STM32F427xx STM32F429xx Table 124. Document revision history Date Revision Changes Update SPI/IS2 in Table 2: STM32F427xx and STM32F429xx features and peripheral counts. Updated LQFP208 in Table 4: Regulator ON/OFF and internal reset ON/OFF availability. Updated Figure 19: Memory map. Changed PLS[2:0]=101 (falling edge) maximum value in Table 22: reset and power control block characteristics. 19-Feb-2015 236/239 5 Updated current consumption with all peripherals disabled in Table 24: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled except prefetch) or RAM. Updated note 1. in Table 28: Typical and maximum current consumptions in Standby mode. Updated tWUSTOP in Table 36: Low-power mode wakeup timings. Updated ESD standards and Table 53: ESD absolute maximum ratings. Updated Table 56: I/O static characteristics. Section : I2C interface characteristics: updated section introduction, removed Table I2C characteristics, Figure I2C bus AC waveforms and measurement circuit and Table SCL frequency; added Table 61: I2C analog filter characteristics. Updated measurement conditions in Table 62: SPI dynamic characteristics. Updated Figure 51: Typical connection diagram using the ADC. Updated Section : Device marking for LQFP100. Updated Figure 83: WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package outline and Table 111: WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package mechanical data; added Figure 84: WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale recommended footprint and Table 112: WLCSP143 recommended PCB design rules (0.4 mm pitch). Updated Figure 85: WLCSP143 marking example (package top view) and related note. Updated Section : Device marking for WLCSP143. Updated Section : Device marking for LQFP144. Updated Section : Device marking for LQFP176. Updated Figure 92: LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline; Updated Section : Device marking for LQFP208. Modified UFBGA169 pitch, updated Figure 95: UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package outline and Table 116: UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data; updated Section : Device marking for LQFP208. updated Section : Device marking for UFBGA169, Section : Device marking for UFBGA176+25 and Section : Device marking for TFBGA176. Updated Z pin count in Table 122: Ordering information scheme. DocID024030 Rev 10 STM32F427xx STM32F429xx Revision history Table 124. Document revision history Date Revision Changes 6 Updated notes related to the minimum and maximum values guaranteed by design, characterization or test in production. Updated IDD_STOP_UDM in Table 27: Typical and maximum current consumptions in Stop mode. Removed note related to tests in production in Table 24: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled except prefetch) or RAM and Table 26: Typical and maximum current consumption in Sleep mode. Updated Table 41: HSI oscillator characteristics. Figure 31 renamed ACCHSI accuracy versus temperature and updated. Updated Figure 38: SPI timing diagram - slave mode and CPHA = 0. Updated Section : Ethernet characteristics. Updated Table 43: Main PLL characteristics, Table 44: PLLI2S (audio PLL) characteristics and Table 45: PLLISAI (audio and LCD-TFT PLL) characteristics. Removed note 1 in Table 75: ADC static accuracy at fADC = 18 MHz, Table 76: ADC static accuracy at fADC = 30 MHz and Table 77: ADC static accuracy at fADC = 36 MHz. Updated td(SDCLKL _Data) and th(SDCLKL _Data) in Table 104: SDRAM write timings. Added Figure 96: UFBGA169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array recommended footprint and Table 117: UFBGA169 recommended PCB design rules (0.5 mm pitch BGA). Added Figure 99: UFBGA176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package recommended footprint and Table 119: UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA). 30-Nov-2015 7 Updated |VSSX -VSS| in Table 14: Voltage characteristics to add VREF-. Updated td(TXEN) and td(TXD) minimum value in Table 72: Dynamics characteristics: Ethernet MAC signals for RMII and Table 73: Dynamics characteristics: Ethernet MAC signals for MII. Added VREF- in Table 74: ADC characteristics. Added A1 minimum and maximum values in Table 111: WLCSP143 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package mechanical data. Updated Figure 86: LQFP144-144-pin, 20 x 20 mm low-profile quad flat package outline. Updated Figure 98: UFBGA176+25 - ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch ball grid array package outline and Table 118: UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data. Updated Figure 101: TFBGA216 216 ball 13 x 13 mm 0.8 mm pitch thin fine pitch ball grid array package outline and Table 120: TFBGA216 - 216 ball 13 x 13 mm 0.8 mm pitch thin fine pitch ball grid array package mechanical data. 21-Jan-2016 8 Updated Figure 22: Power supply scheme. Added td(TXD) values corresponding to 1.71 V < VDD < 3.6 V in Table 72: Dynamics characteristics: Ethernet MAC signals for RMII. 17-Sep-2015 DocID024030 Rev 10 237/239 238 Revision history STM32F427xx STM32F429xx Table 124. Document revision history Date Revision Changes Updated Figure 1: Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package. Added mission profile compliance with JEDEC JESD47 in Section 6.2: Absolute maximum ratings. 18-Jul-2016 9 Changed Figure 31 HSI deviation versus temperature to ACCHSI versus temperature. Updated RLOAD in Table 85: DAC characteristics. Added note 2. related to the position of the 0.1 F capacitor below Figure 37: Recommended NRST pin protection. Updated Figure 40: SPI timing diagram - master mode. Added reference to optional marking or inset/upset marks in all package device marking sections. Updated Figure 85: WLCSP143 marking example (package top view), Figure 88: LQFP144 marking example (package top view), Figure 91: LQFP176 marking (package top view), Figure 94: LQFP208 marking example (package top view). Updated Figure 98: UFBGA176+25 - ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch ball grid array package outline and Table 118: UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data. 19-Jan-2018 238/239 10 Updated Arm wordmark and added Arm logo in Section 2: Description. Updated LDC-TFT feature on cover page. Updated Table 24: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled except prefetch) or RAM and Table 26: Typical and maximum current consumption in Sleep mode. RADC minimum value added in Table 74: ADC characteristics. LTDC clock output frequency changed to 83 MHz in Table 107: LTDC characteristics. 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