STM32L15xCC STM32L15xRC STM32L15xUC STM32L15xVC Ultra-low-power 32-bit MCU ARM(R)-based Cortex(R)-M3, 256KB Flash, 32KB SRAM, 8KB EEPROM, LCD, USB, ADC, DAC Datasheet - production data Features * Ultra-low-power platform - 1.65 V to 3.6 V power supply - -40 C to 105 C temperature range - 0.29A Standby mode (3 wakeup pins) - 1.15 A Standby mode + RTC - 0.44 A Stop mode (16 wakeup lines) - 1.4 A Stop mode + RTC - 8.6 A Low-power run mode - 185 A/MHz Run mode - 10 nA ultra-low I/O leakage - 8 s wakeup time * Core: ARM(R) Cortex(R)-M3 32-bit CPU - From 32 kHz up to 32 MHz max - 1.25 DMIPS/MHz (Dhrystone 2.1) - Memory protection unit * Reset and supply management - Low-power, ultrasafe BOR (brownout reset) with 5 selectable thresholds - Ultra-low-power POR/PDR - Programmable voltage detector (PVD) * Clock sources - 1 to 24 MHz crystal oscillator - 32 kHz oscillator for RTC with calibration - High Speed Internal 16 MHz factory-trimmed RC (+/- 1%) - Internal Low-power 37 kHz RC - Internal multispeed low-power 65 kHz to 4.2 MHz PLL for CPU clock and USB (48 MHz) * Pre-programmed bootloader - USB and USART supported * Development support - Serial wire debug supported - JTAG and trace supported * Up to 83 fast I/Os (70 I/Os 5V tolerant), all mappable on 16 external interrupt vectors August 2017 This is information on a product in full production. LQFP100 (14 x 14 mm) LQFP64 (10 x 10 mm) LQFP48 (7 x 7 mm) WLCSP63 UFQFPN48 UFBGA100 (7 x 7 mm) (0.4 mm pitch) (7x7 mm) * Memories - 256 Kbytes of Flash memory with ECC - 32 Kbytes of RAM - 8 Kbytes of true EEPROM with ECC - 128-byte backup register * LCD Driver (except STM32L151xC devices) up to 8x40 segments, contrast adjustment, blinking mode, step-up converter * Rich analog peripherals (down to 1.8 V) - 2x operational amplifiers - 12-bit ADC 1Msps up to 25 channels - 12-bit DAC 2 channels with output buffers - 2x ultra-low-power-comparators (window mode and wake up capability) * DMA controller 12x channels * 9x peripheral communication interfaces - 1x USB 2.0 (internal 48 MHz PLL) - 3x USARTs - Up to 8x SPIs (2x I2S, 3x 16 Mbit/s) - 2x I2Cs (SMBus/PMBus) * 11x timers: 1x 32-bit, 6x 16-bit with up to 4 IC/OC/PWM channels, 2x 16-bit basic timers, 2x watchdog timers (independent and window) * Up to 23 capacitive sensing channels * CRC calculation unit, 96-bit unique ID Table 1. Device summary Reference Part number STM32L151CC STM32L151RC(1) STM32L151UC STM32L151VC(1) STM32L151CCT6, STM32L151CCU6 STM32L151RCT6 STM32L151UCY6 STM32L151VCT6, STM32L151VCH6 STM32L152CC STM32L152RC(1) STM32L152UC STM32L152VC(1) STM32L152CCT6, STM32L152CCU6 STM32L152RCT6 STM32L152UCY6 STM32L152VCT6, STM32L152VCH6 1. For sales types ending with "A" and STM32L15xxC products in WLCSP64 package, please refer to STM32L15xxC/C-A datasheet. DocID022799 Rev 13 1/136 www.st.com Contents STM32L151xC STM32L152xC Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 2/136 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.2 Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.3 Common system strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 ARM(R) Cortex(R)-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 23 3.6 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.8 DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.9 LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.11 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.12 Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.13 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 27 3.14 System configuration controller and routing interface . . . . . . . . . . . . . . . 27 3.15 Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DocID022799 Rev 13 STM32L151xC STM32L152xC 3.16 3.17 Contents Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.16.1 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.16.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.16.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.16.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.16.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.17.1 IC bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.17.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 30 3.17.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.17.4 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.17.5 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.18 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 30 3.19 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.19.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.19.2 Embedded Trace MacrocellTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.7 Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.8 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 57 6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 59 DocID022799 Rev 13 3/136 4 Contents 7 STM32L151xC STM32L152xC 6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.5 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.3.19 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.3.21 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.3.22 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.1 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 7.2 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 7.3 LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 7.4 UFQFPN48 7 x 7 mm, 0.5 mm pitch, package information . . . . . . . . . . .119 7.5 UFBGA100, 7 x 7 mm, 100-ball ultra thin, fine pitch ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.6 WLCSP63, 0.400 mm pitch wafer level chip size package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.7.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4/136 DocID022799 Rev 13 STM32L151xC STM32L152xC List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ultra-low-power STM32L151xC and STM32L152xC device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 15 CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 16 Functionalities depending on the working mode (from Run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VLCD rail decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 STM32L151xC and STM32L152xC pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 57 Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Current consumption in Run mode, code with data processing running from Flash. . . . . . 61 Current consumption in Run mode, code with data processing running from RAM . . . . . . 62 Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 66 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 68 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 81 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 DocID022799 Rev 13 5/136 6 List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. 6/136 STM32L151xC STM32L152xC TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . 91 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Maximum source impedance RAIN max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 110 LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data. . . . . . . . . . 113 LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 117 UFQFPN48 - ultra thin fine pitch quad flat pack no-lead 7 x 7 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 UFBGA100, 7 x 7 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . . . . . . . 122 UFBGA100, 7 x 7 mm, 0.50 mm pitch, recommended PCB design rules . . . . . . . . . . . . 123 WLCSP63, 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . . . . 126 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 STM32L151xC and STM32L152xC ordering information scheme . . . . . . . . . . . . . . . . . . 130 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 DocID022799 Rev 13 STM32L151xC STM32L152xC List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Ultra-low-power STM32L151xC and STM32L152xC block diagram . . . . . . . . . . . . . . . . . 13 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STM32L15xVC UFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 STM32L15xVC LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 STM32L15xRC LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 STM32L15xUC WLCSP63 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 STM32L15xCC UFQFPN48 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 STM32L15xCC LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Maximum dynamic current consumption on VREF+ supply pin during ADC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 110 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example . . . . . . 112 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 113 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 LQFP64 10 x 10 mm, 64-pin low-profile quad flat package top view example . . . . . . . . . 115 LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 116 LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 LQFP48 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 UFQFPN48 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 UFBGA100, 7 x 7 mm, 0.5 mm pitch package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 UFBGA100, 7 x 7 mm, 0.5 mm pitch, package recommended footprint. . . . . . . . . . . . . . 123 DocID022799 Rev 13 7/136 8 List of figures Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. 8/136 STM32L151xC STM32L152xC UFBGA100, 7 x 7 mm, 0.5 mm pitch, package top view example . . . . . . . . . . . . . . . . . . 124 WLCSP63, 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . . . . 125 WLCSP63 device marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Thermal resistance suffix 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Thermal resistance suffix 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 DocID022799 Rev 13 STM32L151xC STM32L152xC 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L151xC and STM32L152xC ultra-low-power ARM(R) Cortex(R)-M3 based microcontroller product line with a Flash memory of 256 Kbytes. The ultra-low-power STM32L151xC and STM32L152xC family includes devices in 6 different package types: from 48 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the ultra-low-power STM32L151xC and STM32L152xC microcontroller family suitable for a wide range of applications: * Medical and handheld equipment * Application control and user interface * PC peripherals, gaming, GPS and sport equipment * Alarm systems, wired and wireless sensors, video intercom * Utility metering This STM32L151xC and STM32L152xC datasheet should be read in conjunction with the STM32L1xxxx reference manual (RM0038). The application note "Getting started with STM32L1xxxx hardware development" (AN3216) gives a hardware implementation overview. Both documents are available from the STMicroelectronics website www.st.com. For information on the ARM(R) Cortex(R)-M3 core please refer to the ARM(R) Cortex(R)-M3 technical reference manual, available from the www.arm.com website. Figure 1 shows the general block diagram of the device family. DocID022799 Rev 13 9/136 51 Description 2 STM32L151xC STM32L152xC Description The ultra-low-power STM32L151xC and STM32L152xC devices incorporate the connectivity power of the universal serial bus (USB) with the high-performance ARM(R) Cortex(R)-M3 32-bit RISC core operating at a frequency of 32 MHz (33.3 DMIPS), a memory protection unit (MPU), high-speed embedded memories (Flash memory up to 256 Kbytes and RAM up to 32 Kbytes) and an extensive range of enhanced I/Os and peripherals connected to two APB buses. The STM32L151xC and STM32L152xC devices offer two operational amplifiers, one 12-bit ADC, two DACs, two ultra-low-power comparators, one general-purpose 32-bit timer, six general-purpose 16-bit timers and two basic timers, which can be used as time bases. Moreover, the STM32L151xC and STM32L152xC devices contain standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2S, three USARTs and an USB. The STM32L151xC and STM32L152xC devices offer up to 23 capacitive sensing channels to simply add a touch sensing functionality to any application. They also include a real-time clock and a set of backup registers that remain powered in Standby mode. Finally, the integrated LCD controller (except STM32L151xC devices) has a built-in LCD voltage generator that allows to drive up to 8 multiplexed LCDs with the contrast independent of the supply voltage. The ultra-low-power STM32L151xC and STM32L152xC devices operate from a 1.8 to 3.6 V power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option. They are available in the -40 to +85 C and -40 to +105 C temperature ranges. A comprehensive set of power-saving modes allows the design of lowpower applications. 10/136 DocID022799 Rev 13 STM32L151xC STM32L152xC 2.1 Description Device overview Table 2. Ultra-low-power STM32L151xC and STM32L152xC device features and peripheral counts Peripheral STM32L15xCC Flash (Kbytes) STM32L15xUC STM32L15xRC 256 Data EEPROM (Kbytes) 8 RAM (Kbytes) 32 Timers Communica tion interfaces STM32L15xVC 32 bit 1 Generalpurpose 6 Basic 2 SPI 8(3)(1) I2S 2 I2C 2 USART 3 USB 1 GPIOs 37 Operation amplifiers 12-bit synchronized ADC Number of channels 1 14 1 4x18 Operating temperatures Packages 1 25 1 1 4x32 or 8x28 4x44 or 8x40 2 16 Max. CPU frequency Operating voltage 1 21 2 2 Comparators Capacitive sensing channels 83 2 12-bit DAC Number of channels LCD (2) COM x SEG 51 23 32 MHz 1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option 1.65 V to 3.6 V without BOR option Ambient operating temperature: -40 C to 85 C / -40 C to 105 C Junction temperature: -40 to + 110 C LQFP48, UFQFPN48 LQFP64, WLCSP63 LQFP100, UFBGA100 1. 5 SPIs are USART configured in synchronous mode emulating SPI master. 2. STM32L152xx devices only. DocID022799 Rev 13 11/136 51 Description 2.2 STM32L151xC STM32L152xC Ultra-low-power device continuum The ultra-low-power family offers a large choice of cores and features. From proprietary 8bit to up to Cortex-M3, including the Cortex-M0+, the STM32Lx series are the best choice to answer the user needs, in terms of ultra-low-power features. The STM32 ultra-low-power series are the best fit, for instance, for gas/water meter, keyboard/mouse or fitness and healthcare, wearable applications. Several built-in features like LCD drivers, dual-bank memory, Low-power run mode, op-amp, AES 128-bit, DAC, USB crystal-less and many others will clearly allow to build very cost-optimized applications by reducing BOM. Note: STMicroelectronics as a reliable and long-term manufacturer ensures as much as possible the pin-to-pin compatibility between any STM8Lxxxxx and STM32Lxxxxx devices and between any of the STM32Lx and STM32Fx series. Thanks to this unprecedented scalability, the old applications can be upgraded to respond to the latest market features and efficiency demand. 2.2.1 Performance All the families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM Cortex-M3 core for STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios. This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs. 2.2.2 Shared peripherals STM8L15xxx, STM32L15xxx and STM32L162xx share identical peripherals which ensure a very easy migration from one family to another: 2.2.3 * Analog peripherals: ADC, DAC and comparators * Digital peripherals: RTC and some communication interfaces Common system strategy. To offer flexibility and optimize performance, the STM8L15xxx, STM32L15xxx and STM32L162xx family uses a common architecture: 2.2.4 * Same power supply range from 1.65 V to 3.6 V * Architecture optimized to reach ultra-low consumption both in low-power modes and Run mode * Fast startup strategy from low-power modes * Flexible system clock * Ultrasafe reset: same reset strategy including power-on reset, power-down reset, brownout reset and programmable voltage detector Features ST ultra-low-power continuum also lies in feature compatibility: 12/136 * More than 15 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm * Memory density ranging from 2 to 512 Kbytes DocID022799 Rev 13 STM32L151xC STM32L152xC Functional overview Figure 1. Ultra-low-power STM32L151xC and STM32L152xC block diagram 75$&(&.75$&('75$&('75$&('75$&(' -7$* 6: )PD[0+] 038 92/75(* ,EXV 'EXV 6\VWHP 19,& REO (( ,QWHUIDFH 0&38 %XV0DWUL[06 1-7567 -7', -&7.6:&/. -7066:'$7 -7'2 $V$) #9'' 32:(5 9''&25( 7UDFH&RQWUROOHU(70 SEXV 6XSSO\PRQLWRULQJ 3'5 #9'' $+%3&/. $3%3&/. +&/. 5&06, ,QW 3%>@ *3,23257$ *3,23257% 3&>@ *3,23257& 3'>@ *3,23257' 3(>@ *3,23257( 3+>@ *3,23257+ $) 026,0,62 6&.166DV$) 5;7;&76576 6PDUW&DUGDV$) $) 9''5()B$'& $+%$3% 86$57 /& 9665()B$'& 7HPSVHQVRU 7,0(5 FKDQQHO 7,0(5 FKDQQHO 7,0(5 7,0(5 &KDQQHOV 7,0(5 &KDQQHOV 7,0(5 &KDQQHOV &KDQQHOV 86$57 5;7;&76576 6PDUW&DUGDV$) 86$57 5;7;&76576 6PDUW&DUGDV$) :LQ:$7&+'2* 7,0(5 7,0(5 63,,6 [ [ELW 026,0,626&.166:6&. 0&.6'DV$) 63,,6 026,0,626&.166:6&. 0&.6'DV$) [ 86%65$0% *HQHUDOSXUSRVH WLPHUV FKDQQHOV 9/&' 9WR9 $+%$3% 63, #9''$ 7$03(5 #9'' /&'%RRVWHU 7,0(56 ELWV (;7,7 :.83 ELW$'& %DFNXS 5HJ %DFNXSLQWHUIDFH $3%)PD[ 0+] 3$>@ #9''$ 26&B,1 26&B287 57&B287 57&9 $:8 $+%)PD[ 0+] *3&RPS 383' ;7$/N+] 5&/6, #9''$ &DSVHQV &203[B,1[ 6WDQGE\ LQWHUIDFH 5&+6, %25 26&B,1 26&B287 :'*. 9/&' 39' ;7$/26& 0+] 3// &ORFN 0JPW )&/. %25%JDS EZ^d 3'5 #9''$ *3'0$FKDQQHOV 9''$ 966$ 9VV 9UHI .%352*5$0 .%'$7$ .%%227 65$0. 6XSSO\ PRQLWRULQJ 9'' 9WR9 ((3520ELWV *3'0$FKDQQHOV $3%)PD[ 0+] 3 Functional overview ,& 6&/6'$ $V$) ,& 6&/6'$60%XV30%XV $V$) 86%)6GHYLFH 86%B'3 86%B'0 &DSVHQVLQJ 3[ /&'[ 6(*[ 23$03 &20[ #9''$ 23$03 ELW'$& Khd& ELW'$& Khd& ,,) /&) 9,13 9,10 9287 9,13 9,10 9287 DocID022799 Rev 13 06Y9 13/136 51 Functional overview 3.1 STM32L151xC STM32L152xC Low-power modes The ultra-low-power STM32L151xC and STM32L152xC devices support dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the internal lowdrop regulator that supplies the logic can be adjusted according to the system's maximum operating frequency and the external voltage supply. There are three power consumption ranges: * Range 1 (VDD range limited to 1.71 V - 3.6 V), with the CPU running at up to 32 MHz * Range 2 (full VDD range), with a maximum CPU frequency of 16 MHz * Range 3 (full VDD range), with a maximum CPU frequency limited to 4 MHz (generated only with the multispeed internal RC oscillator clock source) Seven low-power modes are provided to achieve the best compromise between low-power consumption, short startup time and available wakeup sources: * Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at 16 MHz is about 1 mA with all peripherals off. * Low-power run mode This mode is achieved with the multispeed internal (MSI) RC oscillator set to the MSI range 0 or MSI range 1 clock range (maximum 131 kHz), execution from SRAM or Flash memory, and internal regulator in low-power mode to minimize the regulator's operating current. In low-power run mode, the clock frequency and the number of enabled peripherals are both limited. * Low-power sleep mode This mode is achieved by entering Sleep mode with the internal voltage regulator in Low-power mode to minimize the regulator's operating current. In Low-power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 kHz. When wakeup is triggered by an event or an interrupt, the system reverts to the run mode with the regulator on. * Stop mode with RTC Stop mode achieves the lowest power consumption while retaining the RAM and register contents and real time clock. All clocks in the VCORE domain are stopped, the PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still running. The voltage regulator is in the low-power mode. The device can be woken up from Stop mode by any of the EXTI line, in 8 s. The EXTI line source can be one of the 16 external lines. It can be the PVD output, the Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp event or the RTC wakeup. 14/136 DocID022799 Rev 13 STM32L151xC STM32L152xC * Functional overview Stop mode without RTC Stop mode achieves the lowest power consumption while retaining the RAM and register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and HSE crystal oscillators are disabled. The voltage regulator is in the low-power mode. The device can be woken up from Stop mode by any of the EXTI line, in 8 s. The EXTI line source can be one of the 16 external lines. It can be the PVD output, the Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can also be wakened by the USB wakeup. * Standby mode with RTC Standby mode is used to achieve the lowest power consumption and real time clock. The internal voltage regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched off. The LSE or LSI is still running. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc, RCC_CSR). The device exits Standby mode in 60 s when an external reset (NRST pin), an IWDG reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B), RTC tamper event, RTC timestamp event or RTC Wakeup event occurs. * Standby mode without RTC Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc, RCC_CSR). The device exits Standby mode in 60 s when an external reset (NRST pin) or a rising edge on one of the three WKUP pin occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by entering Stop or Standby mode. Table 3. Functionalities depending on the operating power supply range Functionalities depending on the operating power supply range(1) Operating power supply range DAC and ADC operation USB Dynamic voltage scaling range VDD= VDDA = 1.65 to 1.71 V Not functional Not functional Range 2 or Range 3 Not functional Not functional Range 1, Range 2 or Range 3 Conversion time up to 500 Ksps Not functional Range 1, Range 2 or Range 3 VDD=VDDA= 1.71 to 1.8 V(2) VDD=VDDA= 1.8 to 2.0 V(2) DocID022799 Rev 13 15/136 51 Functional overview STM32L151xC STM32L152xC Table 3. Functionalities depending on the operating power supply range (continued) Functionalities depending on the operating power supply range(1) Operating power supply range DAC and ADC operation USB Dynamic voltage scaling range VDD=VDDA = 2.0 to 2.4 V Conversion time up to 500 Ksps Functional(3) Range 1, Range 2 or Range 3 VDD=VDDA = 2.4 to 3.6 V Conversion time up to 1 Msps Functional(3) Range 1, Range 2 or Range 3 1. The GPIO speed also depends from VDD voltage and the user has to refer to Table 45: I/O AC characteristics for more information about I/O speed. 2. CPU frequency changes from initial to final must respect "FCPU initial < 4*FCPU final" to limit VCORE drop due to current consumption peak when frequency increases. It must also respect 5 s delay between two changes. For example to switch from 4.2 MHz to 32 MHz, the user can switch from 4.2 MHz to 16 MHz, wait 5 s, then switch from 16 MHz to 32 MHz. 3. Should be USB compliant from I/O voltage standpoint, the minimum VDD is 3.0 V. Table 4. CPU frequency range depending on dynamic voltage scaling 16/136 CPU frequency range Dynamic voltage scaling range 16 MHz to 32 MHz (1ws) 32 kHz to 16 MHz (0ws) Range 1 8 MHz to 16 MHz (1ws) 32 kHz to 8 MHz (0ws) Range 2 2.1MHz to 4.2 MHz (1ws) 32 kHz to 2.1 MHz (0ws) Range 3 DocID022799 Rev 13 STM32L151xC STM32L152xC Functional overview Table 5. Functionalities depending on the working mode (from Run/active down to standby) Standby Run/Active Sleep CPU Y -- Y -- -- -- -- -- Flash Y Y Y Y -- -- -- -- RAM Y Y Y Y Y -- -- -- Backup Registers Y Y Y Y Y -- Y -- EEPROM Y Y Y Y Y -- -- -- Brown-out rest (BOR) Y Y Y Y Y Y Y -- DMA Y Y Y Y -- -- -- -- Programmable Voltage Detector (PVD) Y Y Y Y Y Y Y -- Power On Reset (POR) Y Y Y Y Y Y Y -- Power Down Rest (PDR) Y Y Y Y Y -- Y -- High Speed Internal (HSI) Y Y -- -- -- -- -- -- High Speed External (HSE) Y Y -- -- -- -- -- -- Low Speed Internal (LSI) Y Y Y Y Y -- Y -- Low Speed External (LSE) Y Y Y Y Y -- Y -- Multi-Speed Internal (MSI) Y Y Y Y -- -- -- -- Inter-Connect Controller Y Y Y Y -- -- -- -- RTC Y Y Y Y Y Y Y -- RTC Tamper Y Y Y Y Y Y Y Y Auto WakeUp (AWU) Y Y Y Y Y Y Y Y LCD Y Y Y Y Y -- -- -- USB Y Y -- -- -- Y -- -- -- -- Ips Lowpower Sleep Stop Lowpower Run Wakeup capability Wakeup capability USART Y Y Y Y Y (1) SPI Y Y Y Y -- -- -- -- I2C Y Y -- -- -- (1) -- -- DocID022799 Rev 13 17/136 51 Functional overview STM32L151xC STM32L152xC Table 5. Functionalities depending on the working mode (from Run/active down to standby) (continued) Standby Run/Active Sleep ADC Y Y -- -- -- -- -- -- DAC Y Y Y Y Y -- -- -- Tempsensor Y Y Y Y Y -- -- -- OP amp Y Y Y Y Y -- -- -- Comparators Y Y Y Y Y Y -- -- 16-bit and 32-bit Timers Y Y Y Y -- -- -- -- IWDG Y Y Y Y Y Y Y Y WWDG Y Y Y Y -- -- -- -- Touch sensing Y Y -- -- -- -- -- -- Systic Timer Y Y Y Y -- -- -- GPIOs Y Y Y Y Y -- 3 pins 0 s 0.4 s 3 s 46 s Ips Wakeup time to Run mode Consumption VDD=1.8 to 3.6 V (Typ) Down to 185 A/MHz (from Flash) Down to 34.5 A/MHz (from Flash) Down to 8.6 A Lowpower Sleep Stop Lowpower Run Down to 4.4 A Wakeup capability Y Wakeup capability < 8 s 58 s 0.43 A (no RTC) VDD=1.8V 0.29 A (no RTC) VDD=1.8V 1.15 A (with RTC) VDD=1.8V 0.9 A (with RTC) VDD=1.8V 0.44 A (no RTC) VDD=3.0V 0.29 A (no RTC) VDD=3.0V 1.4 A (with RTC) VDD=3.0V 1.15 A (with RTC) VDD=3.0V 1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before entering run mode. 3.2 ARM(R) Cortex(R)-M3 core with MPU The ARM(R) Cortex(R)-M3 processor is the industry leading processor for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM(R) Cortex(R)-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. 18/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Functional overview The memory protection unit (MPU) improves system reliability by defining the memory attributes (such as read/write access permissions) for different memory regions. It provides up to eight different regions and an optional predefined background region. Owing to its embedded ARM core, the STM32L151xC and STM32L152xC devices are compatible with all ARM tools and software. Nested vectored interrupt controller (NVIC) The ultra-low-power STM32L151xC and STM32L152xC devices embed a nested vectored interrupt controller able to handle up to 53 maskable interrupt channels (not including the 16 interrupt lines of ARM(R) Cortex(R)-M3) and 16 priority levels. * Closely coupled NVIC gives low-latency interrupt processing * Interrupt entry vector table address passed directly to the core * Closely coupled NVIC core interface * Allows early processing of interrupts * Processing of late arriving, higher-priority interrupts * Support for tail-chaining * Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 3.3 Reset and supply management 3.3.1 Power supply schemes 3.3.2 * VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. * VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 1.8 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. Power supply supervisor The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset (PDR) that can be coupled with a brownout reset (BOR) circuitry. The device exists in two versions: * The version with BOR activated at power-on operates between 1.8 V and 3.6 V. * The other version without BOR operates between 1.65 V and 3.6 V. After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or not at power-on), the option byte loading process starts, either to confirm or modify default thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes 1.65 V (whatever the version, BOR active or not, at power-on). When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits the POR area. DocID022799 Rev 13 19/136 51 Functional overview STM32L151xC STM32L152xC Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Stop mode, it is possible to automatically switch off the internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external reset circuit. Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the startup time at power-on can be decreased down to 1 ms typically for devices with BOR inactive at power-up. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.3.3 Voltage regulator The regulator has three operation modes: main (MR), low-power (LPR) and power down. 3.3.4 * MR is used in Run mode (nominal regulation) * LPR is used in the Low-power run, Low-power sleep and Stop modes * Power down is used in Standby mode. The regulator output is high impedance, the kernel circuitry is powered down, inducing zero consumption but the contents of the registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE crystal 32K osc, RCC_CSR). Boot modes At startup, boot pins are used to select one of three boot options: * Boot from Flash memory * Boot from System memory * Boot from embedded RAM The boot loader is located in System memory. It is used to reprogram the Flash memory by using USART1, USART2 or USB. See Application note "STM32 microcontroller system memory boot mode" (AN2606) for details. 20/136 DocID022799 Rev 13 STM32L151xC STM32L152xC 3.4 Functional overview Clock management The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features: * Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. * Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. * Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. * System clock source: three different clock sources can be used to drive the master clock SYSCLK: * - 1-24 MHz high-speed external crystal (HSE), that can supply a PLL - 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can supply a PLL - Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7 frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz). When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be trimmed by software down to a 0.5% accuracy. Auxiliary clock source: two ultra-low-power clock sources that can be used to drive the LCD controller and the real-time clock: - 32.768 kHz low-speed external crystal (LSE) - 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock can be measured using the high-speed internal RC oscillator for greater precision. * RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock the RTC and the LCD, whatever the system clock. * USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply the USB interface. * Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. * Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI and a software interrupt is generated if enabled. * Clock-out capability (MCO: microcontroller clock output): it outputs one of the internal clocks for external use by the application. Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See Figure 2 for details on the clock tree. DocID022799 Rev 13 21/136 51 Functional overview STM32L151xC STM32L152xC Figure 2. Clock tree 3TANDBY SUPPLIED VOLTAGE DOMAIN ENABLE 7ATCHDOG ,3) 2# ,3) TEMPO ,3% /3# ,3% TEMPO 7ATCHDOG ,3 24# ENABLE 24# 2ADIO 3LEEP 4IMER 2ADIO 3LEEP 4IMER ENABLE ,3 ,3 ,3 ,3 6$$#/2% -(Z ,#$ ENABLE 6 -3) 2# LEVEL SHIFTERS 6$$#/2% #+?!$# !$# ENABLE CK?LSI CK?LSE #+?,#$ -#/ NOT DEEPSLEEP #+?072 6 NOT DEEPSLEEP (3) 2# NOT SLEEP OR DEEPSLEEP LEVEL SHIFTERS 6$$#/2% 3YSTEM CLOCK 6 (3% /3# CK?MSI CK?HSI CK?HSE LEVEL SHIFTERS 6$$#/2% !(" PRESCALER 6 CK?PLL 0,, CK?PLLIN 8 ,3 6 -(Z CLOCK DETECTOR NOT SLEEP OR DEEPSLEEP #+?&#,+ #+?#05 #+?4)-393 !0" !0" PRESCALER PRESCALER (3% PRESENT OR NOT ,3 #+?53" LEVEL SHIFTERS 6$$#/2% #LOCK SOURCE CONTROL USBEN AND NOT DEEPSLEEP CK?USB 6CO 6CO MUST BE ATZ -( #+?4)-4'/ #+?!0" #+?!0" TIMEREN AND NOT DEEPSLEEP APB PERIPHEN AND NOT DEEPSLEEP IF !0" PRESC X X ELSE APB PERIPHEN AND NOT DEEPSLEEP -36 22/136 DocID022799 Rev 13 STM32L151xC STM32L152xC 3.5 Functional overview Low-power real-time clock and backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are made automatically. The RTC provides two programmable alarms and programmable periodic interrupts with wakeup from Stop and Standby modes. The programmable wakeup time ranges from 120 s to 36 hours. The RTC can be calibrated with an external 512 Hz output, and a digital compensation circuit helps reduce drift due to crystal deviation. The RTC can also be automatically corrected with a 50/60Hz stable powerline. The RTC calendar can be updated on the fly down to sub second precision, which enables network system synchronization. A time stamp can record an external event occurrence, and generates an interrupt. There are thirty-two 32-bit backup registers provided to store 128 bytes of user application data. They are cleared in case of tamper detection. Three pins can be used to detect tamper events. A change on one of these pins can reset backup register and generate an interrupt. To prevent false tamper event, like ESD event, these three tamper inputs can be digitally filtered. 3.6 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated AFIO registers. All GPIOs are high current capable. The alternate function configuration of I/Os can be locked if needed following a specific sequence in order to avoid spurious writing to the I/O registers. The I/O controller is connected to the AHB with a toggling speed of up to 16 MHz. External interrupt/event controller (EXTI) The external interrupt/event controller consists of 24 edge detector lines used to generate interrupt/event requests. Each line can be individually configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 83 GPIOs can be connected to the 16 external interrupt lines. The 8 other lines are connected to RTC, PVD, USB, comparator events or capacitive sensing acquisition. DocID022799 Rev 13 23/136 51 Functional overview 3.7 STM32L151xC STM32L152xC Memories The STM32L151xC and STM32L152xC devices have the following features: * 32 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait states. With the enhanced bus matrix, operating the RAM does not lead to any performance penalty during accesses to the system bus (AHB and APB buses). * The non-volatile memory is divided into three arrays: - 256 Kbytes of embedded Flash program memory - 8 Kbytes of data EEPROM - Options bytes The options bytes are used to write-protect or read-out protect the memory (with 4 Kbytes granularity) and/or readout-protect the whole memory with the following options: - Level 0: no readout protection - Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected - Level 2: chip readout protection, debug features (ARM Cortex-M3 JTAG and serial wire) and boot in RAM selection disabled (JTAG fuse) The whole non-volatile memory embeds the error correction code (ECC) feature. The user area of the Flash memory can be protected against Dbus read access by PCROP feature (see RM0038 for details). 3.8 DMA (direct memory access) The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers, DAC and ADC. 24/136 DocID022799 Rev 13 STM32L151xC STM32L152xC 3.9 Functional overview LCD (liquid crystal display) The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels. * Internal step-up converter to guarantee functionality and contrast control irrespective of VDD. This converter can be deactivated, in which case the VLCD pin is used to provide the voltage to the LCD * Supports static, 1/2, 1/3, 1/4 and 1/8 duty * Supports static, 1/2, 1/3 and 1/4 bias * Phase inversion to reduce power consumption and EMI * Up to 8 pixels can be programmed to blink * Unneeded segments and common pins can be used as general I/O pins * LCD RAM can be updated at any time owing to a double-buffer * The LCD controller can operate in Stop mode * VLCD rail decoupling capability Table 6. VLCD rail decoupling Bias Pin 3.10 1/2 1/3 1/4 VLCDRAIL1 1/2 VLCD 2/3 VLCD 1/2 VLCD PB2 VLCDRAIL2 N/A 1/3 VLCD 1/4 VLCD PB12 PE11 VLCDRAIL3 N/A N/A 3/4 VLCD PB0 PE12 ADC (analog-to-digital converter) A 12-bit analog-to-digital converters is embedded into STM32L151xC and STM32L152xC devices with up to 25 external channels, performing conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs with up to 24 external channels in a group. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions and timers. An injection mode allows high priority conversions to be done by interrupting a scan mode which runs in as a background task. The ADC includes a specific low-power mode. The converter is able to operate at maximum speed even if the CPU is operating at a very low frequency and has an auto-shutdown function. The ADC's runtime and analog front-end current consumption are thus minimized whatever the MCU operating mode. DocID022799 Rev 13 25/136 51 Functional overview 3.10.1 STM32L151xC STM32L152xC Temperature sensor The temperature sensor (TS) generates a voltage VSENSE that varies linearly with temperature. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. See Table 61: Temperature sensor calibration values. 3.10.2 Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. It enables accurate monitoring of the VDD value (when no external voltage, VREF+, is available for ADC). The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in readonly mode. See Table 16: Embedded internal reference voltage calibration values. 3.11 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration. This dual digital Interface supports the following features: * Two DAC converters: one for each output channel * 8-bit or 12-bit monotonic output * Left or right data alignment in 12-bit mode * Synchronized update capability * Noise-wave generation * Triangular-wave generation * Dual DAC channels, independent or simultaneous conversions * DMA capability for each channel (including the underrun interrupt) * External triggers for conversion * Input reference voltage VREF+ Eight DAC trigger inputs are used in the STM32L151xC and STM32L152xC devices. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 26/136 DocID022799 Rev 13 STM32L151xC STM32L152xC 3.12 Functional overview Operational amplifier The STM32L151xC and STM32L152xC devices embed two operational amplifiers with external or internal follower routing capability (or even amplifier and filter capability with external components). When one operational amplifier is selected, one external ADC channel is used to enable output measurement. The operational amplifiers feature: 3.13 * Low input bias current * Low offset voltage * Low-power mode * Rail-to-rail input Ultra-low-power comparators and reference voltage The STM32L151xC and STM32L152xC devices embed two comparators sharing the same current bias and reference voltage. The reference voltage can be internal or external (coming from an I/O). * One comparator with fixed threshold * One comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of the following: - DAC output - External I/O - Internal reference voltage (VREFINT) or a sub-multiple (1/4, 1/2, 3/4) Both comparators can wake up from Stop mode, and be combined into a window comparator. The internal reference voltage is available externally via a low-power / low-current output buffer (driving current capability of 1 A typical). 3.14 System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I/O ports. The highly flexible routing interface allows the application firmware to control the routing of different I/Os to the TIM2, TIM3 and TIM4 timer input captures. It also controls the routing of internal analog signals to ADC1, COMP1 and COMP2 and the internal reference voltage VREFINT. 3.15 Touch sensing The STM32L151xC and STM32L152xC devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 23 capacitive sensing channels distributed over 10 analog I/O groups. Both software and timer capacitive sensing acquisition modes are supported. Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation DocID022799 Rev 13 27/136 51 Functional overview STM32L151xC STM32L152xC introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. The capacitive sensing acquisition only requires few external components to operate. This acquisition is managed directly by the GPIOs, timers and analog I/O groups (see Section 3.14: System configuration controller and routing interface). Reliable touch sensing functionality can be quickly and easily implemented using the free STM32L1xx STMTouch touch sensing firmware library. 3.16 Timers and watchdogs The ultra-low-power STM32L151xC and STM32L152xC devices include seven generalpurpose timers, two basic timers, and two watchdog timers. Table 7 compares the features of the general-purpose and basic timers. Table 7. Timer feature comparison DMA Capture/compare Complementary request channels outputs generation Timer Counter resolution Counter type Prescaler factor TIM2, TIM3, TIM4 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM5 32-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM9 16-bit Up, down, up/down Any integer between 1 and 65536 No 2 No TIM10, TIM11 16-bit Up Any integer between 1 and 65536 No 1 No TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 3.16.1 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11) There are seven synchronizable general-purpose timers embedded in the STM32L151xC and STM32L152xC devices (see Table 7 for differences). TIM2, TIM3, TIM4, TIM5 TIM2, TIM3, TIM4 are based on 16-bit auto-reload up/down counter. TIM5 is based on a 32bit auto-reload up/down counter. They include a 16-bit prescaler. They feature four independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input captures/output compares/PWMs on the largest packages. TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM10, TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. 28/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Functional overview TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. TIM10, TIM11 and TIM9 TIM10 and TIM11 are based on a 16-bit auto-reload upcounter. TIM9 is based on a 16-bit auto-reload up/down counter. They include a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases and be clocked by the LSE clock source (32.768 kHz) to provide time bases independent from the main CPU clock. 3.16.2 Basic timers (TIM6 and TIM7) These timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit time bases. 3.16.3 SysTick timer This timer is dedicated to the OS, but could also be used as a standard downcounter. It is based on a 24-bit downcounter with autoreload capability and a programmable clock source. It features a maskable system interrupt generation when the counter reaches 0. 3.16.4 Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 37 kHz internal RC and, as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. 3.16.5 Window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.17 Communication interfaces 3.17.1 IC bus Up to two IC bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus. DocID022799 Rev 13 29/136 51 Functional overview 3.17.2 STM32L151xC STM32L152xC Universal synchronous/asynchronous receiver transmitter (USART) The three USART interfaces are able to communicate at speeds of up to 4 Mbit/s. They support IrDA SIR ENDEC and have LIN Master/Slave capability. The three USARTs provide hardware management of the CTS and RTS signals and are ISO 7816 compliant. All USART interfaces can be served by the DMA controller. 3.17.3 Serial peripheral interface (SPI) Up to three SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. The SPIs can be served by the DMA controller. 3.17.4 Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can operate in master or slave mode, and can be configured to operate with a 16-/32-bit resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. The I2Ss can be served by the DMA controller. 3.17.5 Universal serial bus (USB) The STM32L151xC and STM32L152xC devices embed a USB device peripheral compatible with the USB full-speed 12 Mbit/s. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and supports suspend/resume. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). 3.18 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 30/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Functional overview 3.19 Development support 3.19.1 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP. The JTAG port can be permanently disabled with a JTAG fuse. 3.19.2 Embedded Trace MacrocellTM The ARM(R) Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L151xC and STM32L152xC device through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools. DocID022799 Rev 13 31/136 51 Pin descriptions 4 STM32L151xC STM32L152xC Pin descriptions Figure 3. STM32L15xVC UFBGA100 ballout $ 3( 3( 3% %227 3' 3' 3% 3% 3$ 3$ 3$ 3$ % 3( 3( 3% 3% 3% 3' 3' 3' 3' 3& 3& 3$ & 3& :.83 3( 3( 3' 3' 3& 3+ 3$ 966B 3$ 3$ 3& 966B 3& 3& 3& 966B 966B 9''B 9''B ' ( 3( 3& 26&B,1 :8.3 3& 9/&' 26&B287 9''B 3% ) 3+ 26&B,1 * 3+ 9''B 26&B287 + 3& 1567 9''B 3' 3' 3' - 966$ 3& 3& 3' 3' 3' . 95() 3& 3$ 3$ 3& / 95() 3$ :.83 3$ 3$ 3& 3% 0 9''$ 3$ 3$ 3$ 3% 3% 966B 3' 3' 3% 3% 3% 3( 3( 3( 3% 3% 3% 3( 3( 3( 3( 3( 3( AIF 1. This figure shows the package top view. 32/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Pin descriptions 6$$? 633? 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 4. STM32L15xVC LQFP100 pinout ,1&0 6$$? 633? 0( 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 0! 633? 6$$? 0! 0! 0! 0! 0# 0# 0" 0" 0" 0% 0% 0% 0% 0% 0% 0% 0% 0% 0" 0" 633? 6$$? 0% 0% 0% 0% 0% 7+50 6,#$ 0# 7+50 0# /3#?). 0# /3#?/54 633? 6$$? 0( /3#?). 0( /3#?/54 .234 0# 0# 0# 0# 633! 62%& 62%& 6$$! 0! 7+50 0! 0! AIC 1. This figure shows the package top view. DocID022799 Rev 13 33/136 51 Pin descriptions STM32L151xC STM32L152xC 6$$? 633? 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0# 0# 0# 0! 0! Figure 5. STM32L15xRC LQFP64 pinout ,1&0 6$$? 633? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0" 0" 0" 0" 0! 633? 6$$? 0! 0! 0! 0! 0# 0# 0" 0" 0" 0" 0" 633? 6$$? 6,#$ 0# 7+50 0# /3#?). 0# /3#?/54 0( /3#?). 0( /3#?/54 .234 0# 0# 0# 0# 633! 6$$! 0! 7+50 0! 0! AIC 1. This figure shows the package top view. 34/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Pin descriptions Figure 6. STM32L15xUC WLCSP63 ballout ! 633? 0! 0# 0$ 0" "//4 633? " 0! 6$$? 0# 0# 0" 0" 6$$? # 0! 0! 0! 0" 0" 0" 6,#$ $ 0# 0! 0! 0" 0# 0# 0# 0# 0# 0! 0! 0# 0# .234 0# 0" 0" 0# 633! 0( 0( 0" 0" 0" 0! 0! 0# 0# ( 6$$? 0" 0" 0! 633 0! 6$$! * 633? 0" 0" 0# 0! 0! 0! % & ' -36 1. This figure shows the package top view. DocID022799 Rev 13 35/136 51 Pin descriptions STM32L151xC STM32L152xC 0! 6$$? 0# 7+50 633? 0# /3#?). 0! 0# /3#?/54 0! 0( /3#?). 0! 0( /3#?/54 0! .234 0! 633! 0! 6$$! 0" 0! 7+50 0" 0! 0" 0! 0" 0" 5&1&0. 6$$? 633? 0! 0" 0" 0" 0" 0" 0" 0" 0" 0! 0" "//4 0" 0! 0" 0! 633? 0! 6,#$ 0! 6$$? Figure 7. STM32L15xCC UFQFPN48 pinout AID 1. This figure shows the package top view. 36/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Pin descriptions 9''B 966B 3% 3% %227 3% 3% 3% 3% 3% 3$ 3$ Figure 8. STM32L15xCC LQFP48 pinout /4)3 9''B 966B 3$ 3$ 3$ 3$ 3$ 3$ 3% 3% 3% 3% 3$ 3$ 3$ 3$ 3$ 3% 3% 3% 3% 3% 966B 9''B 9/&' 3&:.83 3&26&B,1 3&26&B287 3+26&B,1 3+26&B287 1567 966$ 9''$ 3$:.83 3$ 3$ 069 1. This figure shows the package top view. DocID022799 Rev 13 37/136 51 Pin descriptions STM32L151xC STM32L152xC Table 8. Legend/abbreviations used in the pinout table Name Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TC Standard 3.3 V I/O B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull-up resistor Pin type I/O structure Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Notes Alternate Functions selected through GPIOx_AFR registers functions Pin functions Additional Functions directly selected/enabled through peripheral registers functions Table 9. STM32L151xC and STM32L152xC pin definitions Pin functions UFBGA100 LQFP100 LQFP64 WLCSP63 LQFP48 or UFQFPN48 Pin type(1) I / O Structure Pins Main function(2) (after reset) B2 1 - - - PE2 I/O FT PE2 TIM3_ETR/LCD_SEG38 /TRACECLK - A1 2 - - - PE3 I/O FT PE3 TIM3_CH1/LCD_SEG39 /TRACED0 - B1 3 - - - PE4 I/O FT PE4 TIM3_CH2/TRACED1 - C2 4 - - - PE5 I/O FT PE5 TIM9_CH1/TRACED2 - D2 5 - - - PE6WKUP3 I/O FT PE6 TIM9_CH2/ TRACED3 WKUP3/ RTC_TAMP3 E2 6 1 C7 1 VLCD(3) S - VLCD - - 38/136 Pin name Alternate functions Additional functions DocID022799 Rev 13 STM32L151xC STM32L152xC Pin descriptions Table 9. STM32L151xC and STM32L152xC pin definitions (continued) Pin functions LQFP64 WLCSP63 LQFP48 or UFQFPN48 7 2 D5 2 D1 8 3 D7 E1 9 4 F2 10 G2 I / O Structure LQFP100 C1 Pin type(1) UFBGA100 Pins Main function(2) (after reset) I/O FT PC13 - WKUP2/ RTC_TAMP1/ RTC_TS/RTC_OUT 3 PC14I/O OSC32_IN(4) TC PC14 - OSC32_IN D6 4 PC15I/O OSC32_OUT TC PC15 - OSC32_OUT - - - VSS_5 S - VSS_5 - - 11 - - - VDD_5 S - VDD_5 - - F1 12 5 F6 5 PH0OSC_IN(5) I/O TC PH0 - OSC_IN G1 13 6 F7 6 PH1I/O OSC_OUT(5) TC PH1 - OSC_OUT H2 14 7 E7 7 NRST NRST - - H1 15 8 E6 - PC0 I/O FT PC0 LCD_SEG18 ADC_IN10/ COMP1_INP J2 16 9 E5 - PC1 I/O FT PC1 LCD_SEG19 ADC_IN11/ COMP1_INP J3 17 10 G7 - PC2 I/O FT PC2 LCD_SEG20 ADC_IN12/ COMP1_INP K2 18 11 G6 - PC3 I/O TC PC3 LCD_SEG21 ADC_IN13/ COMP1_INP J1 19 12 F5 8 VSSA S - VSSA - - K1 20 - - - VREF- S - VREF- - - L1 21 - - - VREF+ S - VREF+ - - M1 22 9 VDDA S - VDDA - - PA0 TIM2_CH1_ETR/ TIM5_CH1/ USART2_CTS WKUP1/ RTC_TAMP2/ ADC_IN0/ COMP1_INP L2 23 13 H7 14 E4 10 Pin name PC13WKUP2 PA0-WKUP1 I/O RST I/O FT Alternate functions Additional functions DocID022799 Rev 13 39/136 51 Pin descriptions STM32L151xC STM32L152xC Table 9. STM32L151xC and STM32L152xC pin definitions (continued) Pin functions LQFP100 LQFP64 Pin type(1) I / O Structure Main function(2) (after reset) M2 24 15 G5 11 PA1 I/O FT PA1 TIM2_CH2/TIM5_CH2/ USART2_RTS/ LCD_SEG0 ADC_IN1/ COMP1_INP/ OPAMP1_VINP K3 25 16 H6 12 PA2 I/O FT PA2 TIM2_CH3/TIM5_CH3/ TIM9_CH1/USART2_TX /LCD_SEG1 ADC_IN2/ COMP1_INP/ OPAMP1_VINM L3 26 17 J7 13 PA3 I/O TC PA3 TIM2_CH4/TIM5_CH4/ TIM9_CH2/USART2_RX /LCD_SEG2 ADC_IN3/ COMP1_INP/ OPAMP1_VOUT E3 27 18 - - VSS_4 S - VSS_4 - - H3 28 19 - - VDD_4 S - VDD_4 - - M3 29 20 J6 14 PA4 I/O TC PA4 SPI1_NSS/SPI3_NSS/ I2S3_WS/ USART2_CK ADC_IN4/ DAC_OUT1/ COMP1_INP K4 30 21 H4 15 PA5 I/O TC PA5 TIM2_CH1_ETR/ SPI1_SCK ADC_IN5/ DAC_OUT2/ COMP1_INP L4 31 22 G4 16 PA6 I/O FT PA6 TIM3_CH1/TIM10_CH1/ SPI1_MISO/LCD_SEG3 ADC_IN6/ COMP1_INP/ OPAMP2_VINP M4 32 23 J5 17 PA7 I/O FT PA7 TIM3_CH2/TIM11_CH1/ SPI1_MOSI/LCD_SEG4 ADC_IN7/ COMP1_INP/ OPAMP2_VINM K5 33 24 F4 - PC4 I/O FT PC4 LCD_SEG22 ADC_IN14/ COMP1_INP L5 34 25 J4 - PC5 I/O FT PC5 LCD_SEG23 ADC_IN15/ COMP1_INP TIM3_CH3/LCD_SEG5 ADC_IN8/ COMP1_INP/ OPAMP2_VOUT/ VLCDRAIL3/ VREF_OUT M5 40/136 35 WLCSP63 UFBGA100 LQFP48 or UFQFPN48 Pins 26 J3 18 Pin name PB0 I/O TC PB0 Alternate functions Additional functions DocID022799 Rev 13 STM32L151xC STM32L152xC Pin descriptions Table 9. STM32L151xC and STM32L152xC pin definitions (continued) Pin functions LQFP100 LQFP64 Pin type(1) I / O Structure Main function(2) (after reset) M6 36 27 H3 19 PB1 I/O FT PB1 TIM3_CH4/LCD_SEG6 ADC_IN9/ COMP1_INP/ VREF_OUT L6 37 28 G3 20 PB2 I/O FT PB2 /BOOT1 BOOT1 VLCDRAIL1/ ADCIN0b M7 38 - - - PE7 I/O TC PE7 - ADC_IN22/ COMP1_INP L7 39 - - - PE8 I/O TC PE8 - ADC_IN23/ COMP1_INP M8 40 - - - PE9 - TC PE9 TIM2_CH1_ETR/ TIM5_ETR ADC_IN24/ COMP1_INP L8 41 - - - PE10 I/O TC PE10 TIM2_CH2 ADC_IN25/ COMP1_INP M9 42 - - - PE11 I/O FT PE11 TIM2_CH3 VLCDRAIL2 L9 43 - - - PE12 I/O FT PE12 TIM2_CH4/SPI1_NSS VLCDRAIL3 M10 44 - - - PE13 I/O FT PE13 SPI1_SCK - M11 45 - - - PE14 I/O FT PE14 SPI1_MISO - M12 46 - - - PE15 I/O FT PE15 SPI1_MOSI - L10 47 29 J2 21 PB10 I/O FT PB10 TIM2_CH3/I2C2_SCL/ USART3_TX/ LCD_SEG10 - L11 48 30 H2 22 PB11 I/O FT PB11 TIM2_CH4/I2C2_SDA/ USART3_RX/ LCD_SEG11 - - - - VSS S - VSS - - F12 49 31 J1 23 VSS_1 S - VSS_1 - - G12 50 32 H1 24 VDD_1 S - VDD_1 - - - WLCSP63 UFBGA100 LQFP48 or UFQFPN48 Pins H5 Pin name Alternate functions Additional functions DocID022799 Rev 13 41/136 51 Pin descriptions STM32L151xC STM32L152xC Table 9. STM32L151xC and STM32L152xC pin definitions (continued) Pin functions L12 51 33 G2 25 PB12 I/O I / O Structure Pin name Pin type(1) LQFP48 or UFQFPN48 WLCSP63 LQFP64 LQFP100 UFBGA100 Pins FT Main function(2) (after reset) Alternate functions Additional functions PB12 TIM10_CH1 /I2C2_SMBA/ SPI2_NSS/I2S2_WS/ USART3_CK/ LCD_SEG12 ADC_IN18/ COMP1_INP/ VLCDRAIL2 K12 52 34 G1 26 PB13 I/O FT PB13 TIM9_CH1/SPI2_SCK/ I2S2_CK/ USART3_CTS/ LCD_SEG13 K11 53 35 F3 27 PB14 I/O FT PB14 TIM9_CH2/SPI2_MISO/ USART3_RTS/ LCD_SEG14 ADC_IN20/ COMP1_INP K10 54 36 F2 28 PB15 I/O FT PB15 TIM11_CH1/SPI2_MOSI /I2S2_SD/LCD_SEG15 ADC_IN21/ COMP1_INP/ RTC_REFIN K9 55 - - - PD8 I/O FT PD8 USART3_TX/ LCD_SEG28 - K8 56 - - - PD9 I/O FT PD9 USART3_RX/ LCD_SEG29 - J12 57 - - - PD10 I/O FT PD10 USART3_CK/ LCD_SEG30 - J11 58 - - - PD11 I/O FT PD11 USART3_CTS/ LCD_SEG31 - J10 59 - - - PD12 I/O FT PD12 TIM4_CH1/ USART3_RTS/ LCD_SEG32 - H12 60 - - - PD13 I/O FT PD13 TIM4_CH2/LCD_SEG33 - H11 61 - - - PD14 I/O FT PD14 TIM4_CH3/LCD_SEG34 - H10 62 - - - PD15 I/O FT PD15 TIM4_CH4/LCD_SEG35 - E12 63 - PC6 I/O FT PC6 TIM3_CH1/I2S2_MCK/ LCD_SEG24 - 42/136 37 F1 DocID022799 Rev 13 ADC_IN19/ COMP1_INP STM32L151xC STM32L152xC Pin descriptions Table 9. STM32L151xC and STM32L152xC pin definitions (continued) Pin functions LQFP100 LQFP64 Pin type(1) I / O Structure Main function(2) (after reset) E11 64 38 E1 - PC7 I/O FT PC7 TIM3_CH2/I2S3_MCK/ LCD_SEG25 - E10 65 39 D1 - PC8 I/O FT PC8 TIM3_CH3/LCD_SEG26 - D12 66 40 E2 - PC9 I/O FT PC9 TIM3_CH4/LCD_SEG27 - D11 67 41 E3 29 PA8 I/O FT PA8 USART1_CK/MCO/ LCD_COM0 - D10 68 42 C1 30 PA9 I/O FT PA9 USART1_TX/ LCD_COM1 - C12 69 43 D2 31 PA10 I/O FT PA10 USART1_RX/ LCD_COM2 - B12 70 44 B1 32 PA11 I/O FT PA11 USART1_CTS/ SPI1_MISO USB_DM A12 71 45 D3 33 PA12 I/O FT PA12 USART1_RTS/ SPI1_MOSI USB_DP A11 72 46 C2 34 PA13 I/O FT JTMSSWDIO JTMS-SWDIO - C11 73 PH2 I/O FT PH2 - - F11 74 47 A1 35 VSS_2 S - VSS_2 - - G11 75 48 B2 36 VDD_2 S - VDD_2 - - A10 76 49 C3 37 PA14 I/O FT JTCKSWCLK JTCK-SWCLK - JTDI TIM2_CH1_ETR/ SPI1_NSS/ SPI3_NSS/I2S3_WS/ LCD_SEG17/JTDI - PC10 SPI3_SCK/I2S3_CK/ USART3_TX/ LCD_SEG28/ LCD_SEG40/ LCD_COM4 - A9 B11 77 78 - WLCSP63 UFBGA100 LQFP48 or UFQFPN48 Pins - - 50 A2 38 51 B3 - Pin name PA15 PC10 I/O I/O FT FT Alternate functions Additional functions DocID022799 Rev 13 43/136 51 Pin descriptions STM32L151xC STM32L152xC Table 9. STM32L151xC and STM32L152xC pin definitions (continued) Pin functions C10 79 52 A3 PC11 I/O I / O Structure Pin type(1) LQFP48 or UFQFPN48 - Pin name FT Main function(2) (after reset) Alternate functions Additional functions PC11 SPI3_MISO/ USART3_RX/ LCD_SEG29/ LCD_SEG41/ LCD_COM5 - - - PC12 I/O FT PC12 SPI3_MOSI/I2S3_SD/ USART3_CK/ LCD_SEG30/ LCD_SEG42/ LCD_COM6 - - PD0 I/O FT PD0 TIM9_CH1/SPI2_NSS/ I2S2_WS - - - PD1 I/O FT PD1 SPI2_SCK/I2S2_CK - - PD2 I/O FT PD2 TIM3_ETR/LCD_SEG31 /LCD_SEG43/ LCD_COM7 - - - PD3 I/O FT PD3 SPI2_MISO/ USART2_CTS - - - PD4 I/O FT PD4 SPI2_MOSI/I2S2_SD/ USART2_RTS - - PD5 I/O FT PD5 USART2_TX - - - PD6 I/O FT PD6 USART2_RX - - - PD7 I/O FT PD7 TIM9_CH2/USART2_CK - 55 C4 39 PB3 I/O FT JTDO TIM2_CH2/SPI1_SCK/ SPI3_SCK/I2S3_CK/ LCD_SEG7/JTDO COMP2_INM 90 56 D4 40 PB4 I/O FT NJTRST TIM3_CH1/SPI1_MISO/ SPI3_MISO/LCD_SEG8 /NJTRST COMP2_INP 91 57 A5 41 PB5 I/O FT PB5 TIM3_CH2/I2C1_SMBA/ SPI1_MOSI/SPI3_MOSI /I2S3_SD/LCD_SEG9 B10 80 C9 81 - B9 82 - C8 83 B8 84 - B7 85 - A6 86 - B6 87 - A5 88 - A8 89 A7 C5 44/136 WLCSP63 LQFP64 LQFP100 UFBGA100 Pins 53 B4 54 A4 DocID022799 Rev 13 COMP2_INP STM32L151xC STM32L152xC Pin descriptions Table 9. STM32L151xC and STM32L152xC pin definitions (continued) Pin functions LQFP100 LQFP64 Pin type(1) I / O Structure Main function(2) (after reset) B5 92 58 B5 42 PB6 I/O FT PB6 TIM4_CH1/I2C1_SCL/ USART1_TX COMP2_INP B4 93 59 C5 43 PB7 I/O FT PB7 TIM4_CH2/I2C1_SDA/ USART1_RX COMP2_INP/PVD_IN A4 94 60 A6 44 BOOT0 I B BOOT0 - - A3 95 61 B6 45 PB8 I/O FT PB8 TIM4_CH3/TIM10_CH1/ I2C1_SCL/LCD_SEG16 - B3 96 62 C6 46 PB9 I/O FT PB9 TIM4_CH4/TIM11_CH1/ I2C1_SDA/LCD_COM3 - C3 97 - - - PE0 I/O FT PE0 TIM4_ETR/TIM10_CH1/ LCD_SEG36 - A2 98 - - - PE1 I/O FT PE1 TIM11_CH1/ LCD_SEG37 - D3 99 63 A7 47 VSS_3 S - VSS_3 - - C4 100 64 B7 48 VDD_3 S - VDD_3 - - WLCSP63 UFBGA100 LQFP48 or UFQFPN48 Pins Pin name Alternate functions Additional functions 1. I = input, O = output, S = supply. 2. Function availability depends on the chosen device. 3. Applicable to STM32L152xC devices only. In STM32L151xC devices, this pin should be connected to VDD. 4. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is ON (by setting the LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose PH0/PH1 I/Os, respectively, when the LSE oscillator is off (after reset, the LSE oscillator is off). The LSE has priority over the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins section in the STM32L151xx, STM32L152xx and STM32L162xx reference manual (RM0038). 5. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is ON (by setting the HSEON bit in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os, respectively, when the HSE oscillator is off ( after reset, the HSE oscillator is off ). The HSE has priority over the GPIO function. DocID022799 Rev 13 45/136 51 Table 10. Alternate function input/output Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 Port name AFIO5 AFIO6 AFIO7 . . AFIO11 AFIO14 . . AFIO15 Alternate function SYSTEM TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 LCD CPRI SYSTEM BOOT0 BOOT0 - - - - - - - - - EVENT OUT NRST NRST - - - - - - - - - - DocID022799 Rev 13 PA0WKUP1 - TIM2_CH1_ ETR TIM5_CH1 - - - - USART2_CTS - TIMx_IC1 EVENT OUT PA1 - TIM2_CH2 TIM5_CH2 - - - - USART2_RTS SEG0 TIMx_IC2 EVENT OUT PA2 - TIM2_CH3 TIM5_CH3 TIM9_CH1 - - - USART2_TX SEG1 TIMx_IC3 EVENT OUT PA3 - TIM2_CH4 TIM5_CH4 TIM9_CH2 - - - USART2_RX SEG2 TIMx_IC4 EVENT OUT PA4 - USART2_CK - TIMx_IC1 EVENT OUT PA5 - PA6 - PA7 MCO PA9 - - SPI3_NSS I2S3_WS - - - SPI1_NSS - - - SPI1_SCK - - - TIMx_IC2 EVENT OUT - TIM3_CH1 TIM10_ CH1 - SPI1_MISO - - SEG3 TIMx_IC3 EVENT OUT - TIM3_CH2 TIM11_ CH1 - SPI1_MOSI - - SEG4 TIMx_IC4 EVENT OUT - - - - - - USART1_CK COM0 TIMx_IC1 EVENT OUT - - - - - - USART1_TX COM1 TIMx_IC2 EVENT OUT TIM2_CH1_ETR PA10 - - - - - - - USART1_RX COM2 TIMx_IC3 EVENT OUT PA11 - - - - - SPI1_MISO - USART1_CTS - TIMx_IC4 EVENT OUT PA12 - - - - - SPI1_MOSI - USART1_RTS - TIMx_IC1 EVENT OUT PA13 JTMS-SWDIO - - - - - - - - TIMx_IC2 EVENT OUT PA14 JTCK-SWCLK - - - - - - - - TIMx_IC3 EVEN TOUT TIMx_IC4 EVEN TOUT PA15 JTDI TIM2_CH1_ETR - - - SPI1_NSS SPI3_NSS I2S3_WS - SEG17 STM32L151xC STM32L152xC PA8 Pin descriptions 46/136 Alternate functions Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 Port name AFIO5 AFIO6 AFIO7 . . AFIO11 AFIO14 . . AFIO15 Alternate function SYSTEM TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 - - TIM3_CH3 - - - - - PB1 - - TIM3_CH4 - - - - PB2 BOOT1 - - - - - PB3 JTDO - - - SPI1_SCK PB4 NJTRST - TIM3_CH1 - - PB5 - - TIM3_CH2 - I2C1_SMBA PB6 - TIM4_CH1 - PB7 - - TIM4_CH2 - PB8 - - TIM4_CH3 - TIM4_CH4 PB0 TIM2_CH2 DocID022799 Rev 13 CPRI SYSTEM SEG5 - EVEN TOUT - SEG6 - EVENT OUT - - - EVENT OUT - SEG7 - EVENT OUT SPI1_MISO SPI3_MISO - SEG8 - EVENT OUT SPI1_MOSI SPI3_MOSI I2S3_SD - SEG9 - EVENT OUT I2C1_SCL - - USART1_TX - - EVENT OUT I2C1_SDA - - USART1_RX - - EVENT OUT TIM10_CH1 I2C1_SCL - - - SEG16 - EVENT OUT TIM11_CH1 SPI3_SCK I2S3_CK LCD - I2C1_SDA - - - COM3 - EVENT OUT PB10 - TIM2_CH3 - - I2C2_SCL - - USART3_TX SEG10 - EVENT OUT PB11 - TIM2_CH4 - - I2C2_SDA - - USART3_RX SEG11 - EVENT OUT PB12 - - - TIM10_CH1 I2C2_SMBA SPI2_NSS I2S2_WS - USART3_CK SEG12 - EVENT OUT PB13 - - - TIM9_CH1 - SPI2_SCK I2S2_CK - USART3_CTS SEG13 - EVENT OUT PB14 - - - TIM9_CH2 - SPI2_MISO - USART3_RTS SEG14 - EVENT OUT PB15 - - - TIM11_CH1 - SPI2_MOSI I2S2_SD - - SEG15 - EVENT OUT PC0 - - - - - - - - SEG18 TIMx_IC1 EVENT OUT PC1 - - - - - - - - SEG19 TIMx_IC2 EVENT OUT PC2 - - - - - - - - SEG20 TIMx_IC3 EVENT OUT PC3 - - - - - - - - SEG21 TIMx_IC4 EVENT OUT Pin descriptions 47/136 PB9 STM32L151xC STM32L152xC Table 10. Alternate function input/output (continued) Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 Port name AFIO5 AFIO6 AFIO7 . . AFIO11 AFIO14 . . AFIO15 Alternate function DocID022799 Rev 13 SYSTEM TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 PC4 - - - - - - - - PC5 - - - - - - - PC6 - - TIM3_CH1 - - I2S2_MCK - PC7 - - TIM3_CH2 - - - PC8 - - TIM3_CH3 - - PC9 - - TIM3_CH4 - - LCD CPRI SYSTEM SEG22 TIMx_IC1 EVENT OUT - SEG23 TIMx_IC2 EVENT OUT - SEG24 TIMx_IC3 EVENT OUT I2S3_MCK - SEG25 TIMx_IC4 EVENT OUT - - - SEG26 TIMx_IC1 EVENT OUT - - - SEG27 TIMx_IC2 EVENT OUT TIMx_IC3 EVENT OUT - - - - - - SPI3_SCK I2S3_CK USART3_TX PC11 - - - - - - SPI3_MISO USART3_RX COM5/ SEG29 /SEG41 TIMx_IC4 EVENT OUT PC12 - - - - - - SPI3_MOSI I2S3_SD USART3_CK COM6/ SEG30/ SEG42 TIMx_IC1 EVENT OUT PC13WKUP2 - - - - - - - - - TIMx_IC2 EVENT OUT PC14 OSC32_IN - - - - - - - - - TIMx_IC3 EVENT OUT PC15 OSC32_ OUT - - - - - - - - - TIMx_IC4 EVENT OUT PD0 - - - - SPI2_NSS I2S2_WS - - - TIMx_IC1 EVENT OUT PD1 - - - - - SPI2 SCK I2S2_CK - - - TIMx_IC2 EVENT OUT PD2 - - TIM3_ETR - - - - TIMx_IC3 EVENT OUT TIM9_CH1 - COM7/ SEG31/ SEG43 STM32L151xC STM32L152xC PC10 COM4/ SEG28/ SEG40 Pin descriptions 48/136 Table 10. Alternate function input/output (continued) Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 Port name AFIO5 AFIO6 AFIO7 . . AFIO11 AFIO14 . . AFIO15 Alternate function DocID022799 Rev 13 SYSTEM TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 PD3 - - - - - SPI2_MISO - USART2_CTS PD4 - - - - - SPI2_MOSI I2S2_SD - PD5 - - - - - PD6 - - - PD7 - - - TIM9_CH2 USART1/2/3 LCD CPRI SYSTEM - TIMx_IC4 EVENT OUT USART2_RTS - TIMx_IC1 EVENT OUT - USART2_TX - TIMx_IC2 EVENT OUT - - - USART2_RX - TIMx_IC3 EVENT OUT - - - USART2_CK - TIMx_IC4 EVENT OUT PD8 - - - - - - - USART3_TX SEG28 TIMx_IC1 EVENT OUT PD9 - - - - - - - USART3_RX SEG29 TIMx_IC2 EVENT OUT PD10 - - - - - - - USART3_CK SEG30 TIMx_IC3 EVENT OUT PD11 - - - - - - - USART3_CTS SEG31 TIMx_IC4 EVENT OUT USART3_RTS PD12 - - TIM4_CH1 - - - - SEG32 TIMx_IC1 EVENT OUT PD13 - - TIM4_CH2 - - - - - SEG33 TIMx_IC2 EVENT OUT PD14 - - TIM4_CH3 - - - - - SEG34 TIMx_IC3 EVENT OUT PD15 - - TIM4_CH4 - - - - - SEG35 TIMx_IC4 EVENT OUT PE0 - - TIM4_ETR TIM10_CH1 - - - - SEG36 TIMx_IC1 EVENT OUT PE1 - - - TIM11_CH1 - - - - SEG37 TIMx_IC2 EVENT OUT - SEG 38 TIMx_IC3 EVENT OUT - SEG 39 TIMx_IC4 EVENT OUT TRACECK - TIM3_ETR - PE3 TRACED0 - TIM3_CH1 - PE4 TRACED1 - TIM3_CH2 - - - - - TIMx_IC1 EVENT OUT PE5 TRACED2 - - TIM9_CH1 - - - - - TIMx_IC2 EVENT OUT PE6WKUP3 TRACED3 - - TIM9_CH2 - - - - - TIMx_IC3 EVENT OUT - - - - - - - TIMx_IC4 EVENT OUT PE7 - - - - - - Pin descriptions 49/136 PE2 STM32L151xC STM32L152xC Table 10. Alternate function input/output (continued) Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 Port name AFIO5 AFIO6 AFIO7 . . AFIO11 AFIO14 . . AFIO15 Alternate function DocID022799 Rev 13 SYSTEM TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 LCD PE8 - - - - - - - - PE9 - TIM2_CH1_ETR TIM5_ETR - - - - PE10 - TIM2_CH2 - - - - - PE11 - TIM2_CH3 - - - - PE12 - TIM2_CH4 - - - PE13 - - - - PE14 - - - - PE15 - - - PH0OSC _IN - - PH1OSC_ OUT - PH2 - CPRI SYSTEM - TIMx_IC1 EVENT OUT - - TIMx_IC2 EVENT OUT - - TIMx_IC3 EVENT OUT - - - TIMx_IC4 EVENT OUT SPI1_NSS - - - TIMx_IC1 EVENT OUT - SPI1_SCK - - - TIMx_IC2 EVENT OUT - SPI1_MISO - - - TIMx_IC3 EVENT OUT - - SPI1_MOSI - - - TIMx_IC4 EVENT OUT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Pin descriptions 50/136 Table 10. Alternate function input/output (continued) STM32L151xC STM32L152xC STM32L151xC STM32L152xC 5 Memory mapping Memory mapping Figure 9. Memory map X && X X X X # X X&&&& &&&& $-! $-! RESERVED &LASH )NTERF ACE 2## RESERVED X X RESERVED X% X% #2# #O RTEX - )NTERNAL 0ERIPHERALS X X X X # X X X# X X # X 0ORT ( 0ORT % 0ORT $ 0ORT # 0ORT " 0ORT ! RESERVED 53!24 RESERVED X X X! 30) RESERVED X !$# X X X X X # X&& & RESERVED X&& /PTION BYTE X 4)- %84) 393#&' RESERVED RESERVED X # #/-0 2) RESERVED X X X&& 0ERIPHERALS $!# 072 3YSTEM MEMORY X RESERVED X&& X X X # X RESERVED X 4)- 4)- X X X X X X&& RESE RVE D BYTE 53" 53" 2EG ISTERS )# )# X 32!- RESERVED X # .ON VOLATILE X X MEMORY X X X X RESERVED X # X X X X &LASH MEMORY 2ESERVED 53!24 53!24 $ATA %%02/- X !LIASED TO &LASH OR SYSTEM MEMORY DEPENDING ON "//4 PINS X RESERVED 30) 30) RESERVED )7$' 77$' X # X X X # 24# ,#$ RESERVED X 4)- X 4)- 4)- X # X X X 4)- 4)- 4)- -36 DocID022799 Rev 13 51/136 51 Electrical characteristics STM32L151xC STM32L152xC 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.6 V (for the 1.65 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11. Figure 10. Pin loading conditions Figure 11. Pin input voltage 0&8SLQ 0&8SLQ & S) 9,1 DLF 52/136 DocID022799 Rev 13 DLG STM32L151xC STM32L152xC Power supply scheme Figure 12. Power supply scheme 6WDQGE\SRZHUFLUFXLWU\ /6(57&:DNHXS ORJLF57&EDFNXS UHJLVWHUV 287 *3,2V ,1 9'' 9'' /HYHOVKLIWHU 6.1.6 Electrical characteristics ,2 /RJLF .HUQHOORJLF &38 'LJLWDO 0HPRULHV 5HJXODWRU 1iQ) i) 966 9''$ 9''$ 95() Q) ) Q) ) 95() 95() $'& '$& $QDORJ 26&3//&203 966$ 1QXPEHURI 9''966SDLUV 069 DocID022799 Rev 13 53/136 109 Electrical characteristics 6.1.7 STM32L151xC STM32L152xC Optional LCD power supply scheme Figure 13. Optional LCD power supply scheme 96(/ 9'' 1[Q) [) 2SWLRQ 6WHSXS &RQYHUWHU 9''1 9/&' Q) 9/&' 2SWLRQ &(;7 &UDLO /&' &UDLO 3%RU3( 9/&'UDLO 3% 9/&'UDLO 3%RU3( 9/&'UDLO &UDLO 9661 069 1. Option 1: LCD power supply is provided by a dedicated VLCD supply source, VSEL switch is open. 2. Option 2: LCD power supply is provided by the internal step-up converter, VSEL switch is closed, an external capacitance is needed for correct behavior of this converter. 6.1.8 Current consumption measurement Figure 14. Current consumption measurement scheme $ 1[Q) [) 1[9'' 1[966 9/&' 9''$ Q) ) 95() 95() 966$ 069 54/136 DocID022799 Rev 13 STM32L151xC STM32L152xC 6.2 Electrical characteristics Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 11. Voltage characteristics Symbol VDD-VSS VIN(2) |VDDx| Ratings Min Max -0.3 4.0 Input voltage on five-volt tolerant pin VSS -0.3 VDD+4.0 Input voltage on any other pin VSS - 0.3 4.0 - 50 - 50 0.4 External main supply voltage (including VDDA and VDD)(1) Variations between different VDD power pins pins(3) |VSSX - VSS| Variations between all different ground VREF+ -VDDA Allowed voltage difference for VREF+ > VDDA - Electrostatic discharge voltage (human body model) see Section 6.3.11 VESD(HBM) Unit V mV V 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 12 for maximum allowed injected current values. 3. Include VREF- pin. Table 12. Current characteristics Symbol IVDD() IVSS() (2) Ratings Max. Total current into sum of all VDD_x power lines (source)(1) 100 (sink)(1) 100 Total current out of sum of all VSS_x ground lines IVDD(PIN) Maximum current into each VDD_x power pin (source)(1) 70 IVSS(PIN) (sink)(1) -70 IIO IIO(PIN) IINJ(PIN) (3) IINJ(PIN) Maximum current out of each VSS_x ground pin Output current sunk by any I/O and control pin 25 Output current sourced by any I/O and control pin - 25 Total output current sunk by sum of all IOs and control pins(2) Total output current sourced by sum of all IOs and control pins Injected current on five-volt tolerant Injected current on any other pin mA 60 (2) I/O(4), Unit RST and B pins (5) Total injected current (sum of all I/O and control pins)(6) -60 -5/+0 5 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. 3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.17. DocID022799 Rev 13 55/136 109 Electrical characteristics STM32L151xC STM32L152xC 4. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 11 for maximum allowed input voltage values. 5. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer to Table 11: Voltage characteristics for the maximum allowed input voltage values. 6. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 13. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature 6.3 Operating conditions 6.3.1 General operating conditions Value Unit -65 to +150 C 150 C Table 14. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 32 fPCLK1 Internal APB1 clock frequency - 0 32 fPCLK2 Internal APB2 clock frequency - 0 32 BOR detector disabled 1.65 3.6 BOR detector enabled, at power on 1.8 3.6 BOR detector disabled, after power on 1.65 3.6 1.65 3.6 1.8 3.6 FT pins; 2.0 V VDD -0.3 5.5(3) FT pins; VDD < 2.0 V -0.3 5.25(3) 0 5.5 -0.3 VDD+0.3 LQFP48 package - 364 LQFP100 package - 465 LQFP64 package - 435 UFQFPN48 package - 625 UFBGA100 - 339 WLCSP63 package - 408 VDD (1) VDDA VIN Standard operating voltage Analog operating voltage (ADC and DAC not used) Analog operating voltage (ADC or DAC used) I/O input voltage Must be the same voltage as VDD(2) BOOT0 pin Any other pin PD 56/136 Power dissipation at TA = 85 C for suffix 6 or TA = 105 C for suffix 7(4) DocID022799 Rev 13 Unit MHz V V V mW STM32L151xC STM32L152xC Electrical characteristics Table 14. General operating conditions (continued) Symbol TA TJ Parameter Conditions Min Max -40 85 -40 105 6 suffix version -40 105 7 suffix version -40 110 Ambient temperature for 6 suffix version Maximum power dissipation (5) Ambient temperature for 7 suffix version Maximum power dissipation Junction temperature range Unit C C 1. When the ADC is used, refer to Table 56: ADC characteristics. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and up to 140 mV in operation. 3. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled. 4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 73: Thermal characteristics on page 128). 5. In low-power dissipation state, TA can be extended to -40C to 105C temperature range as long as TJ does not exceed TJ max (see Table 73: Thermal characteristics on page 128). 6.3.2 Embedded reset and power control block characteristics The parameters given in the following table are derived from the tests performed under the conditions summarized in Table 14. Table 15. Embedded reset and power control block characteristics Symbol Parameter VDD rise time rate tVDD(1) VDD fall time rate TRSTTEMPO(1) Reset temporization VPOR/PDR Power on/power down reset threshold VBOR0 Brown-out reset threshold 0 VBOR1 Brown-out reset threshold 1 VBOR2 Brown-out reset threshold 2 Conditions Min Typ Max BOR detector enabled 0 - BOR detector disabled 0 - 1000 BOR detector enabled 20 - BOR detector disabled 0 - 1000 VDD rising, BOR enabled - 2 3.3 0.4 0.7 1.6 Falling edge 1 1.5 1.65 Rising edge 1.3 1.5 1.65 Falling edge 1.67 1.7 1.74 Rising edge 1.69 1.76 1.8 Falling edge 1.87 1.93 1.97 Rising edge 1.96 2.03 2.07 Falling edge 2.22 2.30 2.35 Rising edge 2.31 2.41 2.44 VDD rising, BOR DocID022799 Rev 13 disabled(2) Unit s/V ms V 57/136 109 Electrical characteristics STM32L151xC STM32L152xC Table 15. Embedded reset and power control block characteristics (continued) Symbol Parameter Conditions VBOR3 Brown-out reset threshold 3 VBOR4 Brown-out reset threshold 4 VPVD0 Programmable voltage detector threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 VPVD6 PVD threshold 6 Vhyst Hysteresis voltage Min Typ Max Falling edge 2.45 2.55 2.6 Rising edge 2.54 2.66 2.7 Falling edge 2.68 2.8 2.85 Rising edge 2.78 2.9 2.95 Falling edge 1.8 1.85 1.88 Rising edge 1.88 1.94 1.99 Falling edge 1.98 2.04 2.09 Rising edge 2.08 2.14 2.18 Falling edge 2.20 2.24 2.28 Rising edge 2.28 2.34 2.38 Falling edge 2.39 2.44 2.48 Rising edge 2.47 2.54 2.58 Falling edge 2.57 2.64 2.69 Rising edge 2.68 2.74 2.79 Falling edge 2.77 2.83 2.88 Rising edge 2.87 2.94 2.99 Falling edge 2.97 3.05 3.09 Rising edge 3.08 3.15 3.20 BOR0 threshold - 40 - All BOR and PVD thresholds excepting BOR0 - 100 - Unit V mV 1. Guaranteed by characterization results. 2. Valid for device version without BOR at power up. Please see option "D" in Ordering information scheme for more details. 58/136 DocID022799 Rev 13 STM32L151xC STM32L152xC 6.3.3 Electrical characteristics Embedded internal reference voltage The parameters given in Table 17 are based on characterization results, unless otherwise specified. Table 16. Embedded internal reference voltage calibration values Calibration value name Description Raw data acquired at temperature of 30 C 5 C VDDA= 3 V 10 mV VREFINT_CAL Memory address 0x1FF8 00F8 - 0x1FF8 00F9 Table 17. Embedded internal reference voltage Symbol VREFINT out Parameter (1) Conditions Internal reference voltage Min Typ - 40 C < TJ < +110 C 1.202 1.224 Max Unit 1.242 V Internal reference current consumption - - 1.4 2.3 A TVREFINT Internal reference startup time - - 2 3 ms VVREF_MEAS VDDA and VREF+ voltage during VREFINT factory measure - 2.99 3 3.01 V AVREF_MEAS Including uncertainties Accuracy of factory-measured VREF due to ADC and (2) value VDDA/VREF+ values - - 5 mV TCoeff(3) Temperature coefficient -40 C < TJ < +110 C - 25 100 ppm/ C ACoeff(3) Long-term stability 1000 hours, T= 25 C - - 1000 ppm VDDCoeff(3) Voltage coefficient 3.0 V < VDDA < 3.6 V - - 2000 ppm/V TS_vrefint(3) ADC sampling time when reading the internal reference voltage - 4 - - s TADC_BUF(3) (4) Startup time of reference voltage buffer for ADC - - - 10 s IBUF_ADC(3) Consumption of reference voltage buffer for ADC - - 13.5 25 A IVREF_OUT(3) VREF_OUT output current (5) - - - 1 A CVREF_OUT(3) VREF_OUT output load - - - 50 pF Consumption of reference voltage buffer for VREF_OUT and COMP - - 730 1200 nA VREFINT_DIV1(3) 1/4 reference voltage - 24 25 26 VREFINT_DIV2(3) 1/2 reference voltage - 49 50 51 VREFINT_DIV3(3) 3/4 reference voltage - 74 75 76 IREFINT ILPBUF(3) % VREFIN T 1. Guaranteed by test in production. 2. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes. 3. Guaranteed by characterization results. 4. Shortest sampling time can be determined in the application by multiple iterations. DocID022799 Rev 13 59/136 109 Electrical characteristics STM32L151xC STM32L152xC 5. To guarantee less than 1% VREF_OUT deviation. 6.3.4 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 14: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to the Dhrystone 2.1 code, unless otherwise specified. The current consumption values are derived from tests performed under ambient temperature TA = 25 C and VDD supply voltage conditions summarized in Table 14: General operating conditions, unless otherwise specified. The MCU is placed under the following conditions: 60/136 * All I/O pins are configured in analog input mode * All peripherals are disabled except when explicitly mentioned. * The Flash memory access time, 64-bit access and prefetch is adjusted depending on fHCLK frequency and voltage range to provide the best CPU performance. * When the peripherals are enabled fAPB1 = fAPB2 = fAHB. * When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or HSE = 16 MHz (if HSE bypass mode is used). * The HSE user clock applied to OSCI_IN input follows the characteristic specified in Table 27: High-speed external user clock characteristics. * For maximum current consumption VDD = VDDA = 3.6 V is applied to all supply pins. * For typical current consumption VDD = VDDA = 3.0 V is applied to all supply pins if not specified otherwise. DocID022799 Rev 13 STM32L151xC STM32L152xC Electrical characteristics Table 18. Current consumption in Run mode, code with data processing running from Flash Symbol Parameter fHCLK Typ Max(1) 1 MHz 215 400 2 MHz 400 600 4 MHz 725 960 4 MHz 0.915 1.1 8 MHz 1.75 2.1 16 MHz 3.4 3.9 8 MHz 2.1 2.8 16 MHz 4.2 4.9 32 MHz 8.25 9.4 Range 2, VCORE=1.5 V VOS[1:0] = 10 16 MHz 3.5 4 Range 1, VCORE=1.8 V VOS[1:0] = 01 32 MHz 8.2 9.6 65 kHz 40.5 110 524 kHz 125 190 4.2 MHz 775 900 Conditions Range 3, VCORE=1.2 V VOS[1:0] = 11 IDD (Run from Flash) Supply current in Run mode, code executed from Flash fHSE = fHCLK up to 16 MHz included, fHSE = fHCLK/2 above 16 MHz (PLL ON)(2) Range 2, VCORE=1.5 V VOS[1:0] = 10 Range 1, VCORE=1.8 V VOS[1:0] = 01 HSI clock source (16 MHz) MSI clock, 65 kHz Range 3, VCORE=1.2 V VOS[1:0] = 11 MSI clock, 524 kHz MSI clock, 4.2 MHz Unit A mA A 1. Guaranteed by characterization results, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). DocID022799 Rev 13 61/136 109 Electrical characteristics STM32L151xC STM32L152xC Table 19. Current consumption in Run mode, code with data processing running from RAM Symbol Parameter fHSE = fHCLK up to 16 MHz, included fHSE = fHCLK/2 above 16 MHz (PLL ON)(2) IDD (Run from RAM) Typ Max(1) 1 MHz Range 3, VCORE=1.2 V VOS[1:0] 2 MHz = 11 4 MHz 185 240 345 410 4 MHz Range 2, VCORE=1.5 V VOS[1:0] 8 MHz = 10 16 MHz 0.755 1.4 1.5 2.1 3 3.5 8 MHz 1.8 2.8 16 MHz 3.6 4.1 32 MHz 7.15 8.3 Range 2, VCORE=1.5 V VOS[1:0] 16 MHz = 10 2.95 3.5 Range 1, VCORE=1.8 V VOS[1:0] 32 MHz = 01 7.15 8.4 38.5 85 110 160 690 810 Conditions Range 1, VCORE=1.8 V VOS[1:0] = 01 Supply current in Run mode, code executed from RAM, Flash switched off HSI clock source (16 MHz) MSI clock, 65 kHz MSI clock, 524 kHz MSI clock, 4.2 MHz 65 kHz Range 3, VCORE=1.2 V VOS[1:0] 524 kHz = 11 4.2 MHz 1. Guaranteed by characterization results, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). 3. Guaranteed by test in production. 62/136 fHCLK DocID022799 Rev 13 645 Unit A (3) 880 mA A STM32L151xC STM32L152xC Electrical characteristics Table 20. Current consumption in Sleep mode Symbol Parameter Conditions Range 3, VCORE=1.2 V VOS[1:0] = 11 fHSE = fHCLK up to 16 MHz included, Range 2, fHSE = fHCLK/2 VCORE=1.5 V above 16 MHz (PLL VOS[1:0] = 10 ON)(2) Supply current in Sleep mode, Flash OFF HSI clock source (16 MHz) Typ Max(1) 1 MHz 50 130 2 MHz 78.5 195 4 MHz 140 310 4 MHz 165 310 8 MHz 310 440 16 MHz 590 830 Range 1, VCORE=1.8 V VOS[1:0] = 01 8 MHz 350 550 16 MHz 680 990 32 MHz 1600 2100 Range 2, VCORE=1.5 V VOS[1:0] = 10 16 MHz 640 890 Range 1, VCORE=1.8 V VOS[1:0] = 01 32 MHz 1600 2200 65 kHz 19 60 524 kHz 33 99 4.2 MHz 145 210 1 MHz 60.5 130 2 MHz 89.5 190 4 MHz 150 320 4 MHz 180 320 MSI clock, 65 kHz IDD (Sleep) fHCLK Range 3, MSI clock, 524 kHz VCORE=1.2 V VOS[1:0] = 11 MSI clock, 4.2 MHz Range 3, VCORE=1.2 V VOS[1:0] = 11 fHSE = fHCLK up to 16 MHz included, Range 2, fHSE = fHCLK/2 VCORE=1.5 V above 16 MHz (PLL VOS[1:0] = 10 Supply current ON)(2) in Sleep Range 1, mode, Flash VCORE=1.8 V ON VOS[1:0] = 01 8 MHz 320 460 16 MHz 605 840 8 MHz 380 540 16 MHz 695 1000 32 MHz 1600 2100 Range 2, VCORE=1.5 V VOS[1:0] = 10 16 MHz 650 910 Range 1, VCORE=1.8 V VOS[1:0] = 01 32 MHz 1600 2200 65 kHz 30 90 524 kHz 44 96 4.2 MHz 155 220 HSI clock source (16 MHz) Supply current MSI clock, 65 kHz Range 3, in Sleep MSI clock, 524 kHz VCORE=1.2V mode, Flash VOS[1:0] = 11 ON MSI clock, 4.2 MHz Unit A 1. Guaranteed by characterization results, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register) DocID022799 Rev 13 63/136 109 Electrical characteristics STM32L151xC STM32L152xC Table 21. Current consumption in Low-power run mode Symbol Parameter All peripherals OFF, code executed from RAM, Flash switched OFF, VDD from 1.65 V to 3.6 V IDD (LP Run) Typ Max(1) TA = -40 C to 25 C 8.6 12 TA = 85 C 19 25 TA = 105 C 35 47 TA =-40 C to 25 C 14 16 TA = 85 C 24 29 TA = 105 C 40 51 TA = -40 C to 25 C 26 29 TA = 55 C 28 31 TA = 85 C 36 42 TA = 105 C 52 64 TA = -40 C to 25 C 20 24 TA = 85 C 32 37 TA = 105 C 49 61 TA = -40 C to 25 C 26 30 TA = 85 C 38 44 TA = 105 C 55 67 TA = -40 C to 25 C 41 46 TA = 55 C 44 50 TA = 85 C 56 87 TA = 105 C 73 110 - 200 Conditions Supply current in Low-power run mode MSI clock, 65 kHz fHCLK = 32 kHz MSI clock, 65 kHz fHCLK = 65 kHz MSI clock, 131 kHz fHCLK = 131 kHz MSI clock, 65 kHz fHCLK = 32 kHz All peripherals OFF, code executed from Flash, VDD from 1.65 V to 3.6 V Max allowed VDD from IDD max current in 1.65 V to (LP Run) Low-power 3.6 V run mode MSI clock, 65 kHz fHCLK = 65 kHz MSI clock, 131 kHz fHCLK = 131 kHz - 1. Guaranteed by characterization results, unless otherwise specified. 64/136 DocID022799 Rev 13 - Unit A STM32L151xC STM32L152xC Electrical characteristics Table 22. Current consumption in Low-power sleep mode Symbol Parameter MSI clock, 65 kHz fHCLK = 32 kHz Flash OFF MSI clock, 65 kHz fHCLK = 32 kHz Flash ON All peripherals OFF, VDD from 1.65 V to 3.6 V IDD (LP Sleep) Typ Max(1) TA = -40 C to 25 C 4.4 - TA = -40 C to 25 C 14 16 TA = 85 C 19 23 TA = 105 C 27 33 TA = -40 C to 25 C 15 17 TA = 85 C 20 23 TA = 105 C 28 33 TA = -40 C to 25 C 17 19 18 21 22 25 TA = 105 C 30 35 TA = -40 C to 25 C 14 16 TA = 85 C 19 22 TA = 105 C 27 32 TA = -40 C to 25 C 15 17 TA = 85 C 20 23 TA = 105 C 28 33 TA = -40 C to 25 C 17 19 18 21 22 25 30 36 - 200 Conditions MSI clock, 65 kHz fHCLK = 65 kHz, Flash ON MSI clock, 131 kHz T = 55 C A fHCLK = 131 kHz, TA = 85 C Flash ON Supply current in Low-power sleep mode MSI clock, 65 kHz fHCLK = 32 kHz TIM9 and USART1 enabled, Flash ON, VDD from 1.65 V to 3.6 V MSI clock, 65 kHz fHCLK = 65 kHz MSI clock, 131 kHz TA = 55 C fHCLK = 131 kHz TA = 85 C TA = 105 C IDD max (LP Sleep) Max allowed VDD from 1.65 V current in to 3.6 V Low-power sleep mode - - Unit A 1. Guaranteed by characterization results, unless otherwise specified. DocID022799 Rev 13 65/136 109 Electrical characteristics STM32L151xC STM32L152xC Table 23. Typical and maximum current consumptions in Stop mode Symbol Parameter Conditions LCD OFF RTC clocked by LSI or LSE external clock (32.768kHz), regulator in LP mode, HSI and HSE OFF (no independent watchdog) Typ TA = -40C to 25C VDD = 1.8 V 1.15 - TA = -40C to 25C 1.4 - TA = 55C 2 - TA= 85C 3.4 10 TA = 105C 6.35 23 1.55 6 2.15 7 3.55 12 6.3 27 3.9 10 4.65 11 6.25 16 TA = 105C 9.1 44 TA = -40C to 25C 1.5 - TA = 55C 2.15 - TA= 85C 3.7 - TA = 105C 6.75 - 1.6 - 2.3 - 3.8 - 6.85 - 4 - 4.85 - 6.5 - TA = 105C 9.1 - TA = -40C to 25C VDD = 1.8V 1.2 - TA = -40C to 25C VDD = 3.0V 1.5 - TA = -40C to 25C VDD = 3.6V 1.75 - TA = -40C to 25C LCD TA = 55C ON (static T = 85C A duty)(2) TA = 105C TA = -40C to 25C LCD TA = 55C ON (1/8 duty)(3) TA= 85C IDD (Stop with RTC) Supply current in Stop mode with RTC enabled LCD OFF TA = -40C to 25C LCD TA = 55C ON (static T = 85C A duty)(2) TA = 105C RTC clocked by LSE external quartz (32.768kHz), regulator in LP mode, TA = -40C to 25C HSI and HSE OFF LCD TA = 55C (no independent ON (1/8 watchdog(4) duty)(3) TA= 85C LCD OFF 66/136 DocID022799 Rev 13 Max(1) Unit A STM32L151xC STM32L152xC Electrical characteristics Table 23. Typical and maximum current consumptions in Stop mode (continued) Symbol Parameter Conditions Regulator in LP mode, HSI and HSE OFF, independent watchdog and LSI enabled IDD (Stop) Supply current in Stop mode (RTC disabled) Typ TA = -40C to 25C 1.8 2.2 TA = -40C to 25C 0.435 1 0.99 3 2.4 9 5.5 22(5) 2 - 1.45 - 1.45 - Regulator in LP mode, LSI, HSI T = 55C A and HSE OFF (no independent TA= 85C watchdog) TA = 105C IDD (WU from Stop) MSI = 4.2 MHz Supply current during wakeup from Stop MSI = 1.05 MHz mode MSI = 65 kHz(6) Max(1) Unit TA = -40C to 25C A mA 1. Guaranteed by characterization results, unless otherwise specified. 2. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected. 3. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected. 4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 5. Guaranteed by test in production. 6. When MSI = 64 kHz, the RMS current is measured over the first 15 s following the wakeup event. For the remaining part of the wakeup period, the current corresponds the Run mode current. DocID022799 Rev 13 67/136 109 Electrical characteristics STM32L151xC STM32L152xC Table 24. Typical and maximum current consumptions in Standby mode Symbol Parameter Typ Max(1) 0.905 - 1.15 1.9 1.5 2.2 TA= 85 C 1.75 4 TA = 105 C 2.1 8.3(2) TA = -40 C to 25 C VDD = 1.8 V 0.98 - TA = -40 C to 25 C 1.3 - TA = 55 C 1.7 - TA= 85 C 2.05 - TA = 105 C 2.45 - 1 1.7 0.29 0.6 0.345 0.9 0.575 2.75 1.45 7(2) 1 - Conditions TA = -40 C to 25 C VDD = 1.8 V T = -40 C to 25 C RTC clocked by LSI (no A independent watchdog) TA = 55 C IDD (Standby with RTC) Supply current in Standby mode with RTC enabled RTC clocked by LSE external quartz (no independent watchdog)(3) Independent watchdog TA = -40 C to 25 C and LSI enabled IDD (Standby) Supply current in Standby mode (RTC disabled) TA = -40 C to 25 C Independent watchdog TA = 55 C and LSI OFF TA = 85 C TA = 105 C IDD (WU from Standby) Supply current during wakeup time from Standby mode - TA = -40 C to 25 C Unit A mA 1. Guaranteed by characterization results, unless otherwise specified. 2. Guaranteed by test in production. 3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF loading capacitors. On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in the following table. The MCU is placed under the following conditions: 68/136 * all I/O pins are in input mode with a static value at VDD or VSS (no load) * all peripherals are disabled unless otherwise mentioned * the given value is calculated by measuring the current consumption - with all peripherals clocked off - with only one peripheral clocked on DocID022799 Rev 13 STM32L151xC STM32L152xC Electrical characteristics Table 25. Peripheral current consumption(1) Typical consumption, VDD = 3.0 V, TA = 25 C Range 1, VCORE= 1.8 V VOS[1:0] = 01 Range 2, VCORE= 1.5 V VOS[1:0] = 10 Range 3, VCORE= 1.2 V VOS[1:0] = 11 Low-power sleep and run TIM2 11.2 8.9 7.0 8.9 TIM3 11.2 9.0 7.1 9.0 TIM4 12.9 10.4 8.2 10.4 TIM5 14.4 11.5 9.0 11.5 TIM6 4.0 3.1 2.4 3.1 TIM7 3.8 3.0 2.3 3.0 LCD 5.8 4.6 3.6 4.6 WWDG 2.9 2.3 1.8 2.3 SPI2 6.5 5.2 4.1 5.2 SPI3 5.9 4.6 3.6 4.6 USART2 8.8 7.0 5.5 7.0 USART3 8.4 6.8 5.3 6.8 I2C1 7.3 5.8 4.6 5.8 I2C2 7.9 6.3 5.0 6.3 USB 13.3 10.6 8.3 10.6 PWR 2.8 2.2 1.8 2.2 DAC 6.1 4.9 3.9 4.9 COMP 4.8 3.8 3.0 3.8 Peripheral APB1 DocID022799 Rev 13 Unit A/MHz (fHCLK) 69/136 109 Electrical characteristics STM32L151xC STM32L152xC Table 25. Peripheral current consumption(1) (continued) Typical consumption, VDD = 3.0 V, TA = 25 C Range 1, VCORE= 1.8 V VOS[1:0] = 01 Range 2, VCORE= 1.5 V VOS[1:0] = 10 Range 3, VCORE= 1.2 V VOS[1:0] = 11 Low-power sleep and run SYSCFG & RI 2.6 2.0 1.6 2.0 TIM9 7.9 6.4 5.0 6.4 TIM10 5.9 4.7 3.8 4.7 TIM11 5.9 4.6 3.7 4.6 ADC 10.5 8.3 6.6 8.3 SPI1 4.3 3.4 2.8 3.4 USART1 8.8 7.1 5.6 7.1 GPIOA 4.3 3.3 2.6 3.3 GPIOB 4.3 3.5 2.8 3.5 GPIOC 4.0 3.2 2.5 3.2 GPIOD 4.1 3.3 2.5 3.3 GPIOE 4.2 3.4 2.7 3.4 GPIOH 3.7 3.0 2.3 3.0 CRC 0.8 0.6 0.5 0.6 FLASH 11.1 9.4 8 -(3) DMA1 15.6 12.7 10 12.7 DMA2 16.3 13.4 10.5 13.4 187 154 120 144.6 Peripheral APB2 (2) AHB All enabled IDD (RTC) 0.4 IDD (LCD) 3.1 IDD (ADC)(4) 1450 IDD (DAC)(5) 340 IDD (COMP1) 0.16 IDD (COMP2) Slow mode 2 Fast mode 5 IDD (PVD / BOR)(6) 2.6 IDD (IWDG) 0.25 Unit A/MHz (fHCLK) A 1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz (range 3), fHCLK = 64kHz (Low-power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. 2. HSI oscillator is OFF for this measure. 70/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Electrical characteristics 3. In Low-power sleep and run mode, the Flash memory must always be in power-down mode. 4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion (HSI consumption not included). 5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of VDD/2. DAC is in buffered mode, output is left floating. 6. Including supply current of internal reference voltage. 6.3.5 Wakeup time from low-power mode The wakeup times given in the following table are measured with the MSI RC oscillator. The clock source used to wake up the device depends on the current operating mode: * Sleep mode: the clock source is the clock that was set before entering Sleep mode * Stop mode: the clock source is the MSI oscillator in the range configured before entering Stop mode * Standby mode: the clock source is the MSI oscillator running at 2.1 MHz All timings are derived from tests performed under the conditions summarized in Table 14. Table 26. Low-power mode wakeup timings Symbol tWUSLEEP tWUSLEEP_LP Parameter Wakeup from Sleep mode tWUSTDBY Typ Max(1) Unit fHCLK = 32 MHz 0.4 - fHCLK = 262 kHz Flash enabled 46 - fHCLK = 262 kHz Flash switched OFF 46 - fHCLK = fMSI = 4.2 MHz 8.2 - fHCLK = fMSI = 4.2 MHz Voltage range 1 and 2 7.7 8.9 fHCLK = fMSI = 4.2 MHz Voltage range 3 8.2 13.1 fHCLK = fMSI = 2.1 MHz 10.2 13.4 fHCLK = fMSI = 1.05 MHz 16 20 fHCLK = fMSI = 524 kHz 31 37 fHCLK = fMSI = 262 kHz 57 66 fHCLK = fMSI = 131 kHz 112 123 fHCLK = MSI = 65 kHz 221 236 Wakeup from Standby mode ULP bit = 1 and FWU bit = 1 fHCLK = MSI = 2.1 MHz 58 104 Wakeup from Standby mode FWU bit = 0 fHCLK = MSI = 2.1 MHz 2.6 3.25 Wakeup from Low-power sleep mode, fHCLK = 262 kHz Wakeup from Stop mode, regulator in Run mode ULP bit = 1 and FWU bit = 1 tWUSTOP Conditions Wakeup from Stop mode, regulator in low-power mode ULP bit = 1 and FWU bit = 1 s ms 1. Guaranteed by characterization, unless otherwise specified DocID022799 Rev 13 71/136 109 Electrical characteristics 6.3.6 STM32L151xC STM32L152xC External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.The external clock signal has to respect the I/O characteristics in Section 6.3.12. However, the recommended clock input waveform is shown in Figure 15. Table 27. High-speed external user clock characteristics(1) Symbol fHSE_ext Parameter User external clock source frequency Conditions Min Typ Max Unit CSS is on or PLL is used 1 8 32 MHz CSS is off, PLL not used 0 8 32 MHz VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD 12 - - tw(HSEH) tw(HSEL) OSC_IN high or low time tr(HSE) tf(HSE) OSC_IN rise or fall time - - 20 OSC_IN input capacitance - 2.6 - Cin(HSE) - V ns pF 1. Guaranteed by design. Figure 15. High-speed external clock source AC timing diagram WZ +6(+ 9+6(+ 9+6(/ WU +6( WI +6( WZ +6(/ W 7+6( 069 72/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Electrical characteristics Low-speed external user clock generated from an external source The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under the conditions summarized in Table 14. Table 28. Low-speed external user clock characteristics(1) Symbol Parameter Conditions fLSE_ext User external clock source frequency VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage tw(LSEH) tw(LSEL) OSC32_IN high or low time tr(LSE) tf(LSE) OSC32_IN rise or fall time CIN(LSE) Min Typ Max Unit 1 32.768 1000 kHz 0.7VDD - VDD V - VSS - 0.3VDD 465 - ns OSC32_IN input capacitance - - - 10 - 0.6 - pF 1. Guaranteed by design. Figure 16. Low-speed external clock source AC timing diagram WZ /6(+ 9/6(+ 9/6(/ WU /6( WI /6( W WZ /6(/ 7/6( 069 High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 29. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). DocID022799 Rev 13 73/136 109 Electrical characteristics STM32L151xC STM32L152xC Table 29. HSE oscillator characteristics(1)(2) Symbol fOSC_IN Parameter Conditions Min Typ Max Unit 24 MHz Oscillator frequency - 1 RF Feedback resistor - - 200 - k C Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) RS = 30 - 20 - pF VDD= 3.3 V, VIN = VSS with 30 pF load - - 3 mA C = 20 pF fOSC = 16 MHz - - 2.5 (startup) 0.7 (stabilized) C = 10 pF fOSC = 16 MHz - - 2.5 (startup) 0.46 (stabilized) Startup 3.5 - - mA /V VDD is stabilized - 1 - ms IHSE IDD(HSE) gm tSU(HSE)(4) HSE driving current HSE oscillator power consumption Oscillator transconductance Startup time mA 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Guaranteed by characterization results. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 17). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. 74/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Electrical characteristics Figure 17. HSE oscillator circuit diagram I+6(WRFRUH 5P 5) &2 /P &/ 26&B,1 &P JP 5HVRQDWRU &RQVXPSWLRQ FRQWURO 5HVRQDWRU 670 26&B287 &/ DLE 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 30. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 30. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) Symbol Parameter Conditions Min Typ Max Unit fLSE Low speed external oscillator frequency - - 32.768 - kHz RF Feedback resistor - - 1.2 - M C(2) Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) RS = 30 k - 8 - pF ILSE LSE driving current VDD = 3.3 V, VIN = VSS - - 1.1 A VDD = 1.8 V - 450 - VDD = 3.0 V - 600 - VDD = 3.6V - 750 - - 3 - - A/V VDD is stabilized - 1 - s IDD (LSE) gm LSE oscillator current consumption Oscillator transconductance tSU(LSE)(4) Startup time nA 1. Guaranteed by characterization results. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers". 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details. DocID022799 Rev 13 75/136 109 Electrical characteristics 4. STM32L151xC STM32L152xC tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator (see Figure 18). CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if the user chooses a resonator with a load capacitance of CL = 6 pF and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 18. Typical application with a 32.768 kHz crystal 5HVRQDWRUZLWK LQWHJUDWHGFDSDFLWRUV &/ I/6( 26&B,1 N+] UHVRQDWRU 5) 26&B287 %LDV FRQWUROOHG JDLQ 670/[[ &/ DLE 76/136 DocID022799 Rev 13 STM32L151xC STM32L152xC 6.3.7 Electrical characteristics Internal clock source characteristics The parameters given in Table 31 are derived from tests performed under the conditions summarized in Table 14. High-speed internal (HSI) RC oscillator Table 31. HSI oscillator characteristics Symbol fHSI TRIM (1)(2) Parameter Conditions Min Typ Max Unit Frequency VDD = 3.0 V - 16 - MHz HSI user-trimmed resolution Trimming code is not a multiple of 16 - 0.4 0.7 % Trimming code is a multiple of 16 - Accuracy of the ACCHSI(2) factory-calibrated HSI oscillator - 1.5 % VDDA = 3.0 V, TA = 25 C -1(3) - 1(3) % VDDA = 3.0 V, TA = 0 to 55 C -1.5 - 1.5 % VDDA = 3.0 V, TA = -10 to 70 C -2 - 2 % VDDA = 3.0 V, TA = -10 to 85 C -2.5 - 2 % VDDA = 3.0 V, TA = -10 to 105 C -4 - 2 % VDDA = 1.65 V to 3.6 V TA = -40 to 105 C -4 - 3 % tSU(HSI)(2) HSI oscillator startup time - - 3.7 6 s IDD(HSI)(2) HSI oscillator power consumption - - 100 140 A 1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0). 2. Guaranteed by characterization results. 3. Guaranteed by test in production. Low-speed internal (LSI) RC oscillator Table 32. LSI oscillator characteristics Symbol fLSI(1) DLSI(2) tsu(LSI)(3) IDD(LSI) (3) Parameter Min Typ Max Unit LSI frequency 26 38 56 kHz LSI oscillator frequency drift 0C TA 105C -10 - 4 % LSI oscillator startup time - - 200 s LSI oscillator power consumption - 400 510 nA 1. Guaranteed by test in production. 2. This is a deviation for an individual part, once the initial frequency has been measured. 3. Guaranteed by design. DocID022799 Rev 13 77/136 109 Electrical characteristics STM32L151xC STM32L152xC Multi-speed internal (MSI) RC oscillator Table 33. MSI oscillator characteristics Symbol Condition Typ MSI range 0 65.5 - MSI range 1 131 - MSI range 2 262 - MSI range 3 524 - MSI range 4 1.05 - MSI range 5 2.1 - MSI range 6 4.2 - Frequency error after factory calibration - 0.5 - % DTEMP(MSI)(1) MSI oscillator frequency drift 0 C TA 105 C - 3 - % DVOLT(MSI)(1) MSI oscillator frequency drift 1.65 V VDD 3.6 V, TA = 25 C - - 2.5 %/V MSI range 0 0.75 - MSI range 1 1 - MSI range 2 1.5 - MSI range 3 2.5 - MSI range 4 4.5 - MSI range 5 8 - MSI range 6 15 - MSI range 0 30 - MSI range 1 20 - MSI range 2 15 - MSI range 3 10 - MSI range 4 6 - MSI range 5 5 - MSI range 6, Voltage range 1 and 2 3.5 - MSI range 6, Voltage range 3 5 - fMSI ACCMSI IDD(MSI)(2) tSU(MSI) 78/136 Parameter Frequency after factory calibration, done at VDD= 3.3 V and TA = 25 C MSI oscillator power consumption MSI oscillator startup time DocID022799 Rev 13 Max Unit kHz MHz A s STM32L151xC STM32L152xC Electrical characteristics Table 33. MSI oscillator characteristics (continued) Symbol tSTAB(MSI)(2) fOVER(MSI) Parameter MSI oscillator stabilization time MSI oscillator frequency overshoot Condition Typ Max Unit MSI range 0 - 40 MSI range 1 - 20 MSI range 2 - 10 MSI range 3 - 4 MSI range 4 - 2.5 MSI range 5 - 2 MSI range 6, Voltage range 1 and 2 - 2 MSI range 3, Voltage range 3 - 3 Any range to range 5 - 4 Any range to range 6 - s MHz 6 1. This is a deviation for an individual part, once the initial frequency has been measured. 2. Guaranteed by characterization results. DocID022799 Rev 13 79/136 109 Electrical characteristics 6.3.8 STM32L151xC STM32L152xC PLL characteristics The parameters given in Table 34 are derived from tests performed under the conditions summarized in Table 14. Table 34. PLL characteristics Value Symbol Parameter Unit Min Typ Max(1) PLL input clock(2) 2 - 24 MHz PLL input clock duty cycle 45 - 55 % fPLL_OUT PLL output clock 2 - 32 MHz tLOCK PLL lock time PLL input = 16 MHz PLL VCO = 96 MHz - 115 160 s Jitter Cycle-to-cycle jitter - - 600 ps IDDA(PLL) Current consumption on VDDA - 220 450 IDD(PLL) Current consumption on VDD - 120 150 fPLL_IN A 1. Guaranteed by characterization results. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 6.3.9 Memory characteristics The characteristics are given at TA = -40 to 105 C unless otherwise specified. RAM memory Table 35. RAM and hardware registers Symbol VRM Parameter Conditions Data retention mode(1) STOP mode (or RESET) Min Typ Max Unit 1.65 - - V 1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware registers (only in Stop mode). 80/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Electrical characteristics Flash memory and data EEPROM Table 36. Flash memory and data EEPROM characteristics Symbol Conditions Min Typ Max(1) Unit - 1.65 - 3.6 V Erasing - 3.28 3.94 Programming - 3.28 3.94 Average current during the whole programming / erase operation - 600 900 A Maximum current (peak) TA = 25 C, VDD = 3.6 V during the whole programming / erase operation - 1.5 2.5 mA Parameter VDD Operating voltage Read / Write / Erase tprog Programming/ erasing time for byte / word / double word / half-page IDD ms 1. Guaranteed by design. Table 37. Flash memory and data EEPROM endurance and retention Value Symbol NCYC(2) Parameter Cycling (erase / write) Program memory Cycling (erase / write) EEPROM data memory Data retention (program memory) after 10 kcycles at TA = 85 C tRET (2) Data retention (EEPROM data memory) after 300 kcycles at TA = 85 C Data retention (program memory) after 10 kcycles at TA = 105 C Data retention (EEPROM data memory) after 300 kcycles at TA = 105 C Conditions TA = -40C to 105 C Min(1) Typ Max 10 - - 300 - - 30 - - 30 - - 10 - - 10 - - Unit kcycles TRET = +85 C years TRET = +105 C 1. Guaranteed by characterization results. 2. Characterization is done according to JEDEC JESD22-A117. DocID022799 Rev 13 81/136 109 Electrical characteristics 6.3.10 STM32L151xC STM32L152xC EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: * Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. * FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 38. They are based on the EMS levels and classes defined in application note AN1709. Table 38. EMS characteristics Symbol Parameter Conditions VFESD VDD = 3.3 V, LQFP100, TA = +25 C, Voltage limits to be applied on any I/O pin to fHCLK = 32 MHz induce a functional disturbance conforms to IEC 61000-4-2 VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance Level/ Class VDD = 3.3 V, LQFP100, TA = +25 C, fHCLK = 32 MHz conforms to IEC 61000-4-4 2B 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: * Corrupted program counter * Unexpected reset * Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1 second. 82/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Electrical characteristics To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 39. EMI characteristics Max vs. frequency range Symbol Parameter SEMI 6.3.11 Conditions VDD = 3.3 V, TA = 25 C, Peak level LQFP100 package compliant with IEC 61967-2 Monitored frequency band 4 MHz 16 MHz 32 MHz voltage voltage voltage range 3 range 2 range 1 0.1 to 30 MHz 3 -6 -5 30 to 130 MHz 18 4 -7 130 MHz to 1GHz 15 5 -7 SAE EMI Level 2.5 2 1 Unit dBV - Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114, ANSI/ESD STM5.3.1. standard. Table 40. ESD absolute maximum ratings Symbol Ratings Conditions Electrostatic VESD(HBM) discharge voltage (human body model) TA = +25 C, conforming to JESD22-A114 Electrostatic TA = +25 C, conforming VESD(CDM) discharge voltage to ANSI/ESD STM5.3.1. (charge device model) Class Maximum Unit value(1) 2 2000 V C4 500 V 1. Guaranteed by characterization results. DocID022799 Rev 13 83/136 109 Electrical characteristics STM32L151xC STM32L152xC Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: * A supply overvoltage is applied to each power supply pin * A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 41. Electrical sensitivities Symbol LU 6.3.12 Parameter Conditions Static latch-up class Class TA = +105 C conforming to JESD78A II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of -5 A/+0 A range), or other functional failure (for example reset occurrence oscillator frequency deviation, LCD levels). The test results are given in the Table 42. Table 42. I/O current injection susceptibility Functional susceptibility Symbol Description Injected current on all 5 V tolerant (FT) pins IINJ Injected current on BOOT0 Injected current on any other pin Negative injection Positive injection -5 (1) NA(2) -0 NA(2) -5 (1) +5 1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 2. Injection is not possible. 84/136 DocID022799 Rev 13 Unit mA STM32L151xC STM32L152xC 6.3.13 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 43. I/O static characteristics Symbol VIL VIH Parameter Conditions Input low level voltage Input high level voltage Ilkg I/O Schmitt trigger voltage hysteresis(2) Input leakage current (4) Typ Max 0.3 Unit VDD(1)(2) TC and FT I/O - - BOOT0 - - 0.14 VDD(2) TC I/O 0.45 VDD+0.38(2) - - FT I/O 0.39 VDD+0.59(2) - - 0.15 VDD+0.56(2) - - BOOT0 Vhys Min V TC and FT I/O - 10% VDD(3) - BOOT0 - 0.01 - VSS VIN VDD I/Os with LCD - - 50 VSS VIN VDD I/Os with analog switches - - 50 VSS VIN VDD I/Os with analog switches and LCD - - 50 VSS VIN VDD I/Os with USB - - 250 VSS VIN VDD TC and FT I/Os - - 50 FT I/O VDD VIN 5V - - 10 A nA RPU Weak pull-up equivalent resistor(5)(1) VIN = VSS 25 45 65 k RPD Weak pull-down equivalent resistor(5) VIN = VDD 25 45 65 k CIO I/O pin capacitance - - 5 - pF 1. Guaranteed by test in production. 2. Guaranteed by design. 3. With a minimum of 200 mV. 4. The max. value may be exceeded if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). DocID022799 Rev 13 85/136 109 Electrical characteristics STM32L151xC STM32L152xC Output driving current The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or source up to 20 mA with the non-standard VOL/VOH specifications given in Table 44. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: * The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD() (see Table 12). * The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS() (see Table 12). Output voltage levels Unless otherwise specified, the parameters given in Table 44 are derived from tests performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 44. Output voltage characteristics Symbol VOL(1)(2) Parameter Output low level voltage for an I/O pin VOH (2)(3) Output high level voltage for an I/O pin VOL (3)(4) Output low level voltage for an I/O pin VOH (3)(4) Output high level voltage for an I/O pin VOL(1)(4) VOH (3)(4) Conditions Min Max IIO = 8 mA 2.7 V < VDD < 3.6 V - 0.4 VDD-0.4 - IIO = 4 mA 1.65 V < VDD < 3.6 V V -0.45 DD Output low level voltage for an I/O pin Output high level voltage for an I/O pin IIO = 20 mA 2.7 V < VDD < 3.6 V Unit 0.45 - - 1.3 VDD-1.3 - 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. Guaranteed by test in production. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Guaranteed by characterization results. 86/136 DocID022799 Rev 13 V STM32L151xC STM32L152xC Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 19 and Table 45, respectively. Unless otherwise specified, the parameters given in Table 45 are derived from tests performed under the conditions summarized in Table 14. Table 45. I/O AC characteristics(1) OSPEEDRx [1:0] bit value(1) Symbol Parameter fmax(IO)out Maximum frequency(3) tf(IO)out tr(IO)out Output rise and fall time fmax(IO)out Maximum frequency(3) tf(IO)out tr(IO)out Output rise and fall time 00 01 Fmax(IO)out Maximum frequency(3) 10 tf(IO)out tr(IO)out Output rise and fall time Fmax(IO)out Maximum frequency(3) 11 - tf(IO)out tr(IO)out Output rise and fall time tEXTIpw Pulse width of external signals detected by the EXTI controller Min Max(2) CL = 50 pF, VDD = 2.7 V to 3.6 V - 400 CL = 50 pF, VDD = 1.65 V to 2.7 V - 400 CL = 50 pF, VDD = 2.7 V to 3.6 V - 625 CL = 50 pF, VDD = 1.65 V to 2.7 V - 625 CL = 50 pF, VDD = 2.7 V to 3.6 V - 2 CL = 50 pF, VDD = 1.65 V to 2.7 V - 1 CL = 50 pF, VDD = 2.7 V to 3.6 V - 125 CL = 50 pF, VDD = 1.65 V to 2.7 V - 250 CL = 50 pF, VDD = 2.7 V to 3.6 V - 10 CL = 50 pF, VDD = 1.65 V to 2.7 V - 2 CL = 50 pF, VDD = 2.7 V to 3.6 V - 25 CL = 50 pF, VDD = 1.65 V to 2.7 V - 125 CL = 30 pF, VDD = 2.7 V to 3.6 V - 50 CL = 50 pF, VDD = 1.65 V to 2.7 V - 8 CL = 30 pF, VDD = 2.7 V to 3.6 V - 5 CL = 50 pF, VDD = 1.65 V to 2.7 V - 30 Conditions - Unit kHz ns MHz ns MHz ns MHz ns 8 - 1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L151xx, STM32L152xx and STM32L162xx reference manual for a description of GPIO Port configuration register. 2. Guaranteed by design. 3. The maximum frequency is defined in Figure 19. DocID022799 Rev 13 87/136 109 Electrical characteristics STM32L151xC STM32L152xC Figure 19. I/O AC characteristics definition %84%2.!, /54054 /. P& TR)/ OUT TF)/ OUT 4 -AXIMUM FREQUENCY IS ACHIEVED IF T R TF 4 AND IF THE DUTY CYCLE IS WHEN LOADED BY P& AIC 6.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 46) Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under the conditions summarized in Table 14. Table 46. NRST pin characteristics Symbol Parameter Conditions Min Typ Max VIL(NRST)(1) NRST input low level voltage - - - 0.3 VDD VIH(NRST)(1) NRST input high level voltage - 0.39VDD+0.59 - - VOL(NRST)(1) NRST output low level voltage Unit V IOL = 2 mA 2.7 V < VDD < 3.6 V - IOL = 1.5 mA 1.65 V < VDD < 2.7 V - - 0.4 Vhys(NRST)(1) NRST Schmitt trigger voltage hysteresis - - 10%VDD(2) - mV RPU Weak pull-up equivalent resistor(3) VIN = VSS 25 45 65 k VF(NRST)(1) NRST input filtered pulse - - - 50 ns VNF(NRST)(3) NRST input not filtered pulse - 350 - - ns 1. Guaranteed by design. 2. With a minimum of 200 mV. 3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is around 10%. 88/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Electrical characteristics Figure 20. Recommended NRST pin protection ([WHUQDOUHVHWFLUFXLW 1567 9'' 538 ,QWHUQDOUHVHW )LOWHU ) 670/[[ DLE 1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as possible to the chip. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 46. Otherwise the reset will not be taken into account by the device. 6.3.15 TIM timer characteristics The parameters given in the Table 47 are guaranteed by design. Refer to Section 6.3.13: I/O port characteristics for details on the input/output ction characteristics (output compare, input capture, external clock, PWM output). Table 47. TIMx(1) characteristics Symbol tres(TIM) fEXT ResTIM tCOUNTER Parameter Timer resolution time Conditions Min Max Unit - 1 - tTIMxCLK fTIMxCLK = 32 MHz 31.25 - ns 0 fTIMxCLK/2 MHz 0 16 MHz 16 bit 65536 tTIMxCLK 2048 s Timer external clock frequency on CH1 to CH4 f TIMxCLK = 32 MHz Timer resolution - 16-bit counter clock period when internal clock is selected (timer's prescaler disabled) - tMAX_COUNT Maximum possible count 1 fTIMxCLK = 32 MHz 0.0312 - - 65536 x 65536 tTIMxCLK fTIMxCLK = 32 MHz - 134.2 s 1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers. DocID022799 Rev 13 89/136 109 Electrical characteristics 6.3.16 STM32L151xC STM32L152xC Communications interfaces I2C interface characteristics The device I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: SDA and SCL are not "true" open-drain I/O pins. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 48. Refer also to Section 6.3.13: I/O port characteristics for more details on the input/output ction characteristics (SDA and SCL). Table 48. I2C characteristics Symbol Parameter Standard mode I2C(1)(2) Fast mode I2C(1)(2) Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time - 3450(3) - 900(3) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.6 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - s tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - s Cb Capacitive load for each bus line - 400 - 400 pF tSP Pulse width of spikes that are suppressed by the analog filter 0 50(4) 0 50(4) ns s ns s 1. Guaranteed by design. 2. fPCLK1 must be at least 2 MHz to achieve standard mode IC frequencies. It must be at least 4 MHz to achieve fast mode IC frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum IC fast mode clock. 3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL signal. 4. The minimum width of the spikes filtered by the analog filter is above tSP(max). 90/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Electrical characteristics Figure 21. I2C bus AC waveforms and measurement circuit s/ s/ ZW ZW ^dD> Z^ ^ / Z^ ^> ^ dZdZWd ^ dZd ^ dZd ^d ^ ^ ^ ^ ^d ^<> ^ ^d^dK ^ dKW ^> ^< ^<, ^< ^dK 1. RS = series protection resistor. 2. RP = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. 4. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 49. SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 k 400 0x801B 300 0x8024 200 0x8035 100 0x00A0 50 0x0140 20 0x0320 1. RP = External pull-up resistance, fSCL = I2C speed. 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed is 2%. These variations depend on the accuracy of the external components used to design the application. DocID022799 Rev 13 91/136 109 Electrical characteristics STM32L151xC STM32L152xC SPI characteristics Unless otherwise specified, the parameters given in the following table are derived from tests performed under the conditions summarized in Table 14. Refer to Section 6.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 50. SPI characteristics(1) Symbol Min Max(2) Master mode - 16 Slave mode - 16 Slave transmitter - 12(3) - 6 ns % Parameter Conditions fSCK 1/tc(SCK) SPI clock frequency tr(SCK)(2) tf(SCK)(2) SPI clock rise and fall time Capacitive load: C = 30 pF SPI slave input clock duty cycle Slave mode 30 70 tsu(NSS) NSS setup time Slave mode 4tHCLK - th(NSS) NSS hold time Slave mode 2tHCLK - SCK high and low time Master mode tSCK/2-5 tSCK/2+3 Master mode 5 - Slave mode 6 - Master mode 5 - Slave mode 5 - DuCy(SCK) tw(SCKH)(2) tw(SCKL)(2) tsu(MI)(2) tsu(SI)(2) th(MI) th(SI) Data input setup time (2) (2) Data input hold time ta(SO)(4) Data output access time Slave mode 0 3tHCLK tv(SO) (2) Data output valid time Slave mode - 33 (2) Data output valid time Master mode - 6.5 Slave mode 17 - Master mode 0.5 - tv(MO) th(SO) (2) th(MO)(2) Data output hold time Unit MHz ns 1. The characteristics above are given for voltage range 1. 2. Guaranteed by characterization results. 3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty cycle (DuCy(SCK)) ranging between 40 to 60%. 4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data. 92/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Electrical characteristics Figure 22. SPI timing diagram - slave mode and CPHA = 0 Figure 23. SPI timing diagram - slave mode and CPHA = 1(1) 166LQSXW 6&.LQSXW W68 166 &3+$ &32/ &3+$ &32/ WZ 6&.+ WZ 6&./ WK 62 WY 62 WD 62 0,62 287387 06%287 %,7287 WU 6&. WI 6&. WGLV 62 /6%287 WK 6, WVX 6, 026, ,1387 WK 166 WF 6&. 06%,1 %,7,1 /6%,1 DLE 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. DocID022799 Rev 13 93/136 109 Electrical characteristics STM32L151xC STM32L152xC Figure 24. SPI timing diagram - master mode(1) +LJK 166LQSXW 6&.2XWSXW &3+$ &32/ 6&.2XWSXW WF 6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WVX 0, 0,62 ,13 87 WZ 6&.+ WZ 6&./ WU 6&. WI 6&. %,7,1 06%,1 /6%,1 WK 0, 026, 287387 06%287 WY 02 % , 7287 /6%287 WK 02 DLF 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 94/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Electrical characteristics USB characteristics The USB interface is USB-IF certified (full speed). Table 51. USB startup time Symbol tSTARTUP Parameter (1) USB transceiver startup time Max Unit 1 s 1. Guaranteed by design. Table 52. USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit - 3.0 3.6 V 0.2 - Input levels VDD USB operating voltage VDI(2) Differential input sensitivity VCM(2) Differential common mode range Includes VDI range 0.8 2.5 VSE(2) Single ended receiver threshold 1.3 2.0 - 0.3 2.8 3.6 I(USB_DP, USB_DM) - V Output levels VOL(3) VOH (3) RL of 1.5 k to 3.6 V(4) Static output level low Static output level high RL of 15 k to VSS (4) V 1. All the voltages are measured from the local ground potential. 2. Guaranteed by characterization results. 3. Guaranteed by test in production. 4. RL is the load connected on the USB drivers. Figure 25. USB timings: definition of data signal rise and fall time &URVVRYHU SRLQWV 'LIIHUHQWLDO GDWDOLQHV 9&56 966 WI WU DLE Table 53. USB: full speed electrical characteristics Driver characteristics(1) Symbol Parameter Conditions Min Max Unit tr Rise time(2) CL = 50 pF 4 20 ns tf Time(2) CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V trfm VCRS Fall Rise/ fall time matching Output signal crossover voltage DocID022799 Rev 13 95/136 109 Electrical characteristics STM32L151xC STM32L152xC 1. Guaranteed by design. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). I2S characteristics Table 54. I2S characteristics Symbol fMCK Parameter Conditions Min Max 256 x 8K 256xFs (1) I2S Main Clock Output Master data: 32 bits - 64xFs Slave data: 32 bits - 64xFs 30 70 fCK I2S clock frequency DCK I2S clock frequency duty cycle Slave receiver, 48KHz tr(CK) I2S clock rise time tf(CK) I2S clock fall time tv(WS) - WS valid time Master mode 4 24 th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 15 - th(WS) WS hold time Slave mode 0 - tsu(SD_MR) Data input setup time Master receiver 8 - tsu(SD_SR) Data input setup time Slave receiver 9 - th(SD_MR) Master receiver 5 - Slave receiver 4 - th(SD_SR) MHz MHz % 8 Capacitive load CL=30pF Data input hold time Unit 8 tv(SD_ST) Data output valid time Slave transmitter (after enable edge) - 64 th(SD_ST) Data output hold time Slave transmitter (after enable edge) 22 - tv(SD_MT) Data output valid time Master transmitter (after enable edge) - 12 th(SD_MT) Data output hold time Master transmitter (after enable edge) 8 - ns 1. The maximum for 256xFs is 8 MHz Note: 96/136 Refer to the I2S section of the product reference manual for more details about the sampling frequency (Fs), fMCK, fCK and DCK values. These values reflect only the digital peripheral behavior, source clock precision might slightly change them. DCK depends mainly on the ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of (I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition. DocID022799 Rev 13 STM32L151xC STM32L152xC Electrical characteristics Figure 26. I2S slave timing diagram (Philips protocol)(1) 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 27. I2S master timing diagram (Philips protocol)(1) 1. Guaranteed by characterization results. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. DocID022799 Rev 13 97/136 109 Electrical characteristics 6.3.17 STM32L151xC STM32L152xC 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 56 are guaranteed by design. Table 55. ADC clock frequency Symbol fADC Parameter ADC clock frequency Conditions 2.4 V VDDA 3.6 V Voltage range 1 & 2 Min VREF+ = VDDA 16 VREF+ < VDDA VREF+ > 2.4 V 8 VREF+ < VDDA VREF+ 2.4 V 1.8 V VDDA 2.4 V Max 0.480 4 VREF+ = VDDA 8 VREF+ < VDDA 4 Voltage range 3 Unit MHz 4 Table 56. ADC characteristics Symbol VDDA Parameter Power supply Conditions Min Typ Max - 1.8 - 3.6 - VDDA VREF+ Positive reference voltage - 1.8(1) VREF- Negative reference voltage - - VSSA - IVDDA Current on the VDDA input pin - - 1000 1450 Peak - Average - - 0(4) - VREF+ Direct channels - - 1 Multiplexed channels - - 0.76 Direct channels - - 1.07 Multiplexed channels - - 0.8 Direct channels - - 1.23 Multiplexed channels - - 0.89 Direct channels - - 1.45 Multiplexed channels - - 1 IVREF(2) VAIN Current on the VREF input pin Conversion voltage range(3) 12-bit sampling rate 10-bit sampling rate fS 8-bit sampling rate 6-bit sampling rate 98/136 DocID022799 Rev 13 400 700 Unit V A 450 V Msps Msps Msps Msps STM32L151xC STM32L152xC Electrical characteristics Table 56. ADC characteristics (continued) Symbol tS(5) Parameter Sampling time tCONV Total conversion time (including sampling time) CADC Internal sample and hold capacitor fTRIG External trigger frequency Regular sequencer fTRIG External trigger frequency Injected sequencer RAIN(6) Signal source impedance Conditions Min Typ Max Direct channels 2.4 V VDDA 3.6 V 0.25 - - Multiplexed channels 2.4 V VDDA 3.6 V 0.56 - - Direct channels 1.8 V VDDA 2.4 V 0.56 - - Multiplexed channels 1.8 V VDDA 2.4 V 1 - - - 4 - 384 1/fADC fADC = 16 MHz 1 - 24.75 s - Unit s 4 to 384 (sampling phase) +12 (successive approximation) 1/fADC Direct channels - Multiplexed channels - 12-bit conversions - - 6/8/10-bit conversions - - 12-bit conversions - - Tconv+2 1/fADC 6/8/10-bit conversions - - Tconv+1 1/fADC - - 50 k 16 - pF - Tconv+1 1/fADC Tconv 1/fADC tlat Injection trigger conversion latency fADC = 16 MHz 219 - 281 ns - 3.5 - 4.5 1/fADC tlatr Regular trigger conversion latency fADC = 16 MHz 156 - 219 ns - 2.5 - 3.5 1/fADC - - - 3.5 s tSTAB Power-up time 1. The Vref+ input can be grounded if neither the ADC nor the DAC are used (this allows to shut down an external voltage reference). 2. The current consumption through VREF is composed of two parameters: - one constant (max 300 A) - one variable (max 400 A), only during sampling time + 2 first conversion pulses So, peak consumption is 300+400 = 700 A and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 A at 1Msps 3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 4: Pin descriptions for further details. 4. VSSA or VREF- must be tied to ground. 5. Minimum sampling time is reached for an external input impedance limited to a value as defined in Table 58: Maximum source impedance RAIN max. 6. External impedance has another high value limitation when using short sampling time as defined in Table 58: Maximum source impedance RAIN max. DocID022799 Rev 13 99/136 109 Electrical characteristics STM32L151xC STM32L152xC Table 57. ADC accuracy(1)(2) Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion Test conditions 2.4 V VDDA 3.6 V 2.4 V VREF+ 3.6 V fADC = 8 MHz, RAIN = 50 TA = -40 to 105 C 2.4 V VDDA 3.6 V VDDA = VREF+ fADC = 16 MHz, RAIN = 50 TA = -40 to 105 C Finput=10kHz 1.8 V VDDA 2.4 V VDDA = VREF+ fADC = 8 MHz or 4 MHz, RAIN = 50 TA = -40 to 105 C Finput=10kHz Min(3) Typ Max(3) - 2 4 - 1 2 - 1.5 3.5 - 1 2 - 1.7 3 9.2 10 - 57.5 62 - 57.5 62 - - -70 -65 9.2 10 - 57.5 62 - 57.5 62 - - -70 -65 - 4 6.5 - 2 4 - 4 6 - 1 2 ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error - 1.5 3 ET Total unadjusted error - 2 3 EO Offset error - 1 1.5 EG Gain error - 1.5 2 ED Differential linearity error - 1 2 EL Integral linearity error - 1 1.5 2.4 V VDDA 3.6 V 1.8 V VREF+ 2.4 V fADC = 4 MHz, RAIN = 50 TA = -40 to 105 C 1.8 V VDDA 2.4 V 1.8 V VREF+ 2.4 V fADC = 4 MHz, RAIN = 50 TA = -40 to 105 C Unit LSB bits dB bits dB LSB LSB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.12 does not affect the ADC accuracy. 3. Guaranteed by characterization results. 100/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Electrical characteristics Figure 28. ADC accuracy characteristics 9''$ RUGHSHQGLQJRQSDFNDJH 95() >/6%,'($/ (* ([DPSOHRIDQDFWX DOWUDQVIH UFXUYH 7KHLGHDOWUDQVIHUFX UYH (QGSRLQWFRUUHODWLRQOLQH (7 7RWDOXQDGMXVWHG(UURUPD[LPXPGHYLDWLRQ EHWZHHQWKHDFWXDODQGWKHLGHDOWUDQVIHUFXUYHV (2 2IIVHW(UURUGHYLDWLRQEHWZHHQWKHILUVWDFWXDO WUDQVLWLRQDQGWKHODVWDFWXDORQH (* *DLQ(UURUGHYLDWLRQEHWZHHQWKHODVWLGHDO WUDQVLWLRQDQGWKHODVWDFWXDORQH (' 'LIIHUHQWLDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ EHWZHHQDFWXDOVWHSVDQGWKHLGHDORQH (/ ,QWHJUDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ EHWZHHQDQ\DFWXDOWUDQVLWLRQDQGWKHHQGSRLQW FRUUHODWLRQOLQH (7 (2 (/ (' /6%,'($/ 966$ 9''$ DLH Figure 29. Typical connection diagram using the ADC 9''$ 670/[[ 6DPSOHDQGKROG $'&FRQYHUWHU 5$,1 9$,1 $,1[ &SDUDVLWLF ,/Q$ ELW FRQYHUWHU &$'& DLH 1. Refer to Table 58: Maximum source impedance RAIN max for the value of RAIN and Table 56: ADC characteristics for the value of CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. DocID022799 Rev 13 101/136 109 Electrical characteristics STM32L151xC STM32L152xC Figure 30. Maximum dynamic current consumption on VREF+ supply pin during ADC conversion Sampling (n cycles) Conversion (12 cycles) ADC clock Iref+ 700A 300A MS36686V1 Table 58. Maximum source impedance RAIN max(1) RAIN max (k) Ts (s) Multiplexed channels Ts (cycles) Direct channels fADC=16 MHz(2) 2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 0.25 Not allowed Not allowed 0.7 Not allowed 4 0.5625 0.8 Not allowed 2.0 1.0 9 1 2.0 0.8 4.0 3.0 16 1.5 3.0 1.8 6.0 4.5 24 3 6.8 4.0 15.0 10.0 48 6 15.0 10.0 30.0 20.0 96 12 32.0 25.0 50.0 40.0 192 24 50.0 50.0 50.0 50.0 384 1. Guaranteed by design. 2. Number of samples calculated for fADC = 16 MHz. For fADC = 8 and 4 MHz the number of sampling cycles can be reduced with respect to the minimum sampling time Ts (s), General PCB design guidelines Power supply decoupling should be performed as shown in Figure 12. The applicable procedure depends on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip. 102/136 DocID022799 Rev 13 STM32L151xC STM32L152xC 6.3.18 Electrical characteristics DAC electrical specifications Data guaranteed by design, unless otherwise specified. Table 59. DAC characteristics Symbol Parameter Conditions Min Typ Max - 1.8 - 3.6 1.8 - 3.6 VDDA Analog supply voltage VREF+ Reference supply voltage VREF- Lower reference voltage IDDVREF+(1) Current consumption on No load, middle code (0x800) VREF+ supply No load, worst code (0x000) VREF+ = 3.3 V - 130 220 - 220 350 IDDA(1) Current consumption on No load, middle code (0x800) VDDA supply No load, worst code (0xF1C) VDDA = 3.3 V - 210 320 - 320 520 5 - - 25 - - RL Resistive load VREF+ must always be below VDDA - Connected to DAC output VSSA buffer ON Conected to VDDA CL (2) RO VDAC_OUT DNL(1) INL(1) Offset(1) Offset1(1) Unit V VSSA A k Capacitive load DAC output buffer ON - - 50 pF Output impedance DAC output buffer OFF 12 16 20 k DAC output buffer ON 0.2 - VDDA - 0.2 V DAC output buffer OFF 0.5 - VREF+ - 1LSB mV CL 50 pF, RL 5 k DAC output buffer ON - 1.5 3 No RL, CL 50 pF DAC output buffer OFF - 1.5 3 CL 50 pF, RL 5 k DAC output buffer ON - 2 4 No RL, CL 50 pF DAC output buffer OFF - 2 4 CL 50 pF, RL 5 k DAC output buffer ON - 10 25 No RL, CL 50 pF DAC output buffer OFF - 5 8 No RL, CL 50 pF DAC output buffer OFF - 1.5 5 Voltage on DAC_OUT output Differential non linearity(3) Integral non linearity(4) Offset error at code 0x800 (5) Offset error at code 0x001(6) DocID022799 Rev 13 LSB 103/136 109 Electrical characteristics STM32L151xC STM32L152xC Table 59. DAC characteristics (continued) Symbol Parameter Conditions VDDA = 3.3V VREF+ = 3.0V TA = 0 to 50 C DAC output buffer OFF Offset error temperature dOffset/dT(1) coefficient (code 0x800) V = 3.3V Min Typ Max -20 -10 0 Unit V/C DDA VREF+ = 3.0V TA = 0 to 50 C DAC output buffer ON 0 20 50 CL 50 pF, RL 5 k DAC output buffer ON - No RL, CL 50 pF DAC output buffer OFF - +0 / -0.2% +0 / -0.4% VDDA = 3.3V VREF+ = 3.0V TA = 0 to 50 C DAC output buffer OFF -10 -2 0 VDDA = 3.3V VREF+ = 3.0V TA = 0 to 50 C DAC output buffer ON -40 -8 0 CL 50 pF, RL 5 k DAC output buffer ON - 12 30 No RL, CL 50 pF DAC output buffer OFF - 8 12 tSETTLING Settling time (full scale: for a 12-bit code transition between the lowest and the highest CL 50 pF, RL 5 k input codes till DAC_OUT reaches final value 1LSB - 7 12 s Update rate Max frequency for a correct DAC_OUT change (95% of final value) with 1 LSB variation in the input code CL 50 pF, RL 5 k - - 1 Msps tWAKEUP Wakeup time from off state (setting the ENx bit CL 50 pF, RL 5 k in the DAC Control (8) register) - 9 15 s PSRR+ VDDA supply rejection ratio (static DC measurement) - -60 -35 dB Gain(1) dGain/dT(1) TUE(1) Gain error(7) Gain error temperature coefficient Total unadjusted error CL 50 pF, RL 5 k 1. Data based on characterization results. 2. Connected between DAC_OUT and VSSA. 3. Difference between two consecutive codes - 1 LSB. 104/136 DocID022799 Rev 13 +0.1 / -0.2% +0.2 / -0.5% % V/C LSB STM32L151xC STM32L152xC Electrical characteristics 4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095. 5. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2. 6. Difference between the value measured at Code (0x001) and the ideal value. 7. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (VDDA - 0.2) V when buffer is ON. 8. In buffered mode, the output can overshoot above the final value for low input code (starting from min value). Figure 31. 12-bit buffered /non-buffered DAC %XIIHUHG1RQEXIIHUHG'$& %XIIHU 5/ '$&B287[ ELW GLJLWDOWR DQDORJ FRQYHUWHU &/ AI6 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.19 Operational amplifier characteristics Table 60. Operational amplifier characteristics Symbol CMIR VIOFFSET Condition(1) Min(2) Typ Max(2) - 0 - VDD Maximum calibration range - - - 15 After offset calibration - - - 1.5 - - - 40 - - - 80 - - 1 - - 10 Parameter Common mode input range Input offset voltage VIOFFSET Input offset voltage Normal mode drift Low-power mode IIB Input current bias ILOAD Drive current IDD Consumption CMRR Common mode rejection ration mV Dedicated input General purpose input 75 C Normal mode - - - 500 Low-power mode - - - 100 - 100 220 - 30 60 Normal mode Low-power mode Unit No load, quiescent mode Normal mode - - -85 - Low-power mode - - -90 - DocID022799 Rev 13 V/C nA A A dB 105/136 109 Electrical characteristics STM32L151xC STM32L152xC Table 60. Operational amplifier characteristics (continued) Symbol PSRR Condition(1) Parameter Power supply rejection ratio Normal mode Low-power mode Normal mode GBW Bandwidth Low-power mode Normal mode Low-power mode SR Slew rate RL Resistive load CL Capacitive load VOHSAT High saturation voltage VDD<2.4 V Max(2) - -85 - - -90 - 400 1000 3000 150 300 800 200 500 2200 70 150 800 VDD>2.4 V (between 0.1 V and VDD-0.1 V) - 700 - Low-power mode VDD>2.4 V - 100 - - 300 - - 50 - Normal mode 55 100 - Low-power mode 65 110 - 4 - - 20 - - - - 50 VDD100 - - VDD-50 - - - - 100 - - 50 Low-power mode Open loop gain VDD>2.4 V Typ Normal mode Normal mode AO DC Min(2) Normal mode Low-power mode VDD<2.4 V VDD<2.4 V - Normal mode Low-power mode Normal mode ILOAD = max or RL = min Unit dB kHZ V/ms dB k pF mV VOLSAT Low saturation voltage m Phase margin - - 60 - GM Gain margin - - -12 - dB tOFFTRIM Offset trim time: during calibration, minimum time needed between two steps to have 1 mV accuracy - - 1 - ms 10 - tWAKEUP Low-power mode Normal mode CL 50 pf, RL 4 k - Low-power mode CL 50 pf, RL 20 k - Wakeup time s 30 - 1. Operating conditions are limited to junction temperature (0 C to 105 C) when VDD is below 2 V. Otherwise to the full ambient temperature range (-40 C to 85 C, -40 C to 105 C). 2. Guaranteed by characterization results. 106/136 DocID022799 Rev 13 STM32L151xC STM32L152xC 6.3.20 Electrical characteristics Temperature sensor characteristics Table 61. Temperature sensor calibration values Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 C 5 C VDDA= 3 V 10 mV 0x1FF8 00FA - 0x1FF8 00FB TS_CAL2 TS ADC raw data acquired at temperature of 110 C 5 C VDDA= 3 V 10 mV 0x1FF8 00FE - 0x1FF8 00FF Table 62. Temperature sensor characteristics Symbol Parameter TL(1) VSENSE linearity with temperature Avg_Slope(1) Average slope V110 Voltage at 110C I 5C(2) Min Typ Max Unit - 1 2 C 1.48 1.61 1.75 mV/C 612 626.8 641.5 mV A Current consumption - 3.4 6 tSTART(3) Startup time - - 10 TS_temp(3) ADC sampling time when reading the temperature 4 - - (3) DDA(TEMP) s 1. Guaranteed by characterization results. 2. Measured at VDD = 3 V 10 mV. V110 ADC conversion result is stored in the TS_CAL2 byte. 3. Guaranteed by design. 6.3.21 Comparator Table 63. Comparator 1 characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit 3.6 V VDDA Analog supply voltage - 1.65 R400K R400K value - - 400 - R10K R10K value - - 10 - Comparator 1 input voltage range - 0.6 - VDDA Comparator startup time - - 7 10 VIN tSTART (2) k V s td Propagation delay - - 3 10 Voffset Comparator offset - - 3 10 mV VDDA = 3.6 V Comparator offset VIN+ = 0 V variation in worst voltage VIN- = VREFINT stress conditions TA = 25 C 0 1.5 10 mV/1000 h Current consumption(3) - 160 260 nA dVoffset/dt ICOMP1 - DocID022799 Rev 13 107/136 109 Electrical characteristics STM32L151xC STM32L152xC 1. Guaranteed by characterization results. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference. 3. Comparator consumption only. Internal reference voltage not included. Table 64. Comparator 2 characteristics Symbol VDDA VIN Parameter Min Analog supply voltage - 1.65 - 3.6 V Comparator 2 input voltage range - 0 - VDDA V Fast mode - 15 20 Slow mode - 20 25 1.65 V VDDA 2.7 V - 1.8 3.5 2.7 V VDDA 3.6 V - 2.5 6 1.65 V VDDA 2.7 V - 0.8 2 2.7 V VDDA 3.6 V - 1.2 4 - 4 20 mV VDDA = 3.3V TA = 0 to 50 C V- =VREFINT, 3/4 VREFINT, 1/2 VREFINT, 1/4 VREFINT. - 15 100 ppm /C Fast mode - 3.5 5 Slow mode - 0.5 2 tSTART Comparator startup time td slow Propagation delay(2) in slow mode td fast Propagation delay(2) in fast mode Voffset Comparator offset error dThreshold/ Threshold voltage temperature dt coefficient ICOMP2 Typ Max(1) Unit Conditions Current consumption(3) 1. Guaranteed by characterization results. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference. 3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not included. 108/136 DocID022799 Rev 13 s A STM32L151xC STM32L152xC 6.3.22 Electrical characteristics LCD controller The device embeds a built-in step-up converter to provide a constant LCD reference voltage independently from the VDD voltage. An external capacitor Cext must be connected to the VLCD pin to decouple this converter. Table 65. LCD controller characteristics Symbol Parameter Min Typ Max Unit VLCD LCD external voltage - - 3.6 VLCD0 LCD internal reference voltage 0 - 2.6 - VLCD1 LCD internal reference voltage 1 - 2.73 - VLCD2 LCD internal reference voltage 2 - 2.86 - VLCD3 LCD internal reference voltage 3 - 2.98 - VLCD4 LCD internal reference voltage 4 - 3.12 - VLCD5 LCD internal reference voltage 5 - 3.26 - VLCD6 LCD internal reference voltage 6 - 3.4 - VLCD7 LCD internal reference voltage 7 - 3.55 - 0.1 - 2 Supply current at VDD = 2.2 V - 3.3 - Supply current at VDD = 3.0 V - 3.1 - Low drive resistive network overall value 5.28 6.6 7.92 M High drive resistive network total value 192 240 288 k V Cext ILCD(1) RHtot(2) RL (2) VLCD external capacitance V44 Segment/Common highest level voltage - - VLCD V34 Segment/Common 3/4 level voltage - 3/4 VLCD - V23 Segment/Common 2/3 level voltage - 2/3 VLCD - V12 Segment/Common 1/2 level voltage - 1/2 VLCD - V13 Segment/Common 1/3 level voltage - 1/3 VLCD - V14 Segment/Common 1/4 level voltage - 1/4 VLCD - V0 Segment/Common lowest level voltage 0 - - Segment/Common level voltage error TA = -40 to 105 C - - 50 Vxx(3) V F A V mV 1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected. 2. Guaranteed by design. 3. Guaranteed by characterization results. DocID022799 Rev 13 109/136 109 Package information 7 STM32L151xC STM32L152xC Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.1 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package information Figure 32. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.% $ ! + CCC # , $ , $ 0). )$%.4)&)#!4)/. % % % B E ,?-%?6 1. Drawing is not to scale. Table 66. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol 110/136 Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 DocID022799 Rev 13 STM32L151xC STM32L152xC Package information Table 66. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 33. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint 069 1. Dimensions are in millimeters. DocID022799 Rev 13 111/136 135 Package information STM32L151xC STM32L152xC LQFP100 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 34. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example 3URGXFWLGHQWLILFDWLRQ 670/ 9&75 5HYLVLRQFRGH 'DWHFRGH < :: 3LQ LQGHQWLILHU 06Y9 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 112/136 DocID022799 Rev 13 STM32L151xC STM32L152xC LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package information Figure 35. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline PP *$8*(3/$1( F $ $ 6($7,1*3/$1( & $ $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( E ( 7.2 Package information H :B0(B9 1. Drawing is not to scale. Table 67. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - DocID022799 Rev 13 113/136 135 Package information STM32L151xC STM32L152xC Table 67. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0 3.5 7 0 3.5 7 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 36. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package recommended footprint AIC 1. Dimensions are in millimeters. 114/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Package information LQFP64 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 37. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package top view example 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 5 670/ 5&7 'DWHFRGH < :: 3LQ LQGHQWLILHU 06Y9 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DocID022799 Rev 13 115/136 135 Package information 7.3 STM32L151xC STM32L152xC LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package information Figure 38. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM '!5'% 0,!.% CCC # + ! $ $ , , $ % 0). )$%.4)&)#!4)/. E 1. Drawing is not to scale. 116/136 % % B DocID022799 Rev 13 "?-%?6 STM32L151xC STM32L152xC Package information Table 68. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 39. LQFP48 recommended footprint AID 1. Dimensions are in millimeters. DocID022799 Rev 13 117/136 135 Package information STM32L151xC STM32L152xC LQFP48 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 40. LQFP48 package top view example 3URGXFW LGHQWLILFDWLRQ 45.$$5 'DWHFRGH : 88 3LQ LGHQWLILFDWLRQ 5HYLVLRQFRGH 3 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 118/136 DocID022799 Rev 13 STM32L151xC STM32L152xC 7.4 Package information UFQFPN48 7 x 7 mm, 0.5 mm pitch, package information Figure 41. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline 3LQLGHQWLILHU ODVHUPDUNLQJDUHD ' $ ( ( 7 GGG $ 6HDWLQJ SODQH E H 'HWDLO< ' ([SRVHGSDG DUHD < ' / &[ SLQFRUQHU ( 5W\S 'HWDLO= = $%B0(B9 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground. DocID022799 Rev 13 119/136 135 Package information STM32L151xC STM32L152xC Table 69. UFQFPN48 - ultra thin fine pitch quad flat pack no-lead 7 x 7 mm, 0.5 mm pitch package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 42. UFQFPN48 recommended footprint 1. Dimensions are in millimeters. 120/136 DocID022799 Rev 13 !"?&0?6 STM32L151xC STM32L152xC Package information UFQFPN48 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 43. UFQFPN48 package top view example 3URGXFW LGHQWLILFDWLRQ 45.$$6 'DWHFRGH : 88 3LQ LGHQWLILFDWLRQ 5HYLVLRQFRGH 3 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DocID022799 Rev 13 121/136 135 Package information 7.5 STM32L151xC STM32L152xC UFBGA100, 7 x 7 mm, 100-ball ultra thin, fine pitch ball grid array package information Figure 44. UFBGA100, 7 x 7 mm, 0.5 mm pitch package outline = 6HDWLQJSODQH GGG = $ $ $ $ $ ( H $EDOO $EDOO LGHQWLILHU LQGH[DUHD ) ; ( $ ) ' ' H < 0 %277209,(: E EDOOV HHH 0 = < ; III 0 = 7239,(: $&B0(B9 1. Drawing is not to scale. Table 70. UFBGA100, 7 x 7 mm, 0.5 mm pitch package mechanical data inches(1) millimeters Symbol 122/136 Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 0.080 0.130 0.180 0.0031 0.0051 0.0071 A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.200 0.250 0.300 0.0079 0.0098 0.0118 D 6.950 7.000 7.050 0.2736 0.2756 0.2776 D1 5.450 5.500 5.550 0.2146 0.2165 0.2185 E 6.950 7.000 7.050 0.2736 0.2756 0.2776 E1 5.450 5.500 5.550 0.2146 0.2165 0.2185 e - 0.500 - - 0.0197 - F 0.700 0.750 0.800 0.0276 0.0295 0.0315 ddd - - 0.100 - - 0.0039 DocID022799 Rev 13 STM32L151xC STM32L152xC Package information Table 70. UFBGA100, 7 x 7 mm, 0.5 mm pitch package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 45. UFBGA100, 7 x 7 mm, 0.5 mm pitch, package recommended footprint 'SDG 'VP $&B)3B9 Table 71. UFBGA100, 7 x 7 mm, 0.50 mm pitch, recommended PCB design rules Dimension Recommended values Pitch 0.5 Dpad 0.280 mm Dsm 0.370 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 0.125 mm DocID022799 Rev 13 123/136 135 Package information STM32L151xC STM32L152xC UFBGA100 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 46. UFBGA100, 7 x 7 mm, 0.5 mm pitch, package top view example 3URGXFW LGHQWLILFDWLRQ 45.7$) 'DWHFRGH : 88 %DOO$ LGHQWLILHU 5HYLVLRQFRGH 3 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 124/136 DocID022799 Rev 13 STM32L151xC STM32L152xC 7.6 Package information WLCSP63, 0.400 mm pitch wafer level chip size package information Figure 47. WLCSP63, 0.400 mm pitch wafer level chip size package outline H EEE $%DOOORFDWLRQ ) * 'HWDLO$ H H * ) H $ %RWWRPYLHZ %XPEVLGH $ $ 6LGHYLHZ ' %XPS $ $ ( HHH $UHIHUHQFH ORFDWLRQ E FFF GGG DDD 7RSYLHZ :DIHUEDFN6LGH = ;< = 6HDWLQJSODQH 'HWDLO$ URWDWHG $7*B0(B9 1. Drawing is not to scale. DocID022799 Rev 13 125/136 135 Package information STM32L151xC STM32L152xC Table 72. WLCSP63, 0.400 mm pitch wafer level chip size package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.540 0.570 0.600 0.0213 0.0224 0.0236 A1 - 0.190 - - 0.0075 - A2 - 0.380 - - 0.0150 - A3 - 0.025 - - 0.0010 - Ob 0.240 0.270 0.300 0.0094 0.0106 0.0118 D 3.193 3.228 3.263 0.1257 0.1271 0.1285 E 4.129 4.164 4.199 0.1626 0.1639 0.1653 e - 0.400 - - 0.0157 - e1 - 2.400 - - 0.0945 - e2 - 3.200 - - 0.1260 - F - 0.414 - - 0.0163 - G - 0.482 - 0.0190 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. 126/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Package information WLCSP63 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 48. WLCSP63 device marking example 3URGXFWLGHQWLILFDWLRQ -6$: 'DWHFRGH 5HYLVLRQFRGH : 88 3 %DOO$ LGHQWLILHU 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DocID022799 Rev 13 127/136 135 Package information 7.7 STM32L151xC STM32L152xC Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: * TA max is the maximum ambient temperature in C, * JA is the package junction-to-ambient thermal resistance, in C/W, * PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), * PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 73. Thermal characteristics Symbol JA 128/136 Parameter Value Thermal resistance junction-ambient UFBGA100 - 7 x 7 mm 59 Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch 43 Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch 46 Thermal resistance junction-ambient WLCSP63 - 0.400 mm pitch 49 Thermal resistance junction-ambient LQFP48 - 7 x 7 mm / 0.5 mm pitch 55 Thermal resistance junction-ambient UFQFPN48 - 7 x 7 mm / 0.5 mm pitch 33 DocID022799 Rev 13 Unit C/W STM32L151xC STM32L152xC Package information Figure 49. Thermal resistance suffix 6 &Z d:d: :/&63 3' P: /4)3[PP 8)%*$[PP /4)3[PP 8)4)31[PP /4)3[PP 7HPSHUDWXUH & D^s Figure 50. Thermal resistance suffix 7 )RUELGGHQDUHD 7-!7-PD[ :/&63 3' P: /4)3[PP 8)%*$[PP /4)3[PP 8)4)31[PP /4)3[PP 7HPSHUDWXUH & 06Y9 7.7.1 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. DocID022799 Rev 13 129/136 135 Part numbering 8 STM32L151xC STM32L152xC Part numbering Table 74. STM32L151xC and STM32L152xC ordering information scheme Example: STM32 L 151 R C T 6 D TR Device family STM32 = ARM-based 32-bit microcontroller Product type L = Low-power Device subfamily 151: Devices without LCD 152: Devices with LCD Pin count C = 48 pins U = 63 pins R = 64 pins V = 100 pins Flash memory size C = 256 Kbytes of Flash memory Package H = BGA T = LQFP Y = WLCSP U = UFQFPN Temperature range 6 = Industrial temperature range, -40 to 85 C 7 = Industrial temperature range, -40 to 105 C Options No character = VDD range: 1.8 to 3.6 V and BOR enabled D = VDD range: 1.65 to 3.6 V and BOR disabled Packing TR = tape and reel No character = tray or tube For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the nearest ST sales office. 130/136 DocID022799 Rev 13 STM32L151xC STM32L152xC 9 Revision History Revision History Table 75. Document revision history Date Revision 21-Feb-2012 1 Initial release. 2 Added WLCSP63 package. Updated Figure 1: Ultra-low-power STM32L162xC block diagram. Changed maximum number of touch sensing channels to 34, and updated Table 2: Ultralow power STM32L15xxC device features and peripheral counts. Added Table 4: Functionalities depending on the working mode (from Run/active down to standby), and Table 3: ange depending on dynamic voltage scaling. Updated Section 3.10: ADC (analog-to-digital converter) to add Section 3.10.1: Temperature sensor and Section 3.10.2: Internal voltage reference (VREFINT). Updated Figure 3: STM32L162VC LQFP100 pinout. Table 10: STM32L15xxC pin definitions: updated name of reference manual in footnote 5. Changed I2C1_SMBAI into I2C1_SMBA in Table 10: STM32L15xxC pin definitions. Modified PB10/11/12 for AFIO4 alternate function, and replaced LBAR by NADV for AFIO12 in Table 10: Alternate function input/output. Removed caution note below Figure 8: Power supply scheme. Added Note 2 in Table 15: Embedded reset and power control block characteristics. Updated Table 14: General operating conditions. Updated Table 22: Typical and maximum current consumptions in Stop mode and added Note 6. Updated Table 23: Typical and maximum current consumptions in Standby mode. Updated tWUSTOP in Table : . Updated Table 26: Peripheral current consumption. Updated Table 60: SPI characteristics, added Note 1 and Note 3, and applied Note 2 to tr(SCK), tf(SCK), tw(SCKH), tw(SCKL), tsu(MI), tsu(SI), th(MI), and th(SI). Added Table 61: I2S characteristics, Figure 29: I2S slave timing diagram (Philips protocol)(1) and Figure 30: I2S master timing diagram (Philips protocol)(1). Updated Table 72: Temperature sensor characteristics. Added Figure 40: Thermal resistance. 12-Oct-2012 Changes DocID022799 Rev 13 131/136 135 Revision History STM32L151xC STM32L152xC Table 75. Document revision history (continued) Date 01-Feb-2013 02-Sep-2013 132/136 Revision Changes 3 Removed AHB1/AHB2 and corrected typo on APB1/APB2 in:Figure 1: Ultra-low-power STM32L162xC block diagram-low-power STM32L162xC block diagram Updated "OP amp" line in Table 4: Functionalities depending on the working mode (from Run/active down to standby) Added IWDG and WWDG rows in Table 4: Functionalities depending on the working mode (from Run/active down to standby) Updated address range in Table 7: Internal voltage reference measured values The comment "HSE = 16 MHz(2) (PLL ON for fHCLK above 16 MHz)" replaced by "fHSE = fHCLK up to 16 MHz included, fHSE = fHCLK/2 above 16 MHz (PLL ON)(2)" in table Table 27: Current consumption in Sleep mode replaced pin names D7,C7,C6,C8,B8,A8 respectively by D11,D10,C12,B12,A12,A11 in column UFBGA100 of Table 9: STM32L15xxC pin definitionsAdded more alternate functions supported on pin K3 and M4 for UFBGA100 package in Table 9: STM32L15xxC pin definitions Added part number STM32L151CC in Table 1: Device summary Updated Stop mode current to 1.5 A in Ultra-low-power platform Updated entire Section 7: Package information 4 Removed UFBGA132 and LQFP144 packages Removed first sentence in Section : I2C interface characteristics Added Section Table 5.: VLCD rail decoupling Added VRAIL functions in Table 9: STM32L15xxC pin definitions Updated PH0-OSC_IN and PH1-OSC_OUT type in Table 9: STM32L15xxC pin definitions. Added Table 6.1.7: Optional LCD power supply scheme. Updated consumption data in Table 6.3.4: Supply current characteristics Updated Table 7: Pin loading conditions Updated Table 8: Pin input voltage Updated Table 15: Typical application with a 32.768 kHz crystal Updated Table 25: Recommended NRST pin protection Table 26: I2C bus AC waveforms and measurement circuitUpdated Table 35: Typical connection diagram using the ADC and definition of symbol "RAIN" in Table 77: ADC characteristics Updated dThreshold/dt conditions in Table 85: Comparator 2 characteristics. Updated Table 49: Thermal resistance suffix 6. Added D2 and E2 in Table 69: UFQFPN48 - ultra thin fine pitch quad flat pack no-lead 7 x 7 mm, 0.5 mm pitch package mechanical data Fixed columns inversion in Table 67: LQFP64, 10 x 10 mm 64-pin lowprofile quad flat package mechanical data and Table 70: UFBGA100, 7 x 7 mm, 0.5 mm pitch package mechanical data DocID022799 Rev 13 STM32L151xC STM32L152xC Revision History Table 75. Document revision history (continued) Date 12-Nov-2013 Revision Changes 5 Updated Section 3.15: Touch sensing. Added VDD= 1.71 to 1.8 V operating power supply range in Table 4: Functionalities depending on the working mode (from Run/active down to standby) Renamed "I/O Level" to "I/O structure" in Table 9: STM32L15xxC pin definitions, added the I/O structure for PC14, PC15, PC3, PH0, PH1, PA3, PA4, PA5, PB0, PE7, PE8, PE9, PE10, NRST and BOOT0 Updated Table 10: Voltage characteristics added row Updated Table 11: Current characteristics replaced with the one inside STM32L15xxBxxA datasheet. Updated Table 13: General operating conditions, footnote and added row. Updated Table 15: Embedded internal reference voltage calibration values and moved inside Section 6.3.3: Embedded internal reference voltage Updated Section 6.3.4: Supply current characteristics. Updated Table 19: Current consumption in Run mode, code with data processing running from Flash. Updated Table 22: Current consumption in Run mode, code with data processing running from RAM. Created Section 6.3.5: Wakeup time from low-power mode.. Updated Table 38: High-speed external user clock characteristics. Moved Figure 12: High-speed external clock source AC timing diagram after Table 38: High-speed external user clock characteristics. Updated Table 40: HSE oscillator characteristics. Updated Section 6.3.12: Electrical sensitivity characteristics (title). Updated Section 6.3.13: I/O current injection characteristics. Updated Table 61: I/O current injection susceptibility and added footnote. Updated Table 63: I/O static characteristics Updated Section 6.3.15: NRST pin characteristics. Updated Table 77: ADC characteristics. Added footnote(5) and (6) in Table 77: ADC characteristics Updated THD values and added 4 more rows ENOB, SINAD, SNR, THD in Table 78: ADC accuracy Updated "SDA data hold time" and "SDA and SCL rise time" values and added "Pulse width of spikes that are suppressed by the analog filter" row in Table 68: I2C characteristics Updated direct channels VDDA range in Table 79: RAIN max for fADC = 16 MHz Moved Table 82: Temperature sensor calibration values and moved inside Section 6.3.23: Temperature sensor characteristics Updated IDD (WU from Standby) unit in Table 31: Typical and maximum current consumptions in Standby mode. Updated Table 67: LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data Updated Chapter 8: Part numbering (title). DocID022799 Rev 13 133/136 135 Revision History STM32L151xC STM32L152xC Table 75. Document revision history (continued) Date Revision Changes 6 Apply footnote 1 also to VDD= 1.8 to 2.0 V in Table 2: Functionalities depending on the operating power supply range. Updated Iinj pin in Table 11: Current characteristics. Added Input Voltage in Table 13: General operating conditions. Updated Input leakage current conditions in Table 63: I/O static characteristics Removed minimum value for fSin Table 77: ADC characteristics. Removed Finput for ENOB,SINAD,SNR,THD in Table 78: ADC accuracy. Added tolerance for TS_CAL1 and TS_CAL2 in Table 82: Temperature sensor calibration values. 7 Updated Section 3.7: Memories, Table 33: Peripheral current consumption : updated Flash value, Table 61: I/O current injection susceptibility, Table 63: I/O static characteristics:added BOOT0 pin Table 66: NRST pin characteristics, Chapter 2.2: Ultra-low-power device continuum. removed figures "Power supply and reference decoupling (VREF+ not connected to VDDA) and "Power supply and reference decoupling(VREF+ connected to VDDA). Updated Table 19: Current consumption in Run mode, code with data processing running from Flash Updated Section 6.3.1: General operating conditions. Updated Table 80: DAC characteristics Added marking for LQFP48/UFQFPN48 packages Updated Table 66: NRST pin characteristics Updated Table 63: I/O static characteristics 8 Updated IIO in Table 12: Current characteristics. Updated conditions in Table 44: Output voltage characteristics. Removed note 4 in Table 62: Temperature sensor characteristics Updated the conditions in Table 26: Low-power mode wakeup timings. Removed ambiguity of "ambient temperature" in the electrical characteristics description. 13-Oct-2014 9 Updated Section 3.17: Communication interfaces putting I2S characteristics inside. Updated DMIPS features in cover page and Section 2: Description. Updated max temperature at 105C instead of 85C in the whole datasheet. Updated current consumption in Table 20: Current consumption in Sleep mode. Updated Table 25: Peripheral current consumption with new measured current values. Updated Table 58: Maximum source impedance RAIN max adding note 2. 06-Mar-2015 10 Updated Section 7: Package information with new package device marking. Updated Figure 9: Memory map. 09-Dec-2013 13-Mar-2014 16-May-2014 134/136 DocID022799 Rev 13 STM32L151xC STM32L152xC Revision History Table 75. Document revision history (continued) Date 20-Aug-2015 10-Mar-2016 25-Aug-2017 Revision Changes 11 Updated Table 17: Embedded internal reference voltage temperature coefficient at 100ppm/C and table footnote 3: "guaranteed by design" changed by "guaranteed by characterization results". Updated Table 64: Comparator 2 characteristics new maximum threshold voltage temperature coefficient at 100ppm/C. 12 Updated cover page putting eight SPIs in the peripheral communication interface list. Updated Table 2: Ultra-low-power STM32L151xC and STM32L152xC device features and peripheral counts SPI and I2S lines. Updated Table 40: ESD absolute maximum ratings CDM class. Updated all the notes, removing `not tested in production'. Updated thermal resistance for UFQFPN48 to value of 33 C/W. Updated Table 11: Voltage characteristics adding note about VREF- pin. Updated Table 5: Functionalities depending on the working mode (from Run/active down to standby) LSI and LSE functionalities putting "Y" in Standby mode. Removed note 1 below Figure 2: Clock tree. 13 Updated Table 43: I/O static characteristics pull-up and pull-down values. Updated Table 46: NRST pin characteristics pull-up values. Updated Section 7: Package information adding information about other optional marking or inset/upset marks. Updated note 1 below all the package device marking figures. Updated Section 7: Package information replacing "Marking of engineering samples" by "device marking". Updated Nested vectored interrupt controller (NVIC) in Section 3.2: ARM(R) Cortex(R)-M3 core with MPU about process state automatically saved. Updated Table 3: Functionalities depending on the operating power supply range removing I/O operation column and adding note about GPIO speed. Updated Table 42: I/O current injection susceptibility note by `injection is not possible'. Updated Figure 20: Recommended NRST pin protection note about the 0.1uF capacitor. Updated Table 59: DAC characteristics resistive load. Updated Section 3.1: Low-power modes Low-power run mode (MSI) RC oscillator clock. Updated Table 5: Functionalities depending on the working mode (from Run/active down to standby) disabling I2C functionality in Lowpower Run and Low-power Sleep modes. DocID022799 Rev 13 135/136 135 STM32L151xC STM32L152xC IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2017 STMicroelectronics - All rights reserved 136/136 DocID022799 Rev 13