CY14B104NA 4-Mbit (256K x 16) Automotive nvSRAM 4-Mbit (256K x 16) Automotive nvSRAM Features 25 ns and 45 ns access times Internally organized as 256K x 16 Hands off automatic STORE on power-down with only a small capacitor STORE to QuantumTrap non-volatile elements initiated by software, device pin, or AutoStore on power-down RECALL to SRAM initiated by software or power-up High reliability Infinite read, write, and recall cycles STORE cycles to QuantumTrap * Automotive-A: 1,000K STORE cycles * Automotive-E: 100K STORE cycles Data retention Automotive-A: 20 years Automotive-E: 1 year Automotive-A Temperature: -40 C to +85 C Single 3 V +20, -10 Operation Automotive-E Temperature: -40 C to +125 C Single 3.3 V + 0.3 V Operation Packages 48-ball fine-pitch ball grid array (FBGA) 44-pin thin small outline package (TSOP) Type II Pb-free and restriction of hazardous substances (RoHS) compliant Functional Description The Cypress CY14B104NA is a fast static RAM (SRAM), with a non-volatile element in each memory cell. The memory is organized as 256K words of 16-bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world's most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent non-volatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. Logic Block Diagram Cypress Semiconductor Corporation Document Number: 001-54469 Rev. *H * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised January 12, 2017 CY14B104NA Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 4 Device Operation .............................................................. 5 SRAM Read ................................................................ 5 SRAM Write ................................................................. 5 AutoStore Operation .................................................... 5 Hardware STORE Operation ....................................... 5 Hardware RECALL (Power-Up) .................................. 6 Software STORE ......................................................... 6 Software RECALL ....................................................... 6 Preventing AutoStore .................................................. 8 Data Protection ............................................................ 8 Maximum Ratings ............................................................. 9 Operating Range ............................................................... 9 DC Electrical Characteristics .......................................... 9 Data Retention and Endurance ..................................... 10 Capacitance .................................................................... 10 Thermal Resistance ........................................................ 10 AC Test Loads ................................................................ 11 AC Test Conditions ........................................................ 11 AC Switching Characteristics ....................................... 12 Switching Waveforms .................................................... 13 Document Number: 001-54469 Rev. *H AutoStore/Power-Up RECALL ....................................... 16 Switching Waveforms - AutoStore/Power-up RECALL ....................................... 16 Software Controlled STORE/RECALL Cycle ................ 17 Switching Waveforms - Software Controlled STORE/RECALL Cycle ................ 17 Hardware STORE Cycle ................................................. 18 Switching Waveforms - Hardware STORE Cycle ........ 18 Truth Table For SRAM Operations ................................ 19 Ordering Information ...................................................... 20 Ordering Code Definitions ......................................... 20 Package Diagrams .......................................................... 21 Acronyms ........................................................................ 23 Document Conventions ................................................. 23 Units of Measure ....................................................... 23 Document History Page ................................................. 24 Sales, Solutions, and Legal Information ...................... 25 Worldwide Sales and Design Support ....................... 25 Products .................................................................... 25 PSoC(R)Solutions ....................................................... 25 Cypress Developer Community ................................. 25 Technical Support ..................................................... 25 Page 2 of 25 CY14B104NA Pinouts Figure 1. 48-ball FBGA pinout 48-ball FBGA (x 16) Top View (not to scale) 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A DQ8 BHE A3 A4 CE DQ0 B DQ9 DQ10 A5 A6 DQ1 DQ2 C VSS A17 A7 DQ3 VCC D VCC DQ12 VCAP A16 DQ4 VSS E DQ14 DQ13 A14 A15 DQ5 DQ6 F DQ15 HSB A12 A13 WE DQ7 G A9 A10 A11 NC H NC [1] DQ11 A8 Figure 2. 44-pin TSOP II pinout (x 16) A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 [3] 44-pin TSOP II (x 16) Top View (not to scale) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 Notes 1. Address expansion for 8-Mbit. NC pin not connected to die. 2. Address expansion for 16-Mbit. NC pin not connected to die. 3. HSB pin is not available in 44-pin TSOP II (x 16) package. Document Number: 001-54469 Rev. *H Page 3 of 25 CY14B104NA Pin Definitions Pin Name I/O Type A0-A17 Input Description Address inputs. Used to Select one of the 262,144 words of the nvSRAM. DQ0-DQ15 Input/Output Bidirectional data I/O lines. Used as input or output lines depending on operation. WE Input Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific address location. CE Input Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. OE Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. I/O pins are tristated on deasserting OE HIGH. BHE Input Byte High Enable, Active LOW. Controls DQ15-DQ8. BLE VSS Input Byte Low Enable, Active LOW. Controls DQ7-DQ0. Ground Ground for the device. Must be connected to the ground of the system. VCC Power supply Power supply inputs to the device. HSB Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. After each Hardware and Software STORE operation, HSB is driven HIGH for a short time (tHHHD) with standard output high current, and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection optional). VCAP Power supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to non-volatile elements. NC No connect No Connect. This pin is not connected to the die. Document Number: 001-54469 Rev. *H Page 4 of 25 CY14B104NA The CY14B104NA nvSRAM is made up of two functional components paired in the same physical cell. They are a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations, SRAM read and write operations are inhibited. The CY14B104NA supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the non-volatile cells. Refer to the Truth Table For SRAM Operations on page 19 for a complete description of read and write modes. SRAM Read The CY14B104NA performs a read cycle when CE and OE are LOW and WE and HSB are HIGH. The address specified on pins A0-17 determines which of the 262,144 words of 16 bits each are accessed. Byte enables (BHE, BLE) determine which bytes are enabled to the output, in the case of 16-bit words. When the read is initiated by an address transition, the outputs are valid after a delay of tAA (read cycle 1). If the read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (read cycle 2). The data output repeatedly responds to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. SRAM Write A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ0-15 are written into the memory if the data is valid (tSD time) before the end of a WE controlled write or before the end of an CE controlled write. The Byte Enable inputs (BHE, BLE) determine which bytes are written, in the case of 16-bit words. It is recommended that OE be kept HIGH during the entire write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. AutoStore Operation The CY14B104NA stores data to the nvSRAM using one of the following three storage operations: Hardware STORE activated by the HSB; Software STORE activated by an address sequence; AutoStore on device power-down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B104NA. During a normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Note If the capacitor is not connected to VCAP pin, AutoStore must be disabled using the soft sequence specified in Preventing Document Number: 001-54469 Rev. *H AutoStore on page 8. In case AutoStore is enabled without a capacitor on VCAP pin, the device attempts an AutoStore operation without sufficient charge to complete the Store. This corrupts the data stored in nvSRAM. Figure 3 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to DC Electrical Characteristics on page 9 for the size of VCAP. The voltage on the VCAP pin is driven to VCC by a regulator on the chip. A pull-up should be placed on WE to hold it inactive during power-up. This pull-up is effective only if the WE signal is tristate during power-up. Many MPUs tristate their controls on power-up. This should be verified when using the pull-up. When the nvSRAM comes out of power-on-RECALL, the MPU must be active or the WE held inactive until the MPU comes out of reset. To reduce unnecessary non-volatile stores, AutoStore and hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. Figure 3. AutoStore Mode VCC 0.1 uF 10 kOhm Device Operation VCC WE VCAP VSS VCAP Hardware STORE Operation The CY14B104NA provides the HSB pin to control and acknowledge the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven LOW, the CY14B104NA conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver (internal 100 k weak pull-up resistor) that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. Note After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then remains HIGH by internal 100 k pull-up resistor. SRAM write operations that are in progress when HSB is driven LOW by any means are given time (tDELAY) to complete before the STORE operation is initiated. However, any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. In case the write latch is not set, HSB is not driven LOW by the CY14B104NA. But any SRAM read and write cycles Page 5 of 25 CY14B104NA are inhibited until HSB is returned HIGH by MPU or other external source. During any STORE operation, regardless of how it is initiated, the CY14B104NA continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after HSB pin returns HIGH. Leave the HSB unconnected if it is not used. Hardware RECALL (Power-Up) During power-up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the VSWITCH on power up, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, the HSB pin is driven LOW by the HSB driver and all reads and writes to nvSRAM are inhibited. Software STORE Data is transferred from the SRAM to the non-volatile memory by a software address sequence. The CY14B104NA software STORE cycle is initiated by executing sequential CE or OE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous non-volatile data is first performed, followed by a program of the non-volatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of reads from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following read sequence must be performed. Document Number: 001-54469 Rev. *H 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8FC0 Initiate STORE cycle The software sequence may be clocked with CE controlled reads or OE controlled reads, with WE kept HIGH for all the six READ sequences. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation. Software RECALL Data is transferred from the non-volatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, perform the following sequence of CE or OE controlled read operations must be performed. 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4C63 Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the non-volatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the non-volatile elements. Page 6 of 25 CY14B104NA Table 1. Mode Selection CE WE OE BHE, BLE A15-A0[4] Mode I/O Power H X X X X Not selected Output high Z Standby L H L L X Read SRAM Output data Active L L X L X Write SRAM Input data Active L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Output data Output data Output data Output data Output data Output data Active[5] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Output data Output data Output data Output data Output data Output data Active[6] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Non-volatile STORE Output data Output data Output data Output data Output data Output high Z Active ICC2[6] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Non-volatile RECALL Output data Output data Output data Output data Output data Output high Z Active[6] Notes 4. While there are 18 address lines on the CY14B104NA, only 13 address lines (A14-A2) are used to control software modes. The remaining address lines are don't care. 5. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle. 6. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle. Document Number: 001-54469 Rev. *H Page 7 of 25 CY14B104NA Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8B45 AutoStore Disable The AutoStore is re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the Document Number: 001-54469 Rev. *H AutoStore enable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4B46 AutoStore Enable If the AutoStore function is disabled or re-enabled, a manual STORE operation (hardware or software) must be issued to save the AutoStore state through subsequent power-down cycles. The part comes from the factory with AutoStore enabled and 0x00 written in all cells. Data Protection The CY14B104NA protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC < VSWITCH. If the CY14B104NA is in a write mode (both CE and WE are LOW) at power-up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). This protects against inadvertent writes during power-up or brown out conditions. Page 8 of 25 CY14B104NA Maximum Ratings Transient voltage (< 20 ns) on any pin to ground potential ............ -2.0 V to VCC + 2.0 V Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Package power dissipation capability (TA = 25 C) ................................................................. 1.0 W Storage temperature ................................ -65 C to +150 C Surface mount Pb soldering temperature (3 Seconds) ............................................................. +260 C Maximum accumulated storage time At 150 C ambient temperature ...................... 1000 h DC output current (1 output at a time, 1s duration) .... 15 mA At 85 C ambient temperature ..................... 20 Years Static discharge voltage (per MIL-STD-883, Method 3015) .......................... > 2001 V At 125 C ambient temperature ....................... 1 Year Latch up current ..................................................... > 200 mA Ambient temperature with power applied ................................... -55 C to +150 C Operating Range Supply voltage on VCC relative to VSS ...........-0.5 V to 4.1 V Range Automotive-A Automotive-E Voltage applied to outputs in high Z state ..................................... -0.5 V to VCC + 0.5 V Input voltage ........................................-0.5 V to Vcc + 0.5 V Ambient Temperature -40 C to +85 C -40 C to +125 C VCC 2.7 V to 3.6 V 3.0 V to 3.6 V DC Electrical Characteristics Over the Operating Range Parameter VCC ICC1 Description Power supply Typ [7] Max Unit Automotive-A 2.7 3.0 3.6 V Automotive-E 3.0 3.3 3.6 V Automotive-A - - 70 mA tRC = 45 ns Automotive-A Values obtained without output Automotive-E loads (IOUT = 0 mA) - - 52 mA - - 65 mA Average VCC current during STORE All inputs don't care, VCC = Max Average current for duration tSTORE Automotive-A - - 10 mA Automotive-E - - 15 mA ICC3 Average VCC current at tRC = 200 ns, VCC(Typ), 25 C All inputs cycling at CMOS levels. Values obtained without output loads (IOUT = 0 mA). - 35 - mA ICC4[8] Average VCAP current during AutoStore cycle All inputs don't care. Average Automotive-A current for duration tSTORE Automotive-E - - 5 mA - - 10 mA ISB VCC standby current Automotive-A CE > (VCC - 0.2 V). VIN < 0.2 V or > (VCC - 0.2 V). Automotive-E Standby current level after non-volatile cycle is complete. Inputs are static. f = 0 MHz. - - 5 mA - - 10 mA ICC2 IIX[9] Average VCC current Min Test Conditions Input leakage current (except tRC = 25 ns VCC = Max, VSS < VIN < VCC HSB) Input leakage current (for HSB) IOZ VCC = Max, VSS < VIN < VCC Automotive-A -1 - +1 A Automotive-E -5 - +5 A Automotive-A -100 - +1 A Automotive-E -100 - +5 A Off-state output leakage current VCC = Max, VSS < VOUT < VCC, Automotive-A -1 - +1 A Automotive-E -5 - +5 A CE or OE > VIH or BHE/BLE > VIH or WE < VIL Notes 7. Typical values are at 25 C, VCC = VCC(Typ). Not 100% tested. 8. This parameter is guaranteed by design but not tested. 9. The HSB pin has IOUT = -2 A for VOH of 2.4 V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This parameter is characterized but not tested. Document Number: 001-54469 Rev. *H Page 9 of 25 CY14B104NA DC Electrical Characteristics (continued) Over the Operating Range Parameter VIH Description Min Typ [7] Max Unit Automotive-A 2.0 - VCC + 0.5 V Automotive-E 2.2 - VCC + 0.5 V Vss - 0.5 - 0.8 V 2.4 - - V Test Conditions Input HIGH voltage VIL Input LOW voltage VOH Output HIGH voltage VOL Output LOW voltage IOUT = 4 mA - - 0.4 V VCAP[10] Storage capacitor Between VCAP pin and VSS, 5 V rated 61 68 180 F IOUT = -2 mA Data Retention and Endurance Over the Operating Range Parameter DATAR NVC Description Data retention Non-volatile STORE operations Min Unit Automotive-A 20 Years Automotive-E 1 Automotive-A 1,000 Automotive-E 100 K Capacitance Parameter[11] CIN Description Test Conditions Max Unit 7 pF 8 pF Output capacitance (except HSB) 7 pF Output capacitance (for HSB) 8 pF Input capacitance (except BHE, TA = 25 C, f = 1 MHz, VCC = VCC(Typ) BLE and HSB) Input capacitance (for BHE, BLE and HSB) COUT Thermal Resistance Parameter [11] JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 48-pin FBGA 44-pin TSOP II Unit 46.09 43.3 C/W 7.84 5.56 C/W Notes 10. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor on VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on VCAP options. 11. These parameters are guaranteed by design but not tested. Document Number: 001-54469 Rev. *H Page 10 of 25 CY14B104NA AC Test Loads Figure 4. AC Test Loads 577 577 3.0 V 3.0 V R1 for tristate specs R1 OUTPUT OUTPUT 30 pF R2 789 5 pF R2 789 AC Test Conditions Input pulse levels .................................................. 0 V to 3 V Input rise and fall times (10%-90%) ........................... < 3 ns Input and output timing reference levels ...................... 1.5 V Document Number: 001-54469 Rev. *H Page 11 of 25 CY14B104NA AC Switching Characteristics Over the Operating Range Parameters [12] Cypress Parameter 25 ns Description Alt Parameter 45 ns Min Max Min Max Unit SRAM Read Cycle tACE tACS Chip enable access time - 25 - 45 ns tRC[13] tRC Read cycle time 25 - 45 - ns tAA[14] tAA Address access time - 25 - 45 ns tDOE tOE Output enable to data valid - 12 - 20 ns tOHA[14] tLZCE[15, 16] tHZCE[15, 16] tLZOE[15, 16] tHZOE[15, 16] tPU[15] tPD[15] tOH Output hold after address change 3 - 3 - ns tLZ Chip enable to output active 3 - 3 - ns tHZ Chip disable to output inactive - 10 - 15 ns tOLZ Output enable to output active 0 - 0 - ns tOHZ Output disable to output inactive - 10 - 15 ns tPA Chip enable to power active 0 - 0 - ns tPS Chip disable to power standby - 25 - 45 ns tDBE - Byte enable to data valid - 12 - 20 ns tLZBE[15] tHZBE[15] - Byte enable to output active 0 - 0 - ns - Byte disable to output inactive - 10 - 15 ns SRAM Write Cycle tWC tWC Write cycle time 25 - 45 - ns tPWE tWP Write pulse width 20 - 30 - ns tSCE tCW Chip enable to end of write 20 - 30 - ns tSD tDW Data setup to end of write 10 - 15 - ns tHD tDH Data hold after end of write 0 - 0 - ns tAW tAW Address setup to end of write 20 - 30 - ns tSA tAS Address setup to start of write 0 - 0 - ns tHA tWR Address hold after end of write 0 - 0 - ns tHZWE[15, 16, 17] tLZWE[15, 16] tWZ Write enable to output disable - 10 - 15 ns tOW Output active after end of write 3 - 3 - ns tBW - Byte enable to end of write 20 - 30 - ns Notes 12. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH and load capacitance shown in Figure 4 on page 11. 13. WE must be HIGH during SRAM read cycles. 14. Device is continuously selected with CE, OE and BHE / BLE LOW. 15. These parameters are guaranteed by design but not tested. 16. Measured 200 mV from steady state output voltage. 17. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. Document Number: 001-54469 Rev. *H Page 12 of 25 CY14B104NA Switching Waveforms Figure 5. SRAM Read Cycle No. 1 (Address Controlled) [18, 19, 20] tRC Address Address Valid tAA Data Output Output Data Valid Previous Data Valid tOHA Figure 6. SRAM Read Cycle No. 2 (CE and OE Controlled) [18, 20] Address Address Valid tRC tHZCE tACE CE tAA tLZCE tHZOE tDOE OE tHZBE tLZOE tDBE BHE, BLE tLZBE Data Output High Impedance Output Data Valid tPU ICC Standby tPD Active Notes 18. WE must be HIGH during SRAM read cycles. 19. Device is continuously selected with CE, OE and BHE / BLE LOW. 20. HSB must remain HIGH during read and write cycles. Document Number: 001-54469 Rev. *H Page 13 of 25 CY14B104NA Switching Waveforms (continued) Figure 7. SRAM Write Cycle No. 1 (WE Controlled) [21, 22, 23] tWC Address Address Valid tSCE tHA CE tBW BHE, BLE tAW tPWE WE tSA tSD Data Input Input Data Valid tHZWE Data Output tHD Previous Data tLZWE High Impedance Notes 21. HSB must remain HIGH during read and write cycles. 22. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 23. CE or WE must be >VIH during address transitions. Document Number: 001-54469 Rev. *H Page 14 of 25 CY14B104NA Switching Waveforms (continued) Figure 8. SRAM Write Cycle No. 2 (CE Controlled) [24, 25, 26] tWC Address Valid Address tSA tSCE tHA CE tBW BHE, BLE tPWE WE tHD tSD Input Data Valid Data Input High Impedance Data Output Figure 9. SRAM Write Cycle No. 3 (BHE and BLE Controlled) [24, 25, 26] tWC Address Address Valid tSCE CE tSA tHA tBW BHE, BLE tAW tPWE WE tSD Data Input tHD Input Data Valid High Impedance Data Output Notes 24. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 25. HSB must remain HIGH during read and write cycles. 26. CE or WE must be >VIH during address transitions. Document Number: 001-54469 Rev. *H Page 15 of 25 CY14B104NA AutoStore/Power-Up RECALL Over the Operating Range Parameter tHRECALL [27] tSTORE [28] 25 ns Description 45 ns Unit Min Max Min Max Power-Up RECALL duration - 20 - 20 ms STORE cycle duration - 8 - 8 ms tDELAY [29] Time allowed to complete SRAM write cycle - 25 - 25 ns VSWITCH Low voltage trigger level Automotive-A - 2.65 - 2.65 V Automotive-E - - - 2.95 V 150 - 150 - s VHDIS[30] HSB output disable voltage - 1.9 - 1.9 V tLZHSB[30] tHHHD[30] HSB to output active time - 5 - 5 s HSB high active time - 500 - 500 ns tVCCRISE [30] VCC rise time Switching Waveforms - AutoStore/Power-up RECALL Figure 10. AutoStore or Power-Up RECALL [31] VCC VSWITCH VHDIS t VCCRISE tHHHD Note 28 Note28 tSTORE tHHHD 32 Note tSTORE Note 32 HSB OUT tDELAY tLZHSB AutoStore tLZHSB tDELAY POWERUP RECALL tHRECALL tHRECALL Read & Write Inhibited (RWI) POWER-UP RECALL Read & Write BROWN OUT AutoStore POWER-UP RECALL Read & Write POWER DOWN AutoStore Notes 27. tHRECALL starts from the time VCC rises above VSWITCH. 28. If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware STORE takes place. 29. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY. 30. These parameters are guaranteed by design but not tested. 31. Read and write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. 32. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor. Document Number: 001-54469 Rev. *H Page 16 of 25 CY14B104NA Software Controlled STORE/RECALL Cycle Over the Operating Range Parameter [33, 34] 25 ns Description 45 ns Min Max Min Max Unit tRC STORE/RECALL initiation cycle time 25 - 45 - ns tSA Address setup time 0 - 0 - ns tCW Clock pulse width 20 - 30 - ns tHA Address hold time 0 - 0 - ns tRECALL RECALL duration - 200 - 200 s Switching Waveforms - Software Controlled STORE/RECALL Cycle Figure 11. CE and OE Controlled Software STORE/RECALL Cycle [34] tRC Address tRC Address #1 tSA Address #6 tCW tCW CE tHA tSA tHA tHA tHA OE tHHHD HSB (STORE only) tHZCE tLZCE t DELAY 35 Note tLZHSB High Impedance tSTORE/tRECALL DQ (DATA) RWI Figure 12. AutoStore Enable/Disable Cycle [34] Address tRC tRC Address #1 Address #6 tSA CE tCW tCW tHA tSA tHA tHA tHA OE tLZCE tHZCE tSS 35 Note t DELAY DQ (DATA) RWI Notes 33. The software sequence is clocked with CE controlled or OE controlled reads. 34. The six consecutive addresses must be read in the order listed in Table 1 on page 7. WE must be HIGH during all six consecutive cycles. 35. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time. Document Number: 001-54469 Rev. *H Page 17 of 25 CY14B104NA Hardware STORE Cycle Over the Operating Range Parameter 25 ns Description 45 ns Min Max Min Max Unit tDHSB HSB to output active time when write latch not set - 25 - 25 ns tPHSB Hardware STORE pulse width 15 - 15 - ns Soft sequence processing time - 100 - 100 s tSS [36, 37] Switching Waveforms - Hardware STORE Cycle Figure 13. Hardware STORE Cycle [38] Write latch set tPHSB HSB (IN) tSTORE tHHHD tDELAY HSB (OUT) tLZHSB DQ (Data Out) RWI Write latch not set tPHSB HSB pin is driven high to VCC only by Internal 100 kOhm resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven low. HSB (IN) HSB (OUT) tDELAY tDHSB tDHSB RWI Figure 14. Soft Sequence Processing [36, 37] Soft Sequence Command Address Address #1 tSA Address #6 tCW tSS Soft Sequence Command Address #1 tSS Address #6 tCW CE VCC Notes 36. This is the amount of time it takes to take action on a soft sequence command. VCC power must remain HIGH to effectively register command. 37. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. 38. If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware STORE takes place. Document Number: 001-54469 Rev. *H Page 18 of 25 CY14B104NA Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations. CE WE OE BHE BLE H X X X X High Z Deselect/Power-down Standby L X X H H High Z Output disabled Active L H L L L Data out (DQ0-DQ15) Read Active L H L H L Data out (DQ0-DQ7); DQ8-DQ15 in High Z Read Active L H L L H Data out (DQ8-DQ15); DQ0-DQ7 in High Z Read Active L H H L L High Z Output disabled Active L H H H L High Z Output disabled Active L H H L H High Z Output disabled Active L L X L L Data in (DQ0-DQ15) Write Active L L X H L Data in (DQ0-DQ7); DQ8-DQ15 in High Z Write Active L L X L H Data in (DQ8-DQ15); DQ0-DQ7 in High Z Write Active Document Number: 001-54469 Rev. *H Inputs/Outputs Mode Power Page 19 of 25 CY14B104NA Ordering Information Speed (ns) 25 Package Diagram Ordering Code CY14B104NA-ZS25XE Package Type 51-85087 44-pin TSOP II (Pb-free) Operating Range Automotive-E CY14B104NA-ZS25XET 45 CY14B104NA-BA45XE 51-85128 48-ball FBGA (Pb-free) CY14B104NA-BA45XET CY14B104NA-ZS45XE 51-85087 44-pin TSOP II (Pb-free) CY14B104NA-ZS45XET Ordering Code Definitions CY 14 B 104 N A - BA 45 X E T Option: T - Tape and Reel Blank - Std. X - Pb-free Blank - Sn Pb Die Revision: Blank - No Rev A - 1st Rev Temperature: A - Automotive-A (-40 C to 85 C) E - Automotive-E (-40 C to 125 C) Speed: 25 - 25 ns 45 - 45 ns Package: BA - 48-ball FBGA ZS - 44-pin TSOP II Data Bus: N - x 16 Density: 104 - 4 Mb Voltage: B - 3.0 V 14 - nvSRAM Cypress Document Number: 001-54469 Rev. *H Page 20 of 25 CY14B104NA Package Diagrams Figure 15. 48-ball FBGA (6 x 10 x 1.2 mm) Package Outline, 51-85128 51-85128 *G Document Number: 001-54469 Rev. *H Page 21 of 25 CY14B104NA Package Diagrams (continued) Figure 16. 44-pin TSOP II Package Outline, 51-85087 51-85087 *E Document Number: 001-54469 Rev. *H Page 22 of 25 CY14B104NA Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable C degree Celsius Chip Enable Hz hertz Complementary Metal Oxide Semiconductor kHz kilohertz EIA Electronic Industries Alliance k kilohm FBGA Fine-Pitch Ball Grid Array MHz megahertz HSB I/O Hardware Store Busy A microampere F microfarad nvSRAM nonvolatile Static Random Access Memory s microsecond Output Enable mA milliampere OE RoHS ms millisecond ns nanosecond RWI Read and Write Inhibited ohm SRAM Static Random Access Memory % percent WE Write Enable pF picofarad V volt W watt CE CMOS Input/Output Restriction of Hazardous Substances Document Number: 001-54469 Rev. *H Symbol Unit of Measure Page 23 of 25 CY14B104NA Document History Page Document Title: CY14B104NA, 4-Mbit (256K x 16) Automotive nvSRAM Document Number: 001-54469 Rev. ECN Orig. of Change Submission Date *F 5157487 GVCH 03/03/2016 Changed status from Preliminary to Final. *G 5349257 GVCH 07/13/2016 Added 44-pin TSOP II package related information in all instances across the document. Updated Ordering Information: Updated part numbers. Updated Ordering Code Definitions. Updated Package Diagrams: Added spec 51-85087 *E. Updated to new template. *H 5583673 GVCH 01/12/2017 Updated Ordering Information: Updated part numbers. Updated to new template. Document Number: 001-54469 Rev. *H Description of Change Page 24 of 25 CY14B104NA Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-54469 Rev. *H Revised January 12, 2017 Page 25 of 25