Dual Balanced Line Receiver ICs THAT 1280, 1283, 1286 FEATURES APPLICATIONS * High CMRR: typ. 90 dB at 60Hz * Balanced Audio Line Receivers * Self-contained * Excellent audio performance - Wide bandwidth: typ. >7.6 MHz - High slew rate: typ. 15 V/s - Low distortion: typ. 0.0006% THD - Low noise: typ. -104.5 dBu * Instrumentation Amplifiers * Low current: typ. 3 mA (per amplifier) * Precision Summers * Differential Amplifiers * Several gains: 0 dB, 3 dB, 6 dB * Current Shunt Monitors * Industry Standard Pinout Description reliability, matching, and small size of a fully integrated solution. The THAT 1280 series of precision differential amplifiers was designed primarily for use as balanced line receivers for audio applications. Gains of 0 dB, 3 dB, and 6 dB are available to suit various applications requirements. All three versions of the part typically exhibit 90 dB of common-mode rejection. With 15 V/s slew rate, 7.6 MHz or higher bandwidth, and 0.0006% THD, these devices are sonically transparent. Moreover, current consumption is typically a low 6 mA (3 mA per amplifier). These devices are laser-trimmed in wafer form to obtain the precision resistor matching needed for high CMR performance and precise gain. Manufactured in THAT Corporation's proprietary complementary dielectric isolation (DI) process, the 1280 series provides the sonic benefits of discrete designs with the simplicity, Ref A Out A Sns A 14 13 12 Vcc 11 The 1280 series is available in a 14-pin SOIC package. The 1280 is pin-compatible with the TI INA2134, and the 1286 is pin-compatible with the TI INA2137 and the ADI AD8273. Sns B Out B Ref B 10 9 8 R4 R2 R2 R3 R4 R1 R3 R1 1 2 NC In- A 3 In+ A Part No. Gain THAT1280 THAT1283 THAT1286 0 dB -3 dB -6 dB 4 Vee 5 6 In+ B R1 & R3 Figure 1. Equivalent circuit 7 In- B NC R 2 & R4 Pin Name Pin Number N/C 1 IN- A 2 IN+ A 3 VEE 4 IN+ B 5 IN- B 6 N/C 7 REF B 8 OUT B 9 SENSE B 10 VCC 11 SENSE A 12 OUT A 13 REF A 14 Table 1. Pin assignments THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright (c) 2007, THAT Corporation Document 600114 Rev 01 Document 600114 Rev 01 Page 2 of 10 THAT 1280 Series Dual Balanced Line Receiver ICs SPECIFICATIONS 1 Absolute Maximum Ratings 2,3 Supply Voltages (VCC - VEE) 40V Storage Temperature Range (TST) Maximum In- or In+ Voltage -50V + VCC, 50V + VEE Operating Temperature Range (TOP) Max/Min Ref or Sense Voltage VCC + 0.5V, VEE - 0.5V Output Short-Circuit Duration (tSH) Maximum Output Voltage (VOM) VCC + 0.5V, VEE - 0.5V Junction Temperature (TJ) -40 to +125 C -40 to +85 C Continuous +125 C Electrical Characteristics 2,4 Parameter Symbol Conditions Min Typ Max Units Supply Current ICC; -IEE No signal -- 6 8 mA Supply Voltage VCC-VEE 6 -- 36 V Input Voltage Range VIN-DIFF -- -- -- 21.5 24.5 27.5 -- -- -- dBu dBu dBu -- -- -- 27.5 29.1 31 -- -- -- dBu dBu dBu VIN-CM Input Impedance5 ZIN-DIFF Differential -- -- -- 18 21 24 -- -- -- k k k ZIN-CM 1280 (0dB gain) 1283 (-3dB gain) 1286 (-6dB gain) Common Mode All versions -- 18 -- k DC 60Hz 20kHz 70 70 -- 90 90 85 -- -- -- dB dB dB 3V to 18V; VCC = -VEE; all gains -- 90 -- dB 0.0006 -- % Common Mode Rejection Ratio CMRR Power Supply Rejection Ratio6 Total Harmonic Distortion Output Noise Slew Rate Differential (equal and opposite swing) 1280 (0dB gain) 1283 (-3dB gain) 1286 (-6dB gain) Common Mode 1280 (0dB gain) 1283 (-3dB gain) 1286 (-6dB gain) PSRR THD eOUT SR Matched source impedances; V CM = 10V Vout = 5Vrms, f = 1kHz, BW = 22kHz, R L = 2 k -- 22 Hz to 22kHz bandwidth 1280 (0dB gain) 1283 (-3dB gain) 1286 (-6dB gain) -- -- -- -104.5 -105.9 -107.3 -- -- -- dBu dBu dBu RL = 2k; CL = 300 pF, all gains 10.5 15 -- V/s 1. All specifications are subject to change without notice. 2. Unless otherwise noted, T A=25C, VCC=+15V, VEE= -15V. 3. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impli ed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4. 0 dBu = 0.775 Vrms. 5. While specific resistor ratios are very closely trimmed, absolute resistance values can vary 25% from the typical values show n. Input impedance is monitored by lot sampling. 6. Defined with respect to differential gain. 7. Parameter guaranteed over the entire range of power supply and temperature. THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright (c) 2007, THAT Corporation THAT 1280 Series Dual Balanced Line Receiver ICs Page 3 of 10 Document 600114 Rev 01 Electrical Characteristics (con't )2,4 Parameter Symbol Conditions Min Typ Max Units Small signal bandwidth BW-3dB RL = 2k; CL = 10 pF 1280 (0dB gain) 1283 (-3dB gain) 1286 (-6dB gain) -- -- -- 7.6 9.6 11.6 -- -- -- MHz MHz MHz -0.05 -- 0.05 dB Output Gain Error GER-OUT Output Voltage Swing VO+ VO- RL = 2k; CL = 200 pF RL = 2k; CL = 200 pF VCC-2.5 -- VCC-2 VEE+2 -- VEE+2.5 V V Output Offset Voltage VOFF No signal -1 -- 1 mV ISC RL = 0 -- 42 -- mA -- -- 300 pF -- 120 -- dB Output Short Circuit Current Capacitive Load 7 CL Channel Separation f = 1kHz VCC In- ~ R1 b R2 1/2vIN(DIFF) Sense Vout 1/2vIN(DIFF) ~ In+ R4 R 3 Ref a VIN(CM) ~ VEE Figure 2. Simplified test circuit (1/2 of 128x shown) THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright (c) 2007, THAT Corporation RL CL Document 600114 Rev 01 Page 4 of 10 THAT 1280 Series Dual Balanced Line Receiver ICs Theory of Operation The THAT 1280 series ICs consist of two high performance opamps with integrated, laser-trimmed resistors. These designs take advantage of THAT's fully complementary dielectric isolation (DI) process to deliver excellent performance with low current consumption. The devices are simple to apply in a wide range of applications. A further consideration is that after trimming, the two resistor divider ratios are tightly controlled, but the actual value of any individual resistor is not. The initial tolerance of the resistors is quite wide, so it is possible for any given resistor to vary over a surprisingly wide range. Lot-to-lot variations of up to 30 % are to be expected. Resistor Trimming, Values, and CMRR Input Considerations The 1280-series devices rely upon proprietary, laser-trimmed, silicon-chromium (Si-Cr), thin-film, integrated resistors to deliver the precise matching required to achieve a 90 dB common mode rejection ratio. Trimming is performed in two cycles, both using dc inputs. First, gain is set by trimming the R1/R2 pair. Then, CMRR is set by trimming the other pair (R3/R4). Generally, only one resistor of each pair is trimmed (whichever needs to increase to meet the required specification). The 1280-series devices are internally protected against input overload via an unusual arrangement of diodes connecting the + and - input pins to the power supply pins. The circuit of Figure 3 shows the arrangement used for the R3/R4 side; a similar one applies to the other side. The zener diodes prevent the protection network from conducting until an input pin is raised at least 50 V above VCC or lowered 50V below VEE. Thus, the protection networks protect the devices without constraining the allowable signal swing at the input pins. The reference (and sense) pins are protected via more conventional reversebiased diodes which will conduct if these pins are raised above VCC or below VEE. To achieve 90 dB CMRR, the R3/R4 ratio is trimmed to within 0.005 % of the R1/R2 ratio. Since the resistors themselves are on the order of 10 k (see Figure 1 for actual values, which change with the specific part), an increase of as little as 0.6 can reduce the CMRR from over 90 dB to 84 dB. The better the starting CMRR, the more impact (in dB) a given added resistance will have. Therefore, to achieve this high CMRR in practice, take care to ensure that all source impedances remain balanced. To accomplish this, PCB traces carrying signals should be balanced in length, connector resistance should be minimized, and any input capacitance (including strays) should be balanced between the + and - legs of the input circuitry. Note that the additional contact resistance of some sockets is sufficient to undo the effects of precision trimming. Therefore, socketing the parts is not recommended. THAT's 1200-series InGenius(R) input stages address many of these difficulties through a patented method of increasing commonmode input impedance, and should be considered for any critical applications. To reduce risk of damage from ESD, and to prevent RF from reaching the devices, THAT recommends the circuit of Figure 4. C3 through C5 should be located close to the point where the input signal comes into the chassis, preferably directly on the connector. The unusual circuit design is intended to minimize the unbalancing impact of differences in the values of C4 and C5 by forcing the capacitance from each input to chassis ground to depend primarily on the value of C3. The circuit shown is approximately ten times less sensitive to mismatches between C4 and C5 than the more conventional approach in which the junction of C4 and C5 is grounded directly. An excellent discussion of input stage grounding can be found in the June 1995 issue of the Journal of the Audio Engineering Society, Vol. 43, No. 6, in articles by Stephen Macatee, Bill Whitlock, and others. Note that because of the tight matching of the internal resistor ratios, coupled with the uncertainty - VCC C2 + VCC In- 100n VCC C3 In+ Ref R3 47p C4 470p C5 470p 11 2/6 In- 12/10 Sens 13/9 Out Ref VEE 3/5 14/8 In+ 4 VCC U1 THAT 1286/ 1283/ 1280 R4 C1 In+ VEE 100n VEE VEE Figure 3. Representative input protection circuit Figure 4. RFI and supply bypassing THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright (c) 2007, THAT Corporation Out THAT 1280 Series Dual Balanced Line Receiver ICs Page 5 of 10 in absolute value of any individual resistor, RF bypassing through the addition of R-C networks at the inputs (series resistor followed by a capacitor to ground at each input) is not recommended. The added resistors can interact with the internal ones in unexpected ways. If some impedance for the RF-bypass capacitor to work against is deemed necessary, THAT recommends the use of a ferrite bead or balun instead. If it is necessary to ac-couple the inputs of the 1280-series parts, the coupling capacitors should be sized to present negligible impedance at any frequencies of interest for common mode rejection. Regardless of the type of coupling capacitor chosen, variations in the values of the two capacitors, working against the 1280-series input impedance (itself subject to potential imbalances in absolute value, even when trimmed for perfect ratio match), can unbalance common mode input signals. This can convert common-mode to balanced signals which will not be rejected by the CMRR of the devices. For this reason, THAT recommends dc-coupling the inputs of the 1280-series devices. Input Voltage Limitations When configured, respectively, for -3 dB and -6 dB gain, the 1283 and 1286 devices are capable of accepting input signals above the power supply rails. This is because the internal opamp's inputs connect to the outside world only through the on-chip resistors R1 through R4 at nodes a and b as shown in Figure 2. Consider the following analysis. Differential Input Signals For differential signals (vIN(DIFF)), the limitation to signal handling will be output clipping. The outputs of all the devices typically clip at within 2V of the supply rails. Therefore, maximum differential input signal levels are directly related to the gain and supply rails and can be calculated in dBu as follows: V in(diff) = 20 log V CC -V EE -2V 2 2 0.775 - Gain or V in(diff) = 20 log(V CC - V EE - 4V) - Gain - 6.8dB For example, If VCC=15V, VEE=-15V, and Gain = -3 dB, then V in(diff) = 20 log[15V - (-15V) - 4V] - (-3dB) - 6.8dB = 24.5 dBu Common-Mode Input Signals For common-mode input signals, there is essentially no output signal. The limitation on commonmode handling is the point at which the inputs are overloaded. So, we must consider the inputs of the opamp. For common-mode signals (VIN(CM)), the common-mode input current splits to flow through both R1/R2 and through Document 600114 Rev 01 R3/R4. Because vb is constrained to follow Va, we will consider only the voltage at node a. The voltage at a can be calculated as: V a = V IN(CM) R4 R 3 +R 4 Solving for vIN(CM), V IN(CM) = V a R 3 +R 4 R4 For the 1280, (R3 + R4) /R4 = 2. For the 1283, (R3 + R4) /R4 = 2.4. For the 1286, (R3 + R4) /R4 = 3. Furthermore, the same constraints apply to va as in the differential analysis. Following the same reasoning as above, the maximum common-mode input signal for the 1280 is (2VCC - 4) V, and the minimum is (2VEE + 4) V. For the 1283, these figures are (2.4VCC - 4.8) V, and (2.4VEE + 4.8) V. For the 1286, these figures are (3VCC - 6) V, and (3VEE + 6) V. Therefore, for common-mode signals and 15 V rails, the 1280 will accept up to ~26 V in either direction. As an ac signal, this is 52 V peak-peak, 18.4 V rms, or +27.5 dBu. With the same supply rails, the 1283 will accept up to ~31 V in either direction. As an ac signal, this is 62 V peak-peak, 21.9 V rms, or +29 dBu. With the same supply rails, the 1286 will accept up to ~39 V in either direction. As an ac signal, this is 78 V peak-peak, 27.6 V rms, or +31 dBu. Of course, in the real world, differential and common-mode signals combine. The maximum signal that can be accommodated will depend on the superposition of both differential and common-mode limitations. Output Considerations The 1280-series devices are typically capable of supplying 42 mA into a short circuit. While they will survive a short, power dissipation will rise dramatically if the output is shorted. Junction temperature must be kept under 125 C to maintain the devices' specifications. These devices are stable with up to 300 pF of load capacitance over the entire rated temperature range, and even more at room temperature. Power Supply Considerations The 1280-series parts are not particularly sensitive to the power supply, but they do contain wide bandwidth opamps. Accordingly, small local bypass capacitors should be located within a few inches of the supply pins on these parts, as shown in Figure 4. Selecting a Gain Variation The three different parts offer different gain structures to suit different applications. The 1286 is customarily configured for -6 dB gain, but by reversing the resistor connections, it can also be configured for +6 dB. The 1283 is most often configured for -3 dB gain, but can also be configured for +3 dB. The choice of input gain is determined by the input THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright (c) 2007, THAT Corporation Document 600114 Rev 01 Page 6 of 10 voltage range to be accommodated, and the power supply voltages used within the circuit. To minimize noise and maximize signal-to-noise ratio, the input stage should be selected and configured for the highest possible gain that will ensure that maximum-level input signals will not clip the input stage or succeeding stages. For example, with 18 V supply rails, the 1280-series parts have a maximum output signal swing of +23 dBu. In order to accommodate +24 dBu input signals, the maximum gain for the stage is -1 dB. With 15 V supply rails, the maximum output signal swing is ~+21.1 dBu; here, -3 dB is the maximum gain. In THAT 1280 Series Dual Balanced Line Receiver ICs each case, a 1283 configured for -3 dB gain is the ideal choice. The 1280 (0 dB gain only) will not provide enough headroom at its output to support a +24 dBu input signal. The 1286 (configured for -6 dB gain) will increase noise, thus reducing dynamic range, by attenuating the input signal more than necessary to support a +24 dBu input. In fact, for most professional audio applications, THAT recommends the -3 dB input configuration possible only with the 1283 in order to preserve dynamic range within a reasonable range of power supply voltages and external headroom limits. THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright (c) 2007, THAT Corporation THAT 1280 Series Dual Balanced Line Receiver ICs Page 7 of 10 Document 600114 Rev 01 Applications The THAT 1280, 1283, and 1286 are usually thought of as precision differential amplifiers with gains of zero, -3 and -6 dB respectively. These devices are primarily intended as balanced line receivers for audio applications. However, their topology lends itself to other applications as well. Basic Balanced Receiver Applications Figures 5, 6, and 7, respectively, show the 1280, 1286 and 1286 configured as zero, -3 dB, and -6 dB line receivers. Figures 8 and 9, respectively, show the 1283 and 1286 configured as +3 dB and +6 dB line receivers. The higher gains are achieved by swapping the positions of the resistors within each pair in regard to signal input vs. Output. Precision Summing Application Figure 10 shows a 1280 configured as a precision summing amplifier. This circuit uses both the In+ and Ref pins as inputs. Because of the excellent matching between the laser-trimmed resistor pairs, the output voltage is precisely equal to the sum of the two input voltages. 9k 2/6 Figure 11 shows one half of a 1280 configured as an instrumentation amplifier. The two opamps preceding the 1280 buffer the input signal before passing it on to the 1280. The OP270 shown was chosen for its combination of good ac and dc performance. In this configuration, the opamps provide gain equal to 1+(9.98 k / Rg) for differential signals, but unity gain for common-mode signals. The 1280 then rejects the common mode signal while passing on the differential portion. As well, the opamps buffer the input of the 1280, raising the circuit's input impedance to both differential and common-mode signals. This makes the circuit's common-mode rejection less sensitive to variations in the source impedance driving the stage. As noted in the Theory of Operation section, THAT's InGenius(R) input stages use patented circuitry to increase common-mode input impedance. This even further inproves common-mode rejection in real-world applications. See the THAT 1200-series datasheet for more information. U1 1280 11 In- Instrumentation Amplifier Application VCC 9k In- 12/10 12k 2/6 Sense In- U1 1286 11 VCC 6k 13/9 12/10 Sense In- Output 13/9 Vout Vout In+ 9k 3/5 9k In+ In+ 14/8 Ref 12k 3/5 VEE 4 10.5k 2/6 7.5k 12/10 In13/9 Vout 10.5k 3/5 7.5k 11 VCC U1 1283 7.5k 14/8 VEE 12/10 Sense In- Output 13/9 Vout In+ Ref In+ 10.5k 2/6 Sense In- In+ Figure 7. -6 dB line receiver U1 1283 VCC 14/8 Ref VEE Figure 5. Zero dB line receiver In- 6k In+ 4 11 Output 10.5k 3/5 7.5k 14/8 Ref In+ VEE 4 4 Figure 6. -3 dB line receiver Figure 8. +3 dB line receiver THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright (c) 2007, THAT Corporation Out Document 600114 Rev 01 Page 8 of 10 Driving Analog-to-Digital Converters Figure 12 shows a convenient method of driving a typical audio ADC with balanced inputs. This circuit accepts +24 dBu in. By using both halves of a single 1283 IC connected in anti-phase, the maximum signal level between their respective outputs is +27 dBu. An attenuator network brings U1 1286 11 In- VCC 12k 2/6 6k Sense 12k 3/5 6k In ADC applications such as this, noise is usually a significant consideration. The output noise of one channel of a THAT1283 is -105.9 dBu in a 22 kHz bandwidth, or 26.6 nV/Hz. Since both channels are used, and since noise adds in random fashion (square-root of the sum of the squares), the total noise level at the input of the resistive pad (R1 ~ R3) will be -102.9 dBu or 37.5 nV/Hz. The pad reduces this noise level to -121.7 dBu or 4.3 nV/Hz at the input to the ADC, while C1 provides low-pass filtering typically required by ADCs. Output 13/9 Vout In+ this signal down by 18.8 dB while attenuating the noise of the line receivers as well. The thermal noise of the resistive attenuator is 1.87 nV/Hz or the equivalent noise of a 210 resistor. Therefore, the total noise density going into the input of the ADC will be 12/10 In- THAT 1280 Series Dual Balanced Line Receiver ICs e n ADC input = (1.87 14/8 VEE 4 Noise (dBu ) = 20 log U1 1280 VCC 9k 2/6 9k 12/10 Sense In- Output 13/9 Vout Input 1 3/5 9k 9k 14/8 VEE 4 Input 2 Figure 10. Precision two-input summing circuit In- 3 U2A OP-270 1 VCC C1 2 R4 100k 100n R2 11 2 In- 12 Sens 13 Out Ref VEE 3 14 U1 In+ 4 4k99 R1 Rg R3 4k99 In+ VCC Out THAT1280 C2 6 R5 100k 7 5 U2B OP-270 ) 2 = 4.7 nV Hz . 4.7 nV Hz % 22kHz 0.775 = -121 dBu. 100n VEE When it becomes necessary to control gain in a balanced system, designers are often tempted to keep the signal balanced and use two Voltage Controlled Amplifiers (VCAs) to control the gain on each half of the balanced signal. Unfortunately, this can result in common-mode to differential-mode conversion (degrading CMRR) when there are even slight differences in gain between the VCAs. A better approach is to convert the signal to single-ended, alter the gain, and then convert back to balanced. Figure 13 shows a stereo gain control for a balanced system. First, we use a 1283 -3 dB line receiver to perform the balanced to single-ended conversion. A THAT 1606, with +6dB gain, is used to rebalance the signal before the circuit's output. A THAT 2162 dual VCA is used to alter gain based on a dc voltage applied at EC-, the "Control Voltage" node. (This point is intended to be driven from a low-impedance, low-noise voltage source. See the THAT 2162-series data sheet for details.) Ref In+ nV Hz Controlling Gain in Balanced Systems Figure 9. +6 dB line receiver 11 ) 2 + (4.3 The noise floor can then be calculated to be Ref In+ nV Hz As shown, the VCA section is configured for "static" gain of -3 dB (gain with 0 Vdc applied to the EC-) due to the choice of ratio of R3 to R2 and R7 to R6. Additionally, the 1283 has a gain of -3 dB for a total attenuation of 6 dB before the output driver. The 1606 has a gain of 6 dB, therefore the circuit has a gain of 0 dB with 0 V at the control voltage node. This circuit accepts and delivers over +24 dBu before clipping, and has a noise floor of -91.5 dBu (22 kHz bandwidth). By varying the Control Voltage, gains from -70 dB to +40 dB may easily be achieved. The VCA's "deci-linear" relationship between Control Voltage and gain makes the gain setting precise, predictable, and repeatable. Figure 11. Instrumentation amplifier THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright (c) 2007, THAT Corporation THAT 1280 Series Dual Balanced Line Receiver ICs Page 9 of 10 Document 600114 Rev 01 -18.8 dB 2 12 InSense R1 13 Vout 909R Ref 3 In+ U1 14 THAT 1283 C1 +27 dBu 2n2 In Hi +24 dBu In AIN- to ADC R2 237R 2 Vrms Out 6 10 InSense 9 Vout 5 Ref In+ U2 8 THAT 1283 In Lo R3 909R U3A 1 3 AIN+ to ADC 1/2 Vref of ADC 2 4580 Figure 12. Circuit for audio ADCs with balanced inputs -3dB +6dB -3dB C3 U3A 2162(VCA1) VCC 11 12 V+ In- Sense 13 Vout 3 Ref In+ 14 U1A 1283 In 1 Lo 2 In 1 Hi 6 C2 10n R2 12 V+ 7 2 IN OUT 20k0 SYM 14k3 VCC 2 8 1 3 V+ 3 EC- 4 U4A 4580 N/C Control Voltage 1 6.2mV/dB C6 11 10 Sense Vout In 2 Hi 5 Ref In+ V8 4 VEE 9 U1B 1283 C5 10n R6 10 IN 15 OUT GND EC- 13 Control Voltage 2 6.2mV/dB 8 C4 V- 5 VEE 6 5 U4B 4580 7 V- 4 VEE 100n 12 4 Vcc 7 In+ Cap1 14 6 Out+ InOut5 Gnd Cap2 3 Vee 13 11 VEE R1 1M0 Out 1 Hi Out 1 Lo U2 1606 VCC 14k3 14 SYM 20k0 VEE R7 N/C EC+ 100n 12 4 Vcc 7 In+ Cap1 14 6 Out+ InOut5 Gnd Cap2 3 Vee 13 11 22p U3B 2162(VCA2) In 2 Lo 6 In- VCC R3 VCC EC+ C1 22p U5 1606 Figure 13. Voltage-controlled gain control of a balanced signal THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright (c) 2007, THAT Corporation R5 1M0 Out 2 Hi Out 2 Lo Document 600114 Rev 01 Page 10 of 10 THAT 1280 Series Dual Balanced Line Receiver ICs Package Information The THAT1280 series is available in a 14-pin surface mount (SOIC) package. Package dimensions are shown in Figure 14 below; Pinouts are given in Table 1 on page 1. Ordering information is provided in Table 2 below. The 1280 series package is entirely lead-free. The lead-frame is copper, plated with successive layers of nickel, palladium, and gold. This approach makes it possible to solder these devices using leadfree and lead-bearing solders. Neither the lead-frame nor the the plastic mold compound used in the 1280-series contains any hazardous substances as specified in the European Union's Directive on the Restriction of the Use of Certain Hazardous Substances in Electrical and Electronic Equipment 2002/95/EG of January 27, 2003. The surface-mount package is suitable for use in a 100% tin solder process. Package Characteristics Parameter Symbol Conditions Package Style JA Thermal Resistance Min Typ See Fig. 14 for dimensions 14 Pin SO SO package soldered to board 100 Environmental Regulation Compliance Max C/W Complies with January 27, 2003 RoHS requirements Soldering Reflow Profile JEDEC JESD22-A113-D (250 C) Moisture Sensitivity Level MSL Above-referenced JEDEC soldering profile E F B C H 11 1 Gain Order Number 0 dB 1280S14-U -3 dB 1283S14-U -6 dB 1286S14-U Table 2. Ordering information G D A ITEM A B C D E F G H Units MILLIMETERS 8.56/8.79 3.81/3.99 5.80/6.20 0.36/0.46 1.27 1.35/1.73 0.19/0.25 0.41/1.27 INCHES 0.337/0.346 0.150/0.157 0.228/0.244 0.014/0.018 0.050 0.053/0.068 0.0075/0.0098 0.016/0.05 Figure 14. SO package outline drawing THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright (c) 2007, THAT Corporation