THEORY OF OPERATION
Power Supplies
System Power-Up/Power-Down Sequence
Powering Up
Powering Down
TAS5261
SLES188 – AUGUST 2006
PCB placement, and routing. As indicated, each halfbridge has independent power-stage supply pins(PVDD_x). For optimal electrical performance, EMITo facilitate system design, the TAS5261 needs only
compliance, and system reliability, it is important thata 12-V supply in addition to a typical 50-V
each PVDD_x pin is decoupled with two 100-nFpower-stage supply. An internal voltage regulator
ceramic capacitors placed as close as possible toprovides suitable voltage levels for the digital and
each supply pin on the same side of the PCB as thelow-voltage analog circuitry. Additionally, all circuitry
TAS5261 location. It is recommended to follow therequiring a floating voltage supply, e.g., the high-side
PCB layout of the TAS5261 reference design. Forgate drive, is accommodated by built-in bootstrap
additional information on the recommended powercircuitry requiring only a few external capacitors.
supply and required components, see the applicationdiagrams given in this data sheet.To provide outstanding electrical and acousticcharacteristics, the PWM signal path, including gate
The 12-V supply should be powered from adrive and output stage, is designed as identical,
low-noise, low-output-impedance voltage regulator.independent half bridges. For this reason, each half
Likewise, the 50-V power-stage supply is assumed tobridge has separated gate-drive supply (GVDD_x),
have low output impedance and low noise. Thebootstrap pins (BST_x) and power-stage supply pins
internal POR circuit eliminates the need for(PVDD_x). Furthermore, an additional pin (VDD) is
power-supply sequencing. Moreover, the TAS5261 isprovided as power supply for all common circuits.
fully protected against erroneous power-stage turnAlthough supplied from the same 12-V source, it is
on due to parasitic gate charging. Thus,highly recommended to separate GVDD_x and VDD
voltage-supply ramp rates (dv/dt) are noncriticalon the printed circuit board (PCB) by RC filters (see
within the specified range (see the Recommendedapplication diagram for details). These RC filters
Operating Conditions section of this data sheet).provide the recommended high-frequency isolation.Special attention should be paid to placing alldecoupling capacitors as close to their associatedpins as possible. In general, inductance between thepower-supply pins and decoupling capacitors mustbe avoided. (See reference board documentation for There is no power-up sequence is required for theadditional information.) TAS5261. The outputs of the H-bridge remain in ahigh-impedance state until the gate-drive supplyFor a properly functioning bootstrap circuit, a small
voltage (GVDD_x) and VDD voltage are above theceramic capacitor must be connected from each
undervoltage protection (UVP) voltage threshold (seebootstrap pin (BST_x) to the power-stage output pin
the Electrical Characteristics section of this data(OUT_x). When the power-stage output is low, the
sheet). Although not specifically required, it isbootstrap capacitor is charged through an internal
recommended to hold RESET in a low state whilediode connected between the gate-drive
powering up the device. This allows an internalpower-supply pin (GVDD_x) and the bootstrap pin.
circuit to charge the external bootstrap capacitors byWhen the power-stage output voltage is high, the
enabling a weak pulldown of the half-bridge output.bootstrap capacitor voltage is shifted above theoutput voltage potential and, thus, provides a While powering up the TAS5261, RESET should besuitable voltage supply for the high-side gate driver. held low.In an application with PWM switching frequencies inthe range of 352 kHz to 384 kHz, it is recommendedto use 33-nF ceramic capacitors, size 0603 or 0805,
There is no power-down sequence is required for thefor the bootstrap capacitor. These 33-nF capacitors
TAS5261. The device remains fully operational asensure sufficient energy storage, even during
long as the gate-drive supply (GVDD_x) voltage andminimal PWM duty cycles, to keep the high-side
VDD voltage are above the undervoltage protectionpower-stage FET (LDMOS) fully started during all of
(UVP) threshold level (see the Electricalthe remaining part of the PWM cycle. In an
Characteristics section of this data sheet). Althoughapplication running at a reduced switching frequency,
not specifically required, it is a good practice to holdgenerally 250 kHz to 192 kHz, the bootstrap
RESET low during power down, thus, preventingcapacitor might need to be increased in value.
audible artifacts including pops and clicks.Special attention should be paid to the power-stagepower supply – this includes component selection,
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