1. General description
The 74LVC1G17 provides a buffer function with Schmitt trigger action. It is capable of
transforming slowly changing input signals into sharply defined outputs.
The input can be driven from either 3.3 Vor 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features
■Wide supply voltage range from 1.65 V to 5.5 V
■High noise immunity
■Complies with JEDEC standard
◆JESD8-7 (1.65 V to 1.95 V)
◆JESD8-5 (2.3 V to 2.7 V)
◆JESD8B/JESD36 (2.7 V to 3.6 V)
■±24 mA output drive (VCC = 3.0 V)
■CMOS low power consumption
■Latch-up performance exceeds 250 mA
■Direct interface with TTL levels
■Unlimited rise and fall times
■Inputs accept voltages up to 5 V
■Multiple package options
■ESD protection:
◆HBM JESD22-A114E exceeds 2000 V
◆MM JESD22-A115-A exceeds 200 V
■Specified from −40 °C to +125 °C
74LVC1G17
Single Schmitt trigger buffer
Rev. 06 — 27 August 2007 Product data sheet
74LVC1G17_6 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 06 — 27 August 2007 2 of 16
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
3. Ordering information
4. Marking
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC1G17GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package;
5 leads; body width 1.25 mm SOT353-1
74LVC1G17GV −40 °C to +125 °C SC-74A plastic surface-mounted package; 5 leads SOT753
74LVC1G17GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package;
no leads; 6 terminals; body 1 ×1.45 ×0.5 mm SOT886
74LVC1G17GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package;
no leads; 6 terminals; body 1 ×1×0.5 mm SOT891
Table 2. Marking codes
Type number Marking
74LVC1G17GW VJ
74LVC1G17GV V17
74LVC1G17GM VJ
74LVC1G17GF VJ
Fig 1. Logic symbol Fig 2. IEC logic symbol
mnb150
AY
2424
mnb151
Fig 3. Logic diagram
mnb152
AY
74LVC1G17_6 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 06 — 27 August 2007 3 of 16
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level
Fig 4. Pin configuration SOT353-1
and SOT753 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891
74LVC1G17
n.c. VCC
A
GND Y
001aaf190
1
2
3
5
4
74LVC1G17
A
001aaf191
n.c.
GND
n.c.
VCC
Y
Transparent top view
2
3
1
5
4
674LVC1G17
A
001aaf402
n.c.
GND
n.c.
VCC
Y
Transparent top view
2
3
1
5
4
6
Table 3. Pin description
Symbol Pin Description
SOT353-1/SOT753 SOT886/SOT891
n.c. 1 1, 5 not connected
A 2 2 data input
GND 3 3 ground (0 V)
Y 4 4 data output
VCC 5 6 supply voltage
Table 4. Function table[1]
Input Output
A Y
LL
HH
74LVC1G17_6 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 06 — 27 August 2007 4 of 16
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
10. Static characteristics
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +6.5 V
IIK input clamping current VI < 0 V −50 - mA
VIinput voltage [1] −0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - ±50 mA
VOoutput voltage Active mode [1][2] −0.5 VCC + 0.5 V
Power-down mode [1][2] −0.5 +6.5 V
IOoutput current VO = 0 V to VCC -±50 mA
ICC supply current - 100 mA
IGND ground current −100 - mA
Ptot total power dissipation Tamb =−40 °C to +125 °C[3] - 250 mW
Tstg storage temperature −65 +150 °C
Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 5.5 V
VIinput voltage 0 - 5.5 V
VOoutput voltage Active mode 0 - VCC V
VCC = 0 V; Power-down mode 0 - 5.5 V
Tamb ambient temperature −40 - +125 °C
Table 7. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ[1] Max Unit
Tamb = −40 °C to +85 °C
VOH HIGH-level output voltage VI= VCC or GND
IO=−100 µA; VCC = 1.65 V to 5.5 V VCC − 0.1 - - V
IO=−4 mA; VCC = 1.65 V 1.2 - - V
IO=−8 mA; VCC = 2.3 V 1.9 - - V
IO=−12 mA; VCC = 2.7 V 2.2 - - V
IO=−24 mA; VCC = 3.0 V 2.3 - - V
IO=−32 mA; VCC = 4.5 V 3.8 - - V
74LVC1G17_6 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 06 — 27 August 2007 5 of 16
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
[1] All typical values are measured at maximum VCC and Tamb = 25 °C.
VOL LOW-level output voltage VI= VCC or GND
IO= 100 µA; VCC = 1.65 V to 5.5 V - - 0.1 V
IO= 4 mA; VCC = 1.65 V - - 0.45 V
IO= 8 mA; VCC = 2.3 V - - 0.3 V
IO= 12 mA; VCC = 2.7 V - - 0.4 V
IO= 24 mA; VCC = 3.0 V - - 0.55 V
IO= 32 mA; VCC = 4.5 V - - 0.55 V
IIinput leakage current VI= 5.5 Vor GND; VCC = 0 V to 5.5 V - ±0.1 ±5µA
IOFF power-off leakage current VIor VO = 5.5 V; VCC =0 V - ±0.1 ±10 µA
ICC supply current VI= 5.5 Vor GND;
VCC = 1.65 V to 5.5 V; IO=0A - 0.1 10 µA
∆ICC additional supply current VI=V
CC − 0.6 V; IO=0A;
VCC = 2.3 V to 5.5 V; per pin - 5 500 µA
CIinput capacitance - 5 - pF
Tamb = −40 °C to +125 °C
VOH HIGH-level output voltage VI= VCC or GND
IO=−100 µA; VCC = 1.65 V to 5.5 V VCC − 0.1 - - V
IO=−4 mA; VCC = 1.65 V 0.95 - - V
IO=−8 mA; VCC = 2.3 V 1.7 - - V
IO=−12 mA; VCC = 2.7 V 1.9 - - V
IO=−24 mA; VCC = 3.0 V 2.0 - - V
IO=−32 mA; VCC = 4.5 V 3.4 - - V
VOL LOW-level output voltage VI= VCC or GND
IO= 100 µA; VCC = 1.65 V to 5.5 V - - 0.1 V
IO= 4 mA; VCC = 1.65 V - - 0.7 V
IO= 8 mA; VCC = 2.3 V - - 0.45 V
IO= 12 mA; VCC = 2.7 V - - 0.6 V
IO= 24 mA; VCC = 3.0 V - - 0.80 V
IO= 32 mA; VCC = 4.5 V - - 0.80 V
IIinput leakage current VI= 5.5 Vor GND; VCC = 0 V to 5.5 V - - ±100 µA
IOFF power-off leakage current VIor VO = 5.5 V; VCC =0 V - - ±200 µA
ICC supply current VI= 5.5 Vor GND;
VCC = 1.65 V to 5.5 V; IO=0A - - 200 µA
∆ICC additional supply current per pin; VI=V
CC − 0.6 V; IO=0A;
VCC = 2.3 V to 5.5 V - - 5000 µA
Table 7. Static characteristics
…continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ[1] Max Unit
74LVC1G17_6 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 06 — 27 August 2007 6 of 16
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
[1] All typical values are measured at Tamb = 25 °C.
10.1 Transfer characteristic waveforms
Table 8. Transfer characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
VT+ positive-going
threshold voltage see Figure 7 and Figure 8
VCC = 1.8 V 0.82 1.0 1.14 0.79 1.14 V
VCC = 2.3 V 1.03 1.2 1.40 1.00 1.40 V
VCC = 3.0 V 1.29 1.5 1.71 1.26 1.71 V
VCC = 4.5 V 1.84 2.1 2.36 1.81 2.36 V
VCC = 5.5 V 2.19 2.5 2.79 2.16 2.79 V
VT−negative-going
threshold voltage see Figure 7 and Figure 8
VCC = 1.8 V 0.46 0.6 0.75 0.46 0.78 V
VCC = 2.3 V 0.65 0.8 0.96 0.65 0.99 V
VCC = 3.0 V 0.88 1.0 1.24 0.88 1.27 V
VCC = 4.5 V 1.32 1.5 1.84 1.32 1.87 V
VCC = 5.5 V 1.58 1.8 2.24 1.58 2.27 V
VHhysteresis voltage see Figure 7,Figure 8 and
Figure 9
VCC = 1.8 V 0.26 0.4 0.51 0.19 0.51 V
VCC = 2.3 V 0.28 0.4 0.57 0.22 0.57 V
VCC = 3.0 V 0.31 0.5 0.64 0.25 0.64 V
VCC = 4.5 V 0.40 0.6 0.77 0.34 0.77 V
VCC = 5.5 V 0.47 0.6 0.88 0.41 0.88 V
Fig 7. Transfer characteristic Fig 8. Definitions of VT+, VT− and VH
mnb154
VO
VHVI
VT+
VT−
mnb155
VO
VIVH
VT+
VT−
74LVC1G17_6 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 06 — 27 August 2007 7 of 16
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
11. Dynamic characteristics
[1] Typical values are measured at Tamb =25°C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi×N+∑(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL×VCC2×fo) = sum of outputs.
VCC = 3.0 V
Fig 9. Typical transfer characteristics
03
VI (V)
ICC
(mA)
10
0
2
mna641
4
6
8
12
Table 9. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 11.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
tpd propagation delay A to Y; see Figure 10 [2]
VCC = 1.65 V to 1.95 V 1.0 4.1 11.0 1.0 14.0 ns
VCC = 2.3 V to 2.7 V 0.7 2.8 6.5 0.7 8.5 ns
VCC = 2.7 V 0.7 3.2 6.5 0.7 8.5 ns
VCC = 3.0 V to 3.6 V 0.7 3.0 5.5 0.7 7.0 ns
VCC = 4.5 V to 5.5 V 0.7 2.2 5.0 0.7 6.5 ns
CPD power dissipation
capacitance VI = GND to VCC;
VCC = 3.3 V [3] - 16.6 - - - pF
74LVC1G17_6 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 06 — 27 August 2007 8 of 16
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
12. Waveforms
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. The input A to output Y propagation delay times
mnb153
tPHL tPLH
VM
VM
A input
Y output
GND
VI
VOH
VOL
Table 10. Measurement points
Supply voltage Input Output
VCC VMVM
1.65 V to 1.95 V 0.5 ×VCC 0.5 ×VCC
2.3 V to 2.7 V 0.5 ×VCC 0.5 ×VCC
2.7 V 1.5 V 1.5 V
3.0 V to 3.6 V 1.5 V 1.5 V
4.5 V to 5.5 V 0.5 ×VCC 0.5 ×VCC
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 11. Load circuitry for switching times
VEXT
VCC
VIVO
mna616
DUT
CL
RT
RL
RL
G
74LVC1G17_6 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 06 — 27 August 2007 9 of 16
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
13. Application information
Table 11. Test data
Supply voltage Input Load VEXT
VCC VItr=t
fCLRLtPLH, tPHL
1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩopen
2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ωopen
2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ωopen
3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ωopen
4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ωopen
Linear change of VI between 0.8 V to 2.0 V.
(1) Positive-going edge.
(2) Negative-going edge.
Fig 12. Average supply current as a function of supply voltage
234 6
50
0
40
5
30
20
10
mnb156
ICC
(mA)
VCC (V)
(1)
(2)
74LVC1G17_6 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 06 — 27 August 2007 10 of 16
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
14. Package outline
Fig 13. Package outline SOT353-1 (TSSOP5)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(1) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.1
01.0
0.8 0.30
0.15 0.25
0.08 2.25
1.85 1.35
1.15 0.65
e1
1.3 2.25
2.0 0.60
0.15 7°
0°
0.1 0.10.30.425
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
0.46
0.21
SOT353-1 MO-203 SC-88A 00-09-01
03-02-19
wM
bp
D
Z
e
e1
0.15
13
54
θ
A
A2
A1
Lp
(A3)
detail X
L
HE
E
c
vMA
X
A
y
1.5 3 mm0
scale
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1
1.1
74LVC1G17_6 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 06 — 27 August 2007 11 of 16
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
Fig 14. Package outline SOT753 (SC-74A)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT753 SC-74A
wBM
bp
D
e
A
A1
Lp
Q
detail X
HE
E
vMA
AB
y
0 1 2 mm
scale
c
X
132
45
Plastic surface-mounted package; 5 leads SOT753
UNIT A1bpcDEHELpQywv
mm 0.100
0.013 0.40
0.25 3.1
2.7
0.26
0.10 1.7
1.3
e
0.95 3.0
2.5 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.6
0.2 0.33
0.23
A
1.1
0.9
02-04-16
06-03-16
74LVC1G17_6 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 06 — 27 August 2007 12 of 16
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
Fig 15. Package outline SOT886 (XSON6)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT886 MO-252
SOT886
04-07-15
04-07-22
DIMENSIONS (mm are the original dimensions)
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
UNIT
mm 0.25
0.17 1.5
1.4 0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.50.6
A(1)
max
0.5 0.04
1
6
2
5
3
4
6×
(2)
4×
(2)
A
74LVC1G17_6 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 06 — 27 August 2007 13 of 16
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
Fig 16. Package outline SOT891 (XSON6)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT891
SOT891
05-04-06
07-05-15
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm 0.20
0.12 1.05
0.95 0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.350.55
A
max
0.5 0.04
1
6
2
5
3
4
A
6×
(1)
4×
(1)
Note
1. Can be visible in some manufacturing processes.
74LVC1G17_6 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 06 — 27 August 2007 14 of 16
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
15. Abbreviations
16. Revision history
Table 12. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC1G17_6 20070827 Product data sheet - 74LVC1G17_5
Modifications: •In Section 10 “Static characteristics”, changed conditions for
input leakage and supply current.
•Figure 16 “Package outline SOT891 (XSON6)” updated.
74LVC1G17_5 20061006 Product data sheet - 74LVC1G17_4
74LVC1G17_4 20041130 Product specification - 74LVC1G17_3
74LVC1G17_3 20041018 Product specification - 74LVC1G17_2
74LVC1G17_2 20040407 Product specification - 74LVC1G17_1
74LVC1G17_1 20040324 Product specification - -
74LVC1G17_6 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 06 — 27 August 2007 15 of 16
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
17. Legal information
17.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
© NXP B.V. 2007. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 August 2007
Document identifier: 74LVC1G17_6
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
19. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
10.1 Transfer characteristic waveforms. . . . . . . . . . . 6
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
13 Application information. . . . . . . . . . . . . . . . . . . 9
14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
18 Contact information. . . . . . . . . . . . . . . . . . . . . 15
19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
