83054 4:1, Single-Ended Multiplexer Data Sheet GENERAL DESCRIPTION FEATURES The 83054 is a low skew, 4:1, Single-ended Multiplexer and a member of the family of High Performance Clock Solutions from IDT. The 83054 has four selectable single-ended clock inputs and one single-ended clock output. The output has a VDDO pin which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage translation applications. An output enable pin places the output in a high impedance state which may be useful for testing or debug purposes. The device operates up to 250MHz and is packaged in a 16 TSSOP package. * 4:1 single-ended multiplexer * Q nominal output impedance: 7 (VDDO = 3.3V) * Maximum output frequency: 250MHz * Propagation delay: 3ns (maximum), VDD = VDDO = 3.3V * Input skew: 225ps (maximum), VDD = VDDO = 3.3V * Part-to-part skew: 780ps (maximum), VDD = VDDO = 3.3V * Additive phase jitter, RMS: 0.19ps (typical), 3.3V/3.3V * Operating supply modes: VDD/VDDO 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V * -40C to 85C ambient operating temperature * Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT CLK0 CLK1 Q CLK2 CLK3 83054 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View SEL1 SEL0 OE (c)2015 Integrated Device Technology, Inc 1 December 15, 2015 83054 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name 1 Q Type Output Input Description Single-ended clock output. LVCMOS/LVTTL interface levels. Pullup Output enable. When LOW, outputs are in HIGH impedance state. When HIGH, outputs are active. LVCMOS / LVTTL interface levels. 3 OE 4, 8, 10, 14 5 CLK3, CLK2, CLK1, CLK0 GND Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. Power 7, 9 SEL1, SEL0 Input Power supply ground. Clock select input. See Control Input Function Table. Pulldown LVCMOS / LVTTL interface levels. 2, 6, 11, 13, 15 nc Unused 12 VDD Power Power and input supply pin. 16 VDDO Power Output supply pin. No connect. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k V = 3.465V 18 pF V = 2.625V 20 pF DDO Power Dissipation Capacitance (per output) CPD DDO V = 1.89V 30 pF V = 3.465V 7 V = 2.625V 7 V = 1.89V 10 DDO DDO Output Impedance ROUT DDO DDO TABLE 3. CONTROL INPUT FUNCTION TABLE Control Inputs SEL1 SEL0 0 0 Input Selected to Q CLK0 0 1 CLK1 1 0 CLK2 1 1 CLK3 (c)2015 Integrated Device Technology, Inc 2 December 15, 2015 83054 Data Sheet ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 89C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40C TO 85C Symbol Parameter Minimum Typical Maximum Units VDD Power Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 40 mA IDDO Output Supply Current 5 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 40 mA IDDO Output Supply Current 5 mA TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C Symbol Parameter VDD VDDO IDD IDDO Test Conditions Minimum Typical Maximum Units Power Supply Voltage 3.135 3.3 3.465 V Output Supply Voltage 1.71 1.8 1.89 V Power Supply Current 40 mA Output Supply Current 5 mA TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = -40C TO 85C Symbol Parameter VDD VDDO IDD IDDO Test Conditions Minimum Typical Maximum Units Power Supply Voltage 2.375 2.5 2.625 V Output Supply Voltage 2.375 2.5 2.625 V Power Supply Current 35 mA Output Supply Current 5 mA TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Power Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 1.71 1.8 1.89 V IDD Power Supply Current 35 mA IDDO Output Supply Current 5 mA (c)2015 Integrated Device Technology, Inc 3 December 15, 2015 83054 Data Sheet TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40C TO 85C Symbol Parameter VIH Input High Voltage VIL IIH IIL Input Low Voltage Input High Current Input Low Current VOL Minimum VDD = 3.3V 5% Typical Maximum Units 2 VDD + 0.3 V VDD = 2.5V 5% 1.7 VDD + 0.3 V VDD = 3.3V 5% -0.3 0.8 V VDD = 2.5V 5% -0.3 0.7 V CLK0:CLK3, SEL0, SEL1 VDD = 3.3V or 2.5V 5% 150 A OE VDD = 3.3V or 2.5V 5% 5 A CLK0:CLK3, SEL0, SEL1 VDD = 3.3V or 2.5V 5% -5 A OE VOH Test Conditions Output HighVoltage Output Low Voltage VDD = 3.3V or 2.5V 5% -150 A VDDO = 3.3V 5%; NOTE 1 2.6 V VDDO = 2.5V 5%; NOTE 1 1.8 V VDDO = 1.8V 5%; NOTE 1 VDD - 0.3 V VDDO = 3.3V 5%; NOTE 1 0.5 V VDDO = 2.5V 5%; NOTE 1 0.45 V VDDO = 1.8V 5%; NOTE 1 0.35 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams. TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5%, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low to High; NOTE 1 2.4 2.7 3.0 ns tpHL Propagation Delay, High to Low; NOTE 1 2.5 2.7 2.9 ns 55 225 ps tsk(i) Input Skew; NOTE 2 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 tsk(pp) Part-to-Part Skew; NOTE 2, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle MUXISOL MUX Isolation 155.52MHz, (12kHz to 20MHz) 20% to 80% @ 100MHz 0.19 ps 780 ps 50 500 ps 45 55 % 45 dB NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. (c)2015 Integrated Device Technology, Inc 4 December 15, 2015 83054 Data Sheet TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = -40C TO 85C Symbol Parameter fMAX Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 2.5 tpHL Propagation Delay, High to Low; NOTE 1 2.6 tsk(i) Input Skew; NOTE 2 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 tsk(pp) Part-to-Part Skew; NOTE 2, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle MUXISOL MUX Isolation Test Conditions Minimum 155.52MHz, (12kHz to 20MHz) 20% to 80% Typical Maximum Units 250 MHz 2.8 3.1 ns 2.8 3.0 ns 45 150 ps 0.14 ps 780 ps 50 500 ps 45 55 % @ 100MHz 45 dB NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 5%, TA = -40C TO 85C Symbol Parameter fMAX Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 2.7 tpHL Propagation Delay, High to Low; NOTE 1 2.8 tsk(i) Input Skew; NOTE 2 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 tsk(pp) Part-to-Part Skew; NOTE 2, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle MUXISOL MUX Isolation Test Conditions Minimum 155.52MHz, (12kHz to 20MHz) 20% to 80% @ 100MHz Typical Maximum Units 250 MHz 3.2 3.8 ns 3.3 3.8 ns 50 150 ps 0.16 ps 780 ps 100 700 ps 45 55 % 45 dB NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. (c)2015 Integrated Device Technology, Inc 5 December 15, 2015 83054 Data Sheet TABLE 5D. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5%, TA = -40C TO 85C Symbol Parameter fMAX Output Frequency Test Conditions Minimum tpLH Propagation Delay, Low to High; NOTE 1 2.5 3.0 tpHL Propagation Delay, High to Low; NOTE 1 2.5 2.9 3.4 ns tsk(i) Input Skew; NOTE 2 60 175 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 tsk(pp) Part-to-Part Skew; NOTE 2, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle MUXISOL MUX Isolation 155.52MHz, (12kHz to 20MHz) 20% to 80% Typical Maximum Units 250 MHz 3.5 ns 0.21 100 40 @ 100MHz ps 780 ps 500 ps 60 45 % dB NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. TABLE 5E. AC CHARACTERISTICS, VDD = 2.5V 5%, VDDO = 1.8V -5%, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low to High; NOTE 1 2.6 3.3 4.0 ns tpHL Propagation Delay, High to Low; NOTE 1 2.7 3.3 4.0 ns 50 150 ps tsk(i) Input Skew; NOTE 2 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 tsk(pp) Part-to-Part Skew; NOTE 2, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle MUXISOL MUX Isolation 155.52MHz, (12kHz to 20MHz) 20% to 80% @ 100MHz 0.17 ps 780 ps 100 700 ps 40 60 % 45 dB NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. (c)2015 Integrated Device Technology, Inc 6 December 15, 2015 83054 Data Sheet ADDITIVE PHASE JITTER fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the Additive Phase Jitter @ 155.52MHz SSB PHASE NOISE dBc/HZ (12kHz to 20MHz) = 0.19ps typical OFFSET FROM CARRIER FREQUENCY (HZ) This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. (c)2015 Integrated Device Technology, Inc 7 December 15, 2015 83054 Data Sheet PARAMETER MEASUREMENT INFORMATION 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW (c)2015 Integrated Device Technology, Inc 8 December 15, 2015 83054 Data Sheet 80% 80% 20% 20% Q tR PROPAGATION DELAY OUTPUT RISE/FALL TIME INPUT SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD (c)2015 Integrated Device Technology, Inc 9 tF December 15, 2015 83054 Data Sheet APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS: CLK INPUTS For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. (c)2015 Integrated Device Technology, Inc 10 December 15, 2015 83054 Data Sheet RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 137.1C/W 89.0C/W 118.2C/W 81.8C/W 106.8C/W 78.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for 83054 is: 874 PACKAGE OUTLINE AND PACKAGE DIMENSIONS PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N Maximum 16 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 (c)2015 Integrated Device Technology, Inc 11 December 15, 2015 83054 Data Sheet TABLE 8. ORDERING INFORMATION Part/Order Number 83054AGILF 83054AGILFT Marking 83054AIL 83054AIL (c)2015 Integrated Device Technology, Inc Package 16 Lead "Lead-Free" TSSOP 16 Lead "Lead-Free" TSSOP 12 Shipping Packaging tube tape & reel Temperature -40C to 85C -40C to 85C December 15, 2015 83054 Data Sheet REVISION HISTORY SHEET Rev Table Page A T8 12 B T5A - T5E 1 4-6 7 Features Section - added Additive Phase Jitter bullet. AC Characteristics Tables - added tjit row and spec. Added Additive Phase Jitter section. 01/04/07 C T5A - T5E 4-6 AC Characteristics Tables - changed part-to-part skew specs. 03/07/08 T8 12 T8 1 12 C C Description of Change Ordering Information Table - corrected Part/Order Numbers. Ordering Information - removed leaded devices. Updated data sheet format. General Description - Removed HiPerClockS. Ordering Information - removed LF note below the table. Updated header and footer. (c)2015 Integrated Device Technology, Inc 13 Date 1/3/06 3/20/15 12/15/15 December 15, 2015 83054 Data Sheet Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. 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