83054AGILFT - INTEGRATED DEVICE TECHNOLOGY

4:1, Single-Ended Multiplexer 83054

Data Sheet

GENERAL DESCRIPTION

The 83054 is a low skew, 4:1, Single-ended Multiplexer and a

member of the family of High Performance Clock Solutions from IDT.

The 83054 has four selectable single-ended clock inputs and one

single-ended clock output. The output has a VDDO pin which may be

set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage

translation applications. An output enable pin places the output in

a high impedance state which may be useful for testing or

debug purposes. The device operates up to 250MHz and is pack-

aged in a 16 TSSOP package.

BLOCK DIAGRAM PIN ASSIGNMENT

FEATURES

• 4:1 single-ended multiplexer

• Q nominal output impedance: 7Ω (VDDO = 3.3V)

• Maximum output frequency: 250MHz

• Propagation delay: 3ns (maximum), VDD = VDDO = 3.3V

• Input skew: 225ps (maximum), VDD = VDDO = 3.3V

• Part-to-part skew: 780ps (maximum), VDD = VDDO = 3.3V

• Additive phase jitter, RMS: 0.19ps (typical), 3.3V/3.3V

• Operating supply modes:

VDD/VDDO

3.3V/3.3V

3.3V/2.5V

3.3V/1.8V

2.5V/2.5V

2.5V/1.8V

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package

CLK0

CLK1

CLK2

CLK3

SEL1

SEL0

83054

16-Lead TSSOP

4.4mm x 5.0mm x 0.92mm package body

G Package

Top View

83054 Data Sheet

TABLE 1. PIN DESCRIPTIONS

TABLE 2. PIN CHARACTERISTICS

TABLE 3. CONTROL INPUT FUNCTION TABLE

Number Name Type Description

1 Q Output Single-ended clock output. LVCMOS/LVTTL interface levels.

3 OE Input Pullup Output enable. When LOW, outputs are in HIGH impedance state.

When HIGH, outputs are active. LVCMOS / LVTTL interface levels.

4, 8,

10, 14

CLK3, CLK2,

CLK1, CLK0 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.

5 GND Power Power supply ground.

7, 9 SEL1, SEL0 Input Pulldown Clock select input. See Control Input Function Table.

LVCMOS / LVTTL interface levels.

2, 6, 11, 13, 15 nc Unused No connect.

12 VDD Power Power and input supply pin.

16 VDDO Power Output supply pin.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance 4 pF

RPULLUP Input Pullup Resistor 51 kΩ

RPULLDOWN Input Pulldown Resistor 51 kΩ

CPD

Power Dissipation Capacitance

(per output)

VDDO = 3.465V 18 pF

VDDO = 2.625V 20 pF

VDDO = 1.89V 30 pF

ROUT Output Impedance

VDDO = 3.465V 7 Ω

VDDO = 2.625V 7 Ω

VDDO = 1.89V 10 Ω

Control Inputs Input Selected to Q

SEL1 SEL0

0 0 CLK0

0 1 CLK1

1 0 CLK2

1 1 CLK3

83054 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

DD 4.6V

Inputs, VI -0.5V to VDD + 0.5 V

Outputs, VO -0.5V to VDDO + 0.5V

Package Thermal Impedance, θ

JA 89°C/W (0 lfpm)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress speciﬁ cations only. Functional

operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is

not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C

TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C

TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C

TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C

TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Power Supply Voltage 3.135 3.3 3.465 V

VDDO Output Supply Voltage 3.135 3.3 3.465 V

IDD Power Supply Current 40 mA

IDDO Output Supply Current 5mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Power Supply Voltage 3.135 3.3 3.465 V

VDDO Output Supply Voltage 2.375 2.5 2.625 V

IDD Power Supply Current 40 mA

IDDO Output Supply Current 5mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Power Supply Voltage 3.135 3.3 3.465 V

VDDO Output Supply Voltage 1.71 1.8 1.89 V

IDD Power Supply Current 40 mA

IDDO Output Supply Current 5mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Power Supply Voltage 2.375 2.5 2.625 V

VDDO Output Supply Voltage 2.375 2.5 2.625 V

IDD Power Supply Current 35 mA

IDDO Output Supply Current 5mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Power Supply Voltage 2.375 2.5 2.625 V

VDDO Output Supply Voltage 1.71 1.8 1.89 V

IDD Power Supply Current 35 mA

IDDO Output Supply Current 5mA

83054 Data Sheet

TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = -40°C TO 85°C

TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input High Voltage VDD = 3.3V ± 5% 2 VDD + 0.3 V

VDD = 2.5V ± 5% 1.7 VDD + 0.3 V

VIL Input Low Voltage VDD = 3.3V ± 5% -0.3 0.8 V

VDD = 2.5V ± 5% -0.3 0.7 V

IIH Input High Current

CLK0:CLK3,

SEL0, SEL1 VDD = 3.3V or 2.5V ± 5% 150 µA

OE VDD = 3.3V or 2.5V ± 5% 5 µA

IIL Input Low Current

CLK0:CLK3,

SEL0, SEL1 VDD = 3.3V or 2.5V ± 5% -5 µA

OE VDD = 3.3V or 2.5V ± 5% -150 µA

VOH Output HighVoltage

VDDO = 3.3V ± 5%; NOTE 1 2.6 V

VDDO = 2.5V ± 5%; NOTE 1 1.8 V

VDDO = 1.8V ± 5%; NOTE 1 VDD - 0.3 V

VOL Output Low Voltage

VDDO = 3.3V ± 5%; NOTE 1 0.5 V

VDDO = 2.5V ± 5%; NOTE 1 0.45 V

VDDO = 1.8V ± 5%; NOTE 1 0.35 V

NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, “Load Test Circuit” diagrams.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency 250 MHz

tpLH Propagation Delay, Low to High; NOTE 1 2.4 2.7 3.0 ns

tpHL Propagation Delay, High to Low; NOTE 1 2.5 2.7 2.9 ns

tsk(i) Input Skew; NOTE 2 55 225 ps

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section;

NOTE 3

155.52MHz,

(12kHz to 20MHz) 0.19 ps

tsk(pp) Part-to-Part Skew; NOTE 2, 4 780 ps

tR / tFOutput Rise/Fall Time 20% to 80% 50 500 ps

odc Output Duty Cycle 45 55 %

MUXISOL MUX Isolation @ 100MHz 45 dB

NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.

NOTE 2: This parameter is deﬁ ned in accordance with JEDEC Standard 65.

NOTE 3: Driving only one input clock.

NOTE 4: Deﬁ ned as skew between outputs on different devices operating a the same supply voltages and

with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.

83054 Data Sheet

TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C

TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± 5%, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency 250 MHz

tpLH Propagation Delay, Low to High; NOTE 1 2.5 2.8 3.1 ns

tpHL Propagation Delay, High to Low; NOTE 1 2.6 2.8 3.0 ns

tsk(i) Input Skew; NOTE 2 45 150 ps

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section;

NOTE 3

155.52MHz,

(12kHz to 20MHz) 0.14 ps

tsk(pp) Part-to-Part Skew; NOTE 2, 4 780 ps

tR / tFOutput Rise/Fall Time 20% to 80% 50 500 ps

odc Output Duty Cycle 45 55 %

MUXISOL MUX Isolation @ 100MHz 45 dB

NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.

NOTE 2: This parameter is deﬁ ned in accordance with JEDEC Standard 65.

NOTE 3: Driving only one input clock.

NOTE 4: Deﬁ ned as skew between outputs on different devices operating a the same supply voltages and

with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency 250 MHz

tpLH Propagation Delay, Low to High; NOTE 1 2.7 3.2 3.8 ns

tpHL Propagation Delay, High to Low; NOTE 1 2.8 3.3 3.8 ns

tsk(i) Input Skew; NOTE 2 50 150 ps

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section;

NOTE 3

155.52MHz,

(12kHz to 20MHz) 0.16 ps

tsk(pp) Part-to-Part Skew; NOTE 2, 4 780 ps

tR / tFOutput Rise/Fall Time 20% to 80% 100 700 ps

odc Output Duty Cycle 45 55 %

MUXISOL MUX Isolation @ 100MHz 45 dB

NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.

NOTE 2: This parameter is deﬁ ned in accordance with JEDEC Standard 65.

NOTE 3: Driving only one input clock.

NOTE 4: Deﬁ ned as skew between outputs on different devices operating a the same supply voltages and

with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.

83054 Data Sheet

TABLE 5D. AC CHARACTERISTICS, VDD = VDDO = 2.5V ± 5%, TA = -40°C TO 85°C

TABLE 5E. AC CHARACTERISTICS, VDD = 2.5V ± 5%, VDDO = 1.8V ± -5%, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency 250 MHz

tpLH Propagation Delay, Low to High; NOTE 1 2.5 3.0 3.5 ns

tpHL Propagation Delay, High to Low; NOTE 1 2.5 2.9 3.4 ns

tsk(i) Input Skew; NOTE 2 60 175 ps

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section;

NOTE 3

155.52MHz,

(12kHz to 20MHz) 0.21 ps

tsk(pp) Part-to-Part Skew; NOTE 2, 4 780 ps

tR / tFOutput Rise/Fall Time 20% to 80% 100 500 ps

odc Output Duty Cycle 40 60 %

MUXISOL MUX Isolation @ 100MHz 45 dB

NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.

NOTE 2: This parameter is deﬁ ned in accordance with JEDEC Standard 65.

NOTE 3: Driving only one input clock.

NOTE 4: Deﬁ ned as skew between outputs on different devices operating a the same supply voltages and

with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency 250 MHz

tpLH Propagation Delay, Low to High; NOTE 1 2.6 3.3 4.0 ns

tpHL Propagation Delay, High to Low; NOTE 1 2.7 3.3 4.0 ns

tsk(i) Input Skew; NOTE 2 50 150 ps

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section;

NOTE 3

155.52MHz,

(12kHz to 20MHz) 0.17 ps

tsk(pp) Part-to-Part Skew; NOTE 2, 4 780 ps

tR / tFOutput Rise/Fall Time 20% to 80% 100 700 ps

odc Output Duty Cycle 40 60 %

MUXISOL MUX Isolation @ 100MHz 45 dB

NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.

NOTE 2: This parameter is deﬁ ned in accordance with JEDEC Standard 65.

NOTE 3: Driving only one input clock.

NOTE 4: Deﬁ ned as skew between outputs on different devices operating a the same supply voltages and

with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.

83054 Data Sheet

ADDITIVE PHASE JITTER

Additive Phase Jitter @ 155.52MHz

(12kHz to 20MHz) = 0.19ps typical

The spectral purity in a band at a speciﬁ c offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the speciﬁ ed plot in many applications. Phase

noise is deﬁ ned as the ratio of the noise power present in a 1Hz

band at a speciﬁ ed offset from the fundamental frequency to the

power value of the fundamental. This ratio is expressed in decibels

(dBm) or a ratio of the power in the 1Hz band to the power in the

As with most timing speciﬁ cations, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

ﬂ oor of the equipment is higher than the noise ﬂ oor of the device.

fundamental. When the required offset is speciﬁ ed, the phase noise

is called a dBc value, which simply means dBm at a speciﬁ ed offset

from the fundamental. By investigating jitter in the frequency domain,

we get a better understanding of its effects on the desired application

over the entire time record of the signal. It is mathematically possible

to calculate an expected bit error rate given a phase noise plot.

This is illustrated above. The device meets the noise ﬂ oor of what

is shown, but can actually be lower. The phase noise is dependent

on the input source and measurement equipment.

OFFSET FROM CARRIER FREQUENCY (HZ)

SSB PHASE NOISE dBc/HZ

83054 Data Sheet

PARAMETER MEASUREMENT INFORMATION

3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT

2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT

3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT

2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW

83054 Data Sheet

20%

80% 80%

20%

tRtF

INPUT SKEW

OUTPUT RISE/FALL TIMEPROPAGATION DELAY

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

83054 Data Sheet

APPLICATION INFORMATION

INPUTS:

CLK INPUTS

For applications not requiring the use of a clock input, it can be left

ﬂ oating. Though not required, but for additional protection, a 1kΩ

resistor can be tied from the CLK input to ground.

LVCMOS CONTROL PINS

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional protection.

A 1kΩ resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT PINS

83054 Data Sheet

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for 83054 is: 874

TABLE 6. θ

JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 118.2°C/W 106.8°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 89.0°C/W 81.8°C/W 78.1°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP

TABLE 7. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MO-153

SYMBOL Millimeters

Minimum Maximum

N16

A -- 1.20

A1 0.05 0.15

A2 0.80 1.05

b 0.19 0.30

c 0.09 0.20

D 4.90 5.10

E 6.40 BASIC

E1 4.30 4.50

e 0.65 BASIC

L 0.45 0.75

α0° 8°

aaa -- 0.10

PACKAGE OUTLINE AND PACKAGE DIMENSIONS

83054 Data Sheet

TABLE 8. ORDERING INFORMATION

Part/Order Number Marking Package Shipping Packaging Temperature

83054AGILF 83054AIL 16 Lead “Lead-Free” TSSOP tube -40°C to 85°C

83054AGILFT 83054AIL 16 Lead “Lead-Free” TSSOP tape & reel -40°C to 85°C

83054 Data Sheet

REVISION HISTORY SHEET

Rev Table Page Description of Change Date

A T8 12 Ordering Information Table - corrected Part/Order Numbers. 1/3/06

B T5A - T5E

4 - 6

Features Section - added Additive Phase Jitter bullet.

AC Characteristics Tables - added tjit row and spec.

Added Additive Phase Jitter section.

01/04/07

C T5A - T5E 4 - 6 AC Characteristics Tables - changed part-to-part skew specs. 03/07/08

CT8 12 Ordering Information - removed leaded devices.

Updated data sheet format. 3/20/15

CT8

General Description - Removed HiPerClockS.

Ordering Information - removed LF note below the table.

Updated header and footer.

12/15/15

83054 Data Sheet

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operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided

without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe-

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their respective third party owners.

For datasheet type deﬁ nitions and a glossary of common terms, visit www.idt.com/go/glossary.

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