MCM6341
1
MOTOROLA FAST SRAM
Advance Information
128K x 24 Bit Static Random
Access Memory
The MCM6341 is a 3,145,728–bit static random access memory organized as
131,072 words of 24 bits. Static design eliminates the need for external clocks
or timing strobes.
The MCM6341 is equipped with chip enable (E1, E2, E3) and output enable
(G) pins, allowing for greater system flexibility and eliminating bus contention
problems.
The MCM6341 is available in a 119–bump PBGA package.
•Single 3.3 V ± 10% Power Supply
•Fast Access Time: 10/11/12/15 ns
•Equal Address and Chip Enable Access Time
•All Inputs and Outputs are TTL Compatible
•Three–State Outputs
•Power Operation: 280/275/270/260 mA Maximum, Active AC
•Commercial Temperature (0°C to 70°C) and
Industrial Temperature (– 40°C to + 85°C) Options
DQ
BLOCK DIAGRAM
G
AAAAAAAA
MEMORY MATRIX
ROW
DECODER
INPUT
DATA
CONTROL
A
A
A
A
A
A
A
DQ
E1
W
A
A
COLUMN I/O
COLUMN DECODER
DQ
DQ
E2
E3
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Order this document
by MCM6341/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MCM6341
A Address Inputs. . . . . . . . . . . . . . . . . . . . . .
WWrite Enable. . . . . . . . . . . . . . . . . . . . . . .
GOutput Enable. . . . . . . . . . . . . . . . . . . . .
E1, E2, E3 Chip Enable. . . . . . . . . . . . . . . .
DQ Data Input/Output. . . . . . . . . . . . . . . . .
NC No Connection. . . . . . . . . . . . . . . . . . . .
VDD + 3.3 V Power Supply. . . . . . . . . . . . .
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . .
PIN NAMES
ZP PACKAGE
PBGA
CASE 999–02
REV 2
2/18/98
Motorola, Inc. 1998
MCM6341
2MOTOROLA FAST SRAM
PIN ASSIGNMENT
119–BUMP PBGA
TOP VIEW
6543217
B
C
V
SS
G
A
D
E
F
H
J
VDD
VSS
VDD
VSS
A
VSS
VSS
AA AA
NC
AA AA
NC
DQ
DQ
NC NC
A
NC
VDD
DQ
NCNC
A
W
AA
NC
G
DQ VSS
NC
VDD
DQ
DQ VSS
DQ
VDD
DQ
DQ VSS VSS
DQ
VDD
VDD
VSS
VDD
VSS
DQ
DQ VDD VSS
VSS
VSS
VDD
VSS
DQ
DQ VDD VSS VSS VDD
DQ
NC A A E1
K
L
M
N
P
R
T
U
NC NC
A
NC NC
DQ
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VDD
E2 NC E3 NC
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
MCM6341
3
MOTOROLA FAST SRAM
TRUTH TABLE (X = Don’t Care)
E1 E2 E3 G W Mode I/O Pin Cycle Current
H X X X X Not Selected High–Z — ISB1, ISB2
X L X X X Not Selected High–Z — ISB1, ISB2
X X H X X Not Selected High–Z — ISB1, ISB2
L H L H H Output Disabled High–Z — IDDA
L H L L H Read Dout Read IDDA
L H L X L Write High–Z Write IDDA
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Symbol Value Unit
Power Supply Voltage Relative to VSS VDD – 0.5 to + 5.0 V
Voltage Relative to VSS for Any Pin
Except VDD Vin, Vout – 0.5 to VDD + 0.5 V
Output Current (per I/O) Iout ±20 mA
Power Dissipation PD1.0 W
Temperature Under Bias Commercial
Industrial Tbias – 10 to + 85
– 45 to + 90 °C
Storage Temperature — Plastic Tstg – 55 to + 150 °C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could af fect device reliability.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid ap-
plication of any voltage higher than maximum
rated voltages to these high–impedance circuits.
This CMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board and
transverse air flow of at least 500 linear feet per
minute is maintained.
MCM6341
4MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ±10%, TA = 0 to + 70°C, Unless Otherwise Noted)
(TA = – 40 to + 85°C for Industrial Temperature Offering)
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
Supply V oltage (Operating Voltage Range) VDD 3.0 3.3 3.6 V
Input High Voltage VIH 2.2 — VDD + 0.3** V
Input Low Voltage VIL – 0.5*— 0.8 V
*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns).
**VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width ≤ 2.0 ns).
DC CHARACTERISTICS (See Note)
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VDD) Ilkg(I) —±1.0 µA
Output Leakage Current (E = VIH, Vout = 0 to VDD) Ilkg(O) —±1.0 µA
Output Low Voltage (IOL = + 8.0 mA) VOL —0.4 V
Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V
NOTE: E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
POWER SUPPLY CURRENTS (See Note)
Parameter Symbol 0 to 70°C– 40 to
+ 85°CUnit
AC Active Supply Current MCM6341–10
(Iout = 0 mA, VDD = max) MCM6341–11
MCM6341–12
MCM6341–15
IDD 280
275
270
260
290
285
280
270
mA
AC Standby Current (VDD = max, E = VIH, MCM6341–10
No other restrictions on other inputs) MCM6341–11
MCM6341–12
MCM6341–15
ISB1 50
50
50
45
55
55
55
50
mA
CMOS Standby Current (E ≥ VDD – 0.2 V, Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)
(VDD = max, f = 0 MHz) ISB2 20 20
mA
NOTE: E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter Symbol Typ Max Unit
Input Capacitance All Inputs Except Clocks and DQs
E, G, W Cin
Cck 4
56
8pF
Input/Output Capacitance DQ CI/O 5 8 pF
MCM6341
5
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ±10%, TA = 0 to + 70°C, Unless Otherwise Noted)
(TA = – 40 to + 85°C for Industrial Temperature Offering)
Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .
Output Load See Figure 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ CYCLE TIMING (See Notes 1, 2, and 3)
P
Sbl
MCM6341–10 MCM6341–11 MCM6341–12 MCM6341–15
Ui
N
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
Read Cycle T ime tAVAV 10 — 11 — 12 — 15 — ns 4
Address Access Time tAVQV —10 — 11 — 12 — 15 ns
Enable Access T ime tELQV — 10 — 11 — 12 — 15 ns 5
Output Enable Access T ime tGLQV — 5 — 6 — 6 — 7 ns
Output Hold from Address Change tAXQX 3 — 3 — 3 — 3 — ns
Enable Low to Output Active tELQX 3 — 3 — 3 — 3 — ns 6, 7, 8
Output Enable Low to Output Active tGLQX 0 — 0 — 0 — 0 — ns 6, 7, 8
Enable High to Output High–Z tEHQZ 0 5 0 6 0 6 0 7 ns 6, 7, 8
Output Enable High to Output High–Z tGHQZ 0 5 0 6 0 6 0 7 ns 6, 7, 8
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
4. All read cycle timings are referenced from the last valid address to the first transitioning address.
5. Addresses valid prior to or coincident with E going low.
6. At any given voltage and temperature, tEHQZ max
t
tELQX min, and tGHQZ max
t
tGLQX min, both for a given device and from device
to device.
7. T ransition is measured ± 200 mV from steady–state voltage.
8. This parameter is sampled and not 100% tested.
9. Device is continuously selected (E ≤ VIL, G ≤ VIL).
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
VL = 1.5 V
Figure 1. AC Test Load
MCM6341
6MOTOROLA FAST SRAM
tAXQX
tAVAV
tAVQV
DATA VALIDPREVIOUS DATA V ALID
A (ADDRESS)
Q (DATA OUT)
READ CYCLE 1 (See Note 9)
Q (DATA OUT)
A (ADDRESS)
E (CHIP ENABLE)
G (OUTPUT ENABLE)
tAVAV
tELQV
tELQX tEHQZ
tGHQZ
tGLQV
tGLQX
tAVQV
ISB
SUPPLY CURRENT IDD
HIGH–Z DATA VALID
READ CYCLE 2 (See Notes 3 and 5)
MCM6341
7
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled; See Notes 1, 2, 3, and 4)
P
Sbl
MCM6341–10 MCM6341–11 MCM6341–12 MCM6341–15
Ui
N
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
Write Cycle Time tAVAV 10 — 11 — 12 — 15 — ns 5
Address Setup T ime tAVWL 0 — 0 — 0 — 0 — ns
Address Valid to End of Write tAVWH 9 — 10 — 10 — 12 — ns
Address Valid to End of Write (G
High) tAVWH 8 — 9 — 9 — 10 — ns
Write Pulse Width tWLWH
tWLEH 9 — 10 — 10 — 12 — ns
Write Pulse Width (G High) tWLWH
tWLEH 8 — 9 — 9 — 10 — ns
Data Valid to End of Write tDVWH 4 — 5 — 5 — 6 — ns
Data Hold T ime tWHDX 0 — 0 — 0 — 0 — ns
Write Low to Data High–Z tWLQZ 0 5 0 6 0 6 0 7 ns 6, 7, 8
Write High to Output Active tWHQX 3 — 3 — 3 — 3 — ns 6, 7, 8
Write Recovery Time tWHAX 0 — 0 — 0 — 0 — ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
5. All write cycle timings are referenced from the last valid address to the first transitioning address.
6. T ransition is measured ± 200 mV from steady–state voltage.
7. This parameter is sampled and not 100% tested.
8. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
DATA VALID
HIGH–Z HIGH–Z
tAVAV
tAVWH tWHAX
tWHDX
tWHQX
tWLWH
tAVWL tDVWH
tWLQZ
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
tWLEH
WRITE CYCLE 1 (W Controlled; See Notes 1, 2, 3, and 4)
MCM6341
8MOTOROLA FAST SRAM
WRITE CYCLE 2 (E Controlled; See Notes 1, 2, 3, and 4)
P
Sbl
MCM6341–10 MCM6341–11 MCM6341–12 MCM6341–15
Ui
N
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
Write Cycle Time tAVAV 10 — 11 — 12 — 15 — ns 5
Address Setup T ime tAVEL 0 — 0 — 0 — 0 — ns
Address Valid to End of Write tAVEH 9 — 10 — 10 — 12 — ns
Address Valid to End of Write (G
High) tAVEH 8 — 9 — 9 — 10 — ns
Enable Pulse Width tELEH,
tELWH 9 — 10 — 10 — 12 — ns 6, 7
Enable Pulse Width (G High) tELEH,
tELWH 8 — 9 — 9 — 10 — ns 6, 7
Data Valid to End of Write tDVEH 4 — 5 — 5 — 6 — ns
Data Hold T ime tEHDX 0 — 0 — 0 — 0 — ns
Write Recovery Time tEHAX 0 — 0 — 0 — 0 — ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
5. All write cycle timing is referenced from the last valid address to the first transitioning address.
6. If E goes low coincident with or after W goes low , the output will remain in a high–impedance condition.
7. If E goes high coincident with or before W goes high, the output will remain in a high–impedance condition.
DATA VALID
HIGH–Z
tAVAV
tAVEH
tAVEL tELWH tEHAX
tDVEH
tEHDX
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
tELEH
WRITE CYCLE 2 (E Controlled; See Notes 1, 2, 3, and 4)
MCM6341
9
MOTOROLA FAST SRAM
Motorola Memory Prefix
Part Number
Package (ZP = PBGA)
Shipping Method (PBGA Standard)
Speed (10 = 10 ns, 11 = 11 ns, 12 = 12 ns,
15 = 15 ns)
xCM 6341 XX XX XX
ORDERING INFORMATION
(Order by Full Part Number)
Full Commercial Part Numbers — MCM6341ZP10
MCM6341ZP11
MCM6341ZP12
MCM6341ZP15
Full Industrial Temperature Part Numbers — SCM6341ZP10A
SCM6341ZP12A
SCM6341ZP15A
ZP PACKAGE
119–PBGA
CASE 999–02
PACKAGE DIMENSIONS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
D2
E2
4X
16X
119X
TOP VIEW BOTTOM VIEW
SIDE VIEW
D
0.20
6X e
e
7654321
b
0.35 A
CE
0.25 A
0.20 A
A
SEATING
PLANE
A
A1
A2
A3
M
0.3 CA B
M
0.15 A
D1
E1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. ALL DIMENSIONS IN MILLIMETERS.
3. DIMENSION b IS THE MAXIMUM SOLDER BALL
DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
DIM MIN MAX
MILLIMETERS
A––– 2.40
A1 0.50 0.70
A2 1.30 1.70
A3 0.80 1.00
D22.00 BSC
D1 20.32 BSC
D2 19.40 19.60
E14.00 BSC
E1 7.62 BSC
E2 11.90 12.10
b0.60 0.90
e1.27 BSC
B
MCM6341
10 MOTOROLA FAST SRAM
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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Opportunity/Af firmative Action Employer.
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MCM6341/D
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