© Semiconductor Components Industries, LLC, 2009
October, 2009 − Rev. 7
1Publication Order Number:
CAT28LV65/D
CAT28LV65
64 kb CMOS Parallel
EEPROM
Description
The CAT28LV65 is a low voltage, low power, CMOS Parallel
EEPROM organized as 8K x 8−bits. It requires a simple interface for
in−system programming. On−chip address and data latches,
self−timed write cycle with auto−clear and VCC power up/down write
protection eliminate additional timing and protection hardware. DATA
Polling, RDY/BUSY and Toggle status bit signal the start and end of
the self−timed write cycle. Additionally, the CAT28LV65 features
hardware and software write protection.
The CAT28LV65 is manufactured using ON Semiconductor’s
advanced CMOS floating gate technology. It is designed to endure
100,000 program/erase cycles and has a data retention of 100 years.
The device is available in JEDEC approved 28−pin DIP, 28−pin TSOP,
28−pin SOIC or 32−pin PLCC packages.
Features
•3.0 V to 3.6 V Supply
•Read Access Times:
– 150/200/250 ns
•Low Power CMOS Dissipation:
– Active: 8 mA Max.
– Standby: 100 mA Max.
•Simple Write Operation:
– On−chip Address and Data Latches
– Self−timed Write Cycle with Auto−clear
•Fast Write Cycle Time:
– 5 ms Max.
•Commercial, Industrial and Automotive Temperature Ranges
•CMOS and TTL Compatible I/O
•Automatic Page Write Operation:
– 1 to 32 bytes in 5 ms
– Page Load Timer
•End of Write Detection:
– Toggle Bit
– DATA Polling
– RDY/BUSY
•Hardware and Software Write Protection
•100,000 Program/Erase Cycles
•100 Year Data Retention
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
ORDERING INFORMATION
PDIP−28
P, L SUFFIX
CASE 646AE
PLCC−32
N, G SUFFIX
CASE 776AK
Address InputsA0−A12
Data Inputs/OutputsI/O0−I/O7
Chip EnableCE
Output EnableOE
Write EnableWE
3.0 V to 3.6 V SupplyVCC
FunctionPin Name
PIN FUNCTION
SOIC−28
J, K, W, X SUFFIX
CASE 751BM
GroundVSS
No ConnectNC
Ready/BUSY StatusRDY/BSY
TSOP−28
H13 SUFFIX
CASE 318AE
CAT28LV65
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PIN CONFIGURATIONS
5
7
6
10
9
12
11
8
13
14 15 16 17 18 19 20
4 3 2 1 32 31 30
29
27
28
24
25
22
23
26
21
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
A7
A12
RDY/BUSY
NC
VCC
WE
NC
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
VSS
NC
PLCC Package (N, G)
DIP Package (P, L) SOIC Package (J, K, W, X)
5
4
7
6
3
2
1
10
9
12
11
8
22
23
20
21
24
25
26
17
18
15
16
19
14
13
27
28
5
4
7
6
3
2
1
10
9
12
11
8
22
23
20
21
24
25
26
17
18
15
16
19
14
13
27
28
TSOP Package (8 mm x 13.4 mm) (H13)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
A11
A9
A8
WE
VCC
RDY/BUSY
NC
RDY/BUSY
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
WE
VCC
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
RDY/BUSY
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
WE
VCC
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
(Top Views)
CAT28LV65
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ADDR. BUFFER
& LATCHES
ADDR. BUFFER
& LATCHES
INADVERTENT
CONTROL
LOGIC
TIMER
HIGH VOLTAGE
GENERATOR
I/O BUFFERS
32 BYTE PAGE
REGISTER
WRITE
PROTECTION
ROW
DECODER
COLUMN
DECODER
Figure 1. Block Diagram
CE
OE
WE
VCC
A0−A4
A5−A12
RDY/BUSY
DATA POLLING
RDY/BUSY &
TOGGLE BIT I/O0−I/O7
8,192 x 8
E2PROM
ARRAY
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Temperature Under Bias –55 to +125 °C
Storage Temperature –65 to +150 °C
Voltage on Any Pin with Respect to Ground (Note 1) –2.0 V to +VCC + 2.0 V V
VCC with Respect to Ground −2.0 to +7.0 V
Package Power Dissipation Capability (TA = 25°C) 1.0 W
Lead Soldering Temperature (10 secs) 300 °C
Output Short Circuit Current (Note 2) 100 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 2. RELIABILITY CHARACTERISTICS (Note 3)
Symbol Parameter Test Method Min Max Units
NEND Endurance MIL−STD−883, Test Method 1033 105Cycles/Byte
TDR Data Retention MIL−STD−883, Test Method 1008 100 Years
VZAP ESD Susceptibility MIL−STD−883, Test Method 3015 2,000 V
ILTH (Note 4) Latch−Up JEDEC Standard 17 100 mA
3. These parameters are tested initially and after a design or process change that affects the parameters.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC + 1 V.
Table 3. MODE SELECTION
Mode CE WE OE I/O Power
Read L H L DOUT ACTIVE
Byte Write (WE Controlled) L H DIN ACTIVE
Byte Write (CE Controlled) L H DIN ACTIVE
Standby and Write Inhibit H X X High−Z STANDBY
Read and Write Inhibit X H H High−Z ACTIVE
CAT28LV65
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Table 4. CAPACITANCE (TA = 25°C, f = 1.0 MHz)
Symbol Test Max Conditions Units
CI/O (Note 5) Input/Output Capacitance 10 VI/O = 0 V pF
CIN (Note 5) Input Capacitance 6 VIN = 0 V pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
Table 5. D.C. OPERATING CHARACTERISTICS (VCC = 3.0 V to 3.6 V, unless otherwise specified.)
Symbol Parameter Test Conditions
Limits
Units
Min Typ Max
ICC VCC Current (Operating, TTL) CE = OE = VIL,
f = 1/tRC min, All I/O’s Open
8 mA
ISBC (Note 6) VCC Current (Standby, CMOS) CE = VIHC, All I/O’s Open 100 mA
ILI Input Leakage Current VIN = GND to VCC −1 1 mA
ILO Output Leakage Current VOUT = GND to VCC,
CE = VIH
−5 5 mA
VIH (Note 6) High Level Input Voltage 2 VCC + 0.3 V
VIL Low Level Input Voltage −0.3 0.6 V
VOH High Level Output Voltage IOH = −100 mA2 V
VOL Low Level Output Voltage IOL = 1.0 mA 0.3 V
VWI Write Inhibit Voltage 2 V
6. VIHC = VCC − 0.3 V to VCC + 0.3 V.
Table 6. A.C. CHARACTERISTICS, READ CYCLE (VCC = 3.0 V to 3.6 V, unless otherwise specified.)
Symbol Parameter
28LV65−15 28LV65−20 28LV65−25
Units
Min Max Min Max Min Max
tRC Read Cycle Time 150 200 250 ns
tCE CE Access Time 150 200 250 ns
tAA Address Access Time 150 200 250 ns
tOE OE Access Time 70 80 100 ns
tLZ (Note 7) CE Low to Active Output 0 0 0 ns
tOLZ (Note 7) OE Low to Active Output 0 0 0 ns
tHZ (Notes 7, 8) CE High to High−Z Output 50 50 55 ns
tOHZ (Notes 7, 8) OE High to High−Z Output 50 50 55 ns
tOH (Note 7) Output Hold from Address
Change
0 0 0 ns
7. This parameter is tested initially and after a design or process change that affects the parameter.
8. Output floating (High−Z) is defined as the state when the external data line is no longer driven by the output buffer.
CAT28LV65
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Figure 2. A.C. Testing Input/Output Waveform (Note 9)
INPUT PULSE LEVELS REFERENCE POINTS
2.0 V
0.6 V
0.0 V
VCC − 0.3 V
9. Input rise and fall times (10% and 90%) < 10 ns.
Figure 3. A.C. Testing Load Circuit (example)
DEVICE
UNDER
TEST
1.8 K
OUTPUT
1. 3 K CL = 100 pF
CL INCLUDES JIG CAPACITANCE
VCC
Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (VCC = 3.0 V to 3.6 V, unless otherwise specified.)
Symbol Parameter
28LV65−15 28LV65−20 28LV65−25
Units
Min Max Min Max Min Max
tWC Write Cycle Time 5 5 5 ms
tAS Address Setup Time 0 0 0 ns
tAH Address Hold Time 100 100 100 ns
tCS CE Setup Time 0 0 0 ns
tCH CE Hold Time 0 0 0 ns
tCW (Note 10) CE Pulse Time 110 150 150 ns
tOES OE Setup Time 0 10 10 ns
tOEH OE Hold Time 0 10 10 ns
tWP (Note 10) WE Pulse Width 110 150 150 ns
tDS Data Setup Time 60 100 100 ns
tDH Data Hold Time 0 0 0 ns
tINIT (Note 11) Write Inhibit Period After Power−up 5 10 5 10 5 10 ms
tBLC (Notes 11, 12) Byte Load Cycle Time 0.05 100 0.1 100 0.1 100 ms
tRB WE Low to RDY/BUSY Low 220 220 220 ns
10.A write pulse of less than 20 ns duration will not initiate a write cycle.
11. This parameter is tested initially and after a design or process change that affects the parameter.
12. A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however
a transition from HIGH to LOW within tBLC max. stops the timer.
CAT28LV65
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DEVICE OPERATION
Read
Data stored in the CAT28LV65 is transferred to the data
bus when WE is held high, and both OE and CE are held low.
The data bus is set to a high impedance state when either CE
or OE goes high. This 2−line control architecture can be used
to eliminate bus contention in a system environment.
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either WE
or CE, with the address input being latched on the falling
edge of WE or CE, whichever occurs last. Data, conversely,
is latched on the rising edge of WE or CE, whichever occurs
first. Once initiated, a byte write cycle automatically erases
the addressed byte and the new data is written within 5 ms.
Figure 4. Read Cycle
ADDRESS
DATA OUT DATA VALIDDATA VALID
HIGH−Z
tOHZ
tHZ
tAA
tOH
tOE
tOLZ
tCE
tLZ
tRC
VIH
CE
OE
WE
Figure 5. Byte Write Cycle [WE Controlled]
ADDRESS
DATA OUT
DATA IN DATA VALID
HIGH−Z
HIGH−Z HIGH−Z
tOES tWP
tWC
CE
OE
WE
RDY/BUSY
tDS tDH
tCH
tOEH
tRB tBLC
tCS
tAH
tAS
CAT28LV65
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7
Page Write
The page write mode of the CAT28LV65 (essentially an
extended BYTE WRITE mode) allows from 1 to 32 bytes of
data to be programmed within a single EEPROM write
cycle. This effectively reduces the byte−write time by a
factor of 32.
Following an initial WRITE operation (WE pulsed low,
for tWP
, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address and
data bytes into a 32 byte temporary buffer. The page address
where data is to be written, specified by bits A5 to A12, is
latched on the last falling edge of WE. Each byte within the
page is defined by address bits A0 to A4 (which can be loaded
in any order) during the first and subsequent write cycles.
Each successive byte load cycle must begin within tBLC MAX
of the rising edge of the preceding WE pulse. There is no
page write window limitation as long as WE is pulsed low
within tBLC MAX.
Upon completion of the page write sequence, WE must
stay high a minimum of tBLC MAX for the internal automatic
program cycle to commence. This programming cycle
consists of an erase cycle, which erases any data that existed
in each addressed cell, and a write cycle, which writes new
data back into the cell. A page write will only write data to
the locations that were addressed and will not rewrite the
entire page.
Figure 6. Byte Write Cycle [CE Controlled]
ADDRESS
CE
OE
WE
DATA OUT
DATA IN
RDY/BUSY
tAS
tCS
tOES tCH
tOEH
DATA VALID
HIGH−Z
HIGH−Z
tDS tDH
tAH
tCW
tWC
tRB
tBLC
HIGH−Z
ADDRESS
I/O
BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2
LAST BYTE
Figure 7. Page Mode Write Cycle
OE
CE
WE
tWP tBLC
tWC
CAT28LV65
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DATA Polling
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is initiated,
attempting to read the last byte written will output the
complement of that data on I/O7 (I/O0–I/O 6 are
indeterminate) until the programming cycle is complete.
Upon completion of the self−timed write cycle, all I/O’s will
output true data during a read cycle.
Toggle Bit
In addition to the DATA Polling feature, the device offers
an additional method for determining the completion of a
write cycle. While a write cycle is in progress, reading data
from the device will result in I/O6 toggling between one and
zero. However, once the write is complete, I/O6 stops
toggling and valid data can be read from the device.
Ready/BUSY (RDY/BUSY)
The RDY/BUSY pin is an open drain output which
indicates device status during programming. It is pulled low
during the write cycle and released at the end of
programming. Several devices may be OR−tied to the same
RDY/BUSY line.
Figure 8. DATA Polling
ADDRESS
I/O7
WE
OE
CE
DIN = X DOUT = X DOUT = X
tOEH tOE
tWC
tOES
Figure 9. Toggle Bit
WE
OE
I/O6
CE
tOEH tOE
tWC
tOES
(Note 13) (Note 13)
13.Beginning and ending state of I/O6 is indeterminate.
CAT28LV65
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Hardware Data Protection
The following is a list of hardware data protection features
that are incorporated into the CAT28LV65.
1. VCC sense provides for write protection when VCC
falls below 2.0 V min.
2. A power on delay mechanism, tINIT (see AC
characteristics), provides a 5 to 10 ms delay before
a write sequence, after VCC has reached 2.40 V
min.
3. Write inhibit is activated by holding any one of
OE low, CE high or WE high.
4. Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
Software Data Protection
The CAT28LV65 features a software controlled data
protection scheme which, once enabled, requires a data
algorithm to be issued to the device before a write can be
performed. The device is shipped from ON Semiconductor
with the software protection NOT ENABLED (the
CAT28LV65 is in the standard operating mode).
Figure 10. Write Sequence for Activating Software
Data Protection
Figure 11. Write Sequence for Deactivating
Software Data Protection
WRITE DATA: XX
WRITE LAST BYTE
TO
LAST ADDRESS
TO ANY ADDRESS
WRITE DATA: AA
ADDRESS: 1555
WRITE DATA: 55
ADDRESS: 0AAA
WRITE DATA: A0
ADDRESS: 1555
WRITE DATA: AA
ADDRESS: 1555
WRITE DATA: 55
ADDRESS: 0AAA
WRITE DATA: 80
ADDRESS: 1555
WRITE DATA: AA
ADDRESS: 1555
WRITE DATA: 55
ADDRESS: 0AAA
WRITE DATA: 20
ADDRESS: 1555
SOFTWARE DATA
PROTECTION ACTIVATED (Note 14)
14.Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC Max.,
after SDP activation.
CAT28LV65
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Software Data Protection
To activate the software data protection, the device must
be sent three write commands to specific addresses with
specific data (Figure 10). This sequence of commands
(along with subsequent writes) must adhere to the page write
timing specifications (Figure 12). Once this is done, all
subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transitions.
This gives the user added inadvertent write protection on
power−up in addition to the hardware protection provided.
To allow the user the ability to program the device with an
EEPROM programmer (or for testing purposes) there is a
software command sequence for deactivating the data
protection. The six step algorithm (Figure 11) will reset the
internal protection circuitry, and the device will return to
standard operating mode (Figure 13 provides reset timing).
After the sixth byte of this reset sequence has been issued,
standard byte or page writing can commence.
AA
1555
55
0AAA
A0
1555
DATA
ADDRESS
BYTE OR
PAG E
WRITES
ENABLED
DATA
ADDRESS
SDP
RESET
DEVICE
UNPROTECTED
AA
1555
55
0AAA
80
1555
AA
1555
55
0AAA
20
1555
Figure 12. Software Data Protection Timing
Figure 13. Resetting Software Data Protection Timing
WE
CE
tWP tBLC
WE
CE
tWC
tWC
CAT28LV65
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11
PACKAGE DIMENSIONS
PLCC 32
CASE 776AK−01
ISSUE O
E1 E2E
PIN#1 IDENTIFICATION
D
D1
be
b1
D2
A2
A3
SIDE VIEW
TOP VIEW END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-016.
SYMBOL MIN NOM MAX
A2
A3
b
b1
D
D1
D2
E
E1
e
E2
2.54
0.33
0.66
12.32
12.10
11.36
9.56
14.86
0.38
2.80
0.54
0.82
12.57
13.86
11.50
11.32
15.11
1.27 BSC
13.90 14.04
CAT28LV65
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12
PACKAGE DIMENSIONS
SOIC−28, 300 mils
CASE 751BM−01
ISSUE O
L
hh
E
PIN #1
IDENTIFICATION
D
A1 c
q1
be
E1
A
A2
TOP VIEW
SIDE VIEW END VIEW
q1
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
q
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
h
0º 8º
0.10
0.31
0.20
0.25
17.78
10.11
7.34
1.27 BSC
2.65
0.30
0.51
0.33
0.75
18.03
10.51
7.60
L0.40 1.27
2.35
A2 2.05 2.55
θ1 5º 15º
CAT28LV65
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13
PACKAGE DIMENSIONS
PDIP−28, 600 mils
CASE 646AE−01
ISSUE A
c
E1
D
ebb1
A2 A
A1 L
eB
SIDE VIEW
TOP VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-011.
E
SYMBOL MIN NOM MAX
A
A1
A2
b
b1
c
D
e
E1
L
0.39
3.18
0.36
12.32
0.77
0.21
35.10
2.54 BSC
6.35
4.95
0.55
14.73
1.77
0.38
39.70
eB 15.24 17.78
E 15.24 15.87
2.93 5.08
CAT28LV65
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14
PACKAGE DIMENSIONS
TSOP 28, 8x13.4
CASE 318AE−01
ISSUE O
TOP VIEW
D
D1
PIN 1
e
L
L2
c
L1
b
A2
E1
SIDE VIEW
END VIEW
q1
A1
A
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-183.
SYMBOL MIN NOM MAX
q
θ
A
A1
A2
b
c
D
D1
E
e
L1
0° 5°
L2
0.05
0.90
0.17
0.10
0.675
13.20
11.70
7.90
0.55 BSC
0.25 BSC
1.20
0.15
1.05
0.27
0.20
13.60
11.90
8.10
13.40
11.80
8.00
θ1 10° 12° 16°
3°
1.00 1.10
1.00
0.22
0.15
L 0.30 0.700.50
CAT28LV65
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15
Example of Ordering Information (Note 15)
Prefix Device # Suffix
Company ID
CAT 28LV65 N
Product Number
28LV65
I− 25 T
Package
Blank = Commercial (0°C to +70°C)
I = Industrial (−40°C to +85°C)
A = Automotive (−40°C to +105°C) (Note 17)
Temperature Range
P: PDIP (Note 16)
J: SOIC (JEDEC) (Note 16)
K: SOIC (EIAJ) (Note 16)
N: PLCC (Note 16)
L: PDIP (Lead Free, Halogen Free)
W: SOIC (JEDEC) (Lead Free, Halogen Free)
X: SOIC (EIAJ) (Lead Free, Halogen Free)
G: PLCC (Lead Free, Halogen Free)
H13: TSOP (8 mm x 13.4 mm) (Lead Free, Halogen Free)
T: Tape & Reel
Speed
15: 150 ns
20: 200 ns
25: 250 ns
Tape & Reel (Note 18)
(Optional)
15.The device used in the above example is a CAT28LV65NI−25T (PLCC, Industrial temperature, 250 ns Access Time, Tape & Reel).
16.Solder−plate (tin−lead) packages, contact Factory for availability.
17.−40°C to +125°C is available upon request.
18.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ORDERING INFORMATION
Orderable Part Numbers (for Pb−Free Devices)
CAT28LV65GI−15T CAT28LV65H13A15T CAT28LV65WI−15T CAT28LV65XA−15T
CAT28LV65GI−20T CAT28LV65H13A20T CAT28LV65WI−20T CAT28LV65XA−20T
CAT28LV65GI−25T CAT28LV65H13A25T CAT28LV65WI−25T CAT28LV65XA−25T
CAT28LV65GA−15T CAT28LV65LI15 CAT28LV65WA−15T
CAT28LV65GA−20T CAT28LV65LI20 CAT28LV65WA−20T
CAT28LV65GA−25T CAT28LV65LI25 CAT28LV65WA−25T
CAT28LV65H13I15T CAT28LV65LA15 CAT28LV65XI−15T
CAT28LV65H13I20T CAT28LV65LA20 CAT28LV65XI−20T
CAT28LV65H13I25T CAT28LV65LA25 CAT28LV65XI−25T
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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CAT28LV65/D
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