CS4365-CQZ - Cirrus Logic - Datasheet.Directory

http://www.cirrus.com

114 dB, 192 kHz 6-Channel D/A Converter

Features

Advanced Multi-bit Delta Sigma Architecture

24-bit Conversion

Automatic Detection of Sample Rates up to

192 kHz

114 dB Dynamic Range

-100 dB THD+N

Direct Stream Digital Mode

– Non-Decimating Volume Control

– On-Chip 50 kHz Filter

– Matched PCM and DSD Analog Output

Levels

Selectable Digital Filters

Volume Control with 1/2-dB Step Size and Soft

Ramp

Low Clock-Jitter Sensitivity

+5 V Analog Supply, +2.5 V Digital Supply

Separate 1.8 to 5 V Logic Supplies for the

Control and Serial Ports

Description

The CS4365 is a complete 6-channel digital-to-analog

system. This D/A system includes digital de-emphasis,

half-dB step size volume control, ATAPI channel mix-

ing, selectable fast and slow digital interpolation filters

followed by an oversampled, mul ti-bit de lta sig ma mod-

ulator which includes mismatch-shaping technology

that eliminates distortion due to capacitor mismatch.

Following this stage is a multi-element switched capac-

itor stage and low-pass filter with differential analog

outputs.

The CS4365 also has a proprietary DSD processor

which allows for volume control and 50 kHz on-chip fil-

tering without an intermediate decimation stage. It also

offers an opti on al p ath fo r dir ect DSD conversion by di-

rectly using the multi-element switched ca pa citor array.

The CS4365 is available in a 48-pin LQFP package in

both Commercial (-40°C to +85°C) and Automotive

(-40°C to +105°C) grades. The CDB4365 Customer

Demonstration board is also available for device evalu-

ation and implementation suggestions. Please see

“Ordering Information” on p age 51 for complete details.

The CS4365 accepts PCM data at sample rates from

4 kHz to 216 kHz, DSD audio data, and delivers excel-

lent sound quality. These features are ideal for multi-

channel audio systems, including SACD players, A/V

receivers, digi ta l TV ’s, m ixing co ns ole s , e ffects proces-

sors, sound cards, and automotive audio systems.

Con tro l P o rt Su p p ly = 1 .8 V to 5 V

Configuration

Internal Voltage

Reference

Reset

Serial Interface

Level Translator

Digital Supply = 2.5 V

H a rd wa re Mod e o r

I2C/SPI Software Mode

Con tro l D ata

Analog Supply = 5 V

Six Channels of

D ifferen tia l

Outputs

PCM Serial

Audio Input

Volume

Controls

Digital

Filters

Switch-Cap

DAC and

Analog Filters

Multi-bit ΔΣ

Modulators

DSD Audio

Input

DSD Processor

-Volu me c o n trol

-50 k Hz filter

Ex te rna l M ute

Control M ute Signals

Serial Audio Port

Supply = 1.8 V to 5 V

FEB '08

DS670F2

CS4365

2DS670F2
CS4365
TABLE OF CONTENTS
PIN DESCRIPTION  ................................................................................................................................ 6
CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8
RECOMMENDED OPERATING CONDITIONS ..................................................................................... 8
ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 8
DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ)  ............................................................. 9
DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ) ............................................................ 10
POWER AND THERMAL CHARACTERISTICS  .................................................................................. 11
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE  ...................................... 12
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (CONTINUED) .............. 13
DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE ............................................. 13
DIGITAL CHARACTERISTICS ............................................................................................................. 14
SWITCHING CHARACTERISTICS - PCM ........................................................................................... 15
SWITCHING CHARACTERISTICS - DSD  ........................................................................................... 16
SWITCHING CHARACTE RISTIC S - CONTRO L PORT - I ²C FORMAT  ........... ... .... ... ... ... ... .... ... ... ... ... 17
SWITCHING CHARACTE RISTIC S - CONTRO L PORT - SPI FORMAT  ............................................. 18
TYPICAL CONNECTION DIAGRAM   .................................................................................................. 19
APPLICATIONS  ................................................................................................................................... 21
1 Master Clock ................................................................................................................................... 21
2 Mode Select .................................................................................................................................... 22
3 Digital Interface Formats  ................................................................................................................ 23
3.1 OLM #1 ........... ................ .... ... ... ................ ... .... ................ ... ... ... ................. ... ... ...................... 24
3.2 OLM #2 ........... ................ .... ... ... ................ ... .... ................ ... ... ... ................. ... ... ...................... 24
4 Oversampling Modes ...................................................................................................................... 24
5 Interpolation Filter ........................................................................................................................... 25
6 De-Emphasis .................................................................................................................................. 25
7 ATAPI Specification ........................................................................................................................ 26
8 Direct Stream Digital (DSD) Mode .................................................................................................. 26
9 Grounding and Power Supply Arrangements . ... ................ .... ... ... ................ ... .... ................ ... ... ... ... 27
9.1 Capacitor Placement ............................................................................................................. 27
10 Analog Output and Filtering .......................................................................................................... 28
11 The MUTEC Outputs .................................................................................................................... 29
12 Recommended Power-Up Sequence ........................................................................................... 29
12.1 Hardware Mode ................................................................................................................... 29
12.2 Software Mode .................................................................................................................... 30
13 Recommended Procedure for Switching Operational Modes ....................................................... 30
14 Control Port Interface  ................................................................................................................... 30
14.1 MAP Auto Increment . ... ....................................................................................................... 30
14.2 I²C Mode .......... .... ... ................ ... ... ................. ... ... ... ................ .... ... ................ ... ... ................ 30
14.2.1 I²C Write ......... ... .... ................ ... ... ................ .... ... ... ................ ... .... ................ ... ......... 31
14.2.2 I²C Read  ..................... ... ... .... ................ ... ... ................ .... ... ... ................ ... .... ............ 31
14.3 SPI Mode ............................................................................................................................. 32
14.3.1 SPI Write ........ ... .... ................ ... ... ................ .... ... ... ................ ... .... ................ ... ......... 32
15  Memory Address Pointer (MAP) .................................................................................................. 32
15.1 INCR (Auto Map Increment Enable) . ... ...... ....... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ...... 32
15.2 MAP4-0 (Memory Address Pointer)  . ................ ... ... .... ................ ... ... ................ ... .... ... ......... 32
REGISTER QUICK REFERENCE  ....................................................................................................... 33
REGISTER DESCRIPTION .................................................................................................................. 34
1 Chip Revision (address  01h) ......................................................................................................... 34
1.1 Part Number ID (PART) [Read Only]  .................................................................................... 34
2 Mode Control 1 (address 02h) ........................................................................................................ 34
2.1 Control Port Enable (CPEN) .. ... ... ... .... ... ... ................ .... ... ................ ... ... .... ................ ... ... ...... 34
2.2 Freeze Controls (FREEZE) ................................................................................................... 34

DS670F2 3
CS4365
2.3 PCM/DSD Selection (DSD/PCM) .......................................................................................... 35
2.4 DAC Pair Disable (DACx_DIS) ..............................................................................................35
2.5 Power Down (PDN) ............................ ... ... ................ .... ... ... ................ ... .... ................ ... ......... 35
3 PCM Control (address 03h) ............................................................................................................ 35
3.1 Digital Interface Format (DIF) ................................................................................................ 35
3.2 Functional Mode (FM) ........................................................................................................... 36
4 DSD Control (address 04h) ............................................................................................................ 36
4.1 DSD Mode Digital Interface Format (DSD_DIF) .... .......... ......... .......... ....... ......... .......... ......... 36
4.2 Direct DSD Conversion (DIR_DSD) ...................................................................................... 37
4.3 Static DSD Detect (STATIC_DSD) ........................................................................................ 37
4.4 Invalid DSD Detect (INVALID_DSD) ..................................................................................... 37
4.5 DSD Phase Modulation Mode Select (DSD_PM_MODE) ..................... .... ... ... ... ... .... ... ... ... ... 37
4.6 DSD Phase Modulation Mode Enable (DSD_PM_EN)  ... ... ... ... .... ... ... ... .... ...... ... ... .... ... ... ... ... 37
5 Filter Control (address 05h) ............................................................................................................ 38
5.1 Interpolation Filter Select (FILT_SEL) ...................................................................................38
6 Invert Control (address 06h) ........................................................................................................... 38
6.1 Invert Signal Polarity (Inv_xx) ................................................................................................ 38
7 Group Control (address 07h) .......................................................................................................... 38
7.1 Mute Pin Control (MUTEC1, MUTEC0) ................................................................................. 38
7.2 Channel A Volume = Channel B Volume (Px_A=B) .............................................................. 39
7.3 Single Volume Control (SNGLVOL) ...................................................................................... 39
8 Ramp and Mute (address 08h) ............. ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ...... ... .... ... ... ... ... .... ... ......... 39
8.1 Soft Ramp and Zero Cross CONTROL (SZC)  ...................................................................... 39
8.2 Soft Volume Ramp-Up after Error (RMP_UP) ....................................................................... 40
8.3 Soft Ramp-Down before Filter Mode Change (RMP_DN) ............ ... ... ... .... ... ... ... ... .... ... ...... ... 40
8.4 PCM Auto-Mute (PAMUTE)  .................................................................................................. 40
8.5 DSD Auto-Mute (DAMUTE) ...................................................................................................41
8.6 MUTE Polarity and DETECT (MUTEP1:0) ............................................................................ 41
9 Mute Control (address 09h) ............................................................................................................ 41
9.1 Mute (MUTE_xx) ................................................................................................................... 41
10 Mixing Control (address 0Ah, 0Dh, 10h, 13h)  .... .... ...... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ...... ... ... 42
10.1 De-Emphasis Control (PX_DEM1:0) ................................................................................... 42
10.2 ATAPI Channel Mixing and Muting (ATAPI) ........................................................................ 42
11 Volume Control (address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h) ............................................................ 43
11.1 Digital Volume Control (xx_VOL7:0) ................................................................................... 43
12 PCM Clock Mode (address 16h)  .................................................................................................. 44
12.1 Master Clock DIVIDE by 2 ENABLE (MCLKDIV) ................................................................ 44
FILTER PLOTS ..................................................................................................................................... 45
PARAMETER DEFINITIONS ................................................................................................................ 49
PACKAGE DIMENSIONS   ................................................................................................................... 50
ORDERING INFORMATIO N  ........... ................ ... ... ................ .... ... ... ................ ... .... ................ ... ......... 51
REFERENCES  ... .... ... ... ... .... ................ ... ... ................ .... ... ... ................ ... .... ................ ... ...................... 51
REVISION HISTORY  .. ... .... ... ... ................ ... .... ... ................ ... .... ... ................ ... ... ................................ 51

4DS670F2
CS4365
LIST OF FIGURES
Figure 1.Serial Audio Interface Timing ......... ... ... .... ... ... ... .... ... ... ... .... ... ...... ... .... ... ... ... .... ... ... ... ... ................ 15
Figure 2.Direct Stream Digital - Serial Audio Input Timing ........................................................................ 16
Figure 3.Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode ........................... 16
Figure 4.Control Port Timing - I²C Format . ... ................ ... .... ... ................ ... ... ................. ... ... ... ................... 17
Figure 5.Control Port Timing - SPI Format ... ... ... .... ...... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ...... ... .... ............ 18
Figure 6.Typical Connection Diagram, Software Mode .......... .......... ............ ............. ............. ............. ......19
Figure 7.Typical Connection Diagram, Hardware Mode ........................................................................... 20
Figure 8.Format 0 - Left-Justified up to 24-bit Data .................................................................................. 23
Figure 9.Format 1 - I²S up to 24-bit Data .................................................................................................. 23
Figure 10.Format 2 - Right-Justified 16-bit Data ....................................................................................... 23
Figure 11.Format 3 - Right-Justified 24-bit Data ....................................................................................... 23
Figure 12.Format 4 - Right-Justified 20-bit Data ....................................................................................... 23
Figure 13.Format 5 - Right-Justified 18-bit Data ....................................................................................... 24
Figure 14.Format 8 - One-Line Mode 1 ..................................................................................................... 24
Figure 15.Format 9 - One-Line Mode 2 ..................................................................................................... 24
Figure 16.De-Emphasis Curve ..... ... ... ................ .... ... ................ ... .... ... ................ ... ... ................ ................ 25
Figure 17.ATAPI Block Diagram (x = channel pair 1, 2, or 3) .......... ... ... ... ... .... ... ... ................ ... .... ............ 26
Figure 18.DSD Phase Modulation Mode Diagram .... ... ... ................. ... ... ................ ... .... ... ................ ... ... ...27
Figure 19.Full-Scale Output ............... .... ...... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ...... ... .... ... ... ...................... 28
Figure 20.Recommended Output Filter ..................................................................................................... 28
Figure 21.Recommended Mute Circuitry  .. ... ...... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ....... ... ... ... ... .... ... . ........ 29
Figure 22.Control Port Timing, I²C Mode .................................................................................................. 31
Figure 23.Control Port Timing, SPI Mode ................................................................................................. 32
Figure 24.Single-Speed (fast) Stopband Rejection ................................................................................... 45
Figure 25.Single-Speed (fast) Transition Band ......................................................................................... 45
Figure 26.Single-Speed (fast) Transition Band (detail) ............................................................................. 45
Figure 27.Single-Speed (fast) Passband Ripple ....................................................................................... 45
Figure 28.Single-Speed (slow) Stopband Rejection  ................................................................................. 45
Figure 29.Single-Speed (slow) Transition Band ........................................................................................ 45
Figure 30.Single-Speed (slow) Transition Band (detail) ............................................................................ 46
Figure 31.Single-Speed (slow) Passband Ripple ...................................................................................... 46
Figure 32.Double-Speed (fast) Stopband Rejection  ................................................................................. 46
Figure 33.Double-Speed (fast) Transition Band ........................................................................................ 46
Figure 34.Double-Speed (fast) Transition Band (detail) ............................................................................ 46
Figure 35.Double-Speed (fast) Passband Ripple ...................................................................................... 46
Figure 36.Double-Speed (slow) Stopband Rejection ................ ... .... ................ ... ... ................ ... .... ... ......... 47
Figure 37.Double-Speed (slow) Transition Band ......... ... .... ... ... ... .... ................ ... ... ................ ... .... ... ......... 47
Figure 38.Double-Speed (slow) Transition Band (detail) .......... ................................................................ 47
Figure 39.Double-Speed (slow) Passband Ripple ....... ... .... ... ... ... .... ... ................ ... ... .... ................ ... ... ...... 47
Figure 40.Quad-Speed (fast) Stopband Rejection .............. ... ... ... .... ... ... ... ... .... ... ... ... .... ...... ... ... .... ... ... .. .... 47
Figure 41.Quad-Speed (fast) Transition Band ............................. .... ... ... ... ... .... ... ... ....... ... ... ... ... .... ... .. ....... 47
Figure 42.Quad-Speed (fast) Transition Band (det ail) . ................ .... ... ... ................ ... .... ................ ... ... ...... 48
Figure 43.Quad-Speed (fast) Passband Ripple ........................................................................................ 48
Figure 44.Quad-Speed (slow) Stopband Rejection ................................................................................... 48
Figure 45.Quad-Speed (slow) Transition Band ......................................................................................... 48
Figure 46.Quad-Speed (slow) Transition Band (detail) ............................................................................. 48
Figure 47.Quad-Speed (slow) Passband Ripple ....................................................................................... 48

DS670F2 5
CS4365
LIST OF TABLES
Table 1. Single-Speed Mode Standard Frequencies ................................................................................21
Table 2. Double-Speed Mode Standard Frequencies ............................................................................... 21
Table 3. Quad-Speed Mode Standard Frequencies  . ... ... .... ... ................ ... ... .... ................ ... ... ................ ... 21
Table 4. PCM Digital Interface Format, Hardware Mode Options ............................................................. 22
Table 5. Mode Selection, Hardware Mode Options  .................................................................................. 22
Table 6. Direct Stream Digital (DSD), Hardware Mode Options  ............................................................... 22
Table 7. Digital Interface Formats - PCM Mode ........................................................................................ 36
Table 8. Digital Interface Formats - DSD Mode  ........................................................................................ 36
Table 9. ATAPI Decode Table  ........ ... .... ... ... ... ... ................. ... ... ... ................ .... ... ................ ... ... ................ 42
Table 10. Example Digital Volume Settings .............................................................................................. 43

6DS670F2

CS4365

1. PIN DESCRIPTION

Pin Name # Pin Description

VD 4 Digita l Power (Input) - Positive power supply for the digital section. Refer to the Recom-

mended Operating Conditions for appropriate voltages.

GND 5, 31 Ground (Input) - Ground reference. Shou ld be connected to analog ground.

MCLK 6 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Tables 1

through 3 illustrate several standard audio sample rates and th e required master clock fre-

quencies.

LRCK 7 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the

serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.

SDIN1

SDIN2

SDIN3

13 Serial Data Input (Input) - Input for two’s complement serial audio data.

SCLK 9 Serial Clock (Input) - Serial clocks for the serial audio interface.

TST 14

45 Test - These pins need to be tied to analog ground.

RST 19 Reset (Input) - The device enters a low power mode and all internal registers are reset to their

default settings when low.

VA 32 Analog Power (Input) - Positive power supply for the analog section. Refer to the Recom-

mended Operating Conditions for appropriate voltages.

VLS 43 Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio

interface. Refer to the Recommended Operating Conditions for appropriate voltages.

VLC 18 Control Port Power (Input) - Determines the required signal leve l for the control port and

Hardware Mode configuration pins. Refer to the Recommended Operating Conditions fo r

appropriate voltages.

SDIN3

GND

AOUTB2-

AOUTA3+

AOUTB3-

AOUTB2+

AOUTA3-

AOUTB3+

MUTEC2

MUTEC3

1213 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37

MCLK

DSDB1

SDIN1

M4(TST)

DSDA2

DSDA1

GND

SCLK

SDIN2

M3(TST)

LRCK

DSD_SCLK

DSDB3

DSDA3

TST

CS4365

TST

VLS

TST

M2(SCL/CCLK)

M1(SDA/CDIN)

VLC

RST

FILT+

MUTEC6

MUTEC5

MUTEC4

M0(AD0/CS)

AOUTA2+

AOUTA2-

AOUTB1+

AOUTB1-

AOUTA1-

AOUTA1+

DSDB2

MUTEC1

DS670F2 7

CS4365

VQ 21

Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be

capacitively coupled to analog ground, as shown in the T ypical Connection Diagram. The nom-

inal voltage level is specified in the Analog Characteristics and Specifications section. VQ pre-

sents an appreciable source impedance and any current drawn from this pin will alter device

performance. However, VQ can be used to bias the analog circuitry assuming th ere is no AC

signal component and the DC current is less then the maximum specified in the Analog Char-

acteristics and Specifications section.

FILT+ 20 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-

cuits. Requires the capacitive decoupling to analog ground as shown in the T ypical Connection

Diagram.

AOUTA1 +,-

AOUTB1 +,-

AOUTA2 +,-

AOUTB2 +,-

AOUTA3 +,-

AOUTB3 +,-

39,40

37,38

35,36

33,34

29,30

27,28

Differential Analog Output (Output) - The full-scale differential analog output level is specified

in the Analog Characteristics specification table.

MUTEC1

MUTEC2

MUTEC3

MUTEC4

MUTEC5

MUTEC6

Mute Control (Output) - The Mute Control pins go high during power-up initialization , reset,

muting, power-down or if the master clock to left/right clock frequency ratio is incorrect. These

pins are intended to be used as a control for external mute circuits on the line outputs to pre-

vent the clicks and pops that can occur in any single supply system. Use of Mute Control is not

mandatory but recommended for designs requiring the absolute minimum in extraneous clicks

and pops.

Hardware Mode Definitions

Mode Selection (Input) - Determines the operational mode of the device as detailed in Table 6

and Table 7.

Software Mode Definitions

SCL/CCLK 15 Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external

pull-up resistor to the logic interfa c e voltage in I²C® Mode as shown in th e Typical Connection

Diagram.

SDA/CDIN 16 Serial Control Port Data (Input/Output) - SDA is a data I/O line in I²C Mode and is open drain,

requiring an external pull-up resistor to the logic interface voltage, as shown in the T ypical Con-

nection Diagram; CDIN is the input da ta line for the control port interface in SPI™ Mode.

AD0/CS 17 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C

Mode; CS is the chip-select signal for SPI Mode.

TST 10, 12 Test - These pins need to be tied to analog ground .

DSD Definitions

DSDA1

DSDB1

DSDA2

DSDB2

DSDA3

DSDB3

Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data. GND if

unused.

DSD_SCLK 42 DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital serial audio interface.

Pin Name # Pin Description

8DS670F2

CS4365

2. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

GND = 0 V; all voltages with respect to ground.

ABSOLUTE MAXIMUM RATINGS

GND = 0 V; all voltages with respect to ground.

WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

Parameters Symbol Min Typ Max Units

DC Power Supply Analog power

Digital internal power

Serial data port interfa c e p owe r

Control po rt interface p ow e r

VLS

VLC

4.75

2.37

1.71

5.0

2.5

5.0

5.25

2.63

5.25

Ambient Operating Temperature (Power Applied)

Commercial Grade (-CQZ)

Automotive Grade (-DQZ) TA-40

-40 -

-+ 85

+105 °C

°C

Parameters Symbol Min Max Units

DC Power Supply Analog power

Digital internal power

Serial data port interfa c e p owe r

Control po rt interface p ow e r

VLS

VLC

-0.3

6.0

3.2

6.0

Input Current Any Pin Except Supplies Iin -±10mA

Digital Input Voltage Serial data port interface

Control port interface VIND-S

VIND-C

-0.3

-0.3 VLS+ 0.4

VLC+ 0.4 V

Ambient Operating Temperature (Power Applied) Top -55 125 °C

Storage Temperature Tstg -65 150 °C

DS670F2 9

CS4365

DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ)

Test Conditions (unless otherwise specified): VA = VLS = VLC = 5 V; VD = 2.5 V; TA = 25°C; Full-scale 997 Hz

input sine wave (Note 1); Tested under max ac-load resistance; Valid with FILT+ and VQ capacitors as shown in

“Typical Connection Diagram” on page 19; Measurement Bandwidth 10 Hz to 20 kHz.

Notes: 1. One-half LSB of triangular PDF dither is added to data.

2. Performance limited by 16-bit quantization noise.

3. VFS is tested under load RL and includes attenuation due to ZOUT.

Parameters Symbol Min Typ Max Unit

Fs = 48 kHz, 96 kHz, 192 kHz and DSD

Dynamic Range 24-bit A-weighted

unweighted

16-bit A-weighted

(Note 2) unweighted

108

105

114

111

Total Harmonic Distortion + Noise 24-bit

0 dB

-20 dB

-60 dB

(Note 2) 16-bit 0 dB

-20 dB

-60 dB

THD+N

-100

-91

-51

-94

-74

-34

-94

-45

Idle Channel Noise / Signal-to-noise ratio A-weighted - 114 - dB

Interchannel Isolation (1 kHz) - 110 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB

Gain Drift - 100 - ppm/°

Analog Output

Full-Scale Differential- PCM, DSD processor

Output Voltage (Note 3) Direct DSD Mode VFS 1.28•VA

0.90•VA

1.32•VA

0.94•VA

1.36•VA

0.98•VA

Vpp

Output Impedance ZOUT - 130 - Ω

Max DC Current draw from an AOUT pin IOUTmax -1.0-mA

Min AC-Load Resistance RL-3-kΩ

Max Load Capacitance CL- 100 - pF

Quiescent Voltage VQ - 50% VA-VDC

Max Current draw from VQ IQMAX -10-μA

10 DS670F2

CS4365

DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ)

Test Conditions (unless otherwise specified): VA = 4.75 to 5.25 V; VLS = 1.71 to 5.25 V; VLC = 1.71 to 5.25 V;

VD = 2.37 to 2.63 V; TA = -40°C to 85°C; Full-scale 997 Hz input sine wave (Note 1); Tested un de r m ax ac -lo ad

resistance; Valid with FILT+ and VQ capacitors as shown in “Typical Connection Diagram” on page 19; Measure-

ment Bandwidth 10 Hz to 20 kHz.

Parameters Symbol Min Typ Max Units

Fs = 48 kHz, 96 kHz, 192 kHz and DSD

Dynamic Range (Note 1) 24-bit A-weighted

unweighted

16-bit A-weighted

(Note 2) unweighted

105

102

114

111

Total Harmonic Distortion + Noise (Note 1)

24-bit 0 dB

-20 dB

-60 dB

(Note 2) 16-bit 0 dB

-20 dB

-60 dB

THD+N

-100

-91

-51

-94

-74

-34

-91

-42

Idle Channel Noise / Signal-to-noise ratio A-weighted - 114 - dB

Interchannel Isolation (1 kHz) - 110 - dB

DC Accuracy

Interchannel Gain Misma tch - 0.1 - dB

Gain Drift - 100 - ppm/°C

Analog Output

Full-Scale Differential- PCM, DSD processor

Output Voltage (Note 3) Direct DSD Mode VFS 1.28•VA

0.90•VA

1.32•VA

0.94•VA

1.36•VA

0.98•VA

Vpp

Output Impedance ZOUT -130-Ω

Max DC Current draw from an AOUT pin IOUTmax -1.0-mA

Min AC-Load Resistance RL-3 -kΩ

Max Load Capacitance CL-100 -pF

Quiescent Voltage VQ - 50% VA-VDC

Max Current draw from VQ IQMAX -10-μA

DS670F2 11
CS4365
POWER AND THERMAL CHARACTERISTICS
    
Notes: 4. Cur rent consumption increases with incr easing Fs within a given speed mod e and is signal dependent.
Max values are based on highest Fs and highest MCLK. 
5. ILC measured with no external loading on the SDA pin.
6. Power-Down Mode is defined as RST pin = Low with all clock and data lines held static. 
7. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 6 and 7.
Parameters Symbol Min Typ Max Units
Power Supplies
Power Supply Current      normal operation, VA= 5 V
(Note 4)            VD= 2.5 V
(Note 5) Interface current, VLC=5 V
VLS=5 V
(Note 6) power-down state (all supplies)
IA
ID
ILC
ILS
Ipd
-
-
-
-
-
60
16
2
84
200
65
22
-
-
-
mA
mA
μA
μA
μA
Power Dissipation (Note 4) VA = 5V, VD = 2.5V
normal operation
(Note 6) power-down -
-340
1390
-mW
mW
Package Thermal Resistance multi-layer
dual-layer θJA
θJA
θJC
-
-
-
48
65
15
-
-
-
°C/Watt
°C/Watt
°C/Watt
Power Supply Rejection Ratio (Note 7)   (1 kHz)
 (60 Hz) PSRR -
-60
40 -
-dB
dB

12 DS670F2
CS4365
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
The filter charact er istic s ha ve be e n no rm a lized  to th e sample rate (Fs) and can be referenced to the desired sam-
ple rate by multiplying the given characteristic by Fs. See Note 12.
Notes: 8. Slow roll-off interpolation filter is only available in Software Mode.
9. Response is clock-dependent and will scale with  Fs.
10. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. 
For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.
11. De-emphasis is availa ble only in Single-Speed Mode; only 44.1 kHz De-emphasis is available in Hard-
ware Mode.
12. Amplitude vs. Frequency plots of this data are available in Section 7. “Filter Plots” on page 45.
Parameter Fast Roll-Off Unit
Min Typ Max
Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz 
Passband (Note 9) to -0.01 dB corner
to -3 dB corner 0
0-
-.454
.499 Fs
Fs
Frequency Response  10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand 0.547 - - Fs
StopBand Attenuation (Note 10) 102 - - dB
Group Delay  - 10.4/Fs - s
De-emphasis Error (Note 11) Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
±0.36
±0.21
±0.14
dB
dB
dB
Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz 
Passband (Note 9) to -0.01 dB corner
to -3 dB corner 0
0-
-.430
.499 Fs
Fs
Frequency Response  10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand .583 - - Fs
StopBand Attenuation (Note 10) 80 - - dB
Group Delay - 6.15/Fs - s
Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz 
Passband (Note 9)  to -0.01 dB corner
to -3 dB corner 0
0-
-.105
.490 Fs
Fs
Frequency Response  10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand .635 - - Fs
StopBand Attenuation (Note 10) 90 - - dB
Group Delay - 7.1/Fs - s

DS670F2 13
CS4365
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE 
(CONTINUED)
DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE
Parameter Slow Roll-Off (Note 8) Unit
Min Typ Max
Single-Spe e d Mo d e  - 48 kHz 
Passband (Note 9) to -0.01 dB corner
to -3 dB corner 0
0-
-0.417
0.499 Fs
Fs
Frequency Response  10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand .583 - - Fs
StopBand Attenuation (Note 10) 64 - - dB
Group Delay  - 7.8/Fs - s
De-emphasis Error (Note 11) Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
±0.36
±0.21
±0.14
dB
dB
dB
Double-Speed Mode - 96 kHz
Passband (Note 9) to -0.01 dB corner
to -3 dB corner 0
0-
-.296
.499 Fs
Fs
Frequency Response  10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand .792 - - Fs
StopBand Attenuation (Note 10) 70 - - dB
Group Delay - 5.4/Fs - s
Quad-Speed Mode - 192 kHz 
Passband (Note 9)  to -0.01 dB corner
to -3 dB corner 0
0-
-.104
.481 Fs
Fs
Frequency Response  10 Hz to 20 kHz -0.01 - +0.01 dB
StopBand .868 - - Fs
StopBand Attenuation (Note 10) 75 - - dB
Group Delay - 6.6/Fs - s
Parameter Min Typ Max Unit
DSD Processor Mode
Passband (Note 9) to -3 dB corner 0 - 50 kHz
Frequency Response  10 Hz to 20 kHz -0.05 - +0.05 dB
Roll-off 27 - - dB/Oct
Direct DSD Mode
Passband (Note 9)  to -0.1 dB corner
to -3 dB corner 0
0-
-26.9
176.4 kHz
kHz
Frequency Response 10 Hz to 20 kHz -0.1 - 0 dB

14 DS670F2

CS4365

DIGITAL CHARACTERISTICS

Notes: 13. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latch-

up.

Parameters Symbol Min Typ Max Units

Input Leakage Current (Note 13) Iin --±10μA

Input Capacitance - 8 - pF

High-Level Input Voltage Serial I/O

Control I/O VIH

VIH

0.70•VLS

0.70•VLC

-V

Low-Level Input Voltage Serial I/O

Control I/O VIL

VIL

-0.30•VLS

0.30•VLC

Low-Level Output Voltage (IOL = -1.2 mA) Control I/O = 3.3 V, 5 V VOL - - 0.20•VLC V

Low-Level Output Voltage (IOL = -1.2 mA) Control I/O = 1.8 V, 2.5 V VOL - - 0.25•VLC V

MUTEC auto detect input high voltage VIH 0.70•VA--V

MUTEC auto detect input low voltage VIL - - 0.30•VAV

Maximum MUTEC Drive Current Imax -3-mA

MUTEC High-Level Output Voltage VOH -VA-V

MUTEC Low-Level Output Voltage VOL -0-V

DS670F2 15

CS4365

SWITCHING CHARACTERISTICS - PCM

Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 20 pF.

Notes: 14. After powering up, RST should be held low until after the power supplies and clocks ar e settled.

15. See Tables 1 - 3 for suggested MCLK frequencies.

16. MSB of CH1 is always the second SCLK rising edge following LRCK rising edge.

Parameters Symbol Min Max Units

RST pin Low Pulse Width (Note 14) 1-ms

MCLK Frequency 1.024 55.2 MHz

MCLK Duty Cycle (Note 15) 45 55 %

Input Sample Rate - LRCK (Manual selection) Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

100

108

216

kHz

Input Sample Rate - LRCK (Auto detect) Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

170

108

216

kHz

LRCK Duty Cycle 45 55 %

SCLK Duty Cycle 45 55 %

SCLK High Time tsckh 8-ns

SCLK Low Time tsckl 8-ns

LRCK Edge to SCLK Rising Edge tlcks 5-ns

SCLK Rising Edge to LRCK Falling Edge tlckd 5-ns

SDIN Setup Time Before SCLK Rising Edge tds 3-ns

SDIN Hold Time After SCLK Rising Edge tdh 5-ns

SDINx

tds

SCLK

LRCK

MSB

tdh

tsckh tsckl

tlcks

MSB-1

Figure 1. Serial Audio Interface Timing

16 DS670F2

CS4365

SWITCHING CHARACTERISTICS - DSD

Logic 0 = GND; Logic 1 = VLS; CL=20pF.

Parameter Symbol Min Typ Max Unit

MCLK Duty Cycle 40 - 60 %

DSD_SCLK Pulse Width Low tsclkl 160 - - ns

DSD_SCLK Pulse Width High tsclkh 160 - - ns

DSD_SCLK Frequency (64x Oversampled)

(128x Oversampled) 1.024

2.048 -

-3.2

6.4 MHz

MHz

DSD_A / _B valid to DSD_SCLK rising setup time tsdlrs 20 - - ns

DSD_SCLK rising to DSD_A or DSD_B hold time tsdh 20 - - ns

DSD clock to data transition (Phase Modulation Mode) tdpm -20 - 20 ns

sclkh

sclkl

DSDxx

DSD_SCLK

sdlrs

tsdh

Figure 2. Direct Stream Digital - Serial Audio Input Timing

dpm

DSDxx

DSD_SCLK

(64Fs)

DSD_SCLK

(128Fs)

dpm

Figure 3. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode

DS670F2 17

CS4365

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT

Inputs: Logic 0 = GND, Logic 1 = VLC, CL=20pF.

Notes: 17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

Parameter Symbol Min Max Unit

SCL Clock Frequency fscl - 100 kHz

RST Rising Edge to Start tirs 500 - ns

Bus Free Time Between Transmissions tbuf 4.7 - µs

Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs

Clock Low time tlow 4.7 - µs

Clock High Time thigh 4.0 - µs

Setup Time for Repeated Start Condition tsust 4.7 - µs

SDA Hold Time from SCL Falling (Note 17) thdd 0-µs

SDA Setup time to SCL Rising tsud 250 - ns

Rise T ime of SCL and SDA trc, trc -1µs

Fall Time SCL and SDA tfc, tfc -300ns

Setup Time for Stop Condition tsusp 4.7 - µs

Acknowledge Delay from SCL Falling tack 300 1000 ns

buf thdst

hdst

low

hdd

thigh

sud

sust

susp

Stop Start

Start

Stop

Repeated

SDA

SCL

irs

RST

Figure 4. Control Port Timing - I²C Format

18 DS670F2

CS4365

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT

Inputs: Logic 0 = GND, Logic 1 = VLC, CL=20pF.

Notes: 18. tspi is only needed before first falling edge of CS after RST rising edge . t spi = 0 at all other times.

19. Data must be held for sufficient time to bridge the transition time of CCLK.

20. For FSCK < 1 MHz.

Parameter Symbol Min Max Unit

CCLK Clock Frequency fsclk -6MHz

RST Rising Edge to CS Falling tsrs 500 - ns

CCLK Edge to CS Falling (Note 18) tspi 500 - ns

CS High Time Between Tr ansmissions tcsh 1.0 - µs

CS Falling to CCLK Edge tcss 20 - ns

CCLK Low Time tscl 66 - ns

CCLK High Time tsch 66 - ns

CDIN to CCLK Rising Setup Time tdsu 40 - ns

CCLK Rising to DATA Hold Time (Note 19) tdh 15 - ns

Rise Time of CCLK and CDIN (Note 20) tr2 - 100 ns

Fall Time of CCLK and CDIN (Note 20) tf2 - 100 ns

tr2 tf2

tdsu t

sch

tscl

CCLK

CDIN

tcss t

csh

tspi

tsrs

RST

Figure 5. Control Port Timing - SPI Format

DS670F2 19

CS4365

3. TYPICAL CONNECTION DIAGRAM

VLS

MCLK

AOUTA1+

0.1 µF +1 µF

+2.5 V

SDIN1

1 µF 0.1 µF

FILT+

CMOUT

LRCK

SCLK

SDIN3

SDIN2

0.1 µF47 µF

0.1 µF

1 µF

0.1 µF

+1.8 V to +5 V

+5 V

Analog Conditioning

and Muting

AOUTA1-

AOUTB1+ 38

37 Analog Conditioning

and Muting

AOUTB1-

AOUTA2+ 35

36 Analog Conditioning

and Muting

AOUTA2-

AOUTB2+ 34

33 Analog Conditioning

and Muting

AOUTB2-

AOUTA3+ 29

30 Analog Conditioning

and Muting

AOUTA3-

AOUTB3+ 28

27 Analog Conditioning

and Muting

AOUTB3-

MUTEC1 41

Mute

Drive

MUTEC2

Micro-

Controller

VLC

0.1 µF

+1.8 V to +5 V 18

48 DSDB2

42 DSD_SCLK

DSDA1

DSDB3

DSDA3

DSDB1

DSDA2

15 SCL/CCLK

SDA/CDIN

ADO/CS

RST

2 KΩ

Note*: Necessary for I2C

control port operation

Note*

MUTEC3 25

MUTEC4

MUTEC5 23

MUTEC6

CS4365

GND GND

5TST

10, 12,

14, 44, 45

DSD

Audio

Source

220 Ω

470 Ω

Digital

Audio

Source

PCM

Figure 6. Typical Connection Diagram, Software Mode

20 DS670F2

CS4365

VLS CS4365

MCLK

AOUTA1+

0.1 µF +1 µF

+2.5 V

SDIN1

1 µF 0.1 µF

FILT+

CMOUT

LRCK

SCLK

SDIN3

SDIN2

0.1 µF47 µF

0.1 µF

1 µF

0.1 µF

+1 .8 V to + 5 V

+5 V

AOUTA1-

AOUTB1+ 38

AOUTB1-

AOUTA2+ 35

AOUTA2-

AOUTB2+ 34

AOUTB2-

AOUTA3+ 29

AOUTA3-

AOUTB3+ 28

27 Analog Conditioning

and Muting

AOUTB3-

GND GND

VLC

0.1 µF

+1.8 V to + 5 V 18

48 DSDB2

12 M3

DSDA1

DSDB3

DSDA3

DSDB1

DSDA2

15 M2

RST

17 22

MUTEC6

Analog Conditioning

and Muting

MUTEC5

Analog Conditioning

and Muting

MUTEC4

Analog Conditioning

and Muting

MUTEC3

Analog Conditioning

and Muting

MUTEC2

Analog Conditioning

and Muting

MUTEC1

Stand-Alone

Mode

Configuration

DSD_SCLK

10 M4

TST

14, 44, 45

DSD

Digital

Audio

Source

PCM

Audio

Source

220 Ω

470 Ω

47 KΩ

Optional

Figure 7. Typical Connection Diagram, Hardware Mode

DS670F2 21

CS4365

4. APPLICATIONS

The CS4365 serially accepts two’s complement formatted PCM data at standard audio sample rates including 48,

44.1 and 32 kHz in SSM, 96, 88.2 an d 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio d ata is input via

the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input

on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer. For more information on serial

audio interfaces, see Cirrus Application Note AN282, “The 2-Channel Serial Audio Interface: A Tutor ial.”

The CS4365 can be configured in Hardware Mode by the M0, M1, M2, M3 and M4 pins and in Software Mode

through I²C or SPI.

4.1 Master Clock

MCLK/LRCK must be an integer ratio as shown in Tables 1 - 3. The LRCK frequency is equal to Fs, the

frequency at which words fo r each channel are input to the device. The MCLK-to-LRCK frequency ratio and

speed mode is detected automatically during the initialization sequence by countin g the number of MCLK

transitions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers are

then set to generate the proper internal clocks. Tables 1 - 3 illustrate several standard audio sample rates

and the required MCLK and LRCK frequencies. Please note there is no required phase relationship, but

MCLK, LRCK and SCLK must be synchronous.

Table 1. Single-Speed Mode Standard Frequencies

Table 2. Double-Speed Mod e Standard Frequencies

Table 3. Quad-Speed Mode Standard Frequencies

Sample Rate

(kHz) MCLK (MHz)

256x 384x 512x 768x 1024x 1152x

32 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640

44.1 11.2896 16.9344 22.5792 33.8688 45.1584

48 12.2880 18.4320 24.5760 36.8640 49.1520

= Denotes clock ratio and sample rate combinations which are NOT supported under auto speed-

mode detection. Please see “Switching Characteristics - PCM” on page 15.

Sample Rate

(kHz) MCLK (MHz)

128x 192x 256x 384x 512x

64 8.1920 12.2880 16.3840 24.5760 32.7680

88.2 11.2896 16.9344 22.5792 33.8688 45.1584

96 12.2880 18.4320 24.5760 36.8640 49.1520

= Denotes clock ratio and sample rate combinations which are NOT supported under auto speed-

mode detection. Please see “Switching Characteristics - PCM” on page 15.

Sample Rate

(kHz) MCLK (MHz)

64x 96x 128x 192x 256x

176.4 11.2896 16.9344 22.5792 33.8688 45.1584

192 12.2880 18.4320 24.5760 36.8640 49.1520

= Denotes clock ratio and sample rate combinations which are NOT supported under auto speed-

mode detection. Please see “Switching Characteristics - PCM” on page 15.

22 DS670F2
CS4365
4.2 Mode Select
In Hardware Mode, operatio n is determined by the Mode Select pins. The states of these pins are continu-
ally scanned for any changes; however, the mode should only be changed while the device is in reset
(RST pin low) to ensure proper switching from one mode  to another. Th ese pins require con nection to sup-
ply or ground as outlined in Figure 7. For M0, M1, and M2, supply is VLC. For M3 and M4, supply is VLS.
Tables 4 - 6 show the decode of these  pin s .
In Software Mode, the operational mode and data format are set in the FM and DIF registers. See “PCM
Control (address 03h)” on page 35.
Table 4. PCM Digital Interfa ce Forma t, Ha rdw a re  Mode  Options
M1
(DIF1) M0
(DIF0) DESCRIPTION FORMAT FIGURE
0 0 Left-Justified, up to 24-bit data 0 8
0 1 I²S, up to 24-bit data 1 9
1 0 Right-Justified, 16-bit Data 2 10
1 1 Right-Justified, 24-bit Data 3 11
M4 M3 M2
(DEM) DESCRIPTION
0 0 0 Single-Speed without De-Emphasis (4 to 50 kHz sample rates)
0 0 1 Single-Speed with 44.1 kHz De-Emphasis; see Figure 16
0 1 0 Double-Speed (50 to 100 kHz sample rates)
0 1 1 Quad-Speed (100 to 200 kHz sample rates)
1 0 0 Auto Speed-Mode Detect (32 kHz to 200 kHz sample rates)
1 0 1 Auto Spe ed-Mode Detect with 44.1 kHz De-Emphasis; see Figure 16
1 1 X DSD Processor Mode  (see  Table 6 for details)
Table 5. Mode Selection, Hardware Mode Options
M2 M1 M0 DESCRIPTION
000
64x oversampled DSD data with a 4x MCLK to DSD data rate
001
64x oversampled DSD data with a 6x MCLK to DSD data rate
010
64x oversampled DSD data with a 8x MCLK to DSD data rate
011
64x oversampled DSD data with a 12x MCLK to DSD data rate
100
128x oversampled DSD data with a 2x MCLK to DSD data rate
101
128x oversampled DSD data with a 3x MCLK to DSD data rate
110
128x oversampled DSD data with a 4x MCLK to DSD data rate
111
128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 6. Direct Stream Digital (DSD), Hardware Mode Options

DS670F2 23

CS4365

4.3 Digital Interface Formats

The serial port operates as a slave and supports th e I²S, Lef t-Justified, Right- Justified, and One- Line Mode

(OLM) digital interface formats with varying bit depths from 16 to 32, as shown in Figures 8-15. Data is

clocked into the DAC on the rising edge. OLM configuration is only supported in Software Mode.

LRCK

SCLK

Left Channel Right Channel

SDINx +3 +2 +1+5 +4

-1 -2 -3 -4 -5 +3 +2 +1+5 +4

-1 -2 -3 -4

MSB LSB MSB LSB

Figure 8. Format 0 - Left-Justified up to 24-bit Data

LRCK

SCLK

Left Channel Right Channel

SDINx +3 +2 +1+5 +4

-1 -2 -3 -4 -5 +3 +2 +1+5 +4

-1 -2 -3 -4

MSB MSB

LSB LSB

Figure 9. Format 1 - I²S up to 24-bit Data

LRCK

SCLK

Left Channel Right Channel

SDINx 6543210987

15 14 13 12 11 10 6543210987

15 14 13 12 11 10

32 clocks

Figure 10. Format 2 - Right-Justified 16-bit Data

LRCK

SCLK

Left Channel

SDINx 65432107

23 22 21 20 19 18 65432107

23 22 21 20 19 18

32 clocks

Right Channel

Figure 11. Format 3 - Right-Justified 24-bit Data

LRCK

SCLK

Left Channel Right Channel

SDINx 6543210987

15 14 13 12 11 10

10 6543210987

15 14 13 12 11 10

17 16 17 16

32 clocks

19 18 19 18

Figure 12. Format 4 - Right-Justified 20-bit Data

24 DS670F2

CS4365

4.3.1 OLM #1

OLM #1 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to

SCLK at 128 Fs. Six channels of MSB first 20-bit PCM data are input on SDIN1.

4.3.2 OLM #2

OLM #2 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to

SCLK at 256 Fs. Six channels of MSB first 24-bit PCM data are input on SDIN1.

4.4 Oversampling Modes

The CS4365 operates in one o f three oversamplin g modes base d on the input sample ra te. Mode selection

is determined by the M4, M3 and M2 pins in Hardware Mod e or the FM bits in Software Mode . Single-Speed

mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed Mode

supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode sup-

ports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.

The auto-speed mode detect feature allows for the automatic selectio n of spee d m ode ba sed off o f th e in-

coming sample rate. This allows the CS43 65 to accept a wid e rang e of sampl e rate s with no exte rnal inter -

vention necessary. The auto- speed mode detect featu re is available in both hardware and Software Mode.

LRCK

SCLK

Left Channel Right Channel

SDINx 6543210987

15 14 13 12 11 10

10 6543210987

15 14 13 12 11 10

17 16 17 16

32 clocks

Figure 13. Format 5 - Right-Justified 18-bit Data

LRCK

SCLK LSBMSB

20 clks

64 clks 64 clks

LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB MSB

DAC_A1

20 clks 20 clks 20 clks 20 clks 20 clks

Left Channel Right Channel

SDIN1 DAC_A2 DAC_A3 DAC_B1 DAC_B2 DAC_B3

Figure 14. Format 8 - One-Line Mode 1

LSBMSB

24 clks

128 clks

LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB MSB

DAC_A1

24 clks 24 clks 24 clks 24 clks 24 clks

Left Channel Right Channel

128 clks

LRCK

SCLK

SDIN1 DAC_A2 DAC_A3 DAC_B1 DAC_B2 DAC_B3

Figure 15. Format 9 - One-Line Mode 2

DS670F2 25

CS4365

4.5 Interpolation Filter

To accommodate the increasingly complex r equirements of digital audio systems, the CS4365 incorpor ates

selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is available in

each of Single, Double, and Qu ad -Spe ed mod es. The se filte rs have be en designed to accomm odate a va-

riety of musical tastes and styles. The FILT_SEL bit is used to select which filter is used (see the “Filter

Plots” on page 45 for more details).

When in Hardware Mode, only the “fast” roll-off filter is available.

Filter specifications can be found in Section , and filter response plots can be found in Figures 24 to 47.

4.6 De-Emphasis

The CS4365 includes on-chip d igital de-emphasis filters. The de-emphasis fe ature is included to accommo-

date older audio recordings that utilize pre-emphasis equalization as a means of noise reduction. Figure 16

shows the de-emphasis curve. The frequency response of the de-emphasis curve will s cale proportionally

with changes in sample rate, Fs if the input sample rate does not match the coefficient which has been se-

lected.

In Software M o de th e r equir ed d e- em pha sis filter coefficient s for 32 kHz, 44.1 kHz, or 48 kHz are selected

via the de-emphasis control bits.

In Hardware Mode only the 44.1 kHz coefficient is available (enabled through the M2 pin) . If the input sam-

ple rate is not 44.1 kHz and de-emphasis has been selected then the corner frequencies of the de-emphasis

filter will be scaled by a factor of the actual Fs over 44,100.

Gain

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1 F2

3.183 k Hz 10.61 kHz

Figure 16. De-Emphasis Curve

26 DS670F2

CS4365

4.7 ATAPI Specification

The CS4365 implements the channel-mixing functions of the ATAPI CD-ROM specification. The

ATAPI functions are applied per A-B pair. Refer to Table 9 on page 42 and Figure 17 fo r additional informa-

tion.

4.8 Direct Stream Digital (DSD) Mode

In Software Mode, the DSD/PCM bits (Reg. 02h) are used to configure the device for DSD Mode. The

DSD_DIF bits (Reg 04h) then control the expected DSD rate and MCLK ratio.

The DIR_DSD bit (Reg 04h) selects between two proprietary methods for DSD-to-analog conversion. The

first method use s a decim at i on -f re e D SD pr ocessing tech niqu e wh ich allo ws for fe atu r es s uc h a s ma tched

PCM-level output, DSD volume control, and 50kHz on-chip filter. The second method sends the DSD data

directly to the on-chip switched-capacitor filter for conversion (without the above-mentioned features).

The DSD_PM_EN bit (Reg. 04h) selects Phase Modulation (data plus data inverted) as the style of data

input. In this mode, the DSD_PM_mode bit selects whether a 128Fs or 64x clock is used for phase modu-

lated 64x data (see Figure 18). Use of Phase Modulation Mode may not directly affect the performance of

the CS4365, but may lower the sensitivity to board-level routing of the DSD data signals.

The CS4365 can detect errors in the DSD data which does not comply with the SACD specification. The

STATIC_DSD and INVALID_DSD bits (Reg. 04h) a llow the CS4365 to alte r the incoming invalid DSD data .

Depending on the error, the data may either be attenuated or replaced with a muted DSD signal (the

MUTEC pins would be set according to the DAMUTE bit (Reg. 08h)).

More information for any of these register bits can be found in Section 7. “Filter Plots” on page 45.

The DSD input structure and analog outputs are designed to handle a nominal 0 dB-SACD (50% modulation

index) at full rated performa nce. Sign als of +3 dB-SACD may be applied for b rief per iods of time, however ;

performance at these levels is not guaranteed. If sustained +3 dB-SACD levels are required, th e digital vol-

ume control should be set to -3.0 dB. This same volume control register affects PCM output levels. There

is no need to change the volume control setting between PCM and DSD in order to have the 0dB output

levels match (both 0 dBFS and 0 dB-SACD will output at -3 dB in this case).

ΣΣ

A Channel

Volume

Control AoutAx

AoutBx

Left Channel

Audio Data

Right Channel

Audio Data

BChannel

Volume

Control

MUTE

SDINx

Figure 17. ATAPI Block Diagram (x = channel pair 1, 2, or 3)

DS670F2 27

CS4365

4.9 Grounding and Power Supply Arrangements

As with any high-resolution converter, the CS4365 requires careful attention to power supply and grounding

arrangements if its potential perfor mance is to be realized . The Typical Connection Dia gram shows the rec-

ommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground

planes are split between d igital ground and analo g ground, the GND pins of the CS4365 should be connect-

ed to the analog ground plane.

All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted

coupling into the DAC.

4.9.1 Capacitor Placement

Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic ca-

pacitor being the closest. To further minimize impedance, these capacitors should b e located on the same

layer as the DAC. If desired, all supply pins with similar voltage ratings may be connected to the same

supply, but a decoupling capacitor should still be placed on each supply pin.

Notes: All decoupling capacitors should be referenced to ground.

The CDB4365 evaluation board demonstrates the optimum layout and power supply arrangements.

BCKA

(128Fs)

BCKD

(64Fs)

DSD_SCLK

DSDAx,

DSDBx

D1 D1

D1D0 D2

D2D0

DSD_SCLK

DSDAx,

DSDBx

BCKA

(64Fs)

DSD_SCLK

DSD Phase

Modulation Mode

DSD Normal Mode

Not Used

Figure 18. DSD Phase Modulation Mode Diagram

28 DS670F2

CS4365

4.10 Analog Output and Filtering

The application note “Design Notes for a 2-Pole Filter with Differential Input” discusses the second-order

Butterworth filter and differential to single-ended converter which was implemented on the CS4365 evalua-

tion board, CDB4365, as seen in Figure 20. The CS4365 does not include phase or amplitude compensa-

tion for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on

the external analog circuitry. The off-chip filter has been designed to attenuate the typical full-scale output

level to below 2 Vrms.

Figure 19 shows how the full-scale differential analog output level specification is derived.

AOUT+

AOUT-

Full-Scale Output Level= (AOUT+) - (AOUT-)= 6.6 Vpp

4.15 V

2.5 V

0.85 V

4.15 V

2.5 V

0.85 V

Figure 19. Full-Scale Output

Figure 20. Recommended Output Filter

DS670F2 29

CS4365

4.11 The MUTEC Outputs

The MUTEC1-6 pins have an auto-polarity detect feature. The MUTEC output pins are high impedance at

the time of reset. The e xternal mute circuitry needs to be self-biased into an active state in order to be muted

during reset. Upon release of reset, the CS4365 will detect the status of the MUTEC pins (high or low) and

will then select that state as the polarity to drive when the mutes become active. The external-bias voltage

level that the MUTEC pins see at the time of release of reset must meet the “MUTEC auto-detect input

high/low voltage” specifications as outlined in the Digital Characteristics section.

Figure 21 shows a single example of both an active high and an active low mute drive circuit. In these de-

signs, the pull-up a nd pull-down resistors have been espe cially chosen to meet the input high/low threshold

when used with the MMUN2111 and MMUN2211 internal bias resistances of 10 kΩ. Use of the Mute Control

function is not mandatory, but recommended, for designs requiring the absolute minimum in extraneous

clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle chan-

nel noise/signal-to-noise ratios which are only limited by the external mute circuit.

4.12 Recommended Power-Up Sequence

4.12.1 Hardware Mode

1. Hold RST low until the power supplies and configura tion pins are stable, and the ma ster and left/right

clocks are locked to the appropriate frequencies, as discussed in Section 4.1. In this state, the

registers are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2.

If RST can not be held low long enough the SDINx pins should remain static low until all other clocks

are stable, and if possible the RST should be toggled low again once the system is stable.

2. Bring RST high. The device will remain in a low power state with FILT+ low and will initiate the

Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024

LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).

Figure 21. Recommended Mute Circuitry

30 DS670F2

CS4365

4.12.2 Software Mode

1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the

appropriate frequencies, as discussed in Section 4.1. In this state, the registers are reset to the default

settings, FILT+ will remain low, and VQ will be connected to VA/2.

2. Bring RST high. The device will remain in a low power state with FILT+ low for 512 LRCK cycles in

Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LR CK cycles in Quad-

Speed Mode).

3. In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior to the

completion of approximately 51 2 LRCK cycles in Single- Speed Mod e (1024 LRCK cycles in Doub le-

Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be

loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1; then set the

format and mode control bits to the desired settings.

If more than the stated range of LRCK cycles passes before CPEN bit is written, the chip will enter

Hardware Mod e and begin to operate with the M0-M4 as the mode settings. CPEN bit may be written

at anytime, even after the Har dware sequence has begun. It is advised that if the CPEN bit cannot be

set in time, the SDINx pins should remain static low ( this way no audio data can be converted

incorrectly by th e Hardware Mode settings).

4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs .

4.13 Recommended Procedure for Switching Operational Modes

For systems where the ab solute minimu m in clicks and po ps is required , it is recommende d that the MUTE

bits are set prio r to changing sig nificant DAC fu nctions (suc h as changin g sample rate s or clock sour ces).

The mute bits may then be released after clocks have settled and the proper modes have been set.

It is required to have the device held in reset if the minimum high/low time specs of MC LK cannot be met

during clock source changes.

4.14 Control Port Interface

The control port is used to load all the internal register settings in order to operate in Software Mode (see

Section 7. “Filter Plots” on page 45). The oper ation of the control port may be completely asynchronous with

the audio sample rate. However, to avoid potential interference problems, the control port pins should re-

main static if no operation is required.

The control port operates in one of two modes: I²C or SPI.

4.14.1 MAP Auto Increment

The device has MAP (memory address pointer) auto-increment capability enabled by the INCR bit (also

the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and

SPI writes. If INCR is set to 1, MAP will auto-increment after each byte is written, allowing block reads or

writes of successive registers.

4.14.2 I²C Mode

In the I²C Mode, data is clocked into and out of the bi -directional serial control data line, SDA, by the serial

control port clock, SCL (see Figure 22 for the clock to data relationship). There is no CS pin. The AD0 pin

enables the user to alter the chip address ( 001100[AD0 ][R/W]) and should be tied to VLC or GND, as re-

quired, before power ing up th e device. If t he device ever de tects a h igh-to-lo w transitio n on the AD0 /CS

pin after power-up, SPI Mode will be selected.

DS670F2 31

CS4365

4.14.2.1 I²C Writ e

To write to the device, follow the procedure below while adhe ring to the control port Switching Specifica-

tions in Section .

1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be

001100. The seventh bi t must match the se tting of the AD0 pin, and the eighth must be 0. The eig hth

bit of the address byte is the R/W bit.

2. Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This

byte points to the register to be written.

3. Wait for an acknowledge (ACK) from the part, then write the desired da ta to the register poin ted to by

the MAP.

4. If the INCR bit (see Section 4.14.1) is set to 1, repeat the previous step until all the desired registers

are written, then initiate a STOP condition to the bus.

5. If the INCR bit is set to 0 and further I²C writes to other register s are d esired, it is necessar y to initi ate

a repeated START condition and follow the procedure detailed from step 1. If no fu rther writes to other

registers are desired, initiate a STOP condition to the bus.

4.14.2.2 I²C Read

To read from the device, follow the procedure below while adhering to the control port Switching Specifi-

cations.

1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be

001100. The seventh bi t must match the se tting of the AD0 pin, and the eighth must be 1. The eig hth

bit of the address byte is the R/W bit.

2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register

pointed to by the MAP. The MAP register will contain the address of the last register written to the

MAP, or the default addre ss ( see Section 4.14.1) if an I²C read is the first operation perfor med on the

device.

3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.

4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Con-

tinue providin g a cloc k an d issue an ACK afte r each byte until all the desir ed re gis te rs a re re ad , th en

initiate a STOP condition to the bus.

5. If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary to initiate

a repeated START condition and follow the procedure detailed from steps 1 and 2 from the I²C Write

instructions followed by step 1 of the I²C Rea d section. If no furthe r reads from othe r registers are de-

sired, initiate a STOP condition to the bus.

SDA

SCL

001100 ADDR

AD0 R/W

Start

ACK DATA

1-8 ACK DATA

1-8 ACK

Stop

Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.

Note 1

Figure 22. Control Port Timing, I²C Mode

32 DS670F2

CS4365

4.14.3 SPI Mode

In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK

(see Figure 23 for the clock to data relationship). Th ere is no AD0 pin. Pin CS is the chip select signal and

is used to control SPI writes to the control port. When the device detects a high to low transition on the

AD0/CS pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in on the

rising edge of CCLK.

4.14.3.1 SPI Write

To write to the device, follow the procedure below while adhering to the control port Switching Specifica-

tions in Section .

1. Bring CS low.

2. The address byte on the CDIN pin must then be 00110000.

3. Write to the memory address pointer, MAP. This byte points to the register to be written.

4. Write the desired data to the register pointed to by the MAP.

5. If the INCR bit (see Sectio n 4.14.1 ) is set to 1, repeat the previous step until all the desired registers

are written, then bring CS high.

6. I f the INC R bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring

CS high, and follow the procedure detailed from step 1. If no further writes to other registers are de-

sired, bring CS high.

4.15 Memory Address Pointer (MAP)

4.15.1 INCR (Auto Map Increment Enable)

Default = ‘0’

0 - Disabled

1 - Enabled

4.15.2 MAP4-0 (Memory Address Pointer)

Default = ‘00000’

76543210

INCR Reserved Reserved MAP4 MAP3 MAP2 MAP1 MAP0

00000000

MAP

MSB LSB

DATA

byte 1 byte n

R/W

MAP = Memory Address Pointer

ADDRESS

CHIP

CDIN

CCLK

0011000

Figure 23. Control Port Timing, SPI Mode

DS670F2 33

CS4365

5. REGISTER QUICK REFERENCE

Addr Function 7 6 5 4 3 2 1 0

01h Chip Revision PART4 PART3 PART2 PART1 PART0 REV REV REV

default 0 1 1 0 1 x x x

02h Mode Control CPEN FREEZE DSD/PCM Reserved DAC3_DIS DAC2_DIS DAC1_DIS PDN

default 0 0 0 0 0 0 0 1

03h PCM Control DIF3 DIF2 DIF1 DIF0 Reserved Reserved FM1 FM0

default 0 0 0 0 0 0 1 1

04h DSD Control DSD_DIF2 DSD_DIF1 DSD_DIF0 DIR_DSD STATIC_D

SD INVALID_D

SD DSD_PM_

MD DSD_PM_

default 0 0 0 0 1 0 0 0

05h Filter Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved FILT_SEL

default 0 0 0 0 0 0 0 0

06h Invert Control Reserved Reserved INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1

default 0 0 0 0 0 0 0 0

07h Group Control MUTEC1 M UTEC0 Reserved P1_A=B P 2_A=B P3_A=B Reserved SNGLVOL

default 0 0 0 0 0 0 0 0

08h Ramp and Mute SZC1 SZC0 RMP_UP RMP_DN PAMUTE DAMUTE MUTE_P1 MUTE_P0

default 1 0 1 1 1 1 0 0

09h Mute Control Reserved Reserved MUTE_B3 MUTE_A3 MUTE_B2 MUTE_A2 MUTE_B1 MUTE_A1

default 0 0 0 0 0 0 0 0

0Ah Mixing Control

Pair 1 (AOUTx1) Reserved P1_DEM1 P1_DEM0 P1ATAPI4 P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0

default 0 0 0 0 1 0 0 1

0Bh Vol. Control A1 A1_VOL7 A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0

default 0 0 0 0 0 0 0 0

0Ch Vol. Control B1 B1_VOL7 B1_VOL6 B1_VOL5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0

default 0 0 0 0 0 0 0 0

0Dh Mixing Control

Pair 2 (AOUTx1) Reserved P2_DEM1 P2_DEM0 P2ATAPI4 P2ATAPI3 P2ATAPI2 P2ATAPI1 P2ATAPI0

default 0 0 0 0 1 0 0 1

0Eh Vol. Control A2 A2_VOL7 A2_VOL6 A2_VOL5 A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1 A2_VOL0

default 0 0 0 0 0 0 0 0

0Fh Vol. Control B2 B2_VOL7 B2_VOL6 B2_VOL5 B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1 B2_VOL0

default 0 0 0 0 0 0 0 0

10h Mixing Control

Pair 3 (AOUTx1) Reserved P3_DEM1 P3_DEM0 P3ATAPI4 P3ATAPI3 P3ATAPI2 P3ATAPI1 P3ATAPI0

default 0 0 0 0 1 0 0 1

11h Vol. Control A3 A3_VOL7 A3_VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3_VOL2 A3_VOL1 A3_VOL0

default 0 0 0 0 0 0 0 0

12h Vol. Control B3 B3_VOL7 B3_VOL6 B3_VOL5 B3_VOL4 B3_VOL3 B3_VOL2 B3_VOL1 B3_VOL0

default 0 0 0 0 0 0 0 0

16h PCM clock mode Reserved Reserved MCLKDIV Reserved Reserved Reserved Reserved Reserved

default 0 0 0 0 0 0 0 0

34 DS670F2

CS4365

6. REGISTER DESCRIPTION

Note: All registers ar e re a d/w rite in I²C Mod e an d wr it e on ly in S PI, un les s othe rwise noted.

6.1 Chip Revision (address 01h)

6.1.1 Part Number ID (PART) [Read Only]

01101- CS4365

Revision ID (REV) [Read Only]

000 - Revision A0

001 - Revision B0

Function:

This read-only register can be used to identify the model and revision number of the device.

6.2 Mode Control 1 (address 02h)

6.2.1 Control Port Enable (CPEN)

Default = 0

0 - Disabled

1 - Enabled

Function:

This bit defaults to 0, allowi ng the devic e to powe r-up in Stan d-Alone Mode. The Contro l Port Mod e can

be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the reg-

isters, and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user

should write this bit within 10 ms following the release of Reset.

6.2.2 Freeze Controls (FREEZE)

Default = 0

0 - Disabled

1 - Enabled

Function:

This function allows modifications to be made to the registers without the changes taking effect until the

FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously,

enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.

76543210

PART4 PART3 PART2 PART1 PART0 REV2 REV1 REV0

01101- - -

76543210

CPEN FREEZE DSD/PCM Reserved DAC3_DIS DAC2_DIS DAC1_DIS PDN

00000001

DS670F2 35

CS4365

6.2.3 PCM/DSD Selection (DSD/PCM)

Default = 0

0 - PCM

1 - DSD

Function:

This function selects DSD or PCM Mode. The appropriate data and clocks should be present before

changing modes, or else MUTE should be selected.

6.2.4 DAC Pair Disable (DACx_DIS)

Default = 0

0 - DAC Pair x Enabled

1 - DAC Pair x Disabled

Function:

When the bit is set, the respective DAC channel pair (AOUTAx and AOUTBx) will remain in a reset state.

It is advised that changes to these bits be made while the power-down (PDN) bit is enabled to eliminate

the possibility of audible artifacts.

6.2.5 Power Down (PDN)

Default = 1

0 - Disabled

1 - Enabled

Function:

The entire device will enter a low-power state when this function is enabled, and the contents of the control

registers are re tained in this mode. The power- down bit defaults to ‘enabled’ on power-up and must be

disabled before normal operation in Control Port Mode can occur.

6.3 PCM Control (address 03h)

6.3.1 Digital Interface Format (DIF)

Default = 0000 - Format 0 (Left-Justified, up to 24-bit data)

Function:

These bits select the interface format for the serial audio input. The DSD/PCM bit determines whether

PCM or DSD Mode is selected.

The required relationship between the Left/Right clock, seri al clock and serial data is defined by the Digital

Interface Fo r ma t an d the op tio ns are det aile d in Figures 8 through 15.

Note: While in PCM Mode, the DIF bits should only be changed when the power-down (PDN) bit is set

to ensure proper switching from one mode to another.

76543210

DIF3 DIF2 DIF1 DIF0 Reserved Reserved FM1 FM0

00000011

36 DS670F2

CS4365

6.3.2 Functional Mode (FM)

Default = 11

00 - Single-Speed Mode (4 to 50 kHz sample rates)

01 - Double-Speed Mode (50 to 100 kHz sample rates)

10 - Quad-Speed Mode (100 to 200 kHz sample rates)

11 - Auto Speed Mode detect (32 kHz to 200 kHz sample rates)

Function:

Selects the required range of input sample rates or Auto Speed Mode.

6.4 D SD Control (address 04h)

6.4.1 DSD Mode Digital Interface Format (DSD_DIF)

Default = 000 - Format 0 (64x oversampled DSD data with a 4x MCLK to DSD data rate)

Function:

The relationship b etween the oversamplin g ratio of the DSD audio data and the required Master clock-to-

DSD-data rate is defined by the Digital Interface Format pins.

The DSD/PCM bit determines whether PCM or DSD Mode is selected.

DIF3 DIF2 DIF1 DIF0 DESCRIPTION FORMAT

0 0 0 0 Left-Justified, up to 24-bit data 0

0 0 0 1 I²S, up to 24-bit data 1

0 0 1 0 Right-Justified, 16-bit data 2

0 0 1 1 Right-Justified, 24-bit data 3

0 1 0 0 Right-Justified, 20-bit data 4

0 1 0 1 Right-Justified, 18-bit data 5

1000

One-Line Mode 1, 24-bit Data 8

1001

One-Line Mode 2, 20-bit Data 9

X X X X All other combinations are Reserved

Table 7. Dig ital Interface Formats - PCM Mode

765 4 3 2 1 0

DSD_DIF2 DSD_DIF1 DSD_DIF0 DIR_DSD STATIC_DSD INVALID_DSD DSD_PM_MD DSD_PM_EN

000 0 1 1 0 0

DIF2 DIF1 DIFO DESCRIPTION

0 0 0 64x oversamp l e d DSD data with a 4x MCLK to DSD dat a rate

0 0 1 64x oversamp l e d DSD data with a 6x MCLK to DSD dat a rate

0 1 0 64x oversamp l e d DSD data with a 8x MCLK to DSD dat a rate

0 1 1 64x oversampl ed DSD data with a 12x MCLK to DSD data rate

1 0 0 128x oversampled DSD data with a 2x MCLK to DSD data rate

1 0 1 128x oversampled DSD data with a 3x MCLK to DSD data rate

1 1 0 128x oversampled DSD data with a 4x MCLK to DSD data rate

1 1 1 128x oversampled DSD data with a 6x MCLK to DSD data rate

Table 8. Digital Interface Formats - DSD Mode

DS670F2 37

CS4365

6.4.2 Direct DSD Conversion (DIR_DSD)

Function:

When set to 0 (default), DSD input data is sent to the DSD processor for filter ing and volume control func-

tions.

When set to 1, DSD input data is sent directly to the switche d capacitor DACs for a pure DSD co nversion.

In this mode, the full-scale DSD and PCM levels will not be matched (see Section ), the dynamic range

performance may be reduced, the volume control is inactive, and the 50 kHz low pass filter is not available

(see Section for filter specifications).

6.4.3 Static DSD Detect (STATIC_DSD)

Function:

When set to 1 (default), the DSD processor checks for 28 consecutive zeroes or ones and, if detected,

sends a mute signal to the DACs. The MUTEC pins will eventually go active according to the DAMUTE

When set to 0, this function is disabled.

6.4.4 Invalid DSD Detect (INVALID_DSD)

Function:

When set to 1, the DSD processor checks for greater than 24 out of 28 bits of the same value and, if de-

tected, will attenuate the data sent to the DACs. The MUTEC pins go active according to the DAMUTE

When set to 0 (default), this function is disabled.

6.4.5 DSD Phase Modulation Mode Select (DSD_PM_MODE)

Function:

When set to 0 (default), the 128Fs (BCKA) clock should be input to DSD_SCLK for Phase Modulation

Mode. (See Figure 18 on page 27)

When set to 1, the 64Fs (BCKD) clock should be input to DSD_SCLK for Phase Modulation Mode.

6.4.6 DSD Phase Modulation Mode Enable (DSD_PM_EN)

Function:

When set to 1, DSD phase mod ulation input mod e is enabled, and the DSD_PM_MODE bit should be set

accordingly.

When set to 0 (default), this function is disabled (DSD normal mode).

38 DS670F2

CS4365

6.5 Filter Control (address 05h)

6.5.1 Interpolation Filter Select (FILT_SEL)

Function:

When set to 0 (default), the Interpolation Filter has a fast roll-off.

When set to 1, the Interpolation Filter has a slow roll-off.

The specifications for each filter can b e found in the Analo g characteristics table, and r esponse plots can

be found in Figures 24 to 47.

6.6 Invert Control (address 06h)

6.6.1 Invert Signal Po larity (Inv_xx)

Function:

When set to 1, this bit inverts the signal polarity of channel xx.

When set to 0 (default), this function is disabled.

6.7 Group Control (address 07h)

6.7.1 Mute Pin Control (MUTEC1, MUTEC0)

Default = 00

00 - Six mute control signals

01, 10 - One mute control signal

11 - Three mute control signals

Function:

Selects how the internal mute control signals are routed to the MUTEC1 through MUTEC6 pins. When

set to ‘00’, there is one mute control signal for each channel: AOUT1A on MUTEC1, AOUT1B on

MUTEC2, etc. When set to ‘01’ or ‘10’, there is a single mute control signal on the MUTEC1 pin. When

set to ‘11’, there are three mute control signals, one for each stereo pair: AOUT1A and AOUT1B on

MUTEC1, AOUT2A and AOUT2B on MUTEC2, and AOUT3A and AOUT3B on MUTEC3.

76543210

Reserved Reserved Reserved Reserved Reserved Reserved Reserved FILT_SEL

00000000

76543210

Reserved Reserved INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1

00000000

76543210

MUTEC1 MUTEC0 Reserved P1_A=B P2_A=B P3_A=B Reserved SNGLVOL

00000000

DS670F2 39

CS4365

6.7.2 Channel A Vo lume = Channel B Volume (Px_A=B)

Default = 0

0 - Disabled

1 - Enabled

Function:

The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Vol-

ume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are deter-

mined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes

are ignored when this function is enabled.

6.7.3 Single Volume Control (SNGLVOL)

Default = 0

0 - Disabled

1 - Enabled

Function:

The individual channel volume levels are independently controlled by their respective Volume Control

Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel Volume

Control Byte, and the other Volume Control Bytes are igno red when this function is enabled.

6.8 Ramp and Mute (address 08h)

6.8.1 Soft Ramp and Zero Cross CONTROL (SZC)

Default = 10

00 - Immediate Change

01 - Zero Cross

10 - Soft Ramp

11 - Soft Ramp on Zero Crossings

Function:

Immediate Change

When Immediate Change is selected, all level changes will take effect immediately in one step.

Zero Cross

Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur

on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a tim-

eout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal

does not encounter a zero crossing. The zero cross function is independently monitored and implemented

for each channel.

Soft Ramp

Soft Ramp allows level changes, bo th muting and attenuation, to be implemented by incrementally ra mp-

ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.

76543210

SZC1 SZC0 RMP_UP RMP_DN PAMUTE DAMUTE MUTE_P1 MUTE_P0

10111100

40 DS670F2

CS4365

Soft Ramp on Zero Crossing

Soft Ramp and Zero Cross Enable dictates that signal-level changes, either by attenuation changes or

muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change

will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz

sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently

monitored and implemented for each channel.

6.8.2 Soft Volume Ramp-Up after Error (RMP_UP)

Function:

An un-mute will be performed after executing an LRCK/MCLK ratio change or error, and after changing

the Functional Mode.

When set to 1 (default), this unmute is effected, similar to attenuation changes, by the Soft and Zero Cross

bits in the Volume and Mixing Control register.

When set to 0, an immediate unmute is performed in these instances.

Note: For best results, it is recommende d that this feature be used in conjunction with the RMP_DN bit.

6.8.3 Soft Ramp-Down before Filter Mode Change (RMP_DN)

Function:

If either the FILT_SEL or DEM bits are changed the DAC will stop conversion for a period of time to

change its filter values. This bit selects how the data is effected prior to and after the change of the filter

values.

When set to 1 (default), a mute will be performed prior to executing a filter mode change and an un-mute

will be performed after executing the filter mode change. This mute and un-mute are effected, similar to

attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register.

When set to 0, an immediate mute is performed prior to executing a filter mode change.

Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.

6.8.4 PCM Auto-Mute (PAMUTE)

Function:

When set to 1 (default), the Digital-to-Analog converter output will mute following the reception of 8192

consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. De-

tection and muting is done independently for each channel. The quiescent voltage on the output will be

retained and the Mute Control pin will go active during the mute period.

When set to 0, this function is disabled.

DS670F2 41

CS4365

6.8.5 DSD Auto-Mute (DAMUTE)

Function:

When set to 1 (default), the Digital-to-Analog converter output will mute following the reception of 256 re-

peated 8-bit DSD mute patterns (as defined in the SACD specification).

A single bit not fitting the repeated mute pattern (mentioned above) will release the mute. Detection and

muting is done independently for each channel. The quiescent voltage on the output will be retained, and

the Mute Control pin will go active during the mute period.

6.8.6 MUTE Polarity and DETECT (MUTEP1:0)

Default = 00

00 - Auto polarity detect, selected from MUTEC1 pin

01 - Reserved

10 - Active low mute polarity

11 - Active high mute polarity

Function:

Auto mute polarity detect (00)

See Section 4.11 “The MUT EC Ou tp ut s” on pag e 29 for description.

Active low mute polarity (10)

When RST is low, the outputs are high impedance and will need to be biased active. Once reset has been

released and after this bit is set, the MUTEC output pins will be active low polarity.

Active high mute polarity (11)

At reset time, the outputs are high impedance and will need to be biased active. Once reset has been

released and after this bit is set, the MUTEC output pins will be active high polarity.

6.9 Mute Control (address 09h)

6.9.1 Mute (MUTE_xx)

Default = 0

0 - Disabled

1 - Enabled

Function:

The Digital-to-Analog converter output will mute when enabled. The qu iescent voltage on the output will

be retained. The mutin g function is affected, simila rly to attenuation chang es, by the Soft and Zero Cross

bits. The MUTE pins will go active during the mute period according to the MUTEC bits.

76543210

Reserved Reserved MUTE_B3 MUTE_A3 MUTE_B2 MUTE_A2 MUTE_B1 MUTE_A1

00000000

42 DS670F2

CS4365

6.10 Mixing Control (address 0Ah, 0Dh, 10h, 13h)

6.10.1 De-Emphasis Control (PX_DEM1:0)

Default = 00

00 - Disabled

01 - 44.1 kHz

10 - 48 kHz

11 - 32 kHz

Function:

Selects the appropriate digital filter to maintain the standard 15 μs/50 μs digital de-emphasis filter re-

sponse at 32, 44.1 or 48 kHz sample rates. (see Figure 16)

De-emphasis is only available in Single-Speed Mode.

6.10.2 ATAPI Channel Mixing and Muting (ATAPI)

Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo)

Function:

The CS4365 implements the channel-mixing functions of the ATAPI CD-ROM specification. The ATAPI

functions are applied per A-B pair. Refer to Table 9 and Figure 17 fo r additional information.

76543210

Reserved Px_DEM1 Px_DEM0 PxATAPI4 PxATAPI3 PxATAPI2 PxATAPI1 PxATAPI0

00001001

ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTAx AOUTBx

0 0 0 0 0 MUTE MUTE

00001 MUTE bR

00010 MUTE bL

0 0 0 1 1 MUTE b[(L+R)/2]

00100 aR MUTE

00101 aR bR

00110 aR bL

00111 aR b[(L+R)/2]

01000 aL MUTE

01001 aL bR

01010 aL bL

01011 aL b[(L+R)/2]

0 1 1 0 0 a[(L+R)/2] MUTE

01101 a[(L+R)/2] bR

01110 a[(L+R)/2] bL

0 1 1 1 1 a[(L+R)/2] b[(L+R)/2]

1 0 0 0 0 MUTE MUTE

10001 MUTE bR

10010 MUTE bL

Table 9. ATAPI Decode Table

DS670F2 43

CS4365

6.11 Volume Control (address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h)

These six registers provide individual volume and mute control for each of the six channels.

The values for “xx” in the bit fields above are as follows:

6.11.1 Digital Volume Control (xx_VOL7:0)

Default = 00h (0 dB)

Function:

The Digital Volume Control registers allow independent control of the signal levels in 1/2 dB increments

from 0 to -127.5 dB. Volume settings are decoded as shown in Table 10. The vo lume changes are im ple-

mented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. Note that

the values in the volume setting column in Table 10 are approximate. The actual attenuation is determined

by taking the decimal value of the volume register and multiplying by 6.02/12.

1 0 0 1 1 MUTE [(bL+aR)/2]

10100 aR MUTE

10101 aR bR

10110 aR bL

1 0 1 1 1 aR [(aL+bR)/2]

11000 aL MUTE

11001 aL bR

11010 aL bL

1 1 0 1 1 aL [(aL+bR)/2]

1 1 1 0 0 [(aL+bR)/2] MUTE

1 1 1 0 1 [(aL+bR)/2] bR

1 1 1 1 0 [(bL+aR)/2] bL

1 1 1 1 1 [(aL+bR)/2] [(aL+bR)/2]

76543210

xx_VOL7 xx_VOL6 xx_VOL5 xx_VOL4 xx_VOL3 xx_VOL2 xx_VOL1 xx_VOL0

00000000

Binary Code Decimal Value Volume Setting

00000000 0 0 dB

00000001 1 -0.5 dB

00000110 6 -3.0 dB

11111111 255 -127.5 dB

Table 10. Example Digital Volume Settings

ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTAx AOUTBx

Table 9. ATAPI Decode Table

44 DS670F2

CS4365

6.12 PCM Clock Mode (address 16h)

6.12.1 Master Clock DIVIDE by 2 ENABLE (MCLKDIV)

Function:

When set to 1, the M CLKDIV bit enable s a circuit whic h divides the externally applied MCLK signal by 2

prior to all other internal circuitry.

When set to 0 (default), MCLK is unchanged.

76543210

Reserved Reserved MCLKDIV Reserved Reserved Reserved Reserved Reserved

00000000

DS670F2 45

CS4365

7. FILTER PLOTS

0.4 0.5 0.6 0.7 0.8 0.9

−120

−100

−80

−60

−40

−20

Frequency(normalized to Fs)

Amplitude (dB)

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.

−120

−100

−80

−60

−40

−20

Frequency(normalized to Fs)

Amplitude (dB)

Figure 24. Single-Speed (fast) Stopband Rejectio n Figure 25. Single-Spee d (fast) Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

Frequency(normalized to Fs)

Amplitude (dB)

00.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45

−0.02

−0.015

−0.01

−0.005

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 26. Single-Speed (fast) Transition Band (detail) Figure 27. Single-Speed (fast) Passband Ripple

0.4 0.5 0.6 0.7 0.8 0.9

−120

−100

−80

−60

−40

−20

Frequency(normalized to Fs)

Amplitude (dB)

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.

−120

−100

−80

−60

−40

−20

Frequency(normalized to Fs)

Amplitude (dB)

Figure 28. Single-Speed (slow) Stopband Reject ion Figure 29. Single-Speed (slow) Transition Band

46 DS670F2

CS4365

00.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45

−0.02

−0.015

−0.01

−0.005

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

Frequency(normalized to Fs)

Amplitude (dB)

Figure 30. Single-Speed (slow) Transition Band (detail) Figure 31. Single-Speed (slow) Passband Ripple

0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 32. Double-Spee d (fas t) Stop ba n d Rejec t ion F igure 33. Double-Spee d (fast) Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 34. Double-Speed (fast) Tran sitio n Ban d (detail) Figure 35. Double-Speed (fast) Passband Ripple

DS670F2 47

CS4365

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.2 0.3 0.4 0.5 0.6 0.7 0.

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 36. Double-Speed (slow) Stopband Rejection Figure 37. Double-Speed (slow) Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.3

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 38. Doub le-Speed (slow) Transition Ba nd (detail) Figure 39. Double-Speed (slow) Passband Ripple

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.2 0.3 0.4 0.5 0.6 0.7 0.

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 40. Quad-Speed (fast) Stopband Rejection Figure 41. Quad-Speed (fast) Transitio n Ban d

48 DS670F2

CS4365

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.2

0.2

0.15

0.1

0.05

0.1

0.15

0.2

Frequency(normalized to Fs)

Amplitude (dB)

Figure 42. Quad-Speed (fast) Transition Band (detail) Figure 43. Quad-Speed (fast) Passband Ripple

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 44. Quad-Speed (slow) Stopband Rejection Figure 45. Quad-Speed (slow) Transition Band

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5

Frequency(normalized to Fs)

Amplitude (dB)

0 0.02 0.04 0.06 0.08 0.1 0.1

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 46. Quad-Speed (slow) Transition Ban d (detail) Figure 47. Quad-Speed (slow) Passband Ripple

DS670F2 49

CS4365

8. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the sig nal to the rms sum of all other spectral components over the specified

bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full-scale rms va lue of the signal to the rms sum of all other spectr al components over the

specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified ba ndwidth

made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measure-

ment to full scale. Th is tech n iqu e en su re s that the distortion comp o ne n ts ar e be low the no ise level and

do not affect the measurement. This measurement technique has b een accepted by the Au dio Engine er-

ing Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's

output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in

decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain DriftThe change in gain value with temperature. Units in ppm/°C.

50 DS670F2

CS4365

9. PACKAGE DIMENSIONS

INCHES MILLIMETERS

DIM MIN NOM MAX MIN NOM MAX

A --- 0.055 0.063 --- 1.40 1.60

A1 0.002 0.004 0.006 0.05 0.10 0.15

B 0.007 0.009 0.011 0.17 0.22 0.27

D 0.343 0.354 0.366 8.70 9.0 BSC 9.30

D1 0.272 0.28 0.280 6.90 7.0 BSC 7.10

E 0.343 0.354 0.366 8.70 9.0 BSC 9.30

E1 0.272 0.28 0.280 6.90 7.0 BSC 7.10

e* 0.016 0.020 0.024 0.40 0.50 BSC 0.60

L 0.018 0.24 0.030 0.45 0.60 0.75

µ 0.000° 4° 7.000° 0.00° 4° 7.00°

* Nominal pin pitch is 0.50 mm

*Controlling dimension is mm.

*JEDEC Designation: MS022

48L LQFP PACKAGE DRAWING

∝

DS670F2 51
CS4365
10.ORDERING INFORMATION
11.REFERENCES
1. How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters, by Steven Harris. Paper
presented at the 93rd Convention of the Audio Engineering Society, October 1992.
2. CDB4365 data sheet, available at http://www.cirrus.com.
3. Design Notes for a 2-Pole Filter with Differential Input, by Steven Green. Cirrus Logic Application Note AN48
4. The I²C-Bus Specification: Version 2.0, Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com.
12.REVISION HISTORY 
Product Description Package Pb-Free Grade Temp Range Cont ainer Order #
CS4365 114 dB, 192 kHz 6-chan-
nel D/A Converter 48-pin 
LQFP YES Commercial -40°C to +85°C Tray CS4365-CQZ
Tape & Reel CS4365-CQZR
Automotive -40°C to +105°C Tray CS4365-DQZ 
Tape & Reel CS4365-DQZR 
CDB4365  CS4365 Evaluation Board  - - - - CDB4365
Release Changes
PP3
Updated Guaranteed Operational Temperature Range in “Recommended Operating Conditions” on page 8.
Updated VA, VLC, and VLS current cunsumption specs
Updated Fullscale outp ut level
Updated Dynamic perforamnce limits.
Removed VOH specification
Updated VOL specification
F1
Updated “Recommende d Operating Conditions” on page 8
Updated “DAC Analog Characteristics - Commercial (-CQZ)” on page 9
Updated “DAC Analog Characteristics - Automotive (-DQZ)” on page 10
Updated “Power and Thermal Characteristics” on page 11
Updated Legal Information on page 52
Removed TDM Mode functionality
F2
Updated “DAC Pair Disable (DACx_DIS)” on page 35
Updated “Digital Interface Format (DIF)” on page 35
Added PCM mode format changeable in reset only to “Mode Select” on page 22
Updated Package Thermal Resistance in “Power and Thermal Characteristics” on page 11

52 DS670F2

CS4365

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative.

To find the one near e st to yo u, go to www.cirrus.com

IMPORTANT NOTICE

Cirrus Logic, Inc. and its sub sidiaries ("Cirrus") believe that the information con tained in this document is accurate and reliable. However, the information is subject

to chang e withou t noti ce and is provide d "AS IS" without warrant y of any kind (ex press or implie d). Cust omers are advised to obtain the latest version of relevant

information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditio ns of sale

supplied at the time of order acknowled gment, including th ose pertaining to warra nty, indemnification, and limitation of liability. No respons ibility is a ssumed by Cirrus

for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of pate nts or other righ ts of thir d

parties. This docu m ent is the prop erty of Cirrus and by fu rnishing this information, Cirrus grants no license, express or implied under any paten ts, mask work rights,

copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained he rein and gives con-

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does not extend to othe r co pying such as copying for ge ne ral distribution, adver tising or pro m o tion al p ur poses, or for creating any wo rk for resa le.

CERTAIN APPLICAT IONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL I NJU RY, OR SEVERE P ROP-

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IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT-

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FITNESS FOR PARTICULAR PURPOSE, WITH REGARD T O ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF TH E CUSTOMER OR CUSTOM-

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INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRI BUTORS AND OTHER AGENTS FROM ANY AND ALL LI ABILI TY, INCLUDING AT-

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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks

or service marks of their resp ective owners.

I²C is a regis t er ed trademar k o f P h ilips Semiconduc to r.

SPI is a trademark of Mo toro la , Inc.