M41T50Q6F - STMicroelectronics - Datasheet.Directory

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PRELIMINARY DATA

January 2005

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notic e.

M41T50

Seri al Acc ess Digit al In put

Real-Time Clock with Alarms

FEATURES SUMMARY

■TIMEKEEPING DOWN TO 1.3V

■1.7V TO 3.6V I 2C BUS OPER ATING

VOLTAGE

■OP ERAT ES FROM 50Hz OR 60Hz DIGITAL

C LOC K SI GNA L

■COUNTERS FOR SECONDS, MINUTES,

HOURS, DAY, DATE, MONT H, YEAR, AND

CENTURY

■SERIA L INT ERFACE SU PPORTS I 2C BUS

(400kHz)

■PROGRAMMABLE ALARM AN D

INTERRUPT FUNCTION

■1Hz SQUARE WAVE OUTPUT

■LOW OPERATING CURRENT OF 350µ A

■AUTOMAT IC L EAP YEAR C OMP EN SATION

■SOFTWARE PROGRAMMABLE OUTPUT

(OUT)

■OP ERAT ING TEMPER ATURE OF –40 TO

85°C

■LEAD-FREE 16-PIN QFN PACKAGE

Figure 1. Package

QFN16 (Q)

M41T50

2/23

TABLE OF CONTENTS

FEATUR ES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUM MARY DESCRIPT ION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logi c Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signa l Na mes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. 16-pi n QFN Conne ctions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2-Wire Bus Chara cteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Stop data transfe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Data Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Acknowl edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5. S erial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 6. A c knowledg eme nt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 7. Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 8. RE A D Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 9. Alternative READ Mod e Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

WRITE M ode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 10.WRITE Mode Seq uence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CLOCK O PERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Digital Cloc k Inp ut. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

Figure 11.Alarm Interrupt Reset Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 3. Alarm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Sq uare Wave Outp ut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Centur y Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Initial Powe r-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 4. Initial Power-on Default Value s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5. Century Bits Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 6. Absolute Maximum Rati ngs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DC AND AC PARAM ETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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M41T50

Table 7. Operating a nd AC Measurement Cond itions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 13.Bus Timing Requiremen ts Sequenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 10. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

PACKAGE MECHANICAL INFORMATIO N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 14.QFN16 – 16-lead, Quad, Flat Package, No Lead, 3 x3mm body size, Outline . . . . . . . . 19

Table 11. QF N16 – 16-lead, Quad, Flat Packag e, No Lead, 3x3mm body size, Mecha nical Data. 20

Figure 15.QFN16 – 16-lead, Quad, Flat Package, No Lead, 3 x3mm body size, Footprint . . . . . . . 20

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12. Orderi ng Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

REVISION HISTO RY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 13. Document Revision Histo ry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

M41T50

4/23

S UM MARY DESCRIPTION

The M41T50 Serial Access TIMEKEEPER® is a

low power Serial RT C that does not require a crys-

tal. The clock operates from a digital clock input

pin at 50Hz or 60Hz. Eight registers (see Table

2., page 12) are used for the clock/calend ar f unc-

tion and are configured in binary coded decimal

(BCD) format. An additional 8 registers provide

status/control of Alarm, Square Wave (1Hz), and

50Hz or 60Hz digital clock frequency selection

functions. Addresse s and data are transferred se-

rially via a two line, bi-directional I2C in ter fac e. The

built-in address register is incremented automati-

cally after e ach WRITE or READ data byte.

Functions available to the user include a time-of-

day clock/calendar, Alarm interrupts, and Square

Wave output. The eight clock address locations

contain the century, year, month, d ate, day, hour,

minute, and seconds in 24-hour BCD format. Cor-

rections for 28-, 29- (leap year), 30- and 31-day

months are made automat ically.

The M41T5 0 is supplied in a 16-pin QFN.

Figure 2. Logic Diagram

Note: 1. Ope n Drain on l y.

2. Defau lts to p ush-p ul l (SQ W d isa bled ) on po we r- up. Ma y

also be programm ed to be Open Drain.

Table 1. Signal Names

Figu re 3. 16- pi n QF N C onn e ct i on s

Note: 1. Ope n Drain on l y.

2. Defau lts to p ush- pull (SQ W d isa bled ) on po we r- up. May

also be programm ed to be Open Drain.

SCL

VCC

M41T50

VSS

SDA

IRQ/OUT(1)

SQW (1Hz)(2)

CLKIN

AI09110

CLKIN Digital Clock Input (50Hz or 60Hz)

SDA Serial Data Input/Output

SCL Serial Clock Input

IRQ/OUT Interrupt or OUT Output (Open

Drain)

SQW

(1Hz) Square Wave Output (Open Drain

or Push-pull)

VCC Supply Vo ltage

VSS Ground

5678

CLKIN

SQW (1Hz)(2)

VSS

VCC

SCL

SDA

IRQ/OUT(1)

AI09111

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M41T50

Figu re 4. Blo ck Diagram

Note: 1. May b e configur ed as either push- pul l or open drain.

2. Open drain only .

AI09112

SECONDS

ALARM

SERIAL

BUS

INTERFACE

DIVIDER

CONTROL

LOGIC

ADDRESS

MINUTES

HOURS

DAY

DATE

CENTURY/

MONTH

YEAR

CLKIN

VCC

VSS

SCL

SDA

1 Hz

IRQ/OUT(2)

AFE

OUT

SQWE SQW(1)

M41T50

6/23

OPERATION

The M41T 50 clock operates as a s lave device on

the serial bus . Access is obtained by implementing

a start condition f ollowed by the correc t slave ad-

dress (D0h). The 16 bytes contained i n the device

can then be accessed sequentially in t he foll owing

order:

1. Reserved0 Register

2. Seconds Register

3. Min utes Register

4. Hours Register

5. Day Register

6. D ate Register

7. Cent ury/Month Register

8. Yea r Register

9. Out Register

10. Reserved1 Register

11 - 15. Ala rm Registers

16. Fl ags Register

2-Wire Bus Characteristics

The bus is intended for communication between

different ICs. It consists of two lines: a bi-direction-

al data signal (SDA) and a clock signal (SCL).

Both the SDA and SCL lines mus t be connected to

a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

– D ata transfer may be initiated only when the

bus is not bus y.

– During data transfer, the data line must remain

stable whenever the clock line is High.

– Changes in the data line, while t he clock line is

H igh, will be inte rpreted as control signals.

Accordingly, the following bus conditions have

been defined:

Bus not busy. Both data and clock lines remain

High.

Start data transfer . A change in the state of the

data line, from high to Low, while the clock is High,

defines the START condi tion.

Stop data transfer. A change in the state of the

data line, from Low to High, while the clock is High,

defines the STOP condition .

Data Va lid. T he state of the data line rep resents

valid data when after a start condition, the dat a line

is stable for the duration of the high period of the

clock signal. The data on the line may be changed

during the Low period of the clock signal. There is

one clock pulse per bit of data.

Each data transfer is initiated with a start condi tion

and terminated with a stop condition. The number

of data bytes transferred between the start and

stop conditions is not limited. The information is

transmitted byte-wide and each rec eiver ack nowl-

edges with a ninth bit .

By definition a dev ice t hat gives o ut a m essag e is

called “transmitter,” the receiving dev ice that gets

the message is called “receiver.” The device that

controls the message is called “master.” The de-

vices that are controlled by th e ma ster are called

“slaves.”

Acknowledge. E ac h byte of eig ht bits is foll owed

by one Acknowledge B it. Thi s Acknowledge Bit is

a low level put on t he bus by the receiver whereas

the master generates an extra ac knowled ge relat-

ed clock pulse. A slave receiver which is ad-

dressed is obliged to generate an acknowledge

after the reception of each byte that has been

clocked out of the slave transmitter.

The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse

in such a way that the SDA line is a stable Low dur-

ing the High period of the acknowledge related

clock pulse. Of course, setup and hold times mus t

be taken int o account. A master recei ver must sig-

nal an end of data to the slave transmitter by not

generating an acknowledge on the last byte that

has been clocked out of the slave. In this case the

transmitter must l eave the data l ine High to enable

the mast er to generate the S TOP condition.

7/23

M41T50

Figure 5. Serial Bus Data Transfer Sequen ce

Figure 6. Acknowledgement Sequence

AI00587

DATA

CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION CHANGE OF

DATA ALLOWED STOP

CONDITION

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCL FROM

MASTER

START CLOCK PULSE FOR

ACKNOWLEDGEMENT

12 89

MSB LSB

M41T50

8/23

READ Mode

In this mode the master reads the M41T50 slave

after setting the slave address (see Figure

8., page 9). Following the WRITE Mode Control

Bit (R/W=0) and the Acknowledge Bit, the word

address 'An' is written to the on-chip address

pointer. Next the START condition and slave ad-

dress are repeated followed by the READ Mode

Control Bit (R/W=1). At this point the master trans-

mitter becomes the master receiver. The data byte

which was addressed will be transmitted and the

master receiver will send an Acknowledge Bit to

the slave transmitter. The address pointer is only

incremented on reception of an Acknowledge

Clock. The M41T50 slave transmitter will now

place the data byte at address An+1 on the bus,

the master receiver reads and acknowledges the

new byte and the ad dress p ointer is incremented

to “An+2.”

This cycle of reading consecutive addresses will

continue until the master receiver se nds a STOP

condition to the slave transmitter.

The system-to-user transfer of clock data will be

halted whenever the address bei ng read is a clock

address (00h to 07h). The update will re su me due

to a Stop Condition or when the pointer incr ements

to any non-clock address (08h-0Fh).

Note: This is true bot h in READ Mode and WRITE

Mode.

An alternate READ Mode may al so be implement-

ed whereby the master reads the M41T50 slave

without first w ri tin g to the (volatile) addres s point-

er. The first address that is read is the last one

stored in the p ointer (see Figure 9. , page 9).

Figure 7. Slave Address Locat ion

AI00602

R/W

SLAVE ADDRESS

START A

0100011

MSB

LSB

9/23

M41T50

Figure 8. READ Mode Sequence

Figure 9. Alternative RE AD Mode Sequence

WRITE Mod e

In this mode the master transmitter transmits to

the M41T50 slav e receiver. Bus protocol is shown

in Fig ure 10., page 10. Following the STA RT con-

dition and slave address, a logic '0' (R/W=0) is

placed on the bus and indicates to the addressed

dev ic e t h at word addre s s “ An ” w ill follo w a nd is t o

be written to the on-chip addres s pointer. The data

word to be written to the memory is strobed in nex t

and the internal address pointer is increme nted to

the next address location on the reception of an

acknowledge clock. The M41T50 slave receiver

will send an acknowledge clock to the master

transmitter after i t has received the slave address

see Figure 7., page 8 and again after it has re-

ceived the word address and each data byte.

AI00899

BUS ACTIVITY:

ACK

NO ACK STOP

START

SDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

START

R/W

SLAVE

ADDRESS

ACK

AI00895

BUS ACTIVITY:

ACK

NO ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

SLAVE

ADDRESS

M41T50

10/23

Figure 10. WRI TE Mode Se qu e nce

AI00591

BUS ACTIVITY:

ACK

ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

11/23

M41T50

C LOCK OP ERATION

The eight byte clock register (see Table

2., page 12) is used to both set the clock and to

read the date and time from the clock, in a binary

coded d ecimal f ormat. Reserv ed0, S econds , M in-

utes, and Hours are contained within the first four

registers.

Bits D0 through D2 of Register 04h contain the

Day (day of week). Registers 05h, 06h, and 07h

contain the Date (day of month), Month, and

Years. Bit D 7 of Re gister 01h contains the STOP

Bit (S T). Setting t his bi t to a '1' will cause the oscil-

lator to sto p. When rese t to a '0' the oscillator re-

starts within one second (typical).

Bits D6 and D7 of Clock Register 06h (Century/

Month Register) contain the CENTURY Bit 0

(CB0) and CENTURY Bit 1 (CB1).

Bit D6 of Register 0Ch (Alar m Hour Register) con-

tains the SQW Open Drain Bit (SQWOD). When

this bit is set to '1,' the Square Wave output will be-

come an open drain output and require a pull-up

resistor.

Note: A WRITE to ANY location within the first

eight bytes of the clo ck regi ster (00h -07h), inc lud-

ing the 60Hz Bit and CB0-CB1 Bits wi ll result in an

update of the system clock and a reset of the divid-

er chain. This could result in an inadvertent

change of the current time. These non-clock rel at-

ed bits should be written prior to setting the clock,

and remain unchanged until such time as a new

clock time is also writte n.

The eight Clock Registers may be read one byte at

a time, or in a sequent ial block. Provision has been

made to assure that a clock update does not occur

while any of the eight clock addresses are being

read. If a c lock address is being read, an update of

the clock registers will be halted. T his will prevent

a transition of data duri ng the RE AD.

Digi tal Cl ock Input

The M41T50 requires an external square wave

clock source of 50Hz or 60Hz (45% to 55% duty

cycle) for the clock function. Bit D7 (60Hz bit) of

tween a 50Hz (60Hz Bit = '0') or a 60Hz (60Hz Bit

= '1') clock input frequency signal. The 60Hz Bit

defaults to '1' on power-up.

TIMEKEEPER® Registers

The M41T50 offers 16 internal registers which

contain Clock, Alarm, and Flag Registers. The

Clock registers are memory locations which con-

tain external (user accessible) and internal copies

of the data (usually referred to as BiPORT™ TIME-

KEEPER cells). T he external copies are indepen-

dent of internal functions except that they are

updated periodically by the simultaneous tran sfer

of the incremented internal copy. The internal di-

vider (or clock) chain will be reset upon the com-

pletion of a WRITE to any clock address (00h to

07h).

The system-to-user transfer of clock data will be

halted whenever the address bei ng read is a clock

address (00h to 07h). The update will resume ei-

ther due to a Stop Condition or when the pointer

increments to a non-clock address.

TIMEKEEPER and Alarm Registers store data in

BCD format.

M41T50

12/23

Table 2. T IME KE EPER® Re gister Map

K eys: 0 = Mus t be set to '0'

AF = A l arm F l ag (Read o nl y)

AFE = Alarm Flag Enable Fla g

CB0-CB1 = Century Bits

OUT = Output level

SQWOD = Sq uare Wave output Open Drai n B i t

RP T 1-RPT5 = A l arm Repeat M ode B i ts

SQWE = Square Wave Enable Bit

ST = Stop Bit

60Hz = 50Hz or 60Hz Sele ct Bit

Addr Function/Range BCD

Format

D7 D6 D5 D4 D3 D2 D1 D0

00h 0 0 0 0 0 0 0 0 Reserved0

01h ST 10 Seconds Seconds Seconds 00-59

02h 0 10 Minutes Minutes Minutes 00-59

03h 0 0 10 Hours Hours (24 Hour Format) Hours 00-23

04h 0 0 0 0 0 Day of Week Day 01-7

05h 60Hz 0 10 Date Date: Day of Month Date 01-31

06h CB1 CB0 0 10M Month Century/

Month 0-3/01-12

07h 10 Years Year Year 00-99

08h OUT 0 0 0 0000Out

09h 0 0 0 0 0 0 0 0 Reserved1

0Ah AFE SQWE 0 Al 10M Alarm Month Al Month 01-12

0Bh RPT4 RPT5 AI 10 Date Alarm Date Al Date 01-31

0Ch RPT3 SQWOD AI 10 Hour Alarm Hour Al Hour 00-23

0Dh RPT2 Alarm 10 Minutes Alarm Minutes Al Min 00-59

0Eh RPT1 Alarm 10 Seconds Alarm Seconds Al Sec 00-59

0Fh0AF000000 Flags

13/23

M41T50

Setting Alarm Clock Registers

Address locations 0Ah-0E h cont ain the alarm se t-

tings. The alarm can be configured to go off at a

prescribed time on a specific month, date, hour,

minute, or second, or repeat every year, month,

day, hour, minute, or second. Bits RPT5–RPT1

put the alarm in the repeat mode of operation. Ta-

ble 3., page 13 shows t he possible configurat ions.

Codes not lis ted in the table def ault to the once per

second m ode to quickly alert the user o f a n incor-

rect alarm s etting.

When the clock information matches the alarm

clock settings based on the match criteria defined

by RPT5–RP T1, the AF (Alarm Flag) is set. If AFE

(Alarm Flag Enable) is also set, the alarm condi-

tion activates the IRQ/OUT pin. To disable the

alarm, write '0' to the Alarm Date Register and to

RPT5–RPT1.

Note: If the address pointer is allowed to incre-

ment to the Flag Registe r ad dress, an alarm con-

dition will not cause the Interrupt/Flag to occur until

the address pointer is moved to a different ad-

dress. It should also be noted that if the last ad-

dress written is the “Alarm Seconds,” the address

pointer will increment to t he F lag address, c ausing

this situation to oc cur.

The IRQ output i s cleared by a READ to the Flags

sequent READ of the Flags Regist er is necessary

to see that the value of the Alarm Flag has been

re set to '0. '

Figure 11. Alarm Interrupt Reset Waveform

Table 3. Alarm Repeat Modes

RPT5 RPT4 RPT3 RPT2 RPT1 Alarm Setting

1 1 1 1 1 Once per Second

1 1 1 1 0 Once per Minute

1 1 1 0 0 Once per Hour

11000 Once per Day

1 0 0 0 0 Once per Month

00000 Once per Year

ALARM FLAG BIT (AF)

0Fh0Eh 00h

HIGH-Z

AI09113

IRQ/OUT

M41T50

14/23

Square Wave Output

The M41T50 offers the user a 1Hz square wave

function which is output on the SQW pin. The

SQW pin can be tu rned on and off under software

control with the Square Wave Enable Bit (SQWE )

located in Register 0Ah.

The SQW out put is programm able as an N-chan-

nel, open d rain o utp ut driver, or a full CM OS ou t-

put driver. The initial power-up default for the S QW

output is disabled, in the full-CMOS (or Push-pull

mode). By setting the Square Wave Open Drain

Bit (SQWOD in address 0Ch) to a '1,' the output

will be configured as an open drain (with IOL as

specified i n Table 9., page 17). When SQWOD is

set to '0,' the output will be configured as full-

CMOS (sink and source c urrent as specified in Ta-

ble 9., page 17).

Note: When configured as Open Drain

(SQWOD = '1'), the SQW pin requi res an external

pull-up resistor.

Century Bits

These two bits will increment in a binary fas hion at

the turn of th e century, and handle a ll leap years

co rrectly. See Table 5., page 1 4 for additional ex-

planation.

Output Driver Pin

When t he AFE Bit is not set to g enerate an inter-

rupt, the IRQ/OUT pin becomes an output driver

that reflects the cont ents of D7 of the Out Register.

In other words, when D7 (OUT Bit) is a '0,' then the

IRQ/OUT pi n will be driven low.

Note: The I RQ/OUT pin is an open drain which re-

quires an external pull-up resistor.

In it ial P o wer - o n D efaul ts

Upon application of power to the device, the regis-

ter bit s will initia lly po we r-on in the stat e i ndic ate d

in Table 4.

Table 4 . Initia l Powe r-on D e f a ult Values

Note: 1. All other control bits power-up in an undetermined state.

Tabl e 5. Century Bits Examples

Note: 1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisi ble by 100. The only exceptions

are those yea rs evenly divisi bl e by 400 (t he year 200 0 was a lea p year, year 2100 is not ).

Condition ST SQWOD OUT AFE SQWE 60Hz

Initial

Power-up(1) 001001

CB0 CB1 Leap Year? Example(1)

00Yes2000

0 1 No 2100

1 0 No 2200

1 1 No 2300

15/23

M41T50

MAXI MUM RAT IN G

Stressing the device above t he rating l isted in t he

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Oper ating sections of this specification i s

not impl ied. Exposure to Absol ute Max imum Ra t-

ing conditions for extended periods may affect de-

vice reliability. Refer also to the

STMicroelectronics S URE P rogram and other rel-

evant quality documents.

Table 6. Absolute Maximum Ratings

Note: 1. Reflow at peak temperature of 260°C (total thermal budg et not to exc eed 245°C for gr eater tha n 30 s econds).

Sym Parameter Value Unit

TSTG Storage Temperature (VCC Off) –55 to 125 °C

VCC Supply Voltage –0.3 to 4.6 V

TSLD(1) Lead Solder Temperature for 10 Seconds 260 °C

VIO Input or Output Vo ltages –0.2 to Vcc+0.2 V

IOOutput Curre nt 20 mA

PDPower Dissipation 1 W

M41T50

16/23

DC AND AC PARAM ETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests pe rf ormed unde r t he Measure-

ment Condition s listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 7. Operating and AC Measurem en t Conditions

Note: 1. 0.2VCC to 0. 9V CC fo r CLKIN input (p in 16)

Figu re 12. AC Measure m e nt I/ O Wa veform

Table 8. Capacitance

Note: 1. Effective c apacitance measured with power supply at 3.6V; samp le d only, not 100% tes ted.

2. At 25° C, f = 1MHz.

3. Outputs deselected .

Parameter M41T50

Supply Voltage (VCC)1.7V to 3.6V

Ambient Operating Temperature (TA)–40 to 85°C

Load Capacitance (CL)50pF

Input Rise and Fall Times ≤ 5ns

Input Pulse Voltages 0.2VCC to 0.8 VCC(1)

Input and Output Timing Ref. Voltages 0.3VCC to 0.7 VCC

AI02568

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Symbol Parameter(1,2) Min Max Unit

CIN Input Capacitance 7 pF

COUT(3) Output Capacitance 10 pF

tLP Low-pass filter input time constant (SDA and SCL) 50 ns

17/23

M41T50

Table 9. DC Characteristics

Note: 1. Vali d for Ambient Operating T em perat ure: TA = –40 to 85°C; VCC = 1. 7V to 3.6V (except wher e noted).

2. CL KI N pin = VSS or VCC.

Symb

ol Parameter Test Condition(1) Min Typ Max Unit

VCC Operating Voltage Clock 1.3 3.6 V

I2C bus (400kHz) 1.7 3.6 V

ICC1 Supply Current SCL = 400kHz

(No load)

VCC = 3.6V 400 µA

VCC = 3.0V 350 µA

VCC = 2.5V 300 µA

VCC = 2.0V 250 µA

ICC2 Supply Current (standby)

SCL = 0Hz

All inputs(2)

≥ VCC – 0.2V

≤ VSS + 0.2V

SQW On

(Open Drain)

3.6V 1.3 µA

3.0V 1.2 µA

2.0V 0.9 µA

SQW Off

3.6V 0.7 µA

3.0V 0.65 µA

2.0V 0.6 µA

VIL Input Low Voltage –0.2 0.3VCC V

VIH Input High Voltage 0.9VCC VCC+0.2 V

VOL Output Low Voltage VCC = 3.6V, IOL = 3.0mA (SDA) 0.4 V

VCC = 3.6V, IOL = 1.0mA (IRQ/OUT, SQW) 0.4 V

VOH Output High Voltage VCC = 3.6V, IOH = –1. 0mA (Push -Pull only) 2.4 V

Pull-up Supply Voltage

(Open Drain) IRQ/OUT, SQW (1Hz) 3.6 V

ILI Input Leakage Current 0V ≤ VIN ≤ VCC(2) ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

M41T50

18/23

Figure 13. Bus Timing Requirements Sequence

Table 10. AC Characteristics

Note: 1. Vali d for Ambient Operating T em perat ure: TA = –40 to 85°C; VCC = 1. 7V to 3.6V (except wher e noted).

2. Tran smi tter must internally provide a hold tim e to bridge the undef ined re gion (300ns max) of the falling edge of SCL.

Sym Parameter(1) Min Typ Max Units

fSCL SCL Clock Frequency 0 400 kHz

tLOW Clock Low Period 1.3 µs

tHIGH Clock High Period 600 ns

tRSDA and SCL Rise Time 300 ns

tFSDA and SCL Fall Time 300 ns

tHD:STA START Condition Hold Time

(after this period the first clock pulse is generated) 600 ns

tSU:STA START Condition Setup Time

(only relevant for a repeated start condition) 600 ns

tSU:DAT(2) Data Setup Time 100 ns

tHD:DAT Data Hold Time 0 µs

tSU:STO STOP Condition Setup Time 600 ns

tBUF Time the bus must be free before a new

transmission can start 1.3 µs

AI00589

SDA

PtSU:STOtSU:STA

tHD:STA

SCL

tSU:DAT

tHD:DAT

tHIGH

tLOW

tHD:STAtBUF

19/23

M41T50

P ACKAGE MECHANICAL INFO RMATION

Figure 14. QF N16 – 16-l ead, Qu ad, Flat Package, No Lead, 3x3mm body size, Outline

No te : Drawi ng is not to scale.

A3 A

ddd

QFN16-A

M41T50

20/23

Table 11. QFN16 – 16-lead, Quad, Flat Package, No Lead, 3x3mm bod y size, Mechanical Data

Figure 15. QFN16 – 16-lead, Quad , Flat Package, No Lead, 3x3mm, Recommend ed Footpr int

Note: S ubstra t e pad should be tied to VSS.

Symb mm inches

Typ Min Max Typ Min Max

A 0.90 0.80 1.00 0.035 0.032 0.039

A1 0.02 0.00 0.05 0.001 0.000 0.002

A3 0.20 – – 0.008 – –

b 0.25 0.18 0.30 0.010 0.007 0.012

D 3.00 2.90 3.10 0.118 0.114 0.122

D2 1.70 1.55 1.80 0.067 0.061 0.071

E 3.00 2.90 3.10 0.118 0.114 0.122

E2 1.70 1.55 1.80 0.067 0.061 0.071

e0.50– –0.020– –

K 0.20 – – 0.008 – –

L 0.40 0.30 0.50 0.016 0.012 0.020

ddd – 0.08 – – 0.003 –

Ch –0.33– –0.013–

N16 16

0.28

1.60

3.55 2.0

AI09126

21/23

M41T50

PART NUMBERING

Table 12. Ordering Information Scheme

For other options, or for more information on any aspec t of this device, please contact the ST Sales Office

nearest you.

Example: M41T 50 Q 6 F

Device Family

M41T

Device Type and Supply Voltage

50 = VCC = 1.7V to 3.6V

Package

Q = QFN16

Temperature Range

6 = –40°C to 85°C

Shipping Method for SOIC

F = Lead-free Package (ECO PACK®), Tape & Reel

M41T50

22/23

REVISION HISTORY

Table 13. Document Revi sion History

M41T50, 41T50, T50, T62, T63, T64, T65, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Ser ial, Ser ial, Serial, Serial, Serial, Serial,

Serial, Serial, Serial, Serial, Serial, Ser ial, Serial, Serial, Se rial, Serial , Seri al, Seria l, Se rial, Serial , Seri al, Seria l, Se rial, Serial, Seri al, Serial, Serial, Serial, Serial, Serial,

Serial, Serial, Serial, Access, Access, A ccess, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access,

Access, Access, Access, Access, Access, A ccess, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Ac-

cess, Access, A ccess, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, A ccess, Access, Access, Access, Access, Access, Access,

Access, Access, Access, A ccess, Access, Access, A ccess, Access, Access, Access, Access, Access, Access, Access, Access, A ccess, Access, Access, Access, Inter-

face, In ter fa ce, Inte rface , In ter fa ce, I nte rf ace , In terfa ce, I nte rf ace, Int erface , In te rfa ce, Int erface , In ter fa ce, I nte r face , In terfa ce, I nte rf ace , Int erfa ce, In te rfa ce, Int erface ,

Inter face , Int erface , In ter fa ce, In te rface, Inte rf ace, Inter face , Int er face , In terfa ce, In ter fa ce, In te rface, Inte rf ace, Inter face , Int er face , In terfa ce, In ter fa ce, In te rface, Inte r-

Interfa ce, In terface, Interface, Interface, Interface, Interface, Interface, C lock, Clock, Clock, Cl ock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clo ck, Clock,

Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock,

RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC,

RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programm ab le,

Progra mmable, Programm able, Progra mmable, Programm able, Progra mmable, Prog rammable, Progra mmable, Prog rammable, Progra mmable, Pr ogra mmabl e, Pro-

grammable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Progra mm a b l e , P r ogra m-

m abl e , Prog ra mm ab le, Pr og ra mma b le, Pr og ra mma bl e, Pro gr am ma ble , Pro gr am m abl e, Pro gr am mab le , Pro gra mm ab le , Pr ogr a mm ab le, Pr og ra mm able, Programmabl e,

Progra mmable, Programm able, Progra mmable, Programm able, Progra mmable, Prog rammable, Progra mmable, Prog rammable, Progra mmable, Pr ogra mmabl e, Pro-

grammabl e, Programmable, Programmab l e, Pr ogra m mab le, Programm able, Prog r ammable, Programmable, Prog r ammable Alarm, Programmable Alarm, Programma-

bl e Al arm , P ro g ram ma ble A lar m , Pr og ra mm ab le A la rm , P ro gr amm ab le Al ar m , Pro g ram ma bl e A lar m, Pr og ra mm ab le A la rm , P ro gr am mab le Al arm , Pr og ra mma bl e A lar m,

Alarm, A larm, A larm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,

Alarm, Alar m, Ala rm, Alar m, Ala rm, Al a rm, Al arm , Alar m, Inter r upt, Int er ru pt, Interr upt, In ter r upt, I nterr u pt, Interr upt, Int er rupt, Inte rrup t, In terr upt , Inte rru pt, Interr upt, In-

terrupt, Interrupt, Interrupt, Interrupt, In terrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrup t, In terrupt, Interrupt, Interrupt, Interrupt, Interr upt, Inter -

rupt, Interrupt, Inter rupt, Interrupt, Interrupt, Interru pt, Interrupt, Interrupt, Interrupt, Inter rupt, Interrupt, Interrupt, Interrupt, Interrup t, In terr upt, Interrupt, Interrupt, Inte rrupt,

Interrupt, Interr upt, Interrupt, Interrupt, Interrupt, Interrupt, Interru pt, Interrupt, In terrupt, Interrupt, Interrup t, Interrupt, Inte rrupt, Interrupt, Interrupt, Interrupt, Inte rrupt, In-

terrupt, Interrupt, Interrupt, Interrupt, In terrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrup t, In terrupt, Interrupt, Interrupt, Interrupt, Interr upt, Inter -

rupt, Interrupt, Inter rupt, Interrupt, Interrupt, Interru pt, Interrupt, Interrupt, Interrupt, Inter rupt, Interrupt, Interrupt, Interrupt, Interrup t, In terr upt, Interrupt, Interrupt, Inte rrupt,

Interrupt, Interr upt, Interrupt, Interrupt, Interrupt, Interrupt, Interru pt, Interrupt, In terrupt, Interrupt, Interrup t, Interrupt, Inte rrupt, Interrupt, Interrupt, Interrupt, Inte rrupt, In-

terrupt, Interrupt, Interrupt, Interrupt, In terrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrup t, In terrupt, Interrupt, Interrupt, Interrupt, Interr upt, Inter -

rupt, Interrupt, Inter rupt, Interrupt, Interrupt, Interru pt, Interrupt, Interrupt, Interrupt, Inter rupt, Interrupt, Interrupt, Interrupt, Interrup t, In terr upt, Interrupt, Interrupt, Inte rrupt,

Interrupt, Interr upt, Interrupt, Interrupt, Interrupt, Interrupt, Interru pt, Interrupt, In terrupt, Interrupt, Interrup t, Interrupt, Inte rrupt, Interrupt, Interrupt, Interrupt, Inte rrupt, In-

terrupt, Interrupt, Interrupt, Interrupt, Inte rru pt, Interrupt, In terrupt, Inter rupt, Interrupt, Interrupt, Interrupt, Inter rupt, Interrupt, Watchdog, W atchdog, Watchdog, Watchdo g,

Watchdog, Watchd og, Watchd og, Watchd og, Watchdog, Watch dog, Wa tchdog, Wa tchdog, Wa tchdog, Watchdog, W atchdog, Watchdog , Watchdog, Watchdog, Watch-

dog, Wat chd og, Wa tch do g, Wat chd og, Wa tch dog , Wat chd og, Watc hdog , Wat chd og, Watc hdog , Wat chdo g, Watc hdog , Wat chdo g, Watc hdog , Wa tc hdog, Watc hdog ,

Watchdog, Watchd og, Watchd og, Watchd og, Watchdog, Watch dog, Wa tchdog, Wa tchdog, Wa tchdog, Watchdog, W atchdog, Watchdog , Watchdog, Watchdog, Watch-

dog, Watch dog , Watc hdog , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Switchov er, Sw itc ho ver, Sw i tcho ver , Swi tcho ver , Swi tcho v er,

Switchover, Switchover, Swi tchover, Switchover, Backup, Backup, Backup, Backup, Backup, Backup, Backu p, Backup, Backup, Backup, Backup, Backup, Backup, Ba ck-

up, Backup, Bac kup, Backup, Backup, Backup, Back up, Write Pr otec t, Write Protect, Write Protect, Wri te Protec t, Write Protect , Write Protect, Write Protect, Write Pro-

tect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write

Protect, Wr i te Protec t, Wri te Pr otect, Writ e Pr ot e ct , W ri te Pro t e c t, Wr i te Pr otect, Ind ustr i al , I n dus t ri al , In dustr ia l , Industr ial , In dus tria l, Ind ustr ial , In dust ria l, Indu str ial , In-

dustrial, Industrial, Industri al, vIndustrial, Industrial, Industrial, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT , SNAPHAT, SN AP HA T, SN AP HA T , S NAP H AT ,

SNAPH A T, SNAPH AT , SNAPHAT, SN APH AT, SNAPH AT, SN AP HA T , SN APHAT , SNA PH AT, SN AP HA T , SNAPH AT , SNAPHAT, SNAPHAT, SN APH AT, SN A PH AT ,

SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SOIC, SOIC, SOIC, SO-

IC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC

Date Version Revision Details

December 12, 2003 1.0 First Edition

25-Dec-03 1.1 Add crystal isolation, footprint (Figure 13)

15-Jan-04 1.2 Update characteristics (Figure 2, 3, 13; Table 2, 4, 9, 11, 12)

27-Feb-04 1.3 Update characteristics, mechanical information (Figure 4, 14, 15; Table 6, 9, 11)

02-Mar-04 1.4 Update characteristics (Table 7, 9, 10, 12)

26-Apr-04 2.0 Reformat and publish

13-May-04 3.0 Update characteristics (Table 6, 9, 10; Figure 2, 3, 15)

18-Jan-05 4.0 Update characteristics (Figure 4; Table 2, 7, 9)

23/23

M41T50

Information fur nished is believed to b e accurate and relia ble. However, STMicroelectronics a ssumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. S TMi croelectronics product s are not

authorized for us e as cri t i cal com ponents in lif e support devices or sy stems without express written a p proval of STMicr oel ectro nics.

The ST l ogo i s a regist ered tra dem ark of STMi croelectron ics.

All other names are th e property of their respec tive owners

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