K22F Sub-Family Reference Manual Supports: MK22FN128VDC10, MK22FN128VLL10, MK22FN128VMP10, MK22FN128VLH10, MK22FN128CAK10R Document Number: K22P121M100SF9RM Rev. 4, 08/2016 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 2 NXP Semiconductors Contents Section number Title Page Chapter 1 About This Document 1.1 1.2 Overview.......................................................................................................................................................................45 1.1.1 Purpose.........................................................................................................................................................45 1.1.2 Audience...................................................................................................................................................... 45 Conventions.................................................................................................................................................................. 45 1.2.1 Numbering systems......................................................................................................................................45 1.2.2 Typographic notation................................................................................................................................... 46 1.2.3 Special terms................................................................................................................................................ 46 Chapter 2 Introduction 2.1 Overview.......................................................................................................................................................................47 2.2 Module Functional Categories......................................................................................................................................47 2.3 2.2.1 ARM(R) Cortex(R)-M4 Core Modules............................................................................................................ 48 2.2.2 System Modules........................................................................................................................................... 49 2.2.3 Memories and Memory Interfaces............................................................................................................... 50 2.2.4 Clocks...........................................................................................................................................................50 2.2.5 Security and Integrity modules.................................................................................................................... 50 2.2.6 Analog modules........................................................................................................................................... 51 2.2.7 Timer modules............................................................................................................................................. 51 2.2.8 Communication interfaces........................................................................................................................... 52 2.2.9 Human-machine interfaces.......................................................................................................................... 53 Orderable part numbers.................................................................................................................................................53 Chapter 3 Chip Configuration 3.1 Introduction...................................................................................................................................................................55 3.2 Core modules................................................................................................................................................................ 55 3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................55 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 3 Section number 3.3 3.4 3.5 3.6 Title Page 3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................57 3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................63 3.2.4 FPU Configuration....................................................................................................................................... 64 3.2.5 JTAG Controller Configuration................................................................................................................... 64 System modules............................................................................................................................................................ 65 3.3.1 SIM Configuration....................................................................................................................................... 65 3.3.2 System Mode Controller (SMC) Configuration...........................................................................................66 3.3.3 PMC Configuration......................................................................................................................................66 3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration................................................................................. 67 3.3.5 MCM Configuration.................................................................................................................................... 69 3.3.6 Crossbar-Light Switch Configuration.......................................................................................................... 69 3.3.7 Peripheral Bridge Configuration.................................................................................................................. 71 3.3.8 DMA request multiplexer configuration......................................................................................................72 3.3.9 DMA Controller Configuration................................................................................................................... 75 3.3.10 External Watchdog Monitor (EWM) Configuration....................................................................................76 3.3.11 Watchdog Configuration..............................................................................................................................78 Clock modules.............................................................................................................................................................. 79 3.4.1 MCG Configuration..................................................................................................................................... 79 3.4.2 OSC Configuration...................................................................................................................................... 80 3.4.3 RTC OSC configuration...............................................................................................................................81 Memories and memory interfaces.................................................................................................................................82 3.5.1 Flash Memory Configuration.......................................................................................................................82 3.5.2 Flash Memory Controller Configuration..................................................................................................... 85 3.5.3 SRAM Configuration................................................................................................................................... 85 3.5.4 System Register File Configuration............................................................................................................. 87 3.5.5 VBAT Register File Configuration..............................................................................................................88 3.5.6 EzPort Configuration................................................................................................................................... 88 Security......................................................................................................................................................................... 90 3.6.1 CRC Configuration...................................................................................................................................... 90 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 4 NXP Semiconductors Section number 3.7 3.8 3.9 3.10 Title Page Analog...........................................................................................................................................................................90 3.7.1 16-bit SAR ADC Configuration.................................................................................................................. 90 3.7.2 CMP Configuration......................................................................................................................................97 3.7.3 12-bit DAC Configuration........................................................................................................................... 99 3.7.4 VREF Configuration.................................................................................................................................... 101 Timers........................................................................................................................................................................... 102 3.8.1 PDB Configuration...................................................................................................................................... 102 3.8.2 FlexTimer Configuration............................................................................................................................. 105 3.8.3 PIT Configuration........................................................................................................................................ 111 3.8.4 Low-power timer configuration................................................................................................................... 112 3.8.5 RTC configuration....................................................................................................................................... 114 Communication interfaces............................................................................................................................................ 115 3.9.1 Universal Serial Bus (USB) FS Subsystem................................................................................................. 115 3.9.2 SPI configuration......................................................................................................................................... 119 3.9.3 I2C Configuration........................................................................................................................................ 122 3.9.4 UART Configuration................................................................................................................................... 123 3.9.5 LPUART configuration................................................................................................................................126 3.9.6 I2S configuration..........................................................................................................................................126 Human-machine interfaces........................................................................................................................................... 130 3.10.1 GPIO configuration......................................................................................................................................130 Chapter 4 Memory Map 4.1 Introduction...................................................................................................................................................................133 4.2 System memory map.....................................................................................................................................................133 4.3 4.2.1 Aliased bit-band regions.............................................................................................................................. 134 4.2.2 Flash Access Control Introduction...............................................................................................................136 Flash Memory Map.......................................................................................................................................................136 4.3.1 4.4 Alternate Non-Volatile IRC User Trim Description....................................................................................137 SRAM memory map..................................................................................................................................................... 137 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 5 Section number 4.5 4.6 Title Page Peripheral bridge (AIPS-Lite) memory map.................................................................................................................138 4.5.1 Read-after-write sequence and required serialization of memory operations..............................................138 4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................ 138 Private Peripheral Bus (PPB) memory map..................................................................................................................142 Chapter 5 Clock Distribution 5.1 Introduction...................................................................................................................................................................145 5.2 Programming model......................................................................................................................................................145 5.3 High-Level device clocking diagram............................................................................................................................145 5.4 Clock definitions...........................................................................................................................................................146 5.4.1 5.5 Device clock summary.................................................................................................................................147 Internal clocking requirements..................................................................................................................................... 149 5.5.1 Clock divider values after reset....................................................................................................................150 5.5.2 VLPR mode clocking...................................................................................................................................151 5.6 Clock Gating................................................................................................................................................................. 151 5.7 Module clocks...............................................................................................................................................................151 5.7.1 PMC 1-kHz LPO clock................................................................................................................................ 153 5.7.2 IRC 48MHz clock........................................................................................................................................ 153 5.7.3 WDOG clocking.......................................................................................................................................... 154 5.7.4 Debug trace clock.........................................................................................................................................155 5.7.5 PORT digital filter clocking.........................................................................................................................155 5.7.6 LPTMR clocking..........................................................................................................................................155 5.7.7 RTC_CLKOUT and CLKOUT32K clocking.............................................................................................. 156 5.7.8 USB FS OTG Controller clocking............................................................................................................... 157 5.7.9 UART clocking............................................................................................................................................ 158 5.7.10 LPUART0 clocking..................................................................................................................................... 158 5.7.11 I2S/SAI clocking..........................................................................................................................................159 Chapter 6 Reset and Boot K22F Sub-Family Reference Manual, Rev. 4, 08/2016 6 NXP Semiconductors Section number Title Page 6.1 Introduction...................................................................................................................................................................161 6.2 Reset..............................................................................................................................................................................161 6.3 6.2.1 Power-on reset (POR).................................................................................................................................. 162 6.2.2 System reset sources.................................................................................................................................... 162 6.2.3 MCU Resets................................................................................................................................................. 166 6.2.4 Reset Pin ..................................................................................................................................................... 167 6.2.5 Debug resets................................................................................................................................................. 167 Boot...............................................................................................................................................................................169 6.3.1 Boot sources................................................................................................................................................. 169 6.3.2 Boot options................................................................................................................................................. 169 6.3.3 FOPT boot options....................................................................................................................................... 169 6.3.4 Boot sequence.............................................................................................................................................. 170 Chapter 7 Power Management 7.1 Introduction...................................................................................................................................................................173 7.2 Clocking modes............................................................................................................................................................ 173 7.2.1 Partial Stop................................................................................................................................................... 173 7.2.2 DMA Wakeup.............................................................................................................................................. 174 7.2.3 Compute Operation...................................................................................................................................... 175 7.2.4 Peripheral Doze............................................................................................................................................176 7.2.5 Clock Gating................................................................................................................................................ 177 7.3 Power Modes Description.............................................................................................................................................177 7.4 Entering and exiting power modes............................................................................................................................... 179 7.5 Power mode transitions.................................................................................................................................................180 7.6 Power modes shutdown sequencing............................................................................................................................. 181 7.7 Flash Program Restrictions........................................................................................................................................... 182 7.8 Module Operation in Low Power Modes......................................................................................................................182 Chapter 8 Security K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 7 Section number Title Page 8.1 Introduction...................................................................................................................................................................187 8.2 Flash Security............................................................................................................................................................... 187 8.3 Security Interactions with other Modules..................................................................................................................... 188 8.3.1 Security Interactions with EzPort................................................................................................................ 188 8.3.2 Security Interactions with Debug.................................................................................................................188 Chapter 9 Debug 9.1 Introduction...................................................................................................................................................................189 9.1.1 9.2 References.................................................................................................................................................... 191 The Debug Port............................................................................................................................................................. 191 9.2.1 JTAG-to-SWD change sequence................................................................................................................. 192 9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................192 9.3 Debug Port Pin Descriptions.........................................................................................................................................193 9.4 System TAP connection................................................................................................................................................193 9.4.1 9.5 IR Codes.......................................................................................................................................................193 JTAG status and control registers................................................................................................................................. 194 9.5.1 MDM-AP Control Register..........................................................................................................................195 9.5.2 MDM-AP Status Register............................................................................................................................ 197 9.6 Debug Resets................................................................................................................................................................ 198 9.7 AHB-AP........................................................................................................................................................................199 9.8 ITM............................................................................................................................................................................... 199 9.9 Core Trace Connectivity............................................................................................................................................... 200 9.10 TPIU..............................................................................................................................................................................200 9.11 DWT............................................................................................................................................................................. 200 9.12 Debug in Low Power Modes........................................................................................................................................ 201 9.12.1 9.13 Debug Module State in Low Power Modes................................................................................................. 201 Debug & Security......................................................................................................................................................... 202 Chapter 10 Signal Multiplexing and Signal Descriptions K22F Sub-Family Reference Manual, Rev. 4, 08/2016 8 NXP Semiconductors Section number Title Page 10.1 Introduction...................................................................................................................................................................203 10.2 Signal Multiplexing Integration....................................................................................................................................203 10.3 10.4 10.2.1 Port control and interrupt module features.................................................................................................. 204 10.2.2 Clock gating................................................................................................................................................. 205 10.2.3 Signal multiplexing constraints....................................................................................................................205 Pinout............................................................................................................................................................................ 205 10.3.1 K22 Signal Multiplexing and Pin Assignments........................................................................................... 205 10.3.2 K22 Pinouts..................................................................................................................................................210 Module Signal Description Tables................................................................................................................................215 10.4.1 Core Modules............................................................................................................................................... 215 10.4.2 System Modules........................................................................................................................................... 216 10.4.3 Clock Modules............................................................................................................................................. 216 10.4.4 Memories and Memory Interfaces............................................................................................................... 217 10.4.5 Analog.......................................................................................................................................................... 217 10.4.6 Timer Modules............................................................................................................................................. 218 10.4.7 Communication Interfaces........................................................................................................................... 220 10.4.8 Human-Machine Interfaces (HMI).............................................................................................................. 222 Chapter 11 Port Control and Interrupts (PORT) 11.1 Introduction...................................................................................................................................................................223 11.2 Overview.......................................................................................................................................................................223 11.2.1 Features........................................................................................................................................................ 223 11.2.2 Modes of operation...................................................................................................................................... 224 11.3 External signal description............................................................................................................................................225 11.4 Detailed signal description............................................................................................................................................225 11.5 Memory map and register definition.............................................................................................................................225 11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................232 11.5.2 Global Pin Control Low Register (PORTx_GPCLR).................................................................................. 235 11.5.3 Global Pin Control High Register (PORTx_GPCHR)................................................................................. 235 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 9 Section number 11.6 Title Page 11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................ 236 11.5.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................236 11.5.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................ 237 11.5.7 Digital Filter Width Register (PORTx_DFWR).......................................................................................... 237 Functional description...................................................................................................................................................238 11.6.1 Pin control.................................................................................................................................................... 238 11.6.2 Global pin control........................................................................................................................................ 239 11.6.3 External interrupts........................................................................................................................................239 11.6.4 Digital filter..................................................................................................................................................240 Chapter 12 System Integration Module (SIM) 12.1 Introduction...................................................................................................................................................................243 12.1.1 12.2 Features........................................................................................................................................................ 243 Memory map and register definition.............................................................................................................................244 12.2.1 System Options Register 1 (SIM_SOPT1).................................................................................................. 245 12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................246 12.2.3 System Options Register 2 (SIM_SOPT2).................................................................................................. 247 12.2.4 System Options Register 4 (SIM_SOPT4).................................................................................................. 249 12.2.5 System Options Register 5 (SIM_SOPT5).................................................................................................. 251 12.2.6 System Options Register 7 (SIM_SOPT7).................................................................................................. 253 12.2.7 System Options Register 8 (SIM_SOPT8).................................................................................................. 255 12.2.8 System Device Identification Register (SIM_SDID)...................................................................................256 12.2.9 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................258 12.2.10 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................260 12.2.11 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................262 12.2.12 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................265 12.2.13 System Clock Divider Register 1 (SIM_CLKDIV1)................................................................................... 265 12.2.14 System Clock Divider Register 2 (SIM_CLKDIV2)................................................................................... 267 12.2.15 Flash Configuration Register 1 (SIM_FCFG1)........................................................................................... 268 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 10 NXP Semiconductors Section number 12.3 Title Page 12.2.16 Flash Configuration Register 2 (SIM_FCFG2)........................................................................................... 270 12.2.17 Unique Identification Register High (SIM_UIDH)..................................................................................... 270 12.2.18 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................271 12.2.19 Unique Identification Register Mid Low (SIM_UIDML)........................................................................... 271 12.2.20 Unique Identification Register Low (SIM_UIDL)...................................................................................... 272 Functional description...................................................................................................................................................272 Chapter 13 Kinetis Flashloader 13.1 Chip-Specific Information............................................................................................................................................ 273 13.2 Introduction...................................................................................................................................................................273 13.3 Functional Description..................................................................................................................................................275 13.4 13.5 13.3.1 Memory Maps.............................................................................................................................................. 275 13.3.2 Start-up Process............................................................................................................................................275 13.3.3 Clock Configuration.....................................................................................................................................276 13.3.4 Flashloader Protocol.................................................................................................................................... 276 13.3.5 Flashloader Packet Types.............................................................................................................................281 13.3.6 Flashloader Command API.......................................................................................................................... 288 Peripherals Supported................................................................................................................................................... 307 13.4.1 I2C Peripheral.............................................................................................................................................. 307 13.4.2 SPI Peripheral.............................................................................................................................................. 309 13.4.3 UART Peripheral......................................................................................................................................... 311 13.4.4 USB peripheral.............................................................................................................................................314 Get/SetProperty Command Properties..........................................................................................................................316 13.5.1 13.6 Property Definitions..................................................................................................................................... 317 Kinetis Flashloader Status Error Codes........................................................................................................................ 319 Chapter 14 Reset Control Module (RCM) 14.1 Introduction...................................................................................................................................................................321 14.2 Reset memory map and register descriptions............................................................................................................... 321 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 11 Section number Title Page 14.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................ 322 14.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................ 323 14.2.3 Reset Pin Filter Control register (RCM_RPFC).......................................................................................... 325 14.2.4 Reset Pin Filter Width register (RCM_RPFW)........................................................................................... 326 14.2.5 Mode Register (RCM_MR)......................................................................................................................... 327 14.2.6 Sticky System Reset Status Register 0 (RCM_SSRS0)...............................................................................328 14.2.7 Sticky System Reset Status Register 1 (RCM_SSRS1)...............................................................................329 Chapter 15 System Mode Controller (SMC) 15.1 Introduction...................................................................................................................................................................331 15.2 Modes of operation....................................................................................................................................................... 331 15.3 Memory map and register descriptions.........................................................................................................................333 15.4 15.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................334 15.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................335 15.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................337 15.3.4 Power Mode Status register (SMC_PMSTAT)........................................................................................... 338 Functional description...................................................................................................................................................339 15.4.1 Power mode transitions................................................................................................................................ 339 15.4.2 Power mode entry/exit sequencing.............................................................................................................. 342 15.4.3 Run modes....................................................................................................................................................344 15.4.4 Wait modes.................................................................................................................................................. 346 15.4.5 Stop modes................................................................................................................................................... 346 15.4.6 Debug in low power modes......................................................................................................................... 349 Chapter 16 Power Management Controller (PMC) 16.1 Introduction...................................................................................................................................................................351 16.2 Features......................................................................................................................................................................... 351 16.3 Low-voltage detect (LVD) system................................................................................................................................351 16.3.1 LVD reset operation.....................................................................................................................................352 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 12 NXP Semiconductors Section number Title Page 16.3.2 LVD interrupt operation...............................................................................................................................352 16.3.3 Low-voltage warning (LVW) interrupt operation....................................................................................... 352 16.4 I/O retention.................................................................................................................................................................. 353 16.5 Memory map and register descriptions.........................................................................................................................353 16.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................ 354 16.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................ 355 16.5.3 Regulator Status And Control register (PMC_REGSC).............................................................................. 356 Chapter 17 Low-Leakage Wakeup Unit (LLWU) 17.1 Introduction...................................................................................................................................................................359 17.1.1 Features........................................................................................................................................................ 359 17.1.2 Modes of operation...................................................................................................................................... 360 17.1.3 Block diagram.............................................................................................................................................. 361 17.2 LLWU signal descriptions............................................................................................................................................ 362 17.3 Memory map/register definition................................................................................................................................... 362 17.4 17.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................363 17.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................364 17.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................365 17.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................366 17.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................ 367 17.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................369 17.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................371 17.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................372 17.3.9 LLWU Pin Filter 1 register (LLWU_FILT1).............................................................................................. 374 17.3.10 LLWU Pin Filter 2 register (LLWU_FILT2).............................................................................................. 375 Functional description...................................................................................................................................................376 17.4.1 LLS mode.....................................................................................................................................................377 17.4.2 VLLS modes................................................................................................................................................ 377 17.4.3 Initialization................................................................................................................................................. 377 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 13 Section number Title Page Chapter 18 Miscellaneous Control Module (MCM) 18.1 Introduction...................................................................................................................................................................379 18.1.1 18.2 18.3 Features........................................................................................................................................................ 379 Memory map/register descriptions............................................................................................................................... 379 18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................380 18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................ 380 18.2.3 Crossbar Switch (AXBS) Control Register (MCM_PLACR)..................................................................... 381 18.2.4 Interrupt Status and Control Register (MCM_ISCR).................................................................................. 381 18.2.5 Compute Operation Control Register (MCM_CPO)................................................................................... 384 Functional description...................................................................................................................................................385 18.3.1 Interrupts...................................................................................................................................................... 385 Chapter 19 Crossbar Switch Lite (AXBS-Lite) 19.1 Introduction...................................................................................................................................................................387 19.1.1 Features........................................................................................................................................................ 387 19.2 Memory Map / Register Definition...............................................................................................................................388 19.3 Functional Description..................................................................................................................................................388 19.4 19.3.1 General operation......................................................................................................................................... 388 19.3.2 Arbitration.................................................................................................................................................... 389 Initialization/application information........................................................................................................................... 390 Chapter 20 Peripheral Bridge (AIPS-Lite) 20.1 Introduction...................................................................................................................................................................391 20.1.1 Features........................................................................................................................................................ 391 20.1.2 General operation......................................................................................................................................... 391 20.2 Memory map/register definition................................................................................................................................... 392 20.3 Functional description...................................................................................................................................................392 20.3.1 Access support............................................................................................................................................. 392 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 14 NXP Semiconductors Section number Title Page Chapter 21 Direct Memory Access Multiplexer (DMAMUX) 21.1 Introduction...................................................................................................................................................................393 21.1.1 Overview...................................................................................................................................................... 393 21.1.2 Features........................................................................................................................................................ 394 21.1.3 Modes of operation...................................................................................................................................... 394 21.2 External signal description............................................................................................................................................395 21.3 Memory map/register definition................................................................................................................................... 395 21.3.1 21.4 21.5 Channel Configuration register (DMAMUX_CHCFGn)............................................................................ 395 Functional description...................................................................................................................................................396 21.4.1 DMA channels with periodic triggering capability......................................................................................397 21.4.2 DMA channels with no triggering capability...............................................................................................399 21.4.3 Always-enabled DMA sources.................................................................................................................... 399 Initialization/application information........................................................................................................................... 401 21.5.1 Reset.............................................................................................................................................................401 21.5.2 Enabling and configuring sources................................................................................................................401 Chapter 22 Enhanced Direct Memory Access (eDMA) 22.1 Introduction...................................................................................................................................................................405 22.1.1 eDMA system block diagram...................................................................................................................... 405 22.1.2 Block parts................................................................................................................................................... 406 22.1.3 Features........................................................................................................................................................ 407 22.2 Modes of operation....................................................................................................................................................... 408 22.3 Memory map/register definition................................................................................................................................... 409 22.3.1 TCD memory............................................................................................................................................... 409 22.3.2 TCD initialization........................................................................................................................................ 409 22.3.3 TCD structure...............................................................................................................................................409 22.3.4 Reserved memory and bit fields...................................................................................................................410 22.3.5 Control Register (DMA_CR).......................................................................................................................414 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 15 Section number Title Page 22.3.6 Error Status Register (DMA_ES)................................................................................................................ 417 22.3.7 Enable Request Register (DMA_ERQ)....................................................................................................... 419 22.3.8 Enable Error Interrupt Register (DMA_EEI)...............................................................................................420 22.3.9 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................. 421 22.3.10 Set Enable Error Interrupt Register (DMA_SEEI)...................................................................................... 422 22.3.11 Clear Enable Request Register (DMA_CERQ)........................................................................................... 423 22.3.12 Set Enable Request Register (DMA_SERQ)............................................................................................... 424 22.3.13 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................ 425 22.3.14 Set START Bit Register (DMA_SSRT)...................................................................................................... 426 22.3.15 Clear Error Register (DMA_CERR)............................................................................................................427 22.3.16 Clear Interrupt Request Register (DMA_CINT)......................................................................................... 428 22.3.17 Interrupt Request Register (DMA_INT)......................................................................................................429 22.3.18 Error Register (DMA_ERR)........................................................................................................................ 430 22.3.19 Hardware Request Status Register (DMA_HRS)........................................................................................ 431 22.3.20 Enable Asynchronous Request in Stop Register (DMA_EARS).................................................................433 22.3.21 Channel n Priority Register (DMA_DCHPRIn).......................................................................................... 434 22.3.22 TCD Source Address (DMA_TCDn_SADDR)........................................................................................... 435 22.3.23 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................435 22.3.24 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................436 22.3.25 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................. 437 22.3.26 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCDn_NBYTES_MLOFFNO)....................................................................................................... 437 22.3.27 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCDn_NBYTES_MLOFFYES)..................................................................................................... 439 22.3.28 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................440 22.3.29 TCD Destination Address (DMA_TCDn_DADDR)................................................................................... 440 22.3.30 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................441 22.3.31 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_CITER_ELINKYES)...........................................................................................................441 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 16 NXP Semiconductors Section number 22.3.32 Title Page TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_CITER_ELINKNO)............................................................................................................ 443 22.3.33 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA).......... 444 22.3.34 TCD Control and Status (DMA_TCDn_CSR)............................................................................................ 444 22.3.35 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_BITER_ELINKYES)...........................................................................................................447 22.3.36 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_BITER_ELINKNO)............................................................................................................ 448 22.4 22.5 Functional description...................................................................................................................................................449 22.4.1 eDMA basic data flow................................................................................................................................. 449 22.4.2 Fault reporting and handling........................................................................................................................ 452 22.4.3 Channel preemption..................................................................................................................................... 454 22.4.4 Performance................................................................................................................................................. 454 Initialization/application information........................................................................................................................... 459 22.5.1 eDMA initialization..................................................................................................................................... 459 22.5.2 Programming errors..................................................................................................................................... 461 22.5.3 Arbitration mode considerations.................................................................................................................. 461 22.5.4 Performing DMA transfers.......................................................................................................................... 462 22.5.5 Monitoring transfer descriptor status........................................................................................................... 466 22.5.6 Channel Linking...........................................................................................................................................468 22.5.7 Dynamic programming................................................................................................................................ 469 22.5.8 Lockstep....................................................................................................................................................... 472 Chapter 23 External Watchdog Monitor (EWM) 23.1 Introduction...................................................................................................................................................................475 23.1.1 Features........................................................................................................................................................ 475 23.1.2 Modes of Operation..................................................................................................................................... 476 23.1.3 Block Diagram............................................................................................................................................. 477 23.2 EWM Signal Descriptions............................................................................................................................................ 478 23.3 Memory Map/Register Definition.................................................................................................................................478 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 17 Section number 23.4 Title Page 23.3.1 Control Register (EWM_CTRL)................................................................................................................. 478 23.3.2 Service Register (EWM_SERV)..................................................................................................................479 23.3.3 Compare Low Register (EWM_CMPL)...................................................................................................... 479 23.3.4 Compare High Register (EWM_CMPH)..................................................................................................... 480 23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................ 481 Functional Description..................................................................................................................................................481 23.4.1 The EWM_out Signal.................................................................................................................................. 481 23.4.2 The EWM_in Signal.................................................................................................................................... 482 23.4.3 EWM Counter.............................................................................................................................................. 483 23.4.4 EWM Compare Registers............................................................................................................................ 483 23.4.5 EWM Refresh Mechanism...........................................................................................................................483 23.4.6 EWM Interrupt............................................................................................................................................. 484 23.4.7 Counter clock prescaler................................................................................................................................484 Chapter 24 Watchdog Timer (WDOG) 24.1 Introduction...................................................................................................................................................................485 24.2 Features......................................................................................................................................................................... 485 24.3 Functional overview......................................................................................................................................................486 24.4 24.3.1 Unlocking and updating the watchdog.........................................................................................................488 24.3.2 Watchdog configuration time (WCT).......................................................................................................... 489 24.3.3 Refreshing the watchdog..............................................................................................................................490 24.3.4 Windowed mode of operation......................................................................................................................490 24.3.5 Watchdog disabled mode of operation.........................................................................................................490 24.3.6 Debug modes of operation........................................................................................................................... 490 Testing the watchdog.................................................................................................................................................... 491 24.4.1 Quick test..................................................................................................................................................... 492 24.4.2 Byte test........................................................................................................................................................492 24.5 Backup reset generator..................................................................................................................................................493 24.6 Generated resets and interrupts.....................................................................................................................................494 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 18 NXP Semiconductors Section number 24.7 24.8 24.9 Title Page Memory map and register definition.............................................................................................................................494 24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)........................................................... 495 24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................ 497 24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH)................................................................. 497 24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL).................................................................. 498 24.7.5 Watchdog Window Register High (WDOG_WINH).................................................................................. 498 24.7.6 Watchdog Window Register Low (WDOG_WINL)................................................................................... 499 24.7.7 Watchdog Refresh register (WDOG_REFRESH)....................................................................................... 499 24.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................499 24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH)................................................................. 500 24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL).................................................................. 500 24.7.11 Watchdog Reset Count register (WDOG_RSTCNT).................................................................................. 501 24.7.12 Watchdog Prescaler register (WDOG_PRESC).......................................................................................... 501 Watchdog operation with 8-bit access.......................................................................................................................... 501 24.8.1 General guideline......................................................................................................................................... 501 24.8.2 Refresh and unlock operations with 8-bit access......................................................................................... 502 Restrictions on watchdog operation..............................................................................................................................503 Chapter 25 Multipurpose Clock Generator (MCG) 25.1 Introduction...................................................................................................................................................................505 25.1.1 Features........................................................................................................................................................ 505 25.1.2 Modes of Operation..................................................................................................................................... 507 25.2 External Signal Description.......................................................................................................................................... 508 25.3 Memory Map/Register Definition.................................................................................................................................508 25.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................509 25.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................510 25.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................511 25.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................512 25.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................513 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 19 Section number 25.4 25.5 Title Page 25.3.5 MCG Control 6 Register (MCG_C6)...........................................................................................................513 25.3.6 MCG Status Register (MCG_S).................................................................................................................. 514 25.3.7 MCG Status and Control Register (MCG_SC)............................................................................................515 25.3.8 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................ 516 25.3.9 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................517 25.3.10 MCG Control 7 Register (MCG_C7)...........................................................................................................517 25.3.11 MCG Control 8 Register (MCG_C8)...........................................................................................................518 25.3.12 MCG Control 12 Register (MCG_C12).......................................................................................................519 25.3.12 MCG Status 2 Register (MCG_S2)............................................................................................................. 519 25.3.12 MCG Test 3 Register (MCG_T3)................................................................................................................ 519 Functional description...................................................................................................................................................520 25.4.1 MCG mode state diagram............................................................................................................................ 520 25.4.2 Low-power bit usage....................................................................................................................................523 25.4.3 MCG Internal Reference Clocks..................................................................................................................523 25.4.4 External Reference Clock............................................................................................................................ 523 25.4.5 MCG Fixed Frequency Clock ..................................................................................................................... 524 25.4.6 MCG Auto TRIM (ATM)............................................................................................................................ 524 Initialization / Application information........................................................................................................................ 526 25.5.1 MCG module initialization sequence...........................................................................................................526 25.5.2 Using a 32.768 kHz reference......................................................................................................................528 25.5.3 MCG mode switching.................................................................................................................................. 529 Chapter 26 Oscillator (OSC) 26.1 Introduction...................................................................................................................................................................537 26.2 Features and Modes...................................................................................................................................................... 537 26.3 Block Diagram.............................................................................................................................................................. 538 26.4 OSC Signal Descriptions.............................................................................................................................................. 538 26.5 External Crystal / Resonator Connections.................................................................................................................... 539 26.6 External Clock Connections......................................................................................................................................... 540 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 20 NXP Semiconductors Section number 26.7 26.9 Page Memory Map/Register Definitions............................................................................................................................... 541 26.7.1 26.8 Title OSC Memory Map/Register Definition....................................................................................................... 541 Functional Description..................................................................................................................................................543 26.8.1 OSC module states....................................................................................................................................... 543 26.8.2 OSC module modes..................................................................................................................................... 545 26.8.3 Counter.........................................................................................................................................................547 26.8.4 Reference clock pin requirements................................................................................................................547 Reset..............................................................................................................................................................................547 26.10 Low power modes operation.........................................................................................................................................548 26.11 Interrupts....................................................................................................................................................................... 548 Chapter 27 RTC Oscillator (OSC32K) 27.1 27.2 Introduction...................................................................................................................................................................549 27.1.1 Features and Modes..................................................................................................................................... 549 27.1.2 Block Diagram............................................................................................................................................. 549 RTC Signal Descriptions.............................................................................................................................................. 550 27.2.1 EXTAL32 -- Oscillator Input..................................................................................................................... 550 27.2.2 XTAL32 -- Oscillator Output..................................................................................................................... 550 27.3 External Crystal Connections....................................................................................................................................... 551 27.4 Memory Map/Register Descriptions.............................................................................................................................551 27.5 Functional Description..................................................................................................................................................551 27.6 Reset Overview.............................................................................................................................................................552 27.7 Interrupts....................................................................................................................................................................... 552 Chapter 28 Flash Memory Controller (FMC) 28.1 28.2 Introduction...................................................................................................................................................................553 28.1.1 Overview...................................................................................................................................................... 553 28.1.2 Features........................................................................................................................................................ 553 Modes of operation....................................................................................................................................................... 554 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 21 Section number Title Page 28.3 External signal description............................................................................................................................................554 28.4 Memory map and register descriptions.........................................................................................................................554 28.5 28.6 28.4.1 Flash Access Protection Register (FMC_PFAPR).......................................................................................558 28.4.2 Flash Bank 0 Control Register (FMC_PFB0CR)........................................................................................ 560 28.4.3 Reserved (FMC_Reserved)..........................................................................................................................562 28.4.4 Cache Tag Storage (FMC_TAGVDW0Sn)................................................................................................. 563 28.4.5 Cache Tag Storage (FMC_TAGVDW1Sn)................................................................................................. 564 28.4.6 Cache Tag Storage (FMC_TAGVDW2Sn)................................................................................................. 565 28.4.7 Cache Tag Storage (FMC_TAGVDW3Sn)................................................................................................. 566 28.4.8 Cache Data Storage (upper word) (FMC_DATAW0SnU)..........................................................................566 28.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL).......................................................................... 567 28.4.10 Cache Data Storage (upper word) (FMC_DATAW1SnU)..........................................................................567 28.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL).......................................................................... 568 28.4.12 Cache Data Storage (upper word) (FMC_DATAW2SnU)..........................................................................568 28.4.13 Cache Data Storage (lower word) (FMC_DATAW2SnL).......................................................................... 569 28.4.14 Cache Data Storage (upper word) (FMC_DATAW3SnU)..........................................................................569 28.4.15 Cache Data Storage (lower word) (FMC_DATAW3SnL).......................................................................... 570 Functional description...................................................................................................................................................570 28.5.1 Default configuration................................................................................................................................... 570 28.5.2 Configuration options.................................................................................................................................. 571 28.5.3 Speculative reads..........................................................................................................................................571 28.5.4 Flash Access Control (FAC) Function.........................................................................................................572 Initialization and application information.....................................................................................................................582 Chapter 29 Flash Memory Module (FTFA) 29.1 Introduction...................................................................................................................................................................583 29.1.1 Features........................................................................................................................................................ 584 29.1.2 Block Diagram............................................................................................................................................. 584 29.1.3 Glossary....................................................................................................................................................... 585 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 22 NXP Semiconductors Section number Title Page 29.2 External Signal Description.......................................................................................................................................... 586 29.3 Memory Map and Registers..........................................................................................................................................586 29.4 29.3.1 Flash Configuration Field Description.........................................................................................................587 29.3.2 Program Flash IFR Map...............................................................................................................................587 29.3.3 Register Descriptions................................................................................................................................... 588 Functional Description..................................................................................................................................................602 29.4.1 Flash Protection............................................................................................................................................602 29.4.2 Flash Access Protection............................................................................................................................... 602 29.4.3 Interrupts...................................................................................................................................................... 604 29.4.4 Flash Operation in Low-Power Modes........................................................................................................ 605 29.4.5 Functional Modes of Operation................................................................................................................... 605 29.4.6 Flash Reads and Ignored Writes.................................................................................................................. 605 29.4.7 Read While Write (RWW)...........................................................................................................................606 29.4.8 Flash Program and Erase..............................................................................................................................606 29.4.9 Flash Command Operations.........................................................................................................................606 29.4.10 Margin Read Commands............................................................................................................................. 611 29.4.11 Flash Command Description........................................................................................................................612 29.4.12 Security........................................................................................................................................................ 628 29.4.13 Reset Sequence............................................................................................................................................ 630 Chapter 30 EzPort 30.1 30.2 Overview.......................................................................................................................................................................633 30.1.1 Block diagram.............................................................................................................................................. 633 30.1.2 Features........................................................................................................................................................ 634 30.1.3 Modes of operation...................................................................................................................................... 634 External signal descriptions.......................................................................................................................................... 635 30.2.1 EzPort Clock (EZP_CK).............................................................................................................................. 635 30.2.2 EzPort Chip Select (EZP_CS)......................................................................................................................636 30.2.3 EzPort Serial Data In (EZP_D).................................................................................................................... 636 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 23 Section number 30.2.4 30.3 Page EzPort Serial Data Out (EZP_Q)................................................................................................................. 636 Command definition..................................................................................................................................................... 636 30.3.1 30.4 Title Command descriptions.................................................................................................................................637 Flash memory map for EzPort access...........................................................................................................................644 Chapter 31 Cyclic Redundancy Check (CRC) 31.1 31.2 31.3 Introduction...................................................................................................................................................................645 31.1.1 Features........................................................................................................................................................ 645 31.1.2 Block diagram.............................................................................................................................................. 645 31.1.3 Modes of operation...................................................................................................................................... 646 Memory map and register descriptions.........................................................................................................................646 31.2.1 CRC Data register (CRC_DATA)............................................................................................................... 647 31.2.2 CRC Polynomial register (CRC_GPOLY).................................................................................................. 648 31.2.3 CRC Control register (CRC_CTRL)............................................................................................................648 Functional description...................................................................................................................................................649 31.3.1 CRC initialization/reinitialization................................................................................................................ 649 31.3.2 CRC calculations..........................................................................................................................................650 31.3.3 Transpose feature......................................................................................................................................... 651 31.3.4 CRC result complement............................................................................................................................... 653 Chapter 32 Analog-to-Digital Converter (ADC) 32.1 32.2 Introduction...................................................................................................................................................................655 32.1.1 Features........................................................................................................................................................ 655 32.1.2 Block diagram.............................................................................................................................................. 656 ADC signal descriptions............................................................................................................................................... 658 32.2.1 Analog Power (VDDA)............................................................................................................................... 659 32.2.2 Analog Ground (VSSA)...............................................................................................................................659 32.2.3 Voltage Reference Select............................................................................................................................. 659 32.2.4 Analog Channel Inputs (ADx)..................................................................................................................... 660 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 24 NXP Semiconductors Section number 32.2.5 32.3 32.4 Title Page Differential Analog Channel Inputs (DADx)...............................................................................................660 Memory map and register definitions........................................................................................................................... 660 32.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................662 32.3.2 ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................666 32.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................667 32.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................668 32.3.5 Compare Value Registers (ADCx_CVn)..................................................................................................... 670 32.3.6 Status and Control Register 2 (ADCx_SC2)................................................................................................671 32.3.7 Status and Control Register 3 (ADCx_SC3)................................................................................................673 32.3.8 ADC Offset Correction Register (ADCx_OFS)...........................................................................................674 32.3.9 ADC Plus-Side Gain Register (ADCx_PG).................................................................................................675 32.3.10 ADC Minus-Side Gain Register (ADCx_MG)............................................................................................ 675 32.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD)......................................................... 676 32.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS).......................................................... 677 32.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4).......................................................... 677 32.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3).......................................................... 678 32.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP2).......................................................... 678 32.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1).......................................................... 679 32.3.17 ADC Plus-Side General Calibration Value Register (ADCx_CLP0).......................................................... 679 32.3.18 ADC Minus-Side General Calibration Value Register (ADCx_CLMD).....................................................680 32.3.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMS)..................................................... 680 32.3.20 ADC Minus-Side General Calibration Value Register (ADCx_CLM4)..................................................... 681 32.3.21 ADC Minus-Side General Calibration Value Register (ADCx_CLM3)..................................................... 681 32.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM2)..................................................... 682 32.3.23 ADC Minus-Side General Calibration Value Register (ADCx_CLM1)..................................................... 682 32.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM0)..................................................... 683 Functional description...................................................................................................................................................683 32.4.1 Clock select and divide control.................................................................................................................... 684 32.4.2 Voltage reference selection.......................................................................................................................... 685 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 25 Section number 32.5 Page 32.4.3 Hardware trigger and channel selects.......................................................................................................... 685 32.4.4 Conversion control....................................................................................................................................... 686 32.4.5 Automatic compare function........................................................................................................................694 32.4.6 Calibration function..................................................................................................................................... 695 32.4.7 User-defined offset function........................................................................................................................ 697 32.4.8 Temperature sensor...................................................................................................................................... 698 32.4.9 MCU wait mode operation...........................................................................................................................699 32.4.10 MCU Normal Stop mode operation............................................................................................................. 699 32.4.11 MCU Low-Power Stop mode operation...................................................................................................... 700 Initialization information.............................................................................................................................................. 701 32.5.1 32.6 Title ADC module initialization example............................................................................................................ 701 Application information................................................................................................................................................703 32.6.1 External pins and routing............................................................................................................................. 703 32.6.2 Sources of error............................................................................................................................................ 705 Chapter 33 Comparator (CMP) 33.1 33.2 Introduction...................................................................................................................................................................711 33.1.1 CMP features................................................................................................................................................711 33.1.2 6-bit DAC key features................................................................................................................................ 712 33.1.3 ANMUX key features.................................................................................................................................. 712 33.1.4 CMP, DAC and ANMUX diagram..............................................................................................................713 33.1.5 CMP block diagram..................................................................................................................................... 714 Memory map/register definitions..................................................................................................................................716 33.2.1 CMP Control Register 0 (CMPx_CR0)....................................................................................................... 716 33.2.2 CMP Control Register 1 (CMPx_CR1)....................................................................................................... 717 33.2.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................719 33.2.4 CMP Status and Control Register (CMPx_SCR).........................................................................................719 33.2.5 DAC Control Register (CMPx_DACCR).................................................................................................... 720 33.2.6 MUX Control Register (CMPx_MUXCR).................................................................................................. 721 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 26 NXP Semiconductors Section number 33.3 Title Page Functional description...................................................................................................................................................722 33.3.1 CMP functional modes.................................................................................................................................722 33.3.2 Power modes................................................................................................................................................ 731 33.3.3 Startup and operation................................................................................................................................... 732 33.3.4 Low-pass filter............................................................................................................................................. 733 33.4 CMP interrupts..............................................................................................................................................................735 33.5 DMA support................................................................................................................................................................ 735 33.6 CMP Asynchronous DMA support...............................................................................................................................736 33.7 Digital-to-analog converter...........................................................................................................................................737 33.8 DAC functional description.......................................................................................................................................... 737 33.8.1 33.9 Voltage reference source select....................................................................................................................737 DAC resets.................................................................................................................................................................... 738 33.10 DAC clocks...................................................................................................................................................................738 33.11 DAC interrupts..............................................................................................................................................................738 Chapter 34 12-bit Digital-to-Analog Converter (DAC) 34.1 Introduction...................................................................................................................................................................739 34.2 Features......................................................................................................................................................................... 739 34.3 Block diagram...............................................................................................................................................................739 34.4 Memory map/register definition................................................................................................................................... 740 34.5 34.4.1 DAC Data Low Register (DACx_DATnL)................................................................................................. 742 34.4.2 DAC Data High Register (DACx_DATnH)................................................................................................ 742 34.4.3 DAC Status Register (DACx_SR)............................................................................................................... 743 34.4.4 DAC Control Register (DACx_C0)............................................................................................................. 744 34.4.5 DAC Control Register 1 (DACx_C1).......................................................................................................... 745 34.4.6 DAC Control Register 2 (DACx_C2).......................................................................................................... 746 Functional description...................................................................................................................................................746 34.5.1 DAC data buffer operation...........................................................................................................................746 34.5.2 DMA operation............................................................................................................................................ 748 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 27 Section number Title Page 34.5.3 Resets........................................................................................................................................................... 748 34.5.4 Low-Power mode operation.........................................................................................................................748 Chapter 35 Voltage Reference (VREFV1) 35.1 35.2 35.3 35.4 Introduction...................................................................................................................................................................751 35.1.1 Overview...................................................................................................................................................... 752 35.1.2 Features........................................................................................................................................................ 752 35.1.3 Modes of Operation..................................................................................................................................... 753 35.1.4 VREF Signal Descriptions........................................................................................................................... 753 Memory Map and Register Definition..........................................................................................................................754 35.2.1 VREF Trim Register (VREF_TRM)............................................................................................................754 35.2.2 VREF Status and Control Register (VREF_SC)..........................................................................................755 Functional Description..................................................................................................................................................756 35.3.1 Voltage Reference Disabled, SC[VREFEN] = 0......................................................................................... 757 35.3.2 Voltage Reference Enabled, SC[VREFEN] = 1.......................................................................................... 757 35.3.3 Internal voltage regulator............................................................................................................................. 758 Initialization/Application Information.......................................................................................................................... 759 Chapter 36 Programmable Delay Block (PDB) 36.1 Introduction...................................................................................................................................................................761 36.1.1 Features........................................................................................................................................................ 761 36.1.2 Implementation............................................................................................................................................ 762 36.1.3 Back-to-back acknowledgment connections................................................................................................763 36.1.4 DAC External Trigger Input Connections................................................................................................... 763 36.1.5 Block diagram.............................................................................................................................................. 763 36.1.6 Modes of operation...................................................................................................................................... 765 36.2 PDB signal descriptions................................................................................................................................................765 36.3 Memory map and register definition.............................................................................................................................765 36.3.1 Status and Control register (PDBx_SC).......................................................................................................767 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 28 NXP Semiconductors Section number 36.4 36.5 Title Page 36.3.2 Modulus register (PDBx_MOD).................................................................................................................. 770 36.3.3 Counter register (PDBx_CNT).....................................................................................................................770 36.3.4 Interrupt Delay register (PDBx_IDLY)....................................................................................................... 771 36.3.5 Channel n Control register 1 (PDBx_CHnC1).............................................................................................771 36.3.6 Channel n Status register (PDBx_CHnS).....................................................................................................772 36.3.7 Channel n Delay 0 register (PDBx_CHnDLY0)..........................................................................................773 36.3.8 Channel n Delay 1 register (PDBx_CHnDLY1)..........................................................................................774 36.3.9 DAC Interval Trigger n Control register (PDBx_DACINTCn)...................................................................774 36.3.10 DAC Interval n register (PDBx_DACINTn)............................................................................................... 775 36.3.11 Pulse-Out n Enable register (PDBx_POEN)................................................................................................ 776 36.3.12 Pulse-Out n Delay register (PDBx_POnDLY).............................................................................................776 Functional description...................................................................................................................................................777 36.4.1 PDB pre-trigger and trigger outputs.............................................................................................................777 36.4.2 PDB trigger input source selection.............................................................................................................. 779 36.4.3 Pulse-Out's................................................................................................................................................... 779 36.4.4 Updating the delay registers.........................................................................................................................780 36.4.5 Interrupts...................................................................................................................................................... 782 36.4.6 DMA............................................................................................................................................................ 782 Application information................................................................................................................................................782 36.5.1 Impact of using the prescaler and multiplication factor on timing resolution............................................. 782 Chapter 37 FlexTimer Module (FTM) 37.1 Introduction...................................................................................................................................................................785 37.1.1 FlexTimer philosophy.................................................................................................................................. 785 37.1.2 Features........................................................................................................................................................ 786 37.1.3 Modes of operation...................................................................................................................................... 787 37.1.4 Block diagram.............................................................................................................................................. 788 37.2 FTM signal descriptions............................................................................................................................................... 790 37.3 Memory map and register definition.............................................................................................................................790 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 29 Section number 37.4 Title Page 37.3.1 Memory map................................................................................................................................................ 790 37.3.2 Register descriptions.................................................................................................................................... 791 37.3.3 Status And Control (FTMx_SC).................................................................................................................. 796 37.3.4 Counter (FTMx_CNT)................................................................................................................................. 797 37.3.5 Modulo (FTMx_MOD)................................................................................................................................ 798 37.3.6 Channel (n) Status And Control (FTMx_CnSC)..........................................................................................799 37.3.7 Channel (n) Value (FTMx_CnV)................................................................................................................. 802 37.3.8 Counter Initial Value (FTMx_CNTIN)........................................................................................................802 37.3.9 Capture And Compare Status (FTMx_STATUS)........................................................................................ 803 37.3.10 Features Mode Selection (FTMx_MODE).................................................................................................. 805 37.3.11 Synchronization (FTMx_SYNC)................................................................................................................. 807 37.3.12 Initial State For Channels Output (FTMx_OUTINIT).................................................................................809 37.3.13 Output Mask (FTMx_OUTMASK)............................................................................................................. 810 37.3.14 Function For Linked Channels (FTMx_COMBINE)...................................................................................812 37.3.15 Deadtime Insertion Control (FTMx_DEADTIME)..................................................................................... 817 37.3.16 FTM External Trigger (FTMx_EXTTRIG)................................................................................................. 818 37.3.17 Channels Polarity (FTMx_POL).................................................................................................................. 820 37.3.18 Fault Mode Status (FTMx_FMS).................................................................................................................822 37.3.19 Input Capture Filter Control (FTMx_FILTER)........................................................................................... 824 37.3.20 Fault Control (FTMx_FLTCTRL)............................................................................................................... 825 37.3.21 Quadrature Decoder Control And Status (FTMx_QDCTRL)......................................................................828 37.3.22 Configuration (FTMx_CONF)..................................................................................................................... 830 37.3.23 FTM Fault Input Polarity (FTMx_FLTPOL)...............................................................................................831 37.3.24 Synchronization Configuration (FTMx_SYNCONF)..................................................................................832 37.3.25 FTM Inverting Control (FTMx_INVCTRL)................................................................................................834 37.3.26 FTM Software Output Control (FTMx_SWOCTRL).................................................................................. 835 37.3.27 FTM PWM Load (FTMx_PWMLOAD)..................................................................................................... 838 Functional description...................................................................................................................................................839 37.4.1 Clock source.................................................................................................................................................840 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 30 NXP Semiconductors Section number Title Page 37.4.2 Prescaler....................................................................................................................................................... 841 37.4.3 Counter.........................................................................................................................................................841 37.4.4 Input Capture mode......................................................................................................................................847 37.4.5 Output Compare mode................................................................................................................................. 851 37.4.6 Edge-Aligned PWM (EPWM) mode........................................................................................................... 852 37.4.7 Center-Aligned PWM (CPWM) mode........................................................................................................ 854 37.4.8 Combine mode............................................................................................................................................. 856 37.4.9 Complementary mode.................................................................................................................................. 863 37.4.10 Registers updated from write buffers...........................................................................................................864 37.4.11 PWM synchronization..................................................................................................................................866 37.4.12 Inverting....................................................................................................................................................... 882 37.4.13 Software output control................................................................................................................................883 37.4.14 Deadtime insertion....................................................................................................................................... 885 37.4.15 Output mask................................................................................................................................................. 888 37.4.16 Fault control................................................................................................................................................. 888 37.4.17 Polarity control.............................................................................................................................................892 37.4.18 Initialization................................................................................................................................................. 893 37.4.19 Features priority........................................................................................................................................... 893 37.4.20 Channel trigger output................................................................................................................................. 894 37.4.21 Initialization trigger......................................................................................................................................895 37.4.22 Capture Test mode....................................................................................................................................... 898 37.4.23 DMA............................................................................................................................................................ 898 37.4.24 Dual Edge Capture mode............................................................................................................................. 899 37.4.25 Quadrature Decoder mode........................................................................................................................... 907 37.4.26 BDM mode...................................................................................................................................................912 37.4.27 Intermediate load..........................................................................................................................................913 37.4.28 Global time base (GTB)............................................................................................................................... 915 37.5 Reset overview..............................................................................................................................................................917 37.6 FTM Interrupts..............................................................................................................................................................918 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 31 Section number 37.7 Title Page 37.6.1 Timer Overflow Interrupt.............................................................................................................................919 37.6.2 Channel (n) Interrupt....................................................................................................................................919 37.6.3 Fault Interrupt.............................................................................................................................................. 919 Initialization Procedure.................................................................................................................................................919 Chapter 38 Periodic Interrupt Timer (PIT) 38.1 Introduction...................................................................................................................................................................921 38.1.1 Block diagram.............................................................................................................................................. 921 38.1.2 Features........................................................................................................................................................ 922 38.2 Signal description..........................................................................................................................................................922 38.3 Memory map/register description................................................................................................................................. 923 38.4 38.3.1 PIT Module Control Register (PIT_MCR).................................................................................................. 923 38.3.2 Timer Load Value Register (PIT_LDVALn)...............................................................................................925 38.3.3 Current Timer Value Register (PIT_CVALn)............................................................................................. 925 38.3.4 Timer Control Register (PIT_TCTRLn)...................................................................................................... 926 38.3.5 Timer Flag Register (PIT_TFLGn)..............................................................................................................926 Functional description...................................................................................................................................................927 38.4.1 General operation......................................................................................................................................... 927 38.4.2 Interrupts...................................................................................................................................................... 929 38.4.3 Chained timers............................................................................................................................................. 929 38.5 Initialization and application information.....................................................................................................................929 38.6 Example configuration for chained timers....................................................................................................................930 Chapter 39 Low-Power Timer (LPTMR) 39.1 39.2 Introduction...................................................................................................................................................................933 39.1.1 Features........................................................................................................................................................ 933 39.1.2 Modes of operation...................................................................................................................................... 933 LPTMR signal descriptions.......................................................................................................................................... 934 39.2.1 Detailed signal descriptions......................................................................................................................... 934 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 32 NXP Semiconductors Section number 39.3 39.4 Title Page Memory map and register definition.............................................................................................................................934 39.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)......................................................................935 39.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)................................................................................936 39.3.3 Low Power Timer Compare Register (LPTMRx_CMR).............................................................................938 39.3.4 Low Power Timer Counter Register (LPTMRx_CNR)............................................................................... 938 Functional description...................................................................................................................................................939 39.4.1 LPTMR power and reset.............................................................................................................................. 939 39.4.2 LPTMR clocking..........................................................................................................................................939 39.4.3 LPTMR prescaler/glitch filter...................................................................................................................... 939 39.4.4 LPTMR compare..........................................................................................................................................941 39.4.5 LPTMR counter........................................................................................................................................... 941 39.4.6 LPTMR hardware trigger.............................................................................................................................942 39.4.7 LPTMR interrupt..........................................................................................................................................942 Chapter 40 Real Time Clock (RTC) 40.1 40.2 Introduction...................................................................................................................................................................943 40.1.1 Features........................................................................................................................................................ 943 40.1.2 Modes of operation...................................................................................................................................... 943 40.1.3 RTC signal descriptions............................................................................................................................... 944 Register definition.........................................................................................................................................................945 40.2.1 RTC Time Seconds Register (RTC_TSR)................................................................................................... 945 40.2.2 RTC Time Prescaler Register (RTC_TPR)..................................................................................................946 40.2.3 RTC Time Alarm Register (RTC_TAR)..................................................................................................... 946 40.2.4 RTC Time Compensation Register (RTC_TCR).........................................................................................947 40.2.5 RTC Control Register (RTC_CR)................................................................................................................948 40.2.6 RTC Status Register (RTC_SR).................................................................................................................. 950 40.2.7 RTC Lock Register (RTC_LR)....................................................................................................................951 40.2.8 RTC Interrupt Enable Register (RTC_IER).................................................................................................952 40.2.9 RTC Write Access Register (RTC_WAR).................................................................................................. 953 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 33 Section number 40.2.10 40.3 Title Page RTC Read Access Register (RTC_RAR).................................................................................................... 954 Functional description...................................................................................................................................................956 40.3.1 Power, clocking, and reset........................................................................................................................... 956 40.3.2 Time counter................................................................................................................................................ 957 40.3.3 Compensation...............................................................................................................................................958 40.3.4 Time alarm................................................................................................................................................... 958 40.3.5 Update mode................................................................................................................................................ 959 40.3.6 Register lock................................................................................................................................................ 959 40.3.7 Access control.............................................................................................................................................. 959 40.3.8 Interrupt........................................................................................................................................................959 Chapter 41 Universal Serial Bus Full Speed OTG Controller (USBFSOTG) 41.1 41.2 41.3 41.4 Introduction...................................................................................................................................................................961 41.1.1 References.................................................................................................................................................... 961 41.1.2 USB.............................................................................................................................................................. 962 41.1.3 USB On-The-Go.......................................................................................................................................... 963 41.1.4 USBFS Features........................................................................................................................................... 964 Functional description...................................................................................................................................................964 41.2.1 Data Structures............................................................................................................................................. 964 41.2.2 On-chip transceiver required external components......................................................................................965 Programmers interface.................................................................................................................................................. 967 41.3.1 Buffer Descriptor Table............................................................................................................................... 967 41.3.2 RX vs. TX as a USB peripheral device or USB host................................................................................... 968 41.3.3 Addressing BDT entries...............................................................................................................................969 41.3.4 Buffer Descriptors (BDs)............................................................................................................................. 970 41.3.5 USB transaction........................................................................................................................................... 972 Memory map/Register definitions................................................................................................................................ 974 41.4.1 Peripheral ID register (USBx_PERID)........................................................................................................ 977 41.4.2 Peripheral ID Complement register (USBx_IDCOMP)...............................................................................977 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 34 NXP Semiconductors Section number Title Page 41.4.3 Peripheral Revision register (USBx_REV)..................................................................................................978 41.4.4 Peripheral Additional Info register (USBx_ADDINFO)............................................................................. 978 41.4.5 OTG Interrupt Status register (USBx_OTGISTAT).................................................................................... 979 41.4.6 OTG Interrupt Control register (USBx_OTGICR)...................................................................................... 980 41.4.7 OTG Status register (USBx_OTGSTAT).................................................................................................... 981 41.4.8 OTG Control register (USBx_OTGCTL).................................................................................................... 982 41.4.9 Interrupt Status register (USBx_ISTAT)..................................................................................................... 983 41.4.10 Interrupt Enable register (USBx_INTEN)................................................................................................... 984 41.4.11 Error Interrupt Status register (USBx_ERRSTAT)..................................................................................... 985 41.4.12 Error Interrupt Enable register (USBx_ERREN).........................................................................................986 41.4.13 Status register (USBx_STAT)......................................................................................................................987 41.4.14 Control register (USBx_CTL)......................................................................................................................988 41.4.15 Address register (USBx_ADDR)................................................................................................................. 989 41.4.16 BDT Page register 1 (USBx_BDTPAGE1)................................................................................................. 990 41.4.17 Frame Number register Low (USBx_FRMNUML).....................................................................................990 41.4.18 Frame Number register High (USBx_FRMNUMH)................................................................................... 991 41.4.19 Token register (USBx_TOKEN)..................................................................................................................991 41.4.20 SOF Threshold register (USBx_SOFTHLD)............................................................................................... 992 41.4.21 BDT Page Register 2 (USBx_BDTPAGE2)................................................................................................ 993 41.4.22 BDT Page Register 3 (USBx_BDTPAGE3)................................................................................................ 993 41.4.23 Endpoint Control register (USBx_ENDPTn)...............................................................................................994 41.4.24 USB Control register (USBx_USBCTRL).................................................................................................. 995 41.4.25 USB OTG Observe register (USBx_OBSERVE)........................................................................................ 996 41.4.26 USB OTG Control register (USBx_CONTROL)........................................................................................ 996 41.4.27 USB Transceiver Control register 0 (USBx_USBTRC0)............................................................................ 997 41.4.28 Frame Adjust Register (USBx_USBFRMADJUST)................................................................................... 998 41.4.29 USB Clock recovery control (USBx_CLK_RECOVER_CTRL)................................................................ 999 41.4.30 IRC48M oscillator enable register (USBx_CLK_RECOVER_IRC_EN)................................................... 1000 41.4.31 Clock recovery combined interrupt enable (USBx_CLK_RECOVER_INT_EN)...................................... 1001 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 35 Section number 41.4.32 Title Page Clock recovery separated interrupt status (USBx_CLK_RECOVER_INT_STATUS).............................. 1001 41.5 OTG and Host mode operation..................................................................................................................................... 1002 41.6 Host Mode Operation Examples...................................................................................................................................1002 41.7 On-The-Go operation....................................................................................................................................................1005 41.8 41.7.1 OTG dual role A device operation............................................................................................................... 1006 41.7.2 OTG dual role B device operation............................................................................................................... 1007 Device mode IRC48 operation......................................................................................................................................1009 Chapter 42 Serial Peripheral Interface (SPI) 42.1 42.2 42.3 Introduction...................................................................................................................................................................1011 42.1.1 Block Diagram............................................................................................................................................. 1011 42.1.2 Features........................................................................................................................................................ 1012 42.1.3 Interface configurations............................................................................................................................... 1014 42.1.4 Modes of Operation..................................................................................................................................... 1014 Module signal descriptions........................................................................................................................................... 1016 42.2.1 PCS0/SS--Peripheral Chip Select/Slave Select.......................................................................................... 1016 42.2.2 PCS1-PCS3--Peripheral Chip Selects 1-3................................................................................................. 1017 42.2.3 PCS4--Peripheral Chip Select 4..................................................................................................................1017 42.2.4 PCS5/PCSS--Peripheral Chip Select 5/Peripheral Chip Select Strobe.......................................................1017 42.2.5 SCK--Serial Clock...................................................................................................................................... 1017 42.2.6 SIN--Serial Input........................................................................................................................................ 1017 42.2.7 SOUT--Serial Output..................................................................................................................................1018 Memory Map/Register Definition.................................................................................................................................1018 42.3.1 Module Configuration Register (SPIx_MCR)............................................................................................. 1020 42.3.2 Transfer Count Register (SPIx_TCR).......................................................................................................... 1023 42.3.3 Clock and Transfer Attributes Register (In Master Mode) (SPIx_CTARn)................................................ 1024 42.3.4 Clock and Transfer Attributes Register (In Slave Mode) (SPIx_CTARn_SLAVE)................................... 1028 42.3.5 Status Register (SPIx_SR)........................................................................................................................... 1030 42.3.6 DMA/Interrupt Request Select and Enable Register (SPIx_RSER)............................................................ 1033 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 36 NXP Semiconductors Section number 42.4 42.5 Title Page 42.3.7 PUSH TX FIFO Register In Master Mode (SPIx_PUSHR)........................................................................ 1035 42.3.8 PUSH TX FIFO Register In Slave Mode (SPIx_PUSHR_SLAVE)............................................................1037 42.3.9 POP RX FIFO Register (SPIx_POPR).........................................................................................................1037 42.3.10 Transmit FIFO Registers (SPIx_TXFRn).................................................................................................... 1038 42.3.11 Receive FIFO Registers (SPIx_RXFRn)......................................................................................................1038 Functional description...................................................................................................................................................1039 42.4.1 Start and Stop of module transfers............................................................................................................... 1040 42.4.2 Serial Peripheral Interface (SPI) configuration............................................................................................1040 42.4.3 Module baud rate and clock delay generation............................................................................................. 1044 42.4.4 Transfer formats........................................................................................................................................... 1048 42.4.5 Continuous Serial Communications Clock.................................................................................................. 1057 42.4.6 Slave Mode Operation Constraints.............................................................................................................. 1059 42.4.7 Interrupts/DMA requests..............................................................................................................................1059 42.4.8 Power saving features.................................................................................................................................. 1061 Initialization/application information........................................................................................................................... 1062 42.5.1 How to manage queues................................................................................................................................ 1063 42.5.2 Switching Master and Slave mode...............................................................................................................1063 42.5.3 Initializing Module in Master/Slave Modes.................................................................................................1064 42.5.4 Baud rate settings......................................................................................................................................... 1064 42.5.5 Delay settings............................................................................................................................................... 1065 42.5.6 Calculation of FIFO pointer addresses.........................................................................................................1066 Chapter 43 Inter-Integrated Circuit (I2C) 43.1 Introduction...................................................................................................................................................................1069 43.1.1 Features........................................................................................................................................................ 1069 43.1.2 Modes of operation...................................................................................................................................... 1070 43.1.3 Block diagram.............................................................................................................................................. 1070 43.2 I2C signal descriptions..................................................................................................................................................1071 43.3 Memory map/register definition................................................................................................................................... 1072 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 37 Section number 43.4 43.5 Title Page 43.3.1 I2C Address Register 1 (I2Cx_A1).............................................................................................................. 1073 43.3.2 I2C Frequency Divider register (I2Cx_F).................................................................................................... 1073 43.3.3 I2C Control Register 1 (I2Cx_C1)............................................................................................................... 1074 43.3.4 I2C Status register (I2Cx_S)........................................................................................................................ 1076 43.3.5 I2C Data I/O register (I2Cx_D)................................................................................................................... 1078 43.3.6 I2C Control Register 2 (I2Cx_C2)............................................................................................................... 1078 43.3.7 I2C Programmable Input Glitch Filter Register (I2Cx_FLT)...................................................................... 1079 43.3.8 I2C Range Address register (I2Cx_RA)...................................................................................................... 1081 43.3.9 I2C SMBus Control and Status register (I2Cx_SMB)................................................................................. 1081 43.3.10 I2C Address Register 2 (I2Cx_A2).............................................................................................................. 1083 43.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)..................................................................................1083 43.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)...................................................................................1084 Functional description...................................................................................................................................................1084 43.4.1 I2C protocol................................................................................................................................................. 1084 43.4.2 10-bit address............................................................................................................................................... 1089 43.4.3 Address matching.........................................................................................................................................1091 43.4.4 System management bus specification........................................................................................................ 1092 43.4.5 Resets........................................................................................................................................................... 1094 43.4.6 Interrupts...................................................................................................................................................... 1094 43.4.7 Programmable input glitch filter.................................................................................................................. 1097 43.4.8 Address matching wake-up.......................................................................................................................... 1097 43.4.9 DMA support............................................................................................................................................... 1098 Initialization/application information........................................................................................................................... 1099 Chapter 44 Universal Asynchronous Receiver/Transmitter (UART) 44.1 44.2 Introduction...................................................................................................................................................................1103 44.1.1 Features........................................................................................................................................................ 1103 44.1.2 Modes of operation...................................................................................................................................... 1105 UART signal descriptions.............................................................................................................................................1106 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 38 NXP Semiconductors Section number 44.2.1 44.3 Title Page Detailed signal descriptions......................................................................................................................... 1106 Memory map and registers............................................................................................................................................1107 44.3.1 UART Baud Rate Registers: High (UARTx_BDH).................................................................................... 1112 44.3.2 UART Baud Rate Registers: Low (UARTx_BDL)..................................................................................... 1113 44.3.3 UART Control Register 1 (UARTx_C1)..................................................................................................... 1114 44.3.4 UART Control Register 2 (UARTx_C2)..................................................................................................... 1115 44.3.5 UART Status Register 1 (UARTx_S1)........................................................................................................ 1117 44.3.6 UART Status Register 2 (UARTx_S2)........................................................................................................ 1120 44.3.7 UART Control Register 3 (UARTx_C3)..................................................................................................... 1122 44.3.8 UART Data Register (UARTx_D)...............................................................................................................1123 44.3.9 UART Match Address Registers 1 (UARTx_MA1)....................................................................................1124 44.3.10 UART Match Address Registers 2 (UARTx_MA2)....................................................................................1125 44.3.11 UART Control Register 4 (UARTx_C4)..................................................................................................... 1125 44.3.12 UART Control Register 5 (UARTx_C5)..................................................................................................... 1126 44.3.13 UART Extended Data Register (UARTx_ED)............................................................................................ 1127 44.3.14 UART Modem Register (UARTx_MODEM)............................................................................................. 1128 44.3.15 UART Infrared Register (UARTx_IR)........................................................................................................ 1129 44.3.16 UART FIFO Parameters (UARTx_PFIFO)................................................................................................. 1130 44.3.17 UART FIFO Control Register (UARTx_CFIFO)........................................................................................ 1131 44.3.18 UART FIFO Status Register (UARTx_SFIFO)...........................................................................................1132 44.3.19 UART FIFO Transmit Watermark (UARTx_TWFIFO)............................................................................. 1133 44.3.20 UART FIFO Transmit Count (UARTx_TCFIFO).......................................................................................1134 44.3.21 UART FIFO Receive Watermark (UARTx_RWFIFO)...............................................................................1134 44.3.22 UART FIFO Receive Count (UARTx_RCFIFO)........................................................................................ 1135 44.3.23 UART 7816 Control Register (UARTx_C7816)......................................................................................... 1135 44.3.24 UART 7816 Interrupt Enable Register (UARTx_IE7816).......................................................................... 1137 44.3.25 UART 7816 Interrupt Status Register (UARTx_IS7816)............................................................................1138 44.3.26 UART 7816 Wait Parameter Register (UARTx_WP7816)......................................................................... 1140 44.3.27 UART 7816 Wait N Register (UARTx_WN7816)......................................................................................1140 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 39 Section number 44.4 Title Page 44.3.28 UART 7816 Wait FD Register (UARTx_WF7816).................................................................................... 1141 44.3.29 UART 7816 Error Threshold Register (UARTx_ET7816)..........................................................................1141 44.3.30 UART 7816 Transmit Length Register (UARTx_TL7816)........................................................................ 1142 44.3.31 UART 7816 ATR Duration Timer Register A (UARTx_AP7816A_T0)....................................................1142 44.3.32 UART 7816 ATR Duration Timer Register B (UARTx_AP7816B_T0).................................................... 1143 44.3.33 UART 7816 Wait Parameter Register A (UARTx_WP7816A_T0)............................................................ 1144 44.3.34 UART 7816 Wait Parameter Register A (UARTx_WP7816A_T1)............................................................ 1144 44.3.35 UART 7816 Wait Parameter Register B (UARTx_WP7816B_T0)............................................................ 1145 44.3.36 UART 7816 Wait Parameter Register B (UARTx_WP7816B_T1)............................................................ 1145 44.3.37 UART 7816 Wait and Guard Parameter Register (UARTx_WGP7816_T1).............................................. 1146 44.3.38 UART 7816 Wait Parameter Register C (UARTx_WP7816C_T1)............................................................ 1146 Functional description...................................................................................................................................................1147 44.4.1 Transmitter................................................................................................................................................... 1147 44.4.2 Receiver....................................................................................................................................................... 1153 44.4.3 Baud rate generation.................................................................................................................................... 1167 44.4.4 Data format (non ISO-7816)........................................................................................................................ 1169 44.4.5 Single-wire operation................................................................................................................................... 1172 44.4.6 Loop operation............................................................................................................................................. 1173 44.4.7 ISO-7816/smartcard support........................................................................................................................ 1173 44.4.8 Infrared interface..........................................................................................................................................1178 44.5 Reset..............................................................................................................................................................................1180 44.6 System level interrupt sources...................................................................................................................................... 1180 44.6.1 RXEDGIF description..................................................................................................................................1180 44.7 DMA operation............................................................................................................................................................. 1181 44.8 Application information................................................................................................................................................1182 44.8.1 Transmit/receive data buffer operation........................................................................................................ 1182 44.8.2 ISO-7816 initialization sequence................................................................................................................. 1182 44.8.3 Initialization sequence (non ISO-7816)....................................................................................................... 1184 44.8.4 Overrun (OR) flag implications................................................................................................................... 1185 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 40 NXP Semiconductors Section number Title Page 44.8.5 Overrun NACK considerations.................................................................................................................... 1186 44.8.6 Match address registers................................................................................................................................ 1187 44.8.7 Modem feature............................................................................................................................................. 1187 44.8.8 IrDA minimum pulse width......................................................................................................................... 1188 44.8.9 Clearing 7816 wait timer (WT, BWT, CWT) interrupts..............................................................................1188 44.8.10 Legacy and reverse compatibility considerations........................................................................................ 1189 Chapter 45 Low Power Universal Asynchronous Receiver/Transmitter (LPUART) 45.1 45.2 45.3 Introduction...................................................................................................................................................................1191 45.1.1 Features........................................................................................................................................................ 1191 45.1.2 Modes of operation...................................................................................................................................... 1192 45.1.3 Signal Descriptions...................................................................................................................................... 1192 45.1.4 Block diagram.............................................................................................................................................. 1193 Register definition.........................................................................................................................................................1194 45.2.1 LPUART Baud Rate Register (LPUARTx_BAUD)....................................................................................1195 45.2.2 LPUART Status Register (LPUARTx_STAT)............................................................................................ 1197 45.2.3 LPUART Control Register (LPUARTx_CTRL)......................................................................................... 1201 45.2.4 LPUART Data Register (LPUARTx_DATA)............................................................................................. 1206 45.2.5 LPUART Match Address Register (LPUARTx_MATCH)......................................................................... 1208 45.2.6 LPUART Modem IrDA Register (LPUARTx_MODIR).............................................................................1208 Functional description...................................................................................................................................................1210 45.3.1 Baud rate generation.................................................................................................................................... 1210 45.3.2 Transmitter functional description............................................................................................................... 1211 45.3.3 Receiver functional description................................................................................................................... 1214 45.3.4 Additional LPUART functions.................................................................................................................... 1220 45.3.5 Infrared interface..........................................................................................................................................1222 45.3.6 Interrupts and status flags............................................................................................................................ 1223 Chapter 46 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 41 Section number 46.1 Title Page Introduction...................................................................................................................................................................1225 46.1.1 Features........................................................................................................................................................ 1225 46.1.2 Block diagram.............................................................................................................................................. 1225 46.1.3 Modes of operation...................................................................................................................................... 1226 46.2 External signals.............................................................................................................................................................1227 46.3 Memory map and register definition.............................................................................................................................1228 46.4 46.3.1 SAI Transmit Control Register (I2Sx_TCSR)............................................................................................. 1229 46.3.2 SAI Transmit Configuration 1 Register (I2Sx_TCR1)................................................................................ 1232 46.3.3 SAI Transmit Configuration 2 Register (I2Sx_TCR2)................................................................................ 1233 46.3.4 SAI Transmit Configuration 3 Register (I2Sx_TCR3)................................................................................ 1234 46.3.5 SAI Transmit Configuration 4 Register (I2Sx_TCR4)................................................................................ 1235 46.3.6 SAI Transmit Configuration 5 Register (I2Sx_TCR5)................................................................................ 1237 46.3.7 SAI Transmit Data Register (I2Sx_TDRn).................................................................................................. 1238 46.3.8 SAI Transmit FIFO Register (I2Sx_TFRn)................................................................................................. 1238 46.3.9 SAI Transmit Mask Register (I2Sx_TMR).................................................................................................. 1239 46.3.10 SAI Receive Control Register (I2Sx_RCSR)...............................................................................................1240 46.3.11 SAI Receive Configuration 1 Register (I2Sx_RCR1)..................................................................................1243 46.3.12 SAI Receive Configuration 2 Register (I2Sx_RCR2)..................................................................................1243 46.3.13 SAI Receive Configuration 3 Register (I2Sx_RCR3)..................................................................................1245 46.3.14 SAI Receive Configuration 4 Register (I2Sx_RCR4)..................................................................................1246 46.3.15 SAI Receive Configuration 5 Register (I2Sx_RCR5)..................................................................................1248 46.3.16 SAI Receive Data Register (I2Sx_RDRn)................................................................................................... 1248 46.3.17 SAI Receive FIFO Register (I2Sx_RFRn)...................................................................................................1249 46.3.18 SAI Receive Mask Register (I2Sx_RMR)................................................................................................... 1249 46.3.19 SAI MCLK Control Register (I2Sx_MCR)................................................................................................. 1250 46.3.20 SAI MCLK Divide Register (I2Sx_MDR).................................................................................................. 1251 Functional description...................................................................................................................................................1252 46.4.1 SAI clocking................................................................................................................................................ 1252 46.4.2 SAI resets..................................................................................................................................................... 1254 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 42 NXP Semiconductors Section number Title Page 46.4.3 Synchronous modes..................................................................................................................................... 1255 46.4.4 Frame sync configuration.............................................................................................................................1255 46.4.5 Data FIFO.................................................................................................................................................... 1256 46.4.6 Word mask register...................................................................................................................................... 1259 46.4.7 Interrupts and DMA requests....................................................................................................................... 1259 Chapter 47 General-Purpose Input/Output (GPIO) 47.1 47.2 47.3 Introduction...................................................................................................................................................................1263 47.1.1 Features........................................................................................................................................................ 1263 47.1.2 Modes of operation...................................................................................................................................... 1263 47.1.3 GPIO signal descriptions............................................................................................................................. 1264 Memory map and register definition.............................................................................................................................1265 47.2.1 Port Data Output Register (GPIOx_PDOR).................................................................................................1266 47.2.2 Port Set Output Register (GPIOx_PSOR)....................................................................................................1267 47.2.3 Port Clear Output Register (GPIOx_PCOR)................................................................................................1268 47.2.4 Port Toggle Output Register (GPIOx_PTOR)............................................................................................. 1268 47.2.5 Port Data Input Register (GPIOx_PDIR).....................................................................................................1269 47.2.6 Port Data Direction Register (GPIOx_PDDR).............................................................................................1269 Functional description...................................................................................................................................................1270 47.3.1 General-purpose input..................................................................................................................................1270 47.3.2 General-purpose output................................................................................................................................1270 Chapter 48 JTAG Controller (JTAGC) 48.1 48.2 Introduction...................................................................................................................................................................1271 48.1.1 Block diagram.............................................................................................................................................. 1271 48.1.2 Features........................................................................................................................................................ 1272 48.1.3 Modes of operation...................................................................................................................................... 1272 External signal description............................................................................................................................................1274 48.2.1 TCK--Test clock input................................................................................................................................ 1274 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 43 Section number 48.3 48.4 48.5 Title Page 48.2.2 TDI--Test data input................................................................................................................................... 1274 48.2.3 TDO--Test data output................................................................................................................................1274 48.2.4 TMS--Test mode select...............................................................................................................................1274 Register description...................................................................................................................................................... 1275 48.3.1 Instruction register....................................................................................................................................... 1275 48.3.2 Bypass register............................................................................................................................................. 1275 48.3.3 Device identification register....................................................................................................................... 1275 48.3.4 Boundary scan register.................................................................................................................................1276 Functional description...................................................................................................................................................1277 48.4.1 JTAGC reset configuration.......................................................................................................................... 1277 48.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port.............................................................................................. 1277 48.4.3 TAP controller state machine.......................................................................................................................1277 48.4.4 JTAGC block instructions............................................................................................................................1279 48.4.5 Boundary scan..............................................................................................................................................1282 Initialization/Application information.......................................................................................................................... 1282 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 44 NXP Semiconductors Chapter 1 About This Document 1.1 Overview 1.1.1 Purpose This document describes the features, architecture, and programming model of the microcontroller. 1.1.2 Audience This document is intended for system architects and software application developers who are using (or considering using) the microcontroller in a system. 1.2 Conventions 1.2.1 Numbering systems The following suffixes identify different numbering systems: This suffix Identifies a b Binary number. For example, the binary equivalent of the number 5 is written 101b. In some cases, binary numbers are shown with the prefix 0b. d Decimal number. Decimal numbers are followed by this suffix only when the possibility of confusion exists. In general, decimal numbers are shown without a suffix. h Hexadecimal number. For example, the hexadecimal equivalent of the number 60 is written 3Ch. In some cases, hexadecimal numbers are shown with the prefix 0x. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 45 Conventions 1.2.2 Typographic notation The following typographic notation is used throughout this document: Example Description placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers. code Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type is also used for example code. Instruction mnemonics and directives in text and tables are shown in all caps; for example, BSR. SR[SCM] A mnemonic in brackets represents a named field in a register. This example refers to the Scaling Mode (SCM) field in the Status Register (SR). REVNO[6:4], XAD[7:0] Numbers in brackets and separated by a colon represent either: * A subset of a register's named field For example, REVNO[6:4] refers to bits 6-4 that are part of the COREREV field that occupies bits 6-0 of the REVNO register. * A continuous range of individual signals of a bus For example, XAD[7:0] refers to signals 7-0 of the XAD bus. 1.2.3 Special terms The following terms have special meanings: Term Meaning asserted Refers to the state of a signal as follows: * An active-high signal is asserted when high (1). * An active-low signal is asserted when low (0). deasserted Refers to the state of a signal as follows: * An active-high signal is deasserted when low (0). * An active-low signal is deasserted when high (1). In some cases, deasserted signals are described as negated. reserved Refers to a memory space, register, or field that is either reserved for future use or for which, when written to, the module or chip behavior is unpredictable. w1c Write 1 to clear: Refers to a register bitfield that must be written as 1 to be "cleared." K22F Sub-Family Reference Manual, Rev. 4, 08/2016 46 NXP Semiconductors Chapter 2 Introduction 2.1 Overview This chapter provides high-level descriptions of the modules available on the devices covered by this document. 2.2 Module Functional Categories The modules on this device are grouped into functional categories. The following sections describe the modules assigned to each category in more detail. Table 2-1. Module functional categories Module category Description ARM(R) Cortex(R)-M4 core * 32-bit MCU core from ARM's Cortex-M class adding DSP instructions and single-precision floating point unit based on ARMv7 architecture System * System integration module * Power management and mode controllers * Multiple power modes available based on high speed run, run, wait, stop, and power-down modes * Low-leakage wakeup unit * Miscellaneous control module * Crossbar switch * Peripheral bridge * Direct memory access (DMA) controller with multiplexer to increase available DMA requests. * External watchdog monitor * Watchdog Memories * Internal memories include: * Program flash memory * SRAM * Serial programming interface: EzPort Clocks * Multiple clock generation options available from internally- and externallygenerated clocks * System oscillator to provide clock source for the MCU * RTC oscillator to provide clock source for the RTC Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 47 Module Functional Categories Table 2-1. Module functional categories (continued) Module category Description Security * Cyclic Redundancy Check module for error detection Analog * * * * * High speed analog-to-digital converter Comparator Digital-to-analog converter Internal voltage reference Bandgap voltage reference Timers * * * * * Programmable delay block FlexTimers Periodic interrupt timer Low power timer Independent real time clock Communications * * * * * * USB OTG controller with built-in FS/LS transceiver Serial peripheral interface Inter-integrated circuit (I2C) UART Low-power UART (LPUART) Integrated interchip sound (I2S) Human-Machine Interfaces (HMI) * General purpose input/output controller 2.2.1 ARM(R) Cortex(R)-M4 Core Modules The following core modules are available on this device. Table 2-2. Core modules Module Description ARM Cortex-M4 The ARM(R) Cortex(R)-M4 is the newest member of the Cortex M Series of processors targeting microcontroller cores focused on very cost sensitive, deterministic, interrupt driven environments. The Cortex M4 processor is based on the ARMv7 Architecture and Thumb(R)-2 ISA and is upward compatible with the Cortex M3, Cortex M1, and Cortex M0 architectures. Cortex M4 improvements include an ARMv7 Thumb-2 DSP (ported from the ARMv7-A/R profile architectures) providing 32-bit instructions with SIMD (single instruction multiple data) DSP style multiply-accumulates and saturating arithmetic. Floating point unit (FPU) A single-precision floating point unit (FPU) that is compliant to the IEEE Standard for Floating-Point Arithmetic (IEEE 754). NVIC The ARMv7-M exception model and nested-vectored interrupt controller (NVIC) implement a relocatable vector table supporting many external interrupts, a single non-maskable interrupt (NMI), and priority levels. The NVIC replaces shadow registers with equivalent system and simplified programmability. The NVIC contains the address of the function to execute for a particular handler. The address is fetched via the instruction port allowing parallel register stacking and look-up. The first sixteen entries are allocated to ARM internal sources with the others mapping to MCU-defined interrupts. AWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is to detect asynchronous wake-up events in stop modes and signal to clock control Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 48 NXP Semiconductors Chapter 2 Introduction Table 2-2. Core modules (continued) Module Description logic to resume system clocking. After clock restart, the NVIC observes the pending interrupt and performs the normal interrupt or event processing. Most of this device's debug is based on the ARM CoreSightTM architecture. Four debug interfaces are supported: Debug interfaces * * * * IEEE 1149.1 JTAG IEEE 1149.7 JTAG (cJTAG) Serial Wire Debug (SWD) ARM Real-Time Trace Interface 2.2.2 System Modules The following system modules are available on this device. Table 2-3. System modules Module Description System integration module (SIM) The SIM includes integration logic and several module configuration settings. System mode controller The SMC provides control and protection on entry and exit to each power mode, control for the Power management controller (PMC), and reset entry and exit for the complete MCU. Power management controller (PMC) The PMC provides the user with multiple power options that allow the user to optimize power consumption for the level of functionality needed. Includes poweron-reset (POR) and integrated low voltage detect (LVD) with reset (brownout) capability and selectable LVD trip points. Low-leakage wakeup unit (LLWU) The LLWU module allows the device to wake from low leakage power modes (LLS and VLLS) through various internal peripheral and external pin sources. Miscellaneous control module (MCM) The MCM includes integration logic Crossbar switch (XBS) The XBS connects bus masters and bus slaves, allowing all bus masters to access different bus slaves simultaneously and providing arbitration among the bus masters when they access the same slave. Peripheral bridges The peripheral bridge converts the crossbar switch interface to an interface to access a majority of peripherals on the device. DMA multiplexer (DMAMUX) The DMA multiplexer selects from many DMA requests down to a smaller number for the DMA controller. Direct memory access (DMA) controller The DMA controller provides programmable channels with transfer control descriptors for data movement via dual-address transfers for 8-bit, 16-bit, 32-bit, 16-byte and 32-byte data values. External watchdog monitor (EWM) The EWM is a redundant mechanism to the software watchdog module that monitors both internal and external system operation for fail conditions. Software watchdog (WDOG) The WDOG monitors internal system operation and forces a reset in case of failure. It can run from an independent 1 KHz low power oscillator with a programmable refresh window to detect deviations in program flow or system frequency. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 49 Module Functional Categories 2.2.3 Memories and Memory Interfaces The following memories and memory interfaces are available on this device. Table 2-4. Memories and memory interfaces Module Description Flash memory * Program flash memory -- non-volatile flash memory that can execute program code Flash memory controller Manages the interface between the device and the on-chip flash memory. SRAM Internal system RAM. Partial SRAM kept powered in LLS2 and VLLS2 low leakage mode. System register file 32-byte register file that is accessible during all power modes and is powered by VDD. VBAT register file 32-byte register file that is accessible during all power modes and is powered by VBAT. Serial programming interface (EzPort) Same serial interface as, and subset of, the command set used by industrystandard SPI flash memories. Provides the ability to read, erase, and program flash memory and reset command to boot the system after flash programming. 2.2.4 Clocks The following clock modules are available on this device. Table 2-5. Clock modules Module Description Multi-clock generator (MCG) The MCG provides several clock sources for the MCU that include: * Frequency-locked loop (FLL) -- Digitally-controlled oscillator (DCO) * Internal reference clocks -- Can be used as a clock source for other on-chip peripherals 48 MHz Internal Reference Clock (IRC48M) The IRC48M provides an internally generated clock source. Clock Recovery circuitry uses the incoming USB data stream to adjust the internal oscillator and enables the internal oscillator to meet the requirements for USB clock tolerance. System oscillator The system oscillator, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. Real-time clock oscillator The RTC oscillator has an independent power supply and supports a 32 kHz crystal oscillator to feed the RTC clock. Optionally, the RTC oscillator can replace the system oscillator as the main oscillator source. 2.2.5 Security and Integrity modules The following security and integrity modules are available on this device: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 50 NXP Semiconductors Chapter 2 Introduction Table 2-6. Security and integrity modules Module Description Cyclic Redundancy Check (CRC) Hardware CRC generator circuit using 16/32-bit shift register. Error detection for all single, double, odd, and most multi-bit errors, programmable initial seed value, and optional feature to transpose input data and CRC result via transpose register. 2.2.6 Analog modules The following analog modules are available on this device: Table 2-7. Analog modules Module Description 16-bit analog-to-digital converters (ADC) 16-bit successive-approximation ADC Analog comparators Compares two analog input voltages across the full range of the supply voltage. 6-bit digital-to-analog converters (DAC) 64-tap resistor ladder network which provides a selectable voltage reference for applications where voltage reference is needed. 12-bit digital-to-analog converters (DAC) Low-power general-purpose DAC, whose output can be placed on an external pin or set as one of the inputs to the analog comparator or ADC. Voltage reference (VREF) Supplies an accurate voltage output that is trimmable in 0.5 mV steps. The VREF can be used in medical applications, such as glucose meters, to provide a reference voltage to biosensors or as a reference to analog peripherals, such as the ADC, DAC, or CMP. 2.2.7 Timer modules The following timer modules are available on this device: Table 2-8. Timer modules Module Description Programmable delay block (PDB) * * * * * * * * 16-bit resolution 3-bit prescaler Positive transition of trigger event signal initiates the counter Supports two triggered delay output signals, each with an independentlycontrolled delay from the trigger event Outputs can be OR'd together to schedule two conversions from one input trigger event and can schedule precise edge placement for a pulsed output. This feature is used to generate the control signal for the CMP windowing feature and output to a package pin if needed for applications, such as critical conductive mode power factor correction. Continuous-pulse output or single-shot mode supported, each output is independently enabled, with possible trigger events Supports bypass mode Supports DMA Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 51 Module Functional Categories Table 2-8. Timer modules (continued) Module Description Flexible timer modules (FTM) * Selectable FTM source clock, programmable prescaler * 16-bit counter supporting free-running or initial/final value, and counting is up or up-down * Input capture, output compare, and edge-aligned and center-aligned PWM modes * Operation of FTM channels as pairs with equal outputs, pairs with complimentary outputs, or independent channels with independent outputs * Deadtime insertion is available for each complementary pair * Generation of hardware triggers * Software control of PWM outputs * Up to 4 fault inputs for global fault control * Configurable channel polarity * Programmable interrupt on input capture, reference compare, overflowed counter, or detected fault condition * Quadrature decoder with input filters, relative position counting, and interrupt on position count or capture of position count on external event * DMA support for FTM events Periodic interrupt timers (PIT) * * * * Low-power timer (LPTimer) * Selectable clock for prescaler/glitch filter of 1 kHz (internal LPO), 32.768 kHz (external crystal), or internal reference clock * Configurable Glitch Filter or Prescaler with 16-bit counter * 16-bit time or pulse counter with compare * Interrupt generated on Timer Compare * Hardware trigger generated on Timer Compare Real-time clock (RTC) * Independent power supply, POR, and 32 kHz Crystal Oscillator * 32-bit seconds counter with 32-bit Alarm * 16-bit Prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm Four general purpose interrupt timers Interrupt timers for triggering ADC conversions 32-bit counter resolution DMA support 2.2.8 Communication interfaces The following communication interfaces are available on this device: Table 2-9. Communication modules Module Description USB OTG (low-/full-speed) USB 2.0 compliant module with support for host, device, and On-The-Go modes. Includes an on-chip transceiver for full and low speeds. Serial peripheral interface (SPI) Synchronous serial bus for communication to an external device Inter-integrated circuit (I2C) Allows communication between a number of devices. Also supports the System Management Bus (SMBus) Specification, version 2. Universal asynchronous receiver/ transmitters (UART) Asynchronous serial bus communication interface with programmable 8- or 9-bit data format and support of ISO 7816 smart card interface Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 52 NXP Semiconductors Chapter 2 Introduction Table 2-9. Communication modules (continued) Module Description I2S The I2S is a full-duplex, serial port that allows the chip to communicate with a variety of serial devices, such as standard codecs, digital signal processors (DSPs), microprocessors, peripherals, and audio codecs that implement the interIC sound bus (I2S) and the Intel(R) AC97 standards LPUART Low power UART module that retains functionality in stop modes. 2.2.9 Human-machine interfaces The following human-machine interfaces (HMI) are available on this device: Table 2-10. HMI modules Module Description General purpose input/output (GPIO) All general purpose input or output (GPIO) pins are capable of interrupt and DMA request generation. 2.3 Orderable part numbers The following table summarizes the part numbers of the devices covered by this document. Table 2-11. Orderable part numbers summary Part number CPU Pin count Package frequency Program flash SRAM GPIO MK22FN128VDC10 100 MHz 121 XFBGA 128 KB 24 KB 67 MK22FN128VLL10 100 MHz 100 LQFP 128 KB 24 KB 66 MK22FN128VMP10 100 MHz 64 MAPBGA 128 KB 24 KB 40 MK22FN128VLH10 100 MHz 64 LQFP 128 KB 24 KB 40 MK22FN128CAK10R 100 MHz 49 WLCSP 128 KB 24 KB 35 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 53 Orderable part numbers K22F Sub-Family Reference Manual, Rev. 4, 08/2016 54 NXP Semiconductors Chapter 3 Chip Configuration 3.1 Introduction This chapter provides details on the individual modules of the microcontroller. It includes: * module block diagrams showing immediate connections within the device, * specific module-to-module interactions not necessarily discussed in the individual module chapters, and * links for more information. 3.2 Core modules 3.2.1 ARM Cortex-M4 Core Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 55 Core modules Debug Interrupts ARM Cortex-M4 Core Crossbar switch PPB PPB Modules Figure 3-1. Core configuration Table 3-1. Reference links to related information Topic Related module Reference Full description ARM Cortex-M4 core ARM Cortex-M4 Technical Reference Manual System memory map System memory map Clocking Clock distribution Power management Power management System/instruction/data bus module Crossbar switch Crossbar switch Debug IEEE 1149.1 JTAG Debug IEEE 1149.7 JTAG (cJTAG) Serial Wire Debug (SWD) ARM Real-Time Trace Interface Interrupts Nested Vectored Interrupt Controller (NVIC) NVIC Private Peripheral Bus (PPB) module Miscellaneous Control Module (MCM) MCM Private Peripheral Bus Single-precision floating (PPB) module point unit (FPU) FPU 3.2.1.1 Buses, interconnects, and interfaces The ARM Cortex-M4 core has four buses as described in the following table. Bus name Description Instruction code (ICODE) bus The ICODE and DCODE buses are muxed. This muxed bus is called the CODE bus and is connected to the crossbar switch via a single master port. Data code (DCODE) bus System bus The system bus is connected to a separate master port on the crossbar. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 56 NXP Semiconductors Chapter 3 Chip Configuration Bus name Private peripheral (PPB) bus Description The PPB provides access to these modules: * ARM modules such as the NVIC, ITM, DWT, FBP, and ROM table * Miscellaneous Control Module (MCM) 3.2.1.2 System Tick Timer The System Tick Timer's clock source is always the core clock, FCLK. This results in the following: * The CLKSOURCE bit in SysTick Control and Status register is always set to select the core clock. * Because the timing reference (FCLK) is a variable frequency, the TENMS bit in the SysTick Calibration Value Register is always zero. * The NOREF bit in SysTick Calibration Value Register is always set, implying that FCLK is the only available source of reference timing. 3.2.1.3 Debug facilities This device has extensive debug capabilities including run control and tracing capabilities. The standard ARM debug port that supports JTAG and SWD interfaces. Also the cJTAG interface is supported on this device. 3.2.1.4 Core privilege levels The ARM documentation uses different terms than this document to distinguish between privilege levels. If you see this term... it also means this term... Privileged Supervisor Unprivileged or user User 3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 57 Core modules Interrupts ARM Cortex-M4 core Module Nested Vectored Interrupt Controller (NVIC) PPB Module Module Figure 3-2. NVIC configuration Table 3-2. Reference links to related information Topic Related module Reference Full description Nested Vectored Interrupt Controller (NVIC) ARM Cortex-M4 Technical Reference Manual System memory map System memory map Clocking Clock distribution Power management Power management Private Peripheral Bus (PPB) ARM Cortex-M4 core ARM Cortex-M4 core 3.2.2.1 Interrupt priority levels This device supports 16 priority levels for interrupts. Therefore, in the NVIC each source in the IPR registers contains 4 bits. For example, IPR0 is shown below: 31 R W 30 29 IRQ3 28 27 26 25 24 0 0 0 0 23 22 21 IRQ2 20 19 18 17 16 0 0 0 0 15 14 13 IRQ1 12 11 10 9 8 0 0 0 0 7 6 5 IRQ0 4 3 2 1 0 0 0 0 0 3.2.2.2 Non-maskable interrupt The non-maskable interrupt request to the NVIC is controlled by the external NMI signal. The pin the NMI signal is multiplexed on, must be configured for the NMI function to generate the non-maskable interrupt request. 3.2.2.3 Interrupt channel assignments The interrupt source assignments are defined in the following table. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 58 NXP Semiconductors Chapter 3 Chip Configuration * Vector number -- the value stored on the stack when an interrupt is serviced. * IRQ number -- non-core interrupt source count, which is the vector number minus 16. The IRQ number is used within ARM's NVIC documentation. Table 3-4. Interrupt vector assignments Address IRQ1 Vector NVIC NVIC non-IPR IPR register register number number 2 Source module Source description 3 ARM Core System Handler Vectors 0x0000_0000 0 - - - ARM core Initial Stack Pointer 0x0000_0004 1 - - - ARM core Initial Program Counter 0x0000_0008 2 - - - ARM core Non-maskable Interrupt (NMI) 0x0000_000C 3 - - - ARM core Hard Fault 0x0000_0010 4 - - - ARM core MemManage Fault 0x0000_0014 5 - - - ARM core Bus Fault 0x0000_0018 6 - - - ARM core Usage Fault 0x0000_001C 7 - - - -- -- 0x0000_0020 8 - - - -- -- 0x0000_0024 9 - - - -- -- 0x0000_0028 10 - - - -- -- 0x0000_002C 11 - - - ARM core Supervisor call (SVCall) 0x0000_0030 12 - - - ARM core Debug Monitor 0x0000_0034 13 - - - -- -- 0x0000_0038 14 - - - ARM core Pendable request for system service (PendableSrvReq) 0x0000_003C 15 - - - ARM core System tick timer (SysTick) 0x0000_0040 16 0 0 0 DMA DMA channel 0 transfer complete 0x0000_0044 17 1 0 0 DMA DMA channel 1 transfer complete 0x0000_0048 18 2 0 0 DMA DMA channel 2 transfer complete 0x0000_004C 19 3 0 0 DMA DMA channel 3 transfer complete 0x0000_0050 20 4 0 1 - - 0x0000_0054 21 5 0 1 - - 0x0000_0058 22 6 0 1 - - 0x0000_005C 23 7 0 1 - - 0x0000_0060 24 8 0 2 - - 0x0000_0064 25 9 0 2 - - 0x0000_0068 26 10 0 2 - - 0x0000_006C 27 11 0 2 - - Non-Core Vectors Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 59 Core modules Table 3-4. Interrupt vector assignments (continued) Address Vector IRQ1 NVIC NVIC non-IPR IPR register register number number 2 Source module Source description 3 0x0000_0070 28 12 0 3 - - 0x0000_0074 29 13 0 3 - - 0x0000_0078 30 14 0 3 - - 0x0000_007C 31 15 0 3 - - 0x0000_0080 32 16 0 4 DMA DMA error interrupt channels 0-3 0x0000_0084 33 17 0 4 MCM FPU sources 0x0000_0088 34 18 0 4 Flash memory Command complete 0x0000_008C 35 19 0 4 Flash memory Read collision 0x0000_0090 36 20 0 5 Mode Controller Low-voltage detect, low-voltage warning 0x0000_0094 37 21 0 5 LLWU Low Leakage Wakeup NOTE: The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery. 0x0000_0098 38 22 0 5 WDOG or EWM Both watchdog modules share this interrupt. 0x0000_009C 39 23 0 5 -- -- -- 0x0000_00A0 40 24 0 6 I2C0 0x0000_00A4 41 25 0 6 I2C1 -- 0x0000_00A8 42 26 0 6 SPI0 Single interrupt vector for all sources 0x0000_00AC 43 27 0 6 SPI1 Single interrupt vector for all sources 7 I2S0 Transmit Receive 0x0000_00B0 44 28 0 0x0000_00B4 45 29 0 7 I2S0 0x0000_00B8 46 30 0 7 LPUART0 Status and error 0x0000_00BC 47 31 0 7 UART0 Single interrupt vector for UART status sources 0x0000_00C0 48 32 1 8 UART0 Single interrupt vector for UART error sources 0x0000_00C4 49 33 1 8 UART1 Single interrupt vector for UART status sources 0x0000_00C8 50 34 1 8 UART1 Single interrupt vector for UART error sources 0x0000_00CC 51 35 1 8 UART2 Single interrupt vector for UART status sources 0x0000_00D0 52 36 1 9 UART2 Single interrupt vector for UART error sources 0x0000_00D4 53 37 1 9 -- -- 0x0000_00D8 54 38 1 9 -- -- Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 60 NXP Semiconductors Chapter 3 Chip Configuration Table 3-4. Interrupt vector assignments (continued) Address Vector IRQ1 NVIC NVIC non-IPR IPR register register number number 2 Source module Source description 3 0x0000_00DC 55 39 1 9 ADC0 -- 0x0000_00E0 56 40 1 10 CMP0 -- 0x0000_00E4 57 41 1 10 CMP1 -- 0x0000_00E8 58 42 1 10 FTM0 Single interrupt vector for all sources 0x0000_00EC 59 43 1 10 FTM1 Single interrupt vector for all sources 0x0000_00F0 60 44 1 11 FTM2 Single interrupt vector for all sources 0x0000_00F4 61 45 1 11 -- -- 0x0000_00F8 62 46 1 11 RTC Alarm interrupt 0x0000_00FC 63 47 1 11 RTC Seconds interrupt 0x0000_0100 64 48 1 12 PIT Channel 0 0x0000_0104 65 49 1 12 PIT Channel 1 0x0000_0108 66 50 1 12 PIT Channel 2 0x0000_010C 67 51 1 12 PIT Channel 3 0x0000_0110 68 52 1 13 PDB -- 0x0000_0114 69 53 1 13 USB OTG -- 0x0000_0118 70 54 1 13 -- -- 0x0000_011C 71 55 1 13 -- -- 0x0000_0120 72 56 1 14 DAC0 -- 0x0000_0124 73 57 1 14 MCG -- 0x0000_0128 74 58 1 14 Low Power Timer -- 0x0000_012C 75 59 1 14 Port control module Pin detect (Port A) 0x0000_0130 76 60 1 15 Port control module Pin detect (Port B) 0x0000_0134 77 61 1 15 Port control module Pin detect (Port C) 0x0000_0138 78 62 1 15 Port control module Pin detect (Port D) 0x0000_013C 79 63 1 15 Port control module Pin detect (Port E) 0x0000_0140 80 64 2 16 Software Software interrupt4 0x0000_0144 81 65 2 16 -- -- 0x0000_0148 82 66 2 16 -- -- 0x0000_014C 83 67 2 16 -- -- 0x0000_0150 84 68 2 17 -- -- 0x0000_0154 85 69 2 17 -- -- 0x0000_0158 86 70 2 17 -- -- 0x0000_015C 87 71 2 17 -- -- 0x0000_0160 88 72 2 18 -- -- 0x0000_0164 89 73 2 18 ADC1 -- 1. Indicates the NVIC's interrupt source number. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 61 Core modules 2. Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this value is: IRQ div 32 3. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4 4. This interrupt can only be pended or cleared via the NVIC registers. 3.2.2.3.1 Determining the bitfield and register location for configuring a particular interrupt Suppose you need to configure the low-power timer (LPTMR) interrupt. The following table is an excerpt of the LPTMR row from Interrupt channel assignments. Table 3-5. LPTMR interrupt vector assignment Address IRQ1 Vector NVIC NVIC non-IPR IPR register register number number 2 0x0000_0128 74 58 1 Source module Source description 3 14 Low Power Timer -- 1. Indicates the NVIC's interrupt source number. 2. Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this value is: IRQ div 32 3. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4 * The NVIC registers you would use to configure the interrupt are: * NVICISER1 * NVICICER1 * NVICISPR1 * NVICICPR1 * NVICIABR1 * NVICIPR14 * To determine the particular IRQ's bitfield location within these particular registers: * NVICISER1, NVICICER1, NVICISPR1, NVICICPR1, NVICIABR1 bit location = IRQ mod 32 = 26 * NVICIPR14 bitfield starting location = 8 * (IRQ mod 4) + 4 = 20 Since the NVICIPR bitfields are 4-bit wide (16 priority levels), the NVICIPR14 bitfield range is 20-23 Therefore, the following bitfield locations are used to configure the LPTMR interrupts: * * * * * * NVICISER1[26] NVICICER1[26] NVICISPR1[26] NVICICPR1[26] NVICIABR1[26] NVICIPR14[23:20] K22F Sub-Family Reference Manual, Rev. 4, 08/2016 62 NXP Semiconductors Chapter 3 Chip Configuration 3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com. Clock logic Wake-up requests Asynchronous Wake-up Interrupt Controller (AWIC) Nested vectored interrupt controller (NVIC) Module Module Figure 3-3. Asynchronous Wake-up Interrupt Controller configuration Table 3-6. Reference links to related information Topic Related module Reference System memory map System memory map Clocking Clock distribution Power management Power management Nested Vectored Interrupt Controller (NVIC) Wake-up requests NVIC AWIC wake-up sources 3.2.3.1 Wake-up sources The device uses the following internal and external inputs to the AWIC module. Table 3-7. AWIC Partial Stop, Stop and VLPS Wake-up Sources Wake-up source Description Available system resets RESET pin and WDOG when LPO is its clock source, and JTAG Low-voltage detect Power Mode Controller Low-voltage warning Power Mode Controller Pin interrupts Port Control Module - Any enabled pin interrupt is capable of waking the system ADCx The ADC is functional when using internal clock source Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 63 Core modules Table 3-7. AWIC Partial Stop, Stop and VLPS Wake-up Sources (continued) Wake-up source Description CMPx Since no system clocks are available, functionality is limited, trigger mode provides wakeup functionality with periodic sampling I2C Address match wakeup UART Active edge on RXD LPUART Functional when using clock source which is active in Stop and VLPS modes USB FS/LS Controller Wakeup LPTMR Functional when using clock source which is active in Stop and VLPS modes RTC Functional in Stop/VLPS modes I2S (SAI) Functional when using an external bit clock or external master clock NMI Non-maskable interrupt 3.2.4 FPU Configuration ARM Cortex M4 Core This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. PPB Transfers FPU Figure 3-4. FPU configuration Table 3-8. Reference links to related information Topic Related module Reference Full description FPU ARM Cortex-M4 Technical Reference Manual System memory map System memory map Clocking Clock Distribution Power Management Transfers Power Management ARM Cortex M4 core ARM Cortex-M4 core Private Peripheral Bus (PPB) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 64 NXP Semiconductors Chapter 3 Chip Configuration 3.2.5 JTAG Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. JTAG controller cJTAG Signal multiplexing Figure 3-5. JTAGC Controller configuration Table 3-9. Reference links to related information Topic Related module Reference Full description JTAGC JTAGC Signal multiplexing Port control Signal multiplexing 3.3 System modules 3.3.1 SIM Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access System integration module (SIM) Figure 3-6. SIM configuration Table 3-10. Reference links to related information Topic Related module Full description SIM System memory map Reference System memory map Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 65 System modules Table 3-10. Reference links to related information (continued) Topic Related module Reference Clocking Clock distribution Power management Power management 3.3.2 System Mode Controller (SMC) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access Resets System Mode Controller (SMC) Power Management Controller (PMC) Figure 3-7. System Mode Controller configuration Table 3-11. Reference links to related information Topic Related module Reference Full description System Mode Controller (SMC) SMC System memory map System memory map Power management Power management Power management controller (PMC) PMC Low-Leakage Wakeup Unit (LLWU) LLWU Reset Control Module (RCM) Reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 66 NXP Semiconductors Chapter 3 Chip Configuration 3.3.3 PMC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Table 3-12. Reference links to related information Topic Related module Full description PMC Reference System memory map System memory map Power management Power management Full description Low-Leakage Wakeup Unit (LLWU) LLWU 3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge 0 Register access Wake-up requests Power Management Controller (PMC) Low-Leakage Wake-up Unit (LLWU) Module Module Figure 3-8. Low-Leakage Wake-up Unit configuration Table 3-13. Reference links to related information Topic Related module Full description LLWU System memory map Reference System memory map Clocking Clock distribution Power management Power management chapter Power Management Controller (PMC) Power Management Controller (PMC) Mode Controller Wake-up requests LLWU wake-up sources K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 67 System modules 3.3.4.1 Wake-up Sources The device uses the following internal peripheral and external pin inputs as wakeup sources to the LLWU module. LLWU_Px are external pin inputs, and LLWU_M0IFM7IF are connections to the internal peripheral interrupt flags. NOTE In addition to the LLWU wakeup sources, the device also wakes from low power modes when NMI or RESET pins are enabled and the respective pin is asserted. Table 3-14. Wakeup sources for LLWU inputs Input Wakeup source LLWU_P0 PTE1/LLWU_P0 pin LLWU_P1 PTE2/LLWU_P1 pin LLWU_P2 PTE4/LLWU_P2 pin LLWU_P3 PTA4/LLWU_P3 pin1 LLWU_P4 PTA13/LLWU_P4 pin LLWU_P5 PTB0/LLWU_P5 pin LLWU_P6 PTC1/LLWU_P6 pin LLWU_P7 PTC3/LLWU_P7 pin LLWU_P8 PTC4/LLWU_P8 pin LLWU_P9 PTC5/LLWU_P9 pin LLWU_P10 PTC6/LLWU_P10 pin LLWU_P11 PTC11/LLWU_P11 pin LLWU_P12 PTD0/LLWU_P12 pin LLWU_P13 PTD2/LLWU_P13 pin LLWU_P14 PTD4/LLWU_P14 pin LLWU_P15 PTD6/LLWU_P15 pin LLWU_M0IF LPTMR2 LLWU_M1IF CMP02 LLWU_M2IF CMP12 LLWU_M3IF Reserved LLWU_M4IF Reserved LLWU_M5IF RTC Alarm2 LLWU_M6IF Reserved LLWU_M7IF RTC Seconds2 1. The EZP_CS signal is checked only on Chip Reset not VLLS, so a VLLS wakeup via a non-reset source does not cause EzPort mode entry. If NMI was enabled on entry to LLS/VLLS, asserting the NMI pin generates an NMI interrupt on exit from the low power mode. NMI can also be disabled via the FOPT[NMI_DIS] bit. 2. Requires the peripheral and the peripheral interrupt to be enabled. The LLWU's WUME bit enables the internal module flag as a wakeup input. After wakeup, the flags are cleared based on the peripheral clearing mechanism. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 68 NXP Semiconductors Chapter 3 Chip Configuration 3.3.5 MCM Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. ARM Cortex-M4 core PPB Transfers Miscellaneous Control Module (MCM) Figure 3-9. MCM configuration Table 3-15. Reference links to related information Topic Related module Reference Full description Miscellaneous control module (MCM) MCM System memory map System memory map Clocking Clock distribution Power management Power management Transfers ARM Cortex-M4 core ARM Cortex-M4 core Private Peripheral Bus (PPB) 3.3.6 Crossbar-Light Switch Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 69 System modules Master Modules Slave Modules S0 SRAM controller_L M2 DMA Mux Flash controller S1 ARM core system bus M1 ARM core code bus M0 Crossbar Switch S2 EzPort SRAM controller_U USB Mux GPIO controller M4 S3 Peripheral bridge 0 Figure 3-10. Crossbar-Light switch integration Table 3-16. Reference links to related information Topic Related module Reference Full description Crossbar switch Crossbar Switch System memory map System memory map Clocking Clock Distribution Crossbar switch master ARM Cortex-M4 core ARM Cortex-M4 core Crossbar switch master DMA controller DMA controller Crossbar switch master EzPort EzPort Crossbar switch master USB FS/LS USB FS/LS Crossbar switch slave Flash Flash Crossbar switch slave Peripheral bridges Peripheral bridge Crossbar switch slave GPIO controller GPIO controller K22F Sub-Family Reference Manual, Rev. 4, 08/2016 70 NXP Semiconductors Chapter 3 Chip Configuration 3.3.6.1 Crossbar-Light Switch Master Assignments The masters connected to the crossbar switch are assigned as follows: Master module Master port number ARM core code bus 0 ARM core system bus 1 DMA /EzPort 2 USB OTG 4 NOTE The DMA and EzPort share a master port. Since these modules never operate at the same time, no configuration or arbitration explanations are necessary. 3.3.6.2 Crossbar-Light Switch Slave Assignments The slaves connected to the crossbar switch are assigned as follows: Slave module Slave port number Flash memory controller 0 SRAM controllers 1,2 Peripheral bridge 0/GPIO1 3 1. See System memory map for access restrictions. 3.3.7 Peripheral Bridge Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 71 System modules Crossbar switch Transfers AIPS-Lite peripheral bridge Transfers Peripherals Figure 3-11. Peripheral bridge configuration Table 3-17. Reference links to related information Topic Related module Reference Full description Peripheral bridge (AIPS-Lite) Peripheral bridge (AIPS-Lite) System memory map System memory map Clocking Clock Distribution Crossbar switch Crossbar switch Crossbar switch 3.3.7.1 Number of peripheral bridges This device contains one peripheral bridge. 3.3.7.2 Memory maps The peripheral bridges are used to access the registers of most of the modules on this device. See AIPS0 Memory Map for the memory slot assignment for each module. 3.3.8 DMA request multiplexer configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 72 NXP Semiconductors Chapter 3 Chip Configuration Peripheral bridge 0 Register access Requests DMA controller Channel request DMA Request Multiplexer Module Module Module Figure 3-12. DMA request multiplexer configuration Table 3-18. Reference links to related information Topic Related module Reference Full description DMA request multiplexer DMA Mux System memory map System memory map Clocking Clock distribution Power management Power management Channel request DMA controller DMA Controller Requests DMA request sources 3.3.8.1 DMA MUX request sources This device includes a DMA request mux that allows up to 63 DMA request signals to be mapped to any of the 4 DMA channels. Because of the mux there is not a hard correlation between any of the DMA request sources and a specific DMA channel. Some of the modules support Asynchronous DMA operation as indicated by the last column in the following DMA source assignment table. Table 3-19. DMA request sources - MUX 0 Source number Source module Source description 0 -- Channel disabled1 1 Reserved Not used 2 UART0 Receive 3 UART0 Transmit 4 UART1 Receive 5 UART1 Transmit 6 UART2 Receive 7 UART2 Transmit Async DMA capable Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 73 System modules Table 3-19. DMA request sources - MUX 0 (continued) Source number Source module Source description Async DMA capable 8 Reserved -- 9 Reserved -- 10 Reserved -- 11 Reserved -- 12 I2S0 Receive Yes 13 I2S0 Transmit Yes 14 SPI0 Receive 15 SPI0 Transmit 16 SPI1 Transmit or Receive 17 Reserved -- 18 I2C0 -- 19 I2C1 -- 20 FTM0 Channel 0 21 FTM0 Channel 1 22 FTM0 Channel 2 23 FTM0 Channel 3 24 FTM0 Channel 4 25 FTM0 Channel 5 26 FTM0 Channel 6 27 FTM0 Channel 7 28 FTM1 Channel 0 29 FTM1 Channel 1 30 FTM2 Channel 0 31 FTM2 Channel 1 32 Reserved -- 33 Reserved -- 34 Reserved -- 35 Reserved -- 36 Reserved -- 37 Reserved -- 38 Reserved -- 39 Reserved -- 40 ADC0 -- Yes 41 ADC1 -- Yes 42 CMP0 -- Yes 43 CMP1 -- Yes 44 Reserved -- 45 DAC0 -- 46 Reserved -- Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 74 NXP Semiconductors Chapter 3 Chip Configuration Table 3-19. DMA request sources - MUX 0 (continued) Source number Source module Source description Async DMA capable 47 Reserved -- 48 PDB -- 49 Port control module Port A Yes 50 Port control module Port B Yes 51 Port control module Port C Yes 52 Port control module Port D Yes 53 Port control module Port E Yes 54 Reserved -- 55 Reserved -- 56 Reserved -- 57 Reserved -- 58 LPUART0 Receive Yes 59 LPUART0 Transmit Yes 60 DMA MUX Always enabled 61 DMA MUX Always enabled 62 DMA MUX Always enabled 63 DMA MUX Always enabled 1. Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel. 3.3.8.2 DMA transfers via PIT trigger The PIT module can trigger a DMA transfer on the first four DMA channels. The assignments are detailed at PIT/DMA Periodic Trigger Assignments . 3.3.9 DMA Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 75 System modules Peripheral bridge 0 Register access Crossbar switch Transfers DMA Controller Requests DMA Multiplexer Figure 3-13. DMA Controller configuration Table 3-20. Reference links to related information Topic Related module Reference Full description DMA Controller DMA Controller System memory map Register access System memory map Peripheral bridge (AIPS-Lite 0) AIPS-Lite 0 Clocking Clock distribution Power management Power management Transfers Crossbar switch Crossbar switch 3.3.10 External Watchdog Monitor (EWM) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 76 NXP Semiconductors Chapter 3 Chip Configuration Peripheral bridge 0 Register access External Watchdog Monitor (EWM) Module signals Signal multiplexing Figure 3-14. External Watchdog Monitor configuration Table 3-21. Reference links to related information Topic Related module Reference Full description External Watchdog Monitor (EWM) EWM System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port Control Module Signal multiplexing 3.3.10.1 EWM clocks This table shows the EWM clocks and the corresponding chip clocks. Table 3-22. EWM clock connections Module clock Low Power Clock Chip clock 1 kHz LPO Clock 3.3.10.2 EWM low-power modes This table shows the EWM low-power modes and the corresponding chip low-power modes. Table 3-23. EWM low-power modes Module mode Chip mode Wait Wait, VLPW Stop Stop, VLPS, LLS K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 77 System modules 3.3.10.3 EWM_OUT pin state in low power modes When the CPU enters a Run mode from Wait or Stop recovery, the pin resumes its previous state before entering Wait or Stop mode. When the CPU enters Run mode from Power Down, the pin returns to its reset state. 3.3.11 Watchdog Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge 0 Register access Mode Controller WDOG Figure 3-15. Watchdog configuration Table 3-24. Reference links to related information Topic Related module Reference Full description Watchdog Watchdog System memory map System memory map Clocking Clock distribution Power management Power management Mode Controller (MC) 3.3.11.1 WDOG clocks This table shows the WDOG module clocks and the corresponding chip clocks. Table 3-25. WDOG clock connections Module clock LPO Oscillator Chip clock 1 kHz LPO Clock Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 78 NXP Semiconductors Chapter 3 Chip Configuration Table 3-25. WDOG clock connections (continued) Module clock Chip clock Alt Clock Bus Clock Fast Test Clock Bus Clock System Bus Clock Bus Clock 3.3.11.2 WDOG low-power modes This table shows the WDOG low-power modes and the corresponding chip low-power modes. Table 3-26. WDOG low-power modes Module mode Chip mode Wait Wait, VLPW Stop Stop, VLPS Power Down LLS, VLLSx 3.4 Clock modules 3.4.1 MCG Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 79 Clock modules Peripheral bridge Register access System oscillator System integration module (SIM) Multipurpose Clock Generator (MCG) RTC oscillator Figure 3-16. MCG configuration Table 3-27. Reference links to related information Topic Related module Reference Full description MCG MCG System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.4.1.1 MCG oscillator clock input options The MCG has multiple oscillator input clock sources. Within the context of the MCG these are all referred to as the external reference clock and selection is determined by MCG_C7[OSCSEL] bitfield. The following table shows the chip-specific clock assignments for this bitfield. Table 3-28. MCG Oscillator Reference Options MCG_C7[OSCSEL] MCG defined selection Chip clock 00 OSCCLK0 - System Oscillator OSCCLK - Undivided system oscillator output. Derived from external crystal circuit or directly from EXTAL. 01 OSC2/RTC Oscillator RTC 32kHz oscillator output. RTC clock is derived from external crystal circuit associated with RTC. 10 OSCCLK1 - Oscillator IRC48MCLK. Derived from internal 48 MHz oscillator. 11 Reserved -- See Clock Distribution for more details on these clocks. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 80 NXP Semiconductors Chapter 3 Chip Configuration 3.4.2 OSC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access System oscillator MCG Module signals Signal multiplexing Figure 3-17. OSC configuration Table 3-29. Reference links to related information Topic Related module Reference Full description OSC OSC System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing Full description MCG MCG 3.4.2.1 OSC modes of operation with MCG The MCG's C2 register bits configure the oscillator frequency range. See the OSC and MCG chapters for more details. 3.4.3 RTC OSC configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 81 Memories and memory interfaces 32-kHz RTC oscillator MCG Module signals Signal multiplexing Figure 3-18. RTC OSC configuration Table 3-30. Reference links to related information Topic Related module Reference Full description RTC OSC RTC OSC Signal multiplexing Port control Signal multiplexing Full description MCG MCG 3.5 Memories and memory interfaces 3.5.1 Flash Memory Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge 0 Register access Flash memory controller Transfers Flash memory Figure 3-19. Flash memory configuration Table 3-31. Reference links to related information Topic Related module Full description Flash memory Reference System memory map System memory map Clocking Clock Distribution Transfers Flash memory controller Flash memory controller Register access Peripheral bridge Peripheral bridge K22F Sub-Family Reference Manual, Rev. 4, 08/2016 82 NXP Semiconductors Chapter 3 Chip Configuration 3.5.1.1 Flash memory types This device contains the following types of flash memory: * Program flash memory -- non-volatile flash memory that can execute program code 3.5.1.2 Flash Memory Sizes The devices covered in this document contain: * 1 block of program flash consisting of 2 KB sectors The amounts of flash memory for the devices covered in this document are: Device Program flash (KB) Block 0 address range MK22FN128VDC10 128 0x0000_0000-0x0001_FFFF MK22FN128VLL10 128 0x0000_0000-0x0001_FFFF MK22FN128VMP10 128 0x0000_0000-0x0001_FFFF MK22FN128VLH10 128 0x0000_0000-0x0001_FFFF MK22FN128CAK10R 128 0x0000_0000-0x0001_FFFF 3.5.1.3 Flash Memory Map The flash memory and the flash registers are located at different base addresses as shown in the following figure. The base address for each is specified in System memory map. Flash memory base address Registers Program flash base address Flash configuration field Program flash Figure 3-20. Flash memory map The on-chip Flash is implemented in a portion of the allocated Flash range to form a contiguous block in the memory map beginning at address 0x0000_0000. See Flash Memory Sizes for details of supported ranges. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 83 Memories and memory interfaces Accesses to the flash memory ranges outside the amount of Flash on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. Read collision events in which flash memory is accessed while a flash memory resource is being manipulated by a flash command also generates a bus error response. 3.5.1.4 Flash Security How flash security is implemented on this device is described in Chip Security. 3.5.1.5 Flash Program Restrictions The flash memory on this device should not be programmed or erased while operating in High Speed Run or VLPR power modes. 3.5.1.6 Flash Modes The flash memory operates in NVM normal and NVM special modes. The flash memory enters NVM special mode when the EzPort is enabled (EZP_CS asserted during reset). Otherwise, flash memory operates in NVM normal mode. 3.5.1.7 Erase All Flash Contents The flash of the MCU is protected from erasing all of the flash contents by the FTFA_FSEC[MEEN] bits. If the bits are set to 'b10 mass erase is disabled. An Erase All Flash Blocks operation can be launched by software through a series of peripheral bus writes to flash registers. In addition the entire flash memory may be erased external to the flash memory from the SWJ-DP debug port by setting DAP_CONTROL[0]. DAP_STATUS[0] is set to indicate the mass erase command has been accepted. DAP_STATUS[0] is cleared when the mass erase completes. The EzPort can also initiate an erase of flash contents by issuing a bulk erase (BE) command. See the EzPort chapter for more details. 3.5.1.8 FTF_FOPT Register The flash memory's FTF_FOPT register allows the user to customize the operation of the MCU at boot time. See FOPT boot options for details of its definition. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 84 NXP Semiconductors Chapter 3 Chip Configuration 3.5.2 Flash Memory Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge 0 Register access Crossbar switch Transfers Flash memory controller Transfers Flash memory Figure 3-21. Flash memory controller configuration Table 3-32. Reference links to related information Topic Related module Reference Full description Flash memory controller Flash memory controller System memory map System memory map Clocking Clock Distribution Transfers Flash memory Flash memory Transfers Crossbar switch Crossbar Switch Register access Peripheral bridge Peripheral bridge 3.5.2.1 Number of masters The Flash Memory Controller supports up to eight crossbar switch masters. However, this device has a different number of crossbar switch masters. See Crossbar-Light Switch Configuration for details on the master port assignments. 3.5.3 SRAM Configuration This section summarizes how the module has been configured in the chip. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 85 Memories and memory interfaces Cortex-M4 core crossbar SRAM controller SRAM upper Transfers switch SRAM controller SRAM lower Figure 3-22. SRAM configuration Table 3-33. Reference links to related information Topic Related module Reference Full description SRAM SRAM System memory map System memory map Clocking Clock Distribution Transfers SRAM controller SRAM controller ARM Cortex-M4 core ARM Cortex-M4 core 3.5.3.1 SRAM sizes This device contains SRAM accessed by bus masters through the cross-bar switch. The on-chip SRAM is split into SRAM_L and SRAM_U regions where the SRAM_L and SRAM_U ranges form a contiguous block in the memory map anchored at address 0x2000_0000. As such: * SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending address. * SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning address. NOTE Misaligned accesses across the 0x2000_0000 boundary are not supported in the ARM Cortex-M4 architecture. The amount of SRAM for the devices covered in this document is shown in the following table. Device SRAM_L size (KB) SRAM_U size (KB) Total SRAM (KB) Address Range MK22FN128VDC10 8 16 24 0x1FFF_E000-0x2000_3FFF MK22FN128VLL10 8 16 24 0x1FFF_E000-0x2000_3FFF MK22FN128VLH10 8 16 24 0x1FFF_E000-0x2000_3FFF Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 86 NXP Semiconductors Chapter 3 Chip Configuration Device SRAM_L size (KB) SRAM_U size (KB) Total SRAM (KB) Address Range MK22FN128VMP10 8 16 24 0x1FFF_E000-0x2000_3FFF MK22FN128CAK10R 8 16 24 0x1FFF_E000-0x2000_3FFF 3.5.3.2 SRAM retention in low power modes The SRAM is retained down to LLS3 and VLLS3 mode. In LLS2 and VLLS2 the 8 KB region of SRAM_U from 0x2000_0000 is powered. In VLLS1 and VLLS0 no SRAM is retained; however, the 32-byte register file is available. 3.5.4 System Register File Configuration This section summarizes how the module has been configured in the chip. Peripheral bridge 0 Register access Register file Figure 3-23. System Register file configuration Table 3-34. Reference links to related information Topic Related module Reference Full description Register file Register file System memory map System memory map Clocking Clock distribution Power management Power management K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 87 Memories and memory interfaces 3.5.4.1 System Register file This device includes a 32-byte register file that is powered in all power modes. The System Register file is made up of eight 4-byte registers RFSYS_REGn, where n ranges from 0 to 7. Also, it retains contents during low-voltage detect (LVD) events and is only reset during a power-on reset. 3.5.5 VBAT Register File Configuration This section summarizes how the module has been configured in the chip. Peripheral bridge Register access VBAT register file Figure 3-24. VBAT Register file configuration Table 3-35. Reference links to related information Topic Related module Reference Full description VBAT register file VBAT register file System memory map System memory map Clocking Clock distribution Power management Power management 3.5.5.1 VBAT register file This device includes a 32-byte register file that is powered in all power modes and is powered by VBAT. The VBAT Register file is made up of eight 4-byte registers RFVBAT_REGn, where n ranges from 0 to 7. It is only reset during VBAT power-on reset. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 88 NXP Semiconductors Chapter 3 Chip Configuration 3.5.6 EzPort Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Transfers Crossbar switch EzPort Module signals Signal multiplexing Figure 3-25. EzPort configuration Table 3-36. Reference links to related information Topic Related module Reference Full description EzPort EzPort System memory map System memory map Clocking Clock Distribution Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing 3.5.6.1 JTAG instruction The system JTAG controller implements an EZPORT instruction. When executing this instruction, the JTAG controller resets the core logic and asserts the EzPort chip select signal to force the processor into EzPort mode. 3.5.6.2 Flash Option Register (FOPT) The FOPT[EZPORT_DIS] bit can be used to prevent entry into EzPort mode during reset. If the FOPT[EZPORT_DIS] bit is cleared, then the state of the chip select signal (EZP_CS) is ignored and the MCU always boots in normal mode. This option is useful for systems that use the EZP_CS/NMI signal configured for its NMI function. Disabling EzPort mode prevents possible unwanted entry into EzPort mode if the external circuit that drives the NMI signal asserts it during reset. The FOPT register is loaded from the flash option byte. If the flash option byte is modified the new value takes effect for any subsequent resets, until the value is changed again. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 89 Security 3.6 Security 3.6.1 CRC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access CRC Figure 3-26. CRC configuration Table 3-37. Reference links to related information Topic Related module Reference Full description CRC CRC System memory map System memory map Power management Power management 3.7 Analog 3.7.1 16-bit SAR ADC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 90 NXP Semiconductors Chapter 3 Chip Configuration Peripheral bus controller 0 Register access Other peripherals Transfers 16-bit SAR ADC Module signals Signal multiplexing Figure 3-27. 16-bit SAR ADC configuration Table 3-38. Reference links to related information Topic Related module Reference Full description 16-bit SAR ADC 16-bit SAR ADC System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.1.1 ADC instantiation information This device contains two ADCs. 3.7.1.1.1 Number of ADC channels The number of ADC channels present on the device is determined by the pinout of the specific device package. For details regarding the number of ADC channel available on a particular package, refer to the signal multiplexing chapter of this MCU. 3.7.1.2 DMA Support on ADC Applications may require continuous sampling of the ADC (4K samples/sec) that may have considerable load on the CPU. Though using PDB to trigger ADC may reduce some CPU load, the ADC supports DMA request functionality for higher performance when the ADC is sampled at a very high rate or cases where PDB is bypassed. The ADC can trigger the DMA (via DMA req) on conversion completion. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 91 Analog 3.7.1.3 ADCx Connections/Channel Assignment NOTE As indicated by the following sections, each ADCx_DPx input and certain ADCx_DMx inputs may operate as single-ended ADC channels in single-ended mode. 3.7.1.3.1 ADC0 channel assignment ADC Channel Table 3-39. ADC0 Assignments Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0) 00000 DAD0 ADC0_DP0 and ADC0_DM0 ADC0_DP0 00001 DAD1 ADC0_DP1 and ADC0_DM1 ADC0_DP1 00010 DAD2 ADC0_DP2 and ADC0_DM2 ADC0_DP2 00011 DAD3 ADC0_DP3 and ADC0_DM3 ADC0_DP3 001001 AD4a Reserved Reserved 001011 AD5a Reserved Reserved 001101 AD6a Reserved Reserved 001111 AD7a Reserved Reserved 001001 AD4b Reserved ADC0_SE4b 001011 AD5b Reserved ADC0_SE5b 001101 AD6b Reserved ADC0_SE6b 001111 AD7b Reserved ADC0_SE7b 01000 AD8 Reserved ADC0_SE8 01001 AD9 Reserved ADC0_SE9 01010 AD10 Reserved Reserved 01011 AD11 Reserved Reserved 01100 AD12 Reserved ADC0_SE12 01101 AD13 Reserved ADC0_SE13 01110 AD14 Reserved ADC0_SE14 01111 AD15 Reserved ADC0_SE15 10000 AD16 Reserved Reserved 10001 AD17 Reserved ADC0_SE17 10010 AD18 Reserved ADC0_SE18 10011 AD19 Reserved ADC0_DM0 10100 AD20 Reserved ADC0_DM1 10101 AD21 Reserved Reserved 10110 AD22 Reserved Reserved 10111 AD23 Reserved 12-bit DAC0 Output/ADC0_SE23 11000 AD24 Reserved Reserved 11001 AD25 Reserved Reserved (SC1n[ADCH]) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 92 NXP Semiconductors Chapter 3 Chip Configuration Table 3-39. ADC0 Assignments (continued) ADC Channel Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0) 11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E) 11011 AD27 Bandgap (Diff) Bandgap (S.E)2 11100 AD28 Reserved Reserved 11101 AD29 -VREFH (Diff) VREFH (S.E) 11110 AD30 Reserved VREFL 11111 AD31 Module Disabled Module Disabled (SC1n[ADCH]) 1. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter for details. 2. This is the PMC bandgap 1V reference voltage and not the VREF module 1.2 V reference voltage. Prior to reading from this ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (VBG) specification. 3.7.1.3.2 ADC1 channel assignment ADC Channel Table 3-40. ADC1 Assignments Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0) 00000 DAD0 ADC1_DP0 and ADC1_DM0 ADC1_DP0 00001 DAD1 ADC1_DP1 and ADC1_DM1 ADC1_DP1 00010 DAD2 Reserved Reserved 00011 DAD3 ADC1_DP3 and ADC1_DM3 ADC1_DP3 001001 AD4a Reserved ADC1_SE4a 001011 AD5a Reserved ADC1_SE5a 001101 AD6a Reserved ADC1_SE6a 001111 AD7a Reserved ADC1_SE7a 001001 AD4b Reserved ADC1_SE4b 001011 AD5b Reserved ADC1_SE5b 001101 AD6b Reserved ADC1_SE6b 001111 AD7b Reserved ADC1_SE7b 01000 AD8 Reserved ADC1_SE8 01001 AD9 Reserved ADC1_SE9 01010 AD10 Reserved Reserved 01011 AD11 Reserved Reserved 01100 AD12 Reserved Reserved 01101 AD13 Reserved Reserved 01110 AD14 Reserved ADC1_SE14 01111 AD15 Reserved ADC1_SE15 10000 AD16 Reserved Reserved 10001 AD17 Reserved ADC1_SE17 (SC1n[ADCH]) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 93 Analog Table 3-40. ADC1 Assignments (continued) ADC Channel Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0) 10010 AD18 Reserved VREF Output/ADC1_SE18 10011 AD19 Reserved ADC1_DM0 10100 AD20 Reserved ADC1_DM1 10101 AD21 Reserved Reserved 10110 AD22 Reserved VBAT 10111 AD23 Reserved ADC1_SE23 11000 AD24 Reserved Reserved 11001 AD25 Reserved Reserved 11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E) 11011 AD27 Bandgap (Diff)2 Bandgap (S.E)2 11100 AD28 Reserved Reserved 11101 AD29 -VREFH (Diff) VREFH (S.E) 11110 AD30 Reserved VREFL 11111 AD31 Module Disabled Module Disabled (SC1n[ADCH]) 1. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter for details. 2. This is the PMC bandgap 1V reference voltage and not the VREF module 1.2 V reference voltage. Prior to reading from this ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (VBG) specification. 3.7.1.4 ADC Channels MUX Selection The following figure shows the assignment of ADCx_SEn channels a and b through a MUX selection to ADC. To select between alternate set of channels, refer to ADCx_CFG2[MUXSEL] bit settings for more details. ADCx_SE4a ADCx_SE5a ADCx_SE6a ADCx_SE7a ADCx_SE4b ADCx_SE5b ADCx_SE6b ADCx_SE7b AD4 [00100] AD5 [00101] AD6 [00110] ADC AD7 [00111] Figure 3-28. ADCx_SEn channels a and b selection K22F Sub-Family Reference Manual, Rev. 4, 08/2016 94 NXP Semiconductors Chapter 3 Chip Configuration 3.7.1.5 ADC Hardware Interleaved Channels The AD8 and AD9 channels on ADCx are interleaved in hardware using the following configuration. AD8 ADC0_SE8 /ADC1_SE8 ADC0 AD9 ADC0_SE9 /ADC1_SE9 AD8 ADC1 AD9 Figure 3-29. ADC hardware interleaved channels integration There are other pins on this device that have a similar interleave configuration, including the plus side of differential pair pins available (for example ADC0_DP0 and ADC1_DP3). Refer to the Signal Multiplexing and Pin Assignments table for this device. 3.7.1.6 ADC Reference Options The ADC supports the following references: * VREFH/VREFL - connected as the primary reference option * 1.2 V VREF_OUT - connected as the VALT reference option ADCx_SC2[REFSEL] bit selects the voltage reference sources for ADC. Refer to REFSEL description in ADC chapter for more details. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 95 Analog 3.7.1.7 VBAT connection to ADC input channel The VBAT supply input can be converted as a single ended input to ADC1 Channel 22. When VBAT is greater than the selected voltage reference, the conversion result will show a saturated result (~0xFFFF in 16-bit operation). When measuring the VBAT voltage level the ADC should be configured for a long sample time (ADC1_CFG1[ADLSMP]=1, ADC1_CFG2[ADLSTS]=00). 3.7.1.8 ADC triggers The ADC supports both software and hardware triggers. The primary hardware mechanism for triggering the ADC is the PDB. The PDB itself can be triggered by other peripherals. For example: RTC (Alarm, Seconds) signal is connected to the PDB. The PDB input trigger can receive the RTC (alarm/seconds) trigger forcing ADC conversions in run mode (where PDB is enabled). On the other hand, the ADC can conduct conversions in low power modes, not triggered by PDB. This allows the ADC to do conversions in low power mode and store the output in the result register. The ADC generates interrupt when the data is ready in the result register that wakes the system from low power mode. The PDB can also be bypassed by using the ADCxTRGSEL bits in the SIM_SOPT7 register. Table 3-41. ADC Alternate trigger options SIM_SOPT7[ADCxTRGSEL] Selected source 0000 PDB external trigger pin input (PDB0_EXTRG) 0001 CMP0 output 0010 CMP1 output 0011 Reserved 0100 PIT trigger 0 0101 PIT trigger 1 0110 PIT trigger 2 0111 PIT trigger 3 1000 FTM0 trigger 1001 FTM1 trigger 1010 FTM2 trigger 1011 Reserved 1100 RTC alarm 1101 RTC seconds 1110 LPTMR trigger 1111 Reserved For operation of triggers in different modes, refer to Power Management chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 96 NXP Semiconductors Chapter 3 Chip Configuration 3.7.1.9 ADC conversion clock options The ADC has multiple input clock sources. Selection is determined by ADCx_CFG1[ADICLK] bitfield. The following table shows the chip-specific clock assignments for this bitfield. NOTE The ALTCLK option is only usable when OSCERCLK is in the MHz range. A system with OSCERCLK in the kHz range has the optional clock source below minimum ADC clock operating frequency. Table 3-42. ADC Conversion Clock Options ADCx_CFG1[ADICLK] ADC defined selection Chip clock Note 00 Bus Clock Bus Clock 01 ALTCLK2 IRC48MCLK Note 1 10 ALTCLK OSCERCLK Note 1 11 Asynchronous clock (ADACK) N/A - sourced from within ADC block Note1 1. For ADC operation in Compute only, PSTOP1, Stop and VLPS, ADACK and the alternate clock sources are allowed clock sources. Note however that ALTCLK2 is force disabled and therefore not available in VLPS. 3.7.1.10 ADC low-power modes This table shows the ADC low-power modes and the corresponding chip low-power modes. Table 3-43. ADC low-power modes Module mode Chip mode Wait Wait, VLPW Normal Stop Stop, VLPS Low Power Stop LLS, VLLS3, VLLS2, VLLS1, VLLS0 3.7.2 CMP Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 97 Analog Peripheral bridge 0 Register access CMP Other peripherals Module signals Signal multiplexing Figure 3-30. CMP configuration Table 3-44. Reference links to related information Topic Related module Reference Full description Comparator (CMP) Comparator System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.2.1 CMP input connections The following table shows the fixed internal connections to the CMP. Table 3-45. CMP input connections CMP Inputs CMP0 CMP1 IN0 CMP0_IN0 CMP1_IN0 IN1 CMP0_IN1 CMP1_IN1 IN2 CMP0_IN2 -- IN3 CMP0_IN3 12-bit DAC0_OUT/CMP1_IN3 IN4 CMP0_IN4 -- IN5 VREF Output/CMP0_IN5 VREF Output/CMP1_IN5 IN6 Bandgap Bandgap IN7 6b DAC0 Reference 6b DAC1 Reference 3.7.2.2 CMP external references The 6-bit DAC sub-block supports selection of two references. For this device, the references are connected as follows: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 98 NXP Semiconductors Chapter 3 Chip Configuration * VREF_OUT - Vin1 input * VDD - Vin2 input 3.7.2.3 External window/sample input Individual PDB pulse-out signals control each CMP Sample/Window timing. 3.7.2.4 CMP trigger mode The CMP and 6-bit DAC sub-block supports trigger mode operation when the CMPx_CR1[TRIGM] is set. When trigger mode is enabled, the trigger event will initiate a compare sequence that must first enable the CMP and DAC prior to performing a CMP operation and capturing the output. In this device, control for this two staged sequencing is provided from the LPTMR. The LPTMR provides a single trigger output to all implemented comparators. Through configuration of the CMPx_CR1[TRIGM] bits the trigger can be used to trigger a single comparator or multiple comparators concurrently. The LPTMR triggering output is always enabled when the LPTMR is enabled. The first signal is supplied to enable the CMP and DAC and is asserted at the same time as the TCF flag is set. The delay to the second signal that triggers the CMP to capture the result of the compare operation is dependent on the LPTMR configuration. In Time Counter mode with prescaler enabled, the delay is 1/2 Prescaler output period. In Time Counter mode with prescaler bypassed, the delay is 1/2 Prescaler clock period. The delay between the first signal from LPTMR and the second signal from LPTMR must be greater than the Analog comparator initialization delay as defined in the device datasheet. 3.7.3 12-bit DAC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 99 Analog Peripheral bus controller 0 Register access Other peripherals Transfers 12-bit DAC Module signals Signal multiplexing Figure 3-31. 12-bit DAC configuration Table 3-46. Reference links to related information Topic Related module Reference Full description 12-bit DAC 12-bit DAC System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.3.1 12-bit DAC Overview This device contains one 12-bit digital-to-analog converter (DAC) with programmable reference generator output. The DAC includes a FIFO for DMA support. 3.7.3.2 12-bit DAC Output The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator or ADC. 3.7.3.3 12-bit DAC Reference For this device VREF_OUT and VDDA are selectable as the DAC reference. VREF_OUT is connected to the DACREF_1 input and VDDA is connected to the DACREF_2 input. Use DACx_C0[DACRFS] control bit to select between these two options. Be aware that if the DAC and ADC use the VREF_OUT reference simultaneously, some degradation of ADC accuracy is to be expected due to DAC switching. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 100 NXP Semiconductors Chapter 3 Chip Configuration 3.7.4 VREF Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bus controller 0 Register access Transfers Other peripherals VREF Module signals Signal multiplexing Figure 3-32. VREF configuration Table 3-47. Reference links to related information Topic Related module Reference Full description VREF VREF System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.4.1 VREF Overview This device includes a voltage reference (VREF) to supply an accurate 1.2 V voltage output. The voltage reference can provide a reference voltage to external peripherals or a reference to analog peripherals, such as the ADC, DAC, or CMP. NOTE PMC_REGSC[BGEN] bit must be set if the VREF regulator is required to remain operating in VLPx modes. NOTE For either an internal or external reference if the VREF_OUT functionality is being used, VREF_OUT signal must be K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 101 Timers connected to an output load capacitor. Refer the device data sheet for more details. 3.8 Timers 3.8.1 PDB Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bus controller 0 Register access Transfers Other peripherals PDB Module signals Signal multiplexing Figure 3-33. PDB configuration Table 3-48. Reference links to related information Topic Related module Reference Full description PDB PDB System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.8.1.1 PDB Instantiation 3.8.1.1.1 PDB Output Triggers Table 3-49. PDB output triggers Number of PDB channels for ADC trigger 2 Number of pre-triggers per PDB channel 2 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 102 NXP Semiconductors Chapter 3 Chip Configuration Table 3-49. PDB output triggers (continued) 3.8.1.1.2 Number of DAC triggers 1 Number of PulseOut 2 PDB Input Trigger Connections Table 3-50. PDB Input Trigger Options PDB Trigger PDB Input 0000 External Trigger 0001 CMP 0 0010 CMP 1 0011 Reserved 0100 PIT Ch 0 Output 0101 PIT Ch 1 Output 0110 PIT Ch 2 Output 0111 PIT Ch 3 Output 1000 FTM0 initialization trigger and channel triggers, as programmed in the FTM external trigger register (EXTTRIG) 1001 FTM1 initialization trigger and channel triggers, as programmed in the FTM external trigger register (EXTTRIG) 1010 FTM2 initialization trigger and channel triggers, as programmed in the FTM external trigger register (EXTTRIG) 1011 Reserved 1100 RTC Alarm 1101 RTC Seconds 1110 LPTMR Output 1111 Software Trigger 3.8.1.2 PDB Module Interconnections PDB trigger outputs Connection Channel 0 triggers ADC0 trigger Channel 1 triggers ADC1 trigger and synchronous input 1 of FTM0 DAC triggers DAC0 trigger Pulse-out Pulse-out connected to each CMP module's sample/window input to control sample operation K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 103 Timers 3.8.1.3 Back-to-back acknowledgement connections Back-to-back operation enables the ADC conversions complete to trigger the next PDB channel pre-trigger and trigger output. In this MCU, PDB back-to-back operation acknowledgment connections are implemented as follows: * * * * PDB channel 0 trigger/pre-trigger 0 acknowledgement input: ADC1SC1B_COCO PDB channel 0 trigger/pre-trigger 1 acknowledgement input: ADC0SC1A_COCO PDB channel 1 trigger/pre-trigger 0 acknowledgement input: ADC0SC1B_COCO PDB channel 1 trigger/pre-trigger 1 acknowledgement input: ADC1SC1A_COCO So, the back-to-back chain is connected as a ring: Channel 0 pre-trigger 0 Channel 1 pre-trigger 1 Channel 0 pre-trigger 1 Channel 1 pre-trigger 0 Figure 3-34. PDB back-to-back chain The application code can set the PDBx_CHnC1[BB] bits to configure the PDB pretriggers as a single chain or several chains. 3.8.1.4 PDB Interval Trigger Connections to DAC In this MCU, PDB interval trigger connections to DAC are implemented as follows. * PDB interval trigger 0 connects to DAC0 hardware trigger input. 3.8.1.5 DAC External Trigger Input Connections In this MCU, the following DAC external trigger inputs are implemented. * DAC external trigger input 0: ADC0SC1A_COCO K22F Sub-Family Reference Manual, Rev. 4, 08/2016 104 NXP Semiconductors Chapter 3 Chip Configuration NOTE Application code can set the PDBx_DACINTCn[EXT] bit to allow DAC external trigger input when the corresponding ADC Conversion complete flag, ADCx_SC1n[COCO], is set. 3.8.1.6 Pulse-Out Connection Individual PDB Pulse-Out signals are connected to each CMP block and used for sample window. 3.8.1.7 Pulse-Out Enable Register Implementation The following table shows the comparison of pulse-out enable register at the module and chip level. Table 3-51. PDB pulse-out enable register Register Module implementation Chip implementation POnEN 7:0 - POEN 0 - POEN[0] for CMP0 31:8 - Reserved 1 - POEN[1] for CMP1 31:2 - Reserved 3.8.2 FlexTimer Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 105 Timers Peripheral bus controller 0 Register access Transfers Other peripherals FlexTimer Module signals Signal multiplexing Figure 3-35. FlexTimer configuration Table 3-52. Reference links to related information Topic Related module Reference Full description FlexTimer FlexTimer System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.8.2.1 Instantiation Information This device contains three FlexTimer modules. The following table shows how these modules are configured. Table 3-53. FTM Instantiations FTM instance Number of channels Features/usage FTM0 8 3-phase motor + 2 general purpose or stepper motor FTM1 2 Quadrature decoder or general purpose FTM2 21 Quadrature decoder or general purpose 1. Only channels 0 and 1 are available. 3.8.2.2 External Clock Options By default each FTM is clocked by the internal bus clock (the FTM refers to it as system clock). Each module contains a register setting that allows the module to be clocked from an external clock instead. There are two external FTM_CLKINx pins that can be selected by any FTM module via the SIM_SOPT4 register. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 106 NXP Semiconductors Chapter 3 Chip Configuration 3.8.2.3 Fixed frequency clock The fixed frequency clock for each FTM is MCGFFCLK. 3.8.2.4 FTM Interrupts The FlexTimer has multiple sources of interrupt. However, these sources are OR'd together to generate a single interrupt request to the interrupt controller. When an FTM interrupt occurs, read the FTM status registers (FMS, SC, and STATUS) to determine the exact interrupt source. 3.8.2.5 FTM Fault Detection Inputs The following fault detection input options for the FTM modules are selected via the SIM_SOPT4 register. The external pin option is selected by default. * * * * FTM0 FAULT0 = FTM0_FLT0 pin or CMP0 output FTM0 FAULT1 = FTM0_FLT1 pin or CMP1 output FTM0 FAULT2 = FTM0_FLT2 pin FTM0 FAULT3 = FTM0_FLT3 pin * FTM1 FAULT0 = FTM1_FLT0 pin or CMP0 output * FTM1 FAULT1 = CMP1 output * FTM2 FAULT0 = FTM2_FLT0 pin or CMP0 output * FTM2 FAULT1 = CMP1 output 3.8.2.6 FTM Hardware Triggers The FTM synchronization hardware triggers are connected in the chip as follows: * FTM0 hardware trigger 0 = SIM_SOPT8[FTM0SYNCBIT] or CMP0 Output or FTM1 Match (when enabled in the FTM1 External Trigger (EXTTRIG) register) * FTM0 hardware trigger 1 = PDB channel 1 Trigger Output or FTM2 Match (when enabled in the FTM2 External Trigger (EXTTRIG) register) * FTM0 hardware trigger 2 = FTM0_FLT0 pin * FTM1 hardware trigger 0 = SIM_SOPT8[FTM1SYNCBIT] or CMP0 Output * FTM1 hardware trigger 1 = CMP1 Output * FTM1 hardware trigger 2 = FTM1_FLT0 pin K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 107 Timers * FTM2 hardware trigger 0 = SIM_SOPT8[FTM2SYNCBIT] or CMP0 Output * FTM2 hardware trigger 2 = FTM2_FLT0 pin Having FTMxSYNCBIT fields in the same SOPTx register allows the user to synchronise all FTM timers via their respective TRIG0 input. For the triggers with more than one additional option, the SIM_SOPT4 register implements control fields for selecting the option. 3.8.2.7 Input capture options for FTM module instances The following channel 0 input capture source options are selected via SIM_SOPT4. The external pin option is selected by default. * FTM1 channel 0 input capture = FTM1_CH0 pin or CMP0 output or CMP1 output or USB start of frame pulse * FTM2 channel 0 input capture = FTM2_CH0 pin or CMP0 output or CMP1 output * FTM2 channel 1 input capture = FTM2_CH1 pin or exclusive OR of FTM2_CH0, FTM2_CH1, and FTM1_CH1. See FTM Hall sensor support. NOTE When the USB start of frame pulse option is selected as an FTM channel input capture, disable the USB SOF token interrupt in the USB Interrupt Enable register (INTEN[SOFTOKEN]) to avoid USB enumeration conflicts. 3.8.2.8 FTM Hall sensor support For 3 phase motor control sensor-ed applications the use of Hall sensors, generally 3 sensors placed 120 degrees apart around the rotor, are deployed to detect position and speed. Each of the 3 sensors provides a pulse that applied to an input capture pin, can then be analyzed and both speed and position can be deduced. This device has two 2channel FTMs. (FTM1 and FTM2) and thus provides 4 input capture pins. To simplify the calculations required by the CPU on each hall sensor's input, if all 3 inputs are "exclusively OR'd " into one timer channel and the free running counter is refreshed on every edge then this can simplify the speed calculation. Via the SIM module and SIM_SOPT4 register the FTM2CH1SRC bit provides the choice of normal FTM2_CH1 input or the XOR of FTM2_CH0, FTM2_CH1 and FTM1_CH1 pins that will be applied to FTM2_CH1. Note: If the user utilizes FTM1_CH1 to be an input to FTM2_CH1, FTM1_CH0 can still be utilized for other functions. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 108 NXP Semiconductors Chapter 3 Chip Configuration FTM2 FTM2_CH1 Ch0 Ch1 FTM2_CH0 X OR FTM1 FTM1_CH1 SIM_SOPT4[FTM2CH1SRC] Ch0 Ch1 Figure 3-36. FTM Hall Sensor Configuration 3.8.2.9 FTM modulation implementation FTM0 support a modulation function where the output channels when configured as PWM or Output Compare mode modulate another timer output when the channel signal is asserted. Any of the 8 channels of FTM0 can be configured to support this modulation function. The SIM_SOPT8 register has eight control bits (FTM0CHySRC) that allow the user to select normal PWM/Output Compare mode on the corresponding FTM timer channel or modulate with FTM1_CH1. The diagram below shows the implementation for FTM0. See SIM Block Guide for further information. When FTM1_CH1 is used to modulate an FTM0 channel, then the user must configure FTM1_CH1 to provide a signal that has a higher frequency than the modulated FTM0 channel output. Also it limits the use of the FTM1_CH0 function, as the FTM1_CH1 will be programmed to provide a 50% duty PWM signal and limit the start and modulus values for the free running counter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 109 Timers SIM_SOPT8[FTM0CH7SRC] FTM0 & FTM0_CH7 CH7 SIM_SOPT8[FTM0CH0SRC] & FTM0_CH0 CH0 FTM1_CH1 Figure 3-37. FTM Output Modulation 3.8.2.10 FTM output triggers for other modules FTM output triggers can be selected as input triggers for the PDB and ADC modules. See PDB Instantiation and ADC triggers. 3.8.2.11 FTM Global Time Base This chip provides the optional FTM global time base feature (see Global time base (GTB)). FTM0 provides the only source for the FTM global time base. The other FTM modules can share the time base as shown in the following figure: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 110 NXP Semiconductors Chapter 3 Chip Configuration FTM1 CONF Register GTBEOUT = 0 GTBEEN = 1 FTM0 CONF Register GTBEOUT = 1 GTBEEN = 1 FTM Counter gtb_in gtb_in FTM Counter FTM2 gtb_out CONF Register GTBEOUT = 0 GTBEEN = 1 FTM Counter gtb_in Figure 3-38. FTM Global Time Base Configuration 3.8.2.12 FTM BDM and debug halt mode In the FTM chapter, references to the chip being in "BDM" are the same as the chip being in "debug halt mode". 3.8.3 PIT Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access Periodic interrupt timer Figure 3-39. PIT configuration Table 3-54. Reference links to related information Topic Related module Reference Full description PIT PIT System memory map System memory map Clocking Clock Distribution Power management Power management K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 111 Timers 3.8.3.1 PIT/DMA Periodic Trigger Assignments The PIT generates periodic trigger events to the DMA Mux as shown in the table below. Table 3-55. PIT channel assignments for periodic DMA triggering DMA Channel Number PIT Channel DMA Channel 0 PIT Channel 0 DMA Channel 1 PIT Channel 1 DMA Channel 2 PIT Channel 2 DMA Channel 3 PIT Channel 3 3.8.3.2 PIT/ADC Triggers PIT triggers are selected as ADCx trigger sources using the SIM_SOPT7[ADCxTRGSEL] fields. For more details, refer to SIM chapter. 3.8.4 Low-power timer configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access Low-power timer Module signals Signal multiplexing Figure 3-40. LPTMR configuration Table 3-56. Reference links to related information Topic Related module Full description Low-power timer Reference Low-power timer System memory map System memory map Clocking Clock Distribution Power management Power management Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 112 NXP Semiconductors Chapter 3 Chip Configuration Table 3-56. Reference links to related information (continued) Topic Related module Reference Signal Multiplexing Port control Signal Multiplexing 3.8.4.1 LPTMR prescaler/glitch filter clocking options The prescaler and glitch filter of the LPTMR module can be clocked from one of four sources determined by the LPTMR0_PSR[PCS] bitfield. The following table shows the chip-specific clock assignments for this bitfield. NOTE The chosen clock must remain enabled if the LPTMR is to continue operating in all required low-power modes. LPTMR0_PSR[PCS] Prescaler/glitch filter clock number Chip clock 00 0 MCGIRCLK -- internal reference clock (not available in VLPS/LLS/VLLS modes) 01 1 LPO -- 1 kHz clock (not available in VLLS0 mode) 10 2 ERCLK32K -- secondary external reference clock 11 3 OSCERCLK_UNDIV -- Undivided external reference clock (not available in VLLS0 mode) See Clock Distribution for more details on these clocks. 3.8.4.2 LPTMR pulse counter input options The LPTMR_CSR[TPS] bitfield configures the input source used in pulse counter mode. The following table shows the chip-specific input assignments for this bitfield. LPTMR_CSR[TPS] Pulse counter input number Chip input 00 0 CMP0 output 01 1 LPTMR_ALT1 pin 10 2 LPTMR_ALT2 pin 11 3 Reserved K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 113 Timers 3.8.5 RTC configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access Module signals Real-time clock Signal multiplexing Figure 3-41. RTC configuration Table 3-57. Reference links to related information Topic Related module Reference Full description RTC RTC System memory map System memory map Clocking Clock Distribution Power management Power management 3.8.5.1 RTC_CLKOUT signal When the RTC is enabled and the port control module selects the RTC_CLKOUT function, the RTC_CLKOUT signal outputs a 1 Hz or 32 kHz output derived from RTC oscillator as shown below. RTC_CR[CLKO] RTC 32kHz clock RTC_CLKOUT RTC 1Hz clock SIM_SOPT2[RTCCLKOUTSEL] Figure 3-42. RTC_CLKOUT generation K22F Sub-Family Reference Manual, Rev. 4, 08/2016 114 NXP Semiconductors Chapter 3 Chip Configuration 3.9 Communication interfaces 3.9.1 Universal Serial Bus (USB) FS Subsystem The USB FS subsystem includes these components: * Dual-role USB OTG-capable (On-The-Go) controller that supports a full-speed (FS) device or FS/LS host. The module complies with the USB 2.0 specification. * USB transceiver that includes internal 15 k pulldowns on the D+ and D- lines for host mode functionality and a 1.5 k pullup on the D+ line for device mode functionality. * Status detection and wakeup functions for USB data pins, VBUS pin, and OTG ID pin. * IRC48 with clock recovery block to eliminate the 48MHz crystal. This is available for USB device mode only. USB controller USBVDD IRC 48 FS/LS transceiver D+ D- Figure 3-43. USB FS/LS Subsystem Overview NOTE Use the following code sequence to select USB clock source, USB clock divide ratio, and enable its clock gate to avoid potential clock glitches which may result in USB enumeration stage failure. 1. Select the USB clock source by configuring SIM_SOPT2. 2. Select the desired clock divide ratio by configuring SIM_CLKDIV2. 3. Enable USB clock gate by setting SIM_SCGC4. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 115 Communication interfaces 3.9.1.1 USB pin status detection and wakeup interrupt features This device does not have a dedicated VBUS detect pin. For VBUS detection, use a GPIO pin for both bus-powered and self-powered USB cases. Because the GPIO pins on this device do not directly support a 5V input, use an external resistive voltage divider to keep the input voltage within the valid range if a GPIO pin is used for VBUS detection. This device does not have a dedicated OTG ID detect pin. For OTG ID pin detection, if needed, use a GPIO configured as an input pin with pullup enabled. When the USB detects that there is no activity on the USB bus for more than 3 ms, the USBx_ISTAT[SLEEP] bit is set. This bit can cause an interrupt and software decides the appropriate action. Waking from a low power mode (except in LLS/VLLS mode where USB is not powered) occurs through an asynchronous interrupt triggered by activity on the USB bus. Setting the USBx_USBTRC0[USBRESMEN] bit enables this function. The following wakeup feature is also supported: * In LLS/VLLS, if the GPIO pins chosen to detect VBUS and OTG ID are selected from those pins which are inputs to the LLWU, transitions on them can generate a wakeup. 3.9.1.2 USB Power Distribution This chip includes a separate USBVDD supply pad that powers the USB transceiver. USBVDD can be powered at nominal USB voltage level (3.3V) while the main MCU supply pins are powered across the full operating range for the device. 3.9.1.2.1 AA/AAA cells power supply The chip can be powered by two AA/AAA cells. In this case, the MCU is powered through VDD which is within the 1.8 to 3.0 V range. After USB cable insertion is detected, the off-chip regulator is enabled to power the USB transceiver. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 116 NXP Semiconductors Chapter 3 Chip Configuration VDD 2 AA Cells To PMC and Pads C byp + Chip TYPE A VBUS Regulator USBVDD C byp D+ USB0_DP D- USB0_DM USB XCVR USB Controller Figure 3-44. USB regulator AA cell usecase 3.9.1.2.2 Li-Ion battery power supply The chip can also be powered by a single Li-ion battery. In this case, the regulator supplies VDD and USBVDD supply inputs. When connected to a USB host, the input source of this regulator is switched to the USB bus supply from the Li-ion battery. VDD C byp To PMC and Pads USBVDD C byp Chip TYPE A VBUS Charger Si2301 Regulator D+ USB0_DP DVSS USB XCVR USB Controller USB0_DM Li-Ion Figure 3-45. USB regulator Li-ion usecase 3.9.1.2.3 USB bus power supply The chip can also be powered by the USB bus directly. In this case, the regulator supplies VDD and USBVDD supply inputs. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 117 Communication interfaces VDD To PMC and Pads C byp USBVDD C byp Chip TYPE A VBUS Regulator D+ USB0_DP D- USB0_DM XCVR USB USB Controller Figure 3-46. USB regulator bus supply 3.9.1.3 USB controller configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge 0 Register access Crossbar switch Transfers USB controller Module signals Signal multiplexing Figure 3-47. USB controller configuration Table 3-58. Reference links to related information Topic Related module Full description USB controller Reference USB controller System memory map System memory map Clocking Clock Distribution Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing K22F Sub-Family Reference Manual, Rev. 4, 08/2016 118 NXP Semiconductors Chapter 3 Chip Configuration NOTE When USB is not used in the application, it is recommended that the USB supply pad USBVDD is tied to ground through 10k; leaving this pin floating is not recommended. 3.9.2 SPI configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access SPI Module signals Signal multiplexing Figure 3-48. SPI configuration Table 3-59. Reference links to related information Topic Related module Reference Full description SPI SPI System memory map System memory map Clocking Clock Distribution Signal Multiplexing Port control Signal Multiplexing 3.9.2.1 SPI Modules Configuration This device contains two SPI modules . 3.9.2.2 SPI clocking The SPI module is clocked by the internal bus clock (the DSPI refers to it as system clock). The module has an internal divider, with a minimum divide is two. So, the SPI can run at a maximum frequency of bus clock/2. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 119 Communication interfaces 3.9.2.3 Number of CTARs SPI CTAR registers define different transfer attribute configurations. The SPI module supports up to eight CTAR registers. This device supports two CTARs on all instances of the SPI. In master mode, the CTAR registers define combinations of transfer attributes, such as frame size, clock phase, clock polarity, data bit ordering, baud rate, and various delays. In slave mode only CTAR0 is used, and a subset of its bitfields sets the slave transfer attributes. 3.9.2.4 TX FIFO size Table 3-60. SPI transmit FIFO size SPI Module Transmit FIFO size SPI0 4 SPI1 1 3.9.2.5 RX FIFO Size SPI supports up to 16-bit frame size during reception. Table 3-61. SPI receive FIFO size SPI Module Receive FIFO size SPI0 4 SPI1 1 3.9.2.6 Number of PCS signals The following table shows the number of peripheral chip select signals available per SPI module. Table 3-62. SPI PCS signals SPI Module PCS Signals SPI0 For packages with greater than 64 pins: SPI0_PCS[5:0] For packages with 64 pins: SPI0_PCS[4:0] Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 120 NXP Semiconductors Chapter 3 Chip Configuration Table 3-62. SPI PCS signals (continued) SPI Module PCS Signals SPI1 For packages with greater than 64 pins: SPI0_PCS[3:0] For packages with 64 pins: SPI0_PCS[1:0] 3.9.2.7 SPI Operation in Low Power Modes In VLPR and VLPW modes the SPI is functional; however, the reduced system frequency also reduces the max frequency of operation for the SPI. In VLPR and VLPW modes the max SPI_CLK frequency is 2MHz. In stop and VLPS modes, the clocks to the SPI module are disabled. The module is not functional, but it is powered so that it retains state. There is one way to wake from stop mode via the SPI, which is explained in the following section. 3.9.2.7.1 Using GPIO Interrupt to Wake from stop mode Here are the steps to use a GPIO to create a wakeup upon reception of SPI data in slave mode: 1. Point the GPIO interrupt vector to the desired interrupt handler. 2. Enable the GPIO input to generate an interrupt on either the rising or falling edge (depending on the polarity of the chip select signal). 3. Enter Stop or VLPS mode and Wait for the GPIO interrupt. NOTE It is likely that in using this approach the first word of data from the SPI host might not be received correctly. This is dependent on the transfer rate used for the SPI, the delay between chip select assertion and presentation of data, and the system interrupt latency. 3.9.2.8 SPI Doze Mode The Doze mode for the SPI module is the same as the Wait and VLPW modes for the chip. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 121 Communication interfaces 3.9.2.9 SPI Interrupts The SPI has multiple sources of interrupt requests. However, these sources are OR'd together to generate a single interrupt request per SPI module to the interrupt controller. When an SPI interrupt occurs, read the SPI_SR to determine the exact interrupt source. 3.9.2.10 SPI clocks This table shows the SPI module clocks and the corresponding chip clocks. Table 3-63. SPI clock connections Module clock System Clock Chip clock Bus Clock 3.9.2.11 Writing SPI Transmit FIFO The SPI supports 8-bit or 16-bit writes to the PUSH TX FIFO, allowing a single write to the command word followed by multiple writes to the transmit word. The TX FIFO will save the last command word written, and convert a 8-bit/16-bit write to the transmit word into a 32-bit write that pushes both the command word and transmit word into the TX FIFO (PUSH TX FIFO Register In Master Mode) A 32-bit write to the SPI_PUSH register will push all 32-bits to the TX FIFO. An 8-bit or 16-bit write to the 16-bit transmit data field will push the data together with the last written command word. An 8-bit or 16-bit write to the command word does not push data onto the FIFO, but that command word is pushed to the TX FIFO on all subsequent 8-bit or 16-bit writes to the transmit data field. This allows a single 16-bit write to the command word to be used for all subsequent 8-bit or 16-bit writes to the transmit data word. Writing a different 16-bit command word will cause all subsequent 8-bit or 16-bit writes to the transmit data word to be pushed to the TX FIFO with the new command word. 3.9.3 I2C Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 122 NXP Semiconductors Chapter 3 Chip Configuration Peripheral bridge Register access I2 C Module signals Signal multiplexing Figure 3-49. I2C configuration Table 3-64. Reference links to related information Topic Related module Reference Full description I2C I2C System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.9.3.1 I2C Instantiation Information This device has two I2C modules. The I2C module includes SMBus support and DMA support. It also has optional address match wakeup in Stop/VLPS mode. The digital glitch filter implemented in the IIC module, controlled by the I2Cx_FLT[FLT] registers, is clocked from the bus clock and thus has filter granularity in bus clock cycle counts. 3.9.4 UART Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 123 Communication interfaces Peripheral bridge Register access Module signals UART Signal multiplexing Figure 3-50. UART configuration Table 3-65. Reference links to related information Topic Related module Reference Full description UART UART System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.9.4.1 UART configuration information This chip contains three UART modules. This section describes how each module is configured on this device. 1. Standard features of all UARTs: * RS-485 support * Hardware flow control (RTS/CTS) * 9-bit UART to support address mark with parity * MSB/LSB configuration on data 2. UART0 and UART1 are clocked from the core clock, the remaining UARTs are clocked on the bus clock. The maximum baud rate is 1/16 of related source clock frequency. 3. IrDA is available on all UARTs 4. UART0 contains the standard features plus ISO7816 5. UART0 contains 8-entry transmit and 8-entry receive FIFOs 6. All other UARTs contain a 1-entry transmit and receive FIFOs K22F Sub-Family Reference Manual, Rev. 4, 08/2016 124 NXP Semiconductors Chapter 3 Chip Configuration 3.9.4.2 UART wakeup The UART can be configured to generate an interrupt/wakeup on the first active edge that it receives. 3.9.4.3 UART interrupts The UART has multiple sources of interrupt requests. However, some of these sources are OR'd together to generate a single interrupt request. See below for the mapping of the individual interrupt sources to the interrupt request: The status interrupt combines the following interrupt sources: Source UART 0 UART 1 UART 2 Transmit data empty x x x Transmit complete x x x Idle line x x x Receive data full x x x LIN break detect x x x RxD pin active edge x x x Initial character detect x -- -- The error interrupt combines the following interrupt sources: Source UART 0 UART 1 UART 2 Receiver overrun x x x Noise flag x x x Framing error x x x Parity error x x x Transmitter buffer overflow x x x Receiver buffer overflow x x x Receiver buffer underflow x x x Transmit threshold (ISO7816) x -- -- Receiver threshold (ISO7816) x -- -- Wait timer (ISO7816) x -- -- Character wait timer (ISO7816) x -- -- Block wait timer (ISO7816) x -- -- Guard time violation (ISO7816) x -- -- ATR duration timer (ISO7816) x -- -- K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 125 Communication interfaces 3.9.5 LPUART configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access Module signals LPUART Signal multiplexing Figure 3-51. LPUART configuration Table 3-66. Reference links to related information Topic Related module Reference Full description LPUART0 LPUART System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.9.5.1 LPUART0 overview The LPUART0 module supports basic UART with DMA interface function and x4 to x32 oversampling of baud-rate. The module can remain functional in Stop and VLPS mode provided the clock it is using remains enabled. This module supports LIN slave operation. 3.9.6 I2S configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 126 NXP Semiconductors Chapter 3 Chip Configuration Peripheral bridge Register access I2 S Module signals Signal multiplexing Figure 3-52. I2S configuration Table 3-67. Reference links to related information Topic Related module Reference Full description >I2S I2S System memory map System memory map Clocking Clock Distribution Power management Power management Signal multiplexing Port control Signal Multiplexing 3.9.6.1 Instantiation information This device contains one I2S module. As configured on the device, module features include: * TX data lines: 1 * RX data lines: 1 * FIFO size (words): 8 * Maximum words per frame: 16 * Maximum bit clock divider: 512 3.9.6.2 I2S/SAI clocking 3.9.6.2.1 Audio Master Clock The audio master clock (MCLK) is used to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock. The audio master clock can also be output to or input from a pin. The transmitter and receiver have the same audio master clock inputs. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 127 Communication interfaces 3.9.6.2.2 Bit Clock The I2S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can be generated internally from the audio master clock or supplied externally. The module also supports the option for synchronous operation between the receiver and transmitter product. 3.9.6.2.3 Bus Clock The bus clock is used by the control registers and to generate synchronous interrupts and DMA requests. 3.9.6.2.4 I2S/SAI clock generation Each SAI peripheral can control the input clock selection, pin direction and divide ratio of one audio master clock. The MCLK Input Clock Select bit of the MCLK Control Register (MCR[MICS]) selects the clock input to the I2S/SAI module's MCLK divider. The following table shows the input clock selection options on this device. Table 3-68. I2S0 MCLK input clock selection MCR[MICS] Clock Selection 00 System clock 01 OSC0ERCLK 10 Not supported 11 MCGFLLCLKor IRC48MCLK The module's MCLK Divide Register (MDR) configures the MCLK divide ratio. The module's MCLK Output Enable bit of the MCLK Control Register (MCR[MOE]) controls the direction of the MCLK pin. The pin is the input from the pin when MOE is 0, and the pin is the output from the clock divider when MOE is 1. The transmitter and receiver can independently select between the bus clock and the audio master clock to generate the bit clock. Each module's Clocking Mode field of the Transmit Configuration 2 Register and Receive Configuration 2 Register (TCR2[MSEL] and RCR2[MSEL]) selects the master clock. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 128 NXP Semiconductors Chapter 3 Chip Configuration The following table shows the TCR2[MSEL] and RCR2[MSEL] field settings for this device. Table 3-69. I2S0 master clock settings TCR2[MSEL], RCR2[MSEL] Master Clock 00 Bus Clock 01 I2S0_MCLK 10 Not supported 11 Not supported 3.9.6.2.5 Clock gating and I2S/SAI initialization The clock to the I2S/SAI module can be gated using a bit in the SIM. To minimize power consumption, these bits are cleared after any reset, which disables the clock to the corresponding module. The clock enable bit should be set by software at the beginning of the module initialization routine to enable the module clock before initialization of any of the I2S/SAI registers. 3.9.6.3 I2S/SAI operation in low power modes 3.9.6.3.1 Stop and very low power modes In Stop mode, the SAI transmitter and/or receiver can continue operating provided the appropriate Stop Enable bit is set (TCSR[STOPE] and/or RCSR[STOPE], respectively), and provided the transmitter and/or receiver is/are using an externally generated bit clock or an Audio Master Clock that remains operating in Stop mode. The SAI transmitter and/or receiver can generate an asynchronous interrupt to wake the CPU from Stop mode. In VLPS mode, the module behaves as it does in stop mode if VLPS mode is entered from run mode. However, if VLPS mode is entered from VLPR mode, the FIFO might underflow or overflow before wakeup from stop mode due to the limits in bus bandwidth. In VLPW and VLPR modes, the module is limited by the maximum bus clock frequencies. When operating from an internally generated bit clock or Audio Master Clock that is disabled in stop modes: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 129 Human-machine interfaces In Stop mode, if the Transmitter Stop Enable (TCSR[STOPE]) bit is clear, the transmitter is disabled after completing the current transmit frame, and, if the Receiver Stop Enable (RCSR[STOPE]) bit is clear, the receiver is disabled after completing the current receive frame. Entry into Stop mode is prevented-not acknowledged-while waiting for the transmitter and receiver to be disabled at the end of the current frame. 3.9.6.3.2 Low-leakage modes When entering low-leakage modes, the Stop Enable (TCSR[STOPE] and RCSR[STOPE]) bits are ignored and the SAI is disabled after completing the current transmit and receive Frames. Entry into stop mode is prevented (not acknowledged) while waiting for the transmitter and receiver to be disabled at the end of the current frame. 3.10 Human-machine interfaces 3.10.1 GPIO configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access Crossbar switch Transfers GPIO controller Module signals Signal multiplexing Figure 3-53. GPIO configuration Table 3-70. Reference links to related information Topic Related module Reference Full description GPIO GPIO System memory map System memory map Clocking Clock Distribution Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 130 NXP Semiconductors Chapter 3 Chip Configuration Table 3-70. Reference links to related information (continued) Topic Related module Power management Reference Power management Transfers Crossbar switch Clock Distribution Signal Multiplexing Port control Signal Multiplexing 3.10.1.1 Number of GPIO signals The number of GPIO signals available on the devices covered by this document are detailed in Orderable part numbers . Eight GPIO pins support a high drive capability - PTB0, PTB1, PTD4, PTD5, PTD6, PTD7, PTC3, and PTC4. All other GPIO support normal drive option only. PTA4 includes a passive input filter that is enabled or disabled by PORTA_PCR4[PFE] control. This reset default is to have this function disabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 131 Human-machine interfaces K22F Sub-Family Reference Manual, Rev. 4, 08/2016 132 NXP Semiconductors Chapter 4 Memory Map 4.1 Introduction This device contains various memories and memory-mapped peripherals which are located in one 32-bit contiguous memory space. This chapter describes the memory and peripheral locations within that memory space. 4.2 System memory map The following table shows the high-level device memory map. This map provides the complete architectural address space definition for the various sections. Based on the physical sizes of the memories and peripherals, the actual address regions used may be smaller. The system memory map includes address spaces that are intended for specific purposes. * There is an aliased region that maps a system address space to the Program flash section. Flash region aliasing is specifically intended for references to read-only data coefficients in the flash while still preserving a full Harvard memory organization in the processor core supporting concurrent instruction fetches (for example, from RAM) and data accesses (from flash via the aliased space). * The bitbanding functionality supported by the processor core uses aliased regions that map to the basic RAM and peripheral address spaces. This functionality maps each 32-bit word of the aliased address space to a unique bit in the underlying RAM or peripheral address space to support single-bit insert and extract operations from the processor. Table 4-1. System memory map System 32-bit Address Range 0x0000_0000-0x07FF_FFFF 1 Destination Slave Program flash and read-only data Access All masters Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 133 System memory map Table 4-1. System memory map (continued) System 32-bit Address Range Destination Slave Access (Includes exception vectors in first 1024 bytes) 0x0800_0000-0x0FFF_FFFF 0x1000_0000-0x1BFF_FFFF 0x1C00_0000-0x1FFF_FFFF 2 Reserved -- Reserved -- SRAM_L: Lower SRAM (ICODE/DCODE) All masters 0x2000_0000-0x200F_FFFF 2 SRAM_U: Upper SRAM bitband region All masters 0x2010_0000-0x21FF_FFFF Reserved - 0x2200_0000-0x23FF_FFFF Aliased to SRAM_U bitband Cortex-M4 core only Reserved - Program Flash and read-only data Cortex-M4 core only 0x3400_0000-0x3FFF_FFFF Reserved - 0x4000_0000-0x4007_FFFF Bitband region for peripheral bridge 0 (AIPS-Lite0) Cortex-M4 core & DMA/EzPort 0x4008_0000-0x400F_EFFF Reserved - 0x400F_F000-0x400F_FFFF Bitband region for general purpose input/output (GPIO) Cortex-M4 core & DMA/EzPort 0x4010_0000-0x41FF_FFFF Reserved - 0x4200_0000-0x42FF_FFFF Aliased to peripheral bridge (AIPS-Lite) bitband Cortex-M4 core only 0x4300_0000-0x43FD_FFFF Reserved - 0x43FE_0000-0x43FF_FFFF Aliased to general purpose input/output (GPIO) bitband Cortex-M4 core only 0x4400_0000-0xDFFF_FFFF Reserved - 0xE000_0000-0xE00F_FFFF Private peripherals Cortex-M4 core only 0xE010_0000-0xFFFF_FFFF Reserved - 0x2400_0000-0x2FFF_FFFF 0x3000_0000-0x33FF_FFFF 1 1. This map provides the complete architectural address space definition for the flash. Based on the physical sizes of the memories implemented for a particular device, the actual address regions used may be smaller. See Flash Memory Sizes for details. 2. This range varies depending on amount of SRAM implemented for a particular device. See SRAM sizes for details. NOTE 1. EzPort master port is statically muxed with DMA master port. Access rights to AIPS-Lite peripheral bridge and general purpose input/output (GPIO) module address space is limited to the core, DMA and EzPort. 2. ARM Cortex-M4 core access privileges also includes accesses via the debug interface. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 134 NXP Semiconductors Chapter 4 Memory Map 4.2.1 Aliased bit-band regions The SRAM_U, AIPS-Lite, and general purpose input/output (GPIO) module resources reside in the Cortex-M4 processor bit-band regions. The processor also includes two 32 MB aliased bit-band regions associated with the two 1 MB bit-band spaces. Each 32-bit location in the 32 MB space maps to an individual bit in the bit-band region. A 32-bit write in the alias region has the same effect as a readmodify-write operation on the targeted bit in the bit-band region. Bit 0 of the value written to the alias region determines what value is written to the target bit: * Writing a value with bit 0 set writes a 1 to the target bit. * Writing a value with bit 0 clear writes a 0 to the target bit. A 32-bit read in the alias region returns either: * a value of 0x0000_0000 to indicate the target bit is clear * a value of 0x0000_0001 to indicate the target bit is set Bit-band region Alias bit-band region 31 0 0 32 MByte 1 MByte 31 Figure 4-1. Alias bit-band mapping NOTE Each bit in bit-band region has an equivalent bit that can be manipulated through bit 0 in a corresponding long word in the alias bit-band region. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 135 Flash Memory Map 4.2.2 Flash Access Control Introduction The Flash Access Control (FAC) is a NXP or third-party configurable memory protection scheme optimized to allow end users to utilize software libraries while offering programmable restrictions to these libraries. The flash memory is divided into equal size segments that provide protection to proprietary software libraries. The protection of these segments is controlled as the FAC provides a cycle-by-cycle evaluation of the access rights for each transaction routed to the on-chip flash memory. Configurability allows an increasing number of protected segments while supporting two levels of vendors adding their proprietary software to a device. Flash access control aligns to the three privilege levels supported by ARM Cortex-M family products where the most secure state - supervisor/privileged secure - aligns to the execute-only and supervisor-only access control. The unsecure state of user non-secure aligns to no access control states set, and the mid-level state where user secure aligns to using the access control of execute-only. Control for this protection scheme is implemented in Program Once NVM locations and is configurable through a Program Once flash command operations. The NVM locations controlling FAC are unaffected by Erase All Blocks flash command and debug interface initiated mass erase operations. NOTE The FAC protection scheme has eight XACC and eight SACC registers to control up to 64 segments. For program flash sizes 128KB or less, the memory is divided into 32 segments, controlled by the four lower-order XACC and SACC registers. To protect the NVM locations being used for execute only code from being mass erased FTFA_FSEC[MEEN] bits must be set to 'b10. 4.3 Flash Memory Map The flash memory and the flash registers are located at different base addresses as shown in the following figure. The base address for each is specified in System memory map. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 136 NXP Semiconductors Chapter 4 Memory Map Flash memory base address Registers Program flash base address Flash configuration field Program flash Figure 4-2. Flash memory map The on-chip Flash is implemented in a portion of the allocated Flash range to form a contiguous block in the memory map beginning at address 0x0000_0000. See Flash Memory Sizes for details of supported ranges. Accesses to the flash memory ranges outside the amount of Flash on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. Read collision events in which flash memory is accessed while a flash memory resource is being manipulated by a flash command also generates a bus error response. 4.3.1 Alternate Non-Volatile IRC User Trim Description The following non-volatile locations (4 bytes) are reserved for custom IRC user trim supported by some development tools. An alternate IRC trim to the factory loaded trim can be stored at this location. To override the factory trim, user software must load new values into the MCG trim registers. Non-Volatile Byte Address Alternate IRC Trim Value 0x0000_03FC Reserved 0x0000_03FD Reserved 0x0000_03FE (bit 0) SCFTRIM 0x0000_03FE (bit 4:1) FCTRIM 0x0000_03FE (bit 6) FCFTRIM 0x0000_03FF SCTRIM 4.4 SRAM memory map The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map. See SRAM Configuration for details. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 137 Peripheral bridge (AIPS-Lite) memory map Accesses to the SRAM_L and SRAM_U memory ranges outside the amount of RAM on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. 4.5 Peripheral bridge (AIPS-Lite) memory map Modules that are disabled via their clock gate control bits in the SIM registers disable the associated AIPS slots. Access to any address within an unimplemented or disabled peripheral bridge slot results in a transfer error termination. For programming model accesses via the peripheral bridges, there is generally only a small range within the 4 KB slots that is implemented. Accessing an address that is not implemented in the peripheral results in a transfer error termination. 4.5.1 Read-after-write sequence and required serialization of memory operations In some situations, a write to a peripheral must be completed fully before a subsequent action can occur. Examples of such situations include: * Exiting an interrupt service routine (ISR) * Changing a mode * Configuring a function In these situations, the application software must perform a read-after-write sequence to guarantee the required serialization of the memory operations: 1. Write the peripheral register. 2. Read the written peripheral register to verify the write. 3. Continue with subsequent operations. NOTE One factor contributing to these situations is processor write buffering. The processor architecture has a programmable configuration bit to disable write buffering: ACTLR[DISDEFWBUF]. However, disabling buffered writes is likely to degrade system performance much more than simply performing the required memory serialization for the situations that truly require it. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 138 NXP Semiconductors Chapter 4 Memory Map 4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map Table 4-2. Peripheral bridge 0 slot assignments System 32-bit base address Slot number Module 0x4000_0000 0 -- 0x4000_1000 1 -- 0x4000_2000 2 -- 0x4000_3000 3 -- 0x4000_4000 4 -- 0x4000_5000 5 -- 0x4000_6000 6 -- 0x4000_7000 7 -- 0x4000_8000 8 DMA controller 0x4000_9000 9 DMA controller transfer control descriptors 0x4000_A000 10 -- 0x4000_B000 11 -- 0x4000_C000 12 -- 0x4000_D000 13 -- 0x4000_E000 14 -- 0x4000_F000 15 -- 0x4001_0000 16 -- 0x4001_1000 17 -- 0x4001_2000 18 -- 0x4001_3000 19 -- 0x4001_4000 20 -- 0x4001_5000 21 -- 0x4001_6000 22 -- 0x4001_7000 23 -- 0x4001_8000 24 -- 0x4001_9000 25 -- 0x4001_A000 26 -- 0x4001_B000 27 -- 0x4001_C000 28 -- 0x4001_D000 29 -- 0x4001_E000 30 -- 0x4001_F000 31 Flash memory controller 0x4002_0000 32 Flash memory 0x4002_1000 33 DMA channel mutiplexer 0x4002_2000 34 -- 0x4002_3000 35 -- 0x4002_4000 36 -- Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 139 Peripheral bridge (AIPS-Lite) memory map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot number Module 0x4002_5000 37 -- 0x4002_6000 38 -- 0x4002_7000 39 Analog-to-digital converter (ADC) 1 0x4002_8000 40 -- 0x4002_9000 41 -- 0x4002_A000 42 LPUART0 0x4002_B000 43 -- 0x4002_C000 44 SPI 0 0x4002_D000 45 SPI 1 0x4002_E000 46 -- 0x4002_F000 47 I2S 0 0x4003_0000 48 -- 0x4003_1000 49 -- 0x4003_2000 50 CRC 0x4003_3000 51 -- 0x4003_4000 52 -- 0x4003_5000 53 -- 0x4003_6000 54 Programmable delay block (PDB) 0x4003_7000 55 Periodic interrupt timers (PIT) 0x4003_8000 56 FlexTimer (FTM) 0 0x4003_9000 57 FlexTimer (FTM) 1 0x4003_A000 58 FlexTimer (FTM) 2 0x4003_B000 59 Analog-to-digital converter (ADC) 0 0x4003_C000 60 -- 0x4003_D000 61 Real-time clock (RTC) 0x4003_E000 62 VBAT register file 0x4003_F000 63 DAC0 0x4004_0000 64 Low-power timer (LPTMR) 0x4004_1000 65 System register file 0x4004_2000 66 -- 0x4004_3000 67 -- 0x4004_4000 68 -- 0x4004_5000 69 -- 0x4004_6000 70 -- 0x4004_7000 71 SIM low-power logic 0x4004_8000 72 System integration module (SIM) 0x4004_9000 73 Port A multiplexing control 0x4004_A000 74 Port B multiplexing control 0x4004_B000 75 Port C multiplexing control Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 140 NXP Semiconductors Chapter 4 Memory Map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot number Module 0x4004_C000 76 Port D multiplexing control 0x4004_D000 77 Port E multiplexing control 0x4004_E000 78 -- 0x4004_F000 79 -- 0x4005_0000 80 -- 0x4005_1000 81 -- 0x4005_2000 82 Software watchdog 0x4005_3000 83 -- 0x4005_4000 84 -- 0x4005_5000 85 -- 0x4005_6000 86 -- 0x4005_7000 87 -- 0x4005_8000 88 -- 0x4005_9000 89 -- 0x4005_A000 90 -- 0x4005_B000 91 -- 0x4005_C000 92 -- 0x4005_D000 93 -- 0x4005_E000 94 -- 0x4005_F000 95 -- 0x4006_0000 96 -- 0x4006_1000 97 External watchdog 0x4006_2000 98 -- 0x4006_3000 99 -- 0x4006_4000 100 Multi-purpose Clock Generator (MCG) 0x4006_5000 101 System oscillator (OSC) 0x4006_6000 102 I2C 0 0x4006_7000 103 I2C 1 0x4006_8000 104 -- 0x4006_9000 105 -- 0x4006_A000 106 UART 0 0x4006_B000 107 UART 1 0x4006_C000 108 UART 2 0x4006_D000 109 -- 0x4006_E000 110 -- 0x4006_F000 111 -- 0x4007_0000 112 -- 0x4007_1000 113 -- 0x4007_2000 114 USB OTG FS/LS Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 141 Private Peripheral Bus (PPB) memory map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot number 0x4007_3000 115 Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) 0x4007_4000 116 Voltage reference (VREF) 0x4007_5000 117 -- 0x4007_6000 118 -- 0x4007_7000 119 -- 0x4007_8000 120 -- 0x4007_9000 121 -- 0x4007_A000 122 -- 0x4007_B000 123 -- 0x4007_C000 124 Low-leakage wakeup unit (LLWU) 0x4007_D000 125 Power management controller (PMC) 0x4007_E000 126 System Mode controller (SMC) 0x4007_F000 127 Reset Control Module (RCM) 0x400F_F000 Module GPIO controller 4.6 Private Peripheral Bus (PPB) memory map The PPB is part of the defined ARM bus architecture and provides access to select processor-local modules. These resources are only accessible from the core; other system masters do not have access to them. Table 4-3. PPB memory map System 32-bit Address Range Resource 0xE000_0000-0xE000_0FFF Instrumentation Trace Macrocell (ITM) 0xE000_1000-0xE000_1FFF Data Watchpoint and Trace (DWT) 0xE000_2000-0xE000_2FFF Flash Patch and Breakpoint (FPB) 0xE000_3000-0xE000_DFFF Reserved 0xE000_E000-0xE000_EFFF System Control Space (SCS) (for NVIC and FPU) 0xE000_F000-0xE003_FFFF Reserved 0xE004_0000-0xE004_0FFF Trace Port Interface Unit (TPIU) 0xE004_1000-0xE004_1FFF Reserved 0xE004_2000-0xE004_2FFF Reserved 0xE004_3000-0xE004_3FFF Reserved 0xE004_4000-0xE007_FFFF Reserved 0xE008_0000-0xE008_0FFF Miscellaneous Control Module (MCM) 0xE008_1000-0xE008_1FFF Reserved Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 142 NXP Semiconductors Chapter 4 Memory Map Table 4-3. PPB memory map (continued) System 32-bit Address Range Resource 0xE008_2000-0xE00F_EFFF Reserved 0xE00F_F000-0xE00F_FFFF ROM Table - allows auto-detection of debug components K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 143 Private Peripheral Bus (PPB) memory map K22F Sub-Family Reference Manual, Rev. 4, 08/2016 144 NXP Semiconductors Chapter 5 Clock Distribution 5.1 Introduction The MCG module controls which clock source is used to derive the system clocks. The clock generation logic divides the selected clock source into a variety of clock domains, including the clocks for the system bus masters, system bus slaves, and flash memory . The clock generation logic also implements module-specific clock gating to allow granular shutoff of modules. The primary clocks for the system are generated from the MCGOUTCLK clock. The clock generation circuitry provides several clock dividers that allow different portions of the device to be clocked at different frequencies. This allows for trade-offs between performance and power dissipation. Various modules, such as the USB OTG Controller, have module-specific clocks that can be generated from the IRC48MCLK or MCGFLLCLK clock. In addition, there are various other module-specific clocks that have other alternate sources. Clock selection for most modules is controlled by the SOPT registers in the SIM module. 5.2 Programming model The selection and multiplexing of system clock sources is controlled and programmed via the MCG module. The setting of clock dividers and module clock gating for the system are programmed via the SIM module. Reference those sections for detailed register and bit descriptions. 5.3 High-Level device clocking diagram The following system oscillator, MCG, and SIM module registers control the multiplexers, dividers, and clock gates shown in the below figure: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 145 Clock definitions OSC MCG SIM Multiplexers MCG_Cx MCG_Cx SIM_SOPT1, SIM_SOPT2 Dividers -- MCG_Cx SIM_CLKDIVx Clock gates OSC_CR MCG_C1 SIM_SCGCx SIM MCG 4 MHz IRC FCRDIV MCGIRCLK CG 32 kHz IRC MCGFFCLK FLL Clock options for some peripherals (see note) OUTDIV1 CG Core / system clocks OUTDIV2 CG Bus clock OUTDIV4 CG Flash clock MCGOUTCLK MCGFLLCLK FRDIV System oscillator EXTAL0 OSCERCLK_UNDIV XTAL_CLK XTAL0 IRC48MCLK OSCCLK OSC logic OSCERCLK DIV OSC32KCLK ERCLK32K PMC RTC oscillator EXTAL32 XTAL32 32.768 kHz OSC logic 1 Hz PMC logic IRC48M internal oscillator IRC48M logic Clock options for some peripherals (see note) MCGFLLCLK/ IRC48MCLK LPO RTC_CLKOUT IRC48MCLK CG -- Clock gate Note: See subsequent sections for details on where these clocks are used. Figure 5-1. Clocking diagram 5.4 Clock definitions The following table describes the clocks in the previous block diagram. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 146 NXP Semiconductors Chapter 5 Clock Distribution Clock name Description Core clock MCGOUTCLK divided by OUTDIV1 clocks the ARM CortexM4 core Platform clock MCGOUTCLK divided by OUTDIV1, clocks the crossbar switch and NVIC. System clock MCGOUTCLK divided by OUTDIV1, clocks the bus masters directly. In addition, this clock is used for UART0 and UART1. Bus clock MCGOUTCLK divided by OUTDIV2 clocks the bus slaves and peripheral (excluding memories) Flash clock MCGOUTCLK divided by OUTDIV4 clocks the flash memory MCGIRCLK MCG output of the slow or fast internal reference clock MCGFFCLK MCG output of the slow internal reference clock or a divided MCG external reference clock. MCGOUTCLK MCG output of either IRC, MCGFLLCLK or MCG's external reference clock that sources the core, system, bus, and flash clock. It is also an option for the debug trace clock. MCGFLLCLK MCG output of the FLL. MCGFLLCLK may clock some modules. IRC48MCLK Internal 48 MHz oscillator that can be used as a reference to the MCG and also may clock some on-chip modules. OSCCLK System oscillator output of the internal oscillator or sourced directly from EXTAL OSCERCLK System oscillator output sourced from OSCCLK that may clock some on-chip modules. Dividable by 1, 2, 4, or 8. OSC32KCLK System oscillator 32kHz output ERCLK32K Clock source for some modules that is chosen as OSC32KCLK or the RTC clock. RTC clock RTC oscillator output for the RTC module LPO PMC 1kHz output 5.4.1 Device clock summary The following table provides more information regarding the on-chip clocks. Table 5-1. Clock Summary Clock name High Speed Run mode Run mode VLPR mode clock frequency clock frequency Clock source Clock is disabled when... clock frequency MCGOUTCLK Up to 100 MHz Up to 100 MHz Up to 4 MHz MCG In all stop modes except for partial stop modes. MCGFLLCLK Up to 100 MHz Up to 100 MHz N/A MCG MCG clock controls do not enable. Overriding forced disable in all low Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 147 Clock definitions Table 5-1. Clock Summary (continued) Clock name High Speed Run mode Run mode VLPR mode clock frequency clock frequency Clock source Clock is disabled when... clock frequency powers modes (including STOP and VLPx modes). Core clock Up to 100 MHz Up to 72 MHz Up to 4 MHz MCGOUTCLK clock divider In all wait and stop modes System clock Up to 100 MHz Up to 72 MHz Up to 4 MHz MCGOUTCLK clock divider In all stop modes and Compute Operation Bus clock Up to 50 MHz Up to 50 MHz Up to 4 MHz MCGOUTCLK clock divider In all stop modes except for partial STOP2 mode, and Compute Operation Flash clock Up to 25 MHz Up to 25 MHz Up to 1 MHz in BLPE, Up to 800 kHz in BLPI MCGOUTCLK clock divider In all stop modes except for partial STOP2 mode 30-40 kHz or 4 MHz 4 MHz only MCG MCG_C1[IRCLKEN ] cleared, Internal reference 30-40 kHz or 4 MHz (MCGIRCLK) Stop or VLPS mode and MCG_C1[IREFSTE N] cleared, or LLS/VLLS mode External reference Up to 50 MHz (bypass), (OSCERCLK) 30-40 kHz, or 3-32 MHz (crystal) Up to 50 MHz (bypass), Up to 16 MHz (bypass), 30-40 kHz, or 30-40 kHz (lowrange crystal) or 3-32 MHz (crystal) System OSC Stop mode and OSC_CR[EREFST EN] cleared Up to 16 MHz (high-range crystal) External reference 30-40 kHz 32kHz 30-40 kHz 30-40 kHz (ERCLK32K) Internal 48 MHz clock 48 MHz 48 MHz N/A System OSC's OSC_CR[ERCLKE N] cleared, or System OSC or LPO or RTC OSC depending on SIM_SOPT1[OSC3 2KSEL] System OSC's OSC_CR[ERCLKE N] cleared IRC48M USB MCG or SIM control does not enable. (IRC48MCLK) or RTC's RTC_CR[OSCE] cleared Overriding forced disable in VLPS, LLSx, VLLSx. RTC_CLKOUT 1 Hz or 32 kHz 1 Hz or 32 kHz 1 Hz or 32 kHz RTC clock RTC_CLKOUT is disabled in LLS and VLLSx modes. Overriding clocking is possible via SIM_SOPT1[OSC3 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 148 NXP Semiconductors Chapter 5 Clock Distribution Table 5-1. Clock Summary (continued) Clock name High Speed Run mode Run mode VLPR mode clock frequency clock frequency Clock source Clock is disabled when... clock frequency 2KOUT] to drive CLKOUT32K out in all low power modes. CLKOUT32K 32 kHz 32 kHz 32 kHz ERCLK32K - which is system OSC or LPO or RTC OSC depending on SIM_SOPT1[OSC3 2KSEL] SIM_SOPT1[OSC3 2KOUT] not configured to drive ERCLK32K out. LPO 1 kHz 1 kHz 1 kHz PMC in VLLS0 48 MHz 48 MHz N/A IRC48MCLK or MCGFLLCLK with fractional clock divider, or USB FS OTG is disabled USB FS clock USB_CLKIN I2S master clock Up to 25 MHz Up to 25 MHz Up to 12.5 MHz System clock , IRC48MCLK, OSCERCLK with fractional clock divider, or I2S is disabled I2S_CLKIN TRACE clock Up to 100 MHz Up to 100 MHz Up to 4 MHz System clock or Trace is disabled MCGOUTCLK LPUART0 clock Up to 100 MHz Up to 100MHz Up to 16MHz MCGFLLCLK or IRC48MCLK or LPUART0 is disabled MCGIRCLK or OSCERCLK 5.5 Internal clocking requirements The clock dividers are programmed via the SIM module's CLKDIV registers. Each divider is programmable from a divide-by-1 through divide-by-16 setting. The following requirements must be met when configuring the clocks for this device: 1. The core and system clock frequencies must be 100 MHz or slower in HSRUN, 72 MHz or slower in RUN. 2. The bus clock frequency must be programmed to 50 MHz or less in both HSRUN and RUN, and an integer divide of the core clock. The core clock to bus clock ratio is limited to a max value of 8. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 149 Internal clocking requirements 3. The flash clock frequency must be programmed to 25 MHz or less, less than or equal to the bus clock, and an integer divide of the core clock. The core clock to flash clock ratio is limited to a max value of 8. The following are a few of the more common clock configurations for this device: Option 1: Clock Frequency Core clock 50 MHz System clock 50 MHz Bus clock 50 MHz Flash clock 25 MHz Option 2: Run Clock Frequency Core clock 72 MHz System clock 72 MHz Bus clock 36 MHz Flash clock 24 MHz Option 3: High Speed Run Clock Frequency Core clock 100 MHz System clock 100 MHz Bus clock 50 MHz Flash clock 25 MHz 5.5.1 Clock divider values after reset Each clock divider is programmed via the SIM module's CLKDIVn registers. The flash memory's FTF_FOPT[LPBOOT] bit controls the reset value of the core clock, system clock, bus clock, and flash clock dividers as shown below: FTF_FOPT [LPBOOT] Core/system clock Bus clock Flash clock Description 0 0x7 (divide by 8) 0x7 (divide by 8) 0xF (divide by 16) Low power boot 1 0x0 (divide by 1) 0x0 (divide by 1) 0x1 (divide by 2) Fast clock boot K22F Sub-Family Reference Manual, Rev. 4, 08/2016 150 NXP Semiconductors Chapter 5 Clock Distribution This gives the user flexibility for a lower frequency, low-power boot option. The flash erased state defaults to fast clocking mode, since where the low power boot (FTF_FOPT[LPBOOT]) bit resides in flash is logic 1 in the flash erased state. To enable the low power boot option program FTF_FOPT[LPBOOT] to zero. During the reset sequence, if LPBOOT is cleared, the system is in a slow clock configuration. Upon any system reset, the clock dividers return to this configurable reset state. 5.5.2 VLPR mode clocking The clock dividers cannot be changed while in VLPR mode. They must be programmed prior to entering VLPR mode to guarantee: * the core/system and bus clocks are less than or equal to 4 MHz, and * the flash memory clock is less than or equal to 1 MHz NOTE When the MCG is in BLPI and clocking is derived from the Fast IRC, the clock divider controls, MCG_SC[FCRDIV] and SIM_CLKDIV1[OUTDIV4], must be programmed such that the resulting flash clock nominal frequency is 800 kHz or less. In this case, one example of correct configuration is MCG_SC[FCRDIV]=000b and SIM_CLKDIV1[OUTDIV4]=0100b, resulting in a divide by 5 setting. 5.6 Clock Gating The clock to each module can be individually gated on and off using the SIM module's SCGCx registers. These bits are cleared after any reset, which disables the clock to the corresponding module to conserve power. Prior to initializing a module, set the corresponding bit in SCGCx register to enable the clock. Before turning off the clock, make sure to disable the module. Any bus access to a peripheral that has its clock disabled generates an error termination. 5.7 Module clocks The following table summarizes the clocks associated with each module. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 151 Module clocks Table 5-2. Module clocks Module Bus interface clock Internal clocks I/O interface clocks Core modules ARM Cortex-M4 core System clock Core clock -- NVIC System clock -- -- DAP System clock -- -- ITM System clock -- -- cJTAG, JTAGC -- -- JTAG_CLK DMA System clock -- -- DMA Mux Bus clock -- -- Port control Bus clock LPO -- Crossbar Switch System clock -- -- Peripheral bridges System clock Bus clock, Flash clock -- LLWU, PMC, SIM, RCM Flash clock LPO -- Mode controller Flash clock -- -- System modules MCM System clock -- -- EWM Bus clock LPO -- Watchdog timer Bus clock LPO -- Clocks MCG Flash clock MCGOUTCLK, MCGFLLCLK, MCGIRCLK, OSCCLK, RTC OSC, IRC48MCLK -- OSC Bus clock OSCERCLK, OSCCLK, OSCERCLK_UNDIV, OSC32KCLK -- IRC48M -- IRC48MCLK -- Memory and memory interfaces Flash Controller System clock Flash clock -- Flash memory Flash clock -- -- EzPort System clock -- EZP_CLK -- -- Security CRC Bus clock Analog ADC Bus clock OSCERCLK , IRC48MCLK -- CMP Bus clock -- -- DAC Bus clock -- -- VREF Flash clock -- -- Timers PDB Bus clock -- -- FlexTimers Bus clock MCGFFCLK FTM_CLKINx PIT Bus clock -- -- Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 152 NXP Semiconductors Chapter 5 Clock Distribution Table 5-2. Module clocks (continued) Module Bus interface clock Internal clocks I/O interface clocks LPTMR Flash clock LPO, OSCERCLK_UNDIV, MCGIRCLK, ERCLK32K -- RTC Flash clock EXTAL32 -- Communication interfaces USB FS OTG System clock USB FS clock -- DSPI Bus clock -- DSPI_SCK I2C Bus clock -- I2C_SCL UART0, UART1 System clock -- -- UART2 Bus clock -- -- LPUART0 Bus clock LPUART0 clock -- Bus clock I2S I2S master clock I2S_TX_BCLK, I2S_RX_BCLK Human-machine interfaces GPIO Platform clock -- -- 5.7.1 PMC 1-kHz LPO clock The Power Management Controller (PMC) generates a 1-kHz clock that is enabled in all modes of operation, including all low power modes except VLLS0. This 1-kHz source is commonly referred to as LPO clock or 1-kHz LPO clock. 5.7.2 IRC 48MHz clock The integrated 48 MHz internal reference clock source (IRC48MCLK) is available in High Speed Run, Run, WAIT and Stop modes of operation. IRC48MCLK is also available in Compute Only, PSTOP2 and PSTOP1 modes of operation when entered from Run mode. IRC48MCLK is forced disabled when the MCU transitions into VLPS, LLSx, and VLLSx low power modes. NOTE IRC48MCLK is not forced disabled in Stop modes and should be disabled by software prior to Stop entry unless it is required. IRC48MCLK is not forced disabled in VLPR and should be disabled by software prior to VLPR entry. IRC48MCLK is enabled via any of the following control settings while operating in these modes: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 153 Module clocks * USB Control register enables -- enabled when USB_CLK_RECOVER_IRC_EN[IRC_EN]=1 * MCG Control register selects IRC48 MHz clock (enabled when MCG_C7[OSCSEL]=10) and MCG is configured in an external clocking mode (FBE or FEE). * SIM Control register selects IRC48 MHz clock -- enabled when SIM_SOPT2[PLLFLLSEL]=11 In USB Device applications, the IRC48M block can be enabled in USB Clock Recovery mode in which the internal IRC48M oscillator is tuned to match the clock extracted from the incoming USB data stream. This functionality provides the capability of generating a high precision 48MHz clock source without requiring an on-chip PLL or an associated off-chip crystal circuit. If the USB Device connection is removed from the Host, the IRC48M USB Clock Recovery functionality stops tuning the internal IRC48M oscillator since the clock extracted from the USB data stream is disconnected. The 48MHz clock source frequency does not shift after the USB Device is removed from the USB Host. The IRC48MCLK is also available for use as: * an oscillator reference to the MCG - from which core, system, bus, and flash clock sources can be derived * an ADC alternate clock source * clock source for LPUART communications * clock source for I2S/SAI communications 5.7.3 WDOG clocking The WDOG may be clocked from two clock sources as shown in the following figure. LPO WDOG clock Bus clock WDOG_STCTRLH[CLKSRC] Figure 5-2. WDOG clock generation K22F Sub-Family Reference Manual, Rev. 4, 08/2016 154 NXP Semiconductors Chapter 5 Clock Distribution 5.7.4 Debug trace clock The debug trace clock source can be clocked as shown in the following figure. MCGOUTCLK TRACECLKIN Debug Core / system clock SIM_SOPT2[TRACECLKSEL] Figure 5-3. Trace clock generation 5.7.5 PORT digital filter clocking The digital filters in the PORTD module can be clocked as shown in the following figure. NOTE In stop mode, the digital input filters are bypassed unless they are configured to run from the 1 kHz LPO clock source. Bus clock PORTx digital input filter clock LPO PORTx_DFCR[CS] Figure 5-4. PORTx digital input filter clock generation K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 155 Module clocks 5.7.6 LPTMR clocking The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown in the following figure. NOTE The chosen clock must remain enabled if the LPTMRx is to continue operating in all required low-power modes. MCGIRCLK LPO LPTMRx prescaler/glitch filter clock ERCLK32K OSCERCLK_UNDIV LPTMRx_PSR[PCS] Figure 5-5. LPTMRx prescaler/glitch filter clock generation 5.7.7 RTC_CLKOUT and CLKOUT32K clocking When the RTC is enabled, the RTC_CLKOUT signal can be configured to drive to an external pin via the associated pin muxing control, as shown below. NOTE RTC_CLKOUT is disabled in LLSx and VLLSx modes. CLKOUT32K, controlled by SIM_SOPT1[OSC32KOUT], can also be driven on the pins where the RTC_CLKOUT signal is an option, overriding the existing pin mux configuration for that pin. The CLKOUT32K function is available in all modes of operation. In VLLS0 mode only the RTC oscillator is available. PTE0 is available in all packages for this device. PTE26 is not available in 64-pin packages for this device. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 156 NXP Semiconductors Chapter 5 Clock Distribution SIM_SOPT1[OSC32KSEL] SIM_SOPT1[OSC32KOUT] 01 OSC32KCLK 00 Pad interface ERCLK32K LPO 11 10 PTE26/CLKOUT32K Other modules RTC_CR[CLKO] RTC 32kHz clock Other modules Pad interface 10 PTE0/CLKOUT32K 1 RTC_CLKOUT RTC 1Hz clock 0 SIM_SOPT2[RTCCLKOUTSEL] Figure 5-6. RTC_CLKOUT and CLKOUT32K generation 5.7.8 USB FS OTG Controller clocking The USB FS OTG controller is a bus master attached to the crossbar switch. As such, it uses the system clock. NOTE For the USB FS OTG controller to operate, the minimum system clock frequency is 20 MHz. The USB OTG controller also requires a 48 MHz clock. The clock source options are shown below. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 157 Module clocks USB_CLKIN USB 48MHz MCGFLLCLK SIM_CLKDIV2 [USBFRAC, USBDIV] IRC48MCLK SIM_SOPT2[PLLFLLSEL] SIM_SOPT2[USBSRC] Figure 5-7. USB 48 MHz clock source NOTE The MCGFLLCLK does not meet the USB jitter specifications for certification. The IRC48MCLK is only usable as a USB clock source in USB Device operation with the USB Clock Recover function enabled. 5.7.9 UART clocking UART0 and UART1 modules operate from the core/system clock, which provides higher performance level for these modules. All other UART modules operate from the bus clock. 5.7.10 LPUART0 clocking The LPUART0 module has a selectable clock as shown in the following figure. NOTE The chosen clock must remain enabled if the LPUART0 is to continue operating in all required low-power modes. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 158 NXP Semiconductors Chapter 5 Clock Distribution MCGIRCLK OSCERCLK LPUART0 clock MCGFLLCLK IRC48MCLK SIM_SOPT2[PLLFLLSEL] SIM_SOPT2[LPUARTSRC] Figure 5-8. LPUART0 clock generation 5.7.11 I2S/SAI clocking The audio master clock (MCLK) is used to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock. The audio master clock can also be output to or input from a pin. The transmitter and receiver have the same audio master clock inputs. Each SAI peripheral can control the input clock selection, pin direction and divide ratio of one audio master clock. The I2S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can be generated internally from the audio master clock or supplied externally. The module also supports the option for synchronous operation between the receiver and transmitter product. The transmitter and receiver can independently select between the bus clock and the audio master clock to generate the bit clock. The MCLK and BCLK source options appear in the following figure. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 159 Module clocks I2S/SAI Clock Generation IRC48MCLK 11 MCGFLLCLK 00 OSCERCLK System Clock 11 10 01 00 BCLK_OUT I2Sx_TCR2/RCR2 Fractional Clock Divider 1 MCLK Bus Clock 0 SIM_SOPT2[PLLFLLSEL] 11 10 01 00 Bit Clock Divider [MSEL] [DIV] 1 BCLK_IN 0 BCLK [BCD] I2Sx_MCR[MOE] I2Sx_MDR[FRACT,DIVIDE] I2Sx_MCR[MICS] MCLK_IN MCLK_OUT Direction Control Pad Interface Logic Figure 5-9. I2S/SAI clock generation K22F Sub-Family Reference Manual, Rev. 4, 08/2016 160 NXP Semiconductors Chapter 6 Reset and Boot 6.1 Introduction The following reset sources are supported in this MCU: Table 6-1. Reset sources Reset sources POR reset System resets Debug reset Description * Power-on reset (POR) * * * * * * * * * * External pin reset (PIN) Low-voltage detect (LVD) Computer operating properly (COP) watchdog reset Low leakage wakeup (LLWU) reset Multipurpose clock generator loss of clock (LOC) reset Stop mode acknowledge error (SACKERR) Software reset (SW) Lockup reset (LOCKUP) EzPort reset MDM DAP system reset * JTAG reset * nTRST reset Each of the system reset sources has an associated bit in the system reset status (SRS) registers. See the Reset Control Module for register details. The MCU exits reset in functional mode that is controlled by EZP_CS pin to select between the single chip (default) or serial flash programming (EzPort) modes. See Boot options for more details. 6.2 Reset This section discusses basic reset mechanisms and sources. Some modules that cause resets can be configured to cause interrupts instead. Consult the individual peripheral chapters for more information. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 161 Reset 6.2.1 Power-on reset (POR) When power is initially applied to the MCU or when the supply voltage drops below the power-on reset re-arm voltage level (VPOR), the POR circuit causes a POR reset condition. As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has risen above the LVD low threshold (VLVDL). The POR and LVD bits in SRS0 register are set following a POR. 6.2.2 System reset sources Resetting the MCU provides a way to start processing from a known set of initial conditions. System reset begins with the on-chip regulator in full regulation and system clocking generation from an internal reference. When the processor exits reset, it performs the following: * Reads the start SP (SP_main) from vector-table offset 0 * Reads the start PC from vector-table offset 4 * LR is set to 0xFFFF_FFFF The on-chip peripheral modules are disabled and the non-analog I/O pins are initially configured as disabled. The pins with analog functions assigned to them default to their analog function after reset. During and following a reset, the JTAG pins have their associated input pins configured as: * TDI in pull-up (PU) * TCK in pull-down (PD) * TMS in PU and associated output pin configured as: * TDO with no pull-down or pull-up Note that the nTRST signal is initially configured as disabled, however once configured to its JTAG functionality its associated input pin is configured as: * nTRST in PU K22F Sub-Family Reference Manual, Rev. 4, 08/2016 162 NXP Semiconductors Chapter 6 Reset and Boot 6.2.2.1 External pin reset (PIN) On this device, RESET is a dedicated pin. This pin is open drain and has an internal pullup device. Asserting RESET wakes the device from any mode. During a pin reset, the RCM's SRS0[PIN] bit is set. 6.2.2.1.1 RESET pin filter The RESET pin filter supports filtering from both the 1 kHz LPO clock and the bus clock. RCM_RPFC[RSTFLTSS], RCM_RPFC[RSTFLTSRW], and RCM_RPFW[RSTFLTSEL] control this functionality; see the RCM chapter. The filters are asynchronously reset by Chip POR. The reset value for each filter assumes the RESET pin is negated. For all stop modes where LPO clock is still active (Stop, VLPS, LLS, VLLS3, VLLS2, and VLLS1), the only filtering option is the LPO-based digital filter. The filtering logic either switches to bypass operation or has continued filtering operation depending on the filtering mode selected. When entering VLLS0, the RESET pin filter is disabled and bypassed. The LPO filter has a fixed filter value of 3. Due to a synchronizer on the input data, there is also some associated latency (2 cycles). As a result, 5 cycles are required to complete a transition from low to high or high to low. 6.2.2.2 Low-voltage detect (LVD) The chip includes a system for managing low voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system consists of a power-on reset (POR) circuit and an LVD circuit with a user-selectable trip voltage. The LVD system is always enabled in hsrun, normal run, wait, or stop mode. The LVD system is disabled when entering VLPx, LLS, or VLLSx modes. The LVD can be configured to generate a reset upon detection of a low voltage condition by setting the PMC's LVDSC1[LVDRE] bit to 1. The low voltage detection threshold is determined by the PMC's LVDSC1[LVDV] field. After an LVD reset has occurred, the LVD system holds the MCU in reset until the supply voltage has risen above the low voltage detection threshold. The RCM's SRS0[LVD] bit is set following either an LVD reset or POR. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 163 Reset 6.2.2.3 Computer operating properly (COP) watchdog timer The computer operating properly (COP) watchdog timer (WDOG) monitors the operation of the system by expecting periodic communication from the software. This communication is generally known as servicing (or refreshing) the COP watchdog. If this periodic refreshing does not occur, the watchdog issues a system reset. The COP reset causes the RCM's SRS0[WDOG] bit to set. 6.2.2.4 Low leakage wakeup (LLWU) The LLWU module provides the means for a number of external pins, the RESET pin, and a number of internal peripherals to wake the MCU from low leakage power modes. The LLWU module is functional only in low leakage power modes. * In LLS mode, only the RESET pin via the LLWU can generate a system reset. * In VLLSx modes, all enabled inputs to the LLWU can generate a system reset. After a system reset, the LLWU retains the flags indicating the input source of the last wakeup until the user clears them. NOTE Some flags are cleared in the LLWU and some flags are required to be cleared in the peripheral module. Refer to the individual peripheral chapters for more information. 6.2.2.5 Multipurpose clock generator loss-of-clock (LOC) The MCG module supports an external reference clock. If the C6[CME] bit in the MCG module is set, the clock monitor is enabled. If the external reference falls below floc_low or floc_high, as controlled by the C2[RANGE] field in the MCG module, the MCU resets. The RCM's SRS0[LOC] bit is set to indicate this reset source. NOTE To prevent unexpected loss of clock reset events, all clock monitors should be disabled before entering any low power modes, including VLPR and VLPW. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 164 NXP Semiconductors Chapter 6 Reset and Boot 6.2.2.6 Stop mode acknowledge error (SACKERR) This reset is generated if the core attempts to enter stop mode, but not all modules acknowledge stop mode within 1025 cycles of the 1 kHz LPO clock. A module might not acknowledge the entry to stop mode if an error condition occurs. The error can be caused by a failure of an external clock input to a module. 6.2.2.7 Software reset (SW) The SYSRESETREQ bit in the NVIC application interrupt and reset control register can be set to force a software reset on the device. (See ARM's NVIC documentation for the full description of the register fields, especially the VECTKEY field requirements.) Setting SYSRESETREQ generates a software reset request. This reset forces a system reset of all major components except for the debug module. A software reset causes the RCM's SRS1[SW] bit to set. 6.2.2.8 Lockup reset (LOCKUP) The LOCKUP gives immediate indication of seriously errant kernel software. This is the result of the core being locked because of an unrecoverable exception following the activation of the processor's built in system state protection hardware. The LOCKUP condition causes a system reset and also causes the RCM's SRS1[LOCKUP] bit to set. 6.2.2.9 EzPort reset The EzPort supports a system reset request via EzPort signaling. The EzPort generates a system reset request following execution of a Reset Chip (RESET) command via the EzPort interface. This method of reset allows the chip to boot from flash memory after it has been programmed by an external source. The EzPort is enabled or disabled by the EZP_CS pin. An EzPort reset causes the RCM's SRS1[EZPT] bit to set. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 165 Reset 6.2.2.10 MDM-AP system reset request Set the system reset request bit in the MDM-AP control register to initiate a system reset. This is the primary method for resets via the JTAG/SWD interface. The system reset is held until this bit is cleared. Set the core hold reset bit in the MDM-AP control register to hold the core in reset as the rest of the chip comes out of system reset. 6.2.3 MCU Resets A variety of resets are generated by the MCU to reset different modules. 6.2.3.1 VBAT POR The VBAT POR asserts on a VBAT POR reset source. It affects only the modules within the VBAT power domain: RTC and VBAT Register File. These modules are not affected by the other reset types. 6.2.3.2 POR Only The POR Only reset asserts on the POR reset source only. It resets the PMC and System Register File. The POR Only reset also causes all other reset types (except VBAT POR) to occur. 6.2.3.3 Chip POR not VLLS The Chip POR not VLLS reset asserts on POR and LVD reset sources. It resets parts of the SMC and SIM. It also resets the LPTMR. The Chip POR not VLLS reset also causes these resets to occur: Chip POR, Chip Reset not VLLS, and Chip Reset (including Early Chip Reset). 6.2.3.4 Chip POR The Chip POR asserts on POR, LVD, and VLLS Wakeup reset sources. It resets the Reset Pin Filter registers and parts of the SIM and MCG. The Chip POR also causes the Chip Reset (including Early Chip Reset) to occur. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 166 NXP Semiconductors Chapter 6 Reset and Boot 6.2.3.5 Chip Reset not VLLS The Chip Reset not VLLS reset asserts on all reset sources except a VLLS Wakeup that does not occur via the RESET_b pin. It resets parts of the SMC, LLWU, and other modules that remain powered during VLLS mode. The Chip Reset not VLLS reset also causes the Chip Reset (including Early Chip Reset) to occur. 6.2.3.6 Early Chip Reset The Early Chip Reset asserts on all reset sources. It resets only the flash memory module. It negates before flash memory initialization begins ("earlier" than when the Chip Reset negates). 6.2.3.7 Chip Reset Chip Reset asserts on all reset sources and only negates after flash initialization has completed and the RESET_b pin has also negated. It resets the remaining modules (the modules not reset by other reset types). 6.2.4 Reset Pin For all reset sources except a VLLS Wakeup that does not occur via the RESET pin, the RESET pin is driven low by the MCU for at least 128 bus clock cycles and until flash initialization has completed. After flash initialization has completed, the RESET pin is released, and the internal Chip Reset negates after the RESET pin is pulled high. Keeping the RESET pin asserted externally delays the negation of the internal Chip Reset. 6.2.5 Debug resets The following sections detail the debug resets available on the device. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 167 Reset 6.2.5.1 JTAG reset The JTAG module generate a system reset when certain IR codes are selected. This functional reset is asserted when EzPort, EXTEST, HIGHZ and CLAMP instructions are active. The reset source from the JTAG module is released when any other IR code is selected. A JTAG reset causes the RCM's SRS1[JTAG] bit to set. 6.2.5.2 nTRST reset The nTRST pin causes a reset of the JTAG logic when asserted. Asserting the nTRST pin allows the debugger to gain control of the TAP controller state machine (after exiting LLS or VLLSx) without resetting the state of the debug modules. The nTRST pin does not cause a system reset. 6.2.5.3 Resetting the Debug subsystem Use the CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register to reset the debug modules. However, as explained below, using the CDBGRSTREQ bit does not reset all debug-related registers. CDBGRSTREQ resets the debug-related registers within the following modules: * * * * SWJ-DP AHB-AP TPIU MDM-AP (MDM control and status registers) CDBGRSTREQ does not reset the debug-related registers within the following modules: * * * * * * * * CM4 core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR) FPB DWT ITM NVIC Crossbar bus switch1 AHB-AP1 Private peripheral bus1 1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available during System Reset. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 168 NXP Semiconductors Chapter 6 Reset and Boot 6.3 Boot This section describes the boot sequence, including sources and options. 6.3.1 Boot sources This device only supports booting from internal flash. Any secondary boot must go through an initialization sequence in flash. 6.3.2 Boot options The device's functional mode is controlled by the state of the EzPort chip select (EZP_CS) pin during reset. The device can be in single chip (default) or serial flash programming mode (EzPort). While in single chip mode the device can be in run or various low power modes mentioned in Power mode transitions. Table 6-2. Mode select decoding EzPort chip select (EZP_CS) Description 0 Serial flash programming mode (EzPort) 1 Single chip (default) 6.3.3 FOPT boot options The flash option register (FOPT) in the flash memory module allows the user to customize the operation of the MCU at boot time. The register contains read-only bits that are loaded from the NVM's option byte in the flash configuration field. The user can reprogram the option byte in flash to change the FOPT values that are used for subsequent resets. For more details on programming the option byte, refer to the flash memory chapter. The MCU uses the FOPT register bits to configure the device at reset as shown in the following table. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 169 Boot NOTE Reserved bits in the option byte should be left in their default erased state of logic 1. FOPT[7:0] = 0x00 is not a valid configuration. FOPT register is written to 0xFF if the contents of NVM's option byte in the flash configuration field is 0x00. Table 6-3. Flash Option Register Bit Definitions Bit Num Field Value Definition 7-6 Reserved Reserved for future expansion. 5 FAST_INIT Select initialization speed on POR, VLLSx, and any system reset. 0 Slower initialization. The Flash initialization will be slower with the benefit of reduced average current during this time. The duration of the recovery will be controlled by the clock divider selection determined by the LPBOOT setting. 1 Fast Initialization.The Flash has faster recoveries at the expense of higher current during these times. 4-3 Reserved Reserved for future expansion. 2 NMI_DIS Enable/disable control for the NMI function. 1 0 EZPORT_DIS LPBOOT 0 NMI interrupts are always blocked. The associated pin continues to default to NMI pin controls with internal pullup enabled. 1 NMI pin/interrupts reset default to enabled. Enable/disable EzPort function. 0 EzPort operation is disabled. The device always boots to normal CPU execution and the state of EZP_CS signal during reset is ignored. This option avoids inadvertent resets into EzPort mode if the EZP_CS/NMI pin is used for its NMI function. 1 EzPort operation is enabled. The state of EZP_CS pin during reset determines if device enters EzPort mode. Control the reset value of OUTDIVx values in SIM_CLKDIV1 register. Larger divide value selections produce lower average power consumption during POR, VLLSx recoveries and reset sequencing and after reset exit. The recovery times are also extended if the FAST_INIT option is not selected. 0 Low-power boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured at reset exit for higher divide values that produce lower power consumption at reset exit. * Core and system clock divider (OUTDIV1) and bus clock divider (OUTDIV2) are 0x7 (divide by 8) * Flash clock divider (OUTDIV4)is 0xF (divide by 16) 1 Normal boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured at reset exit for higher frequency values that produce faster operating frequencies at reset exit. * Core and system clock divider (OUTDIV1) and bus clock divider (OUTDIV2) are 0x0 (divide by 1) * Flash clock divider (OUTDIV4)is 0x1 (divide by 2) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 170 NXP Semiconductors Chapter 6 Reset and Boot 6.3.4 Boot sequence At power up, the on-chip regulator holds the system in a POR state until the input supply is above the POR threshold. The system continues to be held in this static state until the internally regulated supplies have reached a safe operating voltage as determined by the LVD. The Mode Controller reset logic then controls a sequence to exit reset. 1. A system reset is held on internal logic, the RESET pin is driven out low, and the MCG is enabled in its default clocking mode. 2. Required clocks are enabled (Core Clock, System Clock, Flash Clock, and any Bus Clocks that do not have clock gate control reset to disabled). 3. The system reset on internal logic continues to be held, but the Flash Controller is released from reset and begins initialization operation while the Reset Control logic continues to drive the RESET pin out low. 4. Early in reset sequencing the NVM option byte is read and stored to the Flash Memory module's FOPT register. If the LPBOOT is programmed for an alternate clock divider reset value, the system/core clock is switched to a slower clock speed. If the FAST_INIT bit is programmed clear, the Flash initialization switches to slower clock resulting longer recovery times. 5. When Flash Initialization completes, the RESET pin is released. If RESET continues to be asserted (an indication of a slow rise time on the RESET pin or external drive in low), the system continues to be held in reset. Once the RESET pin is detected high, the Core clock is enabled and the system is released from reset. EzPort mode is selected instead of the normal CPU execution if EZP_CS is low when the internal reset is deasserted. EzPort mode can be disabled by programming the FOPT[EZPORT_DIS] field in the Flash Memory module. 6. When the system exits reset, the processor sets up the stack, program counter (PC), and link register (LR). The processor reads the start SP (SP_main) from vector-table offset 0. The core reads the start PC from vector-table offset 4. LR is set to 0xFFFF_FFFF. What happens next depends on the NMI input and the FOPT[NMI_DIS] field in the Flash Memory module: * If the NMI input is high or the NMI function is disabled in the NMI_DIS field, the CPU begins execution at the PC location. * If the NMI input is low and the NMI function is enabled in the NMI_DIS field, this results in an NMI interrupt. The processor executes an Exception Entry and reads the NMI interrupt handler address from vector-table offset 8. The CPU begins execution at the NMI interrupt handler. Subsequent system resets follow this same reset flow. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 171 Boot K22F Sub-Family Reference Manual, Rev. 4, 08/2016 172 NXP Semiconductors Chapter 7 Power Management 7.1 Introduction This chapter describes the various chip power modes and functionality of the individual modules in these modes. 7.2 Clocking modes Information found here describes the various clocking modes supported on this device. 7.2.1 Partial Stop Partial Stop is a clocking option that can be taken instead of entering Stop mode and is configured in the SMC Stop Control Register (SMC_STOPCTRL). The Stop mode is only partially entered, which leaves some additional functionality alive at the expense of higher power consumption. Partial Stop can be entered from either Run mode or VLP Run mode. When configured for PSTOP2, only the core and system clocks are gated and the bus clock remains active. The bus masters and bus slaves clocked by the system clock enter Stop mode, but the bus slaves clocked by bus clock remain in Run (or VLP Run) mode. The clock generators in the MCG and the on-chip regulator in the PMC also remain in Run (or VLP Run) mode. Exit from PSTOP2 can be initiated by a reset, an asynchronous interrupt from a bus master or bus slave clocked by the system clock, or a synchronous interrupt from a bus slave clocked by the bus clock. If configured, a DMA request (using the asynchronous DMA wakeup) can also be used to exit Partial Stop for the duration of a DMA transfer before the device is transitioned back into PSTOP2. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 173 Clocking modes When configured for PSTOP1, both the system clock and bus clock are gated. All bus masters and bus slaves enter Stop mode, but the clock generators in the MCG and the onchip regulator in the PMC remain in Run (or VLP Run) mode. Exit from PSTOP1 can be initiated by a reset or an asynchronous interrupt from a bus master or bus slave. If configured, an asynchronous DMA request can also be used to exit Partial Stop for the duration of a DMA transfer before the device is transitioned back into PSTOP1. PSTOP1 is functionally similar to Stop mode, but offers faster wake-up at the expense of higher power consumption. Another benefit is that it keeps all of the MCG clocks enabled, which can be useful for some of the asynchronous peripherals that can remain functional in Stop modes. 7.2.2 DMA Wakeup The DMA can be configured to wake the device on a DMA request whenever it is placed in Stop mode. The wake-up is configured per DMA channel and is supported in Compute Operation, PSTOP, STOP, and VLPS low power modes. When a DMA wake-up is detected in PSTOP, STOP or VLPS then the device will initiate a normal exit from the low power mode. This can include restoring the on-chip regulator and internal power switches, enabling the clock generators in the MCG, enabling the system and bus clocks (but not the core clock) and negating the stop mode signal to the bus masters and bus slaves. The only difference is that the CPU will remain in the low power mode with the CPU clock disabled. During Compute Operation, a DMA wake-up will initiate a normal exit from Compute Operation. This includes enabling the clocks and negating the stop mode signal to the bus masters and bus slaves. The core clock always remains enabled during Compute Operation. Since the DMA wakeup will enable the clocks and negate the stop mode signals to all bus masters and slaves, software needs to ensure that bus masters and slaves that are not involved with the DMA wake-up and transfer remain in a known state. That can be accomplished by disabling the modules before entry into the low power mode or by setting the Doze enable bit in selected modules. Once the DMA request that initiated the wake-up negates and the DMA completes the current transfer, the device will transition back to the original low-power mode. This includes requesting all non-CPU bus masters to enter Stop mode and then requesting bus slaves to enter Stop mode. In STOP and VLPS modes, MCG and PMC would then also enter their appropriate modes. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 174 NXP Semiconductors Chapter 7 Power Management NOTE If the requested DMA transfer cannot cause the DMA request to negate, then the device will remain in a higher power state until the low power mode is fully exited. An enabled DMA wake-up can cause an aborted entry into the low power mode, if the DMA request asserts during the stop mode entry sequence (or reentry if the request asserts during a DMA wakeup) and can cause the SMC to assert its Stop Abort flag. Once the DMA wake-up completes, entry into the low power mode will restart. An interrupt that occurs during a DMA wake-up will cause an immediate exit from the low power mode (this is optional for Compute Operation) without impacting the DMA transfer. A DMA wake-up can be generated by either a synchronous DMA request or an asynchronous DMA request. Not all peripherals can generate an asynchronous DMA request in stop modes, although in general if a peripheral can generate synchronous DMA requests and also supports asynchronous interrupts in stop modes, then it can generate an asynchronous DMA request. 7.2.3 Compute Operation Compute Operation is an execution or compute-only mode of operation that keeps the CPU enabled with full access to the SRAM and Flash read port, but places all other bus masters and bus slaves into their stop mode. Compute Operation can be enabled in Run mode, HSRUN mode, or VLP Run mode. NOTE Do not enter any stop mode without first exiting Compute Operation. Because Compute Operation reuses the stop mode logic (including the staged entry with bus masters disabled before bus slaves), any bus master or bus slave that can remain functional in stop mode also remains functional in Compute Operation, including generation of asynchronous interrupts and DMA requests. When enabling Compute Operation in Run mode, module functionality for bus masters and slaves is the equivalent of STOP mode. When enabling Compute Operation in VLP Run mode, module functionality for bus masters and slaves is the equivalent of VLPS mode. The MCG, PMC, SRAM and Flash read port are not affected by Compute Operation, although the Flash register interface is disabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 175 Clocking modes During Compute Operation, the AIPS peripheral space is disabled and attempted accesses generate bus errors. The private peripheral bus (PPB) remains accessible during Compute Operation, including the MCM, System Control Space (SCS) (for NVIC and FPU), and SysTick. Although access to the GPIO registers is supported, the GPIO port data input registers do not return valid data since clocks are disabled to the Port Control and Interrupt modules. By writing to the GPIO port data output registers, it is possible to control those GPIO ports that are configured as output pins. Compute Operation is controlled by the CPO register in the MCM, which is only accessible to the CPU. Setting or clearing the CPOREQ bit in the MCM initiates entry or exit into Compute Operation. Compute Operation can also be configured to exit automatically on detection of an interrupt, which is required in order to service most interrupts. Only the core system interrupts (exceptions, including NMI and SysTick) and any edge sensitive interrupts can be serviced without exiting Compute Operation. When entering Compute Operation, the CPOACK status bit indicates when entry has completed. When exiting Compute Operation in Run mode, the CPOACK status bit negates immediately. When exiting Compute Operation in VLP Run mode, the exit is delayed to allow the PMC to handle the change in power consumption. This delay means the CPOACK bit is polled to determine when the AIPS peripheral space can be accessed without generating a bus error. The DMA wakeup is also supported during Compute Operation and causes the CPOACK status bit to clear and the AIPS peripheral space to be accessible for the duration of the DMA wakeup. At the completion of the DMA wakeup, the device transitions back into Compute Operation. 7.2.4 Peripheral Doze Several peripherals support a Peripheral Doze mode, where a register bit can be used to disable the peripheral for the duration of a low-power mode. The flash memory can also be placed in a low-power state during Peripheral Doze via a register bit in the SIM. Peripheral Doze is defined to include all of the modes of operation listed below. * The CPU is in Wait mode. * The CPU is in Stop mode, including the entry sequence and for the duration of a DMA wakeup. * The CPU is in Compute Operation, including the entry sequence and for the duration of a DMA wakeup. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 176 NXP Semiconductors Chapter 7 Power Management Peripheral Doze can therefore be used to disable selected bus masters or slaves for the duration of WAIT or VLPW mode. It can also be used to disable selected bus slaves immediately on entry into any stop mode (or Compute Operation), instead of waiting for the bus masters to acknowledge the entry as part of the stop entry sequence. Finally, it can be used to disable selected bus masters or slaves that should remain inactive during a DMA wakeup. If the flash memory is not being accessed during WAIT and PSTOP modes, then the Flash Doze mode can be used to reduce power consumption, at the expense of a slightly longer wake-up when executing code and vectors from flash. It can also be used to reduce power consumption during Compute Operation when executing code and vectors from SRAM. 7.2.5 Clock Gating To conserve power, the clocks to most modules can be turned off using the SCGCx registers in the SIM module. These bits are cleared after any reset, which disables the clock to the corresponding module. Prior to initializing a module, set the corresponding bit in the SCGCx register to enable the clock. Before turning off the clock, make sure to disable the module. For more details, refer to the clock distribution and SIM chapters. 7.3 Power Modes Description The power management controller (PMC) provides multiple power options to allow the user to optimize power consumption for the level of functionality needed. Depending on the stop requirements of the user application, a variety of stop modes are available that provide state retention, partial power down or full power down of certain logic and/or memory. I/O states are held in all modes of operation. The following table compares the various power modes available. For Run and VLPR mode there is a corresponding wait and stop mode. Wait modes are similar to ARM sleep modes. Stop modes (VLPS, STOP) are similar to ARM sleep deep mode. The very low power run (VLPR) operating mode can drastically reduce runtime power when the maximum bus frequency is not required to handle the application needs. Stop mode entry is not supported directly from HSRUN and requires transition to Run prior to an attempt to enter a stop mode. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 177 Power Modes Description The three primary modes of operation are run, wait and stop. The WFI instruction invokes both wait and stop modes for the chip. The primary modes are augmented in a number of ways to provide lower power based on application needs. Table 7-1. Chip power modes Chip mode Description Normal run Default mode out of reset; on-chip voltage regulator is on. Core mode Normal recovery method Run - Run - High Speed run Allows maximum performance of chip. In this state, the MCU is able to operate at a faster frequency compared to normal run mode. Normal Wait via WFI Allows peripherals to function while the core is in sleep mode, reducing power. NVIC remains sensitive to interrupts; peripherals continue to be clocked. Sleep Interrupt Normal Stop via WFI Places chip in static state. Lowest power mode that retains all registers while maintaining LVD protection. NVIC is disabled; AWIC is used to wake up from interrupt; peripheral clocks are stopped. Sleep Deep Interrupt Run - Sleep Interrupt VLPS (Very Low Places chip in static state with LVD operation off. Lowest power mode Power Stop)-via with ADC and pin interrupts functional. Peripheral clocks are stopped, WFI but LPTimer, RTC, CMP, DAC can be used. NVIC is disabled (FCLK = OFF); AWIC is used to wake up from interrupt. On-chip voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. All SRAM is operating (content retained and I/O states held). Sleep Deep Interrupt LLS3 (Low State retention power mode. Most peripherals are in state retention Leakage Stop3) mode (with clocks stopped), but LLWU, LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is used to wake up. Sleep Deep Wakeup Interrupt1 Sleep Deep Wakeup Interrupt1 Sleep Deep Wakeup Reset2 VLPR (Very Low On-chip voltage regulator is in a low power mode that supplies only Power Run) enough power to run the chip at a reduced frequency. Reduced frequency Flash access mode (1 MHz); LVD off; internal oscillator provides a low power 4 MHz source for the core, the bus and the peripheral clocks. VLPW (Very Low Power Wait) -via WFI Same as VLPR but with the core in sleep mode to further reduce power; NVIC remains sensitive to interrupts (FCLK = ON). On-chip voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. NOTE: The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery. All SRAM is operating (content retained and I/O states held). LLS2 (Low State retention power mode. Most peripherals are in state retention Leakage Stop2) mode (with clocks stopped), but LLWU, LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is used to wake up. NOTE: The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery. A portion of SRAM_U remains powered on (content retained and I/O states held). VLLS3 (Very Low Leakage Stop3) Most peripherals are disabled (with clocks stopped), but LLWU, LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is used to wake up. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 178 NXP Semiconductors Chapter 7 Power Management Table 7-1. Chip power modes (continued) Chip mode Description Core mode Normal recovery method Sleep Deep Wakeup Reset2 Sleep Deep Wakeup Reset2 Sleep Deep Wakeup Reset2 Off Power-up Sequence SRAM_U and SRAM_L remain powered on (content retained and I/O states held). VLLS2 (Very Low Leakage Stop2) Most peripherals are disabled (with clocks stopped), but LLWU, LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is used to wake up. SRAM_L is powered off. A portion of SRAM_U remains powered on (content retained and I/O states held). VLLS1 (Very Low Leakage Stop1) Most peripherals are disabled (with clocks stopped), but LLWU, LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is used to wake up. All of SRAM_U and SRAM_L are powered off. The 32-byte system register file and 32-byte VBAT register file remain powered for customer-critical data. VLLS0 (Very Low Leakage Stop 0) Most peripherals are disabled (with clocks stopped), but LLWU and RTC can be used. NVIC is disabled; LLWU is used to wake up. All of SRAM_U and SRAM_L are powered off. The 32-byte system register file and 32-byte VBAT register file remain powered for customer-critical data. The POR detect circuit can be optionally powered off. BAT (backup battery only) The chip is powered down except for the VBAT supply. The RTC and the 32-byte VBAT register file for customer-critical data remain powered. 1. Resumes normal run mode operation by executing the LLWU interrupt service routine. 2. Follows the reset flow with the LLWU interrupt flag set for the NVIC. 7.4 Entering and exiting power modes The WFI instruction invokes wait and stop modes for the chip. The processor exits the low-power mode via an interrupt. The Nested Vectored Interrupt Controller (NVIC) describes interrupt operation and what peripherals can cause interrupts. NOTE The WFE instruction can have the side effect of entering a lowpower mode, but that is not its intended usage. See ARM documentation for more on the WFE instruction. Recovery from VLLSx is through the wake-up Reset event. The chip wake-ups from VLLSx by means of reset, an enabled pin or enabled module. See the table "LLWU inputs" in the LLWU configuration section for a list of the sources. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 179 Power mode transitions The wake-up flow from VLLSx is through reset. The wakeup bit in the SRS registers in the RCM is set indicating that the chip is recovering from a low power mode. Code execution begins; however, the I/O pins are held in their pre low power mode entry states, and the system oscillator and MCG registers are reset (even if EREFSTEN had been set before entering VLLSx). Software must clear this hold by writing a 1 to the ACKISO bit in the Regulator Status and Control Register in the PMC module. NOTE To avoid unwanted transitions on the pins, software must reinitialize the I/O pins to their pre-low-power mode entry states before releasing the hold. If the oscillator was configured to continue running during VLLSx modes, it must be reconfigured before the ACKISO bit is cleared. The oscillator configuration within the MCG is cleared after VLLSx recovery and the oscillator will stop when ACKISO is cleared unless the register is re-configured. 7.5 Power mode transitions The following figure shows the power mode transitions. Any reset always brings the chip back to the normal run state. In run, wait, and stop modes active power regulation is enabled. The VLPx modes offer a lower power operating mode than normal modes. VLPR and VLPW are limited in frequency. The LLS and VLLSx mode(s) are the lowest power stop modes based on amount of logic or memory that is required to be retained by the application. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 180 NXP Semiconductors Chapter 7 Power Management Any RESET VLPW HSRUN 4 5 12 VLPR WAIT 1 3 RUN STOP 6 7 2 VLPS 10 8 9 LLS VLLS 11 Figure 7-1. Power mode state transition diagram 7.6 Power modes shutdown sequencing When entering stop or other low-power modes, the clocks are shut off in an orderly sequence to safely place the chip in the targeted low-power state. All low-power entry sequences are initiated by the core executing an WFI instruction. The ARM core's outputs, SLEEPDEEP and SLEEPING, trigger entry to the various low-power modes: * System level wait and VLPW modes equate to: SLEEPING & SLEEPDEEP * All other low power modes equate to: SLEEPING & SLEEPDEEP When entering the non-wait modes, the chip performs the following sequence: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 181 Flash Program Restrictions * Shuts off Core Clock and System Clock to the ARM Cortex-M4 core immediately. * Polls stop acknowledge indications from the non-core crossbar masters (DMA), supporting peripherals (SPI, PIT) and the Flash Controller for indications that System Clocks, Bus Clock and/or Flash Clock need to be left enabled to complete a previously initiated operation, effectively stalling entry to the targeted low power mode. When all acknowledges are detected, System Clock, Bus Clock and Flash Clock are turned off at the same time. * MCG and Mode Controller shut off clock sources and/or the internal supplies driven from the on-chip regulator as defined for the targeted low power mode. In wait modes, most of the system clocks are not affected by the low power mode entry. The Core Clock to the ARM Cortex-M4 core is shut off. Some modules support stop-inwait functionality and have their clocks disabled under these configurations. The debugger modules support a transition from stop, wait, VLPS, and VLPW back to a halted state when the debugger is enabled. This transition is initiated by setting the Debug Request bit in MDM-AP control register. As part of this transition, system clocking is reestablished and is equivalent to normal run/VLPR mode clocking configuration. 7.7 Flash Program Restrictions The flash memory on this device should not be programmed or erased while operating in High Speed Run or VLPR power modes. 7.8 Module Operation in Low Power Modes The following table illustrates the functionality of each module while the chip is in each of the low power modes. The standard behavior is shown with some exceptions for Compute Operation (CPO) and Partial Stop2 (PSTOP2). (Debug modules are discussed separately; see Debug in Low Power Modes.) Number ratings (such as 2 MHz and 1 Mbit/s) represent the maximum frequencies or maximum data rates per mode. Also, these terms are used: * FF = Full functionality. In VLPR and VLPW the system frequency is limited, but if a module does not have a limitation in its functionality, it is still listed as FF. * Async operation = Fully functional with alternate clock source, provided the selected clock source remains enabled * static = Module register states and associated memories are retained. * powered = Memory is powered to retain contents. * low power = Memory is powered to retain contents in a lower power state K22F Sub-Family Reference Manual, Rev. 4, 08/2016 182 NXP Semiconductors Chapter 7 Power Management * OFF = Modules are powered off; module is in reset state upon wakeup. For clocks, OFF means disabled. * wakeup = Modules can serve as a wakeup source for the chip. Table 7-2. Module operation in low power modes Modules VLPR VLPW Stop VLPS LLSx VLLSx static static OFF Core modules NVIC FF FF static Mode Controller FF FF FF FF FF FF static static static static FF FF2 low power low power ON low power low power low power in VLLS2/3, OFF in VLLS0/1 System modules LLWU1 Regulator LVD disabled disabled ON disabled disabled disabled Brown-out Detection ON ON ON ON ON ON in VLLS1/2/3, optionally disabled in VLLS03 DMA FF FF static OFF Async operation Async operation Async operation in CPO Watchdog FF FF FF FF static OFF EWM FF static static static static OFF ON ON ON in VLLS1/2/3, OFF in VLLS0 static in CPO FF in PSTOP2 Clocks 1kHz LPO ON ON ON OSCERCLK max of 16 MHz crystal OSCERCLK max of 16 MHz crystal OSCERCLK optional OSCERCLK limited to low limited to low max of 16 MHz range/low power range/low power crystal in VLLS1/2/3, OFF in VLLS0 MCG 4 MHz IRC 4 MHz IRC static MCGIRCLK optional static MCGIRCLK optional (4 MHz IRC only). static - no clock output OFF Core clock 4 MHz max OFF OFF OFF OFF OFF Platform clock 4 MHz max 4 MHz max OFF OFF OFF OFF System clock 4 MHz max 4 MHz max OFF OFF OFF OFF 4 MHz max OFF OFF OFF OFF System oscillator (OSC) OFF in CPO Bus clock 4 MHz max OFF in CPO 50 MHz max in PSTOP2 from RUN Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 183 Module Operation in Low Power Modes Table 7-2. Module operation in low power modes (continued) Modules VLPR VLPW Stop VLPS LLSx VLLSx OFF OFF 4 MHz max in PSTOP2 from VLPR Memory and memory interfaces Flash 1 MHz max access - no program/erase low power low power low power No register access in CPO System RAM (SRAM_U and SRAM_L) 4 low power low power low power low power low power in low power in LLS3, partial in VLLS3, partial in LLS2 VLLS2; otherwise OFF VBAT Register file5 powered powered powered powered powered powered System Register files powered powered powered powered powered powered EzPort disabled disabled disabled disabled disabled disabled static, wakeup on resume static, wakeup on resume static, wakeup on resume static, wakeup on resume static OFF 250 kbit/s 250 kbit/s static, wakeup on edge static, wakeup on edge static OFF 250 kbit/s static, wakeup on edge static, wakeup on edge static OFF static OFF static static OFF static, address match wakeup static OFF static OFF static OFF Communication interfaces USB FS/LS UART0, UART1 static, wakeup on edge in CPO UART2 250kbit/s static, wakeup on edge in CPO LPUART0 4 Mbps FF in PSTOP2 4 Mbps Async operation in CPO SPI Async operation Async operation FF in PSTOP2 1 Mbit/s (slave) 1 Mbit/s (slave) static 2 Mbit/s (master) 2 Mbit/s (master) FF in PSTOP2 200 kbit/s static, address match wakeup static in CPO I2C 200 kbit/s static, address match wakeup in CPO I2S FF FF in PSTOP2 FF Async operation in CPO Async operation FF with external with external clock6 clock6 FF in PSTOP2 Security CRC FF FF static static Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 184 NXP Semiconductors Chapter 7 Power Management Table 7-2. Module operation in low power modes (continued) Modules VLPR VLPW Stop VLPS LLSx VLLSx static static OFF static static OFF static static OFF static in CPO Timers FTM FF FF static in CPO PIT FF FF in PSTOP2 FF static in CPO PDB FF FF FF static FF in PSTOP2 static in CPO LPTMR static static FF in PSTOP2 FF Async operation Async operation Async operation FF in PSTOP2 RTC - 32kHz OSC5 FF FF Async operation in CPO Async operation Async operation Async operation7 Async operation8 Async operation8 static OFF HS or LS compare LS compare LS compare in VLLS1/2/3, OFF in VLLS0 static static static, OFF in VLLS0 FF in PSTOP2 Analog 16-bit ADC FF FF ADACK and ALTCLK clocks only in CPO ADACK, ADACK and ALTCLK, and ALTCLK clocks ALTCLK2 clocks only only FF in PSTOP2 CMP9 FF FF HS or LS compare in CPO 6-bit DAC FF HS or LS compare FF in PSTOP2 FF static in CPO static FF in PSTOP2 VREF FF FF FF FF static OFF 12-bit DAC FF FF static static static static static output, wakeup input static, pins latched OFF, pins latched static in CPO FF in PSTOP2 Human-machine interfaces GPIO FF FF GPIO write only in CPO static output, wakeup input FF in PSTOP2 1. Using the LLWU module, the external pins available for this chip do not require the associated peripheral function to be enabled. It only requires the function controlling the pin (GPIO or peripheral) to be configured as an input to allow a transition to occur to the LLWU. 2. Since LPO clock source is disabled, filters will be bypassed during VLLS0 3. The SMC_STOPCTRL[PORPO] bit in the SMC module controls this option. 4. A 8 KB portion of SRAM_U block is in low power when MCU is in low power modes LLS2 and VLLS2. The remaining System RAM is OFF in LLS2 and VLLS2. 5. These components remain powered in BAT power mode. 6. Use an externally generated bit clock or an externally generated audio master clock (including EXTAL). 7. System OSC and LPO clock sources are not available in VLLS0. Pulse counting is available in all modes. 8. RTC_CLKOUT is not available. CLKOUT32K can be configured as an alternate path of supplying 32 kHz. 9. CMP in stop or VLPS supports high speed or low speed external pin to pin or external pin to DAC compares. CMP in LLSx or VLLSx only supports low speed external pin to pin or external pin to DAC compares. Windowed, sampled & filtered modes of operation are not available while in stop, VLPS, LLSx, or VLLSx modes. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 185 Module Operation in Low Power Modes K22F Sub-Family Reference Manual, Rev. 4, 08/2016 186 NXP Semiconductors Chapter 8 Security 8.1 Introduction This device implements security based on the mode selected from the flash module. The following sections provide an overview of flash security and details the effects of security on non-flash modules. 8.2 Flash Security The flash module provides security information to the MCU based on the state held by the FSEC[SEC] bits. The MCU, in turn, confirms the security request and limits access to flash resources. During reset, the flash module initializes the FSEC register using data read from the security byte of the flash configuration field. NOTE The security features apply only to external accesses via debug and EzPort. CPU accesses to the flash are not affected by the status of FSEC. In the unsecured state all flash commands are available to the programming interfaces (JTAG and EzPort), as well as user code execution of Flash Controller commands. When the flash is secured (FSEC[SEC] = 00, 01, or 11), programmer interfaces are only allowed to launch mass erase operations and have no access to memory locations. Further information regarding the flash security options and enabling/disabling flash security is available in the Flash Memory Module. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 187 Security Interactions with other Modules 8.3 Security Interactions with other Modules The flash security settings are used by the SoC to determine what resources are available. The following sections describe the interactions between modules and the flash security settings or the impact that the flash security has on non-flash modules. 8.3.1 Security Interactions with EzPort When flash security is active the MCU can still boot in EzPort mode. The EzPort holds the flash logic in NVM special mode and thus limits flash operation when flash security is active. While in EzPort mode and security is active, flash bulk erase (BE) can still be executed. The write FCCOB registers (WRFCCOB) command is limited to the mass erase (Erase All Blocks) and verify all 1s (Read 1s All Blocks) commands. Read accesses to internal memories via the EzPort are blocked when security is enabled. The mass erase can be used to disable flash security, but all of the flash contents are lost in the process. A mass erase via the EzPort is allowed even when some memory locations are protected. When mass erase has been disabled, mass erase via the EzPort is blocked and cannot be defeated. 8.3.2 Security Interactions with Debug When flash security is active the JTAG port cannot access the memory resources of the MCU. Boundary scan chain operations work, but debugging capabilities are disabled so that the debug port cannot read flash contents. Although most debug functions are disabled, the debugger can write to the Flash Mass Erase in Progress bit in the MDM-AP Control register to trigger a mass erase (Erase All Blocks) command. A mass erase via the debugger is allowed even when some memory locations are protected. When mass erase is disabled, mass erase via the debugger is blocked. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 188 NXP Semiconductors Chapter 9 Debug 9.1 Introduction This device's debug is based on the ARM coresight architecture and is configured in each device to provide the maximum flexibility as allowed by the restrictions of the pinout and other available resources. Four debug interfaces are supported: * * * * IEEE 1149.1 JTAG IEEE 1149.7 JTAG (cJTAG) Serial Wire Debug (SWD) ARM Real-Time Trace Interface(1-pin asynchronous mode only) The basic Cortex-M4 debug architecture is very flexible. The following diagram shows the topology of the core debug architecture and its components. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 189 Introduction INTNMI INTISR[239:0] SLEEPING Cortex-M4 Interrupts Sleep NVIC Core Debug SLEEPDEEP Instr. Data TPIU AWIC Trace port (serial wire or multi-pin) MCM FPB DWT ITM Private Peripheral Bus (internal) ROM Table APB i/f I-code bus Bus Matrix SW/ JTAG SWJ-DP Code bus D-code bus System bus AHB-AP MDM-AP Figure 9-1. Cortex-M4 Debug Topology The following table presents a brief description of each one of the debug components. Table 9-1. Debug Components Description Module Description SWJ-DP+ cJTAG Modified Debug Port with support for SWD, JTAG, cJTAG AHB-AP AHB Master Interface from JTAG to debug module and SOC system memory maps MDM-AP Provides centralized control and status registers for an external debugger to control the device. ROM Table Identifies which debug IP is available. Core Debug Singlestep, Register Access, Run, Core Status ITM S/W Instrumentation Messaging + Simple Data Trace Messaging + Watchpoint Messaging DWT (Data and Address Watchpoints) 4 data and address watchpoints FPB (Flash Patch and Breakpoints) The FPB implements hardware breakpoints and patches code and data from code space to system space. The FPB unit contains two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 190 NXP Semiconductors Chapter 9 Debug Table 9-1. Debug Components Description (continued) Module Description The FPB also contains six instruction comparators for matching against instruction fetches from Code space, and remapping to a corresponding area in System space. Alternatively, the six instruction comparators can individually configure the comparators to return a Breakpoint Instruction (BKPT) to the processor core on a match, so providing hardware breakpoint capability. TPIU (Trace Port Inteface Unit) Asynchronous Mode (1-pin) = TRACE_SWO (available on JTAG_TDO) 9.1.1 References For more information on ARM debug components, see these documents: * ARMv7-M Architecture Reference Manual * ARM Debug Interface v5.1 * ARM CoreSight Architecture Specification 9.2 The Debug Port The configuration of the cJTAG module, JTAG controller, and debug port is illustrated in the following figure: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 191 The Debug Port IR==BYPASSor IDCODE 4'b1111 or 4'b0000 jtag_updateinstr[3:0] A TDI nTRST TCK TMS TDO TRACESWO TDO TDI TDO TDI (1'b1 = 4-pin JTAG) (1'b0 = 2-pin cJTAG) To Test Resources CJTAG TDI TDO PEN TDO TDI nSYS_TDO nSYS_TDI nTRST 1'b1 SWCLKTCK TCK JTAGC nSYS_TRST TCK TMS_OUT TMS_OUT_OE SWDITMS nSYS_TCK nSYS_TMS AHB-AP JTAGir[3:0] TMS_IN IR==BYPASSor IDCODE JTAGNSW A DAP Bus 4'b1111 or 4'b1110 MDM-AP TMS SWDO SWDOEN SWDSEL JTAGSEL SWDITMS SWCLKTCK SWD/ JTAG SELECT Figure 9-2. Modified Debug Port The debug port comes out of reset in standard JTAG mode and is switched into either cJTAG or SWD mode by the following sequences. Once the mode has been changed, unused debug pins can be reassigned to any of their alternative muxed functions. 9.2.1 JTAG-to-SWD change sequence 1. Send more than 50 TCK cycles with TMS (SWDIO) =1 2. Send the 16-bit sequence on TMS (SWDIO) = 0111_1001_1110_0111 (MSB transmitted first) 3. Send more than 50 TCK cycles with TMS (SWDIO) =1 NOTE See the ARM documentation for the CoreSight DAP Lite for restrictions. 9.2.2 JTAG-to-cJTAG change sequence 1. Reset the debug port K22F Sub-Family Reference Manual, Rev. 4, 08/2016 192 NXP Semiconductors Chapter 9 Debug 2. Set the control level to 2 via zero-bit scans 3. Execute the Store Format (STFMT) command (00011) to set the scan format register to 1149.7 scan format 9.3 Debug Port Pin Descriptions The debug port pins default after POR to their JTAG functionality with the exception of JTAG_TRST_b and can be later reassigned to their alternate functionalities. In cJTAG and SWD modes JTAG_TDI and JTAG_TRST_b can be configured to alternate GPIO functions. Table 9-2. Debug port pins Pin Name JTAG Debug Port Type cJTAG Debug Port Description Type SWD Debug Port Description Type Internal Pullup\Down Description JTAG_TMS/ SWD_DIO I JTAG Test Mode Selection I cJTAG Data I/O Serial Wire Data Pull-up JTAG_TCLK/ SWD_CLK I JTAG Test Clock I cJTAG Clock I Serial Wire Clock Pull-down JTAG_TDI I JTAG Test Data Input - JTAG_TDO/ O TRACE_SWO JTAG Test Data Output O JTAG_TRST_ I b JTAG Reset I - - Trace output over a single pin cJTAG Reset O - - Pull-up Trace output over a single pin N/C - Pull-up 9.4 System TAP connection The system JTAG controller is connected in parallel to the ARM TAP controller. The system JTAG controller IR codes overlay the ARM JTAG controller IR codes without conflict. Refer to the IR codes table for a list of the available IR codes. The output of the TAPs (TDO) are muxed based on the IR code which is selected. This design is fully JTAG compliant and appears to the JTAG chain as a single TAP. At power on reset, ARM's IDCODE (IR=4'b1110) is selected. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 193 JTAG status and control registers 9.4.1 IR Codes Table 9-3. JTAG Instructions Instruction Code[3:0] Instruction Summary IDCODE 0000 Selects device identification register for shift SAMPLE/PRELOAD 0010 Selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation SAMPLE 0011 Selects boundary scan register for shifting and sampling without disturbing functional operation EXTEST 0100 Selects boundary scan register while applying preloaded values to output pins and asserting functional reset HIGHZ 1001 Selects bypass register while three-stating all output pins and asserting functional reset CLAMP 1100 Selects bypass register while applying preloaded values to output pins and asserting functional reset EZPORT 1101 Enables the EZPORT function for the SoC and asserts functional reset. ARM_IDCODE 1110 ARM JTAG-DP Instruction BYPASS 1111 Selects bypass register for data operations Factory debug reserved ARM JTAG-DP Reserved Reserved 3 0101, 0110, 0111 Intended for factory debug only 1000, 1010, 1011, 1110 These instructions will go the ARM JTAG-DP controller. Please look at ARM JTAG-DP documentation for more information on these instructions. All other opcodes Decoded to select bypass register 3. The manufacturer reserves the right to change the decoding of reserved instruction codes in the future 9.5 JTAG status and control registers Through the ARM Debug Access Port (DAP), the debugger has access to the status and control elements, implemented as registers on the DAP bus as shown in the following figure. These registers provide additional control and status for low power mode recovery and typical run-control scenarios. The status register bits also provide a means for the debugger to get updated status of the core without having to initiate a bus transaction across the crossbar switch, thus remaining less intrusive during a debug session. It is important to note that these DAP control and status registers are not memory mapped within the system memory map and are only accessible via the Debug Access Port (DAP) using JTAG, cJTAG, or SWD. The MDM-AP is accessible as Debug Access Port 1 with the available registers shown in the table below. Table 9-4. MDM-AP Register Summary Address Register Description Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 194 NXP Semiconductors Chapter 9 Debug Table 9-4. MDM-AP Register Summary (continued) 0x0100_0000 Status See MDM-AP Status Register 0x0100_0004 Control See MDM-AP Control Register 0x0100_00FC ID Read-only identification register that always reads as 0x001C_0000 DPACC APACC A[3:2] RnW 0x0C 0x08 0x04 Data[31:0] Debug Port Read Buffer (REBUFF) AP Select (SELECT) Debug Port ID Register (DPIDR) A[3:2] RnW Control/Status (CTRL/STAT) DP Registers 0x00 Data[31:0] APSEL Decode SWJ-DP See the ARM Debug Interface v5p1 Supplement. Generic Debug Port (DP) Data[31:0] A[7:4] A[3:2] RnW SELECT[31:24] (APSEL) selects the AP Internal SELECT[7:4] (APBANKSEL) selects the bank Bus MDM-AP 0x01 0x3F IDR (AHB-AP) Control AHB Access Port Status 0x00 A[3:2] from the APACC selects the register within the bank AHB-AP SELECT[31:24] = 0x00 selects the AHB-AP See ARM documentation for further details AccessMDM-AP Port SELECT[31:24] = 0x01 selects the MDM-AP SELECT[7:4] = 0x0 selects the bank with Status and Ctrl A[3:2] = 2'b00 selects the Status Register A[3:2] = 2'b01 selects the Control Register Bus Matrix See Control and Status Register Descriptions SELECT[7:4] = 0xF selects the bank with IDR A[3:2] = 2'b11 selects the IDR Register (IDR register reads 0x001C_0000) Figure 9-3. MDM AP Addressing K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 195 JTAG status and control registers 9.5.1 MDM-AP Control Register Table 9-5. MDM-AP Control register assignments Bit 0 Secure1 Name Flash Mass Erase in Progress Y Description Set to cause mass erase. Cleared by hardware after mass erase operation completes. When mass erase is disabled (via MEEN settings), the erase request does not occur and the Flash Mass Erase in Progress bit continues to assert until the next system reset. 1 Debug Disable N Set to disable debug. Clear to allow debug operation. When set it overrides the C_DEBUGEN bit within the DHCSR and force disables Debug logic. 2 Debug Request N Set to force the Core to halt. If the Core is in a stop or wait mode, this bit can be used to wakeup the core and transition to a halted state. 3 System Reset Request N Set to force a system reset. The system remains held in reset until this bit is cleared. 4 Core Hold Reset N Configuration bit to control Core operation at the end of system reset sequencing. 0 Normal operation - release the Core from reset along with the rest of the system at the end of system reset sequencing. 1 Suspend operation - hold the Core in reset at the end of reset sequencing. Once the system enters this suspended state, clearing this control bit immediately releases the Core from reset and CPU operation begins. 5 VLLSx Debug Request (VLLDBGREQ) N Set to configure the system to be held in reset after the next recovery from a VLLSx mode. This bit holds the in reset when VLLSx modes are exited to allow the debugger time to re-initialize debug IP before the debug session continues. The Mode Controller captures this bit logic on entry to VLLSx modes. Upon exit from VLLSx modes, the Mode Controller will hold the in reset until VLLDBGACK is asserted. The VLLDBGREQ bit clears automatically due to the POR reset generated as part of the VLLSx recovery. 6 VLLSx Debug Acknowledge (VLLDBGACK) N Set to release a being held in reset following a VLLSx recovery This bit is used by the debugger to release the system reset when it is being held on VLLSx mode exit. The debugger re-initializes all debug IP and then assert this control bit to allow the Mode Controller to release the from reset and allow CPU operation to begin. The VLLDBGACK bit is cleared by the debugger or can be left set because it clears automatically due to the POR reset generated as part of the next VLLSx recovery. 7 LLS, VLLSx Status Acknowledge N Set this bit to acknowledge the DAP LLS and VLLS Status bits have been read. This acknowledge automatically clears the status bits. This bit is used by the debugger to clear the sticky LLS and VLLSx mode entry status bits. This bit is asserted and cleared by the debugger. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 196 NXP Semiconductors Chapter 9 Debug Table 9-5. MDM-AP Control register assignments (continued) Bit 8 Secure1 Name Timestamp Disable N Description Set this bit to disable the 48-bit global trace timestamp counter during debug halt mode when the core is halted. 0 The timestamp counter continues to count assuming trace is enabled. (default) 1 The timestamp counter freezes when the core has halted (debug halt mode). 9- 31 Reserved for future use N 1. Command available in secure mode 9.5.2 MDM-AP Status Register Table 9-6. MDM-AP Status register assignments Bit 0 Name Flash Mass Erase Acknowledge Description The Flash Mass Erase Acknowledge bit is cleared after POR or any debug reset. The bit is also cleared at launch of a mass erase command due to write of Flash Mass Erase in Progress bit in MDM AP Control Register. The Flash Mass Erase Acknowledge is set after Flash control logic has started the mass erase operation. When mass erase is disabled (via MEEN settings), an erase request due to seting of Flash Mass Erase in Progress bit is not acknowledged. 1 Flash Ready Indicate Flash has been initialized and debugger can be configured even if system is continuing to be held in reset via the debugger. 2 System Security Indicates the security state. When secure, the debugger does not have access to the system bus or any memory mapped peripherals. This bit indicates when the part is locked and no system bus access is possible. 3 System Reset Indicates the system reset state. 0 System is in reset 1 System is not in reset 4 Reserved 5 Mass Erase Enable Indicates if the MCU can be mass erased or not 0 Mass erase is disabled 1 Mass erase is enabled 6 Backdoor Access Key Enable Indicates if the MCU has the backdoor access key enabled. 0 Disabled 1 Enabled 7 LP Enabled Decode of LPLLSM control bits to indicate that VLPS, LLS, or VLLSx are the selected power mode the next time the ARM Core enters Deep Sleep. 0 Low Power Stop Mode is not enabled 1 Low Power Stop Mode is enabled Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 197 Debug Resets Table 9-6. MDM-AP Status register assignments (continued) Bit Name Description Usage intended for debug operation in which Run to VLPS is attempted. Per debug definition, the system actually enters the Stop state. A debugger should interpret deep sleep indication (with SLEEPDEEP and SLEEPING asserted), in conjuntion with this bit asserted as the debuggerVLPS status indication. 8 Very Low Power Mode Indicates current power mode is VLPx. This bit is not `sticky' and should always represent whether VLPx is enabled or not. This bit is used to throttle JTAG TCK frequency up/down. 9 LLS Mode Exit This bit indicates an exit from LLS mode has occurred. The debugger will lose communication while the system is in LLS (including access to this register). Once communication is reestablished, this bit indicates that the system had been in LLS. Since the debug modules held their state during LLS, they do not need to be reconfigured. This bit is set during the LLS recovery sequence. The LLS Mode Exit bit is held until the debugger has had a chance to recognize that LLS was exited and is cleared by a write of 1 to the LLS, VLLSx Status Acknowledge bit in MDM AP Control register. 10 VLLSx Modes Exit This bit indicates an exit from VLLSx mode has occurred. The debugger will lose communication while the system is in VLLSx (including access to this register). Once communication is reestablished, this bit indicates that the system had been in VLLSx. Since the debug modules lose their state during VLLSx modes, they need to be reconfigured. This bit is set during the VLLSx recovery sequence. The VLLSx Mode Exit bit is held until the debugger has had a chance to recognize that a VLLS mode was exited and is cleared by a write of 1 to the LLS, VLLSx Status Acknowledge bit in MDM AP Control register. 11 - 15 Reserved for future use Always read 0. 16 Core Halted Indicates the Core has entered debug halt mode 17 Core SLEEPDEEP Indicates the Core has entered a low power mode 18 Core SLEEPING SLEEPING==1 and SLEEPDEEP==0 indicates wait or VLPW mode. SLEEPING==1 and SLEEPDEEP==1 indicates stop or VLPS mode. 19 - 31 Reserved for future use Always read 0. 9.6 Debug Resets The debug system receives the following sources of reset: * JTAG_TRST_b from an external signal. This signal is optional and may not be available in all packages. * Debug reset (CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register) in the TCLK domain that allows the debugger to reset the debug logic. * TRST asserted via the cJTAG escape command. * System POR reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 198 NXP Semiconductors Chapter 9 Debug Conversely the debug system is capable of generating system reset using the following mechanism: * A system reset in the DAP control register which allows the debugger to hold the system in reset. * SYSRESETREQ bit in the NVIC application interrupt and reset control register * A system reset in the DAP control register which allows the debugger to hold the Core in reset. 9.7 AHB-AP AHB-AP provides the debugger access to all memory and registers in the system, including processor registers through the NVIC. System access is independent of the processor status. AHB-AP does not do back-to-back transactions on the bus, so all transactions are non-sequential. AHB-AP can perform unaligned and bit-band transactions. AHB-AP transactions bypass the FPB, so the FPB cannot remap AHB-AP transactions. SWJ/SW-DP-initiated transaction aborts drive an AHB-AP-supported sideband signal called HABORT. This signal is driven into the Bus Matrix, which resets the Bus Matrix state, so that AHB-AP can access the Private Peripheral Bus for last ditch debugging such as read/stop/reset the core. AHB-AP transactions are little endian. For a short period at the start of a system reset event the system security status is being determined and debugger access to all AHB-AP transactions is blocked. The MDM-AP Status register is accessible and can be monitored to determine when this initial period is completed. After this initial period, if system reset is held via assertion of the RESET pin, the debugger has access via the bus matrix to the private peripheral bus to configure the debug IP even while system reset is asserted. While in system reset, access to other memory and register resources, accessed over the Crossbar Switch, is blocked. 9.8 ITM The ITM is an application-driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets. There are four sources that can generate packets. If multiple sources generate packets at the same time, the ITM arbitrates the order in which packets are output. The four sources in decreasing order of priority are: 1. Software trace -- Software can write directly to ITM stimulus registers. This emits packets. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 199 Core Trace Connectivity 2. Hardware trace -- The DWT generates these packets, and the ITM emits them. 3. Time stamping -- Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate the timestamp. The Cortex-M4 clock or the bitclock rate of the Serial Wire Viewer (SWV) output clocks the counter. 4. Global system timestamping. Timestamps can optionally be generated using a system-wide 48-bit count value. 9.9 Core Trace Connectivity The ITM can route its data to the TPIU. (See the MCM (Miscellaneous Control Module) for controlling the routing to the TPIU.) This configuration enables the use of trace with low cost tools while maintaining the compatibility with trace probes. 9.10 TPIU The TPIU acts as a bridge between the on-chip trace data from the Instrumentation Trace Macrocell (ITM) to a data stream, encapsulating IDs where required, that is then captured by a Trace Port Analyzer (TPA). The TPIU is specially designed for low-cost debug. 9.11 DWT The DWT is a unit that performs the following debug functionality: * It contains four comparators that you can configure as a hardware watchpoint, a PC sampler event trigger, or a data address sampler event trigger. The first comparator, DWT_COMP0, can also compare against the clock cycle counter, CYCCNT. The second comparator, DWT_COMP1, can also be used as a data comparator. * The DWT contains counters for: * Clock cycles (CYCCNT) * Folded instructions * Load store unit (LSU) operations * Sleep cycles * CPI (all instruction cycles except for the first cycle) * Interrupt overhead K22F Sub-Family Reference Manual, Rev. 4, 08/2016 200 NXP Semiconductors Chapter 9 Debug NOTE An event is emitted each time a counter overflows. * The DWT can be configured to emit PC samples at defined intervals, and to emit interrupt event information. 9.12 Debug in Low Power Modes In low power modes in which the debug modules are kept static or powered off, the debugger cannot gather any debug data for the duration of the low power mode. In the case that the debugger is held static, the debug port returns to full functionality as soon as the low power mode exits and the system returns to a state with active debug. In the case that the debugger logic is powered off, the debugger is reset on recovery and must be reconfigured once the low power mode is exited. Power mode entry logic monitors Debug Power Up and System Power Up signals from the debug port as indications that a debugger is active. These signals can be changed in RUN, VLPR, WAIT and VLPW. If the debug signal is active and the system attempts to enter stop or VLPS, FCLK continues to run to support core register access. In these modes in which FCLK is left active the debug modules have access to core registers but not to system memory resources accessed via the crossbar. With debug enabled, transitions from Run directly to VLPS are not allowed and result in the system entering Stop mode instead. Status bits within the MDM-AP Status register can be evaluated to determine this pseudo-VLPS state. Note with the debug enabled, transitions from Run--> VLPR --> VLPS are still possible but also result in the system entering Stop mode instead. In VLLS mode all debug modules are powered off and reset at wakeup. In LLS mode, the debug modules retain their state but no debug activity is possible. NOTE When using cJTAG and entering LLS mode, the cJTAG controller must be reset on exit from LLS mode. Going into a VLLSx mode causes all the debug controls and settings to be reset. To give time to the debugger to sync up with the HW, the MDM-AP Control register can be configured hold the system in reset on recovery so that the debugger can regain control and reconfigure debug logic prior to the system exiting reset and resuming operation. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 201 Debug & Security 9.12.1 Debug Module State in Low Power Modes The following table shows the state of the debug modules in low power modes. These terms are used: * FF = Full functionality. In VLPR and VLPW the system frequency is limited, but if a module does not have a limitation in its functionality, it is still listed as FF. * static = Module register states and associated memories are retained. * OFF = Modules are powered off; module is in reset state upon wakeup. Table 9-7. Debug Module State in Low Power Modes Module STOP VLPR VLPW VLPS LLS VLLSx Debug Port FF FF FF OFF static OFF AHB-AP FF FF FF OFF static OFF ITM FF FF FF OFF static OFF TPIU FF FF FF OFF static OFF DWT FF FF FF OFF static OFF 9.13 Debug & Security When security is enabled (FSEC[SEC] != 10), the debug port capabilities are limited in order to prevent exploitation of secure data. In the secure state the debugger still has access to the MDM-AP Status Register and can determine the current security state of the device. In the case of a secure device, the debugger also has the capability of performing a mass erase operation via writes to the MDM-AP Control Register if mass erase is enabled. In the case of a secure device that has mass erase disabled (FSEC[MEEN] = 10), attempts to mass erase via the debug interface are blocked. When mass erase is disabled (FSEC[MEEN]= 10), the debugger does not have the capability of performing a mass erase operation via writes to MDM-AP Control Register. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 202 NXP Semiconductors Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction To optimize functionality in small packages, pins have several functions available via signal multiplexing. This chapter illustrates which of this device's signals are multiplexed on which external pin. The Port Control block controls which signal is present on the external pin. Reference that chapter to find which register controls the operation of a specific pin. 10.2 Signal Multiplexing Integration This section summarizes how the module is integrated into the device. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge 0 Register access Module External Pins Transfers Signal Multiplexing/ Port Control Module Transfers Module Figure 10-1. Signal multiplexing integration Table 10-1. Reference links to related information Topic Related module Reference Full description Port control Port control System memory map System memory map Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 203 Signal Multiplexing Integration Table 10-1. Reference links to related information (continued) Topic Related module Reference Clocking Clock Distribution Register access Peripheral bus controller Peripheral bridge 10.2.1 Port control and interrupt module features * 32-pin ports NOTE Not all pins are available on the device. See the following section for details. * Each 32-pin port is assigned one interrupt. Table 10-2. Ports summary Feature Port A Port B Port C Port D Port E Yes Yes Yes Yes Pull select at reset PTA1/PTA2/PTA3/ Pull down PTA4/PTA5=Pull up, Others=Pull down Pull down Pull down Pull down Pull enable control Yes Yes Yes Yes Disabled Disabled Disabled Yes Yes Yes Yes Disabled Disabled Disabled Disabled Pull select control Yes Yes Pull enable at reset PTA0/PTA1/PTA2/ Disabled PTA3/ PTA4=Enabled; Others=Disabled Slew rate enable control Yes Slew rate enable at Disabled reset Passive filter enable control PTA4=Yes; Others=No No No No No Passive filter enable at reset Disabled Disabled Disabled Disabled Disabled Open drain enable Yes control Yes Yes Yes Yes Open drain enable Disabled at reset Disabled Disabled Disabled Disabled Drive strength enable control No PTB0/PTB1 only PTC3/PTC4 only PTD4/PTD5/PTD6/ No PTD7 only Drive strength enable at reset Disabled Disabled Disabled Disabled Disabled Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 204 NXP Semiconductors Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-2. Ports summary (continued) Feature Port A Port B Port C Port D Port E Pin mux control Yes Yes Yes Yes Yes Pin mux at reset PTA0/PTA1/PTA2/ ALT0 PTA3/PTA4=ALT7; Others=ALT0 ALT0 ALT0 ALT0 Yes Yes Yes Yes Yes Interrupt and DMA Yes request Yes Yes Yes Yes No No Yes No Lock bit Digital glitch filter No 10.2.2 Clock gating The clock to the port control module can be gated on and off using the SCGC5[PORTx] bits in the SIM module. These bits are cleared after any reset, which disables the clock to the corresponding module to conserve power. Prior to initializing the corresponding module, set SCGC5[PORTx] in the SIM module to enable the clock. Before turning off the clock, make sure to disable the module. For more details, refer to the clock distribution chapter. 10.2.3 Signal multiplexing constraints 1. A given peripheral function must be assigned to a maximum of one package pin. Do not program the same function to more than one pin. 2. To ensure the best signal timing for a given peripheral's interface, choose the pins in closest proximity to each other. 10.3 Pinout 10.3.1 K22 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 205 Pinout 121 100 64 64 49 BGA LQFP LQFP MAP WLC BGA SP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 E4 1 1 A1 B6 PTE0/ ADC1_ CLKOUT32 SE4a K ADC1_ SE4a PTE0/ SPI1_ CLKOUT32 PCS1 K UART1_TX I2C1_SDA RTC_ CLKOUT E3 2 2 B1 D5 PTE1/ LLWU_P0 ADC1_ SE5a ADC1_ SE5a PTE1/ LLWU_P0 SPI1_ SOUT UART1_RX I2C1_SCL SPI1_SIN E2 3 -- -- E5 PTE2/ LLWU_P1 ADC1_ SE6a ADC1_ SE6a PTE2/ LLWU_P1 SPI1_SCK UART1_ CTS_b F4 4 -- -- A7 PTE3 ADC1_ SE7a ADC1_ SE7a PTE3 SPI1_SIN UART1_ RTS_b H7 5 -- -- E4 PTE4/ LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_ PCS0 LPUART0_ TX G4 6 -- -- D4 PTE5 DISABLED PTE5 SPI1_ PCS2 LPUART0_ RX F3 7 -- -- -- PTE6 DISABLED PTE6 SPI1_ PCS3 LPUART0_ I2S0_ CTS_b MCLK E6 8 3 C5 B7 VDD VDD VDD G7 9 4 C4 C6 VSS VSS VSS L6 -- -- -- C6 VSS VSS VSS F1 10 5 E1 C7 USB0_DP USB0_DP USB0_DP F2 11 6 D1 D7 USB0_DM USB0_DM USB0_DM G1 12 7 E2 D6 USBVDD USBVDD USBVDD G2 13 8 D2 -- NC NC NC H1 14 -- -- -- ADC0_DP1 ADC0_DP1 ADC0_DP1 H2 15 -- -- -- ADC0_ DM1 J1 16 -- -- -- ADC1_ ADC1_ ADC1_ DP1/ DP1/ DP1/ ADC0_DP2 ADC0_DP2 ADC0_DP2 J2 17 -- -- -- ADC1_ DM1/ ADC0_ DM2 K1 18 9 G1 -- ADC0_ ADC0_ ADC0_ DP0/ DP0/ DP0/ ADC1_DP3 ADC1_DP3 ADC1_DP3 K2 19 10 F1 -- ADC0_ DM0/ ADC1_ DM3 L1 20 11 G2 -- ADC1_ ADC1_ ADC1_ DP0/ DP0/ DP0/ ADC0_DP3 ADC0_DP3 ADC0_DP3 L2 21 12 F2 -- ADC1_ DM0/ ADC0_ DM3 ADC1_ DM0/ ADC0_ DM3 ADC1_ DM0/ ADC0_ DM3 F5 22 13 F4 F7 VDDA VDDA VDDA ADC0_ DM1 ADC1_ DM1/ ADC0_ DM2 ADC0_ DM0/ ADC1_ DM3 EzPort SPI1_ SOUT USB_SOF_ OUT ADC0_ DM1 ADC1_ DM1/ ADC0_ DM2 ADC0_ DM0/ ADC1_ DM3 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 206 NXP Semiconductors Chapter 10 Signal Multiplexing and Signal Descriptions 121 100 64 64 49 BGA LQFP LQFP MAP WLC BGA SP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 G5 23 14 G4 F7 VREFH VREFH VREFH G6 24 15 G3 G7 VREFL VREFL VREFL F6 25 16 F3 G7 VSSA VSSA VSSA L3 26 17 H1 G6 VREF_ OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_ SE18 VREF_ OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_ SE18 VREF_ OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_ SE18 K5 27 18 H2 -- DAC0_ OUT/ CMP1_IN3/ ADC0_ SE23 DAC0_ OUT/ CMP1_IN3/ ADC0_ SE23 DAC0_ OUT/ CMP1_IN3/ ADC0_ SE23 K4 -- -- -- -- CMP0_IN4/ CMP0_IN4/ CMP0_IN4/ ADC1_ ADC1_ ADC1_ SE23 SE23 SE23 L4 28 19 H3 F5 XTAL32 XTAL32 XTAL32 L5 29 20 H4 G5 EXTAL32 EXTAL32 EXTAL32 K6 30 21 H5 G4 VBAT VBAT VBAT H5 31 -- -- -- PTE24 ADC0_ SE17 ADC0_ SE17 PTE24 I2C0_SCL EWM_ OUT_b J5 32 -- -- -- PTE25 ADC0_ SE18 ADC0_ SE18 PTE25 I2C0_SDA EWM_IN H6 33 -- -- -- PTE26/ DISABLED CLKOUT32 K PTE26/ CLKOUT32 K J6 34 22 D3 F4 PTA0 JTAG_ TCLK/ SWD_CLK/ EZP_CLK PTA0 UART0_ CTS_b H8 35 23 D4 F6 PTA1 JTAG_TDI/ EZP_DI PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI J7 36 24 E5 E7 PTA2 JTAG_ TDO/ TRACE_ SWO/ EZP_DO PTA2 UART0_TX FTM0_CH7 JTAG_ TDO/ TRACE_ SWO EZP_DO H9 37 25 D5 E6 PTA3 JTAG_ TMS/ SWD_DIO PTA3 UART0_ RTS_b FTM0_CH0 JTAG_ TMS/ SWD_DIO J8 38 26 G5 F3 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b PTA4/ LLWU_P3 FTM0_CH1 NMI_b K7 39 27 F5 -- PTA5 DISABLED PTA5 E5 40 -- -- -- VDD VDD VDD G3 41 -- -- -- VSS VSS VSS RTC_ CLKOUT USB_ CLKIN FTM0_CH5 FTM0_CH2 ALT7 EzPort USB_ CLKIN JTAG_ EZP_CLK TCLK/ SWD_CLK I2S0_TX_ BCLK EZP_CS_b JTAG_ TRST_b K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 207 Pinout 121 100 64 64 49 BGA LQFP LQFP MAP WLC BGA SP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 K8 42 28 H6 -- PTA12 DISABLED PTA12 FTM1_CH0 I2S0_TXD0 FTM1_QD_ PHA L8 43 29 G6 -- PTA13/ LLWU_P4 DISABLED PTA13/ LLWU_P4 FTM1_CH1 I2S0_TX_ FS K9 44 -- -- -- PTA14 DISABLED PTA14 SPI0_ PCS0 UART0_TX I2S0_RX_ BCLK L9 45 -- -- -- PTA15 DISABLED PTA15 SPI0_SCK UART0_RX I2S0_ RXD0 J10 46 -- -- -- PTA16 DISABLED PTA16 SPI0_ SOUT UART0_ CTS_b I2S0_RX_ FS H10 47 -- -- -- PTA17 ADC1_ SE17 ADC1_ SE17 PTA17 SPI0_SIN UART0_ RTS_b I2S0_ MCLK L10 48 30 G7 G3 VDD VDD VDD K10 49 31 H7 F2 VSS VSS VSS L11 50 32 H8 G2 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_ FLT2 FTM_ CLKIN0 K11 51 33 G8 G1 PTA19 XTAL0 XTAL0 PTA19 FTM1_ FLT0 FTM_ CLKIN1 J11 52 34 F8 F1 RESET_b RESET_b RESET_b G11 53 35 F7 E3 PTB0/ LLWU_P5 ADC0_ ADC0_ PTB0/ SE8/ SE8/ LLWU_P5 ADC1_SE8 ADC1_SE8 I2C0_SCL FTM1_CH0 FTM1_QD_ PHA G10 54 36 F6 E2 PTB1 ADC0_ ADC0_ PTB1 SE9/ SE9/ ADC1_SE9 ADC1_SE9 I2C0_SDA FTM1_CH1 FTM1_QD_ PHB G9 55 37 E7 D2 PTB2 ADC0_ SE12 ADC0_ SE12 PTB2 I2C0_SCL UART0_ RTS_b FTM0_ FLT3 G8 56 38 E8 E1 PTB3 ADC0_ SE13 ADC0_ SE13 PTB3 I2C0_SDA UART0_ CTS_b FTM0_ FLT0 D11 -- -- -- -- PTB8 DISABLED PTB8 E10 57 -- -- -- PTB9 DISABLED PTB9 SPI1_ PCS1 LPUART0_ CTS_b D10 58 -- -- -- PTB10 ADC1_ SE14 ADC1_ SE14 PTB10 SPI1_ PCS0 LPUART0_ RX FTM0_ FLT1 C10 59 -- -- -- PTB11 ADC1_ SE15 ADC1_ SE15 PTB11 SPI1_SCK LPUART0_ TX FTM0_ FLT2 -- 60 -- -- -- VSS VSS VSS -- 61 -- -- -- VDD VDD VDD B10 62 39 E6 D1 PTB16 DISABLED PTB16 SPI1_ SOUT UART0_RX FTM_ CLKIN0 EWM_IN E9 63 40 D7 C2 PTB17 DISABLED PTB17 SPI1_SIN UART0_TX FTM_ CLKIN1 EWM_ OUT_b D9 64 41 D6 -- PTB18 DISABLED PTB18 FTM2_CH0 I2S0_TX_ BCLK FTM2_QD_ PHA C9 65 42 C7 -- PTB19 DISABLED PTB19 FTM2_CH1 I2S0_TX_ FS FTM2_QD_ PHB EzPort FTM1_QD_ PHB LPTMR0_ ALT1 LPUART0_ RTS_b K22F Sub-Family Reference Manual, Rev. 4, 08/2016 208 NXP Semiconductors Chapter 10 Signal Multiplexing and Signal Descriptions 121 100 64 64 49 BGA LQFP LQFP MAP WLC BGA SP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 F10 66 -- -- -- PTB20 DISABLED PTB20 CMP0_ OUT F9 67 -- -- -- PTB21 DISABLED PTB21 CMP1_ OUT F8 68 -- -- -- PTB22 DISABLED PTB22 E8 69 -- -- -- PTB23 DISABLED PTB23 B9 70 43 D8 C1 PTC0 ADC0_ SE14 ADC0_ SE14 PTC0 SPI0_ PCS4 PDB0_ EXTRG USB_SOF_ OUT D8 71 44 C6 B1 PTC1/ LLWU_P6 ADC0_ SE15 ADC0_ SE15 PTC1/ LLWU_P6 SPI0_ PCS3 UART1_ RTS_b FTM0_CH0 I2S0_TXD0 LPUART0_ RTS_b C8 72 45 B7 B2 PTC2 ADC0_ ADC0_ PTC2 SE4b/ SE4b/ CMP1_IN0 CMP1_IN0 SPI0_ PCS2 UART1_ CTS_b FTM0_CH1 I2S0_TX_ FS LPUART0_ CTS_b B8 73 46 C8 A1 PTC3/ LLWU_P7 CMP1_IN1 CMP1_IN1 PTC3/ LLWU_P7 SPI0_ PCS1 UART1_RX FTM0_CH2 CLKOUT I2S0_TX_ BCLK LPUART0_ RX -- 74 47 E3 C6 VSS VSS VSS -- 75 48 E4 B7 VDD VDD VDD A8 76 49 B8 A2 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_ PCS0 UART1_TX FTM0_CH3 CMP1_ OUT LPUART0_ TX D7 77 50 A8 D3 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 I2S0_ RXD0 CMP0_ OUT FTM0_CH2 C7 78 51 A7 C3 PTC6/ CMP0_IN0 CMP0_IN0 PTC6/ SPI0_ LLWU_P10 LLWU_P10 SOUT PDB0_ EXTRG I2S0_RX_ BCLK I2S0_ MCLK B7 79 52 B6 B3 PTC7 CMP0_IN1 CMP0_IN1 PTC7 USB_SOF_ I2S0_RX_ OUT FS A7 80 53 A6 -- PTC8 ADC1_ ADC1_ PTC8 SE4b/ SE4b/ CMP0_IN2 CMP0_IN2 I2S0_ MCLK D6 81 54 B5 -- PTC9 ADC1_ ADC1_ PTC9 SE5b/ SE5b/ CMP0_IN3 CMP0_IN3 I2S0_RX_ BCLK C6 82 55 B4 -- PTC10 ADC1_ SE6b ADC1_ SE6b PTC10 C5 83 56 A5 -- PTC11/ ADC1_ LLWU_P11 SE7b ADC1_ SE7b PTC11/ I2C1_SDA LLWU_P11 B6 84 -- -- -- PTC12 DISABLED PTC12 A6 85 -- -- -- PTC13 DISABLED PTC13 A5 86 -- -- -- PTC14 DISABLED PTC14 B5 87 -- -- -- PTC15 DISABLED PTC15 F7 88 -- -- -- VSS VSS VSS VDD EzPort SPI0_ PCS5 SPI0_SIN I2C1_SCL FTM2_ FLT0 I2S0_RX_ FS E7 89 -- -- -- VDD VDD D5 90 -- -- -- PTC16 DISABLED PTC16 LPUART0_ RX C4 91 -- -- -- PTC17 DISABLED PTC17 LPUART0_ TX K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 209 Pinout 121 100 64 64 49 BGA LQFP LQFP MAP WLC BGA SP Pin Name Default ALT0 B4 92 -- -- -- PTC18 DISABLED D4 93 57 C3 A3 PTD0/ DISABLED LLWU_P12 D3 94 58 A4 A4 PTD1 C3 95 59 C2 B4 PTD2/ DISABLED LLWU_P13 B3 96 60 B3 C4 PTD3 A3 97 61 A3 A5 PTD4/ DISABLED LLWU_P14 A2 98 62 C1 B5 PTD5 ADC0_ SE6b B2 99 63 B2 C5 PTD6/ ADC0_ LLWU_P15 SE7b A1 100 64 A2 A6 PTD7 DISABLED A11 -- -- -- -- NC NC NC K3 -- -- -- -- NC NC NC H4 -- -- -- -- NC NC NC B11 -- -- -- -- NC NC NC C11 -- -- -- -- NC NC NC H11 -- -- -- -- NC NC NC C1 -- -- -- -- NC NC NC D2 -- -- -- -- NC NC NC D1 -- -- -- -- NC NC NC E1 -- -- -- -- NC NC NC J3 -- -- -- -- NC NC NC H3 -- -- -- -- NC NC NC J9 -- -- -- -- NC NC NC J4 -- -- -- -- NC NC NC A10 -- -- -- -- NC NC NC A9 -- -- -- -- NC NC NC ADC0_ SE5b ADC0_ SE5b DISABLED ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 PTC18 LPUART0_ RTS_b PTD0/ SPI0_ LLWU_P12 PCS0 UART2_ RTS_b LPUART0_ RTS_b PTD1 UART2_ CTS_b LPUART0_ CTS_b PTD2/ SPI0_ LLWU_P13 SOUT UART2_RX LPUART0_ I2C0_SCL RX PTD3 UART2_TX LPUART0_ I2C0_SDA TX SPI0_SCK SPI0_SIN PTD4/ SPI0_ LLWU_P14 PCS1 UART0_ RTS_b FTM0_CH4 EWM_IN SPI1_ PCS0 ADC0_ SE6b PTD5 UART0_ CTS_b FTM0_CH5 EWM_ OUT_b SPI1_SCK ADC0_ SE7b PTD6/ SPI0_ LLWU_P15 PCS3 UART0_RX FTM0_CH6 FTM0_ FLT0 SPI1_ SOUT PTD7 UART0_TX FTM0_CH7 FTM0_ FLT1 SPI1_SIN B1 -- -- -- -- NC NC NC C2 -- -- -- -- NC NC NC L7 -- -- -- -- NC NC NC F11 -- -- -- -- NC NC NC E11 -- -- -- -- NC NC NC A4 -- -- -- -- NC NC NC SPI0_ PCS2 EzPort K22F Sub-Family Reference Manual, Rev. 4, 08/2016 210 NXP Semiconductors Chapter 10 Signal Multiplexing and Signal Descriptions 10.3.2 K22 Pinouts PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2/LLWU_P13 PTD1 PTD0/LLWU_P12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 This figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. ADC0_DP0/ADC1_DP3 9 40 PTB17 ADC0_DM0/ADC1_DM3 10 39 PTB16 ADC1_DP0/ADC0_DP3 11 38 PTB3 ADC1_DM0/ADC0_DM3 12 37 PTB2 VDDA 13 36 PTB1 VREFH 14 35 PTB0/LLWU_P5 VREFL 15 34 RESET_b VSSA 16 33 PTA19 32 PTB18 PTA18 41 31 8 VSS NC 30 PTB19 VDD 42 29 7 PTA13/LLWU_P4 USBVDD 28 PTC0 PTA12 43 27 6 PTA5 USB0_DM 26 PTC1/LLWU_P6 PTA4/LLWU_P3 44 25 5 PTA3 USB0_DP 24 PTC2 PTA2 45 23 4 PTA1 VSS 22 PTC3/LLWU_P7 PTA0 46 21 3 VBAT VDD 20 VSS EXTAL32 47 19 2 XTAL32 PTE1/LLWU_P0 18 VDD DAC0_OUT/CMP1_IN3/ADC0_SE23 48 17 1 VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18 PTE0/CLKOUT32K Figure 10-2. K22 64 LQFP Pinout Diagram (top view) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 211 Pinout A B 1 2 3 4 5 6 PTE0/ CLKOUT32K PTD7 PTD4/ LLWU_P14 PTD1 PTC11/ LLWU_P11 PTC8 PTD3 PTC10 PTC9 PTC7 VSS VDD PTE1/ PTD6/ LLWU_P0 LLWU_P15 PTD2/ PTD0/ LLWU_P13 LLWU_P12 7 8 PTC6/ PTC5/ LLWU_P10 LLWU_P9 A PTC2 PTC4/ LLWU_P8 B PTC1/ LLWU_P6 PTB19 PTC3/ LLWU_P7 C C PTD5 D USB0_DM NC PTA0 PTA1 PTA3 PTB18 PTB17 PTC0 D E USB0_DP USBVDD VSS VDD PTA2 PTB16 PTB2 PTB3 E F ADC0_DM0/ ADC1_DM0/ ADC1_DM3 ADC0_DM3 VSSA VDDA PTA5 PTB1 PTB0/ LLWU_P5 RESET_b F G ADC0_DP0/ ADC1_DP0/ ADC1_DP3 ADC0_DP3 VREFL VREFH PTA4/ LLWU_P3 PTA13/ LLWU_P4 VDD PTA19 G H VREF_OUT/ DAC0_OUT/ CMP1_IN5/ CMP1_IN3/ CMP0_IN5/ ADC0_SE23 ADC1_SE18 XTAL32 EXTAL32 VBAT PTA12 VSS PTA18 H 3 4 5 6 7 8 1 2 Figure 10-3. K22 64 MAPBGA Pinout Diagram (transparent top view) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 212 NXP Semiconductors PTC17 PTC16 VDD VSS PTC15 PTC14 PTC13 PTC12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 90 89 88 87 86 85 84 83 82 81 80 PTC4/LLWU_P8 PTC18 92 91 76 PTD0/LLWU_P12 93 PTC5/LLWU_P9 PTD1 94 77 PTD2/LLWU_P13 95 PTC7 PTD3 96 PTC6/LLWU_P10 PTD4/LLWU_P14 97 78 PTD5 98 79 PTD6/LLWU_P15 99 100 PTD7 Chapter 10 Signal Multiplexing and Signal Descriptions PTE0/CLKOUT32K 1 75 VDD PTE1/LLWU_P0 2 74 VSS PTE2/LLWU_P1 3 73 PTC3/LLWU_P7 PTE3 4 72 PTC2 PTE4/LLWU_P2 5 71 PTC1/LLWU_P6 PTE5 6 70 PTC0 PTE6 7 69 PTB23 VDD 8 68 PTB22 9 67 PTB21 USB0_DP 10 66 PTB20 USB0_DM 11 65 PTB19 USBVDD 12 64 PTB18 NC 13 63 PTB17 ADC0_DP1 14 62 PTB16 VSS ADC0_DM1 15 61 VDD ADC1_DP1/ADC0_DP2 16 60 VSS ADC1_DM1/ADC0_DM2 17 59 PTB11 ADC0_DP0/ADC1_DP3 18 58 PTB10 ADC0_DM0/ADC1_DM3 19 57 PTB9 ADC1_DP0/ADC0_DP3 20 56 PTB3 39 40 41 42 43 44 45 46 47 48 49 50 VDD VSS PTA12 PTA13/LLWU_P4 PTA14 PTA15 PTA16 PTA17 VDD VSS PTA18 PTA2 PTA5 36 PTA1 38 35 PTA0 37 34 PTE26/CLKOUT32K PTA3 33 PTA4/LLWU_P3 32 PTA19 31 RESET_b 51 PTE25 52 25 PTE24 24 VSSA VBAT VREFL 30 PTB0/LLWU_P5 29 53 EXTAL32 23 28 VREFH 27 PTB1 XTAL32 PTB2 54 DAC0_OUT/CMP1_IN3/ADC0_SE23 55 22 26 21 VDDA VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18 ADC1_DM0/ADC0_DM3 Figure 10-4. K22 100 LQFP Pinout Diagram (top view) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 213 Pinout 1 2 3 4 5 6 7 8 9 10 11 A PTD7 PTD5 PTD4/ LLWU_P14 NC PTC14 PTC13 PTC8 PTC4/ LLWU_P8 NC NC NC A B NC PTD6/ LLWU_P15 PTD3 PTC18 PTC15 PTC12 PTC7 PTC3/ LLWU_P7 PTC0 PTB16 NC B C NC NC PTD2/ LLWU_P13 PTC17 PTC11/ LLWU_P11 PTC10 PTC6/ LLWU_P10 PTC2 PTB19 PTB11 NC C D NC NC PTD1 PTD0/ LLWU_P12 PTC16 PTC9 PTC5/ LLWU_P9 PTC1/ LLWU_P6 PTB18 PTB10 PTB8 D E NC PTE2/ LLWU_P1 VDD VDD VDD PTB23 PTB17 PTB9 NC E F USB0_DP USB0_DM PTE6 PTE3 VDDA VSSA VSS PTB22 PTB21 PTB20 NC F G USBVDD NC VSS PTE5 VREFH VREFL VSS PTB3 PTB2 PTB1 PTB0/ LLWU_P5 G PTA1 PTA3 PTA17 NC H PTE1/ PTE0/ LLWU_P0 CLKOUT32K H ADC0_DP1 ADC0_DM1 NC NC PTE24 J ADC1_DP1/ ADC1_DM1/ ADC0_DP2 ADC0_DM2 NC NC PTE25 K ADC0_DP0/ ADC0_DM0/ ADC1_DP3 ADC1_DM3 NC L VREF_OUT/ ADC1_DP0/ ADC1_DM0/ CMP1_IN5/ ADC0_DP3 ADC0_DM3 CMP0_IN5/ ADC1_SE18 1 2 3 PTE26/ PTE4/ CLKOUT32K LLWU_P2 CMP0_IN4/ DAC0_OUT/ ADC1_SE23 CMP1_IN3/ ADC0_SE23 PTA0 PTA2 PTA4/ LLWU_P3 NC PTA16 RESET_b J VBAT PTA5 PTA12 PTA14 VSS PTA19 K L XTAL32 EXTAL32 VSS NC PTA13/ LLWU_P4 PTA15 VDD PTA18 4 5 6 7 8 9 10 11 Figure 10-5. K22 121 XFBGA Pinout Diagram (top view) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 214 NXP Semiconductors Chapter 10 Signal Multiplexing and Signal Descriptions 1 2 3 PTD0/ PTC4/ LLWU_P8 LLWU_P12 4 5 6 7 PTD1 PTD4/ LLWU_P14 PTD7 PTE3 A A PTC3/ LLWU_P7 B PTC1/ LLWU_P6 PTC2 PTC7 PTD2/ LLWU_P13 PTD5 PTE0/ CLKOUT32K VDD B C PTC0 PTB17 PTC6/ LLWU_P10 PTD3 PTD6/ LLWU_P15 VSS USB0_DP C D PTB16 PTB2 PTC5/ LLWU_P9 PTE5 PTE1/ LLWU_P0 USBVDD USB0_DM D E PTB3 PTB1 PTB0/ LLWU_P5 PTE4/ LLWU_P2 PTE2/ LLWU_P1 PTA3 PTA2 E F RESET_b VSS PTA4/ LLWU_P3 PTA0 XTAL32 PTA1 VDDA/ VREFH F G PTA19 PTA18 VDD VBAT VSSA/ VREFL G VREF_OUT/ EXTAL32 CMP1_IN5/ CMP0_IN5/ ADC1_SE18 Figure 10-6. K22 49 WLCSP Pinout Diagram (transparent top view) 10.4 Module Signal Description Tables The following sections correlate the chip-level signal name with the signal name used in the module's chapter. They also briefly describe the signal function and direction. 10.4.1 Core Modules Table 10-3. JTAG Signal Descriptions Chip signal name Module signal name Description I/O JTAG_TMS JTAG_TMS/ SWD_DIO JTAG Test Mode Selection I JTAG_TCLK JTAG_TCLK/ SWD_CLK JTAG Test Clock I JTAG_TDI JTAG_TDI JTAG Test Data Input I JTAG_TDO JTAG_TDO/ TRACE_SWO JTAG Test Data Output O JTAG_TRST JTAG_TRST_b JTAG Reset I K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 215 Module Signal Description Tables Table 10-4. SWD Signal Descriptions Chip signal name Module signal name Description I/O SWD_DIO JTAG_TMS/ SWD_DIO Serial Wire Data I SWD_CLK JTAG_TCLK/ SWD_CLK Serial Wire Clock I Table 10-5. TPIU Signal Descriptions Chip signal name Module signal name Description I/O TRACE_SWO JTAG_TDO/ TRACE_SWO Trace output data from the ARM CoreSight debug block over a single pin O 10.4.2 System Modules Table 10-6. EWM Signal Descriptions Chip signal name Module signal name EWM_IN EWM_in EWM_OUT EWM_out Description I/O EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low. I EWM reset out signal O 10.4.3 Clock Modules Table 10-7. OSC Signal Descriptions Chip signal name Module signal name EXTAL0 EXTAL XTAL0 XTAL Description I/O External clock/Oscillator input I Oscillator output O Table 10-8. RTC OSC Signal Descriptions Chip signal name Module signal name EXTAL32 EXTAL32 XTAL32 XTAL32 Description I/O 32.768 kHz oscillator input I 32.768 kHz oscillator output O K22F Sub-Family Reference Manual, Rev. 4, 08/2016 216 NXP Semiconductors Chapter 10 Signal Multiplexing and Signal Descriptions 10.4.4 Memories and Memory Interfaces Table 10-9. EzPort Signal Descriptions Chip signal name Module signal name Description I/O EZP_CLK EZP_CK EzPort Clock Input EZP_CS EZP_CS EzPort Chip Select Input EZP_DI EZP_D EzPort Serial Data In Input EZP_DO EZP_Q EzPort Serial Data Out Output 10.4.5 Analog Table 10-10. ADC 0 Signal Descriptions Chip signal name Module signal name Description I/O ADC0_DP[3:0] DADP3-DADP0 Differential Analog Channel Inputs I ADC0_DM[3:0] DADM3-DADM0 Differential Analog Channel Inputs I ADC0_SEn ADn Single-Ended Analog Channel Inputs I VREFH VREFSH Voltage Reference Select High I VREFL VREFSL Voltage Reference Select Low I VDDA VDDA Analog Power Supply I VSSA VSSA Analog Ground I Table 10-11. ADC 1 Signal Descriptions Chip signal name Module signal name Description I/O ADC1_DP3, ADC1_DP[1:0] DADP3-DADP0 Differential Analog Channel Inputs I ADC1_DM3, ADC1_DM[1:0] DADM3-DADM0 Differential Analog Channel Inputs I ADC1_SEn ADn Single-Ended Analog Channel Inputs I VREFH VREFSH Voltage Reference Select High I VREFL VREFSL Voltage Reference Select Low I VDDA VDDA Analog Power Supply I VSSA VSSA Analog Ground I K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 217 Module Signal Description Tables Table 10-12. CMP 0 Signal Descriptions Chip signal name Module signal name Description I/O CMP0_IN[5:0] IN[5:0] Analog voltage inputs I CMP0_OUT CMPO Comparator output O Table 10-13. CMP 1 Signal Descriptions Chip signal name Module signal name Description I/O CMP1_IN[5:0] IN[5:0] Analog voltage inputs I CMP1_OUT CMPO Comparator output O Table 10-14. DAC 0 Signal Descriptions Chip signal name Module signal name DAC0_OUT -- Description I/O DAC output O Table 10-15. VREF Signal Descriptions Chip signal name Module signal name VREF_OUT VREF_OUT Description I/O Internally-generated Voltage Reference output O 10.4.6 Timer Modules Table 10-16. FTM 0 Signal Descriptions Chip signal name Module signal name FTM_CLKIN[1:0] EXTCLK FTM0_CH[7:0] CHn FTM0_FLT[3:0] FAULTj Description I/O External clock. FTM external clock can be selected to drive the FTM counter. FTM channel (n), where n can be 7-0 I I/O Fault input (j), where j can be 3-0 I Table 10-17. FTM 1 Signal Descriptions Chip signal name Module signal name FTM_CLKIN[1:0] EXTCLK Description I/O External clock. FTM external clock can be selected to drive the FTM counter. I Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 218 NXP Semiconductors Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-17. FTM 1 Signal Descriptions (continued) Chip signal name Module signal name FTM1_CH[1:0] CHn FTM1_FLT0 FAULTj FTM1_QD_PHA FTM1_QD_PHB Description I/O FTM channel (n), where n can be 7-0 I/O Fault input (j), where j can be 3-0 I PHA Quadrature decoder phase A input. Input pin associated with quadrature decoder phase A. I PHB Quadrature decoder phase B input. Input pin associated with quadrature decoder phase B. I Table 10-18. FTM 2 Signal Descriptions Chip signal name Module signal name FTM_CLKIN[1:0] EXTCLK FTM2_CH[1:0] CHn FTM2_FLT0 FAULTj FTM2_QD_PHA FTM2_QD_PHB Description External clock. FTM external clock can be selected to drive the FTM counter. FTM channel (n), where n can be 7-0 I/O I I/O Fault input (j), where j can be 3-0 I PHA Quadrature decoder phase A input. Input pin associated with quadrature decoder phase A. I PHB Quadrature decoder phase B input. Input pin associated with quadrature decoder phase B. I Table 10-19. PDB 0 Signal Descriptions Chip signal name Module signal name PDB0_EXTRG EXTRG Description External Trigger Input Source I/O I If the PDB is enabled and external trigger input source is selected, a positive edge on the EXTRG signal resets and starts the counter. Table 10-20. LPTMR 0 Signal Descriptions Chip signal name Module signal name Description LPTMR0_ALT[:1] LPTMR0_ALTn Pulse Counter Input pin I/O I Table 10-21. RTC Signal Descriptions Chip signal name Module signal name VBAT -- RTC_CLKOUT RTC_CLKOUT Description I/O Backup battery supply for RTC and VBAT register file I 1 Hz square-wave output or OSCERCLK O K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 219 Module Signal Description Tables 10.4.7 Communication Interfaces Table 10-22. USB FS OTG Signal Descriptions Chip signal name Module signal name Description I/O USB0_DM usb_dm USB D- analog data signal on the USB bus. I/O USB0_DP usb_dp USB D+ analog data signal on the USB bus. I/O USB_CLKIN -- Alternate USB clock input I USB_SOF_OUT -- USB start of frame signal. Can be used to make the USB start of frame available for external synchronization. O Table 10-23. SPI 0 Signal Descriptions Chip signal name Module signal name Description I/O SPI0_PCS0 PCS0/SS Peripheral Chip Select 0 (O) I/O SPI0_PCS[3:1] PCS[1:3] Peripheral Chip Selects 1-3 O SPI0_PCS4 PCS4 Peripheral Chip Select 4 O SPI0_PCS5 PCS5/ PCSS Peripheral Chip Select 5 /Peripheral Chip Select Strobe O SPI0_SIN SIN Serial Data In I SPI0_SOUT SOUT Serial Data Out O SPI0_SCK SCK Serial Clock (O) I/O Table 10-24. SPI 1 Signal Descriptions Chip signal name Module signal name Description I/O SPI1_PCS0 PCS0/SS Peripheral Chip Select 0 (O) I/O SPI1_PCS[3:1] PCS[1:3] Peripheral Chip Selects 1-3 O SPI1_SIN SIN Serial Data In I SPI1_SOUT SOUT Serial Data Out O SPI1_SCK SCK Serial Clock (O) I/O Table 10-25. I2C 0 Signal Descriptions Chip signal name Module signal name I2C0_SCL SCL I2C0_SDA SDA Description I/O Bidirectional serial clock line of the I2C system. Bidirectional serial data line of the I2C system. I/O I/O K22F Sub-Family Reference Manual, Rev. 4, 08/2016 220 NXP Semiconductors Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-26. I2C 1 Signal Descriptions Chip signal name Module signal name I2C1_SCL SCL I2C1_SDA SDA Description I/O Bidirectional serial clock line of the I2C system. Bidirectional serial data line of the I2C system. I/O I/O Table 10-27. LPUART Signal Descriptions Chip signal name Module signal name Description I/O UART0_TX TxD Transmit Data O UART0_RX RxD Receive Data I Table 10-28. UART 0 Signal Descriptions Chip signal name Module signal name Description I/O UART0_CTS CTS Clear to send I UART0_RTS RTS Request to send O UART0_TX TXD Transmit data O UART0_RX RXD Receive data I Table 10-29. UART 1 Signal Descriptions Chip signal name Module signal name Description I/O UART1_CTS CTS Clear to send I UART1_RTS RTS Request to send O UART1_TX TXD Transmit data O UART1_RX RXD Receive data I Table 10-30. UART 2 Signal Descriptions Chip signal name Module signal name Description I/O UART2_CTS CTS Clear to send I UART2_RTS RTS Request to send O UART2_TX TXD Transmit data O UART2_RX RXD Receive data I K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 221 Module Signal Description Tables Table 10-31. I2S0 Signal Descriptions Chip signal name Module signal name Description I/O I2S0_MCLK SAI_MCLK Audio Master Clock. The master clock is an input when externally generated and an output when internally generated. I/O I2S0_RX_BCLK SAI_RX_BCLK Receive Bit Clock. The bit clock is an input when externally generated and an output when internally generated. I/O I2S0_RX_FS SAI_RX_SYNC Receive Frame Sync. The frame sync is an input sampled synchronously by the bit clock when externally generated and an output generated synchronously by the bit clock when internally generated. I/O I2S0_RXD SAI_RX_DATA Receive Data. The receive data is sampled synchronously by the bit clock. I I2S0_TX_BCLK SAI_TX_BCLK Transmit Bit Clock. The bit clock is an input when externally generated and an output when internally generated. I/O I2S0_TX_FS SAI_TX_SYNC Transmit Frame Sync. The frame sync is an input sampled synchronously by the bit clock when externally generated and an output generated synchronously by the bit clock when internally generated. I/O I2S0_TXD SAI_TX_DATA Transmit Data. The transmit data is generated synchronously by the bit clock and is tristated whenever not transmitting a word. O 10.4.8 Human-Machine Interfaces (HMI) Table 10-32. GPIO Signal Descriptions Chip signal name Module signal name Description I/O PTA[31:0]1 PORTA31-PORTA0 General-purpose input/output I/O PTB[31:0]1 PORTB31-PORTB0 General-purpose input/output I/O PTC[31:0]1 PORTC31-PORTC0 General-purpose input/output I/O PTD[31:0]1 PORTD31-PORTD0 General-purpose input/output I/O PTE[31:0]1 PORTE31-PORTE0 General-purpose input/output I/O 1. The available GPIO pins depends on the specific package. See the signal multiplexing section for which exact GPIO signals are available. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 222 NXP Semiconductors Chapter 11 Port Control and Interrupts (PORT) 11.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. 11.2 Overview The Port Control and Interrupt (PORT) module provides support for port control, digital filtering, and external interrupt functions. Most functions can be configured independently for each pin in the 32-bit port and affect the pin regardless of its pin muxing state. There is one instance of the PORT module for each port. Not all pins within each port are implemented on a specific device. 11.2.1 Features The PORT module has the following features: * Pin interrupt * Interrupt flag and enable registers for each pin * Support for edge sensitive (rising, falling, both) or level sensitive (low, high) configured per pin * Support for interrupt or DMA request configured per pin * Asynchronous wake-up in low-power modes * Pin interrupt is functional in all digital pin muxing modes * Digital input filter on selected pins K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 223 Overview * Digital input filter for each pin, usable by any digital peripheral muxed onto the pin * Individual enable or bypass control field per pin * Selectable clock source for digital input filter with a five bit resolution on filter size * Functional in all digital pin multiplexing modes * Port control * Individual pull control fields with pullup, pulldown, and pull-disable support * Individual drive strength field supporting high and low drive strength * Individual slew rate field supporting fast and slow slew rates * Individual input passive filter field supporting enable and disable of the individual input passive filter * Individual open drain field supporting enable and disable of the individual open drain output * Individual mux control field supporting analog or pin disabled, GPIO, and up to six chip-specific digital functions * Pad configuration fields are functional in all digital pin muxing modes. 11.2.2 Modes of operation 11.2.2.1 Run mode In Run mode, the PORT operates normally. 11.2.2.2 Wait mode In Wait mode, PORT continues to operate normally and may be configured to exit the Low-Power mode if an enabled interrupt is detected. DMA requests are still generated during the Wait mode, but do not cause an exit from the Low-Power mode. 11.2.2.3 Stop mode In Stop mode, the PORT can be configured to exit the Low-Power mode via an asynchronous wake-up signal if an enabled interrupt is detected. In Stop mode, the digital input filters are bypassed unless they are configured to run from the LPO clock source. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 224 NXP Semiconductors Chapter 11 Port Control and Interrupts (PORT) 11.2.2.4 Debug mode In Debug mode, PORT operates normally. 11.3 External signal description The table found here describes the PORT external signal. Table 11-1. Signal properties Name Function I/O Reset Pull PORTx[31:0] External interrupt I/O 0 - NOTE Not all pins within each port are implemented on each device. 11.4 Detailed signal description The table found here contains the detailed signal description for the PORT interface. Table 11-2. PORT interface--detailed signal description Signal PORTx[31:0] I/O I/O Description External interrupt. State meaning Asserted--pin is logic 1. Negated--pin is logic 0. Timing Assertion--may occur at any time and can assert asynchronously to the system clock. Negation--may occur at any time and can assert asynchronously to the system clock. 11.5 Memory map and register definition Any read or write access to the PORT memory space that is outside the valid memory map results in a bus error. All register accesses complete with zero wait states. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 225 Memory map and register definition PORT memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_9000 Pin Control Register n (PORTA_PCR0) 32 R/W See section 11.5.1/232 4004_9004 Pin Control Register n (PORTA_PCR1) 32 R/W See section 11.5.1/232 4004_9008 Pin Control Register n (PORTA_PCR2) 32 R/W See section 11.5.1/232 4004_900C Pin Control Register n (PORTA_PCR3) 32 R/W See section 11.5.1/232 4004_9010 Pin Control Register n (PORTA_PCR4) 32 R/W See section 11.5.1/232 4004_9014 Pin Control Register n (PORTA_PCR5) 32 R/W See section 11.5.1/232 4004_9018 Pin Control Register n (PORTA_PCR6) 32 R/W See section 11.5.1/232 4004_901C Pin Control Register n (PORTA_PCR7) 32 R/W See section 11.5.1/232 4004_9020 Pin Control Register n (PORTA_PCR8) 32 R/W See section 11.5.1/232 4004_9024 Pin Control Register n (PORTA_PCR9) 32 R/W See section 11.5.1/232 4004_9028 Pin Control Register n (PORTA_PCR10) 32 R/W See section 11.5.1/232 4004_902C Pin Control Register n (PORTA_PCR11) 32 R/W See section 11.5.1/232 4004_9030 Pin Control Register n (PORTA_PCR12) 32 R/W See section 11.5.1/232 4004_9034 Pin Control Register n (PORTA_PCR13) 32 R/W See section 11.5.1/232 4004_9038 Pin Control Register n (PORTA_PCR14) 32 R/W See section 11.5.1/232 4004_903C Pin Control Register n (PORTA_PCR15) 32 R/W See section 11.5.1/232 4004_9040 Pin Control Register n (PORTA_PCR16) 32 R/W See section 11.5.1/232 4004_9044 Pin Control Register n (PORTA_PCR17) 32 R/W See section 11.5.1/232 4004_9048 Pin Control Register n (PORTA_PCR18) 32 R/W See section 11.5.1/232 4004_904C Pin Control Register n (PORTA_PCR19) 32 R/W See section 11.5.1/232 4004_9050 Pin Control Register n (PORTA_PCR20) 32 R/W See section 11.5.1/232 4004_9054 Pin Control Register n (PORTA_PCR21) 32 R/W See section 11.5.1/232 4004_9058 Pin Control Register n (PORTA_PCR22) 32 R/W See section 11.5.1/232 4004_905C Pin Control Register n (PORTA_PCR23) 32 R/W See section 11.5.1/232 4004_9060 Pin Control Register n (PORTA_PCR24) 32 R/W See section 11.5.1/232 4004_9064 Pin Control Register n (PORTA_PCR25) 32 R/W See section 11.5.1/232 4004_9068 Pin Control Register n (PORTA_PCR26) 32 R/W See section 11.5.1/232 4004_906C Pin Control Register n (PORTA_PCR27) 32 R/W See section 11.5.1/232 4004_9070 Pin Control Register n (PORTA_PCR28) 32 R/W See section 11.5.1/232 4004_9074 Pin Control Register n (PORTA_PCR29) 32 R/W See section 11.5.1/232 4004_9078 Pin Control Register n (PORTA_PCR30) 32 R/W See section 11.5.1/232 4004_907C Pin Control Register n (PORTA_PCR31) 32 R/W See section 11.5.1/232 4004_9080 Global Pin Control Low Register (PORTA_GPCLR) 32 W (always 0000_0000h reads 0) 11.5.2/235 4004_9084 Global Pin Control High Register (PORTA_GPCHR) 32 W (always 0000_0000h reads 0) 11.5.3/235 4004_90A0 Interrupt Status Flag Register (PORTA_ISFR) 32 w1c 0000_0000h 11.5.4/236 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 226 NXP Semiconductors Chapter 11 Port Control and Interrupts (PORT) PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_90C0 Digital Filter Enable Register (PORTA_DFER) 32 R/W 0000_0000h 11.5.5/236 4004_90C4 Digital Filter Clock Register (PORTA_DFCR) 32 R/W 0000_0000h 11.5.6/237 4004_90C8 Digital Filter Width Register (PORTA_DFWR) 32 R/W 0000_0000h 11.5.7/237 4004_A000 Pin Control Register n (PORTB_PCR0) 32 R/W See section 11.5.1/232 4004_A004 Pin Control Register n (PORTB_PCR1) 32 R/W See section 11.5.1/232 4004_A008 Pin Control Register n (PORTB_PCR2) 32 R/W See section 11.5.1/232 4004_A00C Pin Control Register n (PORTB_PCR3) 32 R/W See section 11.5.1/232 4004_A010 Pin Control Register n (PORTB_PCR4) 32 R/W See section 11.5.1/232 4004_A014 Pin Control Register n (PORTB_PCR5) 32 R/W See section 11.5.1/232 4004_A018 Pin Control Register n (PORTB_PCR6) 32 R/W See section 11.5.1/232 4004_A01C Pin Control Register n (PORTB_PCR7) 32 R/W See section 11.5.1/232 4004_A020 Pin Control Register n (PORTB_PCR8) 32 R/W See section 11.5.1/232 4004_A024 Pin Control Register n (PORTB_PCR9) 32 R/W See section 11.5.1/232 4004_A028 Pin Control Register n (PORTB_PCR10) 32 R/W See section 11.5.1/232 4004_A02C Pin Control Register n (PORTB_PCR11) 32 R/W See section 11.5.1/232 4004_A030 Pin Control Register n (PORTB_PCR12) 32 R/W See section 11.5.1/232 4004_A034 Pin Control Register n (PORTB_PCR13) 32 R/W See section 11.5.1/232 4004_A038 Pin Control Register n (PORTB_PCR14) 32 R/W See section 11.5.1/232 4004_A03C Pin Control Register n (PORTB_PCR15) 32 R/W See section 11.5.1/232 4004_A040 Pin Control Register n (PORTB_PCR16) 32 R/W See section 11.5.1/232 4004_A044 Pin Control Register n (PORTB_PCR17) 32 R/W See section 11.5.1/232 4004_A048 Pin Control Register n (PORTB_PCR18) 32 R/W See section 11.5.1/232 4004_A04C Pin Control Register n (PORTB_PCR19) 32 R/W See section 11.5.1/232 4004_A050 Pin Control Register n (PORTB_PCR20) 32 R/W See section 11.5.1/232 4004_A054 Pin Control Register n (PORTB_PCR21) 32 R/W See section 11.5.1/232 4004_A058 Pin Control Register n (PORTB_PCR22) 32 R/W See section 11.5.1/232 4004_A05C Pin Control Register n (PORTB_PCR23) 32 R/W See section 11.5.1/232 4004_A060 Pin Control Register n (PORTB_PCR24) 32 R/W See section 11.5.1/232 4004_A064 Pin Control Register n (PORTB_PCR25) 32 R/W See section 11.5.1/232 4004_A068 Pin Control Register n (PORTB_PCR26) 32 R/W See section 11.5.1/232 4004_A06C Pin Control Register n (PORTB_PCR27) 32 R/W See section 11.5.1/232 4004_A070 Pin Control Register n (PORTB_PCR28) 32 R/W See section 11.5.1/232 4004_A074 Pin Control Register n (PORTB_PCR29) 32 R/W See section 11.5.1/232 4004_A078 Pin Control Register n (PORTB_PCR30) 32 R/W See section 11.5.1/232 4004_A07C Pin Control Register n (PORTB_PCR31) 32 R/W See section 11.5.1/232 4004_A080 32 W (always 0000_0000h reads 0) 11.5.2/235 Global Pin Control Low Register (PORTB_GPCLR) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 227 Memory map and register definition PORT memory map (continued) Absolute address (hex) 4004_A084 Register name Global Pin Control High Register (PORTB_GPCHR) Width Access (in bits) 32 Reset value W (always 0000_0000h reads 0) Section/ page 11.5.3/235 4004_A0A0 Interrupt Status Flag Register (PORTB_ISFR) 32 w1c 0000_0000h 11.5.4/236 4004_A0C0 Digital Filter Enable Register (PORTB_DFER) 32 R/W 0000_0000h 11.5.5/236 4004_A0C4 Digital Filter Clock Register (PORTB_DFCR) 32 R/W 0000_0000h 11.5.6/237 4004_A0C8 Digital Filter Width Register (PORTB_DFWR) 32 R/W 0000_0000h 11.5.7/237 4004_B000 Pin Control Register n (PORTC_PCR0) 32 R/W See section 11.5.1/232 4004_B004 Pin Control Register n (PORTC_PCR1) 32 R/W See section 11.5.1/232 4004_B008 Pin Control Register n (PORTC_PCR2) 32 R/W See section 11.5.1/232 4004_B00C Pin Control Register n (PORTC_PCR3) 32 R/W See section 11.5.1/232 4004_B010 Pin Control Register n (PORTC_PCR4) 32 R/W See section 11.5.1/232 4004_B014 Pin Control Register n (PORTC_PCR5) 32 R/W See section 11.5.1/232 4004_B018 Pin Control Register n (PORTC_PCR6) 32 R/W See section 11.5.1/232 4004_B01C Pin Control Register n (PORTC_PCR7) 32 R/W See section 11.5.1/232 4004_B020 Pin Control Register n (PORTC_PCR8) 32 R/W See section 11.5.1/232 4004_B024 Pin Control Register n (PORTC_PCR9) 32 R/W See section 11.5.1/232 4004_B028 Pin Control Register n (PORTC_PCR10) 32 R/W See section 11.5.1/232 4004_B02C Pin Control Register n (PORTC_PCR11) 32 R/W See section 11.5.1/232 4004_B030 Pin Control Register n (PORTC_PCR12) 32 R/W See section 11.5.1/232 4004_B034 Pin Control Register n (PORTC_PCR13) 32 R/W See section 11.5.1/232 4004_B038 Pin Control Register n (PORTC_PCR14) 32 R/W See section 11.5.1/232 4004_B03C Pin Control Register n (PORTC_PCR15) 32 R/W See section 11.5.1/232 4004_B040 Pin Control Register n (PORTC_PCR16) 32 R/W See section 11.5.1/232 4004_B044 Pin Control Register n (PORTC_PCR17) 32 R/W See section 11.5.1/232 4004_B048 Pin Control Register n (PORTC_PCR18) 32 R/W See section 11.5.1/232 4004_B04C Pin Control Register n (PORTC_PCR19) 32 R/W See section 11.5.1/232 4004_B050 Pin Control Register n (PORTC_PCR20) 32 R/W See section 11.5.1/232 4004_B054 Pin Control Register n (PORTC_PCR21) 32 R/W See section 11.5.1/232 4004_B058 Pin Control Register n (PORTC_PCR22) 32 R/W See section 11.5.1/232 4004_B05C Pin Control Register n (PORTC_PCR23) 32 R/W See section 11.5.1/232 4004_B060 Pin Control Register n (PORTC_PCR24) 32 R/W See section 11.5.1/232 4004_B064 Pin Control Register n (PORTC_PCR25) 32 R/W See section 11.5.1/232 4004_B068 Pin Control Register n (PORTC_PCR26) 32 R/W See section 11.5.1/232 4004_B06C Pin Control Register n (PORTC_PCR27) 32 R/W See section 11.5.1/232 4004_B070 Pin Control Register n (PORTC_PCR28) 32 R/W See section 11.5.1/232 4004_B074 Pin Control Register n (PORTC_PCR29) 32 R/W See section 11.5.1/232 4004_B078 Pin Control Register n (PORTC_PCR30) 32 R/W See section 11.5.1/232 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 228 NXP Semiconductors Chapter 11 Port Control and Interrupts (PORT) PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) R/W Reset value Section/ page See section 11.5.1/232 4004_B07C Pin Control Register n (PORTC_PCR31) 32 4004_B080 Global Pin Control Low Register (PORTC_GPCLR) 32 W (always 0000_0000h reads 0) 11.5.2/235 4004_B084 Global Pin Control High Register (PORTC_GPCHR) 32 W (always 0000_0000h reads 0) 11.5.3/235 4004_B0A0 Interrupt Status Flag Register (PORTC_ISFR) 32 w1c 0000_0000h 11.5.4/236 4004_B0C0 Digital Filter Enable Register (PORTC_DFER) 32 R/W 0000_0000h 11.5.5/236 4004_B0C4 Digital Filter Clock Register (PORTC_DFCR) 32 R/W 0000_0000h 11.5.6/237 4004_B0C8 Digital Filter Width Register (PORTC_DFWR) 32 R/W 0000_0000h 11.5.7/237 4004_C000 Pin Control Register n (PORTD_PCR0) 32 R/W See section 11.5.1/232 4004_C004 Pin Control Register n (PORTD_PCR1) 32 R/W See section 11.5.1/232 4004_C008 Pin Control Register n (PORTD_PCR2) 32 R/W See section 11.5.1/232 4004_C00C Pin Control Register n (PORTD_PCR3) 32 R/W See section 11.5.1/232 4004_C010 Pin Control Register n (PORTD_PCR4) 32 R/W See section 11.5.1/232 4004_C014 Pin Control Register n (PORTD_PCR5) 32 R/W See section 11.5.1/232 4004_C018 Pin Control Register n (PORTD_PCR6) 32 R/W See section 11.5.1/232 4004_C01C Pin Control Register n (PORTD_PCR7) 32 R/W See section 11.5.1/232 4004_C020 Pin Control Register n (PORTD_PCR8) 32 R/W See section 11.5.1/232 4004_C024 Pin Control Register n (PORTD_PCR9) 32 R/W See section 11.5.1/232 4004_C028 Pin Control Register n (PORTD_PCR10) 32 R/W See section 11.5.1/232 4004_C02C Pin Control Register n (PORTD_PCR11) 32 R/W See section 11.5.1/232 4004_C030 Pin Control Register n (PORTD_PCR12) 32 R/W See section 11.5.1/232 4004_C034 Pin Control Register n (PORTD_PCR13) 32 R/W See section 11.5.1/232 4004_C038 Pin Control Register n (PORTD_PCR14) 32 R/W See section 11.5.1/232 4004_C03C Pin Control Register n (PORTD_PCR15) 32 R/W See section 11.5.1/232 4004_C040 Pin Control Register n (PORTD_PCR16) 32 R/W See section 11.5.1/232 4004_C044 Pin Control Register n (PORTD_PCR17) 32 R/W See section 11.5.1/232 4004_C048 Pin Control Register n (PORTD_PCR18) 32 R/W See section 11.5.1/232 4004_C04C Pin Control Register n (PORTD_PCR19) 32 R/W See section 11.5.1/232 4004_C050 Pin Control Register n (PORTD_PCR20) 32 R/W See section 11.5.1/232 4004_C054 Pin Control Register n (PORTD_PCR21) 32 R/W See section 11.5.1/232 4004_C058 Pin Control Register n (PORTD_PCR22) 32 R/W See section 11.5.1/232 4004_C05C Pin Control Register n (PORTD_PCR23) 32 R/W See section 11.5.1/232 4004_C060 Pin Control Register n (PORTD_PCR24) 32 R/W See section 11.5.1/232 4004_C064 Pin Control Register n (PORTD_PCR25) 32 R/W See section 11.5.1/232 4004_C068 Pin Control Register n (PORTD_PCR26) 32 R/W See section 11.5.1/232 4004_C06C Pin Control Register n (PORTD_PCR27) 32 R/W See section 11.5.1/232 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 229 Memory map and register definition PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_C070 Pin Control Register n (PORTD_PCR28) 32 R/W See section 11.5.1/232 4004_C074 Pin Control Register n (PORTD_PCR29) 32 R/W See section 11.5.1/232 4004_C078 Pin Control Register n (PORTD_PCR30) 32 R/W See section 11.5.1/232 4004_C07C Pin Control Register n (PORTD_PCR31) 32 R/W See section 11.5.1/232 11.5.2/235 11.5.3/235 4004_C080 Global Pin Control Low Register (PORTD_GPCLR) 32 W (always 0000_0000h reads 0) 4004_C084 Global Pin Control High Register (PORTD_GPCHR) 32 W (always 0000_0000h reads 0) 4004_C0A0 Interrupt Status Flag Register (PORTD_ISFR) 32 w1c 0000_0000h 11.5.4/236 4004_C0C0 Digital Filter Enable Register (PORTD_DFER) 32 R/W 0000_0000h 11.5.5/236 4004_C0C4 Digital Filter Clock Register (PORTD_DFCR) 32 R/W 0000_0000h 11.5.6/237 4004_C0C8 Digital Filter Width Register (PORTD_DFWR) 32 R/W 0000_0000h 11.5.7/237 4004_D000 Pin Control Register n (PORTE_PCR0) 32 R/W See section 11.5.1/232 4004_D004 Pin Control Register n (PORTE_PCR1) 32 R/W See section 11.5.1/232 4004_D008 Pin Control Register n (PORTE_PCR2) 32 R/W See section 11.5.1/232 4004_D00C Pin Control Register n (PORTE_PCR3) 32 R/W See section 11.5.1/232 4004_D010 Pin Control Register n (PORTE_PCR4) 32 R/W See section 11.5.1/232 4004_D014 Pin Control Register n (PORTE_PCR5) 32 R/W See section 11.5.1/232 4004_D018 Pin Control Register n (PORTE_PCR6) 32 R/W See section 11.5.1/232 4004_D01C Pin Control Register n (PORTE_PCR7) 32 R/W See section 11.5.1/232 4004_D020 Pin Control Register n (PORTE_PCR8) 32 R/W See section 11.5.1/232 4004_D024 Pin Control Register n (PORTE_PCR9) 32 R/W See section 11.5.1/232 4004_D028 Pin Control Register n (PORTE_PCR10) 32 R/W See section 11.5.1/232 4004_D02C Pin Control Register n (PORTE_PCR11) 32 R/W See section 11.5.1/232 4004_D030 Pin Control Register n (PORTE_PCR12) 32 R/W See section 11.5.1/232 4004_D034 Pin Control Register n (PORTE_PCR13) 32 R/W See section 11.5.1/232 4004_D038 Pin Control Register n (PORTE_PCR14) 32 R/W See section 11.5.1/232 4004_D03C Pin Control Register n (PORTE_PCR15) 32 R/W See section 11.5.1/232 4004_D040 Pin Control Register n (PORTE_PCR16) 32 R/W See section 11.5.1/232 4004_D044 Pin Control Register n (PORTE_PCR17) 32 R/W See section 11.5.1/232 4004_D048 Pin Control Register n (PORTE_PCR18) 32 R/W See section 11.5.1/232 4004_D04C Pin Control Register n (PORTE_PCR19) 32 R/W See section 11.5.1/232 4004_D050 Pin Control Register n (PORTE_PCR20) 32 R/W See section 11.5.1/232 4004_D054 Pin Control Register n (PORTE_PCR21) 32 R/W See section 11.5.1/232 4004_D058 Pin Control Register n (PORTE_PCR22) 32 R/W See section 11.5.1/232 4004_D05C Pin Control Register n (PORTE_PCR23) 32 R/W See section 11.5.1/232 4004_D060 32 R/W See section 11.5.1/232 Pin Control Register n (PORTE_PCR24) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 230 NXP Semiconductors Chapter 11 Port Control and Interrupts (PORT) PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_D064 Pin Control Register n (PORTE_PCR25) 32 R/W See section 11.5.1/232 4004_D068 Pin Control Register n (PORTE_PCR26) 32 R/W See section 11.5.1/232 4004_D06C Pin Control Register n (PORTE_PCR27) 32 R/W See section 11.5.1/232 4004_D070 Pin Control Register n (PORTE_PCR28) 32 R/W See section 11.5.1/232 4004_D074 Pin Control Register n (PORTE_PCR29) 32 R/W See section 11.5.1/232 4004_D078 Pin Control Register n (PORTE_PCR30) 32 R/W See section 11.5.1/232 4004_D07C Pin Control Register n (PORTE_PCR31) 32 R/W See section 11.5.1/232 4004_D080 Global Pin Control Low Register (PORTE_GPCLR) 32 W (always 0000_0000h reads 0) 11.5.2/235 4004_D084 Global Pin Control High Register (PORTE_GPCHR) 32 W (always 0000_0000h reads 0) 11.5.3/235 4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR) 32 w1c 0000_0000h 11.5.4/236 4004_D0C0 Digital Filter Enable Register (PORTE_DFER) 32 R/W 0000_0000h 11.5.5/236 4004_D0C4 Digital Filter Clock Register (PORTE_DFCR) 32 R/W 0000_0000h 11.5.6/237 4004_D0C8 Digital Filter Width Register (PORTE_DFWR) 32 R/W 0000_0000h 11.5.7/237 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 231 Memory map and register definition 11.5.1 Pin Control Register n (PORTx_PCRn) NOTE See the Signal Multiplexing and Pin Assignment chapter for the reset value of this device. See the GPIO Configuration section for details on the available functions for each pin. Do not modify pin configuration registers associated with pins that are not available in a reduced-pin package offering. Unbonded pins not available in a package are disabled by default to prevent them from consuming power. Address: Base address + 0h offset + (4d x i), where i=0d to 31d Bit 31 30 29 28 27 26 25 0 R 24 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Reset 21 20 19 18 0 0 LK 0 0 0 MUX 0 * * 0 0 0 0 7 6 5 4 0 * * 0 17 16 IRQC w1c Reset W 22 ISF W R 23 DSE ODE PFE * 0 * 0 0 0 0 3 2 1 0 SRE PE PS * * * 0 0 * Notes: * MUX field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. * DSE field: Varies by port. See the Signal Multiplexing and Signal Descriptions chapter for reset values per port. * PFE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. * SRE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. * PE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. * PS field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. PORTx_PCRn field descriptions Field 31-25 Reserved 24 ISF Description This field is reserved. This read-only field is reserved and always has the value 0. Interrupt Status Flag The pin interrupt configuration is valid in all digital pin muxing modes. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 232 NXP Semiconductors Chapter 11 Port Control and Interrupts (PORT) PORTx_PCRn field descriptions (continued) Field Description 0 1 23-20 Reserved 19-16 IRQC Configured interrupt is not detected. Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. This field is reserved. This read-only field is reserved and always has the value 0. Interrupt Configuration The pin interrupt configuration is valid in all digital pin muxing modes. The corresponding pin is configured to generate interrupt/DMA request as follows: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 15 LK 14-12 Reserved 11-8 MUX Interrupt Status Flag (ISF) is disabled. ISF flag and DMA request on rising edge. ISF flag and DMA request on falling edge. ISF flag and DMA request on either edge. Reserved. Reserved. Reserved. Reserved. ISF flag and Interrupt when logic 0. ISF flag and Interrupt on rising-edge. ISF flag and Interrupt on falling-edge. ISF flag and Interrupt on either edge. ISF flag and Interrupt when logic 1. Reserved. Reserved. Reserved. Lock Register 0 1 Pin Control Register fields [15:0] are not locked. Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. This field is reserved. This read-only field is reserved and always has the value 0. Pin Mux Control Not all pins support all pin muxing slots. Unimplemented pin muxing slots are reserved and may result in configuring the pin for a different pin muxing slot. The corresponding pin is configured in the following pin muxing slot as follows: 0000 0001 0010 0011 0100 0101 0110 0111 Pin disabled. Alternative 1 (GPIO). Alternative 2 (chip-specific). Alternative 3 (chip-specific). Alternative 4 (chip-specific). Alternative 5 (chip-specific). Alternative 6 (chip-specific). Alternative 7 (chip-specific). Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 233 Memory map and register definition PORTx_PCRn field descriptions (continued) Field Description 1000 1001 1010 1011 1100 1101 1110 1111 7 Reserved 6 DSE This field is reserved. This read-only field is reserved and always has the value 0. Drive Strength Enable Drive strength configuration is valid in all digital pin muxing modes. 0 1 5 ODE Open drain configuration is valid in all digital pin muxing modes. 2 SRE Passive filter configuration is valid in all digital pin muxing modes. Slew Rate Enable Slew rate configuration is valid in all digital pin muxing modes. Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. Pull Enable Pull configuration is valid in all digital pin muxing modes. 0 1 0 PS Passive input filter is disabled on the corresponding pin. Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. This field is reserved. This read-only field is reserved and always has the value 0. 0 1 1 PE Open drain output is disabled on the corresponding pin. Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. Passive Filter Enable 0 1 3 Reserved Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. High drive strength is configured on the corresponding pin, if pin is configured as a digital output. Open Drain Enable 0 1 4 PFE Alternative 8 (chip-specific). Alternative 9 (chip-specific). Alternative 10 (chip-specific). Alternative 11 (chip-specific). Alternative 12 (chip-specific). Alternative 13 (chip-specific). Alternative 14 (chip-specific). Alternative 15 (chip-specific). Internal pullup or pulldown resistor is not enabled on the corresponding pin. Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. Pull Select Pull configuration is valid in all digital pin muxing modes. 0 1 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 234 NXP Semiconductors Chapter 11 Port Control and Interrupts (PORT) 11.5.2 Global Pin Control Low Register (PORTx_GPCLR) Only 32-bit writes are supported to this register. Address: Base address + 80h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 R 0 0 W GPWE GPWD Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PORTx_GPCLR field descriptions Field Description 31-16 GPWE Global Pin Write Enable Selects which Pin Control Registers (15 through 0) bits [15:0] update with the value in GPWD. If a selected Pin Control Register is locked then the write to that register is ignored. 0 1 GPWD Corresponding Pin Control Register is not updated with the value in GPWD. Corresponding Pin Control Register is updated with the value in GPWD. Global Pin Write Data Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. 11.5.3 Global Pin Control High Register (PORTx_GPCHR) Only 32-bit writes are supported to this register. Address: Base address + 84h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 R 0 0 W GPWE GPWD Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PORTx_GPCHR field descriptions Field 31-16 GPWE Description Global Pin Write Enable Selects which Pin Control Registers (31 through 16) bits [15:0] update with the value in GPWD. If a selected Pin Control Register is locked then the write to that register is ignored. 0 1 GPWD Corresponding Pin Control Register is not updated with the value in GPWD. Corresponding Pin Control Register is updated with the value in GPWD. Global Pin Write Data Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 235 Memory map and register definition 11.5.4 Interrupt Status Flag Register (PORTx_ISFR) The pin interrupt configuration is valid in all digital pin muxing modes. The Interrupt Status Flag for each pin is also visible in the corresponding Pin Control Register, and each flag can be cleared in either location. Address: Base address + A0h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R ISF W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_ISFR field descriptions Field Description ISF Interrupt Status Flag Each bit in the field indicates the detection of the configured interrupt of the same number as the field. 0 1 Configured interrupt is not detected. Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. 11.5.5 Digital Filter Enable Register (PORTx_DFER) The corresponding bit is read only for pins that do not support a digital filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for the pins that support digital filter. The digital filter configuration is valid in all digital pin muxing modes. Address: Base address + C0h offset Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_DFER field descriptions Field DFE Description Digital Filter Enable K22F Sub-Family Reference Manual, Rev. 4, 08/2016 236 NXP Semiconductors Chapter 11 Port Control and Interrupts (PORT) PORTx_DFER field descriptions (continued) Field Description The digital filter configuration is valid in all digital pin muxing modes. The output of each digital filter is reset to zero at system reset and whenever the digital filter is disabled. Each bit in the field enables the digital filter of the same number as the field. 0 1 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. 11.5.6 Digital Filter Clock Register (PORTx_DFCR) This register is read only for ports that do not support a digital filter. The digital filter configuration is valid in all digital pin muxing modes. Address: Base address + C4h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R CS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_DFCR field descriptions Field 31-1 Reserved 0 CS Description This field is reserved. This read-only field is reserved and always has the value 0. Clock Source The digital filter configuration is valid in all digital pin muxing modes. Configures the clock source for the digital input filters. Changing the filter clock source must be done only when all digital filters are disabled. 0 1 Digital filters are clocked by the bus clock. Digital filters are clocked by the LPO clock. 11.5.7 Digital Filter Width Register (PORTx_DFWR) This register is read only for ports that do not support a digital filter. The digital filter configuration is valid in all digital pin muxing modes. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 237 Functional description Address: Base address + C8h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 FILT W Reset 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_DFWR field descriptions Field 31-5 Reserved FILT Description This field is reserved. This read-only field is reserved and always has the value 0. Filter Length The digital filter configuration is valid in all digital pin muxing modes. Configures the maximum size of the glitches, in clock cycles, that the digital filter absorbs for the enabled digital filters. Glitches that are longer than this register setting will pass through the digital filter, and glitches that are equal to or less than this register setting are filtered. Changing the filter length must be done only after all filters are disabled. 11.6 Functional description 11.6.1 Pin control Each port pin has a corresponding Pin Control register, PORT_PCRn, associated with it. The upper half of the Pin Control register configures the pin's capability to either interrupt the CPU or request a DMA transfer, on a rising/falling edge or both edges as well as a logic level occurring on the port pin. It also includes a flag to indicate that an interrupt has occurred. The lower half of the Pin Control register configures the following functions for each pin within the 32-bit port. * * * * * Pullup or pulldown enable Drive strength and slew rate configuration Open drain enable Passive input filter enable Pin Muxing mode The functions apply across all digital pin muxing modes and individual peripherals do not override the configuration in the Pin Control register. For example, if an I2C function is enabled on a pin, that does not override the pullup or open drain configuration for that pin. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 238 NXP Semiconductors Chapter 11 Port Control and Interrupts (PORT) When the Pin Muxing mode is configured for analog or is disabled, all the digital functions on that pin are disabled. This includes the pullup and pulldown enables, output buffer enable, input buffer enable, and passive filter enable. The LK bit (bit 15 of Pin Control Register PCRn) allows the configuration for each pin to be locked until the next system reset. When locked, writes to the lower half of that pin control register are ignored, although a bus error is not generated on an attempted write to a locked register. The configuration of each Pin Control register is retained when the PORT module is disabled. Whenever a pin is configured in any digital pin muxing mode, the input buffer for that pin is enabled allowing the pin state to be read via the corresponding GPIO Port Data Input Register (GPIO_PDIR) or allowing a pin interrupt or DMA request to be generated. If a pin is ever floating when its input buffer is enabled, then this can cause an increase in power consumption and must be avoided. A pin can be floating due to an input pin that is not connected or an output pin that has tri-stated (output buffer is disabled). Enabling the internal pull resistor (or implementing an external pull resistor) will ensure a pin does not float when its input buffer is enabled; note that the internal pull resistor is automatically disabled whenever the output buffer is enabled allowing the Pull Enable bit to remain set. Configuring the Pin Muxing mode to disabled or analog will disable the pin's input buffer and results in the lowest power consumption. 11.6.2 Global pin control The two global pin control registers allow a single register write to update the lower half of the pin control register on up to 16 pins, all with the same value. Registers that are locked cannot be written using the global pin control registers. The global pin control registers are designed to enable software to quickly configure multiple pins within the one port for the same peripheral function. However, the interrupt functions cannot be configured using the global pin control registers. The global pin control registers are write-only registers, that always read as 0. 11.6.3 External interrupts The external interrupt capability of the PORT module is available in all digital pin muxing modes provided the PORT module is enabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 239 Functional description Each pin can be individually configured for any of the following external interrupt modes: * * * * * * * * * Interrupt disabled, default out of reset Active high level sensitive interrupt Active low level sensitive interrupt Rising edge sensitive interrupt Falling edge sensitive interrupt Rising and falling edge sensitive interrupt Rising edge sensitive DMA request Falling edge sensitive DMA request Rising and falling edge sensitive DMA request The interrupt status flag is set when the configured edge or level is detected on the pin or at the output of the digital input filter, if the digital input digital filter is enabled. When not in Stop mode, the input is first synchronized to the bus clock to detect the configured level or edge transition. The PORT module generates a single interrupt that asserts when the interrupt status flag is set for any enabled interrupt for that port. The interrupt negates after the interrupt status flags for all enabled interrupts have been cleared by writing a logic 1 to the ISF flag in either the PORT_ISFR or PORT_PCRn registers. The PORT module generates a single DMA request that asserts when the interrupt status flag is set for any enabled DMA request in that port. The DMA request negates after the DMA transfer is completed, because that clears the interrupt status flags for all enabled DMA requests. During Stop mode, the interrupt status flag for any enabled interrupt is asynchronously set if the required level or edge is detected. This also generates an asynchronous wake-up signal to exit the Low-Power mode. 11.6.4 Digital filter The digital filter capabilities of the PORT module are available in all digital Pin Muxing modes if the PORT module is enabled. The clock used for all digital filters within one port can be configured between the bus clock or the LPO clock. This selection must be changed only when all digital filters for that port are disabled. If the digital filters for a port are configured to use the bus clock, then the digital filters are bypassed for the duration of Stop mode. While the digital filters K22F Sub-Family Reference Manual, Rev. 4, 08/2016 240 NXP Semiconductors Chapter 11 Port Control and Interrupts (PORT) are bypassed, the output of each digital filter always equals the input pin, but the internal state of the digital filters remains static and does not update due to any change on the input pin. The filter width in clock size is the same for all enabled digital filters within one port and must be changed only when all digital filters for that port are disabled. The output of each digital filter is logic zero after system reset and whenever a digital filter is disabled. After a digital filter is enabled, the input is synchronized to the filter clock, either the bus clock or the LPO clock. If the synchronized input and the output of the digital filter remain different for a number of filter clock cycles equal to the filter width register configuration, then the output of the digital filter updates to equal the synchronized filter input. The maximum latency through a digital filter equals three filter clock cycles plus the filter width configuration register. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 241 Functional description K22F Sub-Family Reference Manual, Rev. 4, 08/2016 242 NXP Semiconductors Chapter 12 System Integration Module (SIM) 12.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The System Integration Module (SIM) provides system control and chip configuration registers. 12.1.1 Features Features of the SIM include: * System clocking configuration * System clock divide values * Architectural clock gating control * USB clock selection and divide values * Flash and system RAM size configuration * FlexTimer external clock, hardware trigger, and fault source selection * UART0 and UART1 receive/transmit source selection/configuration K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 243 Memory map and register definition 12.2 Memory map and register definition The SIM module contains many fields for selecting the clock source and dividers for various module clocks. See the Clock Distribution chapter for more information, including block diagrams and clock definitions. NOTE The SIM_SOPT1 and SIM_SOPT1CFG registers are located at a different base address than the other SIM registers. SIM memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_7000 System Options Register 1 (SIM_SOPT1) 32 R/W See section 12.2.1/245 4004_7004 SOPT1 Configuration Register (SIM_SOPT1CFG) 32 R/W 0000_0000h 12.2.2/246 4004_8004 System Options Register 2 (SIM_SOPT2) 32 R/W 0000_1000h 12.2.3/247 4004_800C System Options Register 4 (SIM_SOPT4) 32 R/W 0000_0000h 12.2.4/249 4004_8010 System Options Register 5 (SIM_SOPT5) 32 R/W 0000_0000h 12.2.5/251 4004_8018 System Options Register 7 (SIM_SOPT7) 32 R/W 0000_0000h 12.2.6/253 4004_801C System Options Register 8 (SIM_SOPT8) 32 R/W 0000_0000h 12.2.7/255 4004_8024 System Device Identification Register (SIM_SDID) 32 R See section 12.2.8/256 4004_8034 System Clock Gating Control Register 4 (SIM_SCGC4) 32 R/W F010_0030h 12.2.9/258 4004_8038 System Clock Gating Control Register 5 (SIM_SCGC5) 32 R/W 0004_0182h 12.2.10/260 4004_803C System Clock Gating Control Register 6 (SIM_SCGC6) 32 R/W 4000_0001h 12.2.11/262 4004_8040 System Clock Gating Control Register 7 (SIM_SCGC7) 32 R/W 0000_0002h 12.2.12/265 4004_8044 System Clock Divider Register 1 (SIM_CLKDIV1) 32 R/W See section 12.2.13/265 4004_8048 System Clock Divider Register 2 (SIM_CLKDIV2) 32 R/W 0000_0000h 12.2.14/267 4004_804C Flash Configuration Register 1 (SIM_FCFG1) 32 R See section 12.2.15/268 4004_8050 Flash Configuration Register 2 (SIM_FCFG2) 32 R See section 12.2.16/270 4004_8054 Unique Identification Register High (SIM_UIDH) 32 R See section 12.2.17/270 4004_8058 Unique Identification Register Mid-High (SIM_UIDMH) 32 R See section 12.2.18/271 4004_805C Unique Identification Register Mid Low (SIM_UIDML) 32 R See section 12.2.19/271 4004_8060 Unique Identification Register Low (SIM_UIDL) 32 R See section 12.2.20/272 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 244 NXP Semiconductors Chapter 12 System Integration Module (SIM) 12.2.1 System Options Register 1 (SIM_SOPT1) NOTE The SOPT1 register is only reset on POR or LVD. Address: 4004_7000h base + 0h offset = 4004_7000h Bit 31 R 30 29 28 27 26 25 24 22 21 20 0 Reserved W 23 19 18 17 16 OSC32KSEL OSC32KOUT Reset x* x* x* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x* x* RAMSIZE R 0 Reserved W Reset x* x* x* x* 0* 0* 0* 0* 0* 0* x* x* x* x* * Notes: * x = Undefined at reset. SIM_SOPT1 field descriptions Field Description 31-29 Reserved This field is reserved. 28-20 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 19-18 OSC32KSEL 32K oscillator clock select Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset only on POR/LVD. 00 01 10 11 17-16 OSC32KOUT 32K Oscillator Clock Output Outputs the ERCLK32K on the selected pin in all modes of operation (including LLS/VLLS and System Reset), overriding the existing pin mux configuration for that pin. This field is reset only on POR/LVD. 00 01 10 11 15-12 RAMSIZE System oscillator (OSC32KCLK) Reserved RTC 32.768kHz oscillator LPO 1 kHz ERCLK32K is not output. ERCLK32K is output on PTE0. ERCLK32K is output on PTE26. Reserved. RAM size This field specifies the amount of system RAM available on the device. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 245 Memory map and register definition SIM_SOPT1 field descriptions (continued) Field Description 0001 0011 0100 0101 0110 0111 1000 1001 1011 1101 1111 8 KB 16 KB 24 KB 32 KB 48 KB 64 KB 96 KB 128 KB 256 KB 512 KB 1024 KB 11-6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Reserved This field is reserved. 12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG) NOTE The SOPT1CFG register is reset on System Reset not VLLS. Address: 4004_7000h base + 4h offset = 4004_7004h Bit 31 30 29 28 27 26 0 R 25 24 23 22 21 20 19 18 17 0 16 15 14 13 12 11 10 9 0 8 7 6 5 4 0 3 2 1 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SOPT1CFG field descriptions Field Description 31-27 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 26-24 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 23-10 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 9-8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Reserved This field is reserved. This read-only field is reserved and always has the value 0. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 246 NXP Semiconductors Chapter 12 System Integration Module (SIM) 12.2.3 System Options Register 2 (SIM_SOPT2) SOPT2 contains the controls for selecting many of the module clock source options on this device. See the Clock Distribution chapter for more information including clocking diagrams and definitions of device clocks. Address: 4004_7000h base + 1004h offset = 4004_8004h 30 29 0 R 28 27 26 25 0 W 24 23 0 22 21 0 20 19 0 18 17 USBSRC 31 LPUARTSRC Bit 16 PLLFLLSEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 R W Reset 0 0 0 1 RTCCLKOUTS EL 0 TRACECLKSE L Reset 0 CLKOUTSEL 0 0 0 0 0 0 0 0 0 0 0 SIM_SOPT2 field descriptions Field Description 31-30 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 29-28 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 27-26 LPUARTSRC LPUART clock source select Selects the clock source for the LPUART transmit and receive clock. 00 01 10 11 Clock disabled MCGFLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL]. OSCERCLK clock MCGIRCLK clock 25-24 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 23-22 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 21-19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18 USBSRC USB clock source select Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 247 Memory map and register definition SIM_SOPT2 field descriptions (continued) Field Description Selects the clock source for the USB 48 MHz clock. 0 1 17-16 PLLFLLSEL External bypass clock (USB_CLKIN). MCGFLLCLK, or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, USBDIV]. PLL/FLL clock select Selects the high frequency clock for various peripheral clocking options. NOTE: Not all chips have the option to select a PLL clock. 00 01 10 11 15-13 Reserved MCGFLLCLK clock Reserved Reserved IRC48 MHz clock This field is reserved. This read-only field is reserved and always has the value 0. 12 Debug trace clock select TRACECLKSEL Selects the core/system clock, or MCG output clock (MCGOUTCLK) as the trace clock source. 0 1 MCGOUTCLK Core/system clock 11 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 10 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 9-8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7-5 CLKOUTSEL CLKOUT select Selects the clock to output on the CLKOUT pin. 000 001 010 011 100 101 110 111 Reserved Reserved Flash clock LPO clock (1 kHz) MCGIRCLK RTC 32.768kHz clock OSCERCLK0 IRC 48 MHz clock 4 RTC clock out select RTCCLKOUTSEL Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the RTC_CLKOUT pin. 0 1 Reserved RTC 1 Hz clock is output on the RTC_CLKOUT pin. RTC 32.768kHz clock is output on the RTC_CLKOUT pin. This field is reserved. This read-only field is reserved and always has the value 0. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 248 NXP Semiconductors Chapter 12 System Integration Module (SIM) 12.2.4 System Options Register 4 (SIM_SOPT4) Address: 4004_7000h base + 100Ch offset = 4004_800Ch 23 22 21 20 19 18 17 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 FTM0FLT0 16 FTM0FLT1 FTM1CH0SRC 24 FTM2CH0SRC 25 FTM1FLT0 26 FTM2CH1SRC 27 FTM0CLKSEL 28 FTM1CLKSEL 29 FTM2CLKSEL 30 FTM0TRG0SR C 31 FTM0TRG1SR C Bit 0 0 0 0 0 0 R W 0 W Reset 0 0 0 0 0 FTM2FLT0 0 R 0 0 0 0 0 0 0 0 0 SIM_SOPT4 field descriptions Field 31-30 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 29 FlexTimer 0 Hardware Trigger 1 Source Select FTM0TRG1SRC Selects the source of FTM0 hardware trigger 1. 0 1 PDB output trigger 1 drives FTM0 hardware trigger 1 FTM2 channel match drives FTM0 hardware trigger 1 28 FlexTimer 0 Hardware Trigger 0 Source Select FTM0TRG0SRC Selects the source of FTM0 hardware trigger 0. 0 1 27 Reserved 26 FTM2CLKSEL HSCMP0 output drives FTM0 hardware trigger 0 FTM1 channel match drives FTM0 hardware trigger 0 This field is reserved. This read-only field is reserved and always has the value 0. FlexTimer 2 External Clock Pin Select Selects the external pin used to drive the clock to the FTM2 module. NOTE: The selected pin must also be configured for the FTM2 module external clock function through the appropriate pin control register in the port control module. 0 1 25 FTM1CLKSEL FTM2 external clock driven by FTM_CLK0 pin. FTM2 external clock driven by FTM_CLK1 pin. FTM1 External Clock Pin Select Selects the external pin used to drive the clock to the FTM1 module. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 249 Memory map and register definition SIM_SOPT4 field descriptions (continued) Field Description NOTE: The selected pin must also be configured for the FTM external clock function through the appropriate pin control register in the port control module. 0 1 24 FTM0CLKSEL FTM_CLK0 pin FTM_CLK1 pin FlexTimer 0 External Clock Pin Select Selects the external pin used to drive the clock to the FTM0 module. NOTE: The selected pin must also be configured for the FTM external clock function through the appropriate pin control register in the port control module. 0 1 23 Reserved FTM_CLK0 pin FTM_CLK1 pin This field is reserved. This read-only field is reserved and always has the value 0. 22 FTM2CH1SRC FTM2 channel 1 input capture source select 21-20 FTM2CH0SRC FTM2 channel 0 input capture source select 0 1 FTM2_CH1 signal Exclusive OR of FTM2_CH1, FTM2_CH0 and FTM1_CH1. Selects the source for FTM2 channel 0 input capture. NOTE: When the FTM is not in input capture mode, clear this field. 00 01 10 11 19-18 FTM1CH0SRC FTM2_CH0 signal CMP0 output CMP1 output Reserved FTM1 channel 0 input capture source select Selects the source for FTM1 channel 0 input capture. NOTE: When the FTM is not in input capture mode, clear this field. 00 01 10 11 17-9 Reserved 8 FTM2FLT0 FTM1_CH0 signal CMP0 output CMP1 output USB start of frame pulse This field is reserved. This read-only field is reserved and always has the value 0. FTM2 Fault 0 Select Selects the source of FTM2 fault 0. NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate PORTx pin control register. 0 1 FTM2_FLT0 pin CMP0 out Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 250 NXP Semiconductors Chapter 12 System Integration Module (SIM) SIM_SOPT4 field descriptions (continued) Field Description 7-5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 FTM1FLT0 FTM1 Fault 0 Select Selects the source of FTM1 fault 0. NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate pin control register in the port control module. 0 1 FTM1_FLT0 pin CMP0 out 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 FTM0FLT1 FTM0 Fault 1 Select Selects the source of FTM0 fault 1. NOTE: The pin source for fault 1 must be configured for the FTM module fault function through the appropriate pin control register in the port control module. 0 1 0 FTM0FLT0 FTM0_FLT1 pin CMP1 out FTM0 Fault 0 Select Selects the source of FTM0 fault 0. NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate pin control register in the port control module. 0 1 FTM0_FLT0 pin CMP0 out 12.2.5 System Options Register 5 (SIM_SOPT5) Address: 4004_7000h base + 1010h offset = 4004_8010h 27 26 25 24 23 22 21 20 0 R W Reset 0 0 0 0 0 0 19 18 17 0 0 0 0 0 0 0 0 16 15 14 13 12 0 0 11 10 9 8 7 0 0 0 0 0 0 0 0 0 0 0 6 5 0 0 4 3 0 0 2 1 0 0 0 UART0TXSRC 28 UART0RXSRC 29 UART1TXSRC 30 UART1RXSRC 31 LPUART0RXS RC Bit 0 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 251 Memory map and register definition SIM_SOPT5 field descriptions Field 31-20 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 19-18 LPUART0 receive data source select LPUART0RXSRC Selects the source for the LPUART0 receive data. 00 01 10 11 LPUART0_RX pin CMP0 output CMP1 output Reserved 17-16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15-8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7-6 UART1RXSRC UART 1 receive data source select Selects the source for the UART 1 receive data. 00 01 10 11 5-4 UART1TXSRC UART 1 transmit data source select Selects the source for the UART 1 transmit data. 00 01 10 11 3-2 UART0RXSRC UART1_TX pin UART1_TX pin modulated with FTM1 channel 0 output UART1_TX pin modulated with FTM2 channel 0 output Reserved UART 0 receive data source select Selects the source for the UART 0 receive data. 00 01 10 11 UART0TXSRC UART1_RX pin CMP0 CMP1 Reserved UART0_RX pin CMP0 CMP1 Reserved UART 0 transmit data source select Selects the source for the UART 0 transmit data. 00 01 10 11 UART0_TX pin UART0_TX pin modulated with FTM1 channel 0 output UART0_TX pin modulated with FTM2 channel 0 output Reserved K22F Sub-Family Reference Manual, Rev. 4, 08/2016 252 NXP Semiconductors Chapter 12 System Integration Module (SIM) 12.2.6 System Options Register 7 (SIM_SOPT7) Address: 4004_7000h base + 1018h offset = 4004_8018h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 ADC1TRGSEL 0 0 0 0 0 ADC0PRETRGS EL 0 ADC0ALTTRGE N 0 ADC1PRETRGS EL 0 ADC1ALTTRGE N Reset 0 0 0 0 ADC0TRGSEL 0 0 0 0 SIM_SOPT7 field descriptions Field 31-16 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 15 ADC1 alternate trigger enable ADC1ALTTRGEN Enable alternative conversion triggers for ADC1. 0 1 14-13 Reserved PDB trigger selected for ADC1 Alternate trigger selected for ADC1 as defined by ADC1TRGSEL. This field is reserved. This read-only field is reserved and always has the value 0. 12 ADC1 pre-trigger select ADC1PRETRGSEL Selects the ADC1 pre-trigger source when alternative triggers are enabled through ADC1ALTTRGEN. 0 1 11-8 ADC1TRGSEL Pre-trigger A selected for ADC1. Pre-trigger B selected for ADC1. ADC1 trigger select Selects the ADC1 trigger source when alternative triggers are functional in stop and VLPS modes. 0000 0001 0010 0011 0100 0101 PDB external trigger pin input (PDB0_EXTRG) High speed comparator 0 output High speed comparator 1 output Reserved PIT trigger 0 PIT trigger 1 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 253 Memory map and register definition SIM_SOPT7 field descriptions (continued) Field Description 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PIT trigger 2 PIT trigger 3 FTM0 trigger FTM1 trigger FTM2 trigger Reserved RTC alarm RTC seconds Low-power timer (LPTMR) trigger Reserved 7 ADC0 alternate trigger enable ADC0ALTTRGEN Enable alternative conversion triggers for ADC0. 0 1 6-5 Reserved PDB trigger selected for ADC0. Alternate trigger selected for ADC0. This field is reserved. This read-only field is reserved and always has the value 0. 4 ADC0 pretrigger select ADC0PRETRGSEL Selects the ADC0 pre-trigger source when alternative triggers are enabled through ADC0ALTTRGEN. 0 1 ADC0TRGSEL Pre-trigger A Pre-trigger B ADC0 trigger select Selects the ADC0 trigger source when alternative triggers are functional in stop and VLPS modes. . 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PDB external trigger pin input (PDB0_EXTRG) High speed comparator 0 output High speed comparator 1 output Reserved PIT trigger 0 PIT trigger 1 PIT trigger 2 PIT trigger 3 FTM0 trigger FTM1 trigger FTM2 trigger Reserved RTC alarm RTC seconds Low-power timer (LPTMR) trigger Reserved K22F Sub-Family Reference Manual, Rev. 4, 08/2016 254 NXP Semiconductors Chapter 12 System Integration Module (SIM) 12.2.7 System Options Register 8 (SIM_SOPT8) Address: 4004_7000h base + 101Ch offset = 4004_801Ch 21 20 19 18 17 16 FTM0OCH0SR C 22 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FTM0SYNCBIT 23 FTM0OCH1SR C 24 FTM1SYNCBIT 25 FTM0OCH2SR C 26 FTM2SYNCBIT 27 FTM0OCH3SR C 28 FTM0OCH4SR C 29 FTM0OCH5SR C 30 FTM0OCH6SR C 31 FTM0OCH7SR C Bit 0 0 0 0 R W 0 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SOPT8 field descriptions Field 31-24 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 23 FTM0 channel 7 output source FTM0OCH7SRC 0 FTM0_CH7 pin is output of FTM0 channel 7 output 1 FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by FTM1 channel 1 output 22 FTM0 channel 6 output source FTM0OCH6SRC 0 FTM0_CH6 pin is output of FTM0 channel 6 output 1 FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1 channel 1 output 21 FTM0 channel 5 output source FTM0OCH5SRC 0 FTM0_CH5 pin is output of FTM0 channel 5 output 1 FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output 20 FTM0 channel 4 output source FTM0OCH4SRC 0 FTM0_CH4 pin is output of FTM0 channel 4 output 1 FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output 19 FTM0 channel 3 output source FTM0OCH3SRC 0 FTM0_CH3 pin is output of FTM0 channel 3 output 1 FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 channel 1 output 18 FTM0 channel 2 output source FTM0OCH2SRC 0 FTM0_CH2 pin is output of FTM0 channel 2 output 1 FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 channel 1 output Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 255 Memory map and register definition SIM_SOPT8 field descriptions (continued) Field Description 17 FTM0 channel 1 output source FTM0OCH1SRC 0 FTM0_CH1 pin is output of FTM0 channel 1 output 1 FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 channel 1 output 16 FTM0 channel 0 output source FTM0OCH0SRC 0 FTM0_CH0 pin is output of FTM0 channel 0 output 1 FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 channel 1 output 15-4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 FTM2SYNCBIT FTM2 Hardware Trigger 0 Software Synchronization 1 FTM1SYNCBIT FTM1 Hardware Trigger 0 Software Synchronization 0 FTM0SYNCBIT FTM0 Hardware Trigger 0 Software Synchronization 0 1 0 1 0 1 No effect. Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert. No effect. Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert. No effect Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert. 12.2.8 System Device Identification Register (SIM_SDID) Address: 4004_7000h base + 1024h offset = 4004_8024h Bit R 31 30 29 28 FAMILYID 27 26 25 24 23 SUBFAMID 22 21 20 19 18 SERIESID 17 0 16 15 14 13 12 11 10 REVID 9 8 DIEID 7 6 5 4 FAMID 3 2 1 0 PINID W Reset x* x* x* x* x* x* x* x* x* x* x* x* 0 0 0 0 x* x* x* x* 0 1 1 0 1 x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. SIM_SDID field descriptions Field 31-28 FAMILYID Description Kinetis Family ID Specifies the Kinetis family of the device. 0000 K0x Family Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 256 NXP Semiconductors Chapter 12 System Integration Module (SIM) SIM_SDID field descriptions (continued) Field Description 0001 0010 0011 0100 0110 0111 1000 27-24 SUBFAMID Kinetis Sub-Family ID Specifies the Kinetis sub-family of the device. 0000 0001 0010 0011 0100 0101 0110 23-20 SERIESID Kx0 Subfamily Kx1 Subfamily (tamper detect) Kx2 Subfamily Kx3 Subfamily (tamper detect) Kx4 Subfamily Kx5 Subfamily (tamper detect) Kx6 Subfamily Kinetis Series ID Specifies the Kinetis series of the device. 0000 0001 0101 0110 19-16 Reserved K1x Family K2x Family K3x Family K4x Family K6x Family K7x Family K8x Family Kinetis K series Kinetis L series Kinetis W series Kinetis V series This field is reserved. This read-only field is reserved and always has the value 0. 15-12 REVID Device revision number 11-7 DIEID Device Die ID 6-4 FAMID Kinetis family identification Specifies the silicon implementation number for the device. Specifies the silicon feature set identication number for the device. This field is maintained for compatibility only, but has been superceded by the SERIESID, FAMILYID and SUBFAMID fields in this register. 000 001 010 011 100 101 110 111 PINID K1x Family (without tamper) K2x Family (without tamper) K3x Family or K1x/K6x Family (with tamper) K4x Family or K2x Family (with tamper) K6x Family (without tamper) K7x Family Reserved Reserved Pincount identification Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 257 Memory map and register definition SIM_SDID field descriptions (continued) Field Description Specifies the pincount of the device. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Reserved Reserved 32-pin Reserved 48-pin 64-pin 80-pin 81-pin or 121-pin 100-pin 121-pin 144-pin Custom pinout (WLCSP) 169-pin Reserved 256-pin Reserved 12.2.9 System Clock Gating Control Register 4 (SIM_SCGC4) Address: 4004_7000h base + 1034h offset = 4004_8034h 31 30 29 28 27 26 25 24 1 R 23 22 21 20 19 0 VREF CMP W 18 17 16 0 USBOTG Bit 1 1 0 0 0 0 0 0 0 1 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 R 0 W Reset 0 0 0 UART0 1 UART1 1 UART2 Reset 0 0 0 0 0 1 0 I2C1 I2C0 0 0 0 EWM 1 1 0 0 0 0 SIM_SCGC4 field descriptions Field Description 31-28 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 27-21 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 258 NXP Semiconductors Chapter 12 System Integration Module (SIM) SIM_SCGC4 field descriptions (continued) Field 20 VREF Description VREF Clock Gate Control This bit controls the clock gate to the VREF module. 0 1 19 CMP Comparator Clock Gate Control This bit controls the clock gate to the comparator module. 0 1 18 USBOTG Clock disabled Clock enabled Clock disabled Clock enabled USB Clock Gate Control This bit controls the clock gate to the USB module. 0 1 Clock disabled Clock enabled 17-14 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 13 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12 UART2 UART2 Clock Gate Control This bit controls the clock gate to the UART2 module. 0 1 11 UART1 UART1 Clock Gate Control This bit controls the clock gate to the UART1 module. 0 1 10 UART0 7 I2C1 This bit controls the clock gate to the UART0 module. Clock disabled Clock enabled This field is reserved. This read-only field is reserved and always has the value 0. I2C1 Clock Gate Control This bit controls the clock gate to the I 2 C1 module. 0 1 6 I2C0 Clock disabled Clock enabled UART0 Clock Gate Control 0 1 9-8 Reserved Clock disabled Clock enabled Clock disabled Clock enabled I2C0 Clock Gate Control This bit controls the clock gate to the I 2 C0 module. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 259 Memory map and register definition SIM_SCGC4 field descriptions (continued) Field Description 0 1 Clock disabled Clock enabled 5-4 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 EWM EWM Clock Gate Control This bit controls the clock gate to the EWM module. 0 1 0 Reserved Clock disabled Clock enabled This field is reserved. This read-only field is reserved and always has the value 0. 12.2.10 System Clock Gating Control Register 5 (SIM_SCGC5) Address: 4004_7000h base + 1038h offset = 4004_8038h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0 R 17 1 16 0 W 0 0 0 0 0 0 0 0 1 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R W Reset 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 LPTMR 0 PORTA 0 PORTB 0 PORTC 0 PORTD 0 PORTE Reset 0 SIM_SCGC5 field descriptions Field Description 31-19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 17-14 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 260 NXP Semiconductors Chapter 12 System Integration Module (SIM) SIM_SCGC5 field descriptions (continued) Field 13 PORTE Description Port E Clock Gate Control This bit controls the clock gate to the Port E module. 0 1 12 PORTD Port D Clock Gate Control This bit controls the clock gate to the Port D module. 0 1 11 PORTC This bit controls the clock gate to the Port C module. Clock disabled Clock enabled Port B Clock Gate Control This bit controls the clock gate to the Port B module. 0 1 9 PORTA Clock disabled Clock enabled Port C Clock Gate Control 0 1 10 PORTB Clock disabled Clock enabled Clock disabled Clock enabled Port A Clock Gate Control This bit controls the clock gate to the Port A module. 0 1 Clock disabled Clock enabled 8-7 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3-2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 0 LPTMR Low Power Timer Access Control This bit controls software access to the Low Power Timer module. 0 1 Access disabled Access enabled K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 261 Memory map and register definition 12.2.11 System Clock Gating Control Register 6 (SIM_SCGC6) Address: 4004_7000h base + 103Ch offset = 4004_803Ch Bit 31 29 26 25 24 23 22 PDB 21 20 18 17 Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 DMAMUX FTF 0 0 0 1 RTC 0 R 0 I2S SPI1 SPI0 0 0 W Reset 0 0 0 0 ADC1 FTM0 0 FTM1 0 16 FTM2 0 19 LPUART0 0 27 ADC0 1 28 PIT W DAC0 R 30 0 0 CRC 0 0 0 0 0 SIM_SCGC6 field descriptions Field 31 DAC0 Description DAC0 Clock Gate Control This bit controls the clock gate to the DAC0 module. 0 1 30 Reserved 29 RTC This field is reserved. This read-only field is reserved and always has the value 1. RTC Access Control This bit controls software access and interrupts to the RTC module. 0 1 28 Reserved 27 ADC0 Access and interrupts disabled Access and interrupts enabled This field is reserved. This read-only field is reserved and always has the value 0. ADC0 Clock Gate Control This bit controls the clock gate to the ADC0 module. 0 1 26 FTM2 Clock disabled Clock enabled Clock disabled Clock enabled FTM2 Clock Gate Control This bit controls the clock gate to the FTM2 module. 0 1 Clock disabled Clock enabled Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 262 NXP Semiconductors Chapter 12 System Integration Module (SIM) SIM_SCGC6 field descriptions (continued) Field 25 FTM1 Description FTM1 Clock Gate Control This bit controls the clock gate to the FTM1 module. 0 1 24 FTM0 FTM0 Clock Gate Control This bit controls the clock gate to the FTM0 module. 0 1 23 PIT Clock disabled Clock enabled PIT Clock Gate Control This bit controls the clock gate to the PIT module. 0 1 22 PDB Clock disabled Clock enabled Clock disabled Clock enabled PDB Clock Gate Control This bit controls the clock gate to the PDB module. 0 1 Clock disabled Clock enabled 21 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 20-19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18 CRC CRC Clock Gate Control This bit controls the clock gate to the CRC module. 0 1 17-16 Reserved 15 I2S This field is reserved. This read-only field is reserved and always has the value 0. I2S Clock Gate Control This bit controls the clock gate to the I 2 S module. 0 1 14 Reserved 13 SPI1 Clock disabled Clock enabled Clock disabled Clock enabled This field is reserved. This read-only field is reserved and always has the value 0. SPI1 Clock Gate Control This bit controls the clock gate to the SPI1 module. 0 1 Clock disabled Clock enabled Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 263 Memory map and register definition SIM_SCGC6 field descriptions (continued) Field 12 SPI0 Description SPI0 Clock Gate Control This bit controls the clock gate to the SPI0 module. 0 1 Clock disabled Clock enabled 11 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 10 LPUART0 LPUART0 Clock Gate Control This bit controls the clock gate to the LPUART0 module. 0 1 Clock disabled Clock enabled 9 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7 ADC1 ADC1 Clock Gate Control This bit controls the clock gate to the ADC1 module. 0 1 Clock disabled Clock enabled 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3-2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 DMAMUX DMA Mux Clock Gate Control This bit controls the clock gate to the DMA Mux module. 0 1 0 FTF Clock disabled Clock enabled Flash Memory Clock Gate Control This bit controls the clock gate to the flash memory. Flash reads are still supported while the flash memory is clock gated, but entry into low power modes and HSRUN mode is blocked. 0 1 Clock disabled Clock enabled K22F Sub-Family Reference Manual, Rev. 4, 08/2016 264 NXP Semiconductors Chapter 12 System Integration Module (SIM) 12.2.12 System Clock Gating Control Register 7 (SIM_SCGC7) Address: 4004_7000h base + 1040h offset = 4004_8040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 DMA 0 0 0 1 0 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SCGC7 field descriptions Field Description 31-4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 DMA DMA Clock Gate Control This bit controls the clock gate to the DMA module. 0 1 0 Reserved Clock disabled Clock enabled This field is reserved. This read-only field is reserved and always has the value 0. 12.2.13 System Clock Divider Register 1 (SIM_CLKDIV1) When updating CLKDIV1, update all fields using the one write command. Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the write to be ignored. The maximum divide ratio that can be programmed between core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide by 8). NOTE The CLKDIV1 register cannot be written to when the device is in VLPR mode. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 265 Memory map and register definition Address: 4004_7000h base + 1044h offset = 4004_8044h Bit R W Reset 31 30 29 28 OUTDIV1 27 26 25 24 23 22 21 20 0 OUTDIV2 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 OUTDIV4 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 1* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* SIM_CLKDIV1 field descriptions Field 31-28 OUTDIV1 Description Clock 1 output divider value This field sets the divide value for the core/system clock from MCGOUTCLK. At the end of reset, it is loaded with either 0000 or 0111 depending on FTF_FOPT[LPBOOT]. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 27-24 OUTDIV2 Divide-by-1. Divide-by-2. Divide-by-3. Divide-by-4. Divide-by-5. Divide-by-6. Divide-by-7. Divide-by-8. Divide-by-9. Divide-by-10. Divide-by-11. Divide-by-12. Divide-by-13. Divide-by-14. Divide-by-15. Divide-by-16. Clock 2 output divider value This field sets the divide value for the bus clock from MCGOUTCLK. At the end of reset, it is loaded with either 0000 or 0111 depending on FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock frequency. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Divide-by-1. Divide-by-2. Divide-by-3. Divide-by-4. Divide-by-5. Divide-by-6. Divide-by-7. Divide-by-8. Divide-by-9. Divide-by-10. Divide-by-11. Divide-by-12. Divide-by-13. Divide-by-14. Divide-by-15. Divide-by-16. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 266 NXP Semiconductors Chapter 12 System Integration Module (SIM) SIM_CLKDIV1 field descriptions (continued) Field Description 23-20 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 19-16 OUTDIV4 Clock 4 output divider value This field sets the divide value for the flash clock from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111 depending on FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock frequency. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Reserved Divide-by-1. Divide-by-2. Divide-by-3. Divide-by-4. Divide-by-5. Divide-by-6. Divide-by-7. Divide-by-8. Divide-by-9. Divide-by-10. Divide-by-11. Divide-by-12. Divide-by-13. Divide-by-14. Divide-by-15. Divide-by-16. This field is reserved. This read-only field is reserved and always has the value 0. 12.2.14 System Clock Divider Register 2 (SIM_CLKDIV2) Address: 4004_7000h base + 1048h offset = 4004_8048h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USBFRAC 0 R USBDIV W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 267 Memory map and register definition SIM_CLKDIV2 field descriptions Field Description 31-4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3-1 USBDIV USB clock divider divisor This field sets the divide value for the fractional clock divider when the MCGFLLCLK, or IRC48M clock is the USB clock source (SOPT2[USBSRC] = 1). Divider output clock = Divider input clock x [ (USBFRAC+1) / (USBDIV+1) ] 0 USBFRAC USB clock divider fraction This field sets the fraction multiply value for the fractional clock divider when the MCGFLLCLK, or IRC48M clock is the USB clock source (SOPT2[USBSRC] = 1). Divider output clock = Divider input clock x [ (USBFRAC+1) / (USBDIV+1) ] 12.2.15 Flash Configuration Register 1 (SIM_FCFG1) Address: 4004_7000h base + 104Ch offset = 4004_804Ch Bit 31 30 29 28 27 0 R 26 25 24 23 22 PFSIZE 21 20 19 18 0 17 16 1 Reset 0* 0* 0* 0* 1* 1* 1* 1* 0* 0* 0* 0* 1* 1* 1* 1* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FLASHDOZE FLASHDIS W 0* 0* 0* 0* 0* 0 R 1 0 W Reset 0* 0* 0* 0* 1* 1* 1* 1* 0* 0* 0* K22F Sub-Family Reference Manual, Rev. 4, 08/2016 268 NXP Semiconductors Chapter 12 System Integration Module (SIM) SIM_FCFG1 field descriptions Field 31-28 Reserved 27-24 PFSIZE Description This field is reserved. This read-only field is reserved and always has the value 0. Program flash size This field specifies the amount of program flash memory available on the device . Undefined values are reserved. 0011 0101 0111 1001 1011 1101 1111 32 KB of program flash memory 64 KB of program flash memory 128 KB of program flash memory 256 KB of program flash memory 512 KB of program flash memory 1024 KB of program flash memory 128 KB of program flash memory 23-20 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 19-16 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 15-12 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 11-8 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 7-2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 FLASHDOZE Flash Doze When set, Flash memory is disabled for the duration of Wait mode. An attempt by the DMA or other bus master to access the Flash when the Flash is disabled will result in a bus error. This bit should be clear during VLP modes. The Flash will be automatically enabled again at the end of Wait mode so interrupt vectors do not need to be relocated out of Flash memory. The wakeup time from Wait mode is extended when this bit is set. 0 1 0 FLASHDIS Flash remains enabled during Wait mode Flash is disabled for the duration of Wait mode Flash Disable Flash accesses are disabled (and generate a bus error) and the Flash memory is placed in a low power state. This bit should not be changed during VLP modes. Relocate the interrupt vectors out of Flash memory before disabling the Flash. 0 1 Flash is enabled Flash is disabled K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 269 Memory map and register definition 12.2.16 Flash Configuration Register 2 (SIM_FCFG2) Address: 4004_7000h base + 1050h offset = 4004_8050h Bit 31 R 0 30 29 28 27 26 25 24 23 MAXADDR0 22 21 20 1 19 18 17 16 MAXADDR1 W Reset 0* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0* 0* 0* 0* 0* 0* 0* 0* 0 R W Reset 0* 0* 0* 0* 0* 0* 0* 0* SIM_FCFG2 field descriptions Field Description 31 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 30-24 MAXADDR0 Max address block 0 This field concatenated with 13 trailing zeros indicates the first invalid address of each program flash block. For example, if MAXADDR0 = 0x20 the first invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0 value for a device with 256 KB program flash in flash block 0. 23 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 22-16 MAXADDR1 Max address block 1 This field equals zero if there is only one program flash block, otherwise it equals the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20 the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be the MAXADDR1 value for a device with 512 KB program flash memory across two flash blocks and no FlexNVM. Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12.2.17 Unique Identification Register High (SIM_UIDH) Address: 4004_7000h base + 1054h offset = 4004_8054h Bit R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UID W Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* K22F Sub-Family Reference Manual, Rev. 4, 08/2016 270 NXP Semiconductors Chapter 12 System Integration Module (SIM) SIM_UIDH field descriptions Field Description UID Unique Identification Unique identification for the device. 12.2.18 Unique Identification Register Mid-High (SIM_UIDMH) Address: 4004_7000h base + 1058h offset = 4004_8058h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UID R W Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* SIM_UIDMH field descriptions Field Description UID Unique Identification Unique identification for the device. 12.2.19 Unique Identification Register Mid Low (SIM_UIDML) Address: 4004_7000h base + 105Ch offset = 4004_805Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UID R W Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* SIM_UIDML field descriptions Field UID Description Unique Identification Unique identification for the device. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 271 Functional description 12.2.20 Unique Identification Register Low (SIM_UIDL) Address: 4004_7000h base + 1060h offset = 4004_8060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UID R W Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* SIM_UIDL field descriptions Field UID Description Unique Identification Unique identification for the device. 12.3 Functional description For more information about the functions of SIM, see the Introduction section. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 272 NXP Semiconductors Chapter 13 Kinetis Flashloader 13.1 Chip-Specific Information This device has various peripherals (UART, I2C, SPI, USB) supported by the Kinetis Flashloader. The next table shows the pads used by the Kinetis Flashloader. Table 13-1. Kinetis Flashloader Peripheral Pinmux Port Signal PTE0 UART1_TX PTE1 UART1_RX PTC10 I2C0_SCL PTC11 I2C0_SDA PTD4 SPI0_PCS PTD5 SPI0_SCK PTD6 SPI0_SOUT PTD7 SPI0_SIN 13.2 Introduction The Kinetis devices that do not have an on-chip ROM are shipped with the preprogrammed Kinetis Flashloader in the on-chip flash memory, for one-time, in-system factory programming. The Kinetis Flashloader's main task is to load a customer firmware image into the flash memory. The image on the flash has 2 programs: flashloader_loader and flashloader. After a device reset, the flashloader_loader program starts its execution first. The flashloader_loader program copies the contents of flashloader image from the flash to the on-chip RAM; the device then switches execution to the flashloader program to execute from RAM. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 273 Introduction For this device, the Kinetis Flashloader can interface with USB, UART, I2C, and SPI peripherals in slave mode and respond to the commands sent by a master (or host) communicating on one of those ports. The host/master can be a firmware-download application running on a PC or an embedded host communicating with the Kinetis Flashloader. Regardless of the host/master (PC or embedded host), the Kinetis Flashloader always uses a command protocol to communicate with that host/master. Commands are provided to write to memory (flash or RAM), erase flash, and get/set flashloader options and property values. The host application can query the set of available commands. This chapter describes Kinetis Flashloader features, functionality, command structure and which peripherals are supported. Features supported by the Kinetis Flashloader : * * * * * * * Supports USB FS, UART, I2C, and SPI peripheral interfaces Automatic detection of the active peripheral UART peripheral with autobaud Common packet-based protocol for all peripherals Packet error detection and retransmission Protection of RAM used by the flashloader while it is running Provides command to read properties of the device, such as flash and RAM size Table 13-2. Commands supported by the Kinetis Flashloader Command Description When flash security is enabled, then this command is Call Runs user application code and returns control to bootloader Not supported Execute Run user application code that never returns control to Not supported the flashloader FillMemory Fill a range of bytes in flash with a word pattern Not supported FlashEraseAll Erase the entire flash array Not supported FlashEraseRegion Erase a range of sectors in flash Not supported FlashProgramOnce Writes data provided in a command packet to a specified range of bytes in the program once field Not supported FlashReadOnce Returns the contents of the program once field by given index and byte count Not supported FlashReadResource Returns the contents of the IFR field or Flash firmware Not supported ID, by given offset, byte count and option WriteMemory Write data to memory Not supported ReadMemory Read data from memory Not supported GetProperty Get the current value of a property Supported Reset Reset the chip Supported SetProperty Attempt to modify a writable property Supported K22F Sub-Family Reference Manual, Rev. 4, 08/2016 274 NXP Semiconductors Chapter 13 Kinetis Flashloader 13.3 Functional Description The following sub-sections describe the Kinetis Flashloader functionality. 13.3.1 Memory Maps While executing, the Kinetis Flashloader uses RAM memory. The Kinetis Flashloader requires a minimum memory space of 32 KB of RAM. For Kinetis devices with less than this amount of on-chip RAM, the Kinetis Flashloader is not available. 13.3.2 Start-up Process As the Kinetis Flashloader begins executing, flashloader operations begin: 1. The flashloader's temporary working area in RAM is initialized. 2. All supported peripherals are initialized. 3. The flashloader waits for communication to begin on a peripheral. * There is no timeout for the active peripheral detection process. * If communication is detected, then all inactive peripherals are shut down, and the command phase is entered. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 275 Functional Description Enter flashloader Was activity detected on USB FS? Yes No Init hardware Was a Ping packet received on UARTn? Init Flash, Property and Memory interfaces Init USB FS UARTn SPIn I2Cn Yes No Was Start byte (0x5A) received on I2Cn? Yes Shutdown unused Peripherals Enter flashloader state machine No Was Start byte (0x5A) received on SPIn? Yes No Figure 13-1. Kinetis Flashloader Start-up Flowchart 13.3.3 Clock Configuration The core runs on the default reset clock (20.9 MHz). After exiting the flashloader, the core sets the clock configuration back to the reset state (and enables the internal 48 MHz reference clock for the USB module). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 276 NXP Semiconductors Chapter 13 Kinetis Flashloader 13.3.4 Flashloader Protocol This section explains the general protocol for the packet transfers between the host and the Kinetis Flashloader. The description includes the transfer of packets for different transactions, such as commands with no data phase and commands with incoming or outgoing data phase. The next section describes various packet types used in a transaction. Each command sent from the host is replied to with a response command. Commands may include an optional data phase: * If the data phase is incoming (from host to flashloader ), then the data phase is part of the original command. * If the data phase is outgoing (from flashloader to host), then the data phase is part of the response command. NOTE In all protocols (described in the next subsections), the Ack sent in response to a Command or Data packet can arrive at any time before, during, or after the Command/Data packet has processed. 13.3.4.1 Command with no data phase The protocol for a command with no data phase contains: * Command packet (from host) * Generic response command packet (to host) Target Host Command ACK Process command Response ACK Figure 13-2. Command with No Data Phase K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 277 Functional Description 13.3.4.2 Command with incoming data phase The protocol for a command with an incoming data phase contains: * Command packet (from host) * Generic response command packet (to host) * Incoming data packets (from host) * Generic response command packet (to host) Target Host Command ACK Process command Initial Response ACK Data packet Process data ACK Final data packet ACK Process data Final Response ACK Figure 13-3. Command with incoming data phase K22F Sub-Family Reference Manual, Rev. 4, 08/2016 278 NXP Semiconductors Chapter 13 Kinetis Flashloader * * * * NOTE The host may not send any further packets while it (the host) is waiting for the response to a command. If the Generic Response packet prior to the start of the data phase does not have a status of kStatus_Success, then the data phase is aborted. Data phases may be aborted by the receiving side by sending the final Generic Response early with a status of kStatus_AbortDataPhase. The host may abort the data phase early by sending a zero-length data packet. The final Generic Response packet sent after the data phase includes the status for the entire operation. 13.3.4.3 Command with outgoing data phase The protocol for a command with an outgoing data phase contains: * Command packet (from host) * ReadMemory Response command packet (to host) (kCommandFlag_HasDataPhase set) * Outgoing data packets (to host) * Generic response command packet (to host) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 279 Functional Description Target Host Command ACK Process command Initial Response ACK Data packet Process data ACK Final data packet Process data ACK Final Response ACK Figure 13-4. Command with outgoing data phase NOTE * For the outgoing data phase sequence above, the data phase is really considered part of the response command. * The host may not send any further packets while it (the host) is waiting for the response to a command. * If the ReadMemory Response command packet prior to the start of the data phase does not contain the kCommandFlag_HasDataPhase flag, then the data phase is aborted. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 280 NXP Semiconductors Chapter 13 Kinetis Flashloader * Data phases may be aborted by the host sending the final Generic Response early with a status of kStatus_AbortDataPhase. The sending side may abort the data phase early by sending a zero-length data packet. * The final Generic Response packet sent after the data phase includes the status for the entire operation. 13.3.5 Flashloader Packet Types The Kinetis Flashloader device works in slave mode. All data communication is initiated by a host, which is either a PC or an embedded host . The Kinetis Flashloader device is the target, which receives a command or data packet. All data communication between host and target is packetized. NOTE The term "target" refers to the "Kinetis Flashloader device." There are 6 types of packets used in the device: * Ping packet * Ping Response packet * Framing packet * Command packet * Data packet * Response packet All fields in the packets are in little-endian byte order. 13.3.5.1 Ping packet The Ping packet is the first packet sent from a host to the target (Kinetis Flashloader), to establish a connection on a selected peripheral. For a UART peripheral, the Ping packet is used to determine the baudrate. A Ping packet must be sent before any other communications. In response to a Ping packet, the target sends a Ping Response packet. Table 13-3. Ping Packet Format Byte # Value Name 0 0x5A start byte 1 0xA6 ping K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 281 Functional Description Target Host Ping Packet 0x5a 0xa6 Target executes UART autobaud if necessary PingResponse Packet: 0x5a 0xa7 0x00 0x02 0x01 0x50 0x00 0x00 0xaa 0xea Figure 13-5. Ping Packet Protocol Sequence 13.3.5.2 Ping Response Packet The target (Kinetis Flashloader) sends a Ping Response packet back to the host after receiving a Ping packet. If communication is over a UART peripheral, the target uses the incoming Ping packet to determine the baud rate before replying with the Ping Response packet. Once the Ping Response packet is received by the host, the connection is established, and the host starts sending commands to the target (Kinetis Flashloader). Table 13-4. Ping Response Packet Format Byte # Value Parameter 0 0x5A start byte 1 0xA7 Ping response code 2 Protocol bugfix 3 Protocol minor 4 Protocol major 5 Protocol name = 'P' (0x50) 6 Options low 7 Options high 8 CRC16 low 9 CRC16 high K22F Sub-Family Reference Manual, Rev. 4, 08/2016 282 NXP Semiconductors Chapter 13 Kinetis Flashloader 13.3.5.3 Framing Packet The framing packet is used for flow control and error detection, and it (the framing packet) wraps command and data packets as well. The framing packet described in this section is used for serial peripherals including UART, I2C and SPI. The USB HID peripheral does not use framing packets. Instead, the packetization inherent in the USB protocol itself is used. Please refer to the USB peripheral section for details. Table 13-5. Framing Packet Format Byte # Value 0 0x5A Parameter start byte 1 packetType 2 length_low 3 length_high 4 crc16_low 5 crc16_high 6 . . .n Length is a 16-bit field that specifies the entire command or data packet size in bytes. This is a 16-bit field. The CRC16 value covers entire framing packet, including the start byte and command or data packets, but does not include the CRC bytes. See the CRC16 algorithm after this table. Command or Data packet payload A special framing packet that contains only a start byte and a packet type is used for synchronization between the host and target. Table 13-6. Special Framing Packet Format Byte # Value Parameter 0 0x5A start byte 1 0xAn packetType The Packet Type field specifies the type of the packet from one of the defined types (below): Table 13-7. packetType Field packetType Name Description 0xA1 kFramingPacketType_Ack The previous packet was received successfully; the sending of more packets is allowed. 0xA2 kFramingPacketType_Nak The previous packet was corrupted and must be re-sent. 0xA3 kFramingPacketType_AckAbort Data phase is being aborted. 0xA4 kFramingPacketType_Command The framing packet contains a command packet payload. 0xA5 kFramingPacketType_Data The framing packet contains a data packet payload. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 283 Functional Description Table 13-7. packetType Field (continued) packetType Name Description 0xA6 kFramingPacketType_Ping Sent to verify the other side is alive. Also used for UART autobaud. 0xA7 kFramingPacketType_PingResponse A response to Ping; contains the framing protocol version number and options. 13.3.5.4 Command packet The command packet carries a 32-bit command header and a list of 32-bit parameters. Table 13-8. Command Packet Format Command Packet Format (32 bytes) Command Header (4 bytes) 28 bytes for Parameters (Max 7 parameters) Tag Flags Rsvd Param Param1 Count (32-bit) byte 0 byte 1 byte 2 byte 3 Param2 (32-bit) Param3 (32-bit) Param4 (32-bit) Param5 (32-bit) Param6 (32-bit) Param7 (32-bit) Table 13-9. Command Header Format Byte # Command Header Field 0 Command or Response tag 1 Flags 2 Reserved. Should be 0x00. 3 ParameterCount The command header is 4 bytes long, with these fields. The header is followed by 32-bit parameters up to the value of the ParameterCount field specified in the header. Because a command packet is 32 bytes long, only 7 parameters can fit into the command packet. Command packets are also used by the target to send responses back to the host. As mentioned earlier, command packets and data packets are embedded into framing packets for all of the transfers. Table 13-10. Commands that are supported Command Name 0x01 FlashEraseAll 0x02 FlashEraseRegion 0x03 ReadMemory 0x04 WriteMemory Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 284 NXP Semiconductors Chapter 13 Kinetis Flashloader Table 13-10. Commands that are supported (continued) Command Name 0x05 FillMemory 0x06 Reserved 0x07 GetProperty 0x08 Reserved 0x09 Execute 0x0A Call 0x0B Reset 0x0C SetProperty 0x0D Reserved 0x0E FlashProgramOnce 0x0F FlashReadOnce 0x10 FlashReadResource 0x11 Reserved Table 13-11. Responses that are supported Response Name 0xA0 GenericResponse 0xA3 ReadMemoryResponse (used for sending responses to ReadMemory command only) 0xA7 GetPropertyResponse (used for sending responses to GetProperty command only) 0xAF FlashReadOnceResponse (used for sending responses to FlashReadOnce command only) 0xB0 FlashReadResourceResponse (used for sending responses to FlashReadResource command only) Flags: Each command packet contains a Flag byte. Only bit 0 of the flag byte is used. If bit 0 of the flag byte is set to 1, then data packets will follow in the command sequence. The number of bytes that will be transferred in the data phase is determined by a command-specific parameter in the parameters array. ParameterCount: The number of parameters included in the command packet. Parameters: The parameters are word-length (32 bits). With the default maximum packet size of 32 bytes, a command packet can contain up to 7 parameters. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 285 Functional Description 13.3.5.5 Data packet The data packet carries just the data, either host sending data to target, or target sending data to host. The data transfer direction is determined by the last command sent from the host. The data packet is also wrapped within a framing packet, to ensure the correct packet data is received. The contents of a data packet are simply the data itself. There are no other fields, so that the most data per packet can be transferred. Framing packets are responsible for ensuring that the correct packet data is received. 13.3.5.6 Response packet The responses are carried using the same command packet format wrapped with framing packet data. Types of responses include: * GenericResponse * GetPropertyResponse * ReadMemoryResponse * FlashReadOnceResponse * FlashReadResourceResponse GenericResponse: After the Kinetis Flashloader has processed a command, the flashloader will send a generic response with status and command tag information to the host. The generic response is the last packet in the command protocol sequence. The generic response packet contains the framing packet data and the command packet data (with generic response tag = 0xA0) and a list of parameters (defined in the next section). The parameter count field in the header is always set to 2, for status code and command tag parameters. Table 13-12. GenericResponse Parameters Byte # Parameter Descripton 0-3 Status code The Status codes are errors encountered during the execution of a command by the target (Kinetis Flashloader). If a command succeeds, then a kStatus_Success code is returned. Table 13-47, Kinetis Flashloader Status Error Codes, lists the status codes returned to the host by the Kinetis Flashloader. 4-7 Command tag The Command tag parameter identifies the response to the command sent by the host. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 286 NXP Semiconductors Chapter 13 Kinetis Flashloader GetPropertyResponse: The GetPropertyResponse packet is sent by the target in response to the host query that uses the GetProperty command. The GetPropertyResponse packet contains the framing packet data and the command packet data, with the command/response tag set to a GetPropertyResponse tag value (0xA7). The parameter count field in the header is set to greater than 1, to always include the status code and one or many property values. Table 13-13. GetPropertyResponse Parameters Byte # Value Parameter 0-3 Status code 4-7 Property value ... ... Can be up to maximum 6 property values, limited to the size of the 32-bit command packet and property type. ReadMemoryResponse: The ReadMemoryResponse packet is sent by the target in response to the host sending a ReadMemory command. The ReadMemoryResponse packet contains the framing packet data and the command packet data, with the command/response tag set to a ReadMemoryResponse tag value (0xA3), the flags field set to kCommandFlag_HasDataPhase (1). The parameter count set to 2 for the status code and the data byte count parameters shown below. Table 13-14. ReadMemoryResponse Parameters Byte # Parameter Descripton 0-3 Status code The status of the associated Read Memory command. 4-7 Data byte count The number of bytes sent in the data phase. FlashReadOnceResponse:The FlashReadOnceResponse packet is sent by the target in response to the host sending a FlashReadOnce command. The FlashReadOnceResponse packet contains the framing packet data and the command packet data, with the command/response tag set to a FlashReadOnceResponse tag value (0xAF), and the flags field set to 0. The parameter count is set to 2 plus the number of words requested to be read in the FlashReadOnceCommand. Table 13-15. FlashReadOnceResponse Parameters Byte # 0-3 Value Parameter Status Code Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 287 Functional Description Table 13-15. FlashReadOnceResponse Parameters (continued) 4-7 Byte count to read ... ... Can be up to 20 bytes of requested read data. The FlashReadResourceResponse packet is sent by the target in response to the host sending a FlashReadResource command. The FlashReadResourceResponse packet contains the framing packet data and command packet data, with the command/response tag set to a FlashReadResourceResponse tag value (0xB0), and the flags field set to kCommandFlag_HasDataPhase (1). Table 13-16. FlashReadResourceResponse Parameters Byte # Value Parameter 0-3 Status Code 4-7 Data byte count 13.3.6 Flashloader Command API All Kinetis Flashloader command APIs follow the command packet format that is wrapped by the framing packet, as explained in previous sections. * For a list of commands supported by the Flashloader, see Table 13-2, Commands supported. * For a list of status codes returned by the Kinetis Flashloader, see Table 13-47, Kinetis Flashloader Status Error Codes. NOTE All the examples in this section depict byte traffic on serial peripherals that use framing packets. USB HID transactions use the USB HID report packets instead of the serial framing packets shown in this section. Please refer to the HID reports section for details of the USB HID packet structure. 13.3.6.1 Call command The Call command will execute a function that is written in memory at the address sent in the command. The address needs to be a valid memory location residing in accessible flash (internal or external) or in RAM. The command supports the passing of one 32-bit K22F Sub-Family Reference Manual, Rev. 4, 08/2016 288 NXP Semiconductors Chapter 13 Kinetis Flashloader argument. Although the command supports a stack address, at this time the call will still take place using the current stack pointer. After execution of the function, a 32-bit return value will be returned in the generic response message. Table 13-17. Parameters for Call Command Byte # Command 0-3 Call address 4-7 Argument word 8 - 11 Stack pointer Target Host Call: Address=0x00000cd9, arg=0 0x5a a4 0c 00 16 5c 0a 00 00 02 d9 0c 00 00 00 000 000 00 ACK: 0x5a a1 Generic Response: 0x5a a4 0c 00 79 d0 a0 00 00 02 00 00 00 00 0a 00 00 00 ACK: 0x5a a1 Figure 13-6. Protocol Sequence for Call Command Response: The target (Kinetis Flashloader) will return a GenericResponse packet with a status code either set to the return value of the function called or set to kStatus_InvalidArgument (105). 13.3.6.2 GetProperty command The GetProperty command is used to query the flashloader about various properties and settings. Each supported property has a unique 32-bit tag associated with it. The tag occupies the first parameter of the command packet. The target returns a GetPropertyResponse packet with the property values for the property identified with the tag in the GetProperty command. Properties are the defined units of data that can be accessed with the GetProperty or SetProperty commands. Properties may be read-only or read-write. All read-write properties are 32-bit integers, so they can easily be carried in a command parameter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 289 Functional Description For a list of properties and their associated 32-bit property tags supported by the Kinetis Flashloader, see Table 13-43. The 32-bit property tag is the only parameter required for GetProperty command. Table 13-18. Parameters for GetProperty Command Byte # Command 0-3 Property tag Target Host GetProperty: Property tag = 0x01 0x5a a4 08 00 73 d4 07 00 00 01 01 00 00 00 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 0c 00 07 7a a7 00 00 02 00 00 00 00 00 00 01 4b ACK: 0x5a a1 Figure 13-7. Protocol Sequence for GetProperty Command Table 13-19. GetProperty Command Packet Format (Example) GetProperty Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x08 0x00 crc16 0x73 0xD4 commandTag 0x07 - GetProperty flags 0x00 reserved 0x00 parameterCount 0x01 propertyTag 0x00000001 - CurrentVersion The GetProperty command has no data phase. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 290 NXP Semiconductors Chapter 13 Kinetis Flashloader Response: In response to a GetProperty command, the target will send a GetPropertyResponse packet with the response tag set to 0xA7. The parameter count indicates the number of parameters sent for the property values, with the first parameter showing status code 0, followed by the property value(s). The next table shows an example of a GetPropertyResponse packet. Table 13-20. GetProperty Response Packet Format (Example) GetPropertyResponse Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x0c 0x00 (12 bytes) crc16 0x07 0x7a responseTag 0xA7 flags 0x00 reserved 0x00 parameterCount 0x02 status 0x00000000 propertyValue 0x0000014b - CurrentVersion 13.3.6.3 SetProperty command The SetProperty command is used to change or alter the values of the properties or options in the Kinetis Flashloader. However, the SetProperty command can only change the value of properties that are writable--see Table 13-43, Properties used by Get/ SetProperty Commands. If you try to set a value for a read-only property, then the Kinetis Flashloader will return an error. The property tag and the new value to set are the 2 parameters required for the SetProperty command. Table 13-21. Parameters for SetProperty Command Byte # Command 0-3 Property tag 4-7 Property value K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 291 Functional Description Target Host SetProperty: Property tag = 10, Property Value = 1 0x5a a4 0c 00 67 8d 0c 00 00 02 0a 00 00 00 01 00 00 00 ACK : 0x5a a1 Process command GenericResponse: 0x5a a4 00 9e 10 a0 00 0c 02 00 00 00 00 0c 00 00 00 ACK: 0x5a a1 Figure 13-8. Protocol Sequence for SetProperty Command Table 13-22. SetProperty Command Packet Format (Example) SetProperty Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x0C 0x00 crc16 0x67 0x8D commandTag 0x0C - SetProperty with property tag 10 flags 0x00 reserved 0x00 parameterCount 0x02 propertyTag 0x0000000A - VerifyWrites propertyValue 0x00000001 The SetProperty command has no data phase. Response: The target (Kinetis Flashloader) will return a GenericResponse packet with one of following status codes: Table 13-23. SetProperty Response Status Codes Status Code kStatus_Success kStatus_ReadOnly kStatus_UnknownProperty kStatus_InvalidArgument K22F Sub-Family Reference Manual, Rev. 4, 08/2016 292 NXP Semiconductors Chapter 13 Kinetis Flashloader 13.3.6.4 FlashEraseAll command The FlashEraseAll command performs an erase of the entire flash memory. If any flash regions are protected, then the FlashEraseAll command will fail and return an error status code. Executing the FlashEraseAll command will release flash security if it (flash security) was enabled, by setting the FTFA_FSEC register. However, the FSEC field of the flash configuration field is erased, so unless it is reprogrammed, the flash security will be re-enabled after the next system reset. The Command tag for FlashEraseAll command is 0x01 set in the commandTag field of the command packet. The FlashEraseAll command requires no parameters. Target Host FlashEraseAll 0x5a a4 04 00 c4 2e 01 00 00 00 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 0c 00 53 63 a0 00 04 02 00 00 00 00 01 00 00 00 ACK: 0x5a a1 Figure 13-9. Protocol Sequence for FlashEraseAll Command Table 13-24. FlashEraseAll Command Packet Format (Example) FlashEraseAll Parameter Value Framing packet start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x04 0x00 crc16 0xC4 0x2E commandTag 0x01 - FlashEraseAll flags 0x00 reserved 0x00 parameterCount 0x00 Command packet MemoryID * If MemoryID = 0x00h, then internal flash. * If MemoryID = 0x01h, then QSPI0 memory. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 293 Functional Description The FlashEraseAll command has no data phase. Response: The target (Kinetis Flashloader ) will return a GenericResponse packet with status code either set to kStatus_Success for successful execution of the command, or set to an appropriate error status code. 13.3.6.5 FlashEraseRegion command The FlashEraseRegion command performs an erase of one or more sectors of the flash memory or a specified range of flash within the connected SPI flash devices. The start address and number of bytes are the 2 parameters required for the FlashEraseRegion command. The start and byte count parameters must be , or the FlashEraseRegion command will fail and return kStatus_FlashAlignmentError (0x101). If the region specified does not fit in the flash memory space, the FlashEraseRegion command will fail and return kStatus_FlashAddressError (0x102). If any part of the region specified is protected, the FlashEraseRegion command will fail and return kStatus_MemoryRangeInvalid (0x10200). Table 13-25. Parameters for FlashEraseRegion Command Byte # Parameter 0-3 Start address 4-7 Byte count Target Host FlashEraseRegion: startAddress=0, byteCount=1024 0x5a a4 0c 00 f9 a6 02 00 00 00 00 00 00 00 00 04 00 00 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 0c 00 ba 55 a0 00 00 02 00 00 00 00 02 00 00 00 ACK: 0x5a a1 Figure 13-10. Protocol Sequence for FlashEraseRegion Command K22F Sub-Family Reference Manual, Rev. 4, 08/2016 294 NXP Semiconductors Chapter 13 Kinetis Flashloader Table 13-26. FlashEraseRegion Command Packet Format (Example) FlashEraseRegion Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x0C 0x00 crc16 0xF9 0x A6 commandTag 0x02, kCommandTag_FlashEraseRegion flags 0x00 reserved 0x00 parameterCount 0x02 startAddress 0x00 0x00 0x00 0x00 (0x0000_0000) byte count 0x00 0x04 0x00 0x00 (0x400) The FlashEraseRegion command has no data phase. Response: The target (Kinetis Flashloader ) will return a GenericResponse packet with one of following error status codes. Table 13-27. FlashEraseRegion Response Status Codes Status Code kStatus_Success (0x0) kStatus_MemoryRangeInvalid (0x10200) kStatus_FlashAlignmentError (0x101) kStatus_FlashAddressError (0x102) kStatus_FlashAccessError (0x103) kStatus_FlashProtectionViolation (0x104) kStatus_FlashCommandFailure (0x105) 13.3.6.6 FillMemory command The FillMemory command fills a range of bytes in memory with a data pattern. It follows the same rules as the WriteMemory command. The difference between FillMemory and WriteMemory is that a data pattern is included in FillMemory command parameter, and there is no data phase for the FillMemory command, while WriteMemory does have a data phase. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 295 Functional Description Table 13-28. Parameters for FillMemory Command Byte # Command 0-3 Start address of memory to fill 4-7 Number of bytes to write with the pattern * The start address should be 32-bit aligned. * The number of bytes must be evenly divisible by 4. 8 - 11 32-bit pattern * To fill with a byte pattern (8-bit), the byte must be replicated 4 times in the 32-bit pattern. * To fill with a short pattern (16-bit), the short value must be replicated 2 times in the 32-bit pattern. For example, to fill a byte value with 0xFE, the word pattern would be 0xFEFEFEFE; to fill a short value 0x5AFE, the word pattern would be 0x5AFE5AFE. Special care must be taken when writing to flash. * First, any flash sector written to must have been previously erased with a FlashEraseAll or FlashEraseRegion command. * Writing to flash requires the start address to be 32-bit or 64-bit aligned. * If the VerifyWrites property is set to true, then writes to flash will also perform a flash verify program operation. When writing to RAM, the start address need not be aligned, and the data will not be padded. Target Host FillMemory, with word pattern 0x12345678 0x5a a4 10 00 e4 57 05 00 00 03 00 70 00 00 00 08 00 00 78 56 34 12 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 0c 00 97 04 a0 00 00 02 00 00 00 00 05 00 00 00 ACK: 0x5a a1 Figure 13-11. Protocol Sequence for FillMemory Command K22F Sub-Family Reference Manual, Rev. 4, 08/2016 296 NXP Semiconductors Chapter 13 Kinetis Flashloader Table 13-29. FillMemory Command Packet Format (Example) FillMemory Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x10 0x00 crc16 0xE4 0x57 commandTag 0x05 - FillMemory flags 0x00 Reserved 0x00 parameterCount 0x03 startAddress 0x00007000 byteCount 0x00000800 patternWord 0x12345678 The FillMemory command has no data phase. Response: upon successful execution of the command, the target (Kinetis Flashloader) will return a GenericResponse packet with a status code set to kStatus_Success, or to an appropriate error status code. 13.3.6.7 FlashProgramOnce command The FlashProgramOnce command writes data (that is provided in a command packet) to a specified range of bytes in the program once field. Special care must be taken when writing to the program once field. * The program once field only supports programming once, so any attempted to reprogram a program once field will get an error response. * Writing to the program once field requires the byte count to be 4-byte aligned or 8byte aligned. The FlashProgramOnce command uses 3 parameters: index, byteCount, data. Table 13-30. Parameters for FlashProgramOnce Command Byte # Command 0-3 Index of program once field 4-7 Byte count (must be evenly divisible by 4) 8 - 11 Data 12 - 16 Data K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 297 Functional Description Target Host FlashProgramOnce: index=0, byteCount=4, data=0x12345678 0x5a a4 10 00 7e 89 0e 00 00 03 00 00 00 00 04 00 00 00 78 56 34 12 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 0c 00 88 1a a0 00 00 02 00 00 00 00 0e 00 00 00 ACK: 0x5a a1 Figure 13-12. Protocol Sequence for FlashProgramOnce Command Table 13-31. FlashProgramOnce Command Packet Format (Example) FlashProgramOnce Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x10 0x00 crc16 0x7E4 0x89 commandTag 0x0E - FlashProgramOnce flags 0 reserved 0 parameterCount 3 index 0x0000_0000 byteCount 0x0000_0004 data 0x1234_5678 Response: upon successful execution of the command, the target (Kinetis Flashloader) will return a GenericResponse packet with a status code set to kStatus_Success, or to an appropriate error status code. 13.3.6.8 FlashReadOnce command The FlashReadOnce command returns the contents of the program once field by given index and byte count. The FlashReadOnce command uses 2 parameters: index and byteCount. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 298 NXP Semiconductors Chapter 13 Kinetis Flashloader Table 13-32. Parameters for FlashReadOnce Command Byte # Parameter Description 0-3 index Index of the program once field (to read from) 4-7 byteCount Number of bytes to read and return to the caller Target Host FlashReadOnce: index=0, byteCount=4 0x5a a4 0c 00 c1 a5 0f 00 00 02 00 00 00 00 04 00 00 00 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 10 00 3f 6f af 00 00 03 00 00 00 00 04 00 00 00 78 56 34 12 ACK: 0x5a a1 Figure 13-13. Protocol Sequence for FlashReadOnce Command Table 13-33. FlashReadOnce Command Packet Format (Example) FlashReadOnce Parameter Value Framing packet start byte 0x5A packetType 0xA4 length 0x0C 0x00 crc 0xC1 0xA5 commandTag 0x0F - FlashReadOnce flags 0x00 reserved 0x00 parameterCount 0x02 index 0x0000_0000 byteCount 0x0000_0004 Command packet Table 13-34. FlashReadOnce Response Format (Example) FlashReadOnce Response Parameter Value Framing packet start byte 0x5A packetType 0xA4 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 299 Functional Description Table 13-34. FlashReadOnce Response Format (Example) (continued) FlashReadOnce Response Command packet Parameter Value length 0x10 0x00 crc 0x3F 0x6F commandTag 0xAF flags 0x00 reserved 0x00 parameterCount 0x03 status 0x0000_0000 byteCount 0x0000_0004 data 0x1234_5678 Response: upon successful execution of the command, the target (Kinetis Flashloader) will return a FlashReadOnceResponse packet with a status code set to kStatus_Success, a byte count and corresponding data read from Program Once Field upon successful execution of the command, or will return with a status code set to an appropriate error status code and a byte count set to 0. 13.3.6.9 FlashReadResource command The FlashReadResource command returns the contents of the IFR field or Flash firmware ID, by given offset, byte count, and option. The FlashReadResource command uses 3 parameters: start address, byteCount, option. Table 13-35. Parameters for FlashReadResource Command Byte # Parameter Command 0-3 start address Start address of specific non-volatile memory to be read 4-7 byteCount Byte count to be read 8 - 11 option 0: IFR 1: Flash firmware ID K22F Sub-Family Reference Manual, Rev. 4, 08/2016 300 NXP Semiconductors Chapter 13 Kinetis Flashloader Target Host FlashReadResource: start address=0, byteCount=8, option=1 5a a4 10 00 b3 cc 10 00 00 03 00 00 00 00 08 00 00 00 01 00 00 00 ACK: 0x5a a1 Process command FlashReadResource Response 5a a4 0c 00 08 d2 b0 01 00 02 00 00 00 00 08 00 00 00 ACK: 0x5a a1 Data packet 5a a5 08 00 9c d3 00 08 00 00 00 01 00 06 Process Data ACK: 0x5a a1 Generic Response 5a a4 0c 00 75 a3 a0 00 00 02 00 00 00 00 10 00 00 00 ACK: 0x5a a1 Figure 13-14. Protocol Sequence for FlashReadResource Command Table 13-36. FlashReadResource Command Packet Format (Example) FlashReadResource Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4 length 0x10 0x00 crc 0xB3 0xCC commandTag 0x10 - FlashReadResource flags 0x00 reserved 0x00 parameterCount 0x03 startAddress 0x0000_0000 byteCount 0x0000_0008 option 0x0000_0001 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 301 Functional Description Table 13-37. FlashReadResource Response Format (Example) FlashReadResource Response Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4 length 0x0C 0x00 crc 0xD2 0xB0 commandTag 0xB0 flags 0x01 reserved 0x00 parameterCount 0x02 status 0x0000_0000 byteCount 0x0000_0008 Data phase: The FlashReadResource command has a data phase. Because the target (Kinetis Flashloader ) works in slave mode, the host must pull data packets until the number of bytes of data specified in the byteCount parameter of FlashReadResource command are received by the host. 13.3.6.10 WriteMemory command The WriteMemory command writes data provided in the data phase to a specified range of bytes in memory (flash or RAM). However, if flash protection is enabled, then writes to protected sectors will fail. Special care must be taken when writing to flash. * First, any flash sector written to must have been previously erased with a FlashEraseAll or FlashEraseRegion command. * Writing to flash requires the start address to be . * If the VerifyWrites property is set to true, then writes to flash will also perform a flash verify program operation. When writing to RAM, the start address need not be aligned, and the data will not be padded. The start address and number of bytes are the 2 parameters required for WriteMemory command. Table 13-38. Parameters for WriteMemory Command Byte # Command 0-3 Start address 4-7 Byte count K22F Sub-Family Reference Manual, Rev. 4, 08/2016 302 NXP Semiconductors Chapter 13 Kinetis Flashloader Target Host WriteMemory : startAddress = 0x20000400, byteCount = 0x64 0x5a a4 0c 00 06 5a 04 00 00 02 00 04 00 20 64 00 00 00 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 0c 00 a0 0e 04 01 00 02 00 04 00 20 40 00 00 00 ACK: 0x5a a1 Data packet : 0x5a a5 20 00 CRC16 32 bytes data Process Data ACK: 0x5a a1 Final Data packet 0x5a a5 length16 CRC16 32 bytes data Process Data ACK Generic Response 0x5a a4 0c 00 23 72 a0 00 00 02 00 00 00 00 04 00 00 00 ACK: 0x5a a1 Figure 13-15. Protocol Sequence for WriteMemory Command Table 13-39. WriteMemory Command Packet Format (Example) WriteMemory Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x0C 0x00 crc16 0x06 0x5A commandTag 0x04 - writeMemory flags 0x00 reserved 0x00 parameterCount 0x02 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 303 Functional Description Table 13-39. WriteMemory Command Packet Format (Example) (continued) WriteMemory Parameter Value startAddress 0x20000400 byteCount 0x00000064 Data Phase: The WriteMemory command has a data phase; the host will send data packets until the number of bytes of data specified in the byteCount parameter of the WriteMemory command are received by the target. Response: The target (Kinetis Flashloader ) will return a GenericResponse packet with a status code set to kStatus_Success upon successful execution of the command, or to an appropriate error status code. 13.3.6.11 Read memory command The ReadMemory command returns the contents of memory at the given address, for a specified number of bytes. This command can read any region of memory accessible by the CPU and not protected by security. The start address and number of bytes are the 2 parameters required for ReadMemory command. Table 13-40. Parameters for read memory command Byte Parameter 0-3 Start address 4-7 Byte count Description Start address of memory to read from Number of bytes to read and return to caller K22F Sub-Family Reference Manual, Rev. 4, 08/2016 304 NXP Semiconductors Chapter 13 Kinetis Flashloader Target Host readMemory : startAddress = 0x20000400, byteCount = 100 0x5a a4 0c 00 1d 23 03 00 00 02 00 04 00 20 64 00 00 00 ACK: 0x5a a1 Process command Generic response for command: 0x5a a4 0c 00 27 f6 a3 01 00 02 00 00 00 00 64 00 00 00 ACK: 0x5a a1 Data packet : 0x5a a5 20 00 CRC 16 32 bytes data Process Data ACK: 0x5a a1 Final Data packet 0x5a a5 length 16 CRC 16 32 bytes data ACK: 0x5a a1 Process Data Final Generic Response 0x5a a4 0c 00 23 72 a 0 00 00 02 00 00 00 00 04 00 00 00 0x5a a4 0c 00 0e 23 a0 00 00 02 00 00 00 00 03 00 00 00 ACK: 0x5a a1 Figure 13-16. Command sequence for read memory ReadMemory Parameter Framing packet Start byte packetType Command packet Value 0x5A0xA4, kFramingPacketType_Command length 0x0C 0x00 crc16 0x1D 0x23 commandTag 0x03 - readMemory flags 0x00 reserved 0x00 parameterCount 0x02 startAddress 0x20000400 byteCount 0x00000064 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 305 Functional Description Data Phase: The ReadMemory command has a data phase. Since the target (Kinetis Flashloader) works in slave mode, the host need pull data packets until the number of bytes of data specified in the byteCount parameter of ReadMemory command are received by host. Response: The target (Kinetis Flashloader) will return a GenericResponse packet with a status code either set to kStatus_Success upon successful execution of the command, or set to an appropriate error status code. 13.3.6.12 Execute command The execute command results in the flashloader setting the program counter to the code at the provided jump address, R0 to the provided argument, and a Stack pointer to the provided stack pointer address. Prior to the jump, the system is returned to the reset state. The Jump address, function argument pointer, and stack pointer are the parameters required for the Execute command. Table 13-41. Parameters for Execute Command Byte # Command 0-3 Jump address 4-7 Argument word 8 - 11 Stack pointer address The Execute command has no data phase. Response: Before executing the Execute command, the target (Kinetis Flashloader) will validate the parameters and return a GenericResponse packet with a status code either set to kStatus_Success or an appropriate error status code. 13.3.6.13 Reset command The Reset command will result in flashloader resetting the chip. The Reset command requires no parameters. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 306 NXP Semiconductors Chapter 13 Kinetis Flashloader Target Host Reset 0x5a a4 04 00 6f 46 0b 00 00 00 ACK : 0x5a a1 Process command GenericResponse: 0x5a a4 0c 00 f8 0b a 0 00 04 02 00 00 00 00 0b 00 00 00 ACK: 0x5a a1 Figure 13-17. Protocol Sequence for Reset Command Table 13-42. Reset Command Packet Format (Example) Reset Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x04 0x00 crc16 0x6F 0x46 commandTag 0x0B - reset flags 0x00 reserved 0x00 parameterCount 0x00 The Reset command has no data phase. Response: The target (Kinetis Flashloader) will return a GenericResponse packet with status code set to kStatus_Success, before resetting the chip. 13.4 Peripherals Supported This section describes the peripherals supported by the Kinetis Flashloader. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 307 Peripherals Supported 13.4.1 I2C Peripheral The Kinetis Flashloader supports loading data into flash via the I2C peripheral, where the I2C peripheral serves as the I2C slave. A 7-bit slave address is used during the transfer. The Kinetis Flashloader uses 0x10 as the I2C slave address, and supports 400 kbps as the I2C baud rate. Because the I2C peripheral serves as an I2C slave device, each transfer should be started by the host, and each outgoing packet should be fetched by the host. * An incoming packet is sent by the host with a selected I2C slave address and the direction bit is set as write. * An outgoing packet is read by the host with a selected I2C slave address and the direction bit is set as read. * 0x00 will be sent as the response to host if the target is busy with processing or preparing data. The following flow charts demonstrate the communication flow of how the host reads ping packet, ACK and response from the target. Fetch Ping response End Read 1 byte from target Read leftover bytes of ping response packet No Yes 0x5A received? Yes Read 1 byte from target 0x7A received? Report Error No Figure 13-18. Host reads ping response from target via I2C K22F Sub-Family Reference Manual, Rev. 4, 08/2016 308 NXP Semiconductors Chapter 13 Kinetis Flashloader Fetch ACK Report an error No Read 1 byte from target No Process NAK 0xA2 received? Yes No Reached maximum retries? 0x5A received? No Yes Read 1 byte from target 0xA1 received? Yes Yes Report a timeout error End Figure 13-19. Host reads ACK packet from target via I2C Fetch Response Read 1 byte from target No Reached maximum retries? End No Read payload data from target 0x5A received? Yes Yes Payload length less than supported length? Read 1 byte from target Yes Report a timeout error (End) 0xA4 received? Yes Read payload length part from target (2 bytes) No Set payload length to maximum supported length Read CRC checksum from target (2 bytes) No Figure 13-20. Host reads response from target via I2C 13.4.2 SPI Peripheral The Kinetis Flashloader supports loading data into flash via the SPI peripheral, where the SPI peripheral serves as a SPI slave. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 309 Peripherals Supported The Kinetis Flashloader supports 400 kbps as the SPI baud rate. The SPI peripheral uses the following bus attributes: * Clock Phase = 1 (Second Edge) * Clock Polarity = 1 (Active Low) Because the SPI peripheral serves as a SPI slave device, each transfer should be started by the host, and each outgoing packet should be fetched by the host. The transfer on SPI is slightly different from I2C: * Host will receive 1 byte after it sends out any byte. * Received bytes should be ignored when host is sending out bytes to target * Host starts reading bytes by sending 0x00s to target * The byte 0x00 will be sent as response to host if target is under the following conditions: * Processing incoming packet * Preparing outgoing data * Received invalid data The SPI bus configuration is: * Phase = 1; data is sampled on rising edges * Polarity = 1; idle is high * MSB is transmitted first For any transfer where the target does not have actual data to send, the target (slave) is responsible for ensuring that 0x00 bytes will be returned to the host (master). The host uses framing packets to identify real data and not "dummy" 0x00 bytes (which do not have framing packets). The following flowcharts demonstrate how the host reads a ping response, an ACK and a command response from target via SPI. Fetch Ping response End Send 0x00 to shift out 1 byte from target Send 0x00s to shift out leftover bytes of ping response No Yes 0x5A received? Yes Send 0x00 to shift out 1 byte from target 0xA7 received? No Report Error Figure 13-21. Host reads ping packet from target via SPI K22F Sub-Family Reference Manual, Rev. 4, 08/2016 310 NXP Semiconductors Chapter 13 Kinetis Flashloader Report an error Fetch ACK No Send 0x00 to shift out 1 byte from target No Process NAK 0xA2 received? Yes No Reached maximum retries? No 0x5A received? Yes Yes Report a timeout error Send 0x00 to shift out 1 byte from target 0xA1 received? Yes Next action Figure 13-22. Host reads ACK from target via SPI Fetch Response Send 0x00 to shift out 1 byte from target No Reached maximum retries? End No Write 0x00s to shift out payload data from target 0x5A received? Yes Yes Payload length less than supported length? Send 0x00 to shift out 1 byte from target Yes Report a timeout error (End) 0xA4 received? Yes Write 0x00s to shift out payload length part from target (2 bytes) No Set payload length to maximum supported length Write 0x00s to shift out CRC checksum from target (2 bytes) No Figure 13-23. Host reads response from target via SPI 13.4.3 UART Peripheral The Kinetis Flashloader integrates an autobaud detection algorithm for the UART peripheral, thereby providing flexible baud rate choices. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 311 Peripherals Supported Autobaud feature: If UARTn is used to connect to the flashloader, then the UARTn_RX pin must be kept high and not left floating during the detection phase in order to comply with the autobaud detection algorithm. After the flashloader detects the ping packet (0x5A 0xA6) on UARTn_RX, the flashloader firmware executes the autobaud sequence. If the baudrate is successfully detected, then the flashloader will send a ping packet response [(0x5A 0xA7), protocol version (4 bytes), protocol version options (2 bytes) and crc16 (2 bytes)] at the detected baudrate. The Kinetis Flashloader then enters a loop, waiting for flashloader commands via the UART peripheral. NOTE * The autobaud feature requires a ping packet with a higher accuracy (+/-3%), or the ping packet will be ignored as noise. * The data bytes of the ping packet must be sent continuously (with no more than 80 ms between bytes) in a fixed UART transmission mode (8-bit data, no parity bit and 1 stop bit). If the bytes of the ping packet are sent one-by-one with more than 80 ms delay between them, then the autobaud detection algorithm may calculate an incorrect baud rate. In this case, the autobaud detection state machine should be reset. Supported baud rates: The baud rate is closely related to the MCU core and system clock frequencies. Typical baud rates supported are 9600, 19200, 38400, 57600, and 115200. Packet transfer: After autobaud detection succeeds, flashloader communications can take place over the UART peripheral. The following flow charts show: * How the host detects an ACK from the target * How the host detects a ping response from the target * How the host detects a command response from the target K22F Sub-Family Reference Manual, Rev. 4, 08/2016 312 NXP Semiconductors Chapter 13 Kinetis Flashloader Wait for ACK Report an error No Wait for 1 byte from target No Process NAK Yes 0xA2 received? No Reached maximum retries? 0x5A received? No Yes Wait for 1 byte from target 0xA1 received? Yes Yes End Report a timeout error Figure 13-24. Host reads an ACK from target via UART Wait for ping response End Wait for remaining bytes of ping response packet Wait for 1 byte from target No Yes 0x5A received? Yes Wait for 1 byte from target 0xA7 received? No Report Error Figure 13-25. Host reads a ping response from target via UART K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 313 Peripherals Supported Wait for response Wait for 1 byte from target No Reached maximum retries? End No Wait for payload data from target 0x5A received? Yes Yes Yes Wait for 1 byte from target Report a timeout error (End) 0xA4 received? Payload length less than supported length? Yes Wait for payload length part from target (2 bytes) No Set payload length to maximum supported length Wait for CRC checksum from target (2 bytes) No Figure 13-26. Host reads a command response from target via UART 13.4.4 USB peripheral The Kinetis Flashloader supports loading data into flash via the USB peripheral. The target is implemented as a USB HID class. USB HID does not use framing packets; instead the packetization inherent in the USB protocol itself is used. The ability for the device to NAK Out transfers (until they can be received) provides the required flow control; the built-in CRC of each USB packet provides the required error detection. 13.4.4.1 Clock configuration The flashloader supports the crystal-less USB feature. If the USB peripheral is enabled, then the flashloader enables the 48-MHz IRC. The flashloader also enables the USB clock recovery feature (by setting USBx_CLK_RECOVER_CTRL[CLOCK_RECOVER_EN] to 1 and USB_CLK_RECOVER_IRC_EN[IRC_EN] to 1). 13.4.4.2 Device descriptor The Kinetis flashloader configures the default USB VID/PID/Strings as below: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 314 NXP Semiconductors Chapter 13 Kinetis Flashloader Default VID/PID: * VID = 0x15A2 * PID = 0x0073 Default Strings: * Manufacturer [1] = "Freescale Semiconductor Inc." (Note that Freescale Semiconductor is now NXP Semiconductors.) * Product [2] = "Kinetis Bootloader" 13.4.4.3 Endpoints The HID peripheral uses 3 endpoints: * Control (0) * Interrupt IN (1) * Interrupt OUT (2) The Interrupt OUT endpoint is optional for HID class devices, but the Kinetis Flashloader uses it as a pipe, where the firmware can NAK send requests from the USB host. 13.4.4.4 HID reports There are 4 HID reports defined and used by the flashloader USB HID peripheral. The report ID determines the direction and type of packet sent in the report; otherwise, the contents of all reports are the same. Report ID Packet Type Direction 1 Command OUT 2 Data OUT 3 Command IN 4 Data IN For all reports, these properties apply: Usage Min 1 Usage Max 1 Logical Min 0 Logical Max 255 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 315 Get/SetProperty Command Properties Report Size 8 Report Count 34 Each report has a maximum size of 34 bytes. This is derived from the minimum flashloader packet size of 32 bytes, plus a 2-byte report header that indicates the length (in bytes) of the packet sent in the report. NOTE In the future, the maximum report size may be increased, to support transfers of larger packets. Alternatively, additional reports may be added with larger maximum sizes. The actual data sent in all of the reports looks like: 0 Report ID 1 Packet Length LSB 2 Packet Length MSB 3 Packet[0] 4 Packet[1] 5 Packet[2] ... N+3-1 Packet[N-1] This data includes the Report ID, which is required if more than one report is defined in the HID report descriptor. The actual data sent and received has a maximum length of 35 bytes. The Packet Length header is written in little-endian format, and it is set to the size (in bytes) of the packet sent in the report. This size does not include the Report ID or the Packet Length header itself. During a data phase, a packet size of 0 indicates a data phase abort request from the receiver. 13.5 Get/SetProperty Command Properties This section lists the properties of the GetProperty and SetProperty commands. Table 13-43. Properties used by Get/SetProperty Commands, sorted by Value Property Writable Tag Value Size Description CurrentVersion No 01h 4 Current flashloader version. AvailablePeripherals No 02h 4 The set of peripherals supported on this chip. FlashStartAddress No 03h 4 Start address of program flash. FlashSizeInBytes No 04h 4 Size in bytes of program flash. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 316 NXP Semiconductors Chapter 13 Kinetis Flashloader Table 13-43. Properties used by Get/SetProperty Commands, sorted by Value (continued) Property Writable Tag Value Size Description FlashSectorSize No 05h 4 The size in bytes of one sector of program flash. FlashBlockCount No 06h 4 Number of blocks in the flash array. AvailableCommands No 07h 4 The set of commands supported by the flashloader. VerifyWrites Yes 0Ah 4 Controls whether the flashloader will verify writes to flash. VerifyWrites feature is enabled by default. This is the minimum erase size. 0 - No verification is done. 1 - Enable verification. MaxPacketSize No 0Bh 4 Maximum supported packet size for the currently active peripheral interface. ReservedRegions No 0Ch 16 List of memory regions reserved by the flashloader. Returned as value pairs (<start-address-of-region>, <end-address-of-region>). * If HasDataPhase flag is not set, then the Response packet parameter count indicates the number of pairs. * If HasDataPhase flag is set, then the second parameter is the number of bytes in the data phase. RAMStartAddress No 0Eh 4 Start address of RAM segment. The first parameter to GetProperty command identifies the segment. See the device specific memory map for number of RAM segments the device contains. RAMSizeInBytes No 0Fh 4 Size in bytes of RAM segment. The first parameter to GetProperty command identifies the segment. See the device specific memory map for number of RAM segments the device contains. SystemDeviceId No 10h 4 Value of the Kinetis System Device Identification register. FlashSecurityState No 11h 4 Indicates whether Flash security is enabled 0 - Flash security is disabled 1 - Flash security is enabled UniqueDeviceId No 12h 16 Unique device identification, value of Kinetis Unique Identification registers (16 for K series devices, 12 for KL series devices) 13.5.1 Property Definitions Get/Set property definitions are provided in this section. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 317 Get/SetProperty Command Properties 13.5.1.1 CurrentVersion Property The value of this property is a 4-byte structure containing the current version of the flashloader. Table 13-44. Fields of CurrentVersion property: Bits [31:24] [23:16] [15:8] [7:0] Field Name = 'K' (0x4B) Major version Minor version Bugfix version 13.5.1.2 AvailablePeripherals Property The value of this property is a bitfield that lists the peripherals supported by the flashloader and the hardware on which it is running. Table 13-45. Peripheral bits: Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Peripheral Reserved Reserved Reserved USB HID Reserved SPI Slave I2C Slave UART If the peripheral is available, then the corresponding bit will be set in the property value. All reserved bits must be set to 0. 13.5.1.3 AvailableCommands Property This property value is a bitfield with set bits indicating the commands enabled in the flashloader. Only commands that can be sent from the host to the target are listed in the bitfield. Response commands such as GenericResponse are excluded. The bit number that identifies whether a command is present is the command's tag value minus 1. 1 is subtracted from the command tag because the lowest command tag value is 0x01. To get the bit mask for a given command, use this expression: mask = 1 << (tag - 1) Table 13-46. Command bits: Bit [31: [17] [16] [15] [14] [13] [12] [11] [10] 18] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 318 NXP Semiconductors Chapter 13 Kinetis Flashloader FlashEraseAll FlashEraseRegion ReadMemory WriteMemory FillMemory Reserved GetProperty Reserved Execute Call Reset SetProperty Reserved FlashProgramOnce FlashReadOnce FlashReadResource Reserved Reserved Command Reserved Table 13-46. Command bits: (continued) 13.6 Kinetis Flashloader Status Error Codes This section describes the status error codes that the Kinetis Flashloader returns to the host. Table 13-47. Kinetis Flashloader Status Error Codes, sorted by Value Error Code Value Description kStatus_Success 0 Operation succeeded without error. kStatus_Fail 1 Operation failed with a generic error. kStatus_ReadOnly 2 Requested value cannot be changed because it is read-only. kStatus_OutOfRange 3 Requested value is out of range. kStatus_InvalidArgument 4 The requested command's argument is undefined. kStatus_Timeout 5 A timeout occurred. kStatus_FlashSizeError 100 Not used. kStatus_FlashAlignmentError 101 Address or length does not meet required alignment. kStatus_FlashAddressError 102 Address or length is outside addressable memory. kStatus_FlashAccessError 103 The FTFA_FSTAT[ACCERR] bit is set. kStatus_FlashProtectionViolation 104 The FTFA_FSTAT[FPVIOL] bit is set. kStatus_FlashCommandFailure 105 The FTFA_FSTAT[MGSTAT0] bit is set. kStatus_FlashUnknownProperty 106 Unknown Flash property. kStatus_FlashEraseKeyError 107 The key provided does not match the programmed flash key. kStatus_FlashRegionExecuteOnly 108 The area of flash is protected as execute only. kStatus_I2C_SlaveTxUnderrun 200 I2C Slave TX Underrun error. kStatus_I2C_SlaveRxOverrun 201 I2C Slave RX Overrun error. kStatus_I2C_AribtrationLost 202 I2C Arbitration Lost error. kStatus_SPI_SlaveTxUnderrun 300 SPI Slave TX Underrun error. kStatus_SPI_SlaveRxOverrun 301 SPI Slave RX Overrun error. kStatus_SPI_Timeout 302 SPI tranfser timed out. kStatus_SPI_Busy 303 SPI instance is already busy performing a transfer. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 319 Kinetis Flashloader Status Error Codes Table 13-47. Kinetis Flashloader Status Error Codes, sorted by Value (continued) Error Code kStatus_SPI_NoTransferInProgress Value 304 Description Attempt to abort a transfer when no transfer was in progress. kStatus_UnknownCommand 10000 The requested command value is undefined. kStatus_SecurityViolation 10001 Command is disallowed because flash security is enabled. kStatus_AbortDataPhase 10002 Abort the data phase early. kStatusMemoryRangeInvalid 10200 Memory range conflicts with a protected region. kStatus_UnknownProperty 10300 The requested property value is undefined. kStatus_ReadOnlyProperty 10301 The requested property value cannot be written. kStatus_InvalidPropertyValue 10302 The specified property value is invalid. kStatus_AppCrcCheckPassed 10400 CRC check is valid and passed. kStatus_AppCrcCheckFailed 10401 CRC check is valid but failed. kStatus_AppCrcCheckInactive 10402 CRC check is inactive. kStatus_AppCrcCheckInvalid 10403 CRC check is invalid, because the BCA is invalid or the CRC parameters are unset (all 0xFF bytes). kStatus_AppCrcCheckOutOfRange 10404 CRC check is valid but addresses are out of range. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 320 NXP Semiconductors Chapter 14 Reset Control Module (RCM) 14.1 Introduction Information found here describes the registers of the Reset Control Module (RCM). The RCM implements many of the reset functions for the chip. See the chip's reset chapter for more information. See AN4503: Power Management for Kinetis MCUs for further details on using the RCM. 14.2 Reset memory map and register descriptions The RCM Memory Map/Register Definition can be found here. The Reset Control Module (RCM) registers provide reset status information and reset filter control. NOTE The RCM registers can be written only in supervisor mode. Write accesses in user mode are blocked and will result in a bus error. RCM memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4007_F000 System Reset Status Register 0 (RCM_SRS0) 8 R 82h 14.2.1/322 4007_F001 System Reset Status Register 1 (RCM_SRS1) 8 R 00h 14.2.2/323 4007_F004 Reset Pin Filter Control register (RCM_RPFC) 8 R/W 00h 14.2.3/325 4007_F005 Reset Pin Filter Width register (RCM_RPFW) 8 R/W 00h 14.2.4/326 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 321 Reset memory map and register descriptions RCM memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_F007 Mode Register (RCM_MR) 8 R 00h 14.2.5/327 4007_F008 Sticky System Reset Status Register 0 (RCM_SSRS0) 8 R/W 82h 14.2.6/328 4007_F009 Sticky System Reset Status Register 1 (RCM_SSRS1) 8 R/W 00h 14.2.7/329 14.2.1 System Reset Status Register 0 (RCM_SRS0) This register includes read-only status flags to indicate the source of the most recent reset. The reset state of these bits depends on what caused the MCU to reset. NOTE The reset value of this register depends on the reset source: * POR (including LVD) -- 0x82 * LVD (without POR) -- 0x02 * VLLS mode wakeup due to RESET pin assertion -- 0x41 * VLLS mode wakeup due to other wakeup sources -- 0x01 * Other reset -- a bit is set if its corresponding reset source caused the reset Address: 4007_F000h base + 0h offset = 4007_F000h Bit Read 7 6 5 POR PIN WDOG 1 0 0 4 3 0 2 1 0 LOC LVD WAKEUP 0 1 0 Write Reset 0 0 RCM_SRS0 field descriptions Field 7 POR Description Power-On Reset Indicates a reset has been caused by the power-on detection logic. Because the internal supply voltage was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while the internal supply was below the LVD threshold. 0 1 6 PIN Reset not caused by POR Reset caused by POR External Reset Pin Indicates a reset has been caused by an active-low level on the external RESET pin. 0 1 Reset not caused by external reset pin Reset caused by external reset pin Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 322 NXP Semiconductors Chapter 14 Reset Control Module (RCM) RCM_SRS0 field descriptions (continued) Field 5 WDOG Description Watchdog Indicates a reset has been caused by the watchdog timer timing out. This reset source can be blocked by disabling the watchdog. 0 1 4-3 Reserved 2 LOC This field is reserved. This read-only field is reserved and always has the value 0. Loss-of-Clock Reset Indicates a reset has been caused by a loss of external clock. The MCG clock monitor must be enabled for a loss of clock to be detected. Refer to the detailed MCG description for information on enabling the clock monitor. 0 1 1 LVD Reset not caused by a loss of external clock. Reset caused by a loss of external clock. Low-Voltage Detect Reset If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This field is also set by POR. 0 1 0 WAKEUP Reset not caused by watchdog timeout Reset caused by watchdog timeout Reset not caused by LVD trip or POR Reset caused by LVD trip or POR Low Leakage Wakeup Reset Indicates a reset has been caused by an enabled LLWU module wakeup source while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx mode causes a reset. This bit is cleared by any reset except WAKEUP. 0 1 Reset not caused by LLWU module wakeup source Reset caused by LLWU module wakeup source 14.2.2 System Reset Status Register 1 (RCM_SRS1) This register includes read-only status flags to indicate the source of the most recent reset. The reset state of these bits depends on what caused the MCU to reset. NOTE The reset value of this register depends on the reset source: * POR (including LVD) -- 0x00 * LVD (without POR) -- 0x00 * VLLS mode wakeup -- 0x00 * Other reset -- a bit is set if its corresponding reset source caused the reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 323 Reset memory map and register descriptions Address: 4007_F000h base + 1h offset = 4007_F001h Bit 7 6 5 4 3 2 1 0 Read 0 0 SACKERR EZPT MDM_AP SW LOCKUP JTAG 0 0 0 0 0 0 0 0 Write Reset RCM_SRS1 field descriptions Field Description 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 SACKERR Stop Mode Acknowledge Error Reset Indicates that after an attempt to enter Stop mode, a reset has been caused by a failure of one or more peripherals to acknowledge within approximately one second to enter stop mode. 0 1 4 EZPT EzPort Reset Indicates a reset has been caused by EzPort receiving the RESET command while the device is in EzPort mode. 0 1 3 MDM_AP Indicates a reset has been caused by the host debugger system setting of the System Reset Request bit in the MDM-AP Control Register. Indicates a reset has been caused by software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register in the ARM core. Reset not caused by software setting of SYSRESETREQ bit Reset caused by software setting of SYSRESETREQ bit Core Lockup Indicates a reset has been caused by the ARM core indication of a LOCKUP event. 0 1 0 JTAG Reset not caused by host debugger system setting of the System Reset Request bit Reset caused by host debugger system setting of the System Reset Request bit Software 0 1 1 LOCKUP Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode Reset caused by EzPort receiving the RESET command while the device is in EzPort mode MDM-AP System Reset Request 0 1 2 SW Reset not caused by peripheral failure to acknowledge attempt to enter stop mode Reset caused by peripheral failure to acknowledge attempt to enter stop mode Reset not caused by core LOCKUP event Reset caused by core LOCKUP event JTAG Generated Reset Indicates a reset has been caused by JTAG selection of certain IR codes: EZPORT, EXTEST, HIGHZ, and CLAMP. 0 1 Reset not caused by JTAG Reset caused by JTAG K22F Sub-Family Reference Manual, Rev. 4, 08/2016 324 NXP Semiconductors Chapter 14 Reset Control Module (RCM) 14.2.3 Reset Pin Filter Control register (RCM_RPFC) NOTE The reset values of bits 2-0 are for Chip POR only. They are unaffected by other reset types. NOTE The bus clock filter is reset when disabled or when entering stop mode. The LPO filter is reset when disabled . Address: 4007_F000h base + 4h offset = 4007_F004h Bit Read Write Reset 7 6 5 4 3 0 0 0 0 2 RSTFLTSS 0 0 0 1 0 RSTFLTSRW 0 0 RCM_RPFC field descriptions Field 7-3 Reserved 2 RSTFLTSS Description This field is reserved. This read-only field is reserved and always has the value 0. Reset Pin Filter Select in Stop Mode Selects how the reset pin filter is enabled in Stop and VLPS modes , and also during LLS and VLLS modes. On exit from VLLS mode, this bit should be reconfigured before clearing PMC_REGSC[ACKISO]. 0 1 RSTFLTSRW All filtering disabled LPO clock filter enabled Reset Pin Filter Select in Run and Wait Modes Selects how the reset pin filter is enabled in run and wait modes. 00 01 10 11 All filtering disabled Bus clock filter enabled for normal operation LPO clock filter enabled for normal operation Reserved K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 325 Reset memory map and register descriptions 14.2.4 Reset Pin Filter Width register (RCM_RPFW) NOTE The reset values of the bits in the RSTFLTSEL field are for Chip POR only. They are unaffected by other reset types. Address: 4007_F000h base + 5h offset = 4007_F005h Bit Read Write Reset 7 6 5 4 3 0 0 0 2 1 0 0 0 RSTFLTSEL 0 0 0 0 RCM_RPFW field descriptions Field 7-5 Reserved RSTFLTSEL Description This field is reserved. This read-only field is reserved and always has the value 0. Reset Pin Filter Bus Clock Select Selects the reset pin bus clock filter width. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 Bus clock filter count is 1 Bus clock filter count is 2 Bus clock filter count is 3 Bus clock filter count is 4 Bus clock filter count is 5 Bus clock filter count is 6 Bus clock filter count is 7 Bus clock filter count is 8 Bus clock filter count is 9 Bus clock filter count is 10 Bus clock filter count is 11 Bus clock filter count is 12 Bus clock filter count is 13 Bus clock filter count is 14 Bus clock filter count is 15 Bus clock filter count is 16 Bus clock filter count is 17 Bus clock filter count is 18 Bus clock filter count is 19 Bus clock filter count is 20 Bus clock filter count is 21 Bus clock filter count is 22 Bus clock filter count is 23 Bus clock filter count is 24 Bus clock filter count is 25 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 326 NXP Semiconductors Chapter 14 Reset Control Module (RCM) RCM_RPFW field descriptions (continued) Field Description 11001 11010 11011 11100 11101 11110 11111 Bus clock filter count is 26 Bus clock filter count is 27 Bus clock filter count is 28 Bus clock filter count is 29 Bus clock filter count is 30 Bus clock filter count is 31 Bus clock filter count is 32 14.2.5 Mode Register (RCM_MR) This register includes read-only status flags to indicate the state of the mode pins during the last Chip Reset. Address: 4007_F000h base + 7h offset = 4007_F007h Bit 7 6 5 Read 4 3 2 0 1 0 EZP_MS 0 0 0 Write Reset 0 0 0 0 0 0 RCM_MR field descriptions Field Description 7-2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 EZP_MS EZP_MS_B pin state Reflects the state of the EZP_MS pin during the last Chip Reset 0 1 0 Reserved Pin deasserted (logic 1) Pin asserted (logic 0) This field is reserved. This read-only field is reserved and always has the value 0. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 327 Reset memory map and register descriptions 14.2.6 Sticky System Reset Status Register 0 (RCM_SSRS0) This register includes status flags to indicate all reset sources since the last POR, LVD or VLLS Wakeup that have not been cleared by software. Software can clear the status flags by writing a logic one to a flag. Address: 4007_F000h base + 8h offset = 4007_F008h Bit 7 6 5 Read SPOR SPIN SWDOG Write w1c w1c w1c Reset 1 0 0 4 3 0 0 0 2 1 0 SLOC SLVD SWAKEUP w1c w1c w1c 0 1 0 RCM_SSRS0 field descriptions Field 7 SPOR Description Sticky Power-On Reset Indicates a reset has been caused by the power-on detection logic. Because the internal supply voltage was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while the internal supply was below the LVD threshold. 0 1 6 SPIN Sticky External Reset Pin Indicates a reset has been caused by an active-low level on the external RESET pin. 0 1 5 SWDOG 2 SLOC Indicates a reset has been caused by the watchdog timer timing out.This reset source can be blocked by disabling the watchdog. Reset not caused by watchdog timeout Reset caused by watchdog timeout This field is reserved. This read-only field is reserved and always has the value 0. Sticky Loss-of-Clock Reset Indicates a reset has been caused by a loss of external clock. The MCG clock monitor must be enabled for a loss of clock to be detected. Refer to the detailed MCG description for information on enabling the clock monitor. 0 1 1 SLVD Reset not caused by external reset pin Reset caused by external reset pin Sticky Watchdog 0 1 4-3 Reserved Reset not caused by POR Reset caused by POR Reset not caused by a loss of external clock. Reset caused by a loss of external clock. Sticky Low-Voltage Detect Reset Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 328 NXP Semiconductors Chapter 14 Reset Control Module (RCM) RCM_SSRS0 field descriptions (continued) Field Description If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This field is also set by POR. 0 1 0 SWAKEUP Reset not caused by LVD trip or POR Reset caused by LVD trip or POR Sticky Low Leakage Wakeup Reset Indicates a reset has been caused by an enabled LLWU modulewakeup source while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx mode causes a reset. 0 1 Reset not caused by LLWU module wakeup source Reset caused by LLWU module wakeup source 14.2.7 Sticky System Reset Status Register 1 (RCM_SSRS1) This register includes status flags to indicate all reset sources since the last POR, LVD or VLLS Wakeup that have not been cleared by software. Software can clear the status flags by writing a logic one to a flag. Address: 4007_F000h base + 9h offset = 4007_F009h Bit 7 6 5 4 3 2 1 0 Read 0 0 SSACKERR SEZPT SMDM_AP SSW SLOCKUP SJTAG w1c w1c w1c w1c w1c w1c 0 0 0 0 0 0 Write Reset 0 0 RCM_SSRS1 field descriptions Field Description 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 SSACKERR Sticky Stop Mode Acknowledge Error Reset Indicates that after an attempt to enter Stop mode, a reset has been caused by a failure of one or more peripherals to acknowledge within approximately one second to enter stop mode. 0 1 4 SEZPT Reset not caused by peripheral failure to acknowledge attempt to enter stop mode Reset caused by peripheral failure to acknowledge attempt to enter stop mode Sticky EzPort Reset Indicates a reset has been caused by EzPort receiving the RESET command while the device is in EzPort mode. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 329 Reset memory map and register descriptions RCM_SSRS1 field descriptions (continued) Field Description 0 1 3 SMDM_AP Sticky MDM-AP System Reset Request Indicates a reset has been caused by the host debugger system setting of the System Reset Request bit in the MDM-AP Control Register. 0 1 2 SSW Indicates a reset has been caused by software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register in the ARM core. Reset not caused by software setting of SYSRESETREQ bit Reset caused by software setting of SYSRESETREQ bit Sticky Core Lockup Indicates a reset has been caused by the ARM core indication of a LOCKUP event. 0 1 0 SJTAG Reset not caused by host debugger system setting of the System Reset Request bit Reset caused by host debugger system setting of the System Reset Request bit Sticky Software 0 1 1 SLOCKUP Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode Reset caused by EzPort receiving the RESET command while the device is in EzPort mode Reset not caused by core LOCKUP event Reset caused by core LOCKUP event Sticky JTAG Generated Reset Indicates a reset has been caused by JTAG selection of certain IR codes: EZPORT, EXTEST, HIGHZ, and CLAMP. 0 1 Reset not caused by JTAG Reset caused by JTAG K22F Sub-Family Reference Manual, Rev. 4, 08/2016 330 NXP Semiconductors Chapter 15 System Mode Controller (SMC) 15.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The System Mode Controller (SMC) is responsible for sequencing the system into and out of all low-power Stop and Run modes. Specifically, it monitors events to trigger transitions between power modes while controlling the power, clocks, and memories of the system to achieve the power consumption and functionality of that mode. This chapter describes all the available low-power modes, the sequence followed to enter/ exit each mode, and the functionality available while in each of the modes. The SMC is able to function during even the deepest low power modes. See AN4503: Power Management for Kinetis MCUs for further details on using the SMC. 15.2 Modes of operation The ARM CPU has three primary modes of operation: * Run * Sleep * Deep Sleep The WFI or WFE instruction is used to invoke Sleep and Deep Sleep modes. Run, Wait, and Stop are the common terms used for the primary operating modes of Kinetis microcontrollers. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 331 Modes of operation The following table shows the translation between the ARM CPU modes and the Kinetis MCU power modes. ARM CPU mode MCU mode Sleep Wait Deep Sleep Stop Accordingly, the ARM CPU documentation refers to sleep and deep sleep, while the Kinetis MCU documentation normally uses wait and stop. In addition, Kinetis MCUs also augment Stop, Wait, and Run modes in a number of ways. The power management controller (PMC) contains a run and a stop mode regulator. Run regulation is used in normal run, wait and stop modes. Stop mode regulation is used during all very low power and low leakage modes. During stop mode regulation, the bus frequencies are limited in the very low power modes. The SMC provides the user with multiple power options. The Very Low Power Run (VLPR) mode can drastically reduce run time power when maximum bus frequency is not required to handle the application needs. From Normal Run mode, the Run Mode (RUNM) field can be modified to change the MCU into VLPR mode when limited frequency is sufficient for the application. From VLPR mode, a corresponding wait (VLPW) and stop (VLPS) mode can be entered. Depending on the needs of the user application, a variety of stop modes are available that allow the state retention, partial power down or full power down of certain logic and/or memory. I/O states are held in all modes of operation. Several registers are used to configure the various modes of operation for the device. The following table describes the power modes available for the device. Table 15-1. Power modes Mode Description RUN The MCU can be run at full speed and the internal supply is fully regulated, that is, in run regulation. This mode is also referred to as Normal Run mode. HSRUN The MCU can be run at a faster frequency compared with RUN mode and the internal supply is fully regulated. See the Power Management chapter for details about the maximum allowable frequencies. WAIT The core clock is gated off. The system clock continues to operate. Bus clocks, if enabled, continue to operate. Run regulation is maintained. STOP The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. VLPR The core, system, bus, and flash clock maximum frequencies are restricted in this mode. See the Power Management chapter for details about the maximum allowable frequencies. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 332 NXP Semiconductors Chapter 15 System Mode Controller (SMC) Table 15-1. Power modes (continued) Mode Description VLPW The core clock is gated off. The system, bus, and flash clocks continue to operate, although their maximum frequency is restricted. See the Power Management chapter for details on the maximum allowable frequencies. VLPS The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. LLS3 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by reducing the voltage to internal logic. All system RAM contents, internal logic and I/O states are retained. LLS2 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by reducing voltage to internal logicand powering down the system RAM2 partition. The system RAM1 partition, internal logic and I/O states are retained.1 VLLS3 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic. All system RAM contents are retained and I/O states are held. Internal logic states are not retained. VLLS2 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic and the system RAM2 partition. The system RAM1 partition contents are retained in this mode. Internal logic states are not retained. 1 VLLS1 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic and all system RAM. I/O states are held. Internal logic states are not retained. VLLS0 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic and all system RAM. I/O states are held. Internal logic states are not retained. The 1kHz LPO clock is disabled and the power on reset (POR) circuit can be optionally enabled using STOPCTRL[PORPO]. 1. See the devices' chip configuration details for the size and location of the system RAM partitions. 15.3 Memory map and register descriptions Information about the registers related to the system mode controller can be found here. Different SMC registers reset on different reset types. Each register's description provides details. For more information about the types of reset on this chip, refer to the Reset section details. NOTE The SMC registers can be written only in supervisor mode. Write accesses in user mode are blocked and will result in a bus error. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 333 Memory map and register descriptions NOTE Before executing the WFI instruction, the last register written to must be read back. This ensures that all register writes associated with setting up the low power mode being entered have completed before the MCU enters the low power mode. Failure to do this may result in the low power mode not being entered correctly. SMC memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_E000 Power Mode Protection register (SMC_PMPROT) 8 R/W 00h 15.3.1/334 4007_E001 Power Mode Control register (SMC_PMCTRL) 8 R/W 00h 15.3.2/335 4007_E002 Stop Control Register (SMC_STOPCTRL) 8 R/W 03h 15.3.3/337 4007_E003 Power Mode Status register (SMC_PMSTAT) 8 R 01h 15.3.4/338 15.3.1 Power Mode Protection register (SMC_PMPROT) This register provides protection for entry into any low-power run or stop mode. The enabling of the low-power run or stop mode occurs by configuring the Power Mode Control register (PMCTRL). The PMPROT register can be written only once after any system reset. If the MCU is configured for a disallowed or reserved power mode, the MCU remains in its current power mode. For example, if the MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is still in Normal Run mode. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 0h offset = 4007_E000h Bit Read Write Reset 7 6 5 4 3 2 1 0 AHSRUN 0 AVLP 0 ALLS 0 AVLLS 0 0 0 0 0 0 0 0 0 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 334 NXP Semiconductors Chapter 15 System Mode Controller (SMC) SMC_PMPROT field descriptions Field 7 AHSRUN Description Allow High Speed Run mode Provided the appropriate control bits are set up in PMCTRL, this write-once field allows the MCU to enter High Speed Run mode (HSRUN). 0 1 6 Reserved 5 AVLP This field is reserved. This read-only field is reserved and always has the value 0. Allow Very-Low-Power Modes Provided the appropriate control bits are set up in PMCTRL, this write-once field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS). 0 1 4 Reserved 3 ALLS 1 AVLLS Allow Low-Leakage Stop Mode Provided the appropriate control bits are set up in PMCTRL, this write-once field allows the MCU to enter any low-leakage stop mode (LLS). Any LLSx mode is not allowed Any LLSx mode is allowed This field is reserved. This read-only field is reserved and always has the value 0. Allow Very-Low-Leakage Stop Mode Provided the appropriate control bits are set up in PMCTRL, this write once bit allows the MCU to enter any very-low-leakage stop mode (VLLSx). 0 1 0 Reserved VLPR, VLPW, and VLPS are not allowed. VLPR, VLPW, and VLPS are allowed. This field is reserved. This read-only field is reserved and always has the value 0. 0 1 2 Reserved HSRUN is not allowed HSRUN is allowed Any VLLSx mode is not allowed Any VLLSx mode is allowed This field is reserved. This read-only field is reserved and always has the value 0. 15.3.2 Power Mode Control register (SMC_PMCTRL) The PMCTRL register controls entry into low-power Run and Stop modes, provided that the selected power mode is allowed via an appropriate setting of the protection (PMPROT) register. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 335 Memory map and register descriptions that do not trigger Chip POR not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 1h offset = 4007_E001h Bit Read Write Reset 7 6 Reserved 5 RUNM 0 0 0 4 3 0 STOPA 0 0 2 1 0 STOPM 0 0 0 SMC_PMCTRL field descriptions Field 7 Reserved 6-5 RUNM Description This field is reserved. This bit is reserved for future expansion. Software should write 0 to this bit to maintain compatibility. Run Mode Control When written, causes entry into the selected run mode. Writes to this field are blocked if the protection level has not been enabled using the PMPROT register. NOTE: RUNM may be set to VLPR only when PMSTAT=RUN. After being written to VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR. NOTE: RUNM may be set to HSRUN only when PMSTAT=RUN. After being programmed to HSRUN, RUNM should not be programmed back to RUN until PMSTAT=HSRUN. Also, stop mode entry should not be attempted while RUNM=HSRUN or PMSTAT=HSRUN. 00 01 10 11 4 Reserved 3 STOPA This field is reserved. This read-only field is reserved and always has the value 0. Stop Aborted When set, this read-only status bit indicates an interrupt occured during the previous stop mode entry sequence, preventing the system from entering that mode. This field is cleared by reset or by hardware at the beginning of any stop mode entry sequence and is set if the sequence was aborted. 0 1 STOPM Normal Run mode (RUN) Reserved Very-Low-Power Run mode (VLPR) High Speed Run mode (HSRUN) The previous stop mode entry was successful. The previous stop mode entry was aborted. Stop Mode Control When written, controls entry into the selected stop mode when Sleep-Now or Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are blocked if the protection level has not been enabled using the PMPROT register. After any system reset, this field is cleared by hardware on any successful write to the PMPROT register. NOTE: When set to VLLSxor LLSx, the LLSM in the STOPCTRL register is used to further select the particular VLLSor LLS submode which will be entered. NOTE: When set to STOP, the PSTOPO bits in the STOPCTRL register can be used to select a Partial Stop mode if desired. 000 Normal Stop (STOP) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 336 NXP Semiconductors Chapter 15 System Mode Controller (SMC) SMC_PMCTRL field descriptions (continued) Field Description 001 010 011 100 101 110 111 Reserved Very-Low-Power Stop (VLPS) Low-Leakage Stop (LLSx) Very-Low-Leakage Stop (VLLSx) Reserved Reseved Reserved 15.3.3 Stop Control Register (SMC_STOPCTRL) The STOPCTRL register provides various control bits allowing the user to fine tune power consumption during the stop mode selected by the STOPM field. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 2h offset = 4007_E002h Bit Read Write Reset 7 6 5 PSTOPO 0 0 4 3 PORPO 0 Reserved 0 0 0 2 1 0 LLSM 0 1 1 SMC_STOPCTRL field descriptions Field 7-6 PSTOPO Description Partial Stop Option These bits control whether a Partial Stop mode is entered when STOPM=STOP. When entering a Partial Stop mode from RUN (or VLPR) mode, the PMC, MCG and flash remain fully powered, allowing the device to wakeup almost instantaneously at the expense of higher power consumption. In PSTOP2, only system clocks are gated allowing peripherals running on bus clock to remain fully functional. In PSTOP1, both system and bus clocks are gated. 00 01 10 11 5 PORPO STOP - Normal Stop mode PSTOP1 - Partial Stop with both system and bus clocks disabled PSTOP2 - Partial Stop with system clock disabled and bus clock enabled Reserved POR Power Option This bit controls whether the POR detect circuit is enabled in VLLS0 mode. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 337 Memory map and register descriptions SMC_STOPCTRL field descriptions (continued) Field Description 0 1 POR detect circuit is enabled in VLLS0 POR detect circuit is disabled in VLLS0 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 Reserved This field is reserved. This bit is reserved for future expansion. Software should write 0 to this bit to maintain compatibility. LLSM LLS or VLLS Mode Control This field controls which LLS orVLLS sub-mode to enter if STOPM = LLSx orVLLSx. 000 001 010 011 100 101 110 111 VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx Reserved Reserved Reserved Reserved 15.3.4 Power Mode Status register (SMC_PMSTAT) PMSTAT is a read-only, one-hot register which indicates the current power mode of the system. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 3h offset = 4007_E003h Bit 7 6 5 4 Read 3 2 1 0 0 0 0 1 PMSTAT Write Reset 0 0 0 0 SMC_PMSTAT field descriptions Field PMSTAT Description Power Mode Status NOTE: When debug is enabled, the PMSTAT will not update to STOP or VLPS K22F Sub-Family Reference Manual, Rev. 4, 08/2016 338 NXP Semiconductors Chapter 15 System Mode Controller (SMC) SMC_PMSTAT field descriptions (continued) Field Description NOTE: When a PSTOP mode is enabled, the PMSTAT will not update to STOP or VLPS 0000_0001 0000_0010 0000_0100 0000_1000 0001_0000 0010_0000 0100_0000 1000_0000 Current power mode is RUN. Current power mode is STOP. Current power mode is VLPR. Current power mode is VLPW. Current power mode is VLPS. Current power mode is LLS. Current power mode is VLLS. Current power mode is HSRUN 15.4 Functional description 15.4.1 Power mode transitions The following figure shows the power mode state transitions available on the chip. Any reset always brings the MCU back to the normal RUN state. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 339 Functional description Any RESET VLPW HSRUN 4 5 12 VLPR WAIT 1 3 RUN 7 2 STOP 6 VLPS 10 8 9 LLS VLLS 11 Figure 15-1. Power mode state diagram The following table defines triggers for the various state transitions shown in the previous figure. Table 15-2. Power mode transition triggers Transition # From To 1 RUN WAIT Trigger conditions Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, controlled in System Control Register in ARM core. See note.1 2 WAIT RUN Interrupt or Reset RUN STOP PMCTRL[RUNM]=00, PMCTRL[STOPM]=0002 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 340 NXP Semiconductors Chapter 15 System Mode Controller (SMC) Table 15-2. Power mode transition triggers (continued) Transition # From To Trigger conditions Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note.1 3 STOP RUN Interrupt or Reset RUN VLPR The core, system, bus and flash clock frequencies and MCG clocking mode are restricted in this mode. See the Power Management chapter for the maximum allowable frequencies and MCG modes supported. VLPR RUN VLPR VLPW Set PMPROT[AVLP]=1, PMCTRL[RUNM]=10. Set PMCTRL[RUNM]=00 or Reset. 4 Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, which is controlled in System Control Register in ARM core. See note.1 VLPW VLPR Interrupt 5 VLPW RUN Reset 6 VLPR VLPS PMCTRL[STOPM]=0003 or 010, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note.1 VLPS VLPR Interrupt NOTE: If VLPS was entered directly from RUN (transition #7), hardware forces exit back to RUN and does not allow a transition to VLPR. 7 RUN VLPS PMPROT[AVLP]=1, PMCTRL[STOPM]=010, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note.1 VLPS RUN Interrupt and VLPS mode was entered directly from RUN or Reset 8 9 RUN VLLSx VLLSx RUN VLPR VLLSx PMPROT[AVLLS]=1, PMCTRL[STOPM]=100, STOPCTRL[LLSM]=x (VLLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. Wakeup from enabled LLWU input source or RESET pin PMPROT[AVLLS]=1, PMCTRL[STOPM]=100, STOPCTRL[LLSM]=x (VLLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 341 Functional description Table 15-2. Power mode transition triggers (continued) Transition # From To Trigger conditions 10 RUN LLSx PMPROT[ALLS]=1, PMCTRL[STOPM]=011, STOPCTRL[LLSM]=x (LLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. LLSx RUN Wakeup from enabled LLWU input source and LLSx mode was entered directly from RUN or RESET pin. 11 VLPR LLSx PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. LLSx VLPR Wakeup from enabled LLWU input source and LLSx mode was entered directly from VLPR NOTE: If LLSx was entered directly from RUN, hardware will not allow this transition and will force exit back to RUN 12 RUN HSRUN HSRUN RUN Set PMPROT[AHSRUN]=1, PMCTRL[RUNM]=11. Set PMCTRL[RUNM]=00 or Reset 1. If debug is enabled, the core clock remains to support debug. 2. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=01 or 10, then only a Partial Stop mode is entered instead of STOP 3. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=00, then VLPS mode is entered instead of STOP. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=01 or 10, then only a Partial Stop mode is entered instead of VLPS 15.4.2 Power mode entry/exit sequencing When entering or exiting low-power modes, the system must conform to an orderly sequence to manage transitions safely. The SMC manages the system's entry into and exit from all power modes. This diagram illustrates the connections of the SMC with other system components in the chip that are necessary to sequence the system through all power modes. Figure 15-2. Low-power system components and connections 15.4.2.1 Stop mode entry sequence Entry into a low-power stop mode (Stop, VLPS, LLS, VLLSx) is initiated by a CPU executing the WFI instruction. After the instruction is executed, the following sequence occurs: 1. The CPU clock is gated off immediately. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 342 NXP Semiconductors Chapter 15 System Mode Controller (SMC) 2. Requests are made to all non-CPU bus masters to enter Stop mode. 3. After all masters have acknowledged they are ready to enter Stop mode, requests are made to all bus slaves to enter Stop mode. 4. After all slaves have acknowledged they are ready to enter Stop mode, all system and bus clocks are gated off. 5. Clock generators are disabled in the MCG. 6. The on-chip regulator in the PMC and internal power switches are configured to meet the power consumption goals for the targeted low-power mode. 15.4.2.2 Stop mode exit sequence Exit from a low-power stop mode is initiated either by a reset or an interrupt event. The following sequence then executes to restore the system to a run mode (RUN or VLPR): 1. The on-chip regulator in the PMC and internal power switches are restored. 2. Clock generators are enabled in the MCG. 3. System and bus clocks are enabled to all masters and slaves. 4. The CPU clock is enabled and the CPU begins servicing the reset or interrupt that initiated the exit from the low-power stop mode. 15.4.2.3 Aborted stop mode entry If an interrupt occurs during a stop entry sequence, the SMC can abort the transition early and return to RUN mode without completely entering the stop mode. An aborted entry is possible only if the interrupt occurs before the PMC begins the transition to stop mode regulation. After this point, the interrupt is ignored until the PMC has completed its transition to stop mode regulation. When an aborted stop mode entry sequence occurs, SMC_PMCTRL[STOPA] is set to 1. 15.4.2.4 Transition to wait modes For wait modes (WAIT and VLPW), the CPU clock is gated off while all other clocking continues, as in RUN and VLPR mode operation. Some modules that support stop-inwait functionality have their clocks disabled in these configurations. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 343 Functional description 15.4.2.5 Transition from stop modes to Debug mode The debugger module supports a transition from STOP, WAIT, VLPS, and VLPW back to a Halted state when the debugger has been enabled. As part of this transition, system clocking is re-established and is equivalent to the normal RUN and VLPR mode clocking configuration. 15.4.3 Run modes The run modes supported by this device can be found here. * Run (RUN) * Very Low-Power Run (VLPR) * High Speed Run (HSRUN) 15.4.3.1 RUN mode This is the normal operating mode for the device. This mode is selected after any reset. When the ARM processor exits reset, it sets up the stack, program counter (PC), and link register (LR): * The processor reads the start SP (SP_main) from vector-table offset 0x000 * The processor reads the start PC from vector-table offset 0x004 * LR is set to 0xFFFF_FFFF. To reduce power in this mode, disable the clocks to unused modules. 15.4.3.2 Very-Low Power Run (VLPR) mode In VLPR mode, the on-chip voltage regulator is put into a stop mode regulation state. In this state, the regulator is designed to supply enough current to the MCU over a reduced frequency. To further reduce power in this mode, disable the clocks to unused modules using their corresponding clock gating control bits in the SIM's registers. Before entering this mode, the following conditions must be met: * The MCG must be configured in a mode which is supported during VLPR. See the Power Management details for information about these MCG modes. * All clock monitors in the MCG must be disabled. * The maximum frequencies of the system, bus, flash, and core are restricted. See the Power Management details about which frequencies are supported. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 344 NXP Semiconductors Chapter 15 System Mode Controller (SMC) * Mode protection must be set to allow VLP modes, that is, PMPROT[AVLP] is 1. * PMCTRL[RUNM] must be set to 10b to enter VLPR. * Flash programming/erasing is not allowed. NOTE Do not increase the clock frequency while in VLPR mode, because the regulator is slow in responding and cannot manage fast load transitions. In addition, do not modify the clock source in the MCG module or any clock divider registers. Module clock enables in the SIM can be set, but not cleared. To reenter Normal Run mode, clear PMCTRL[RUNM]. PMSTAT is a read-only status register that can be used to determine when the system has completed an exit to RUN mode. When PMSTAT=RUN, the system is in run regulation and the MCU can run at full speed in any clock mode. If a higher execution frequency is desired, poll PMSTAT until it is set to RUN when returning from VLPR mode. Any reset always causes an exit from VLPR and returns the device to RUN mode after the MCU exits its reset flow. 15.4.3.3 High Speed Run (HSRUN) mode In HSRUN mode, the on-chip voltage regulator remains in a run regulation state, but with a slightly elevated voltage output. In this state, the MCU is able to operate at a faster frequency compared to normal RUN mode. For the maximum allowable frequencies, see the Power Management chapter. While in this mode, the following restrictions must be adhered to: * The maximum allowable change in frequency of the system, bus, flash or core clocks is restricted to 2x (double the frequency). * Before exiting HSRUN mode, clock frequencies should be reduced back down to those acceptable in RUN mode. * Stop mode entry is not supported from HSRUN. * Modifications to clock gating control bits are prohibited. * Flash programming/erasing is not allowed. To enter HSRUN mode, set PMPROT[AHSRUN] to allow HSRUN and then set PMCTRL[RUNM]=HSRUN. Before increasing clock frequencies, the PMSTAT register should be polled to determine when the system has completed entry into HSRUN mode. To reenter normal RUN mode, clear PMCTRL[RUNM]. Any reset also clears PMCTRL[RUNM] and causes the system to exit to normal RUN mode after the MCU exits its reset flow. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 345 Functional description 15.4.4 Wait modes This device contains two different wait modes which are listed here. * Wait * Very-Low Power Wait (VLPW) 15.4.4.1 WAIT mode WAIT mode is entered when the ARM core enters the Sleep-Now or Sleep-On-Exit modes while SLEEPDEEP is cleared. The ARM CPU enters a low-power state in which it is not clocked, but peripherals continue to be clocked provided they are enabled. When an interrupt request occurs, the CPU exits WAIT mode and resumes processing in RUN mode, beginning with the stacking operations leading to the interrupt service routine. A system reset causes an exit from WAIT mode, returning the device to normal RUN mode. 15.4.4.2 Very-Low-Power Wait (VLPW) mode VLPW mode is entered by entering the Sleep-Now or Sleep-On-Exit mode while SLEEPDEEP is cleared and the device is in VLPR mode. In VLPW, the on-chip voltage regulator remains in its stop regulation state. In this state, the regulator is designed to supply enough current to the device at a reduced frequency. To further reduce power in this mode, disable the clocks to unused modules. VLPR mode restrictions also apply to VLPW. When an interrupt from VLPW occurs, the device returns to VLPR mode to execute the interrupt service routine. A system reset causes an exit from VLPW mode, returning the device to normal RUN mode. 15.4.5 Stop modes This device contains a variety of stop modes to meet your application needs. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 346 NXP Semiconductors Chapter 15 System Mode Controller (SMC) The stop modes range from: * a stopped CPU, with all I/O, logic, and memory states retained, and certain asynchronous mode peripherals operating to: * a powered down CPU, with only I/O and a small register file retained, very few asynchronous mode peripherals operating, while the remainder of the MCU is powered down. The choice of stop mode depends upon the user's application, and how power usage and state retention versus functional needs and recovery time may be traded off. The various stop modes are selected by setting the appropriate fields in PMPROT and PMCTRL. The selected stop mode is entered during the sleep-now or sleep-on-exit entry with the SLEEPDEEP bit set in the System Control Register in the ARM core. The available stop modes are: * * * * Normal Stop (STOP) Very-Low Power Stop (VLPS) Low-Leakage Stop (LLS) Very-Low-Leakage Stop (VLLSx) 15.4.5.1 STOP mode STOP mode is entered via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core. The MCG module can be configured to leave the reference clocks running. A module capable of providing an asynchronous interrupt to the device takes the device out of STOP mode and returns the device to normal RUN mode. Refer to the device's Power Management chapter for peripheral, I/O, and memory operation in STOP mode. When an interrupt request occurs, the CPU exits STOP mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. A system reset will cause an exit from STOP mode, returning the device to normal RUN mode via an MCU reset. 15.4.5.2 Very-Low-Power Stop (VLPS) mode The two ways in which VLPS mode can be entered are listed here. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 347 Functional description * Entry into stop via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core while the MCU is in VLPR mode and PMCTRL[STOPM] = 010 or 000. * Entry into stop via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core while the MCU is in normal RUN mode and PMCTRL[STOPM] = 010. When VLPS is entered directly from RUN mode, exit to VLPR is disabled by hardware and the system will always exit back to RUN. In VLPS, the on-chip voltage regulator remains in its stop regulation state as in VLPR. A module capable of providing an asynchronous interrupt to the device takes the device out of VLPS and returns the device to VLPR mode. A system reset will also cause a VLPS exit, returning the device to normal RUN mode. 15.4.5.3 Low-Leakage Stop (LLSx) modes This device contains two Low-Leakage Stop modes: LLS3 and LLS2. LLS or LLSx is often used in this document to refer to both modes. All LLS modes can be entered from normal RUN or VLPR modes. The MCU enters LLS mode if: * In Sleep-Now or Sleep-On-Exit mode, SLEEPDEEP is set in the System Control Register in the ARM core, and * The device is configured as shown in Table 15-2. In LLS, the on-chip voltage regulator is in stop regulation. Most of the peripherals are put in a state-retention mode that does not allow them to operate while in LLS. Before entering LLS mode, the user should configure the Low-Leakage Wake-up (LLWU) module to enable the desired wake-up sources. The available wake-up sources in LLS are detailed in the chip configuration details for this device. After wakeup from LLS, the device returns to the run mode from which LLS was entered (either normal RUN or VLPR) with a pending LLWU module interrupt. In the LLWU interrupt service routine (ISR), the user can poll the LLWU module wake-up flags to determine the source of the wakeup. NOTE The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit Stop mode on an LLS recovery. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 348 NXP Semiconductors Chapter 15 System Mode Controller (SMC) An asserted RESET pin will cause an exit from LLS mode, returning the device to normal RUN mode. When LLS is exiting via the RESET pin, RCM_SRS[PIN] and RCM_SRS[WAKEUP] are set. 15.4.5.4 Very-Low-Leakage Stop (VLLSx) modes This device contains these very low leakage modes: * * * * VLLS3 VLLS2 VLLS1 VLLS0 VLLSx is often used in this document to refer to all of these modes. All VLLSx modes can be entered from normal RUN or VLPR modes. The MCU enters the configured VLLS mode if: * In Sleep-Now or Sleep-On-Exit mode, the SLEEPDEEP bit is set in the System Control Register in the ARM core, and * The device is configured as shown in Table 15-2. In VLLS, the on-chip voltage regulator is in its stop-regulation state while most digital logic is powered off. Before entering VLLS mode, the user should configure the Low-Leakage Wake-up (LLWU) module to enable the desired wakeup sources. The available wake-up sources in VLLS are detailed in the chip configuration details for this device. After wakeup from VLLS, the device returns to normal RUN mode with a pending LLWU interrupt. In the LLWU interrupt service routine (ISR), the user can poll the LLWU module wake-up flags to determine the source of the wake-up. When entering VLLS, each I/O pin is latched as configured before executing VLLS. Because all digital logic in the MCU is powered off, all port and peripheral data is lost during VLLS. This information must be restored before PMC_REGSC[ACKISO] is set. An asserted RESET pin will cause an exit from any VLLS mode, returning the device to normal RUN mode. When exiting VLLS via the RESET pin, RCM_SRS[PIN] and RCM_SRS[WAKEUP] are set. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 349 Functional description 15.4.6 Debug in low power modes When the MCU is secure, the device disables/limits debugger operation. When the MCU is unsecure, the ARM debugger can assert two power-up request signals: * System power up, via SYSPWR in the Debug Port Control/Stat register * Debug power up, via CDBGPWRUPREQ in the Debug Port Control/Stat register When asserted while in RUN, WAIT, VLPR, or VLPR the mode controller drives a corresponding acknowledge for each signal, that is, both CDBGPWRUPACK and CSYSPWRUPACK. When both requests are asserted, the mode controller handles attempts to enter STOP and VLPS by entering an emulated stop state. In this emulated stop state: * * * * * the regulator is in run regulation, the MCG-generated clock source is enabled, all system clocks, except the core clock, are disabled, the debug module has access to core registers, and access to the on-chip peripherals is blocked. No debug is available while the MCU is in LLS or VLLS modes. LLS is a state-retention mode and all debug operation can continue after waking from LLS, even in cases where system wakeup is due to a system reset event. Entering into a VLLS mode causes all of the debug controls and settings to be powered off. To give time to the debugger to sync with the MCU, the MDM AP Control Register includes a Very-Low-Leakage Debug Request (VLLDBGREQ) bit that is set to configure the Reset Controller logic to hold the system in reset after the next recovery from a VLLS mode. This bit allows the debugger time to reinitialize the debug module before the debug session continues. The MDM AP Control Register also includes a Very Low Leakage Debug Acknowledge (VLLDBGACK) bit that is set to release the ARM core being held in reset following a VLLS recovery. The debugger reinitializes all debug IP, and then asserts the VLLDBGACK control bit to allow the RCM to release the ARM core from reset and allow CPU operation to begin. The VLLDBGACK bit is cleared by the debugger (or can be left set as is) or clears automatically due to the reset generated as part of the next VLLS recovery. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 350 NXP Semiconductors Chapter 16 Power Management Controller (PMC) 16.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The power management controller (PMC) contains the internal voltage regulator, power on reset (POR), and low voltage detect system (LVD). See AN4503: Power Management for Kinetis MCUs for further details on using the PMC. 16.2 Features A list of included PMC features can be found here. * Internal voltage regulator * Active POR providing brown-out detect * Low-voltage detect supporting two low-voltage trip points with four warning levels per trip point 16.3 Low-voltage detect (LVD) system This device includes a system to guard against low-voltage conditions. This protects memory contents and controls MCU system states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and a LVD circuit with a user-selectable trip voltage: high (VLVDH) or low (VLVDL). The trip voltage is selected by LVDSC1[LVDV]. The LVD is disabled upon entering VLPx, LLS, and VLLSx modes. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 351 Low-voltage detect (LVD) system Two flags are available to indicate the status of the low-voltage detect system: * The Low Voltage Detect Flag in the Low Voltage Status and Control 1 Register (LVDSC1[LVDF]) operates in a level sensitive manner. LVDSC1[LVDF] is set when the supply voltage falls below the selected trip point (VLVD). LVDSC1[LVDF] is cleared by writing 1 to LVDSC1[LVDACK], but only if the internal supply has returned above the trip point; otherwise, LVDSC1[LVDF] remains set. * The Low Voltage Warning Flag (LVWF) in the Low Voltage Status and Control 2 Register (LVDSC2[LVWF]) operates in a level sensitive manner. LVDSC2[LVWF] is set when the supply voltage falls below the selected monitor trip point (VLVW). LVDSC2[LVWF] is cleared by writing one to LVDSC2[LVWACK], but only if the internal supply has returned above the trip point; otherwise, LVDSC2[LVWF] remains set. 16.3.1 LVD reset operation By setting LVDSC1[LVDRE], the LVD generates a reset upon detection of a low-voltage condition. The low-voltage detection threshold is determined by LVDSC1[LVDV]. After an LVD reset occurs, the LVD system holds the MCU in reset until the supply voltage rises above this threshold. The LVD field in the SRS register of the RCM module (RCM_SRS[LVD]) is set following an LVD or power-on reset. 16.3.2 LVD interrupt operation By configuring the LVD circuit for interrupt operation (LVDSC1[LVDIE] set and LVDSC1[LVDRE] clear), LVDSC1[LVDF] is set and an LVD interrupt request occurs upon detection of a low voltage condition. LVDSC1[LVDF] is cleared by writing 1 to LVDSC1[LVDACK]. 16.3.3 Low-voltage warning (LVW) interrupt operation The LVD system contains a Low-Voltage Warning Flag (LVWF) in the Low Voltage Detect Status and Control 2 Register to indicate that the supply voltage is approaching, but is above, the LVD voltage. The LVW also has an interrupt, which is enabled by setting LVDSC2[LVWIE]. If enabled, an LVW interrupt request occurs when LVDSC2[LVWF] is set. LVDSC2[LVWF] is cleared by writing 1 to LVDSC2[LVWACK]. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 352 NXP Semiconductors Chapter 16 Power Management Controller (PMC) LVDSC2[LVWV] selects one of the four trip voltages: * Highest: VLVW4 * Two mid-levels: VLVW3 and VLVW2 * Lowest: VLVW1 16.4 I/O retention When in LLS mode, the I/O pins are held in their input or output state. Upon wakeup, the PMC is re-enabled, goes through a power up sequence to full regulation, and releases the logic from state retention mode. The I/O are released immediately after a wake-up or reset event. In the case of LLS exit via a RESET pin, the I/O default to their reset state. When in VLLS modes, the I/O states are held on a wake-up event (with the exception of wake-up by reset event) until the wake-up has been acknowledged via a write to REGSC[ACKISO]. In the case of VLLS exit via a RESET pin, the I/O are released and default to their reset state. In this case, no write to REGSC[ACKISO] is needed. 16.5 Memory map and register descriptions Details about the PMC registers can be found here. NOTE Different portions of PMC registers are reset only by particular reset types. Each register's description provides details. For more information about the types of reset on this chip, refer to the Reset section details. The PMC registers can be written only in supervisor mode. Write accesses in user mode are blocked and will result in a bus error. PMC memory map Absolute address (hex) 4007_D000 Register name Width Access (in bits) Low Voltage Detect Status And Control 1 register (PMC_LVDSC1) 8 R/W Reset value Section/ page 10h 16.5.1/354 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 353 Memory map and register descriptions PMC memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_D001 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2) 8 R/W 00h 16.5.2/355 4007_D002 Regulator Status And Control register (PMC_REGSC) 8 R/W 04h 16.5.3/356 16.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1) This register contains status and control bits to support the low voltage detect function. This register should be written during the reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect systems that must have LVD always on, configure the Power Mode Protection (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or low leakage modes from being enabled. See the device's data sheet for the exact LVD trip voltages. NOTE The LVDV bits are reset solely on a POR Only event. The register's other bits are reset on Chip Reset Not VLLS. For more information about these reset types, refer to the Reset section details. Address: 4007_D000h base + 0h offset = 4007_D000h Bit Read 7 6 LVDF 0 Write Reset 5 LVDACK 0 0 4 3 LVDIE LVDRE 0 1 2 1 0 0 0 LVDV 0 0 0 PMC_LVDSC1 field descriptions Field 7 LVDF Description Low-Voltage Detect Flag This read-only status field indicates a low-voltage detect event. 0 1 Low-voltage event not detected Low-voltage event detected Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 354 NXP Semiconductors Chapter 16 Power Management Controller (PMC) PMC_LVDSC1 field descriptions (continued) Field 6 LVDACK 5 LVDIE Description Low-Voltage Detect Acknowledge This write-only field is used to acknowledge low voltage detection errors. Write 1 to clear LVDF. Reads always return 0. Low-Voltage Detect Interrupt Enable Enables hardware interrupt requests for LVDF. 0 1 4 LVDRE Low-Voltage Detect Reset Enable This write-once bit enables LVDF events to generate a hardware reset. Additional writes are ignored. 0 1 3-2 Reserved LVDV Hardware interrupt disabled (use polling) Request a hardware interrupt when LVDF = 1 LVDF does not generate hardware resets Force an MCU reset when LVDF = 1 This field is reserved. This read-only field is reserved and always has the value 0. Low-Voltage Detect Voltage Select Selects the LVD trip point voltage (V LVD ). 00 01 10 11 Low trip point selected (V LVD = V LVDL ) High trip point selected (V LVD = V LVDH ) Reserved Reserved 16.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2) This register contains status and control bits to support the low voltage warning function. While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC2 settings. See the device's data sheet for the exact LVD trip voltages. NOTE The LVW trip voltages depend on LVWV and LVDV. NOTE LVWV is reset solely on a POR Only event. The other fields of the register are reset on Chip Reset Not VLLS. For more information about these reset types, refer to the Reset section details. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 355 Memory map and register descriptions Address: 4007_D000h base + 1h offset = 4007_D001h Bit Read 7 6 LVWF 0 Write Reset LVWACK 0 5 4 3 LVWIE 0 0 2 1 0 0 0 0 LVWV 0 0 0 PMC_LVDSC2 field descriptions Field 7 LVWF Description Low-Voltage Warning Flag This read-only status field indicates a low-voltage warning event. LVWF is set when VSupply transitions below the trip point, or after reset and VSupply is already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW interrupt function, before enabling LVWIE, LVWF must be cleared by writing LVWACK first. 0 1 6 LVWACK 5 LVWIE Low-Voltage Warning Acknowledge This write-only field is used to acknowledge low voltage warning errors. Write 1 to clear LVWF. Reads always return 0. Low-Voltage Warning Interrupt Enable Enables hardware interrupt requests for LVWF. 0 1 4-2 Reserved LVWV Low-voltage warning event not detected Low-voltage warning event detected Hardware interrupt disabled (use polling) Request a hardware interrupt when LVWF = 1 This field is reserved. This read-only field is reserved and always has the value 0. Low-Voltage Warning Voltage Select Selects the LVW trip point voltage (VLVW). The actual voltage for the warning depends on LVDSC1[LVDV]. 00 01 10 11 Low trip point selected (VLVW = VLVW1) Mid 1 trip point selected (VLVW = VLVW2) Mid 2 trip point selected (VLVW = VLVW3) High trip point selected (VLVW = VLVW4) 16.5.3 Regulator Status And Control register (PMC_REGSC) The PMC contains an internal voltage regulator. The voltage regulator design uses a bandgap reference that is also available through a buffer as input to certain internal peripherals, such as the CMP and ADC. The internal regulator provides a status bit (REGONS) indicating the regulator is in run regulation. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 356 NXP Semiconductors Chapter 16 Power Management Controller (PMC) NOTE This register is reset on Chip Reset Not VLLS and by reset types that trigger Chip Reset not VLLS. See the Reset section details for more information. Address: 4007_D000h base + 2h offset = 4007_D002h Bit 7 6 Read 0 0 5 Write Reset 0 0 4 Reserved BGEN 0 0 3 2 ACKISO REGONS w1c 0 1 1 0 Reserved BGBE 0 0 PMC_REGSC field descriptions Field Description 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 Reserved This field is reserved. 4 BGEN Bandgap Enable In VLPx Operation BGEN controls whether the bandgap is enabled in lower power modes of operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage reference in low power modes of operation, set BGEN to continue to enable the bandgap operation. NOTE: When the bandgap voltage reference is not needed in low power modes, clear BGEN to avoid excess power consumption. 0 1 3 ACKISO Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes. Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes. Acknowledge Isolation Reading this field indicates whether certain peripherals and the I/O pads are in a latched state as a result of having been in a VLLS mode. Writing 1 to this field when it is set releases the I/O pads and certain peripherals to their normal run mode state. NOTE: After recovering from a VLLS mode, user should restore chip configuration before clearing ACKISO. In particular, pin configuration for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from being falsely set when ACKISO is cleared. 0 1 2 REGONS Regulator In Run Regulation Status This read-only field provides the current status of the internal voltage regulator. 0 1 1 Reserved Peripherals and I/O pads are in normal run state. Certain peripherals and I/O pads are in an isolated and latched state. Regulator is in stop regulation or in transition to/from it Regulator is in run regulation This field is reserved. NOTE: This reserved bit must remain cleared (set to 0). Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 357 Memory map and register descriptions PMC_REGSC field descriptions (continued) Field 0 BGBE Description Bandgap Buffer Enable Enables the bandgap buffer. 0 1 Bandgap buffer not enabled Bandgap buffer enabled K22F Sub-Family Reference Manual, Rev. 4, 08/2016 358 NXP Semiconductors Chapter 17 Low-Leakage Wakeup Unit (LLWU) 17.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The LLWU module allows the user to select up to 16 external pins and up to 8 internal modules as interrupt wake-up sources from low-leakage power modes. The input sources are described in the device's chip configuration details. Each of the available wake-up sources can be individually enabled. The RESET pin is an additional source for triggering an exit from low-leakage power modes, and causes the MCU to exit both LLS and VLLS through a reset flow. The LLWU module also includes two optional digital pin filters for the external wakeup pins. See AN4503: Power Management for Kinetis MCUs for further details on using the LLWU. 17.1.1 Features The LLWU module features include: * Support for up to 16 external input pins and up to 8 internal modules with individual enable bits for MCU interrupt from low leakage modes * Input sources may be external pins or from internal peripherals capable of running in LLS or VLLS. See the chip configuration information for wakeup input sources for this device. * External pin wake-up inputs, each of which is programmable as falling-edge, risingedge, or any change K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 359 Introduction * Wake-up inputs that are activated after MCU enters a low-leakage power mode * Optional digital filters provided to qualify an external pin detect. Note that when the LPO clock is disabled, the filters are disabled and bypassed. 17.1.2 Modes of operation The LLWU module becomes functional on entry into a low-leakage power mode. After recovery from LLS, the LLWU is immediately disabled. After recovery from VLLS, the LLWU continues to detect wake-up events until the user has acknowledged the wake-up via a write to PMC_REGSC[ACKISO]. 17.1.2.1 LLS mode Wake-up events due to external pin inputs (LLWU_Px) and internal module interrupt inputs (LLWU_MxIF) result in an interrupt flow when exiting LLS. NOTE The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit Stop mode on an LLS recovery. 17.1.2.2 VLLS modes All wakeup and reset events result in VLLS exit via a reset flow. 17.1.2.3 Non-low leakage modes The LLWU is not active in all non-low leakage modes where detection and control logic are in a static state. The LLWU registers are accessible in non-low leakage modes and are available for configuring and reading status when bus transactions are possible. When the wake-up pin filters are enabled, filter operation begins immediately. If a low leakage mode is entered within five LPO clock cycles of an active edge, the edge event will be detected by the LLWU. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 360 NXP Semiconductors Chapter 17 Low-Leakage Wakeup Unit (LLWU) 17.1.2.4 Debug mode When the chip is in Debug mode and then enters LLS or a VLLSx mode, no debug logic works in the fully-functional low-leakage mode. Upon an exit from the LLS or VLLSx mode, the LLWU becomes inactive. 17.1.3 Block diagram The following figure is the block diagram for the LLWU module. enter low leakge mode WUME7 Module7 interrupt flag (LLWU_M7IF) Module0 interrupt flag (LLWU_M0IF) Interrupt module flag detect LLWU_MWUF7 occurred Interrupt module flag detect LLWU_MWUF0 occurred FILT1[FILTSEL] Internal module sources WUME0 LPO LLWU_P15 Synchronizer LLWU_P0 Pin filter 1 LPO Synchronizer Pin filter 2 FILT1[FILTE] Edge detect Pin filter 1 wakeup occurred LLWU controller FILT2[FILTE] Edge detect exit low leakge mode Pin filter 2 wakeup occurred interrupt flow reset flow WUPE15 2 FILT2[FILTSEL] Edge detect Edge detect LLWU_P15 wakeup occurred LLWU_P0 wakeup occurred External pin sources 2 WUPE0 Figure 17-1. LLWU block diagram K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 361 LLWU signal descriptions 17.2 LLWU signal descriptions The signal properties of LLWU are shown in the table found here. The external wakeup input pins can be enabled to detect either rising-edge, falling-edge, or on any change. Table 17-1. LLWU signal descriptions Signal LLWU_Pn Description I/O Wakeup inputs (n = 0-15 ) I 17.3 Memory map/register definition The LLWU includes the following registers: * Wake-up source enable registers * Enable external pin input sources * Enable internal peripheral interrupt sources * Wake-up flag registers * Indication of wakeup source that caused exit from a low-leakage power mode includes external pin or internal module interrupt * Wake-up pin filter enable registers NOTE The LLWU registers can be written only in supervisor mode. Write accesses in user mode are blocked and will result in a bus error. All LLWU registers are reset by Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. Each register's displayed reset value represents this subset of reset types. LLWU registers are unaffected by reset types that do not trigger Chip Reset not VLLS. For more information about the types of reset on this chip, refer to the Introduction details. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 362 NXP Semiconductors Chapter 17 Low-Leakage Wakeup Unit (LLWU) LLWU memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_C000 LLWU Pin Enable 1 register (LLWU_PE1) 8 R/W 00h 17.3.1/363 4007_C001 LLWU Pin Enable 2 register (LLWU_PE2) 8 R/W 00h 17.3.2/364 4007_C002 LLWU Pin Enable 3 register (LLWU_PE3) 8 R/W 00h 17.3.3/365 4007_C003 LLWU Pin Enable 4 register (LLWU_PE4) 8 R/W 00h 17.3.4/366 4007_C004 LLWU Module Enable register (LLWU_ME) 8 R/W 00h 17.3.5/367 4007_C005 LLWU Flag 1 register (LLWU_F1) 8 R/W 00h 17.3.6/369 4007_C006 LLWU Flag 2 register (LLWU_F2) 8 R/W 00h 17.3.7/371 4007_C007 LLWU Flag 3 register (LLWU_F3) 8 R 00h 17.3.8/372 4007_C008 LLWU Pin Filter 1 register (LLWU_FILT1) 8 R/W 00h 17.3.9/374 4007_C009 LLWU Pin Filter 2 register (LLWU_FILT2) 8 R/W 00h 17.3.10/375 17.3.1 LLWU Pin Enable 1 register (LLWU_PE1) LLWU_PE1 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P3-LLWU_P0. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 0h offset = 4007_C000h Bit Read Write Reset 7 6 5 WUPE3 0 4 3 WUPE2 0 0 2 1 WUPE1 0 0 0 WUPE0 0 0 0 LLWU_PE1 field descriptions Field 7-6 WUPE3 Description Wakeup Pin Enable For LLWU_P3 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 5-4 WUPE2 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P2 Enables and configures the edge detection for the wakeup pin. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 363 Memory map/register definition LLWU_PE1 field descriptions (continued) Field Description 00 01 10 11 3-2 WUPE1 Wakeup Pin Enable For LLWU_P1 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 WUPE0 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P0 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection 17.3.2 LLWU Pin Enable 2 register (LLWU_PE2) LLWU_PE2 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P7-LLWU_P4. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 1h offset = 4007_C001h Bit Read Write Reset 7 6 5 WUPE7 0 4 3 WUPE6 0 0 2 1 WUPE5 0 0 0 WUPE4 0 0 0 LLWU_PE2 field descriptions Field 7-6 WUPE7 Description Wakeup Pin Enable For LLWU_P7 Enables and configures the edge detection for the wakeup pin. 00 01 External input pin disabled as wakeup input External input pin enabled with rising edge detection Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 364 NXP Semiconductors Chapter 17 Low-Leakage Wakeup Unit (LLWU) LLWU_PE2 field descriptions (continued) Field Description 10 11 5-4 WUPE6 Wakeup Pin Enable For LLWU_P6 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 3-2 WUPE5 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P5 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 WUPE4 External input pin enabled with falling edge detection External input pin enabled with any change detection External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P4 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection 17.3.3 LLWU Pin Enable 3 register (LLWU_PE3) LLWU_PE3 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P11-LLWU_P8. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 2h offset = 4007_C002h Bit Read Write Reset 7 6 5 WUPE11 0 4 3 WUPE10 0 0 2 1 WUPE9 0 0 0 WUPE8 0 0 0 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 365 Memory map/register definition LLWU_PE3 field descriptions Field 7-6 WUPE11 Description Wakeup Pin Enable For LLWU_P11 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 5-4 WUPE10 Wakeup Pin Enable For LLWU_P10 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 3-2 WUPE9 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P9 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 WUPE8 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P8 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection 17.3.4 LLWU Pin Enable 4 register (LLWU_PE4) LLWU_PE4 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P15-LLWU_P12. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 366 NXP Semiconductors Chapter 17 Low-Leakage Wakeup Unit (LLWU) Address: 4007_C000h base + 3h offset = 4007_C003h Bit Read Write Reset 7 6 5 WUPE15 0 4 3 WUPE14 0 0 2 1 WUPE13 0 0 0 WUPE12 0 0 0 LLWU_PE4 field descriptions Field 7-6 WUPE15 Description Wakeup Pin Enable For LLWU_P15 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 5-4 WUPE14 Wakeup Pin Enable For LLWU_P14 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 3-2 WUPE13 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P13 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 WUPE12 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P12 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection 17.3.5 LLWU Module Enable register (LLWU_ME) LLWU_ME contains the bits to enable the internal module flag as a wakeup input source for inputs MWUF7-MWUF0. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 367 Memory map/register definition types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 4h offset = 4007_C004h Bit Read Write Reset 7 6 5 4 3 2 1 0 WUME7 WUME6 WUME5 WUME4 WUME3 WUME2 WUME1 WUME0 0 0 0 0 0 0 0 0 LLWU_ME field descriptions Field 7 WUME7 Description Wakeup Module Enable For Module 7 Enables an internal module as a wakeup source input. 0 1 6 WUME6 Wakeup Module Enable For Module 6 Enables an internal module as a wakeup source input. 0 1 5 WUME5 Enables an internal module as a wakeup source input. Enables an internal module as a wakeup source input. Enables an internal module as a wakeup source input. Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 2 Enables an internal module as a wakeup source input. 0 1 1 WUME1 Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 3 0 1 2 WUME2 Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 4 0 1 3 WUME3 Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 5 0 1 4 WUME4 Internal module flag not used as wakeup source Internal module flag used as wakeup source Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable for Module 1 Enables an internal module as a wakeup source input. 0 1 Internal module flag not used as wakeup source Internal module flag used as wakeup source Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 368 NXP Semiconductors Chapter 17 Low-Leakage Wakeup Unit (LLWU) LLWU_ME field descriptions (continued) Field 0 WUME0 Description Wakeup Module Enable For Module 0 Enables an internal module as a wakeup source input. 0 1 Internal module flag not used as wakeup source Internal module flag used as wakeup source 17.3.6 LLWU Flag 1 register (LLWU_F1) LLWU_F1 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. The external wakeup flags are read-only and clearing a flag is accomplished by a write of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will remain set if the associated WUPEx bit is cleared. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 5h offset = 4007_C005h Bit 7 6 5 4 3 2 1 0 Read WUF7 WUF6 WUF5 WUF4 WUF3 WUF2 WUF1 WUF0 Write w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 LLWU_F1 field descriptions Field 7 WUF7 Description Wakeup Flag For LLWU_P7 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF7. 0 1 6 WUF6 LLWU_P7 input was not a wakeup source LLWU_P7 input was a wakeup source Wakeup Flag For LLWU_P6 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF6. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 369 Memory map/register definition LLWU_F1 field descriptions (continued) Field Description 0 1 5 WUF5 Wakeup Flag For LLWU_P5 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF5. 0 1 4 WUF4 Indicates that an enabled external wake-up pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF4. Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF3. Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF2. LLWU_P2 input was not a wakeup source LLWU_P2 input was a wakeup source Wakeup Flag For LLWU_P1 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF1. 0 1 0 WUF0 LLWU_P3 input was not a wake-up source LLWU_P3 input was a wake-up source Wakeup Flag For LLWU_P2 0 1 1 WUF1 LLWU_P4 input was not a wakeup source LLWU_P4 input was a wakeup source Wakeup Flag For LLWU_P3 0 1 2 WUF2 LLWU_P5 input was not a wakeup source LLWU_P5 input was a wakeup source Wakeup Flag For LLWU_P4 0 1 3 WUF3 LLWU_P6 input was not a wakeup source LLWU_P6 input was a wakeup source LLWU_P1 input was not a wakeup source LLWU_P1 input was a wakeup source Wakeup Flag For LLWU_P0 Indicates that an enabled external wake-up pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF0. 0 1 LLWU_P0 input was not a wakeup source LLWU_P0 input was a wakeup source K22F Sub-Family Reference Manual, Rev. 4, 08/2016 370 NXP Semiconductors Chapter 17 Low-Leakage Wakeup Unit (LLWU) 17.3.7 LLWU Flag 2 register (LLWU_F2) LLWU_F2 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. The external wakeup flags are read-only and clearing a flag is accomplished by a write of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will remain set if the associated WUPEx bit is cleared. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 6h offset = 4007_C006h Bit 7 6 5 4 3 2 1 0 Read WUF15 WUF14 WUF13 WUF12 WUF11 WUF10 WUF9 WUF8 Write w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 LLWU_F2 field descriptions Field 7 WUF15 Description Wakeup Flag For LLWU_P15 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF15. 0 1 6 WUF14 Wakeup Flag For LLWU_P14 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF14. 0 1 5 WUF13 LLWU_P15 input was not a wakeup source LLWU_P15 input was a wakeup source LLWU_P14 input was not a wakeup source LLWU_P14 input was a wakeup source Wakeup Flag For LLWU_P13 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF13. 0 1 LLWU_P13 input was not a wakeup source LLWU_P13 input was a wakeup source Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 371 Memory map/register definition LLWU_F2 field descriptions (continued) Field 4 WUF12 Description Wakeup Flag For LLWU_P12 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF12. 0 1 3 WUF11 Wakeup Flag For LLWU_P11 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF11. 0 1 2 WUF10 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF10. LLWU_P10 input was not a wakeup source LLWU_P10 input was a wakeup source Wakeup Flag For LLWU_P9 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF9. 0 1 0 WUF8 LLWU_P11 input was not a wakeup source LLWU_P11 input was a wakeup source Wakeup Flag For LLWU_P10 0 1 1 WUF9 LLWU_P12 input was not a wakeup source LLWU_P12 input was a wakeup source LLWU_P9 input was not a wakeup source LLWU_P9 input was a wakeup source Wakeup Flag For LLWU_P8 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF8. 0 1 LLWU_P8 input was not a wakeup source LLWU_P8 input was a wakeup source 17.3.8 LLWU Flag 3 register (LLWU_F3) LLWU_F3 contains the wakeup flags indicating which internal wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. For internal peripherals that are capable of running in a low-leakage power mode, such as a real time clock module or CMP module, the flag from the associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared in the peripheral instead of writing a 1 to the MWUFx bit. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 372 NXP Semiconductors Chapter 17 Low-Leakage Wakeup Unit (LLWU) NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 7h offset = 4007_C007h Bit Read 7 6 5 4 3 2 1 0 MWUF7 MWUF6 MWUF5 MWUF4 MWUF3 MWUF2 MWUF1 MWUF0 0 0 0 0 0 0 0 0 Write Reset LLWU_F3 field descriptions Field 7 MWUF7 Description Wakeup flag For module 7 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 6 MWUF6 Wakeup flag For module 6 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 5 MWUF5 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. Module 4 input was not a wakeup source Module 4 input was a wakeup source Wakeup flag For module 3 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 2 MWUF2 Module 5 input was not a wakeup source Module 5 input was a wakeup source Wakeup flag For module 4 0 1 3 MWUF3 Module 6 input was not a wakeup source Module 6 input was a wakeup source Wakeup flag For module 5 0 1 4 MWUF4 Module 7 input was not a wakeup source Module 7 input was a wakeup source Module 3 input was not a wakeup source Module 3 input was a wakeup source Wakeup flag For module 2 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 373 Memory map/register definition LLWU_F3 field descriptions (continued) Field Description Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 1 MWUF1 Wakeup flag For module 1 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 0 MWUF0 Module 2 input was not a wakeup source Module 2 input was a wakeup source Module 1 input was not a wakeup source Module 1 input was a wakeup source Wakeup flag For module 0 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 Module 0 input was not a wakeup source Module 0 input was a wakeup source 17.3.9 LLWU Pin Filter 1 register (LLWU_FILT1) LLWU_FILT1 is a control and status register that is used to enable/disable the digital filter 1 features for an external pin. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 8h offset = 4007_C008h Bit 7 Read FILTF Write w1c Reset 0 6 5 3 2 0 FILTE 0 4 0 0 1 0 0 0 FILTSEL 0 0 LLWU_FILT1 field descriptions Field 7 FILTF Description Filter Detect Flag Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage power mode. To clear the flag write a one to FILTF. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 374 NXP Semiconductors Chapter 17 Low-Leakage Wakeup Unit (LLWU) LLWU_FILT1 field descriptions (continued) Field Description 0 1 6-5 FILTE Pin Filter 1 was not a wakeup source Pin Filter 1 was a wakeup source Digital Filter On External Pin Controls the digital filter options for the external pin detect. 00 01 10 11 Filter disabled Filter posedge detect enabled Filter negedge detect enabled Filter any edge detect enabled 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. FILTSEL Filter Pin Select Selects 1 out of the 16 wakeup pins to be muxed into the filter. 0000 ... 1111 Select LLWU_P0 for filter ... Select LLWU_P15 for filter 17.3.10 LLWU Pin Filter 2 register (LLWU_FILT2) LLWU_FILT2 is a control and status register that is used to enable/disable the digital filter 2 features for an external pin. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 9h offset = 4007_C009h Bit 7 Read FILTF Write w1c Reset 0 6 5 FILTE 0 4 3 2 0 0 0 1 0 0 0 FILTSEL 0 0 LLWU_FILT2 field descriptions Field 7 FILTF Description Filter Detect Flag Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage power mode. To clear the flag write a one to FILTF. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 375 Functional description LLWU_FILT2 field descriptions (continued) Field Description 0 1 6-5 FILTE Pin Filter 2 was not a wakeup source Pin Filter 2 was a wakeup source Digital Filter On External Pin Controls the digital filter options for the external pin detect. 00 01 10 11 Filter disabled Filter posedge detect enabled Filter negedge detect enabled Filter any edge detect enabled 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. FILTSEL Filter Pin Select Selects 1 out of the 16 wakeup pins to be muxed into the filter. 0000 ... 1111 Select LLWU_P0 for filter ... Select LLWU_P15 for filter 17.4 Functional description Thie low-leakage wakeup unit (LLWU) module allows internal peripherals and external input pins as a source of wakeup from low-leakage modes. It is operational only in LLS and VLLSx modes. The LLWU module contains pin enables for each external pin and internal module. For each external pin, the user can disable or select the edge type for the wakeup with the following options: * Falling-edge * Rising-edge * Either-edge When an external pin is enabled as a wakeup source, the pin must be configured as an input pin. The LLWU implements optional 3-cycle glitch filters, based on the LPO clock. A detected external pin is required to remain asserted until the enabled glitch filter times out. Additional latency of up to 2 cycles is due to synchronization, which results in a total of up to 5 cycles of delay before the detect circuit alerts the system to the wakeup or reset event when the filter function is enabled. Two wakeup detect filters are available for selected external pins. Glitch filtering is not provided on the internal modules. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 376 NXP Semiconductors Chapter 17 Low-Leakage Wakeup Unit (LLWU) For internal module interrupts, the WUMEx bit enables the associated module interrupt as a wakeup source. 17.4.1 LLS mode Wakeup events triggered from either an external pin input or an internal module interrupt, result in a CPU interrupt flow to begin user code execution. 17.4.2 VLLS modes For any wakeup from VLLS, recovery is always via a reset flow and RCM_SRS[WAKEUP] is set indicating the low-leakage mode was active. State retention data is lost and I/O will be restored after PMC_REGSC[ACKISO] has been written. A VLLS exit event due to RESET pin assertion causes an exit via a system reset. State retention data is lost and the I/O states immediately return to their reset state. The RCM_SRS[WAKEUP] and RCM_SRS[PIN] bits are set and the system executes a reset flow before CPU operation begins with a reset vector fetch. 17.4.3 Initialization For an enabled peripheral wakeup input, the peripheral flag must be cleared by software before entering LLS or VLLSx mode to avoid an immediate exit from the mode. Flags associated with external input pins, filtered and unfiltered, must also be cleared by software prior to entry to LLS or VLLSx mode. After enabling an external pin filter or changing the source pin, wait at least five LPO clock cycles before entering LLS or VLLSx mode to allow the filter to initialize. NOTE After recovering from a VLLS mode, user must restore chip configuration before clearing PMC_REGSC[ACKISO]. In particular, pin configuration for enabled LLWU wake-up pins must be restored to avoid any LLWU flag from being falsely set when PMC_REGSC[ACKISO] is cleared. The signal selected as a wake-up source pin must be a digital pin, as selected in the pin mux control. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 377 Functional description K22F Sub-Family Reference Manual, Rev. 4, 08/2016 378 NXP Semiconductors Chapter 18 Miscellaneous Control Module (MCM) 18.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control functions. 18.1.1 Features The MCM includes the following features: * Program-visible information on the platform configuration and revision 18.2 Memory map/register descriptions The memory map and register descriptions below describe the registers using byte addresses. MCM memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page E008_0008 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC) 16 R 000Fh 18.2.1/380 E008_000A Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC) 16 R 0017h 18.2.2/380 32 R/W 0000_0000h 18.2.3/381 E008_000C Crossbar Switch (AXBS) Control Register (MCM_PLACR) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 379 Memory map/register descriptions MCM memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page E008_0010 Interrupt Status and Control Register (MCM_ISCR) 32 R 0002_0000h 18.2.4/381 E008_0040 Compute Operation Control Register (MCM_CPO) 32 R/W 0000_0000h 18.2.5/384 18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC) PLASC is a 16-bit read-only register identifying the presence/absence of bus slave connections to the device's crossbar switch. Address: E008_0000h base + 8h offset = E008_0008h Bit 15 14 13 12 Read 11 10 9 8 7 6 5 4 0 3 2 1 0 1 1 1 1 ASC Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 MCM_PLASC field descriptions Field Description 15-8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 1 A bus slave connection to AXBS input port n is absent A bus slave connection to AXBS input port n is present 18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC) PLAMC is a 16-bit read-only register identifying the presence/absence of bus master connections to the device's crossbar switch. Address: E008_0000h base + Ah offset = E008_000Ah Bit 15 14 13 12 Read 11 10 9 8 7 6 5 4 0 3 2 1 0 0 1 1 1 AMC Write Reset 0 0 0 0 0 0 0 0 0 0 0 1 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 380 NXP Semiconductors Chapter 18 Miscellaneous Control Module (MCM) MCM_PLAMC field descriptions Field Description 15-8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 1 A bus master connection to AXBS input port n is absent A bus master connection to AXBS input port n is present 18.2.3 Crossbar Switch (AXBS) Control Register (MCM_PLACR) The PLACR register selects the arbitration policy for the crossbar masters. Address: E008_0000h base + Ch offset = E008_000Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 4 3 2 1 0 0 0 0 0 0 R W Reset 0 0 0 Bit 15 14 13 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 5 0 R ARB W Reset 0 0 0 Reserved 0 0 0 0 0 0 0 0 0 MCM_PLACR field descriptions Field 31-10 Reserved 9 ARB Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. Arbitration select 0 1 Fixed-priority arbitration for the crossbar masters Round-robin arbitration for the crossbar masters This field is reserved. 18.2.4 Interrupt Status and Control Register (MCM_ISCR) The MCM_ISCR register includes the enable and status bits associated with the core's floating-point exceptions. The individual event indicators are first qualified with their exception enables and then logically summed to form an interrupt request sent to the core's NVIC. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 381 Memory map/register descriptions Bits 15-8 are read-only indicator flags based on the processor's FPSCR register. Attempted writes to these bits are ignored. Once set, the flags remain asserted until software clears the corresponding FPSCR bit. Address: E008_0000h base + 10h offset = E008_0010h Bit 31 30 29 28 27 26 25 24 23 22 21 0 19 18 17 16 FIXCE FUFCE FOFCE FDZCE FIOCE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R FUFC FOFC FDZC FIOC 0 0 0 0 0 0 0 0 0 FIDCE Reset FIXC Reserved FIDC R 20 W 0 0 W Reset 0 0 0 0 0 0 0 MCM_ISCR field descriptions Field 31 FIDCE 30-29 Reserved Description FPU input denormal interrupt enable 0 1 Disable interrupt Enable interrupt This field is reserved. This read-only field is reserved and always has the value 0. 28 FIXCE FPU inexact interrupt enable 27 FUFCE FPU underflow interrupt enable 0 1 0 1 Disable interrupt Enable interrupt Disable interrupt Enable interrupt Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 382 NXP Semiconductors Chapter 18 Miscellaneous Control Module (MCM) MCM_ISCR field descriptions (continued) Field Description 26 FOFCE FPU overflow interrupt enable 25 FDZCE FPU divide-by-zero interrupt enable 24 FIOCE FPU invalid operation interrupt enable 23-16 Reserved 15 FIDC 0 1 0 1 0 1 12 FIXC This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input denormalized number has been detected in the processor's FPU. Once set, this bit remains set until software clears the FPSCR[IDC] bit. FPU inexact interrupt status This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an inexact number has been detected in the processor's FPU. Once set, this bit remains set until software clears the FPSCR[IXC] bit. No interrupt Interrupt occurred FPU underflow interrupt status This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an underflow has been detected in the processor's FPU. Once set, this bit remains set until software clears the FPSCR[UFC] bit. No interrupt Interrupt occurred FPU overflow interrupt status This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an overflow has been detected in the processor's FPU. Once set, this bit remains set until software clears the FPSCR[OFC] bit. 0 1 9 FDZC No interrupt Interrupt occurred This field is reserved. This read-only field is reserved and always has the value 0. 0 1 10 FOFC Disable interrupt Enable interrupt FPU input denormal interrupt status 0 1 11 FUFC Disable interrupt Enable interrupt This field is reserved. 0 1 14-13 Reserved Disable interrupt Enable interrupt No interrupt Interrupt occurred FPU divide-by-zero interrupt status This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a divide by zero has been detected in the processor's FPU. Once set, this bit remains set until software clears the FPSCR[DZC] bit. 0 1 No interrupt Interrupt occurred Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 383 Memory map/register descriptions MCM_ISCR field descriptions (continued) Field Description 8 FIOC FPU invalid operation interrupt status This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an illegal operation has been detected in the processor's FPU. Once set, this bit remains set until software clears the FPSCR[IOC] bit. 0 1 Reserved No interrupt Interrupt occurred This field is reserved. This read-only field is reserved and always has the value 0. 18.2.5 Compute Operation Control Register (MCM_CPO) This register controls the Compute Operation. Address: E008_0000h base + 40h offset = E008_0040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 CPOWOI R CPOREQ 0 CPOACK Reset W Reset 0 0 0 0 0 0 0 0 0 0 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 384 NXP Semiconductors Chapter 18 Miscellaneous Control Module (MCM) MCM_CPO field descriptions Field Description 31-3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 CPOWOI Compute Operation wakeup on interrupt 1 CPOACK Compute Operation acknowledge 0 CPOREQ Compute Operation request 0 1 0 1 No effect. When set, the CPOREQ is cleared on any interrupt or exception vector fetch. Compute operation entry has not completed or compute operation exit has completed. Compute operation entry has completed or compute operation exit has not completed. This bit is auto-cleared by vector fetching if CPOWOI = 1. 0 1 Request is cleared. Request Compute Operation. 18.3 Functional description This section describes the functional description of MCM module. 18.3.1 Interrupts The MCM's interrupt is generated if any of the following is true: * FPU input denormal interrupt is enabled (FIDCE) and an input is denormalized (FIDC) * FPU inexact interrupt is enabled (FIXCE) and a number is inexact (FIXC) * FPU underflow interrupt is enabled (FUFCE) and an underflow occurs (FUFC) * FPU overflow interrupt is enabled (FOFCE) and an overflow occurs (FOFC) * FPU divide-by-zero interrupt is enabled (FDZCE) and a divide-by-zero occurs (FDZC) * FPU invalid operation interrupt is enabled (FDZCE) and an invalid occurs (FDZC) 18.3.1.1 Determining source of the interrupt To determine the exact source of the interrupt qualify the interrupt status flags with the corresponding interrupt enable bits. 1. From MCM_ISCR[31:16] && MCM_ISCR[15:0] K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 385 Functional description 2. Search the result for asserted flags, which indicate the exact interrupt sources K22F Sub-Family Reference Manual, Rev. 4, 08/2016 386 NXP Semiconductors Chapter 19 Crossbar Switch Lite (AXBS-Lite) 19.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The information found here provides information on the layout, configuration, and programming of the crossbar switch. The crossbar switch connects bus masters and bus slaves using a crossbar switch structure. This structure allows up to four bus masters to access different bus slaves simultaneously, while providing arbitration among the bus masters when they access the same slave. 19.1.1 Features The crossbar switch includes these features: * Symmetric crossbar bus switch implementation * Allows concurrent accesses from different masters to different slaves * Up to single-clock 32-bit transfer * Programmable configuration for fixed-priority or round-robin slave port arbitration (see the chip-specific information). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 387 Memory Map / Register Definition 19.2 Memory Map / Register Definition This crossbar switch is designed for minimal gate count. It, therefore, has no memorymapped configuration registers. Please see the chip-specific information for information on whether the arbitration method in the crossbar switch is programmable, and by which module. 19.3 Functional Description 19.3.1 General operation When a master accesses the crossbar switch, the access is immediately taken. If the targeted slave port of the access is available, then the access is immediately presented on the slave port. Single-clock or zero-wait-state accesses are possible through the crossbar. If the targeted slave port of the access is busy or parked on a different master port, the requesting master simply sees wait states inserted until the targeted slave port can service the master's request. The latency in servicing the request depends on each master's priority level and the responding slave's access time. Because the crossbar switch appears to be just another slave to the master device, the master device has no knowledge of whether it actually owns the slave port it is targeting. While the master does not have control of the slave port it is targeting, it simply waits. After the master has control of the slave port it is targeting, the master remains in control of the slave port until it relinquishes the slave port by running an IDLE cycle or by targeting a different slave port for its next access. The master can also lose control of the slave port if another higher-priority master makes a request to the slave port. The crossbar terminates all master IDLE transfers, as opposed to allowing the termination to come from one of the slave buses. Additionally, when no master is requesting access to a slave port, the crossbar drives IDLE transfers onto the slave bus, even though a default master may be granted access to the slave port. When a slave bus is being idled by the crossbar, it remains parked with the last master to use the slave port. This is done to save the initial clock of arbitration delay that otherwise would be seen if the same master had to arbitrate to gain control of the slave port. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 388 NXP Semiconductors Chapter 19 Crossbar Switch Lite (AXBS-Lite) 19.3.2 Arbitration The crossbar switch supports two arbitration algorithms: * Fixed priority * Round-robin The selection of the global slave port arbitration is controlled in the MCM module. For fixed priority, set MCM_PLACR[ARB] to 0. For round robin, set MCM_PLACR[ARB] to 1. This arbitration setting applies to all slave ports. 19.3.2.1 Fixed-priority operation When operating in fixed-priority mode, each master is assigned a unique priority level with the highest numbered master having the highest priority (for example, in a system with 5 masters, master 1 has lower priority than master 3). If two masters request access to the same slave port, the master with the highest priority gains control over the slave port. NOTE In this arbitration mode, a higher-priority master can monopolize a slave port, preventing accesses from any lowerpriority master to the port. When a master makes a request to a slave port, the slave port checks whether the new requesting master's priority level is higher than that of the master that currently has control over the slave port, unless the slave port is in a parked state. The slave port performs an arbitration check at every clock edge to ensure that the proper master, if any, has control of the slave port. The following table describes possible scenarios based on the requesting master port: Table 19-1. How the Crossbar Switch grants control of a slave port to a master When Then the Crossbar Switch grants control to the requesting master Both of the following are true: At the next clock edge * The current master is not running a transfer. * The new requesting master's priority level is higher than that of the current master. Both of the following are true: At the next arbitration point for the undefined length burst transfer Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 389 Initialization/application information Table 19-1. How the Crossbar Switch grants control of a slave port to a master (continued) When Then the Crossbar Switch grants control to the requesting master * The current master is running an undefined length burst transfer. * The requesting master's priority level is higher than that of the current master. The requesting master's priority level is lower than the current At the conclusion of one of the following cycles: master. * An IDLE cycle * A non-IDLE cycle to a location other than the current slave port 19.3.2.2 Round-robin priority operation When operating in round-robin mode, each master is assigned a relative priority based on the master port number. This relative priority is compared to the master port number (ID) of the last master to perform a transfer on the slave bus. The highest priority requesting master becomes owner of the slave bus at the next transfer boundary. Priority is based on how far ahead the ID of the requesting master is to the ID of the last master. After granted access to a slave port, a master may perform as many transfers as desired to that port until another master makes a request to the same slave port. The next master in line is granted access to the slave port at the next transfer boundary, or possibly on the next clock cycle if the current master has no pending access request. As an example of arbitration in round-robin mode, assume the crossbar is implemented with master ports 0, 1, 4, and 5. If the last master of the slave port was master 1, and master 0, 4, and 5 make simultaneous requests, they are serviced in the order: 4 then 5 then 0. The round-robin arbitration mode generally provides a more fair allocation of the available slave-port bandwidth (compared to fixed priority) as the fixed master priority does not affect the master selection. 19.4 Initialization/application information No initialization is required for the crossbar switch. See the chip-specific crossbar switch information for the reset state of the arbitration scheme. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 390 NXP Semiconductors Chapter 20 Peripheral Bridge (AIPS-Lite) 20.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The peripheral bridge converts the crossbar switch interface to an interface that can access most of the slave peripherals on this chip. The peripheral bridge occupies 64 MB of the address space, which is divided into peripheral slots of 4 KB. (It might be possible that all the peripheral slots are not used. See the memory map chapter for details on slot assignments.) The bridge includes separate clock enable inputs for each of the slots to accommodate slower peripherals. 20.1.1 Features Key features of the peripheral bridge are: * Supports peripheral slots with 8-, 16-, and 32-bit datapath width 20.1.2 General operation The slave devices connected to the peripheral bridge are modules which contain a programming model of control and status registers. The system masters read and write these registers through the peripheral bridge. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 391 Memory map/register definition The register maps of the peripherals are located on 4-KB boundaries. Each peripheral is allocated one or more 4-KB block(s) of the memory map. Two global external module enables are available for the remaining address space to allow for customization and expansion of addressed peripheral devices. 20.2 Memory map/register definition The AIPS module(s) on this device do(es) not contain any user-programmable registers. 20.3 Functional description The peripheral bridge functions as a bus protocol translator between the crossbar switch and the slave peripheral bus. The peripheral bridge manages all transactions destined for the attached slave devices and generates select signals for modules on the peripheral bus by decoding accesses within the attached address space. 20.3.1 Access support Aligned and misaligned 32-bit, 16-bit, and byte accesses are supported for 32-bit peripherals. Misaligned accesses are supported to allow memory to be placed on the slave peripheral bus. Peripheral registers must not be misaligned, although no explicit checking is performed by the peripheral bridge. All accesses are performed with a single transfer. All accesses to the peripheral slots must be sized less than or equal to the designated peripheral slot size. If an access is attempted that is larger than the targeted port, an error response is generated. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 392 NXP Semiconductors Chapter 21 Direct Memory Access Multiplexer (DMAMUX) 21.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. 21.1.1 Overview The Direct Memory Access Multiplexer (DMAMUX) routes DMA sources, called slots, to any of the four DMA channels. This process is illustrated in the following figure. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 393 Introduction DMAMUX Source #1 DMA channel #0 DMA channel #1 Source #2 Source #3 Source #x Always #1 Always #y Trigger #1 DMA channel #n Trigger #z Figure 21-1. DMAMUX block diagram 21.1.2 Features The DMAMUX module provides these features: * Up to 3459 peripheral slots and up to four always-on slots can be routed to four channels. * four independently selectable DMA channel routers. * The first four channels additionally provide a trigger functionality. * Each channel router can be assigned to one of the possible peripheral DMA slots or to one of the always-on slots. 21.1.3 Modes of operation The following operating modes are available: * Disabled mode K22F Sub-Family Reference Manual, Rev. 4, 08/2016 394 NXP Semiconductors Chapter 21 Direct Memory Access Multiplexer (DMAMUX) In this mode, the DMA channel is disabled. Because disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA channel MUX. It may also be used to temporarily suspend a DMA channel while reconfiguration of the system takes place, for example, changing the period of a DMA trigger. * Normal mode In this mode, a DMA source is routed directly to the specified DMA channel. The operation of the DMAMUX in this mode is completely transparent to the system. * Periodic Trigger mode In this mode, a DMA source may only request a DMA transfer, such as when a transmit buffer becomes empty or a receive buffer becomes full, periodically. Configuration of the period is done in the registers of the periodic interrupt timer (PIT). This mode is available only for channels 0-3. 21.2 External signal description The DMAMUX has no external pins. 21.3 Memory map/register definition This section provides a detailed description of all memory-mapped registers in the DMAMUX. DMAMUX memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_1000 Channel Configuration register (DMAMUX_CHCFG0) 8 R/W 00h 21.3.1/395 4002_1001 Channel Configuration register (DMAMUX_CHCFG1) 8 R/W 00h 21.3.1/395 4002_1002 Channel Configuration register (DMAMUX_CHCFG2) 8 R/W 00h 21.3.1/395 4002_1003 Channel Configuration register (DMAMUX_CHCFG3) 8 R/W 00h 21.3.1/395 21.3.1 Channel Configuration register (DMAMUX_CHCFGn) Each of the DMA channels can be independently enabled/disabled and associated with one of the DMA slots (peripheral slots or always-on slots) in the system. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 395 Functional description NOTE Setting multiple CHCFG registers with the same source value will result in unpredictable behavior. This is true, even if a channel is disabled (ENBL==0). Before changing the trigger or source settings, a DMA channel must be disabled via CHCFGn[ENBL]. Address: 4002_1000h base + 0h offset + (1d x i), where i=0d to 3d Bit Read Write Reset 7 6 5 ENBL TRIG 0 0 4 3 2 1 0 0 0 0 SOURCE 0 0 0 DMAMUX_CHCFGn field descriptions Field 7 ENBL Description DMA Channel Enable Enables the DMA channel. 0 1 6 TRIG DMA Channel Trigger Enable Enables the periodic trigger capability for the triggered DMA channel. 0 1 SOURCE DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. DMA channel is enabled Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. DMA Channel Source (Slot) Specifies which DMA source, if any, is routed to a particular DMA channel. See the chip-specific DMAMUX information for details about the peripherals and their slot numbers. 21.4 Functional description The primary purpose of the DMAMUX is to provide flexibility in the system's use of the available DMA channels. As such, configuration of the DMAMUX is intended to be a static procedure done during execution of the system boot code. However, if the procedure outlined in Enabling and configuring sources is followed, the configuration of the DMAMUX may be changed during the normal operation of the system. Functionally, the DMAMUX channels may be divided into two classes: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 396 NXP Semiconductors Chapter 21 Direct Memory Access Multiplexer (DMAMUX) * Channels that implement the normal routing functionality plus periodic triggering capability * Channels that implement only the normal routing functionality 21.4.1 DMA channels with periodic triggering capability Besides the normal routing functionality, the first 4 channels of the DMAMUX provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes, frames, or packets at fixed intervals without the need for processor intervention. The trigger is generated by the periodic interrupt timer (PIT); as such, the configuration of the periodic triggering interval is done via configuration registers in the PIT. See the section on periodic interrupt timer for more information on this topic. Note Because of the dynamic nature of the system (due to DMA channel priorities, bus arbitration, interrupt service routine lengths, etc.), the number of clock cycles between a trigger and the actual DMA transfer cannot be guaranteed. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 397 Functional description Source #1 Source #2 Source #3 Trigger #1 Source #x Always #1 Trigger #m DMA channel #0 DMA channel #m-1 Always #y Figure 21-2. DMAMUX triggered channels The DMA channel triggering capability allows the system to schedule regular DMA transfers, usually on the transmit side of certain peripherals, without the intervention of the processor. This trigger works by gating the request from the peripheral to the DMA until a trigger event has been seen. This is illustrated in the following figure. Peripheral request Trigger DMA request Figure 21-3. DMAMUX channel triggering: normal operation After the DMA request has been serviced, the peripheral will negate its request, effectively resetting the gating mechanism until the peripheral reasserts its request and the next trigger event is seen. This means that if a trigger is seen, but the peripheral is not requesting a transfer, then that trigger will be ignored. This situation is illustrated in the following figure. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 398 NXP Semiconductors Chapter 21 Direct Memory Access Multiplexer (DMAMUX) Peripheral request Trigger DMA request Figure 21-4. DMAMUX channel triggering: ignored trigger This triggering capability may be used with any peripheral that supports DMA transfers, and is most useful for two types of situations: * Periodically polling external devices on a particular bus As an example, the transmit side of an SPI is assigned to a DMA channel with a trigger, as described above. After it has been set up, the SPI will request DMA transfers, presumably from memory, as long as its transmit buffer is empty. By using a trigger on this channel, the SPI transfers can be automatically performed every 5 s (as an example). On the receive side of the SPI, the SPI and DMA can be configured to transfer receive data into memory, effectively implementing a method to periodically read data from external devices and transfer the results into memory without processor intervention. * Using the GPIO ports to drive or sample waveforms By configuring the DMA to transfer data to one or more GPIO ports, it is possible to create complex waveforms using tabular data stored in on-chip memory. Conversely, using the DMA to periodically transfer data from one or more GPIO ports, it is possible to sample complex waveforms and store the results in tabular form in onchip memory. A more detailed description of the capability of each trigger, including resolution, range of values, and so on, may be found in the periodic interrupt timer section. 21.4.2 DMA channels with no triggering capability The other channels of the DMAMUX provide the normal routing functionality as described in Modes of operation. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 399 Functional description 21.4.3 Always-enabled DMA sources In addition to the peripherals that can be used as DMA sources, there are four additional DMA sources that are always enabled. Unlike the peripheral DMA sources, where the peripheral controls the flow of data during DMA transfers, the sources that are always enabled provide no such "throttling" of the data transfers. These sources are most useful in the following cases: * Performing DMA transfers to/from GPIO--Moving data from/to one or more GPIO pins, either unthrottled (that is, as fast as possible), or periodically (using the DMA triggering capability). * Performing DMA transfers from memory to memory--Moving data from memory to memory, typically as fast as possible, sometimes with software activation. * Performing DMA transfers from memory to the external bus, or vice-versa--Similar to memory to memory transfers, this is typically done as quickly as possible. * Any DMA transfer that requires software activation--Any DMA transfer that should be explicitly started by software. In cases where software should initiate the start of a DMA transfer, an always-enabled DMA source can be used to provide maximum flexibility. When activating a DMA channel via software, subsequent executions of the minor loop require that a new start event be sent. This can either be a new software activation, or a transfer request from the DMA channel MUX. The options for doing this are: * Transfer all data in a single minor loop. By configuring the DMA to transfer all of the data in a single minor loop (that is, major loop counter = 1), no reactivation of the channel is necessary. The disadvantage to this option is the reduced granularity in determining the load that the DMA transfer will impose on the system. For this option, the DMA channel must be disabled in the DMA channel MUX. * Use explicit software reactivation. In this option, the DMA is configured to transfer the data using both minor and major loops, but the processor is required to reactivate the channel by writing to the DMA registers after every minor loop. For this option, the DMA channel must be disabled in the DMA channel MUX. * Use an always-enabled DMA source. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 400 NXP Semiconductors Chapter 21 Direct Memory Access Multiplexer (DMAMUX) In this option, the DMA is configured to transfer the data using both minor and major loops, and the DMA channel MUX does the channel reactivation. For this option, the DMA channel should be enabled and pointing to an "always enabled" source. Note that the reactivation of the channel can be continuous (DMA triggering is disabled) or can use the DMA triggering capability. In this manner, it is possible to execute periodic transfers of packets of data from one source to another, without processor intervention. 21.5 Initialization/application information This section provides instructions for initializing the DMA channel MUX. 21.5.1 Reset The reset state of each individual bit is shown in Memory map/register definition. In summary, after reset, all channels are disabled and must be explicitly enabled before use. 21.5.2 Enabling and configuring sources To enable a source with periodic triggering: 1. Determine with which DMA channel the source will be associated. Note that only the first 4 DMA channels have periodic triggering capability. 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel. 3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point. 4. Configure the corresponding timer. 5. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are set. NOTE The following is an example. See the chip configuration details for the number of this device's DMA channels that have triggering capability. To configure source #5 transmit for use with DMA channel 1, with periodic triggering capability: 1. Write 0x00 to CHCFG1. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 401 Initialization/application information 2. Configure channel 1 in the DMA, including enabling the channel. 3. Configure a timer for the desired trigger interval. 4. Write 0xC5 to CHCFG1. The following code example illustrates steps 1 and 4 above: void DMAMUX_Init(uint8_t DMA_CH, uint8_t DMAMUX_SOURCE) { DMAMUX_0.CHCFG[DMA_CH].B.SOURCE = DMAMUX_SOURCE; DMAMUX_0.CHCFG[DMA_CH].B.ENBL = 1; DMAMUX_0.CHCFG[DMA_CH].B.TRIG = 1; } To enable a source, without periodic triggering: 1. Determine with which DMA channel the source will be associated. Note that only the first 4 DMA channels have periodic triggering capability. 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel. 3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point. 4. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that CHCFG[ENBL] is set while CHCFG[TRIG] is cleared. NOTE The following is an example. See the chip configuration details for the number of this device's DMA channels that have triggering capability. To configure source #5 transmit for use with DMA channel 1, with no periodic triggering capability: 1. Write 0x00 to CHCFG1. 2. Configure channel 1 in the DMA, including enabling the channel. 3. Write 0x85 to CHCFG1. The following code example illustrates steps 1 and 3 above: In File registers.h: #define DMAMUX_BASE_ADDR 0x40021000/* Example only ! /* Following example assumes char is 8-bits */ volatile unsigned char *CHCFG0 = (volatile unsigned char volatile unsigned char *CHCFG1 = (volatile unsigned char volatile unsigned char *CHCFG2 = (volatile unsigned char volatile unsigned char *CHCFG3 = (volatile unsigned char volatile unsigned char *CHCFG4 = (volatile unsigned char volatile unsigned char *CHCFG5 = (volatile unsigned char volatile unsigned char *CHCFG6 = (volatile unsigned char volatile unsigned char *CHCFG7 = (volatile unsigned char volatile unsigned char *CHCFG8 = (volatile unsigned char volatile unsigned char *CHCFG9 = (volatile unsigned char volatile unsigned char *CHCFG10= (volatile unsigned char volatile unsigned char *CHCFG11= (volatile unsigned char volatile unsigned char *CHCFG12= (volatile unsigned char volatile unsigned char *CHCFG13= (volatile unsigned char */ *) *) *) *) *) *) *) *) *) *) *) *) *) *) (DMAMUX_BASE_ADDR+0x0003); (DMAMUX_BASE_ADDR+0x0002); (DMAMUX_BASE_ADDR+0x0001); (DMAMUX_BASE_ADDR+0x0000); (DMAMUX_BASE_ADDR+0x0007); (DMAMUX_BASE_ADDR+0x0006); (DMAMUX_BASE_ADDR+0x0005); (DMAMUX_BASE_ADDR+0x0004); (DMAMUX_BASE_ADDR+0x000B); (DMAMUX_BASE_ADDR+0x000A); (DMAMUX_BASE_ADDR+0x0009); (DMAMUX_BASE_ADDR+0x0008); (DMAMUX_BASE_ADDR+0x000F); (DMAMUX_BASE_ADDR+0x000E); K22F Sub-Family Reference Manual, Rev. 4, 08/2016 402 NXP Semiconductors Chapter 21 Direct Memory Access Multiplexer (DMAMUX) volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); In File main.c: #include "registers.h" : : *CHCFG1 = 0x00; *CHCFG1 = 0x85; To disable a source: A particular DMA source may be disabled by not writing the corresponding source value into any of the CHCFG registers. Additionally, some module-specific configuration may be necessary. See the appropriate section for more details. To switch the source of a DMA channel: 1. Disable the DMA channel in the DMA and reconfigure the channel for the new source. 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel. 3. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are set. To switch DMA channel 8 from source #5 transmit to source #7 transmit: 1. In the DMA configuration registers, disable DMA channel 8 and reconfigure it to handle the transfers to peripheral slot 7. This example assumes channel 8 doesn't have triggering capability. 2. Write 0x00 to CHCFG8. 3. Write 0x87 to CHCFG8. (In this example, setting CHCFG[TRIG] would have no effect due to the assumption that channel 8 does not support the periodic triggering functionality.) The following code example illustrates steps 2 and 3 above: In File registers.h: #define DMAMUX_BASE_ADDR 0x40021000/* Example only ! /* Following example assumes char is 8-bits */ volatile unsigned char *CHCFG0 = (volatile unsigned char volatile unsigned char *CHCFG1 = (volatile unsigned char volatile unsigned char *CHCFG2 = (volatile unsigned char volatile unsigned char *CHCFG3 = (volatile unsigned char volatile unsigned char *CHCFG4 = (volatile unsigned char volatile unsigned char *CHCFG5 = (volatile unsigned char volatile unsigned char *CHCFG6 = (volatile unsigned char volatile unsigned char *CHCFG7 = (volatile unsigned char volatile unsigned char *CHCFG8 = (volatile unsigned char volatile unsigned char *CHCFG9 = (volatile unsigned char volatile unsigned char *CHCFG10= (volatile unsigned char volatile unsigned char *CHCFG11= (volatile unsigned char volatile unsigned char *CHCFG12= (volatile unsigned char volatile unsigned char *CHCFG13= (volatile unsigned char volatile unsigned char *CHCFG14= (volatile unsigned char volatile unsigned char *CHCFG15= (volatile unsigned char */ *) *) *) *) *) *) *) *) *) *) *) *) *) *) *) *) (DMAMUX_BASE_ADDR+0x0003); (DMAMUX_BASE_ADDR+0x0002); (DMAMUX_BASE_ADDR+0x0001); (DMAMUX_BASE_ADDR+0x0000); (DMAMUX_BASE_ADDR+0x0007); (DMAMUX_BASE_ADDR+0x0006); (DMAMUX_BASE_ADDR+0x0005); (DMAMUX_BASE_ADDR+0x0004); (DMAMUX_BASE_ADDR+0x000B); (DMAMUX_BASE_ADDR+0x000A); (DMAMUX_BASE_ADDR+0x0009); (DMAMUX_BASE_ADDR+0x0008); (DMAMUX_BASE_ADDR+0x000F); (DMAMUX_BASE_ADDR+0x000E); (DMAMUX_BASE_ADDR+0x000D); (DMAMUX_BASE_ADDR+0x000C); K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 403 Initialization/application information In File main.c: #include "registers.h" : : *CHCFG8 = 0x00; *CHCFG8 = 0x87; K22F Sub-Family Reference Manual, Rev. 4, 08/2016 404 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) 22.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data transfers with minimal intervention from a host processor. The hardware microarchitecture includes: * A DMA engine that performs: * Source address and destination address calculations * Data-movement operations * Local memory containing transfer control descriptors for each of the 4 channels 22.1.1 eDMA system block diagram Figure 22-1 illustrates the components of the eDMA system, including the eDMA module ("engine"). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 405 Introduction eDMA system Write Address Write Data 0 Transfer Control Descriptor (TCD) n-1 64 eDMA e ngine Program Model/ Channel Arbitration Read Data Read Data Internal Peripheral Bus To/From Crossbar Switch 1 2 Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 22-1. eDMA system block diagram 22.1.2 Block parts The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-control descriptor local memory. The eDMA engine is further partitioned into four submodules: Table 22-1. eDMA engine submodules Submodule Address path Function This block implements registered versions of two channel transfer control descriptors, channel x and channel y, and manages all master bus-address calculations. All the channels provide the same functionality. This structure allows data transfers associated with one channel to be preempted after the completion of a read/write sequence if a higher priority channel activation is asserted while the first channel is active. After a channel is activated, it runs until the minor loop is completed, unless preempted by a higher priority channel. This provides a mechanism (enabled by DCHPRIn[ECP]) where a large data move operation can be preempted to minimize the time another channel is blocked from execution. When any channel is selected to execute, the contents of its TCD are read from local memory and loaded into the address path channel x registers for a normal start and into channel y registers for a preemption start. After the minor loop completes execution, the address path hardware writes Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 406 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) Table 22-1. eDMA engine submodules (continued) Submodule Function the new values for the TCDn_{SADDR, DADDR, CITER} back to local memory. If the major iteration count is exhausted, additional processing is performed, including the final address pointer updates, reloading the TCDn_CITER field, and a possible fetch of the next TCDn from memory as part of a scatter/gather operation. Data path This block implements the bus master read/write datapath. It includes a data buffer and the necessary multiplex logic to support any required data alignment. The internal read data bus is the primary input, and the internal write data bus is the primary output. The address and data path modules directly support the 2-stage pipelined internal bus. The address path module represents the 1st stage of the bus pipeline (address phase), while the data path module implements the 2nd stage of the pipeline (data phase). Program model/channel arbitration This block implements the first section of the eDMA programming model as well as the channel arbitration logic. The programming model registers are connected to the internal peripheral bus. The eDMA peripheral request inputs and interrupt request outputs are also connected to this block (via control logic). Control This block provides all the control functions for the eDMA engine. For data transfers where the source and destination sizes are equal, the eDMA engine performs a series of source read/ destination write operations until the number of bytes specified in the minor loop byte count has moved. For descriptors where the sizes are not equal, multiple accesses of the smaller size data are required for each reference of the larger size. As an example, if the source size references 16bit data and the destination is 32-bit data, two reads are performed, then one 32-bit write. The transfer-control descriptor local memory is further partitioned into: Table 22-2. Transfer control descriptor memory Submodule Description Memory controller This logic implements the required dual-ported controller, managing accesses from the eDMA engine as well as references from the internal peripheral bus. As noted earlier, in the event of simultaneous accesses, the eDMA engine is given priority and the peripheral transaction is stalled. Memory array TCD storage for each channel's transfer profile. 22.1.3 Features The eDMA is a highly programmable data-transfer engine optimized to minimize any required intervention from the host processor. It is intended for use in applications where the data size to be transferred is statically known and not defined within the transferred data itself. The eDMA module features: * All data movement via dual-address transfers: read from source, write to destination * Programmable source and destination addresses and transfer size * Support for enhanced addressing modes K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 407 Modes of operation * 4-channel implementation that performs complex data transfers with minimal intervention from a host processor * Connections to the crossbar switch for bus mastering the data movement * Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations * 32-byte TCD stored in local memory for each channel * An inner data transfer loop defined by a minor byte transfer count * An outer data transfer loop defined by a major iteration count * Channel activation via one of three methods: * Explicit software initiation * Initiation via a channel-to-channel linking mechanism for continuous transfers * Peripheral-paced hardware requests, one per channel * Fixed-priority and round-robin channel arbitration * Channel completion reported via programmable interrupt requests * One interrupt per channel, which can be asserted at completion of major iteration count * Programmable error terminations per channel and logically summed together to form one error interrupt to the interrupt controller * Programmable support for scatter/gather DMA processing * Support for complex data structures In the discussion of this module, n is used to reference the channel number. 22.2 Modes of operation The eDMA operates in the following modes: Table 22-3. Modes of operation Mode Normal Description In Normal mode, the eDMA transfers data between a source and a destination. The source and destination can be a memory block or an I/O block capable of operation with the eDMA. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 408 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) Table 22-3. Modes of operation (continued) Mode Description A service request initiates a transfer of a specific number of bytes (NBYTES) as specified in the transfer control descriptor (TCD). The minor loop is the sequence of read-write operations that transfers these NBYTES per service request. Each service request executes one iteration of the major loop, which transfers NBYTES of data. Debug DMA operation is configurable in Debug mode via the control register: * If CR[EDBG] is cleared, the DMA continues to operate. * If CR[EDBG] is set, the eDMA stops transferring data. If Debug mode is entered while a channel is active, the eDMA continues operation until the channel retires. Wait Before entering Wait mode, the DMA attempts to complete its current transfer. After the transfer completes, the device enters Wait mode. 22.3 Memory map/register definition The eDMA's programming model is partitioned into two regions: * The first region defines a number of registers providing control functions * The second region corresponds to the local transfer control descriptor (TCD) memory 22.3.1 TCD memory Each channel requires a 32-byte transfer control descriptor for defining the desired data movement operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel 1, ... channel 3. Each TCDn definition is presented as 11 registers of 16 or 32 bits. 22.3.2 TCD initialization Prior to activating a channel, you must initialize its TCD with the appropriate transfer profile. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 409 Memory map/register definition 22.3.3 TCD structure 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0000h SMOD SSIZE DSIZE DMOD 4 3 1 2 0 { SMLOE MLOFF or NBYTES DADDR CITER.E_LINK 0010h CITER or CITER.LINKCH { NBYTES SLAST CITER DMA_CR[EMLM] disabled DMA_CR[EMLM] enabled DOFF INT_MAJ START 5 INT_HALF 6 E_SG 7 D_REQ 8 MAJOR.E_LINK 9 DONE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ACTIVE BWC BITER MAJOR.LINKCH BITER.E_LINK BITER or BITER.LINKCH Reserved DLAST_SGA 0018h 001Ch 5 SOFF 000Ch 0014h 6 NBYTES DMLOE { 7 SADDR 0004h 0008h 8 9 4 3 2 1 0 22.3.4 Reserved memory and bit fields * Reading reserved bits in a register returns the value of zero. * Writes to reserved bits in a register are ignored. * Reading or writing a reserved memory location generates a bus error. DMA memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_8000 Control Register (DMA_CR) 32 R/W See section 22.3.5/414 4000_8004 Error Status Register (DMA_ES) 32 R 0000_0000h 22.3.6/417 4000_800C Enable Request Register (DMA_ERQ) 32 R/W 0000_0000h 22.3.7/419 4000_8014 Enable Error Interrupt Register (DMA_EEI) 32 R/W 0000_0000h 22.3.8/420 4000_8018 Clear Enable Error Interrupt Register (DMA_CEEI) 8 W (always reads 0) 00h 22.3.9/421 4000_8019 Set Enable Error Interrupt Register (DMA_SEEI) 8 W (always reads 0) 00h 22.3.10/422 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 410 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_801A Clear Enable Request Register (DMA_CERQ) 8 W (always reads 0) 00h 22.3.11/423 4000_801B Set Enable Request Register (DMA_SERQ) 8 W (always reads 0) 00h 22.3.12/424 4000_801C Clear DONE Status Bit Register (DMA_CDNE) 8 W (always reads 0) 00h 22.3.13/425 4000_801D Set START Bit Register (DMA_SSRT) 8 W (always reads 0) 00h 22.3.14/426 4000_801E Clear Error Register (DMA_CERR) 8 W (always reads 0) 00h 22.3.15/427 4000_801F Clear Interrupt Request Register (DMA_CINT) 8 W (always reads 0) 00h 22.3.16/428 4000_8024 Interrupt Request Register (DMA_INT) 32 R/W 0000_0000h 22.3.17/429 4000_802C Error Register (DMA_ERR) 32 R/W 0000_0000h 22.3.18/430 4000_8034 Hardware Request Status Register (DMA_HRS) 32 R 0000_0000h 22.3.19/431 4000_8044 Enable Asynchronous Request in Stop Register (DMA_EARS) 32 R/W 0000_0000h 22.3.20/433 4000_8100 Channel n Priority Register (DMA_DCHPRI3) 8 R/W See section 22.3.21/434 4000_8101 Channel n Priority Register (DMA_DCHPRI2) 8 R/W See section 22.3.21/434 4000_8102 Channel n Priority Register (DMA_DCHPRI1) 8 R/W See section 22.3.21/434 4000_8103 Channel n Priority Register (DMA_DCHPRI0) 8 R/W See section 22.3.21/434 4000_9000 TCD Source Address (DMA_TCD0_SADDR) 32 R/W Undefined 22.3.22/435 4000_9004 TCD Signed Source Address Offset (DMA_TCD0_SOFF) 16 R/W Undefined 22.3.23/435 4000_9006 TCD Transfer Attributes (DMA_TCD0_ATTR) 16 R/W Undefined 22.3.24/436 4000_9008 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD0_NBYTES_MLNO) 32 R/W Undefined 22.3.25/437 4000_9008 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD0_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.26/437 4000_9008 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD0_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.27/439 4000_900C TCD Last Source Address Adjustment (DMA_TCD0_SLAST) 32 R/W Undefined 22.3.28/440 4000_9010 TCD Destination Address (DMA_TCD0_DADDR) 32 R/W Undefined 22.3.29/440 4000_9014 TCD Signed Destination Address Offset (DMA_TCD0_DOFF) 16 R/W Undefined 22.3.30/441 4000_9016 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD0_CITER_ELINKYES) 16 R/W Undefined 22.3.31/441 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 411 Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_9016 DMA_TCD0_CITER_ELINKNO 16 R/W Undefined 22.3.32/443 4000_9018 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD0_DLASTSGA) 32 R/W Undefined 22.3.33/444 4000_901C TCD Control and Status (DMA_TCD0_CSR) 16 R/W Undefined 22.3.34/444 4000_901E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD0_BITER_ELINKYES) 16 R/W Undefined 22.3.35/447 4000_901E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD0_BITER_ELINKNO) 16 R/W Undefined 22.3.36/448 4000_9020 TCD Source Address (DMA_TCD1_SADDR) 32 R/W Undefined 22.3.22/435 4000_9024 TCD Signed Source Address Offset (DMA_TCD1_SOFF) 16 R/W Undefined 22.3.23/435 4000_9026 TCD Transfer Attributes (DMA_TCD1_ATTR) 16 R/W Undefined 22.3.24/436 4000_9028 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD1_NBYTES_MLNO) 32 R/W Undefined 22.3.25/437 4000_9028 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD1_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.26/437 4000_9028 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD1_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.27/439 4000_902C TCD Last Source Address Adjustment (DMA_TCD1_SLAST) 32 R/W Undefined 22.3.28/440 4000_9030 TCD Destination Address (DMA_TCD1_DADDR) 32 R/W Undefined 22.3.29/440 4000_9034 TCD Signed Destination Address Offset (DMA_TCD1_DOFF) 16 R/W Undefined 22.3.30/441 4000_9036 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD1_CITER_ELINKYES) 16 R/W Undefined 22.3.31/441 4000_9036 DMA_TCD1_CITER_ELINKNO 16 R/W Undefined 22.3.32/443 4000_9038 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD1_DLASTSGA) 32 R/W Undefined 22.3.33/444 4000_903C TCD Control and Status (DMA_TCD1_CSR) 16 R/W Undefined 22.3.34/444 4000_903E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD1_BITER_ELINKYES) 16 R/W Undefined 22.3.35/447 4000_903E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD1_BITER_ELINKNO) 16 R/W Undefined 22.3.36/448 4000_9040 TCD Source Address (DMA_TCD2_SADDR) 32 R/W Undefined 22.3.22/435 4000_9044 TCD Signed Source Address Offset (DMA_TCD2_SOFF) 16 R/W Undefined 22.3.23/435 4000_9046 TCD Transfer Attributes (DMA_TCD2_ATTR) 16 R/W Undefined 22.3.24/436 4000_9048 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD2_NBYTES_MLNO) 32 R/W Undefined 22.3.25/437 4000_9048 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD2_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.26/437 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 412 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_9048 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD2_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.27/439 4000_904C TCD Last Source Address Adjustment (DMA_TCD2_SLAST) 32 R/W Undefined 22.3.28/440 4000_9050 TCD Destination Address (DMA_TCD2_DADDR) 32 R/W Undefined 22.3.29/440 4000_9054 TCD Signed Destination Address Offset (DMA_TCD2_DOFF) 16 R/W Undefined 22.3.30/441 4000_9056 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD2_CITER_ELINKYES) 16 R/W Undefined 22.3.31/441 4000_9056 DMA_TCD2_CITER_ELINKNO 16 R/W Undefined 22.3.32/443 4000_9058 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD2_DLASTSGA) 32 R/W Undefined 22.3.33/444 4000_905C TCD Control and Status (DMA_TCD2_CSR) 16 R/W Undefined 22.3.34/444 4000_905E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD2_BITER_ELINKYES) 16 R/W Undefined 22.3.35/447 4000_905E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD2_BITER_ELINKNO) 16 R/W Undefined 22.3.36/448 4000_9060 TCD Source Address (DMA_TCD3_SADDR) 32 R/W Undefined 22.3.22/435 4000_9064 TCD Signed Source Address Offset (DMA_TCD3_SOFF) 16 R/W Undefined 22.3.23/435 4000_9066 TCD Transfer Attributes (DMA_TCD3_ATTR) 16 R/W Undefined 22.3.24/436 4000_9068 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD3_NBYTES_MLNO) 32 R/W Undefined 22.3.25/437 4000_9068 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD3_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.26/437 4000_9068 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD3_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.27/439 4000_906C TCD Last Source Address Adjustment (DMA_TCD3_SLAST) 32 R/W Undefined 22.3.28/440 4000_9070 TCD Destination Address (DMA_TCD3_DADDR) 32 R/W Undefined 22.3.29/440 4000_9074 TCD Signed Destination Address Offset (DMA_TCD3_DOFF) 16 R/W Undefined 22.3.30/441 4000_9076 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD3_CITER_ELINKYES) 16 R/W Undefined 22.3.31/441 4000_9076 DMA_TCD3_CITER_ELINKNO 16 R/W Undefined 22.3.32/443 4000_9078 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD3_DLASTSGA) 32 R/W Undefined 22.3.33/444 4000_907C TCD Control and Status (DMA_TCD3_CSR) 16 R/W Undefined 22.3.34/444 4000_907E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD3_BITER_ELINKYES) 16 R/W Undefined 22.3.35/447 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 413 Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name 4000_907E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD3_BITER_ELINKNO) Width Access (in bits) 16 R/W Reset value Section/ page Undefined 22.3.36/448 22.3.5 Control Register (DMA_CR) The CR defines the basic operating configuration of the DMA. Arbitration can be configured to use either a fixed-priority or a round-robin scheme. For fixed-priority arbitration, the highest priority channel requesting service is selected to execute. The channel priority registers assign the priorities; see the DCHPRIn registers. For round-robin arbitration, the channel priorities are ignored and channels are cycled through (from high to low channel number) without regard to priority. NOTE For correct operation, writes to the CR register must be performed only when the DMA channels are inactive; that is, when TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon minor loop completion. When minor loop offsets are enabled, the minor loop offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final destination address (TCDn_DADDR), or to both prior to the addresses being written back into the TCD. If the major loop is complete, the minor loop offset is ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2 is used to specify multiple fields: a source enable bit (SMLOE) to specify the minor loop offset should be applied to the source address (TCDn_SADDR) upon minor loop completion, a destination enable bit (DMLOE) to specify the minor loop offset should be applied to the destination address (TCDn_DADDR) upon minor loop completion, and the sign extended minor loop offset value (MLOFF). The same offset value (MLOFF) is used for both source and destination minor loop offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are assigned to the NBYTES field. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 414 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) Bit 31 R ACTIVE Address: 4000_8000h base + 0h offset = 4000_8000h 30 29 28 27 26 25 24 23 22 21 Reserved 20 19 18 17 16 CX ECX 0 Reset 0 x* x* x* x* x* x* x* 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EMLM CLM HALT HOE Reserved ERCA EDBG Reserved W 0 0 0 0 0 0 0 0 0 R W Reset 0 0 0 0 0 0 0 0 * Notes: * x = Undefined at reset. DMA_CR field descriptions Field 31 ACTIVE Description DMA Active Status 0 1 eDMA is idle. eDMA is executing a channel. 30-24 Reserved This field is reserved. Reserved 23-18 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 17 CX Cancel Transfer 0 1 Normal operation Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 415 Memory map/register definition DMA_CR field descriptions (continued) Field 16 ECX 15-8 Reserved 7 EMLM 6 CLM Description Error Cancel Transfer 0 1 Normal operation Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. This field is reserved. This read-only field is reserved and always has the value 0. Enable Minor Loop Mapping 0 1 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. Continuous Link Mode NOTE: Do not use continuous link mode with a channel linking to itself if there is only one minor loop iteration per service request, e.g., if the channel's NBYTES value is the same as either the source or destination size. The same data transfer profile can be achieved by simply increasing the NBYTES value, which provides more efficient, faster processing. 0 1 A minor loop channel link made to itself goes through channel arbitration before being activated again. A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. 5 HALT Halt DMA Operations 4 HOE Halt On Error 3 Reserved 0 1 0 1 Normal operation Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. Normal operation Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. This field is reserved. Reserved 2 ERCA Enable Round Robin Channel Arbitration 1 EDBG Enable Debug 0 1 0 1 Fixed priority arbitration is used for channel selection . Round robin arbitration is used for channel selection . When in debug mode, the DMA continues to operate. When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 416 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_CR field descriptions (continued) Field Description 0 Reserved This field is reserved. Reserved 22.3.6 Error Status Register (DMA_ES) The ES provides information concerning the last recorded channel error. Channel errors can be caused by: * A configuration error, that is: * An illegal setting in the transfer-control descriptor, or * An illegal priority register setting in fixed-arbitration * An error termination to a bus master read or write cycle * A cancel transfer with error bit that will be set when a transfer is canceled via the corresponding cancel transfer control bit See Fault reporting and handling for more details. Address: 4000_8000h base + 4h offset = 4000_8004h Bit 31 R VLD 30 29 28 27 26 25 24 23 22 21 20 19 18 17 0 16 ECX W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CPE SAE SOE DAE DOE NCE SGE SBE DBE 0 0 0 0 0 0 0 0 0 0 0 ERRCHN W Reset 0 0 0 0 0 0 DMA_ES field descriptions Field 31 VLD 30-17 Reserved 16 ECX Description Logical OR of all ERR status bits 0 1 No ERR bits are set. At least one ERR bit is set indicating a valid error exists that has not been cleared. This field is reserved. This read-only field is reserved and always has the value 0. Transfer Canceled 0 1 No canceled transfers The last recorded entry was a canceled transfer by the error cancel transfer input Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 417 Memory map/register definition DMA_ES field descriptions (continued) Field 15 Reserved 14 CPE Description This field is reserved. This read-only field is reserved and always has the value 0. Channel Priority Error 0 1 No channel priority error The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique. 13-10 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 9-8 ERRCHN Error Channel Number or Canceled Channel Number The channel number of the last recorded error, excluding CPE errors, or last recorded error canceled transfer. 7 SAE Source Address Error 6 SOE Source Offset Error 5 DAE Destination Address Error 4 DOE Destination Offset Error 3 NCE NBYTES/CITER Configuration Error 2 SGE Scatter/Gather Configuration Error 1 SBE Source Bus Error 0 1 0 1 0 1 0 1 0 1 0 1 No source address configuration error. The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. No source offset configuration error The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. No destination address configuration error The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. No destination offset configuration error The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. No NBYTES/CITER configuration error The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. * TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or * TCDn_CITER[CITER] is equal to zero, or * TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] No scatter/gather configuration error The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 418 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_ES field descriptions (continued) Field Description 0 1 0 DBE No source bus error The last recorded error was a bus error on a source read Destination Bus Error 0 1 No destination bus error The last recorded error was a bus error on a destination write 22.3.7 Enable Request Register (DMA_ERQ) The ERQ register provides a bit map for the 4 channels to enable the request signal for each channel. The state of any given channel enable is directly affected by writes to this register; it is also affected by writes to the SERQ and CERQ registers. These registers are provided so the request enable for a single channel can easily be modified without needing to perform a read-modify-write sequence to the ERQ. DMA request input signals and this enable request flag must be asserted before a channel's hardware service request is accepted. The state of the DMA enable request flag does not affect a channel service request made explicitly through software or a linked channel request. Address: 4000_8000h base + Ch offset = 4000_800Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R ERQ3 ERQ2 ERQ1 ERQ0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_ERQ field descriptions Field 31-4 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 3 ERQ3 Enable DMA Request 3 2 ERQ2 Enable DMA Request 2 0 1 0 1 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 419 Memory map/register definition DMA_ERQ field descriptions (continued) Field Description 1 ERQ1 Enable DMA Request 1 0 ERQ0 Enable DMA Request 0 0 1 0 1 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled 22.3.8 Enable Error Interrupt Register (DMA_EEI) The EEI register provides a bit map for the 4 channels to enable the error interrupt signal for each channel. The state of any given channel's error interrupt enable is directly affected by writes to this register; it is also affected by writes to the SEEI and CEEI. These registers are provided so that the error interrupt enable for a single channel can easily be modified without the need to perform a read-modify-write sequence to the EEI register. The DMA error indicator and the error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted to the interrupt controller. Address: 4000_8000h base + 14h offset = 4000_8014h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W Reset 0 0 0 0 0 0 Bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 EEI3 EEI2 EEI1 EEI0 0 0 0 0 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 DMA_EEI field descriptions Field 31-4 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 3 EEI3 Enable Error Interrupt 3 2 EEI2 Enable Error Interrupt 2 0 1 0 1 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 420 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_EEI field descriptions (continued) Field Description 1 EEI1 Enable Error Interrupt 1 0 EEI0 Enable Error Interrupt 0 0 1 0 1 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request 22.3.9 Clear Enable Error Interrupt Register (DMA_CEEI) The CEEI provides a simple memory-mapped mechanism to clear a given bit in the EEI to disable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EEI to be cleared. Setting the CAEE bit provides a global clear function, forcing the EEI contents to be cleared, disabling all DMA request inputs. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 18h offset = 4000_8018h Bit 7 6 Read 0 0 Write NOP CAEE Reset 0 0 5 4 3 2 1 0 0 0 0 0 CEEI 0 0 0 0 DMA_CEEI field descriptions Field Description 7 NOP No Op enable 6 CAEE Clear All Enable Error Interrupts 5-2 Reserved CEEI 0 1 0 1 Normal operation No operation, ignore the other bits in this register Clear only the EEI bit specified in the CEEI field Clear all bits in EEI This field is reserved. Clear Enable Error Interrupt Clears the corresponding bit in EEI K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 421 Memory map/register definition 22.3.10 Set Enable Error Interrupt Register (DMA_SEEI) The SEEI provides a simple memory-mapped mechanism to set a given bit in the EEI to enable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EEI to be set. Setting the SAEE bit provides a global set function, forcing the entire EEI contents to be set. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 19h offset = 4000_8019h Bit 7 6 Read 0 0 Write NOP SAEE Reset 0 0 5 4 3 2 1 0 0 0 0 0 SEEI 0 0 0 0 DMA_SEEI field descriptions Field Description 7 NOP No Op enable 6 SAEE Sets All Enable Error Interrupts 5-2 Reserved SEEI 0 1 0 1 Normal operation No operation, ignore the other bits in this register Set only the EEI bit specified in the SEEI field. Sets all bits in EEI This field is reserved. Set Enable Error Interrupt Sets the corresponding bit in EEI K22F Sub-Family Reference Manual, Rev. 4, 08/2016 422 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) 22.3.11 Clear Enable Request Register (DMA_CERQ) The CERQ provides a simple memory-mapped mechanism to clear a given bit in the ERQ to disable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be cleared. Setting the CAER bit provides a global clear function, forcing the entire contents of the ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Ah offset = 4000_801Ah Bit 7 6 Read 0 0 Write NOP CAER Reset 0 0 5 4 3 2 1 0 0 0 0 0 CERQ 0 0 0 0 DMA_CERQ field descriptions Field 7 NOP 6 CAER Description No Op enable 0 1 Normal operation No operation, ignore the other bits in this register Clear All Enable Requests 0 1 Clear only the ERQ bit specified in the CERQ field Clear all bits in ERQ 5-2 Reserved This field is reserved. CERQ Clear Enable Request Clears the corresponding bit in ERQ. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 423 Memory map/register definition 22.3.12 Set Enable Request Register (DMA_SERQ) The SERQ provides a simple memory-mapped mechanism to set a given bit in the ERQ to enable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be set. Setting the SAER bit provides a global set function, forcing the entire contents of ERQ to be set. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Bh offset = 4000_801Bh Bit 7 6 Read 0 0 Write NOP SAER Reset 0 0 5 4 3 2 1 0 0 0 0 0 SERQ 0 0 0 0 DMA_SERQ field descriptions Field Description 7 NOP No Op enable 6 SAER Set All Enable Requests 0 1 0 1 Normal operation No operation, ignore the other bits in this register Set only the ERQ bit specified in the SERQ field Set all bits in ERQ 5-2 Reserved This field is reserved. SERQ Set Enable Request Sets the corresponding bit in ERQ. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 424 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) 22.3.13 Clear DONE Status Bit Register (DMA_CDNE) The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in the TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding transfer control descriptor to be cleared. Setting the CADN bit provides a global clear function, forcing all DONE bits to be cleared. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Ch offset = 4000_801Ch Bit 7 6 Read 0 0 Write NOP CADN Reset 0 0 5 4 3 2 1 0 0 0 0 0 CDNE 0 0 0 0 DMA_CDNE field descriptions Field 7 NOP Description No Op enable 0 1 Normal operation No operation, ignore the other bits in this register 6 CADN Clears All DONE Bits 5-2 Reserved This field is reserved. CDNE 0 1 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field Clears all bits in TCDn_CSR[DONE] Clear DONE Bit Clears the corresponding bit in TCDn_CSR[DONE] K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 425 Memory map/register definition 22.3.14 Set START Bit Register (DMA_SSRT) The SSRT provides a simple memory-mapped mechanism to set the START bit in the TCD of the given channel. The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set. Setting the SAST bit provides a global set function, forcing all START bits to be set. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Dh offset = 4000_801Dh Bit 7 6 Read 0 0 Write NOP SAST Reset 0 0 5 4 3 2 1 0 0 0 0 0 SSRT 0 0 0 0 DMA_SSRT field descriptions Field Description 7 NOP No Op enable 6 SAST Set All START Bits (activates all channels) 5-2 Reserved SSRT 0 1 0 1 Normal operation No operation, ignore the other bits in this register Set only the TCDn_CSR[START] bit specified in the SSRT field Set all bits in TCDn_CSR[START] This field is reserved. Set START Bit Sets the corresponding bit in TCDn_CSR[START] K22F Sub-Family Reference Manual, Rev. 4, 08/2016 426 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) 22.3.15 Clear Error Register (DMA_CERR) The CERR provides a simple memory-mapped mechanism to clear a given bit in the ERR to disable the error condition flag for a given channel. The given value on a register write causes the corresponding bit in the ERR to be cleared. Setting the CAEI bit provides a global clear function, forcing the ERR contents to be cleared, clearing all channel error indicators. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Eh offset = 4000_801Eh Bit 7 6 Read 0 0 Write NOP CAEI Reset 0 0 5 4 3 2 1 0 0 0 0 0 CERR 0 0 0 0 DMA_CERR field descriptions Field Description 7 NOP No Op enable 6 CAEI Clear All Error Indicators 0 1 0 1 Normal operation No operation, ignore the other bits in this register Clear only the ERR bit specified in the CERR field Clear all bits in ERR 5-2 Reserved This field is reserved. CERR Clear Error Indicator Clears the corresponding bit in ERR K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 427 Memory map/register definition 22.3.16 Clear Interrupt Request Register (DMA_CINT) The CINT provides a simple, memory-mapped mechanism to clear a given bit in the INT to disable the interrupt request for a given channel. The given value on a register write causes the corresponding bit in the INT to be cleared. Setting the CAIR bit provides a global clear function, forcing the entire contents of the INT to be cleared, disabling all DMA interrupt requests. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Fh offset = 4000_801Fh Bit 7 6 Read 0 0 Write NOP CAIR Reset 0 0 5 4 3 2 1 0 0 0 0 0 CINT 0 0 0 0 DMA_CINT field descriptions Field Description 7 NOP No Op enable 6 CAIR Clear All Interrupt Requests 5-2 Reserved CINT 0 1 0 1 Normal operation No operation, ignore the other bits in this register Clear only the INT bit specified in the CINT field Clear all bits in INT This field is reserved. Clear Interrupt Request Clears the corresponding bit in INT K22F Sub-Family Reference Manual, Rev. 4, 08/2016 428 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) 22.3.17 Interrupt Request Register (DMA_INT) The INT register provides a bit map for the 4 channels signaling the presence of an interrupt request for each channel. Depending on the appropriate bit setting in the transfer-control descriptors, the eDMA engine generates an interrupt on data transfer completion. The outputs of this register are directly routed to the interrupt controller. During the interrupt-service routine associated with any given channel, it is the software's responsibility to clear the appropriate bit, negating the interrupt request. Typically, a write to the CINT register in the interrupt service routine is used for this purpose. The state of any given channel's interrupt request is directly affected by writes to this register; it is also affected by writes to the CINT register. On writes to INT, a 1 in any bit position clears the corresponding channel's interrupt request. A zero in any bit position has no affect on the corresponding channel's current interrupt status. The CINT register is provided so the interrupt request for a single channel can easily be cleared without the need to perform a read-modify-write sequence to the INT register. Address: 4000_8000h base + 24h offset = 4000_8024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT3 INT2 INT1 INT0 w1c w1c w1c w1c 0 0 0 0 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 DMA_INT field descriptions Field 31-4 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 3 INT3 Interrupt Request 3 2 INT2 Interrupt Request 2 1 INT1 Interrupt Request 1 0 1 0 1 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 429 Memory map/register definition DMA_INT field descriptions (continued) Field Description 0 1 0 INT0 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Interrupt Request 0 0 1 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active 22.3.18 Error Register (DMA_ERR) The ERR provides a bit map for the 4 channels, signaling the presence of an error for each channel. The eDMA engine signals the occurrence of an error condition by setting the appropriate bit in this register. The outputs of this register are enabled by the contents of the EEI, and then routed to the interrupt controller. During the execution of the interrupt-service routine associated with any DMA errors, it is software's responsibility to clear the appropriate bit, negating the error-interrupt request. Typically, a write to the CERR in the interrupt-service routine is used for this purpose. The normal DMA channel completion indicators (setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request) are not affected when an error is detected. The contents of this register can also be polled because a non-zero value indicates the presence of a channel error regardless of the state of the EEI. The state of any given channel's error indicators is affected by writes to this register; it is also affected by writes to the CERR. On writes to the ERR, a one in any bit position clears the corresponding channel's error status. A zero in any bit position has no affect on the corresponding channel's current error status. The CERR is provided so the error indicator for a single channel can easily be cleared. Address: 4000_8000h base + 2Ch offset = 4000_802Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R ERR3 ERR2 ERR1 ERR0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 w1c w1c w1c w1c 0 0 0 0 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 430 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_ERR field descriptions Field Description 31-4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 ERR3 Error In Channel 3 2 ERR2 Error In Channel 2 1 ERR1 Error In Channel 1 0 ERR0 Error In Channel 0 0 1 0 1 0 1 0 1 An error in this channel has not occurred An error in this channel has occurred An error in this channel has not occurred An error in this channel has occurred An error in this channel has not occurred An error in this channel has occurred An error in this channel has not occurred An error in this channel has occurred 22.3.19 Hardware Request Status Register (DMA_HRS) The HRS register provides a bit map for the DMA channels, signaling the presence of a hardware request for each channel. The hardware request status bits reflect the current state of the register and qualified (via the ERQ fields) DMA request signals as seen by the DMA's arbitration logic. This view into the hardware request signals may be used for debug purposes. NOTE These bits reflect the state of the request as seen by the arbitration logic. Therefore, this status is affected by the ERQ bits. Address: 4000_8000h base + 34h offset = 4000_8034h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R HRS3 HRS2 HRS1 HRS0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 431 Memory map/register definition DMA_HRS field descriptions Field 31-4 Reserved 3 HRS3 Description This field is reserved. This read-only field is reserved and always has the value 0. Hardware Request Status Channel 3 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. 0 1 2 HRS2 Hardware Request Status Channel 2 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. 0 1 1 HRS1 A hardware service request for channel 2 is not present A hardware service request for channel 2 is present Hardware Request Status Channel 1 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. 0 1 0 HRS0 A hardware service request for channel 3 is not present A hardware service request for channel 3 is present A hardware service request for channel 1 is not present A hardware service request for channel 1 is present Hardware Request Status Channel 0 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. 0 1 A hardware service request for channel 0 is not present A hardware service request for channel 0 is present K22F Sub-Family Reference Manual, Rev. 4, 08/2016 432 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) 22.3.20 Enable Asynchronous Request in Stop Register (DMA_EARS) Address: 4000_8000h base + 44h offset = 4000_8044h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EDREQ_3 EDREQ_2 EDREQ_1 EDREQ_0 W 0 0 0 0 0 0 0 0 0 0 0 R W Reset 0 0 0 0 0 0 DMA_EARS field descriptions Field Description 31-4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 EDREQ_3 Enable asynchronous DMA request in stop mode for channel 3. 2 EDREQ_2 Enable asynchronous DMA request in stop mode for channel 2. 1 EDREQ_1 Enable asynchronous DMA request in stop mode for channel 1. 0 EDREQ_0 Enable asynchronous DMA request in stop mode for channel 0. 0 1 0 1 0 1 0 1 Disable asynchronous DMA request for channel 3. Enable asynchronous DMA request for channel 3. Disable asynchronous DMA request for channel 2. Enable asynchronous DMA request for channel 2. Disable asynchronous DMA request for channel 1 Enable asynchronous DMA request for channel 1. Disable asynchronous DMA request for channel 0. Enable asynchronous DMA request for channel 0. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 433 Memory map/register definition 22.3.21 Channel n Priority Register (DMA_DCHPRIn) When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the contents of these registers define the unique priorities associated with each channel. The channel priorities are evaluated by numeric value; for example, 0 is the lowest priority, 1 is the next higher priority, then 2, 3, etc. Software must program the channel priorities with unique values; otherwise, a configuration error is reported. The range of the priority value is limited to the values of 0 through 3. Address: 4000_8000h base + 100h offset + (1d x i), where i=0d to 3d Bit Read Write Reset 7 6 ECP DPA 0 0 5 4 3 2 1 0 0 0 0 CHPRI 0 0 * * * Notes: * CHPRI field: See bit field description. DMA_DCHPRIn field descriptions Field Description 7 ECP Enable Channel Preemption. 6 DPA Disable Preempt Ability. 5-2 Reserved CHPRI 0 1 0 1 Channel n cannot be suspended by a higher priority channel's service request. Channel n can be temporarily suspended by the service request of a higher priority channel. Channel n can suspend a lower priority channel. Channel n cannot suspend any channel, regardless of channel priority. This field is reserved. This read-only field is reserved and always has the value 0. Channel n Arbitration Priority Channel priority when fixed-priority arbitration is enabled NOTE: Reset value for the channel priority field, CHPRI, is equal to the corresponding channel number for each priority register, that is, DCHPRI3[CHPRI] = 0b11. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 434 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) 22.3.22 TCD Source Address (DMA_TCDn_SADDR) Address: 4000_8000h base + 1000h offset + (32d x i), where i=0d to 3d Bit R W Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SADDR x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_SADDR field descriptions Field SADDR Description Source Address Memory address pointing to the source data. 22.3.23 TCD Signed Source Address Offset (DMA_TCDn_SOFF) Address: 4000_8000h base + 1004h offset + (32d x i), where i=0d to 3d Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x* x* x* x* x* x* x* x* SOFF x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_SOFF field descriptions Field SOFF Description Source address signed offset Sign-extended offset applied to the current source address to form the next-state value as each source read is completed. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 435 Memory map/register definition 22.3.24 TCD Transfer Attributes (DMA_TCDn_ATTR) Address: 4000_8000h base + 1006h offset + (32d x i), where i=0d to 3d Bit Read Write Reset 15 14 13 12 11 10 SMOD x* x* x* 9 8 7 6 SSIZE x* x* x* x* 5 4 3 2 DMOD x* x* x* x* 1 0 DSIZE x* x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_ATTR field descriptions Field Description 15-11 SMOD Source Address Modulo 10-8 SSIZE Source data transfer size 0 0 Source address modulo feature is disabled This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. NOTE: Using a Reserved value causes a configuration error. 000 001 010 011 100 101 110 111 8-bit 16-bit 32-bit Reserved 16-byte 32-byte Reserved Reserved 7-3 DMOD Destination Address Modulo DSIZE Destination data transfer size See the SMOD definition See the SSIZE definition K22F Sub-Family Reference Manual, Rev. 4, 08/2016 436 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) 22.3.25 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO) This register, or one of the next two registers (TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use depends on whether minor loop mapping is disabled, enabled but not used for this channel, or enabled and used. TCD word 2 is defined as follows if: * Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions for the definition of TCD word 2. Address: 4000_8000h base + 1008h offset + (32d x i), where i=0d to 3d Bit R W Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NBYTES x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_NBYTES_MLNO field descriptions Field NBYTES Description Minor Byte Transfer Count Number of bytes to be transferred in each service request of the channel. As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted. It can, however, be stalled by using the bandwidth control field, or via preemption. After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed. NOTE: An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer. 22.3.26 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCDn_NBYTES_MLOFFNO) One of three registers (this register, TCD_NBYTES_MLNO, or TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use depends on whether minor loop mapping is disabled, enabled but not used for this channel, or enabled and used. TCD word 2 is defined as follows if: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 437 Memory map/register definition * Minor loop mapping is enabled (CR[EMLM] = 1) and * SMLOE = 0 and DMLOE = 0 If minor loop mapping is enabled and SMLOE or DMLOE is set, then refer to the TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to the TCD_NBYTES_MLNO register description. 31 30 W SMLOE DMLOE Address: 4000_8000h base + 1008h offset + (32d x i), where i=0d to 3d Bit Reset x* x* x* x* x* x* x* x* x* Bit 15 14 13 12 11 10 9 8 7 R 29 28 27 26 25 24 23 22 21 20 19 18 17 16 x* x* x* x* x* x* x* 6 5 4 3 2 1 0 x* x* x* x* x* x* x* NBYTES R NBYTES W Reset x* x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_NBYTES_MLOFFNO field descriptions Field 31 SMLOE Description Source Minor Loop Offset Enable Selects whether the minor loop offset is applied to the source address upon minor loop completion. 0 1 30 DMLOE Destination Minor Loop Offset enable Selects whether the minor loop offset is applied to the destination address upon minor loop completion. 0 1 NBYTES The minor loop offset is not applied to the SADDR The minor loop offset is applied to the SADDR The minor loop offset is not applied to the DADDR The minor loop offset is applied to the DADDR Minor Byte Transfer Count Number of bytes to be transferred in each service request of the channel. As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted. It can, however, be stalled by using the bandwidth control field, or via preemption. After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 438 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) 22.3.27 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCDn_NBYTES_MLOFFYES) One of three registers (this register, TCD_NBYTES_MLNO, or TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use depends on whether minor loop mapping is disabled, enabled but not used for this channel, or enabled and used. TCD word 2 is defined as follows if: * Minor loop mapping is enabled (CR[EMLM] = 1) and * Minor loop offset is enabled (SMLOE or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared, then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop mapping is disabled, then refer to the TCD_NBYTES_MLNO register description. 31 30 W SMLOE DMLOE Address: 4000_8000h base + 1008h offset + (32d x i), where i=0d to 3d Bit Reset x* x* x* x* x* x* x* x* x* Bit 15 14 13 12 11 10 9 8 7 R 29 28 27 26 25 24 23 22 21 20 19 18 17 16 x* x* x* x* x* x* x* 6 5 4 3 2 1 0 x* x* x* x* MLOFF R MLOFF NBYTES W Reset x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_NBYTES_MLOFFYES field descriptions Field 31 SMLOE Description Source Minor Loop Offset Enable Selects whether the minor loop offset is applied to the source address upon minor loop completion. 0 1 30 DMLOE The minor loop offset is not applied to the SADDR The minor loop offset is applied to the SADDR Destination Minor Loop Offset enable Selects whether the minor loop offset is applied to the destination address upon minor loop completion. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 439 Memory map/register definition DMA_TCDn_NBYTES_MLOFFYES field descriptions (continued) Field Description 0 1 29-10 MLOFF The minor loop offset is not applied to the DADDR The minor loop offset is applied to the DADDR If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. NBYTES Minor Byte Transfer Count Number of bytes to be transferred in each service request of the channel. As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted. It can, however, be stalled by using the bandwidth control field, or via preemption. After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed. 22.3.28 TCD Last Source Address Adjustment (DMA_TCDn_SLAST) Address: 4000_8000h base + 100Ch offset + (32d x i), where i=0d to 3d Bit R W Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLAST x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_SLAST field descriptions Field Description SLAST Last Source Address Adjustment Adjustment value added to the source address at the completion of the major iteration count. This value can be applied to restore the source address to the initial value, or adjust the address to reference the next data structure. This register uses two's complement notation; the overflow bit is discarded. 22.3.29 TCD Destination Address (DMA_TCDn_DADDR) Address: 4000_8000h base + 1010h offset + (32d x i), where i=0d to 3d Bit R W Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DADDR x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 440 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_TCDn_DADDR field descriptions Field DADDR Description Destination Address Memory address pointing to the destination data. 22.3.30 TCD Signed Destination Address Offset (DMA_TCDn_DOFF) Address: 4000_8000h base + 1014h offset + (32d x i), where i=0d to 3d Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x* x* x* x* x* x* x* x* DOFF x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_DOFF field descriptions Field DOFF Description Destination Address Signed Offset Sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed. 22.3.31 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_CITER_ELINKYES) If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows. Address: 4000_8000h base + 1016h offset + (32d x i), where i=0d to 3d Bit Read Write Reset Bit Read Write Reset 15 14 13 ELINK 12 11 10 9 LINKCH 0 8 CITER x* x* x* x* x* x* x* x* 7 6 5 4 3 2 1 0 x* x* x* x* CITER x* x* x* x* * Notes: * x = Undefined at reset. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 441 Memory map/register definition DMA_TCDn_CITER_ELINKYES field descriptions Field 15 ELINK Description Enable channel-to-channel linking on minor-loop complete As the channel completes the minor loop, this flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. NOTE: This bit must be equal to the BITER[ELINK] bit; otherwise, a configuration error is reported. 0 1 14-11 Reserved 10-9 LINKCH CITER The channel-to-channel linking is disabled The channel-to-channel linking is enabled This field is reserved. Minor Loop Link Channel Number If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA engine initiates a channel service request to the channel defined by this field by setting that channel's TCDn_CSR[START] bit. Current Major Iteration Count This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current major loop count for the channel. It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. After the major iteration count is exhausted, the channel performs a number of operations, for example, final source and destination address calculations, optionally generating an interrupt to signal channel completion before reloading the CITER field from the Beginning Iteration Count (BITER) field. NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. NOTE: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 442 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) 22.3.32 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_CITER_ELINKNO) If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as follows. Address: 4000_8000h base + 1016h offset + (32d x i), where i=0d to 3d Bit Read Write Reset Bit Read Write Reset 15 14 13 12 11 ELINK 10 9 8 CITER x* x* x* x* x* x* x* x* 7 6 5 4 3 2 1 0 x* x* x* x* CITER x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_CITER_ELINKNO field descriptions Field 15 ELINK Description Enable channel-to-channel linking on minor-loop complete As the channel completes the minor loop, this flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. NOTE: This bit must be equal to the BITER[ELINK] bit; otherwise, a configuration error is reported. 0 1 CITER The channel-to-channel linking is disabled The channel-to-channel linking is enabled Current Major Iteration Count This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current major loop count for the channel. It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. After the major iteration count is exhausted, the channel performs a number of operations, for example, final source and destination address calculations, optionally generating an interrupt to signal channel completion before reloading the CITER field from the Beginning Iteration Count (BITER) field. NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. NOTE: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 443 Memory map/register definition 22.3.33 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA) Address: 4000_8000h base + 1018h offset + (32d x i), where i=0d to 3d Bit R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DLASTSGA Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_DLASTSGA field descriptions Field DLASTSGA Description Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather). If (TCDn_CSR[ESG] = 0) then: * Adjustment value added to the destination address at the completion of the major iteration count. This value can apply to restore the destination address to the initial value or adjust the address to reference the next data structure. * This field uses two's complement notation for the final destination address adjustment. Otherwise: * This address points to the beginning of a 0-modulo-32-byte region containing the next transfer control descriptor to be loaded into this channel. This channel reload is performed as the major iteration count completes. The scatter/gather address must be 0-modulo-32-byte, otherwise a configuration error is reported. 22.3.34 TCD Control and Status (DMA_TCDn_CSR) Address: 4000_8000h base + 101Ch offset + (32d x i), where i=0d to 3d Bit 15 Read 14 13 12 BWC Write 11 10 9 8 MAJORLINKCH 0 Reset x* x* x* x* x* x* x* x* Bit 7 6 5 4 3 2 1 0 ACTIVE MAJORELI NK ESG DREQ INTHALF INTMAJOR START x* x* x* x* x* x* x* Read Write Reset DONE x* * Notes: * x = Undefined at reset. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 444 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_TCDn_CSR field descriptions Field 15-14 BWC Description Bandwidth Control Throttles the amount of bus bandwidth consumed by the eDMA. Generally, as the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch. 00 01 10 11 13-10 Reserved No eDMA engine stalls. Reserved eDMA engine stalls for 4 cycles after each R/W. eDMA engine stalls for 8 cycles after each R/W. This field is reserved. 9-8 Major Loop Link Channel Number MAJORLINKCH If (MAJORELINK = 0) then: * No channel-to-channel linking, or chaining, is performed after the major loop counter is exhausted. Otherwise: * After the major loop counter is exhausted, the eDMA engine initiates a channel service request at the channel defined by this field by setting that channel's TCDn_CSR[START] bit. 7 DONE Channel Done This flag indicates the eDMA has completed the major loop. The eDMA engine sets it as the CITER count reaches zero. The software clears it, or the hardware when the channel is activated. NOTE: This bit must be cleared to write the MAJORELINK or ESG bits. 6 ACTIVE 5 MAJORELINK Channel Active This flag signals the channel is currently in execution. It is set when channel service begins, and is cleared by the eDMA as the minor loop completes or when any error condition is detected. Enable channel-to-channel linking on major loop complete As the channel completes the major loop, this flag enables the linking to another channel, defined by MAJORLINKCH. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. NOTE: To support the dynamic linking coherency model, this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set. 0 1 4 ESG The channel-to-channel linking is disabled. The channel-to-channel linking is enabled. Enable Scatter/Gather Processing As the channel completes the major loop, this flag enables scatter/gather processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a memory pointer to a 0-modulo-32 address containing a 32-byte data structure loaded as the transfer control descriptor into the local memory. NOTE: To support the dynamic scatter/gather coherency model, this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set. 0 1 The current channel's TCD is normal format. The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 445 Memory map/register definition DMA_TCDn_CSR field descriptions (continued) Field 3 DREQ Description Disable Request If this flag is set, the eDMA hardware automatically clears the corresponding ERQ bit when the current major iteration count reaches zero. 0 1 2 INTHALF The channel's ERQ bit is not affected. The channel's ERQ bit is cleared when the major loop is complete. Enable an interrupt when major counter is half complete. If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT register when the current major iteration count reaches the halfway point. Specifically, the comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This halfway point interrupt request is provided to support double-buffered, also known as ping-pong, schemes or other types of data movement where the processor needs an early indication of the transfer's progress. NOTE: If BITER = 1, do not use INTHALF. Use INTMAJOR instead. 0 1 1 INTMAJOR Enable an interrupt when major iteration count completes. If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when the current major iteration count reaches zero. 0 1 0 START The half-point interrupt is disabled. The half-point interrupt is enabled. The end-of-major loop interrupt is disabled. The end-of-major loop interrupt is enabled. Channel Start If this flag is set, the channel is requesting service. The eDMA hardware automatically clears this flag after the channel begins execution. 0 1 The channel is not explicitly started. The channel is explicitly started via a software initiated service request. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 446 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) 22.3.35 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_BITER_ELINKYES) If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as follows. Address: 4000_8000h base + 101Eh offset + (32d x i), where i=0d to 3d Bit Read Write Reset Bit Read Write Reset 15 14 13 ELINK 12 11 10 9 LINKCH 0 8 BITER x* x* x* x* x* x* x* x* 7 6 5 4 3 2 1 0 x* x* x* x* BITER x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_BITER_ELINKYES field descriptions Field Description 15 ELINK Enables channel-to-channel linking on minor loop complete As the channel completes the minor loop, this flag enables the linking to another channel, defined by BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. If channel linking disables, the BITER value extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. 0 1 The channel-to-channel linking is disabled The channel-to-channel linking is enabled 14-11 Reserved This field is reserved. 10-9 LINKCH Link Channel Number If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA engine initiates a channel service request at the channel defined by this field by setting that channel's TCDn_CSR[START] bit. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. BITER Starting major iteration count As the transfer control descriptor is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER field. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 447 Memory map/register definition DMA_TCDn_BITER_ELINKYES field descriptions (continued) Field Description NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. 22.3.36 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_BITER_ELINKNO) If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined as follows. Address: 4000_8000h base + 101Eh offset + (32d x i), where i=0d to 3d Bit Read Write Reset Bit Read Write Reset 15 14 13 12 11 ELINK 10 9 8 BITER x* x* x* x* x* x* x* x* 7 6 5 4 3 2 1 0 x* x* x* x* BITER x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_BITER_ELINKNO field descriptions Field Description 15 ELINK Enables channel-to-channel linking on minor loop complete As the channel completes the minor loop, this flag enables the linking to another channel, defined by BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. If channel linking is disabled, the BITER value extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. 0 1 BITER The channel-to-channel linking is disabled The channel-to-channel linking is enabled Starting Major Iteration Count As the transfer control descriptor is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER field. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 448 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_TCDn_BITER_ELINKNO field descriptions (continued) Field Description contents of this field is reloaded into the CITER field. If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. 22.4 Functional description The operation of the eDMA is described in the following subsections. 22.4.1 eDMA basic data flow The basic flow of a data transfer can be partitioned into three segments. As shown in the following diagram, the first segment involves the channel activation: eDMA Write Address Write Data 0 Transfer Control Descriptor (TCD) 64 eDMA Engine Program Model/ Channel Arbitration Read Data n-1 Internal Peripheral Bus To/From Crossbar Switch 1 2 Read Data Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 22-2. eDMA operation, part 1 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 449 Functional description This example uses the assertion of the eDMA peripheral request signal to request service for channel n. Channel activation via software and the TCDn_CSR[START] bit follows the same basic flow as peripheral requests. The eDMA request input signal is registered internally and then routed through the eDMA engine: first through the control module, then into the program model and channel arbitration. In the next cycle, the channel arbitration performs, using the fixed-priority or round-robin algorithm. After arbitration is complete, the activated channel number is sent through the address path and converted into the required address to access the local memory for TCDn. Next, the TCD memory is accessed and the required descriptor read from the local memory and loaded into the eDMA engine address path channel x or y registers. The TCD memory is 64 bits wide to minimize the time needed to fetch the activated channel descriptor and load it into the address path channel x or y registers. The following diagram illustrates the second part of the basic data flow: eDMA Write Address Write Data To/From Crossbar Switch Transfer Control Descriptor (TCD) n-1 64 eDMA Engine Program Model/ Channel Arbitration Read Data Internal Peripheral Bus 0 1 2 Read Data Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 22-3. eDMA operation, part 2 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 450 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) The modules associated with the data transfer (address path, data path, and control) sequence through the required source reads and destination writes to perform the actual data movement. The source reads are initiated and the fetched data is temporarily stored in the data path block until it is gated onto the internal bus during the destination write. This source read/destination write processing continues until the minor byte count has transferred. After the minor byte count has moved, the final phase of the basic data flow is performed. In this segment, the address path logic performs the required updates to certain fields in the appropriate TCD, for example, SADDR, DADDR, CITER. If the major iteration count is exhausted, additional operations are performed. These include the final address adjustments and reloading of the BITER field into the CITER. Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from memory using the scatter/gather address pointer included in the descriptor (if scatter/ gather is enabled). The updates to the TCD memory and the assertion of an interrupt request are shown in the following diagram. eDMA Write Address Write Data To/From Crossbar Switch Transfer Control Descriptor (TCD) n-1 64 Internal Peripheral Bus 0 1 2 eDMA En g in e Program Model/ Channel Arbitration Read Data Read Data Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 22-4. eDMA operation, part 3 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 451 Functional description 22.4.2 Fault reporting and handling Channel errors are reported in the Error Status register (DMAx_ES) and can be caused by: * A configuration error, which is an illegal setting in the transfer-control descriptor or an illegal priority register setting in Fixed-Arbitration mode, or * An error termination to a bus master read or write cycle A configuration error is reported when the starting source or destination address, source or destination offsets, minor loop byte count, or the transfer size represent an inconsistent state. Each of these possible causes are detailed below: * The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries. * The minor loop byte count must be a multiple of the source and destination transfer sizes. * All source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively. * In fixed arbitration mode, a configuration error is caused by any two channel priorities being equal. All channel priority levels must be unique when fixed arbitration mode is enabled. NOTE When two channels have the same priority, a channel priority error exists and will be reported in the Error Status register. However, the channel number will not be reported in the Error Status register. When all of the channel priorities within a group are not unique, the channel number selected by arbitration is undetermined. To aid in Channel Priority Error (CPE) debug, set the Halt On Error bit in the DMA's Control Register. If all of the channel priorities within a group are not unique, the DMA will be halted after the CPE error is recorded. The DMA will remain halted and will not process any channel service requests. Once all of the channel priorities are set to unique numbers, the DMA may be enabled again by clearing the Halt bit. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 452 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) * If a scatter/gather operation is enabled upon channel completion, a configuration error is reported if the scatter/gather address (DLAST_SGA) is not aligned on a 32byte boundary. * If minor loop channel linking is enabled upon channel completion, a configuration error is reported when the link is attempted if the TCDn_CITER[E_LINK] bit does not equal the TCDn_BITER[E_LINK] bit. If enabled, all configuration error conditions, except the scatter/gather and minor-loop link errors, report as the channel activates and asserts an error interrupt request. A scatter/ gather configuration error is reported when the scatter/gather operation begins at major loop completion when properly enabled. A minor loop channel link configuration error is reported when the link operation is serviced at minor loop completion. If a system bus read or write is terminated with an error, the data transfer is stopped and the appropriate bus error flag set. In this case, the state of the channel's transfer control descriptor is updated by the eDMA engine with the current source address, destination address, and current iteration count at the point of the fault. When a system bus error occurs, the channel terminates after the next transfer. Due to pipeline effect, the next transfer is already in progress when the bus error is received by the eDMA. If a bus error occurs on the last read prior to beginning the write sequence, the write executes using the data captured during the bus error. If a bus error occurs on the last write prior to switching to the next read sequence, the read sequence executes before the channel terminates due to the destination bus error. A transfer may be cancelled by software with the CR[CX] bit. When a cancel transfer request is recognized, the DMA engine stops processing the channel. The current readwrite sequence is allowed to finish. If the cancel occurs on the last read-write sequence of a major or minor loop, the cancel request is discarded and the channel retires normally. The error cancel transfer is the same as a cancel transfer except the Error Status register (DMAx_ES) is updated with the cancelled channel number and ECX is set. The TCD of a cancelled channel contains the source and destination addresses of the last transfer saved in the TCD. If the channel needs to be restarted, you must re-initialize the TCD because the aforementioned fields no longer represent the original parameters. When a transfer is cancelled by the error cancel transfer mechanism, the channel number is loaded into DMA_ES[ERRCHN] and ECX and VLD are set. In addition, an error interrupt may be generated if enabled. NOTE The cancel transfer request allows the user to stop a large data transfer in the event the full data transfer is no longer needed. The cancel transfer bit does not abort the channel. It simply stops the transferring of data and then retires the channel through its normal shutdown sequence. The application K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 453 Functional description software must handle the context of the cancel. If an interrupt is desired (or not), then the interrupt should be enabled (or disabled) before the cancel request. The application software must clean up the transfer control descriptor since the full transfer did not occur. The occurrence of any error causes the eDMA engine to stop normal processing of the active channel immediately (it goes to its error processing states and the transaction to the system bus still has pipeline effect), and the appropriate channel bit in the eDMA error register is asserted. At the same time, the details of the error condition are loaded into the Error Status register (DMAx_ES). The major loop complete indicators, setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request, are not affected when an error is detected. After the error status has been updated, the eDMA engine continues operating by servicing the next appropriate channel. A channel that experiences an error condition is not automatically disabled. If a channel is terminated by an error and then issues another service request before the error is fixed, that channel executes and terminates with the same error condition. 22.4.3 Channel preemption Channel preemption is enabled on a per-channel basis by setting the DCHPRIn[ECP] bit. Channel preemption allows the executing channel's data transfers to temporarily suspend in favor of starting a higher priority channel. After the preempting channel has completed all its minor loop data transfers, the preempted channel is restored and resumes execution. After the restored channel completes one read/write sequence, it is again eligible for preemption. If any higher priority channel is requesting service, the restored channel is suspended and the higher priority channel is serviced. Nested preemption, that is, attempting to preempt a preempting channel, is not supported. After a preempting channel begins execution, it cannot be preempted. Preemption is available only when fixed arbitration is selected. A channel's ability to preempt another channel can be disabled by setting DCHPRIn[DPA]. When a channel's preempt ability is disabled, that channel cannot suspend a lower priority channel's data transfer, regardless of the lower priority channel's ECP setting. This allows for a pool of low priority, large data-moving channels to be defined. These low priority channels can be configured to not preempt each other, thus preventing a low priority channel from consuming the preempt slot normally available to a true, high priority channel. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 454 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) 22.4.4 Performance This section addresses the performance of the eDMA module, focusing on two separate metrics: * In the traditional data movement context, performance is best expressed as the peak data transfer rates achieved using the eDMA. In most implementations, this transfer rate is limited by the speed of the source and destination address spaces. * In a second context where device-paced movement of single data values to/from peripherals is dominant, a measure of the requests that can be serviced in a fixed time is a more relevant metric. In this environment, the speed of the source and destination address spaces remains important. However, the microarchitecture of the eDMA also factors significantly into the resulting metric. 22.4.4.1 Peak transfer rates The peak transfer rates for several different source and destination transfers are shown in the following tables. These tables assume: * Internal SRAM can be accessed with zero wait-states when viewed from the system bus data phase * All internal peripheral bus reads require two wait-states, and internal peripheral bus writes three wait-states, when viewed from the system bus data phase * All internal peripheral bus accesses are 32-bits in size NOTE All architectures will not meet the assumptions listed above. See the SRAM configuration section for more information. This table compares peak transfer rates based on different possible system speeds. Specific chips/devices may not support all system speeds listed. Table 22-4. eDMA peak transfer rates (Mbytes/sec) Internal SRAM-to- Internal SRAM-to-32 bit Internal SRAM 32 bit internal peripheral bus-to-Internal SRAM internal peripheral bus 66.7 MHz, 32 bit 133.3 66.7 53.3 83.3 MHz, 32 bit 166.7 83.3 66.7 100.0 MHz, 32 bit 200.0 100.0 80.0 133.3 MHz, 32 bit 266.7 133.3 106.7 150.0 MHz, 32 bit 300.0 150.0 120.0 System Speed, Width K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 455 Functional description Internal-SRAM-to-internal-SRAM transfers occur at the core's datapath width. For all transfers involving the internal peripheral bus, 32-bit transfer sizes are used. In all cases, the transfer rate includes the time to read the source plus the time to write the destination. 22.4.4.2 Peak request rates The second performance metric is a measure of the number of DMA requests that can be serviced in a given amount of time. For this metric, assume that the peripheral request causes the channel to move a single internal peripheral bus-mapped operand to/from internal SRAM. The same timing assumptions used in the previous example apply to this calculation. In particular, this metric also reflects the time required to activate the channel. The eDMA design supports the following hardware service request sequence. Note that the exact timing from Cycle 7 is a function of the response times for the channel's read and write accesses. In the case of an internal peripheral bus read and internal SRAM write, the combined data phase time is 4 cycles. For an SRAM read and internal peripheral bus write, it is 5 cycles. Table 22-5. Hardware service request process Cycle With internal peripheral bus read and internal SRAM write Description With SRAM read and internal peripheral bus write 1 eDMA peripheral request is asserted. 2 The eDMA peripheral request is registered locally in the eDMA module and qualified. TCDn_CSR[START] bit initiated requests start at this point with the registering of the user write to TCDn word 7. 3 Channel arbitration begins. 4 Channel arbitration completes. The transfer control descriptor local memory read is initiated. 5-6 The first two parts of the activated channel's TCD is read from the local memory. The memory width to the eDMA engine is 64 bits, so the entire descriptor can be accessed in four cycles 7 The first system bus read cycle is initiated, as the third part of the channel's TCD is read from the local memory. Depending on the state of the crossbar switch, arbitration at the system bus may insert an additional cycle of delay here. 8-11 8-12 12 13 The last part of the TCD is read in. This cycle represents the first data phase for the read, and the address phase for the destination write. This cycle represents the data phase of the last destination write. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 456 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) Table 22-5. Hardware service request process (continued) Cycle Description With internal peripheral bus read and internal SRAM write With SRAM read and internal peripheral bus write 13 14 The eDMA engine completes the execution of the inner minor loop and prepares to write back the required TCDn fields into the local memory. The TCDn word 7 is read and checked for channel linking or scatter/gather requests. 14 15 The appropriate fields in the first part of the TCDn are written back into the local memory. 15 16 The fields in the second part of the TCDn are written back into the local memory. This cycle coincides with the next channel arbitration cycle start. 16 17 The next channel to be activated performs the read of the first part of its TCD from the local memory. This is equivalent to Cycle 4 for the first channel's service request. Assuming zero wait states on the system bus, DMA requests can be processed every 9 cycles. Assuming an average of the access times associated with internal peripheral busto-SRAM (4 cycles) and SRAM-to-internal peripheral bus (5 cycles), DMA requests can be processed every 11.5 cycles (4 + (4+5)/2 + 3). This is the time from Cycle 4 to Cycle x +5. The resulting peak request rate, as a function of the system frequency, is shown in the following table. Table 22-6. eDMA peak request rate (MReq/sec) Request rate Request rate with zero wait states with wait states 66.6 7.4 5.8 83.3 9.2 7.2 100.0 11.1 8.7 133.3 14.8 11.6 150.0 16.6 13.0 System frequency (MHz) A general formula to compute the peak request rate with overlapping requests is: PEAKreq = freq / [ entry + (1 + read_ws) + (1 + write_ws) + exit ] where: Table 22-7. Peak request formula operands Operand PEAKreq Description Peak request rate Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 457 Functional description Table 22-7. Peak request formula operands (continued) Operand Description freq System frequency entry Channel startup (4 cycles) read_ws Wait states seen during the system bus read data phase write_ws Wait states seen during the system bus write data phase exit Channel shutdown (3 cycles) 22.4.4.3 eDMA performance example Consider a system with the following characteristics: * Internal SRAM can be accessed with one wait-state when viewed from the system bus data phase * All internal peripheral bus reads require two wait-states, and internal peripheral bus writes three wait-states viewed from the system bus data phase * System operates at 150 MHz For an SRAM to internal peripheral bus transfer, PEAKreq = 150 MHz / [ 4 + (1 + 1) + (1 + 3) + 3 ] cycles = 11.5 Mreq/sec For an internal peripheral bus to SRAM transfer, PEAKreq = 150 MHz / [ 4 + (1 + 2) + (1 + 1) + 3 ] cycles = 12.5 Mreq/sec Assuming an even distribution of the two transfer types, the average peak request rate would be: PEAKreq = (11.5 Mreq/sec + 12.5 Mreq/sec) / 2 = 12.0 Mreq/sec The minimum number of cycles to perform a single read/write, zero wait states on the system bus, from a cold start where no channel is executing and eDMA is idle are: * 11 cycles for a software, that is, a TCDn_CSR[START] bit, request * 12 cycles for a hardware, that is, an eDMA peripheral request signal, request Two cycles account for the arbitration pipeline and one extra cycle on the hardware request resulting from the internal registering of the eDMA peripheral request signals. For the peak request rate calculations above, the arbitration and request registering is absorbed in or overlaps the previous executing channel. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 458 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) Note When channel linking or scatter/gather is enabled, a two cycle delay is imposed on the next channel selection and startup. This allows the link channel or the scatter/gather channel to be eligible and considered in the arbitration pool for next channel selection. 22.5 Initialization/application information The following sections discuss initialization of the eDMA and programming considerations. 22.5.1 eDMA initialization To initialize the eDMA: 1. Write to the CR if a configuration other than the default is desired. 2. Write the channel priority levels to the DCHPRIn registers if a configuration other than the default is desired. 3. Enable error interrupts in the EEI register if so desired. 4. Write the 32-byte TCD for each channel that may request service. 5. Enable any hardware service requests via the ERQ register. 6. Request channel service via either: * Software: setting the TCDn_CSR[START] * Hardware: slave device asserting its eDMA peripheral request signal After any channel requests service, a channel is selected for execution based on the arbitration and priority levels written into the programmer's model. The eDMA engine reads the entire TCD, including the TCD control and status fields, as shown in the following table, for the selected channel into its internal address path module. As the TCD is read, the first transfer is initiated on the internal bus, unless a configuration error is detected. Transfers from the source, as defined by TCDn_SADDR, to the destination, as defined by TCDn_DADDR, continue until the number of bytes specified by TCDn_NBYTES are transferred. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 459 Initialization/application information When the transfer is complete, the eDMA engine's local TCDn_SADDR, TCDn_DADDR, and TCDn_CITER are written back to the main TCD memory and any minor loop channel linking is performed, if enabled. If the major loop is exhausted, further post processing executes, such as interrupts, major loop channel linking, and scatter/gather operations, if enabled. Table 22-8. TCD Control and Status fields TCDn_CSR field name Description START Control bit to start channel explicitly when using a software initiated DMA service (Automatically cleared by hardware) ACTIVE Status bit indicating the channel is currently in execution DONE Status bit indicating major loop completion (cleared by software when using a software initiated DMA service) D_REQ Control bit to disable DMA request at end of major loop completion when using a hardware initiated DMA service BWC Control bits for throttling bandwidth control of a channel E_SG Control bit to enable scatter-gather feature INT_HALF Control bit to enable interrupt when major loop is half complete INT_MAJ Control bit to enable interrupt when major loop completes The following figure shows how each DMA request initiates one minor-loop transfer, or iteration, without CPU intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (BITER). Current major loop iteration count (CITER) Source or destination memory Minor loop DMA request 3 Major loop Minor loop DMA request 2 Minor loop DMA request 1 Figure 22-5. Example of multiple loop iterations The following figure lists the memory array terms and how the TCD settings interrelate. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 460 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) xADDR: (Starting address) xSIZE: (size of one data transfer) Minor loop (NBYTES in minor loop, often the same value as xSIZE) Minor loop Offset (xOFF): number of bytes added to current address after each transfer (often the same value as xSIZE) Each DMA source (S) and destination (D) has its own: Address (xADDR) Size (xSIZE) Offset (xOFF) Modulo (xMOD) Last Address Adjustment (xLAST) where x = S or D Last minor loop Peripheral queues typically have size and offset equal to NBYTES. xLAST: Number of bytes added to current address after major loop (typically used to loop back) Figure 22-6. Memory array terms 22.5.2 Programming errors The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per channel basis with the exception of channel priority error (ES[CPE]). For all error types other than channel priority error, the channel number causing the error is recorded in the Error Status register (DMAx_ES). If the error source is not removed before the next activation of the problem channel, the error is detected and recorded again. If priority levels are not unique, when any channel requests service, a channel priority error is reported. The highest channel priority with an active request is selected, but the lowest numbered channel with that priority is selected by arbitration and executed by the eDMA engine. The hardware service request handshake signals, error interrupts, and error reporting is associated with the selected channel. 22.5.3 Arbitration mode considerations This section discusses arbitration considerations for the eDMA. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 461 Initialization/application information 22.5.3.1 Fixed channel arbitration In this mode, the channel service request from the highest priority channel is selected to execute. 22.5.3.2 Round-robin channel arbitration Channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to the channel priority levels. 22.5.4 Performing DMA transfers This section presents examples on how to perform DMA transfers with the eDMA. 22.5.4.1 Single request To perform a simple transfer of n bytes of data with one activation, set the major loop to one (TCDn_CITER = TCDn_BITER = 1). The data transfer begins after the channel service request is acknowledged and the channel is selected to execute. After the transfer is complete, the TCDn_CSR[DONE] bit is set and an interrupt generates if properly enabled. For example, the following TCD entry is configured to transfer 16 bytes of data. The eDMA is programmed for one iteration of the major loop transferring 16 bytes per iteration. The source memory has a byte wide memory port located at 0x1000. The destination memory has a 32-bit port located at 0x2000. The address offsets are programmed in increments to match the transfer size: one byte for the source and four bytes for the destination. The final source and destination addresses are adjusted to return to their beginning values. TCDn_CITER = TCDn_BITER = 1 TCDn_NBYTES = 16 TCDn_SADDR = 0x1000 TCDn_SOFF = 1 TCDn_ATTR[SSIZE] = 0 TCDn_SLAST = -16 TCDn_DADDR = 0x2000 TCDn_DOFF = 4 TCDn_ATTR[DSIZE] = 2 TCDn_DLAST_SGA= -16 TCDn_CSR[INT_MAJ] = 1 TCDn_CSR[START] = 1 (Should be written last after all other fields have been initialized) All other TCDn fields = 0 This generates the following event sequence: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 462 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) 1. User write to the TCDn_CSR[START] bit requests channel service. 2. The channel is selected by arbitration for servicing. 3. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1. 4. eDMA engine reads: channel TCD data from local memory to internal register file. 5. The source-to-destination transfers are executed as follows: a. Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003. b. Write 32-bits to location 0x2000 first iteration of the minor loop. c. Read byte from location 0x1004, read byte from location 0x1005, read byte from 0x1006, read byte from 0x1007. d. Write 32-bits to location 0x2004 second iteration of the minor loop. e. Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. f. Write 32-bits to location 0x2008 third iteration of the minor loop. g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. h. Write 32-bits to location 0x200C last iteration of the minor loop major loop complete. 6. The eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 1 (TCDn_BITER). 7. The eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] = 1. 8. The channel retires and the eDMA goes idle or services the next channel. 22.5.4.2 Multiple requests The following example transfers 32 bytes via two hardware requests, but is otherwise the same as the previous example. The only fields that change are the major loop iteration count and the final address offsets. The eDMA is programmed for two iterations of the major loop transferring 16 bytes per iteration. After the channel's hardware requests are enabled in the ERQ register, the slave device initiates channel service requests. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 463 Initialization/application information TCDn_CITER = TCDn_BITER = 2 TCDn_SLAST = -32 TCDn_DLAST_SGA = -32 This would generate the following sequence of events: 1. First hardware, that is, eDMA peripheral, request for channel service. 2. The channel is selected by arbitration for servicing. 3. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1. 4. eDMA engine reads: channel TCDn data from local memory to internal register file. 5. The source to destination transfers are executed as follows: a. Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003. b. Write 32-bits to location 0x2000 first iteration of the minor loop. c. Read byte from location 0x1004, read byte from location 0x1005, read byte from 0x1006, read byte from 0x1007. d. Write 32-bits to location 0x2004 second iteration of the minor loop. e. Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. f. Write 32-bits to location 0x2008 third iteration of the minor loop. g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. h. Write 32-bits to location 0x200C last iteration of the minor loop. 6. eDMA engine writes: TCDn_SADDR = 0x1010, TCDn_DADDR = 0x2010, TCDn_CITER = 1. 7. eDMA engine writes: TCDn_CSR[ACTIVE] = 0. 8. The channel retires one iteration of the major loop. The eDMA goes idle or services the next channel. 9. Second hardware, that is, eDMA peripheral, requests channel service. 10. The channel is selected by arbitration for servicing. 11. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 464 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) 12. eDMA engine reads: channel TCD data from local memory to internal register file. 13. The source to destination transfers are executed as follows: a. Read byte from location 0x1010, read byte from location 0x1011, read byte from 0x1012, read byte from 0x1013. b. Write 32-bits to location 0x2010 first iteration of the minor loop. c. Read byte from location 0x1014, read byte from location 0x1015, read byte from 0x1016, read byte from 0x1017. d. Write 32-bits to location 0x2014 second iteration of the minor loop. e. Read byte from location 0x1018, read byte from location 0x1019, read byte from 0x101A, read byte from 0x101B. f. Write 32-bits to location 0x2018 third iteration of the minor loop. g. Read byte from location 0x101C, read byte from location 0x101D, read byte from 0x101E, read byte from 0x101F. h. Write 32-bits to location 0x201C last iteration of the minor loop major loop complete. 14. eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 2 (TCDn_BITER). 15. eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] = 1. 16. The channel retires major loop complete. The eDMA goes idle or services the next channel. 22.5.4.3 Using the modulo feature The modulo feature of the eDMA provides the ability to implement a circular data queue in which the size of the queue is a power of 2. MOD is a 5-bit field for the source and destination in the TCD, and it specifies which lower address bits increment from their original value after the address+offset calculation. All upper address bits remain the same as in the original value. A setting of 0 for this field disables the modulo feature. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 465 Initialization/application information The following table shows how the transfer addresses are specified based on the setting of the MOD field. Here a circular buffer is created where the address wraps to the original value while the 28 upper address bits (0x1234567x) retain their original value. In this example the source address is set to 0x12345670, the offset is set to 4 bytes and the MOD field is set to 4, allowing for a 24 byte (16-byte) size queue. Table 22-9. Modulo example Transfer Number Address 1 0x12345670 2 0x12345674 3 0x12345678 4 0x1234567C 5 0x12345670 6 0x12345674 22.5.5 Monitoring transfer descriptor status This section discusses how to monitor eDMA status. 22.5.5.1 Testing for minor loop completion There are two methods to test for minor loop completion when using software initiated service requests. The first is to read the TCDn_CITER field and test for a change. Another method may be extracted from the sequence shown below. The second method is to test the TCDn_CSR[START] bit and the TCDn_CSR[ACTIVE] bit. The minor-loopcomplete condition is indicated by both bits reading zero after the TCDn_CSR[START] was set. Polling the TCDn_CSR[ACTIVE] bit may be inconclusive, because the active status may be missed if the channel execution is short in duration. The TCD status bits execute the following sequence for a software activated channel: Stage TCDn_CSR bits State START ACTIVE DONE 1 1 0 0 Channel service request via software 2 0 1 0 Channel is executing 3a 0 0 0 Channel has completed the minor loop and is idle 3b 0 0 1 Channel has completed the major loop and is idle K22F Sub-Family Reference Manual, Rev. 4, 08/2016 466 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) The best method to test for minor-loop completion when using hardware, that is, peripheral, initiated service requests is to read the TCDn_CITER field and test for a change. The hardware request and acknowledge handshake signals are not visible in the programmer's model. The TCD status bits execute the following sequence for a hardware-activated channel: Stage TCDn_CSR bits State START ACTIVE DONE 1 0 0 0 Channel service request via hardware (peripheral request asserted) 2 0 1 0 Channel is executing 3a 0 0 0 Channel has completed the minor loop and is idle 3b 0 0 1 Channel has completed the major loop and is idle For both activation types, the major-loop-complete status is explicitly indicated via the TCDn_CSR[DONE] bit. The TCDn_CSR[START] bit is cleared automatically when the channel begins execution regardless of how the channel activates. 22.5.5.2 Reading the transfer descriptors of active channels The eDMA reads back the true TCDn_SADDR, TCDn_DADDR, and TCDn_NBYTES values if read while a channel executes. The true values of the SADDR, DADDR, and NBYTES are the values the eDMA engine currently uses in its internal register file and not the values in the TCD local memory for that channel. The addresses, SADDR and DADDR, and NBYTES, which decrement to zero as the transfer progresses, can give an indication of the progress of the transfer. All other values are read back from the TCD local memory. 22.5.5.3 Checking channel preemption status Preemption is available only when fixed arbitration is selected as the channel arbitration mode. A preemptive situation is one in which a preempt-enabled channel runs and a higher priority request becomes active. When the eDMA engine is not operating in fixed channel arbitration mode, the determination of the actively running relative priority outstanding requests become undefined. Channel priorities are treated as equal, that is, constantly rotating, when Round-Robin Arbitration mode is selected. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 467 Initialization/application information The TCDn_CSR[ACTIVE] bit for the preempted channel remains asserted throughout the preemption. The preempted channel is temporarily suspended while the preempting channel executes one major loop iteration. If two TCDn_CSR[ACTIVE] bits are set simultaneously in the global TCD map, a higher priority channel is actively preempting a lower priority channel. 22.5.6 Channel Linking Channel linking (or chaining) is a mechanism where one channel sets the TCDn_CSR[START] bit of another channel (or itself), therefore initiating a service request for that channel. When properly enabled, the EDMA engine automatically performs this operation at the major or minor loop completion. The minor loop channel linking occurs at the completion of the minor loop (or one iteration of the major loop). The TCDn_CITER[E_LINK] field determines whether a minor loop link is requested. When enabled, the channel link is made after each iteration of the major loop except for the last. When the major loop is exhausted, only the major loop channel link fields are used to determine if a channel link should be made. For example, the initial fields of: TCDn_CITER[E_LINK] = 1 TCDn_CITER[LINKCH] = 0xC TCDn_CITER[CITER] value = 0x4 TCDn_CSR[MAJOR_E_LINK] = 1 TCDn_CSR[MAJOR_LINKCH] = 0x7 executes as: 1. Minor loop done set TCD12_CSR[START] bit 2. Minor loop done set TCD12_CSR[START] bit 3. Minor loop done set TCD12_CSR[START] bit 4. Minor loop done, major loop done set TCD7_CSR[START] bit When minor loop linking is enabled (TCDn_CITER[E_LINK] = 1), the TCDn_CITER[CITER] field uses a nine bit vector to form the current iteration count. When minor loop linking is disabled (TCDn_CITER[E_LINK] = 0), the TCDn_CITER[CITER] field uses a 15-bit vector to form the current iteration count. The bits associated with the TCDn_CITER[LINKCH] field are concatenated onto the CITER value to increase the range of the CITER. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 468 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) Note The TCDn_CITER[E_LINK] bit and the TCDn_BITER[E_LINK] bit must equal or a configuration error is reported. The CITER and BITER vector widths must be equal to calculate the major loop, half-way done interrupt point. The following table summarizes how a DMA channel can link to another DMA channel, i.e, use another channel's TCD, at the end of a loop. Table 22-10. Channel Linking Parameters Desired Link Behavior Link at end of Minor Loop Link at end of Major Loop TCD Control Field Name Description CITER[E_LINK] Enable channel-to-channel linking on minor loop completion (current iteration) CITER[LINKCH] Link channel number when linking at end of minor loop (current iteration) CSR[MAJOR_E_LINK] Enable channel-to-channel linking on major loop completion CSR[MAJOR_LINKCH] Link channel number when linking at end of major loop 22.5.7 Dynamic programming This section provides recommended methods to change the programming model during channel execution. 22.5.7.1 Dynamically changing the channel priority The following two options are recommended for dynamically changing channel priority levels: 1. Switch to Round-Robin Channel Arbitration mode, change the channel priorities, then switch back to Fixed Arbitration mode, 2. Disable all the channels, change the channel priorities, then enable the appropriate channels. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 469 Initialization/application information 22.5.7.2 Dynamic channel linking Dynamic channel linking is the process of setting the TCD.major.e_link bit during channel execution (see the diagram in TCD structure). This bit is read from the TCD local memory at the end of channel execution, thus allowing the user to enable the feature during channel execution. Because the user is allowed to change the configuration during execution, a coherency model is needed. Consider the scenario where the user attempts to execute a dynamic channel link by enabling the TCD.major.e_link bit at the same time the eDMA engine is retiring the channel. The TCD.major.e_link would be set in the programmer's model, but it would be unclear whether the actual link was made before the channel retired. The following coherency model is recommended when executing a dynamic channel link request. 1. Write 1 to the TCD.major.e_link bit. 2. Read back the TCD.major.e_link bit. 3. Test the TCD.major.e_link request status: * If TCD.major.e_link = 1, the dynamic link attempt was successful. * If TCD.major.e_link = 0, the attempted dynamic link did not succeed (the channel was already retiring). For this request, the TCD local memory controller forces the TCD.major.e_link bit to zero on any writes to a channel's TCD.word7 after that channel's TCD.done bit is set, indicating the major loop is complete. NOTE The user must clear the TCD.done bit before writing the TCD.major.e_link bit. The TCD.done bit is cleared automatically by the eDMA engine after a channel begins execution. 22.5.7.3 Dynamic scatter/gather Scatter/gather is the process of automatically loading a new TCD into a channel. It allows a DMA channel to use multiple TCDs; this enables a DMA channel to scatter the DMA data to multiple destinations or gather it from multiple sources.When scatter/gather is enabled and the channel has finished its major loop, a new TCD is fetched from system memory and loaded into that channel's descriptor location in eDMA programmer's model, thus replacing the current descriptor. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 470 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) Because the user is allowed to change the configuration during execution, a coherency model is needed. Consider the scenario where the user attempts to execute a dynamic scatter/gather operation by enabling the TCD.e_sg bit at the same time the eDMA engine is retiring the channel. The TCD.e_sg would be set in the programmer's model, but it would be unclear whether the actual scatter/gather request was honored before the channel retired. Two methods for this coherency model are shown in the following subsections. Method 1 has the advantage of reading the major.linkch field and the e_sg bit with a single read. For both dynamic channel linking and scatter/gather requests, the TCD local memory controller forces the TCD.major.e_link and TCD.e_sg bits to zero on any writes to a channel's TCD.word7 if that channel's TCD.done bit is set indicating the major loop is complete. NOTE The user must clear the TCD.done bit before writing the TCD.major.e_link or TCD.e_sg bits. The TCD.done bit is cleared automatically by the eDMA engine after a channel begins execution. 22.5.7.3.1 Method 1 (channel not using major loop channel linking) For a channel not using major loop channel linking, the coherency model described here may be used for a dynamic scatter/gather request. When the TCD.major.e_link bit is zero, the TCD.major.linkch field is not used by the eDMA. In this case, the TCD.major.linkch bits may be used for other purposes. This method uses the TCD.major.linkch field as a TCD indentification (ID). 1. When the descriptors are built, write a unique TCD ID in the TCD.major.linkch field for each TCD associated with a channel using dynamic scatter/gather. 2. Write 1b to the TCD.d_req bit. Should a dynamic scatter/gather attempt fail, setting the TCD.d_req bit will prevent a future hardware activation of this channel. This stops the channel from executing with a destination address (daddr) that was calculated using a scatter/gather address (written in the next step) instead of a dlast final offest value. 3. Write the TCD.dlast_sga field with the scatter/gather address. 4. Write 1b to the TCD.e_sg bit. 5. Read back the 16 bit TCD control/status field. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 471 Initialization/application information 6. Test the TCD.e_sg request status and TCD.major.linkch value: If e_sg = 1b, the dynamic link attempt was successful. If e_sg = 0b and the major.linkch (ID) did not change, the attempted dynamic link did not succeed (the channel was already retiring). If e_sg = 0b and the major.linkch (ID) changed, the dynamic link attempt was successful (the new TCD's e_sg value cleared the e_sg bit). 22.5.7.3.2 Method 2 (channel using major loop channel linking) For a channel using major loop channel linking, the coherency model described here may be used for a dynamic scatter/gather request. This method uses the TCD.dlast_sga field as a TCD indentification (ID). 1. Write 1b to the TCD.d_req bit. Should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a future hardware activation of this channel. This stops the channel from executing with a destination address (daddr) that was calculated using a scatter/gather address (written in the next step) instead of a dlast final offest value. 2. 3. 4. 5. Write theTCD.dlast_sga field with the scatter/gather address. Write 1b to the TCD.e_sg bit. Read back the TCD.e_sg bit. Test the TCD.e_sg request status: If e_sg = 1b, the dynamic link attempt was successful. If e_sg = 0b, read the 32 bit TCD dlast_sga field. If e_sg = 0b and the dlast_sga did not change, the attempted dynamic link did not succeed (the channel was already retiring). If e_sg = 0b and the dlast_sga changed, the dynamic link attempt was successful (the new TCD's e_sg value cleared the e_sg bit). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 472 NXP Semiconductors Chapter 22 Enhanced Direct Memory Access (eDMA) 22.5.8 Lockstep This chip contains an eDMA Checker which, when enabled, operates in Lockstep mode with the primary eDMA, executing the exact same transfer profiles. The eDMA Checker checks to ensure the primary eDMA is operating correctly. A block diagram is shown below. DMA checker DMA Inputs Signal Compression delay_element DMA Outputs DMA Outputs Alarms delay_element DMA Signal Compression RCCU delay_element delay_element Checker Lake 22.5.8.1 Initialization To prevent the eDMA Checker from generating a false comparison error after power-onreset, the eDMA's data output buffer must be initialized prior to enabling the Checker. To initialize the eDMA data output buffer, the eDMA must perform a one or more 32-bit data transfers using any data value. 22.5.8.2 Errors To handle source-address errors (SAE), perform the following steps. 1. Fix the addressing error. 2. Clear the error bit in Error Register (DMA_ERR). 3. Start the channel in a normal fashion. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 473 Initialization/application information NOTE Error Status Register (DMA_ES) is read-only; the bits cannot be cleared. It saves the last recorded error. The VLD bit shows the user whether any error bits in the Error Register are set, thus indicating an error occurred that hasn't been cleared. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 474 NXP Semiconductors Chapter 23 External Watchdog Monitor (EWM) 23.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. For safety, a redundant watchdog system, External Watchdog Monitor (EWM), is designed to monitor external circuits, as well as the MCU software flow. This provides a back-up mechanism to the internal watchdog that resets the MCU's CPU and peripherals. The watchdog is generally used to monitor the flow and execution of embedded software within an MCU. The watchdog consists of a counter that if allowed to overflow, forces an internal reset (asynchronous) to all on-chip peripherals and optionally assert the RESET pin to reset external devices/circuits. The overflow of the watchdog counter must not occur if the software code works well and services the watchdog to re-start the actual counter. The EWM differs from the internal watchdog in that it does not reset the MCU's CPU and peripherals. The EWM provides an independent EWM_out signal that when asserted resets or places an external circuit into a safe mode. The EWM_out signal is asserted upon the EWM counter time-out. An optional external input EWM_in is provided to allow additional control of the assertion of EWM_out signal. 23.1.1 Features Features of EWM module include: * Independent LPO_CLK clock source * Programmable time-out period specified in terms of number of EWM LPO_CLK clock cycles. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 475 Introduction * Windowed refresh option * Provides robust check that program flow is faster than expected. * Programmable window. * Refresh outside window leads to assertion of EWM_out. * Robust refresh mechanism * Write values of 0xB4 and 0x2C to EWM Refresh Register within 15 (EWM_refresh_time) peripheral bus clock cycles. * One output port, EWM_out, when asserted is used to reset or place the external circuit into safe mode. * One Input port, EWM_in, allows an external circuit to control the assertion of the EWM_out signal. 23.1.2 Modes of Operation This section describes the module's operating modes. 23.1.2.1 Stop Mode When the EWM is in stop mode, the CPU refreshes to the EWM cannot occur. On entry to stop mode, the EWM's counter freezes. There are two possible ways to exit from Stop mode: * On exit from stop mode through a reset, the EWM remains disabled. * On exit from stop mode by an interrupt, the EWM is re-enabled, and the counter continues to be clocked from the same value prior to entry to stop mode. Note the following if the EWM enters the stop mode during CPU refresh mechanism: At the exit from stop mode by an interrupt, refresh mechanism state machine starts from the previous state which means, if first refresh command is written correctly and EWM enters the stop mode immediately, the next command has to be written within the next 15 (EWM_refresh_time) peripheral bus clocks after exiting from stop mode. User must mask all interrupts prior to executing EWM refresh instructions. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 476 NXP Semiconductors Chapter 23 External Watchdog Monitor (EWM) 23.1.2.2 Wait Mode The EWM module treats the stop and wait modes as the same. EWM functionality remains the same in both of these modes. 23.1.2.3 Debug Mode Entry to debug mode has no effect on the EWM. * If the EWM is enabled prior to entry of debug mode, it remains enabled. * If the EWM is disabled prior to entry of debug mode, it remains disabled. 23.1.3 Block Diagram This figure shows the EWM block diagram. LPO_CLK Clock Divider Logic Low Power Clock Clock Gating Cell Counter Value 8-bit Counter Reset to Counter Enable EWM_CLKPRESCALER[CLK_DIV] AND OR CPU Reset EWM_CTRL[EWMEN] EWM Refreshed Counter overflow EWM_out EWM Refresh And /EWM_out Output Control Mechanism EWM_CMPH[COMPAREH] EWM_CMPL[COMPAREL] EWM_in EWM Service Register Figure 23-1. EWM Block Diagram K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 477 EWM Signal Descriptions 23.2 EWM Signal Descriptions The EWM has two external signals, as shown in the following table. Table 23-1. EWM Signal Descriptions Signal Description EWM_in EWM_out I/O EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low. I EWM reset out signal O 23.3 Memory Map/Register Definition This section contains the module memory map and registers. EWM memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4006_1000 Control Register (EWM_CTRL) 8 R/W 00h 23.3.1/478 4006_1001 Service Register (EWM_SERV) 8 W (always reads 0) 00h 23.3.2/479 4006_1002 Compare Low Register (EWM_CMPL) 8 R/W 00h 23.3.3/479 4006_1003 Compare High Register (EWM_CMPH) 8 R/W FFh 23.3.4/480 4006_1005 Clock Prescaler Register (EWM_CLKPRESCALER) 8 R/W 00h 23.3.5/481 23.3.1 Control Register (EWM_CTRL) The CTRL register is cleared by any reset. NOTE INEN, ASSIN and EWMEN bits can be written once after a CPU reset. Modifying these bits more than once, generates a bus transfer error. Address: 4006_1000h base + 0h offset = 4006_1000h Bit Read Write Reset 7 6 5 4 0 0 0 0 0 3 2 1 0 INTEN INEN ASSIN EWMEN 0 0 0 0 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 478 NXP Semiconductors Chapter 23 External Watchdog Monitor (EWM) EWM_CTRL field descriptions Field 7-4 Reserved 3 INTEN 2 INEN 1 ASSIN 0 EWMEN Description This field is reserved. This read-only field is reserved and always has the value 0. Interrupt Enable. This bit when set and EWM_out is asserted, an interrupt request is generated. To de-assert interrupt request, user should clear this bit by writing 0. Input Enable. This bit when set, enables the EWM_in port. EWM_in's Assertion State Select. Default assert state of the EWM_in signal is logic zero. Setting the ASSIN bit inverts the assert state of EWM_in signal to a logic one. EWM enable. This bit when set, enables the EWM module. This resets the EWM counter to zero and deasserts the EWM_out signal. This bit when unset, keeps the EWM module disabled. It cannot be re-enabled until a next reset, due to the write-once nature of this bit. 23.3.2 Service Register (EWM_SERV) The SERV register provides the interface from the CPU to the EWM module. It is writeonly and reads of this register return zero. Address: 4006_1000h base + 1h offset = 4006_1001h Bit 7 6 5 4 Read 0 Write SERVICE Reset 0 0 0 0 3 2 1 0 0 0 0 0 EWM_SERV field descriptions Field SERVICE Description The EWM refresh mechanism requires the CPU to write two values to the SERV register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The EWM refresh is invalid if either of the following conditions is true. * The first or second data byte is not written correctly. * The second data byte is not written within a fixed number of peripheral bus cycles of the first data byte. This fixed number of cycles is called EWM_refresh_time. 23.3.3 Compare Low Register (EWM_CMPL) The CMPL register is reset to zero after a CPU reset. This provides no minimum time for the CPU to refresh the EWM counter. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 479 Memory Map/Register Definition NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error. Address: 4006_1000h base + 2h offset = 4006_1002h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 COMPAREL 0 0 0 0 EWM_CMPL field descriptions Field COMPAREL Description To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) minimum refresh time is required. 23.3.4 Compare High Register (EWM_CMPH) The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum of 256 clocks time, for the CPU to refresh the EWM counter. NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error. NOTE The valid values for CMPH are up to 0xFE because the EWM counter never expires when CMPH = 0xFF. The expiration happens only if EWM counter is greater than CMPH. Address: 4006_1000h base + 3h offset = 4006_1003h Bit Read Write Reset 7 6 5 4 3 2 1 0 1 1 1 1 COMPAREH 1 1 1 1 EWM_CMPH field descriptions Field COMPAREH Description To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) maximum refresh time is required. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 480 NXP Semiconductors Chapter 23 External Watchdog Monitor (EWM) 23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER) This CLKPRESCALER register is reset to 0x00 after a CPU reset. NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error. NOTE Write the required prescaler value before enabling the EWM. NOTE The implementation of this register is chip-specific. See the Chip Configuration details. Address: 4006_1000h base + 5h offset = 4006_1005h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 CLK_DIV 0 0 0 0 EWM_CLKPRESCALER field descriptions Field CLK_DIV Description Selected low power clock source for running the EWM counter can be prescaled as below. * Prescaled clock frequency = low power clock source frequency / ( 1 + CLK_DIV ) 23.4 Functional Description The following sections describe functional details of the EWM module. NOTE When the BUS_CLK is lost, then EWM module doesn't generate the EWM_out signal and no refresh operation is possible 23.4.1 The EWM_out Signal The EWM_out is a digital output signal used to gate an external circuit (application specific) that controls critical safety functions. For example, the EWM_out could be connected to the high voltage transistors circuits that control an AC motor in a large appliance. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 481 Functional Description The EWM_out signal remains deasserted when the EWM is being regularly refreshed by the CPU within the programmable refresh window, indicating that the application code is executed as expected. The EWM_out signal is asserted in any of the following conditions: * The EWM refresh occurs when the counter value is less than CMPL value. * The EWM counter value reaches the CMPH value, and no EWM refresh has occurred. * If functionality of EWM_in pin is enabled and EWM_in pin is asserted while refreshing the EWM. * After any reset (by the virtue of the external pull-down mechanism on the EWM_out pin) The EWM_out is asserted after any reset by the virtue of the external pull-down mechanism on the EWM_out signal. Then, to deassert the EWM_out signal, set EWMEN bit in the CTRL register to enable the EWM. If the EWM_out signal shares its pad with a digital I/O pin, on reset this actual pad defers to being an input signal. The pad state is controlled by the EWM_out signal only after the EWM is enabled by the EWMEN bit in the CTRL register. Note EWM_out pad must be in pull down state when EWM functionality is used and when EWM is under Reset. 23.4.2 The EWM_in Signal The EWM_in is a digital input signal for safety status of external safety circuits, that allows an external circuit to control the assertion of the EWM_out signal. For example, in the application, an external circuit monitors a critical safety function, and if there is fault with safety function, the external circuit can then actively initiate the EWM_out signal that controls the gating circuit. The EWM_in signal is ignored if the EWM is disabled, or if INEN bit of CTRL register is cleared, as after any reset. On enabling the EWM (setting the CTRL[EWMEN] bit) and enabling EWM_in functionality (setting the CTRL[INEN] bit), the EWM_in signal must be in the deasserted state prior to the CPU start refreshing the EWM. This ensures that the EWM_out stays in the deasserted state; otherwise, the EWM_out output signal is asserted. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 482 NXP Semiconductors Chapter 23 External Watchdog Monitor (EWM) Note The user must update the CMPH and CMPL registers prior to enabling the EWM. After enabling the EWM, the counter resets to zero, therefore the user shall provide a reasonable time after a power-on reset for the external monitoring circuit to stabilize. The user shall also ensure that the EWM_in pin is deasserted. 23.4.3 EWM Counter It is an 8-bit ripple counter fed from a clock source that is independent of the peripheral bus clock source. As the preferred time-out is between 1 ms and 100 ms the actual clock source should be in the kHz range. The counter is reset to zero after the CPU reset, or when EWM refresh action completes, or at counter overflow. The counter value is not accessible to the CPU. 23.4.4 EWM Compare Registers The compare registers CMPL and CMPH are write-once after a CPU reset and cannot be modified until another CPU reset occurs. The EWM compare registers are used to create a refresh window to refresh the EWM module. It is illegal to program CMPL and CMPH with same value. In this case, as soon as counter reaches (CMPL + 1), EWM_out is asserted. 23.4.5 EWM Refresh Mechanism Other than the initial configuration of the EWM, the CPU can only access the EWM by the EWM Service Register. The CPU must access the EWM service register with correct write of unique data within the windowed time frame as determined by the CMPL and CMPH registers for correct EWM refresh operation. Therefore, three possible conditions can occur: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 483 Functional Description Table 23-2. EWM Refresh Mechanisms Condition Mechanism An EWM refresh action completes when: The software behaves as expected and the EWM counter is reset to zero. The EWM_out output signal remains in the deasserted state if, during the EWM refresh action, the EWM_in input has been in deasserted state.. CMPL < Counter < CMPH. An EWM refresh action completes when Counter < CMPL The software refreshes the EWM before the windowed time frame, the counter is reset to zero and the EWM_out output signal is asserted irrespective of the input EWM_in. Counter value reaches CMPH prior to completion of EWM refresh action. Software has not refreshed the EWM. The EWM counter is reset to zero and the EWM_out output signal is asserted irrespective of the input EWM_in. 23.4.6 EWM Interrupt When EWM_out is asserted, an interrupt request is generated to indicate the assertion of the EWM reset out signal. This interrupt is enabled when CTRL[INTEN] is set. Clearing this bit clears the interrupt request but does not affect EWM_out. The EWM_out signal can be deasserted only by forcing a system reset. 23.4.7 Counter clock prescaler The EWM counter clock source can be prescaled by a clock divider, by programming CLKPRESCALER[CLK_DIV]. This divided clock is used to run the EWM counter. NOTE The divided clock used to run the EWM counter must be no more than half the frequency of the bus clock. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 484 NXP Semiconductors Chapter 24 Watchdog Timer (WDOG) 24.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The Watchdog Timer (WDOG) keeps a watch on the system functioning and resets it in case of its failure. Reasons for failure include run-away software code and the stoppage of the system clock that in a safety critical system can lead to serious consequences. In such cases, the watchdog brings the system into a safe state of operation. The watchdog monitors the operation of the system by expecting periodic communication from the software, generally known as servicing or refreshing the watchdog. If this periodic refreshing does not occur, the watchdog resets the system. 24.2 Features The features of the Watchdog Timer (WDOG) include: * Clock source input independent from CPU/bus clock. Choice between two clock sources: * Low-power oscillator (LPO) * External system clock * Unlock sequence for allowing updates to write-once WDOG control/configuration bits. * All WDOG control/configuration bits are writable once only within 256 bus clock cycles of being unlocked. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 485 Functional overview * You need to always update these bits after unlocking within 256 bus clock cycles. Failure to update these bits resets the system. * Programmable time-out period specified in terms of number of WDOG clock cycles. * Ability to test WDOG timer and reset with a flag indicating watchdog test. * Quick test--Small time-out value programmed for quick test. * Byte test--Individual bytes of timer tested one at a time. * Read-only access to the WDOG timer--Allows dynamic check that WDOG timer is operational. NOTE Reading the watchdog timer counter while running the watchdog on the bus clock might not give the accurate counter value. * Windowed refresh option * Provides robust check that program flow is faster than expected. * Programmable window. * Refresh outside window leads to reset. * Robust refresh mechanism * Write values of 0xA602 and 0xB480 to WDOG Refresh Register within 20 bus clock cycles. * Count of WDOG resets as they occur. * Configurable interrupt on time-out to provide debug breadcrumbs. This is followed by a reset after 256 bus clock cycles. 24.3 Functional overview K22F Sub-Family Reference Manual, Rev. 4, 08/2016 486 NXP Semiconductors Chapter 24 Watchdog Timer (WDOG) WDOG Unlock Sequence 2 Writes of data within K bus clock cycles of each other Disable Control/Configuration bit changes N bus clk cycles after unlocking Refresh Sequence 2 writes of data within K bus clock cycles of each other 0xC520 N bus clk cycles 0xD928 0xA602 0xB480 Allow update for N bus clk cycles WDOGEN WAITEN STOPEN Window_begin No unlock after reset WINEN DebugEN System Bus Clock WDOG CLKSRC 32-bit Modulus Reg (Time-out Value) Y Invalid Refresh Seq 32-bit Timer IRQ_RST_ EN = = 1? Refresh Outside Window N Timer Time-out WDOGTEST N bus clk cycles R WDOGT Interrupt No config after unlocking System reset and SRS register Invalid Unlock Seq LPO WDOG reset count Osc Alt Clock Fast Fn Test Clock WDOG Clock Selection WDOG CLK WDOGEN = WDOG Enable WINEN = Windowed Mode Enable WDOGT = WDOG Time-out Value WDOGCLKSRC = WDOG Clock Source WDOG Test = WDOG Test Mode WAIT EN = Enable in wait mode STOP EN = Enable in stop mode Debug EN = Enable in debug mode SRS = System Reset Status Register R = Timer Reload Figure 24-1. WDOG operation The preceding figure shows the operation of the watchdog. The values for N and K are: * N = 256 * K = 20 The watchdog is a fail safe mechanism that brings the system into a known initial state in case of its failure due to CPU clock stopping or a run-away condition in code execution. In its simplest form, the watchdog timer runs continuously off a clock source and expects to be serviced periodically, failing which it resets the system. This ensures that the software is executing correctly and has not run away in an unintended direction. Software can adjust the period of servicing or the time-out value for the watchdog timer to meet the needs of the application. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 487 Functional overview You can select a windowed mode of operation that expects the servicing to be done only in a particular window of the time-out period. An attempted servicing of the watchdog outside this window results in a reset. By operating in this mode, you can get an indication of whether the code is running faster than expected. The window length is also user programmable. If a system fails to update/refresh the watchdog due to an unknown and persistent cause, it will be caught in an endless cycle of resets from the watchdog. To analyze the cause of such conditions, you can program the watchdog to first issue an interrupt, followed by a reset. In the interrupt service routine, the software can analyze the system stack to aid debugging. To enhance the independence of watchdog from the system, it runs off an independent LPO oscillator clock. You can also switch over to an alternate clock source if required, through a control register bit. 24.3.1 Unlocking and updating the watchdog As long as ALLOW_UPDATE in the watchdog control register is set, you can unlock and modify the write-once-only control and configuration registers: 1. Write 0xC520 followed by 0xD928 within 20 bus clock cycles to a specific unlock register (WDOG_UNLOCK). 2. Wait one bus clock cycle. You cannot update registers on the bus clock cycle immediately following the write of the unlock sequence. 3. An update window equal in length to the watchdog configuration time (WCT) opens. Within this window, you can update the configuration and control register bits. These register bits can be modified only once after unlocking. If none of the configuration and control registers is updated within the update window, the watchdog issues a reset, that is, interrupt-then-reset, to the system. Trying to unlock the watchdog within the WCT after an initial unlock has no effect. During the update operation, the watchdog timer is not paused and continues running in the background. After the update window closes, the watchdog timer restarts and the watchdog functions according to the new configuration. The update feature is useful for applications that have an initial, non-safety critical part, where the watchdog is kept disabled or with a conveniently long time-out period. This means the application coder does not have to frequently service the watchdog. After the critical part of the application begins, the watchdog can be reconfigured as needed. The watchdog issues a reset, that is, interrupt-then-reset if enabled, to the system for any of these invalid unlock sequences: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 488 NXP Semiconductors Chapter 24 Watchdog Timer (WDOG) * Write any value other than 0xC520 or 0xD928 to the unlock register. * ALLOW_UPDATE is set and a gap of more than 20 bus clock cycles is inserted between the writing of the unlock sequence values. An attempted refresh operation between the two writes of the unlock sequence and in the WCT time following a successful unlock, goes undetected. Also, see Watchdog Operation with 8-bit access for guidelines related to 8-bit accesses to the unlock register. Note A context switch during unlocking and refreshing may lead to a watchdog reset. 24.3.2 Watchdog configuration time (WCT) To prevent unintended modification of the watchdog's control and configuration register bits, you are allowed to update them only within a period of 256 bus clock cycles after unlocking. This period is known as the watchdog configuration time (WCT). In addition, these register bits can be modified only once after unlocking them for editing, even after reset. You must unlock the registers within WCT after system reset, failing which the WDOG issues a reset to the system. In other words, you must write at least the first word of the unlocking sequence within the WCT after reset. After this is done, you have a further 20 bus clock cycles, the maximum allowed gap between the words of the unlock sequence, to complete the unlocking operation. Thereafter, to make sure that you do not forget to configure the watchdog, the watchdog issues a reset if none of the WDOG control and configuration registers is updated in the WCT after unlock. After the close of this window or after the first write, these register bits are locked out from any further changes. The watchdog timer keeps running according to its default configuration through unlocking and update operations that can extend up to a maximum total of 2xWCT + 20 bus clock cycles. Therefore, it must be ensured that the time-out value for the watchdog is always greater than 2xWCT time + 20 bus clock cycles. Updates in the write-once registers take effect only after the WCT window closes with the following exceptions for which changes take effect immediately: * Stop, Wait, and Debug mode enable * IRQ_RST_EN The operations of refreshing the watchdog goes undetected during the WCT. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 489 Functional overview 24.3.3 Refreshing the watchdog A robust refreshing mechanism has been chosen for the watchdog. A valid refresh is a write of 0xA602 followed by 0xB480 within 20 bus clock cycles to watchdog refresh register. If these two values are written more than 20 bus cycles apart or if something other than these two values is written to the register, a watchdog reset, or interrupt-thenreset if enabled, is issued to the system. A valid refresh makes the watchdog timer restart on the next bus clock. Also, an attempted unlock operation in between the two writes of the refresh sequence goes undetected. See Watchdog Operation with 8-bit access for guidelines related to 8-bit accesses to the refresh register. 24.3.4 Windowed mode of operation In this mode of operation, a restriction is placed on the point in time within the time-out period at which the watchdog can be refreshed. The refresh is considered valid only when the watchdog timer increments beyond a certain count as specified by the watchdog window register. This is known as refreshing the watchdog within a window of the total time-out period. If a refresh is attempted before the timer reaches the window value, the watchdog generates a reset, or interrupt-then-reset if enabled. If there is no refresh at all, the watchdog times out and generates a reset or interrupt-then-reset if enabled. 24.3.5 Watchdog disabled mode of operation When the watchdog is disabled through the WDOG_EN bit in the watchdog status and control register, the watchdog timer is reset to zero and is disabled from counting until you enable it or it is enabled again by the system reset. In this mode, the watchdog timer cannot be refreshed-there is no requirement to do so while the timer is disabled. However, the watchdog still generates a reset, or interrupt-then-reset if enabled, on a nontime-out exception. See Generated Resets and Interrupts. You need to unlock the watchdog before enabling it. A system reset brings the watchdog out of the disabled mode. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 490 NXP Semiconductors Chapter 24 Watchdog Timer (WDOG) 24.3.6 Debug modes of operation You can program the watchdog to disable in debug modes through DBG_EN in the watchdog control register. This results in the watchdog timer pausing for the duration of the mode. Register read/writes are still allowed, which means that operations like refresh, unlock, and so on are allowed. Upon exit from the mode, the timer resumes its operation from the point of pausing. The entry of the system into the mode does not excuse it from compulsorily configuring the watchdog in the WCT time after unlock, unless the system bus clock is gated off, in which case the internal state machine pauses too. Failing to do so still results in a reset, or interrupt-then-reset, if enabled, to the system. Also, all of the exception conditions that result in a reset to the system, as described in Generated Resets and Interrupts, are still valid in mode. So, if an exception condition occurs and the system bus clock is on, a reset occurs, or interrupt-then-reset, if enabled. The entry into Debug mode within WCT after reset is treated differently. The WDOG timer is kept reset to zero and there is no need to unlock and configure it within WCT. You must not try to refresh or unlock the WDOG in this state or unknown behavior may result. Upon exit from mode, the WDOG timer restarts and the WDOG has to be unlocked and configured within WCT. 24.4 Testing the watchdog For IEC 60730 and other safety standards, the expectation is that anything that monitors a safety function must be tested, and this test is required to be fault tolerant. To test the watchdog, its main timer and its associated compare and reset logic must be tested. To this end, two tests are implemented for the watchdog, as described in Quick Test and Byte Test. A control bit is provided to put the watchdog into functional test mode. There is also an overriding test-disable control bit which allows the functional test mode to be disabled permanently. After it is set, this test-disable bit can only be cleared by a reset. These two tests achieve the overall aim of testing the counter functioning and the compare and reset logic. Note Do not enable the watchdog interrupt during these tests. If required, you must ensure that the effective time-out value is greater than WCT time. See Generated Resets and Interrupts for more details. To run a particular test: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 491 Testing the watchdog 1. Select either quick test or byte test.. 2. Set a certain test mode bit to put the watchdog in the functional test mode. Setting this bit automatically switches the watchdog timer to a fast clock source. The switching of the clock source is done to achieve a faster time-out and hence a faster test. In a successful test, the timer times out after reaching the programmed time-out value and generates a system reset. Note After emerging from a reset due to a watchdog test, unlock and configure the watchdog. The refresh and unlock operations and interrupt are not automatically disabled in the test mode. 24.4.1 Quick test In this test, the time-out value of watchdog timer is programmed to a very low value to achieve quick time-out. The only difference between the quick test and the normal mode of the watchdog is that TESTWDOG is set for the quick test. This allows for a faster test of the watchdog reset mechanism. 24.4.2 Byte test The byte test is a more thorough a test of the watchdog timer. In this test, the timer is split up into its constituent byte-wide stages that are run independently and tested for time-out against the corresponding byte of the time-out value register. The following figure explains the splitting concept: K22F Sub-Family Reference Manual, Rev. 4, 08/2016 492 NXP Semiconductors Chapter 24 Watchdog Timer (WDOG) Reset Value (Hardwired) Modulus Register (Time-out Value) Byte 3 Byte 2 Byte 1 Byte 4 WDOG Reset WDOG Test Equality Comparison Mod = = Timer? 32-bit Timer Byte Stage 1 en Byte Stage 2 en Byte Stage 3 en Byte Stage 4 CLK Nth Stage Overflow Enables N + 1th Stage Figure 24-2. Watchdog timer byte splitting Each stage is an 8-bit synchronous counter followed by combinational logic that generates an overflow signal. The overflow signal acts as an enable to the N + 1th stage. In the test mode, when an individual byte, N, is tested, byte N - 1 is loaded forcefully with 0xFF, and both these bytes are allowed to run off the clock source. By doing so, the overflow signal from stage N - 1 is generated immediately, enabling counter stage N. The Nth stage runs and compares with the Nth byte of the time-out value register. In this way, the byte N is also tested along with the link between it and the preceding stage. No other stages, N - 2, N - 3... and N + 1, N + 2... are enabled for the test on byte N. These disabled stages, except the most significant stage of the counter, are loaded with a value of 0xFF. 24.5 Backup reset generator The backup reset generator generates the final reset which goes out to the system. It has a backup mechanism which ensures that in case the bus clock stops and prevents the main state machine from generating a reset exception/interrupt, the watchdog timer's time-out is separately routed out as a reset to the system. Two successive timer time-outs without an intervening system reset result in the backup reset generator routing out the time-out signal as a reset to the system. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 493 Generated resets and interrupts 24.6 Generated resets and interrupts The watchdog generates a reset in the following events, also referred to as exceptions: * A watchdog time-out * Failure to unlock the watchdog within WCT time after system reset deassertion * No update of the control and configuration registers within the WCT window after unlocking. At least one of the following registers must be written to within the WCT window to avoid reset: * WDOG_ST_CTRL_H, WDOG_ST_CTRL_L * WDOG_TO_VAL_H, WDOG_TO_VAL_L * WDOG_WIN_H, WDOG_WIN_L * WDOG_PRESCALER * A value other than the unlock sequence or the refresh sequence is written to the unlock and/or refresh registers, respectively. * A gap of more than 20 bus cycles exists between the writes of two values of the unlock sequence. * A gap of more than 20 bus cycles exists between the writes of two values of the refresh sequence. The watchdog can also generate an interrupt. If IRQ_RST_EN is set, then on the above mentioned events WDOG_ST_CTRL_L[INT_FLG] is set, generating an interrupt. A watchdog reset is also generated WCT time later to ensure the watchdog is fault tolerant. The interrupt can be cleared by writing 1 to INT_FLG. The gap of WCT between interrupt and reset means that the WDOG time-out value must be greater than WCT. Otherwise, if the interrupt was generated due to a time-out, a second consecutive time-out will occur in that WCT gap. This will trigger the backup reset generator to generate a reset to the system, prematurely ending the interrupt service routine execution. Also, jobs such as counting the number of watchdog resets would not be done. 24.7 Memory map and register definition This section consists of the memory map and register descriptions. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 494 NXP Semiconductors Chapter 24 Watchdog Timer (WDOG) WDOG memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4005_2000 Watchdog Status and Control Register High (WDOG_STCTRLH) 16 R/W 01D3h 24.7.1/495 4005_2002 Watchdog Status and Control Register Low (WDOG_STCTRLL) 16 R/W 0001h 24.7.2/497 4005_2004 Watchdog Time-out Value Register High (WDOG_TOVALH) 16 R/W 004Ch 24.7.3/497 4005_2006 Watchdog Time-out Value Register Low (WDOG_TOVALL) 16 R/W 4B4Ch 24.7.4/498 4005_2008 Watchdog Window Register High (WDOG_WINH) 16 R/W 0000h 24.7.5/498 4005_200A Watchdog Window Register Low (WDOG_WINL) 16 R/W 0010h 24.7.6/499 4005_200C Watchdog Refresh register (WDOG_REFRESH) 16 R/W B480h 24.7.7/499 4005_200E Watchdog Unlock register (WDOG_UNLOCK) 16 R/W D928h 24.7.8/499 4005_2010 Watchdog Timer Output Register High (WDOG_TMROUTH) 16 R/W 0000h 24.7.9/500 4005_2012 Watchdog Timer Output Register Low (WDOG_TMROUTL) 16 R/W 0000h 24.7.10/500 4005_2014 Watchdog Reset Count register (WDOG_RSTCNT) 16 R/W 0000h 24.7.11/501 4005_2016 Watchdog Prescaler register (WDOG_PRESC) 16 R/W 0400h 24.7.12/501 24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH) 4 3 2 1 0 WDOGEN 0 5 CLKSRC 0 6 IRQRSTEN 0 0 7 WINEN 0 0 8 ALLOWUPDAT E 0 9 DBGEN 0 10 STOPEN Reset 11 WAITEN Write 12 Reserved 0 13 TESTWDOG Read 14 BYTESEL[1:0] 15 DISTESTWDO G Bit TESTSEL Address: 4005_2000h base + 0h offset = 4005_2000h 1 1 1 0 1 0 0 1 1 WDOG_STCTRLH field descriptions Field 15 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 14 Allows the WDOG's functional test mode to be disabled permanently. After it is set, it can only be cleared DISTESTWDOG by a reset. It cannot be unlocked for editing after it is set. 0 1 13-12 BYTESEL[1:0] WDOG functional test mode is not disabled. WDOG functional test mode is disabled permanently until reset. This 2-bit field selects the byte to be tested when the watchdog is in the byte test mode. 00 01 Byte 0 selected Byte 1 selected Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 495 Memory map and register definition WDOG_STCTRLH field descriptions (continued) Field Description 10 11 11 TESTSEL 10 TESTWDOG Byte 2 selected Byte 3 selected Effective only if TESTWDOG is set. Selects the test to be run on the watchdog timer. 0 1 Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test. Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing. Puts the watchdog in the functional test mode. In this mode, the watchdog timer and the associated compare and reset generation logic is tested for correct operation. The clock for the timer is switched from the main watchdog clock to the fast clock input for watchdog functional test. The TESTSEL bit selects the test to be run. 9 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 8 Reserved This field is reserved. 7 WAITEN Enables or disables WDOG in Wait mode. 6 STOPEN Enables or disables WDOG in Stop mode. 5 DBGEN Enables or disables WDOG in Debug mode. 0 1 0 1 0 1 WDOG is disabled in CPU Wait mode. WDOG is enabled in CPU Wait mode. WDOG is disabled in CPU Stop mode. WDOG is enabled in CPU Stop mode. WDOG is disabled in CPU Debug mode. WDOG is enabled in CPU Debug mode. 4 Enables updates to watchdog write-once registers, after the reset-triggered initial configuration window ALLOWUPDATE (WCT) closes, through unlock sequence. 0 1 3 WINEN 2 IRQRSTEN No further updates allowed to WDOG write-once registers. WDOG write-once registers can be unlocked for updating. Enables Windowing mode. 0 1 Windowing mode is disabled. Windowing mode is enabled. Used to enable the debug breadcrumbs feature. A change in this bit is updated immediately, as opposed to updating after WCT. 0 1 WDOG time-out generates reset only. WDOG time-out initially generates an interrupt. After WCT, it generates a reset. 1 CLKSRC Selects clock source for the WDOG timer and other internal timing operations. 0 WDOGEN Enables or disables the WDOG's operation. In the disabled state, the watchdog timer is kept in the reset state, but the other exception conditions can still trigger a reset/interrupt. A change in the value of this bit must be held for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled. 0 1 WDOG clock sourced from LPO . WDOG clock sourced from alternate clock source. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 496 NXP Semiconductors Chapter 24 Watchdog Timer (WDOG) WDOG_STCTRLH field descriptions (continued) Field Description 0 1 WDOG is disabled. WDOG is enabled. 24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL) Address: 4005_2000h base + 2h offset = 4005_2002h Bit Read Write Reset 15 14 13 12 11 INTFLG Bit Read Write Reset 10 9 8 Reserved 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 1 Reserved 0 0 0 0 WDOG_STCTRLL field descriptions Field Description 15 INTFLG Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a precondition to set this flag. INTFLG = 1 results in an interrupt being issued followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this bit. It also gets cleared on a system reset. Reserved This field is reserved. NOTE: Do not modify this field value. 24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH) Address: 4005_2000h base + 4h offset = 4005_2004h Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 0 0 TOVALHIGH 0 0 0 0 0 0 0 0 0 WDOG_TOVALH field descriptions Field Description TOVALHIGH Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer. It is defined in terms of cycles of the watchdog clock. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 497 Memory map and register definition 24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL) The time-out value of the watchdog must be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain. Address: 4005_2000h base + 6h offset = 4005_2006h Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 0 0 TOVALLOW 0 1 0 0 1 0 1 1 0 WDOG_TOVALL field descriptions Field Description TOVALLOW Defines the lower 16 bits of the 32-bit time-out value for the watchdog timer. It is defined in terms of cycles of the watchdog clock. 24.7.5 Watchdog Window Register High (WDOG_WINH) NOTE You must set the Window Register value lower than the Timeout Value Register. Address: 4005_2000h base + 8h offset = 4005_2008h Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 WINHIGH 0 0 0 0 0 0 0 0 0 WDOG_WINH field descriptions Field WINHIGH Description Defines the upper 16 bits of the 32-bit window for the windowed mode of operation of the watchdog. It is defined in terms of cycles of the watchdog clock. In this mode, the watchdog can be refreshed only when the timer has reached a value greater than or equal to this window length. A refresh outside this window resets the system or if IRQRSTEN is set, it interrupts and then resets the system. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 498 NXP Semiconductors Chapter 24 Watchdog Timer (WDOG) 24.7.6 Watchdog Window Register Low (WDOG_WINL) NOTE You must set the Window Register value lower than the Timeout Value Register. Address: 4005_2000h base + Ah offset = 4005_200Ah Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 WINLOW 0 0 0 0 0 0 0 0 0 WDOG_WINL field descriptions Field Description WINLOW Defines the lower 16 bits of the 32-bit window for the windowed mode of operation of the watchdog. It is defined in terms of cycles of the pre-scaled watchdog clock. In this mode, the watchdog can be refreshed only when the timer reaches a value greater than or equal to this window length value. A refresh outside of this window resets the system or if IRQRSTEN is set, it interrupts and then resets the system. 24.7.7 Watchdog Refresh register (WDOG_REFRESH) Address: 4005_2000h base + Ch offset = 4005_200Ch Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 WDOGREFRESH 1 0 1 1 0 1 0 0 1 WDOG_REFRESH field descriptions Field Description WDOGREFRESH Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20 bus clock cycles written to this register refreshes the WDOG and prevents it from resetting the system. Writing a value other than the above mentioned sequence or if the sequence is longer than 20 bus cycles, resets the system, or if IRQRSTEN is set, it interrupts and then resets the system. 24.7.8 Watchdog Unlock register (WDOG_UNLOCK) Address: 4005_2000h base + Eh offset = 4005_200Eh Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 0 0 0 WDOGUNLOCK 1 1 0 1 1 0 0 1 0 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 499 Memory map and register definition WDOG_UNLOCK field descriptions Field Description WDOGUNLOCK Writing the unlock sequence values to this register to makes the watchdog write-once registers writable again. The required unlock sequence is 0xC520 followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens a window equal in length to the WCT within which you can update the registers. Writing a value other than the above mentioned sequence or if the sequence is longer than 20 bus cycles, resets the system or if IRQRSTEN is set, it interrupts and then resets the system. The unlock sequence is effective only if ALLOWUPDATE is set. 24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH) Address: 4005_2000h base + 10h offset = 4005_2010h Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TIMEROUTHIGH 0 0 0 0 0 0 0 0 0 WDOG_TMROUTH field descriptions Field Description TIMEROUTHIGH Shows the value of the upper 16 bits of the watchdog timer. 24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL) During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following the watchdog timer. Address: 4005_2000h base + 12h offset = 4005_2012h Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TIMEROUTLOW 0 0 0 0 0 0 0 0 0 WDOG_TMROUTL field descriptions Field Description TIMEROUTLOW Shows the value of the lower 16 bits of the watchdog timer. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 500 NXP Semiconductors Chapter 24 Watchdog Timer (WDOG) 24.7.11 Watchdog Reset Count register (WDOG_RSTCNT) Address: 4005_2000h base + 14h offset = 4005_2014h Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RSTCNT 0 0 0 0 0 0 0 0 0 WDOG_RSTCNT field descriptions Field Description RSTCNT Counts the number of times the watchdog resets the system. This register is reset only on a POR. Writing 1 to the bit to be cleared enables you to clear the contents of this register. 24.7.12 Watchdog Prescaler register (WDOG_PRESC) Address: 4005_2000h base + 16h offset = 4005_2016h Bit Read Write Reset 15 14 13 12 11 10 0 0 0 0 9 8 7 6 5 4 PRESCVAL 0 0 1 0 3 2 1 0 0 0 0 0 0 0 0 0 0 0 WDOG_PRESC field descriptions Field 15-11 Reserved 10-8 PRESCVAL Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 3-bit prescaler for the watchdog clock source. A value of zero indicates no division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL + 1) to provide the prescaled WDOG_CLK. This field is reserved. This read-only field is reserved and always has the value 0. 24.8 Watchdog operation with 8-bit access 24.8.1 General guideline When performing 8-bit accesses to the watchdog's 16-bit registers where the intention is to access both the bytes of a register, place the two 8-bit accesses one after the other in your code. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 501 Watchdog operation with 8-bit access 24.8.2 Refresh and unlock operations with 8-bit access One exception condition that generates a reset to the system is the write of any value other than those required for a legal refresh/update sequence to the respective refresh and unlock registers. For an 8-bit access to these registers, writing a correct value requires at least two bus clock cycles, resulting in an invalid value in the registers for one cycle. Therefore, the system is reset even if the intention is to write a correct value to the refresh/unlock register. Keeping this in mind, the exception condition for 8-bit accesses is slightly modified. Whereas the match for a correct value for a refresh/unlock sequence is as according to the original definition, the match for an incorrect value is done byte-wise on the refresh/ unlock rather than for the whole 16-bit value. This means that if the high byte of the refresh/unlock register contains any value other than high bytes of the two values that make up the sequence, it is treated as an exception condition, leading to a reset or interrupt-then-reset. The same holds true for the lower byte of the refresh or unlock register. Take the refresh operation that expects a write of 0xA602 followed by 0xB480 to the refresh register, as an example. Table 24-1. Refresh for 8-bit access WDOG_REFRESH[15:8] WDOG_REFRESH[7:0] Sequence value1 or value2 match Mismatch exception Current Value 0xB4 0x80 Value2 match No Write 1 0xB4 0x02 No match No Write 2 0xA6 0x02 Value1 match No Write 3 0xB4 0x02 No match No Write 4 0xB4 0x80 Value2 match. Sequence complete. No Write 5 0x02 0x80 No match Yes As shown in the preceding table, the refresh register holds its reset value initially. Thereafter, two 8-bit accesses are performed on the register to write the first value of the refresh sequence. No mismatch exception is registered on the intermediate write, Write1. The sequence is completed by performing two more 8-bit accesses, writing in the second value of the sequence for a successful refresh. It must be noted that the match of value2 takes place only when the complete 16-bit value is correctly written, write4. Hence, the requirement of writing value2 of the sequence within 20 bus clock cycles of value1 is checked by measuring the gap between write2 and write4. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 502 NXP Semiconductors Chapter 24 Watchdog Timer (WDOG) It is reiterated that the condition for matching values 1 and 2 of the refresh or unlock sequence remains unchanged. The difference for 8-bit accesses is that the criterion for detecting a mismatch is less strict. Any 16-bit access still needs to adhere to the original guidelines, mentioned in the sections Refreshing the Watchdog. 24.9 Restrictions on watchdog operation This section mentions some exceptions to the watchdog operation that may not be apparent to you. * Restriction on unlock/refresh operations--In the period between the closure of the WCT window after unlock and the actual reload of the watchdog timer, unlock and refresh operations need not be attempted. * The update and reload of the watchdog timer happens two to three watchdog clocks after WCT window closes, following a successful configuration on unlock. * Clock Switching Delay--The watchdog uses glitch-free multiplexers at two places - one to choose between the LPO oscillator input and alternate clock input, and the other to choose between the watchdog functional clock and fast clock input for watchdog functional test. A maximum time period of ~2 clock A cycles plus ~2 clock B cycles elapses from the time a switch is requested to the occurrence of the actual clock switch, where clock A and B are the two input clocks to the clock mux. * For the windowed mode, there is a two to three bus clock latency between the watchdog counter going past the window value and the same registering in the bus clock domain. * For proper operation of the watchdog, the watchdog clock must be at least five times slower than the system bus clock at all times. An exception is when the watchdog clock is synchronous to the bus clock wherein the watchdog clock can be as fast as the bus clock. * WCT must be equivalent to at least three watchdog clock cycles. If not ensured, this means that even after the close of the WCT window, you have to wait for the synchronized system reset to deassert in the watchdog clock domain, before expecting the configuration updates to take effect. * The time-out value of the watchdog should be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 503 Restrictions on watchdog operation * You must take care not only to refresh the watchdog within the watchdog timer's actual time-out period, but also provide enough allowance for the time it takes for the refresh sequence to be detected by the watchdog timer, on the watchdog clock. * Updates cannot be made in the bus clock cycle immediately following the write of the unlock sequence, but one bus clock cycle later. * It should be ensured that the time-out value for the watchdog is always greater than 2xWCT time + 20 bus clock cycles. * An attempted refresh operation, in between the two writes of the unlock sequence and in the WCT time following a successful unlock, will go undetected. * Trying to unlock the watchdog within the WCT time after an initial unlock has no effect. * The refresh and unlock operations and interrupt are not automatically disabled in the watchdog functional test mode. * After emerging from a reset due to a watchdog functional test, you are still expected to go through the mandatory steps of unlocking and configuring the watchdog. The watchdog continues to be in its functional test mode and therefore you should pull the watchdog out of the functional test mode within WCT time of reset. * After emerging from a reset due to a watchdog functional test, you still need to go through the mandatory steps of unlocking and configuring the watchdog. * You must ensure that both the clock inputs to the glitchless clock multiplexers are alive during the switching of clocks. Failure to do so results in a loss of clock at their outputs. * There is a gap of two to three watchdog clock cycles from the point that stop mode is entered to the watchdog timer actually pausing, due to synchronization. The same holds true for an exit from the stop mode, this time resulting in a two to three watchdog clock cycle delay in the timer restarting. In case the duration of the stop mode is less than one watchdog clock cycle, the watchdog timer is not guaranteed to pause. * Consider the case when the first refresh value is written, following which the system enters stop mode with system bus clk still on. If the second refresh value is not written within 20 bus cycles of the first value, the system is reset, or interrupt-thenreset if enabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 504 NXP Semiconductors Chapter 25 Multipurpose Clock Generator (MCG) 25.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The multipurpose clock generator (MCG) module provides several clock source choices for the MCU. The module contains a frequency-locked loop (FLL). The FLL is controllable by either an internal or an external reference clock. The module can select either an FLL output clock, or a reference clock (internal or external) as a source for the MCU system clock. The MCG operates in conjuction with a crystal oscillator, which allows an external crystal, ceramic resonator, or another external clock source to produce the external reference clock. 25.1.1 Features Key features of the MCG module are: * Frequency-locked loop (FLL): * Digitally-controlled oscillator (DCO) * DCO frequency range is programmable for up to four different frequency ranges. * Option to program and maximize DCO output frequency for a low frequency external reference clock source. * Option to prevent FLL from resetting its current locked frequency when switching clock modes if FLL reference frequency is not changed. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 505 Introduction * Internal or external reference clock can be used as the FLL source. * Can be used as a clock source for other on-chip peripherals. * Internal reference clock generator: * Slow clock with nine trim bits for accuracy * Fast clock with four trim bits * Can be used as source clock for the FLL. In FEI mode, only the slow Internal Reference Clock (IRC) can be used as the FLL source. * Either the slow or the fast clock can be selected as the clock source for the MCU. * Can be used as a clock source for other on-chip peripherals. * Control signals for the MCG external reference low power oscillator clock generators are provided: * HGO, RANGE, EREFS * External clock from the Crystal Oscillator : * Can be used as a source for the FLL. * Can be selected as the clock source for the MCU. * External clock from the Real Time Counter (RTC): * Can be used as a source for the FLL only. * Can be selected as the clock source for the MCU. * External clock monitor with reset and interrupt request capability to check for external clock failure when running in FBE, BLPE, or FEE modes * Internal Reference Clocks Auto Trim Machine (ATM) capability using an external clock as a reference * Reference dividers for the FLL are provided * Reference dividers for the Fast Internal Reference Clock are provided * MCG FLL Clock (MCGFLLCLK) is provided as a clock source for other on-chip peripherals K22F Sub-Family Reference Manual, Rev. 4, 08/2016 506 NXP Semiconductors Chapter 25 Multipurpose Clock Generator (MCG) * MCG Fixed Frequency Clock (MCGFFCLK) is provided as a clock source for other on-chip peripherals * MCG Internal Reference Clock (MCGIRCLK) is provided as a clock source for other on-chip peripherals This figure presents the block diagram of the MCG module. Oscillator (OSC0) Oscillator (OSC2) Oscillator (OSC1) CLKS OSCINIT EREFS MCG Crystal Oscillator Enable Detect OSCSEL HGO IREFS OSCSELCLK RANGE ATMF SCTRIM SCFTRIM FCTRIM Internal Reference Auto Trim Machine ATMS STOP IREFSTEN / 2n IRCSCLK n=0-7 CME0 CME1 MCGOUTCLK LOCS0 External Clock Monitor LOCS1 DRS IREFS DMX32 LOCRE0 LOCRE1 CLKS IRCS Slow Clock Fast Clock Clock Generator MCGIRCLK IRCLKEN Filter MCGFLLCLK DCO FLTPRSRV / 2n /2 5 DCOOUT n=0-7 FLL FRDIV Peripheral BUSCLK MCGFFCLK RANGE /2 Sync LP Clock Valid Multipurpose Clock Generator (MCG) Figure 25-1. Multipurpose Clock Generator (MCG) block diagram NOTE Refer to the chip configuration chapter to identify the oscillator used in this MCU. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 507 External Signal Description 25.1.2 Modes of Operation The MCG has the following modes of operation: FEI, FEE, FBI, FBE, BLPI, BLPE, and Stop. For details, see MCG modes of operation. 25.2 External Signal Description There are no MCG signals that connect off chip. 25.3 Memory Map/Register Definition This section includes the memory map and register definition. The MCG registers can only be written when in supervisor mode. Write accesses when in user mode will result in a bus error. Read accesses may be performed in both supervisor and user mode. MCG memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_4000 MCG Control 1 Register (MCG_C1) 8 R/W 04h 25.3.1/509 4006_4001 MCG Control 2 Register (MCG_C2) 8 R/W See section 25.3.2/510 4006_4002 MCG Control 3 Register (MCG_C3) 8 R/W Undefined 25.3.3/511 4006_4003 MCG Control 4 Register (MCG_C4) 8 R/W See section 25.3.4/512 4006_4004 MCG Control 5 Register (MCG_C5) 8 R/W 00h 25.3.5/513 4006_4005 MCG Control 6 Register (MCG_C6) 8 R/W 00h 25.3.5/513 4006_4006 MCG Status Register (MCG_S) 8 R 10h 25.3.6/514 4006_4008 MCG Status and Control Register (MCG_SC) 8 R/W 02h 25.3.7/515 4006_400A MCG Auto Trim Compare Value High Register (MCG_ATCVH) 8 R/W 00h 25.3.8/516 4006_400B MCG Auto Trim Compare Value Low Register (MCG_ATCVL) 8 R/W 00h 25.3.9/517 4006_400C MCG Control 7 Register (MCG_C7) 8 R/W 00h 25.3.10/ 517 4006_400D MCG Control 8 Register (MCG_C8) 8 R/W See section 25.3.11/ 518 4006_4011 MCG Control 12 Register (MCG_C12) 8 R/W 00h 25.3.12/ 519 4006_4012 MCG Status 2 Register (MCG_S2) 8 R/W 00h 25.3.12/ 519 4006_4013 MCG Test 3 Register (MCG_T3) 8 R/W 00h 25.3.12/ 519 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 508 NXP Semiconductors Chapter 25 Multipurpose Clock Generator (MCG) 25.3.1 MCG Control 1 Register (MCG_C1) Address: 4006_4000h base + 0h offset = 4006_4000h Bit Read Write Reset 7 6 5 CLKS 0 4 3 FRDIV 0 0 0 0 2 1 0 IREFS IRCLKEN IREFSTEN 1 0 0 MCG_C1 field descriptions Field 7-6 CLKS Description Clock Source Select Selects the clock source for MCGOUTCLK . 00 01 10 11 5-3 FRDIV FLL External Reference Divider Selects the amount to divide down the external reference clock for the FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is not required to meet this range, but it is recommended in the cases when trying to enter a FLL mode from FBE). 000 001 010 011 100 101 110 111 2 IREFS Selects the reference clock source for the FLL. External reference clock is selected. The slow internal reference clock is selected. Internal Reference Clock Enable Enables the internal reference clock for use as MCGIRCLK. 0 1 0 IREFSTEN If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 . Internal Reference Select 0 1 1 IRCLKEN Encoding 0 -- Output of FLL is selected. Encoding 1 -- Internal reference clock is selected. Encoding 2 -- External reference clock is selected. Encoding 3 -- Reserved. MCGIRCLK inactive. MCGIRCLK active. Internal Reference Stop Enable Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 509 Memory Map/Register Definition MCG_C1 field descriptions (continued) Field Description 0 1 Internal reference clock is disabled in Stop mode. Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. 25.3.2 MCG Control 2 Register (MCG_C2) Address: 4006_4000h base + 1h offset = 4006_4001h Bit Read Write Reset 7 6 LOCRE0 FCFTRIM 1 x* 5 4 RANGE 0 3 2 1 0 HGO EREFS LP IRCS 0 0 0 0 0 * Notes: * x = Undefined at reset. MCG_C2 field descriptions Field 7 LOCRE0 Description Loss of Clock Reset Enable Determines whether an interrupt or a reset request is made following a loss of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is set. 0 1 6 FCFTRIM Interrupt request is generated on a loss of OSC0 external reference clock. Generate a reset request on a loss of OSC0 external reference clock. Fast Internal Reference Clock Fine Trim FCFTRIM1 controls the smallest adjustment of the fast internal reference clock frequency. Setting FCFTRIM increases the period and clearing FCFTRIM decreases the period by the smallest amount possible. If an FCFTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this bit. 5-4 RANGE Frequency Range Select Selects the frequency range for the crystal oscillator or external clock source. See the Oscillator (OSC) chapter for more details and the device data sheet for the frequency ranges used. 00 01 1X 3 HGO High Gain Oscillator Select Controls the crystal oscillator mode of operation. See the Oscillator (OSC) chapter for more details. 0 1 2 EREFS Encoding 0 -- Low frequency range selected for the crystal oscillator . Encoding 1 -- High frequency range selected for the crystal oscillator . Encoding 2 -- Very high frequency range selected for the crystal oscillator . Configure crystal oscillator for low-power operation. Configure crystal oscillator for high-gain operation. External Reference Select Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 510 NXP Semiconductors Chapter 25 Multipurpose Clock Generator (MCG) MCG_C2 field descriptions (continued) Field Description Selects the source for the external reference clock. See the Oscillator (OSC) chapter for more details. 0 1 1 LP External reference clock requested. Oscillator requested. Low Power Select Controls whether the FLL is disabled in BLPI and BLPE modes. In FBE mode, setting this bit to 1 will transition the MCG into BLPE mode; in FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any other MCG mode, LP bit has no affect. 0 1 0 IRCS FLL is not disabled in bypass modes. FLL is disabled in bypass modes (lower power) Internal Reference Clock Select Selects between the fast or slow internal reference clock source. 0 1 Slow internal reference clock selected. Fast internal reference clock selected. 1. A value for FCFTRIM is loaded during reset from a factory programmed location. 25.3.3 MCG Control 3 Register (MCG_C3) Address: 4006_4000h base + 2h offset = 4006_4002h Bit Read Write Reset 7 6 5 4 3 2 1 0 x* x* x* x* SCTRIM x* x* x* x* * Notes: * x = Undefined at reset. MCG_C3 field descriptions Field SCTRIM Description Slow Internal Reference Clock Trim Setting SCTRIM 1 controls the slow internal reference clock frequency by controlling the slow internal reference clock period. The SCTRIM bits are binary weighted, that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value increases the period, and decreasing the value decreases the period. An additional fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset, this value is loaded with a factory trim value. If an SCTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this register. 1. A value for SCTRIM is loaded during reset from a factory programmed location. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 511 Memory Map/Register Definition 25.3.4 MCG Control 4 Register (MCG_C4) Address: 4006_4000h base + 3h offset = 4006_4003h Bit Read Write Reset 7 6 DMX32 5 4 3 DRST_DRS 0 0 2 1 FCTRIM 0 x* x* 0 SCFTRIM x* x* x* * Notes: * x = Undefined at reset. MCG_C4 field descriptions Field 7 DMX32 Description DCO Maximum Frequency with 32.768 kHz Reference The DMX32 bit controls whether the DCO frequency range is narrowed to its maximum frequency with a 32.768 kHz reference. The following table identifies settings for the DCO frequency range. NOTE: The system clocks derived from this source should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 0 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 0 31.25-39.0625 kHz 2560 80-100 MHz 1 32.768 kHz 2929 96 MHz 01 10 11 0 1 6-5 DRST_DRS DCO Range Select The DRS bits select the frequency range for the FLL output, DCOOUT. When the LP bit is set, writes to the DRS bits are ignored. The DRST read field indicates the current frequency range for DCOOUT. The DRST field does not update immediately after a write to the DRS field due to internal synchronization between clock domains. See the DCO Frequency Range table for more details. 00 01 10 11 4-1 FCTRIM DCO has a default range of 25%. DCO is fine-tuned for maximum frequency with 32.768 kHz reference. Encoding 0 -- Low range (reset default). Encoding 1 -- Mid range. Encoding 2 -- Mid-high range. Encoding 3 -- High range. Fast Internal Reference Clock Trim Setting Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 512 NXP Semiconductors Chapter 25 Multipurpose Clock Generator (MCG) MCG_C4 field descriptions (continued) Field Description FCTRIM 1 controls the fast internal reference clock frequency by controlling the fast internal reference clock period. The FCTRIM bits are binary weighted, that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value increases the period, and decreasing the value decreases the period. If an FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this register. 0 SCFTRIM Slow Internal Reference Clock Fine Trim SCFTRIM 2 controls the smallest adjustment of the slow internal reference clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM decreases the period by the smallest amount possible. If an SCFTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this bit. 1. A value for FCTRIM is loaded during reset from a factory programmed location. 2. A value for SCFTRIM is loaded during reset from a factory programmed location. 25.3.5 MCG Control 5 Register (MCG_C5) Address: 4006_4000h base + 4h offset = 4006_4004h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 MCG_C5 field descriptions Field Reserved Description Reserved This field is reserved. This read-only field is reserved and always has the value 0. 25.3.5 MCG Control 6 Register (MCG_C6) Address: 4006_4000h base + 5h offset = 4006_4005h Bit Read Write Reset 7 6 0 0 5 4 3 0 CME0 0 0 0 0 0 MCG_C6 field descriptions Field 7-6 Reserved Description Reserved This field is reserved. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 513 Memory Map/Register Definition MCG_C6 field descriptions (continued) Field Description This read-only field is reserved and always has the value 0. 5 CME0 Clock Monitor Enable Determines if an interrupt or a reset request (see MCG_C2[LOCRE0]) is made following a loss of external clock indication. The CME0 bit should only be set to a logic 1 when the MCG is in an operational mode that uses the external clock (FEE, FBE, or BLPE). Whenever the CME0 bit is set to a logic 1, the value of the RANGE bits in the C2 register should not be changed. CME0 bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a reset request may occur when in Stop mode. CME0 should also be set to a logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode. 0 1 Reserved External clock monitor is disabled. Generate an interrupt or a reset request (see MCG_C2[LOCRE0]) on loss of external clock. Reserved This field is reserved. This read-only field is reserved and always has the value 0. 25.3.6 MCG Status Register (MCG_S) Address: 4006_4000h base + 6h offset = 4006_4006h Bit 7 6 Read 5 0 4 3 IREFST 2 CLKST 1 0 OSCINIT0 IRCST 0 0 Write Reset 0 0 0 1 0 0 MCG_S field descriptions Field 7-5 Reserved 4 IREFST Description Reserved This field is reserved. This read-only field is reserved and always has the value 0. Internal Reference Status This bit indicates the current source for the FLL reference clock. The IREFST bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock domains. 0 1 3-2 CLKST Source of FLL reference clock is the external reference clock. Source of FLL reference clock is the internal reference clock. Clock Mode Status These bits indicate the current clock mode. The CLKST bits do not update immediately after a write to the CLKS bits due to internal synchronization between clock domains. 00 01 Encoding 0 -- Output of the FLL is selected (reset default). Encoding 1 -- Internal reference clock is selected. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 514 NXP Semiconductors Chapter 25 Multipurpose Clock Generator (MCG) MCG_S field descriptions (continued) Field Description 10 11 1 OSCINIT0 0 IRCST Encoding 2 -- External reference clock is selected. Reserved. OSC Initialization This bit, which resets to 0, is set to 1 after the initialization cycles of the crystal oscillator clock have completed. After being set, the bit is cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed description for more information. Internal Reference Clock Status The IRCST bit indicates the current source for the internal reference clock select clock (IRCSCLK). The IRCST bit does not update immediately after a write to the IRCS bit due to internal synchronization between clock domains. The IRCST bit will only be updated if the internal reference clock is enabled, either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN] bit . 0 1 Source of internal reference clock is the slow clock (32 kHz IRC). Source of internal reference clock is the fast clock (4 MHz IRC). 25.3.7 MCG Status and Control Register (MCG_SC) Address: 4006_4000h base + 8h offset = 4006_4008h Bit Read Write Reset 7 6 ATME ATMS 0 0 5 ATMF w1c 4 3 FLTPRSRV 0 0 2 1 LOCS0 FCRDIV 0 0 0 w1c 1 0 MCG_SC field descriptions Field 7 ATME Description Automatic Trim Machine Enable Enables the Auto Trim Machine to start automatically trimming the selected Internal Reference Clock. NOTE: ATME deasserts after the Auto Trim Machine has completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim operation and clears this bit. 0 1 6 ATMS Automatic Trim Machine Select Selects the IRCS clock for Auto Trim Test. 0 1 5 ATMF Auto Trim Machine disabled. Auto Trim Machine enabled. 32 kHz Internal Reference Clock selected. 4 MHz Internal Reference Clock selected. Automatic Trim Machine Fail Flag Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 515 Memory Map/Register Definition MCG_SC field descriptions (continued) Field Description Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC registers is detected or the MCG enters into any Stop mode. A write to ATMF clears the flag. 0 1 4 FLTPRSRV FLL Filter Preserve Enable This bit will prevent the FLL filter values from resetting allowing the FLL output frequency to remain the same during clock mode changes where the FLL/DCO output is still valid. (Note: This requires that the FLL reference frequency to remain the same as what it was prior to the new clock mode switch. Otherwise FLL filter and frequency values will change.) 0 1 3-1 FCRDIV FLL filter and FLL frequency will reset on changes to currect clock mode. Fll filter and FLL frequency retain their previous values during new clock mode change. Fast Clock Internal Reference Divider Selects the amount to divide down the fast internal reference clock. The resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the divider when the Fast IRC is enabled is not supported). 000 001 010 011 100 101 110 111 0 LOCS0 Automatic Trim Machine completed normally. Automatic Trim Machine failed. Divide Factor is 1 Divide Factor is 2. Divide Factor is 4. Divide Factor is 8. Divide Factor is 16 Divide Factor is 32 Divide Factor is 64 Divide Factor is 128. OSC0 Loss of Clock Status The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a logic 1 to it when set. 0 1 Loss of OSC0 has not occurred. Loss of OSC0 has occurred. 25.3.8 MCG Auto Trim Compare Value High Register (MCG_ATCVH) Address: 4006_4000h base + Ah offset = 4006_400Ah Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 ATCVH 0 0 0 0 MCG_ATCVH field descriptions Field ATCVH Description ATM Compare Value High K22F Sub-Family Reference Manual, Rev. 4, 08/2016 516 NXP Semiconductors Chapter 25 Multipurpose Clock Generator (MCG) MCG_ATCVH field descriptions (continued) Field Description Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. 25.3.9 MCG Auto Trim Compare Value Low Register (MCG_ATCVL) Address: 4006_4000h base + Bh offset = 4006_400Bh Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 ATCVL 0 0 0 0 MCG_ATCVL field descriptions Field ATCVL Description ATM Compare Value Low Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. 25.3.10 MCG Control 7 Register (MCG_C7) Address: 4006_4000h base + Ch offset = 4006_400Ch Bit Read Write Reset 7 6 5 4 0 0 3 2 1 0 0 0 0 0 OSCSEL 0 0 0 0 MCG_C7 field descriptions Field Description 7-6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5-2 Reserved Reserved OSCSEL MCG OSC Clock Select This field is reserved. This read-only field is reserved and always has the value 0. Selects the MCG FLL external reference clock NOTE: The OSCSEL field can't be changed during MCG modes (like PBE), when external clock is serving as the clock source for MCG. 00 01 Selects Oscillator (OSCCLK0). Selects 32 kHz RTC Oscillator. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 517 Memory Map/Register Definition MCG_C7 field descriptions (continued) Field Description 10 11 Selects Oscillator (OSCCLK1). RESERVED 25.3.11 MCG Control 8 Register (MCG_C8) Address: 4006_4000h base + Dh offset = 4006_400Dh Bit Read Write Reset 7 6 LOCRE1 1 5 0 4 3 0 1 0 CME1 0 2 0 LOCS1 w1c 0 0 0 0 0 MCG_C8 field descriptions Field 7 LOCRE1 Description Loss of Clock Reset Enable Determines if a interrupt or a reset request is made following a loss of RTC external reference clock. The LOCRE1 only has an affect when CME1 is set. 0 1 6 Reserved 5 CME1 This field is reserved. This read-only field is reserved and always has the value 0. Clock Monitor Enable1 Enables the loss of clock monitoring circuit for the output of the RTC external reference clock. The LOCRE1 bit will determine whether an interrupt or a reset request is generated following a loss of RTC clock indication. The CME1 bit should be set to a logic 1 when the MCG is in an operational mode that uses the RTC as its external reference clock or if the RTC is operational. CME1 bit must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a reset request may occur when in Stop mode. CME1 should also be set to a logic 0 before entering VLPR or VLPW power modes. 0 1 4-1 Reserved 0 LOCS1 Interrupt request is generated on a loss of RTC external reference clock. Generate a reset request on a loss of RTC external reference clock External clock monitor is disabled for RTC clock. External clock monitor is enabled for RTC clock. This field is reserved. This read-only field is reserved and always has the value 0. RTC Loss of Clock Status This bit indicates when a loss of clock has occurred. This bit is cleared by writing a logic 1 to it when set. 0 1 Loss of RTC has not occur. Loss of RTC has occur K22F Sub-Family Reference Manual, Rev. 4, 08/2016 518 NXP Semiconductors Chapter 25 Multipurpose Clock Generator (MCG) 25.3.12 MCG Control 12 Register (MCG_C12) Address: 4006_4000h base + 11h offset = 4006_4011h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 3 2 1 0 0 0 0 0 3 2 1 0 0 0 0 0 0 0 0 0 0 MCG_C12 field descriptions Field Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 25.3.12 MCG Status 2 Register (MCG_S2) Address: 4006_4000h base + 12h offset = 4006_4012h Bit Read Write Reset 7 6 5 4 0 0 0 0 0 MCG_S2 field descriptions Field Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 25.3.12 MCG Test 3 Register (MCG_T3) Address: 4006_4000h base + 13h offset = 4006_4013h Bit Read Write Reset 7 6 5 4 0 0 0 0 0 MCG_T3 field descriptions Field Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 519 Functional description 25.4 Functional description 25.4.1 MCG mode state diagram The seven states of the MCG are shown in the following figure and are described in Table 25-1. The arrows indicate the permitted MCG mode transitions. Reset FEI FEE FBI FBE BLPE BLPI Entered from any state when the MCU enters Stop mode Stop Returns to the state that was active before the MCU entered Stop mode, unless a reset occurs while in Stop mode. Figure 25-2. MCG mode state diagram 25.4.1.1 MCG modes of operation The MCG operates in one of the following modes. Note The MCG restricts transitions between modes. For the permitted transitions, see Figure 25-2. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 520 NXP Semiconductors Chapter 25 Multipurpose Clock Generator (MCG) Table 25-1. MCG modes of operation Mode Description FLL Engaged Internal (FEI) FLL engaged internal (FEI) is the default mode of operation and is entered when all the following condtions occur: * 00 is written to C1[CLKS]. * 1 is written to C1[IREFS]. In FEI mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the 32 kHz Internal Reference Clock (IRC). The FLL loop will lock the DCO frequency to the FLL factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency. See the C4[DMX32] bit description for more details. FLL Engaged External (FEE) FLL engaged external (FEE) mode is entered when all the following conditions occur: * 00 is written to C1[CLKS]. * 0 is written to C1[IREFS]. * C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz In FEE mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the external reference clock. The FLL loop will lock the DCO frequency to the FLL factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the external reference frequency, as specified by C1[FRDIV] and C2[RANGE]. See the C4[DMX32] bit description for more details. FLL Bypassed Internal (FBI) FLL bypassed internal (FBI) mode is entered when all the following conditions occur: * 01 is written to C1[CLKS]. * 1 is written to C1[IREFS]. * 0 is written to C2[LP]. In FBI mode, the MCGOUTCLK is derived either from the slow (32 kHz IRC) or fast (4 MHz IRC) internal reference clock, as selected by the C2[IRCS] bit. The FLL is operational but its output is not used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUTCLK is driven from the C2[IRCS] selected internal reference clock. The FLL clock (DCOCLK) is controlled by the slow internal reference clock, and the DCO clock frequency locks to a multiplication factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency. See the C4[DMX32] bit description for more details. FLL Bypassed External FLL bypassed external (FBE) mode is entered when all the following conditions occur: (FBE) * 10 is written to C1[CLKS]. * 0 is written to C1[IREFS]. * C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz. * 0 is written to C2[LP]. In FBE mode, the MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is operational but its output is not used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUTCLK is driven from the external reference clock. The FLL clock (DCOCLK) is controlled by the external reference clock, and the DCO clock frequency locks to a multiplication factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the divided external reference frequency. See the C4[DMX32] bit description for more details. Bypassed Low Power Internal (BLPI) 1 Bypassed Low Power Internal (BLPI) mode is entered when all the following conditions occur: Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 521 Functional description Table 25-1. MCG modes of operation (continued) Mode Description * 01 is written to C1[CLKS]. * 1 is written to C1[IREFS]. * 1 is written to C2[LP]. In BLPI mode, MCGOUTCLK is derived from the internal reference clock. The FLL is disabled Bypassed Low Power External (BLPE) 1 Bypassed Low Power External (BLPE) mode is entered when all the following conditions occur: * 10 is written to C1[CLKS]. * 0 is written to C1[IREFS]. * 1 is written to C2[LP]. In BLPE mode, MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is disabled Stop Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power mode assignments, see the chapter that describes how modules are configured and MCG behavior during Stop recovery. Entering Stop mode, the FLL is disabled, and all MCG clock signals are static except in the following case: MCGIRCLK is active in Normal Stop mode when all the following conditions become true: * C1[IRCLKEN] = 1 * C1[IREFSTEN] = 1 1. Caution: If entering VLPR mode, MCG has to be configured and enter BLPE mode or BLPI mode with the Fast IRC clock selected (C2[IRCS]=1). After it enters VLPR mode, writes to any of the MCG control registers that can cause an MCG clock mode switch to a non low power clock mode must be avoided. NOTE For the chip-specific modes of operation, see the power management chapter of this MCU. 25.4.1.2 MCG mode switching C1[IREFS] can be changed at any time, but the actual switch to the newly selected reference clocks is shown by S[IREFST]. When switching between engaged internal and engaged external modes, the FLL will begin locking again after the switch is completed. C1[CLKS] can also be changed at any time, but the actual switch to the newly selected clock is shown by S[CLKST]. If the newly selected clock is not available, the previous clock will remain selected. The C4[DRST_DRS] write bits can be changed at any time except when C2[LP] bit is 1. If C4[DRST_DRS] write bits are changed while in FLL engaged internal (FEI) or FLL engaged external (FEE) mode, the MCGOUTCLK switches to the new selected DCO range within three clocks of the selected DCO clock. After switching to the new DCO K22F Sub-Family Reference Manual, Rev. 4, 08/2016 522 NXP Semiconductors Chapter 25 Multipurpose Clock Generator (MCG) (indicated by the updated C4[DRST_DRS] read bits), the FLL remains unlocked for several reference cycles. The FLL lock time is provided in the device data sheet as tfll_acquire. 25.4.2 Low-power bit usage C2[LP] is provided to allow the FLL to be disabled and thus conserve power when these systems are not being used. C4[DRST_DRS] can not be written while C2[LP] is 1. However, in some applications, it may be desirable to enable the FLL and allow it to lock for maximum accuracy before switching to an engaged mode. Do this by writing 0 to C2[LP]. 25.4.3 MCG Internal Reference Clocks This module supports two internal reference clocks with nominal frequencies of 32 kHz (slow IRC) and 4 MHz (fast IRC). The fast IRC frequency can be divided down by programming of the FCRDIV to produce a frequency range of 32 kHz to 4 MHz. 25.4.3.1 MCG Internal Reference Clock The MCG Internal Reference Clock (MCGIRCLK) provides a clock source for other onchip peripherals and is enabled when C1[IRCLKEN]=1. When enabled, MCGIRCLK is driven by either the fast internal reference clock (4 MHz IRC which can be divided down by the FRDIV factors) or the slow internal reference clock (32 kHz IRC). The IRCS clock frequency can be re-targeted by trimming the period of its IRCS selected internal reference clock. This can be done by writing a new trim value to the C3[SCTRIM]:C4[SCFTRIM] bits when the slow IRC clock is selected or by writing a new trim value to C4[FCTRIM]:C2[FCFTRIM] when the fast IRC clock is selected. The internal reference clock period is proportional to the trim value written. C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) and C4[FCTRIM]:C2[FCFTRIM] (if C2[IRCS]=1) bits affect the MCGOUTCLK frequency if the MCG is in FBI or BLPI modes. C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) bits also affect the MCGOUTCLK frequency if the MCG is in FEI mode. Additionally, this clock can be enabled in Stop mode by setting C1[IRCLKEN] and C1[IREFSTEN], otherwise this clock is disabled in Stop mode. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 523 Functional description 25.4.4 External Reference Clock The MCG module can support an external reference clock in all modes. See the device datasheet for external reference frequency range. When C1[IREFS] is set, the external reference clock will not be used by the FLL. In these mode, the frequency can be equal to the maximum frequency the chip-level timing specifications will support. If any of the CME bits are asserted the slow internal reference clock is enabled along with the enabled external clock monitor. For the case when C6[CME0]=1, a loss of clock is detected if the OSC0 external reference falls below a minimum frequency (floc_high or floc_low depending on C2[RANGE0]). For the case when C8[CME1]=1, a loss of clock is detected if the RTC external reference falls below a minimum frequency (floc_low). NOTE All clock monitors must be disabled before entering these lowpower modes: Stop, VLPS, VLPR, VLPW, LLS, and VLLSx. On detecting a loss-of-clock event, the MCU generates a system reset if the respective LOCRE bit is set. Otherwise the MCG sets the respective LOCS bit and the MCG generates a LOCS interrupt request. 25.4.5 MCG Fixed Frequency Clock The MCG Fixed Frequency Clock (MCGFFCLK) provides a fixed frequency clock source for other on-chip peripherals; see the block diagram. This clock is driven by either the slow clock from the internal reference clock generator or the external reference clock from the Crystal Oscillator, divided by the FLL reference clock divider. The source of MCGFFCLK is selected by C1[IREFS]. This clock is synchronized to the peripheral bus clock and is valid only when its frequency is not more than 1/8 of the MCGOUTCLK frequency. When it is not valid, it is disabled and held high. The MCGFFCLK is not available when the MCG is in BLPI mode. This clock is also disabled in Stop mode. The FLL reference clock must be set within the valid frequency range for the MCGFFCLK. 25.4.6 MCG Auto TRIM (ATM) The MCG Auto Trim (ATM) is a MCG feature that when enabled, it configures the MCG hardware to automatically trim the MCG Internal Reference Clocks using an external clock as a reference. The selection between which MCG IRC clock gets tested and K22F Sub-Family Reference Manual, Rev. 4, 08/2016 524 NXP Semiconductors Chapter 25 Multipurpose Clock Generator (MCG) enabled is controlled by the ATC[ATMS] control bit (ATC[ATMS]=0 selects the 32 kHz IRC and ATC[ATMS]=1 selects the 4 MHz IRC). If 4 MHz IRC is selected for the ATM, a divide by 128 is enabled to divide down the 4 MHz IRC to a range of 31.250 kHz. When MCG ATM is enabled by writing ATC[ATME] bit to 1, The ATM machine will start auto trimming the selected IRC clock. During the autotrim process, ATC[ATME] will remain asserted and will deassert after ATM is completed or an abort occurs. The MCG ATM is aborted if a write to any of the following control registers is detected : C1, C3, C4, or ATC or if Stop mode is entered. If an abort occurs, ATC[ATMF] fail flag is asserted. The ATM machine uses the bus clock as the external reference clock to perform the IRC auto-trim. Therefore, it is required that the MCG is configured in a clock mode where the reference clock used to generate the system clock is the external reference clock such as FBE clock mode. The MCG must not be configured in a clock mode where selected IRC ATM clock is used to generate the system clock. The bus clock is also required to be running with in the range of 8-16 MHz. To perform the ATM on the selected IRC, the ATM machine uses the successive approximation technique to adjust the IRC trim bits to generate the desired IRC trimmed frequency. The ATM SARs each of the ATM IRC trim bits starting with the MSB. For each trim bit test, the ATM uses a pulse that is generated by the ATM selected IRC clock to enable a counter that counts number of ATM external clocks. At end of each trim bit, the ATM external counter value is compared to the ATCV[15:0] register value. Based on the comparison result, the ATM trim bit under test will get cleared or stay asserted. This is done until all trim bits have been tested by ATM SAR machine. Before the ATM can be enabled, the ATM expected count needs to be derived and stored into the ATCV register. The ATCV expected count is derived based on the required target Internal Reference Clock (IRC) frequency, and the frequency of the external reference clock using the following formula: ATCV * Fr = Target Internal Reference Clock (IRC) Trimmed Frequency * Fe = External Clock Frequency If the auto trim is being performed on the 4 MHz IRC, the calculated expected count value must be multiplied by 128 before storing it in the ATCV register. Therefore, the ATCV Expected Count Value for trimming the 4 MHz IRC is calculated using the following formula. (128) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 525 Initialization / Application information 25.5 Initialization / Application information This section describes how to initialize and configure the MCG module in an application. The following sections include examples on how to initialize the MCG and properly switch between the various available modes. 25.5.1 MCG module initialization sequence The MCG comes out of reset configured for FEI mode. The internal reference will stabilize in tirefsts microseconds before the FLL can acquire lock. As soon as the internal reference is stable, the FLL will acquire lock in tfll_acquire milliseconds. 25.5.1.1 Initializing the MCG Because the MCG comes out of reset in FEI mode, the only MCG modes that can be directly switched to upon reset are FEE, FBE, and FBI modes (see Figure 25-2). Reaching any of the other modes requires first configuring the MCG for one of these three intermediate modes. Care must be taken to check relevant status bits in the MCG status register reflecting all configuration changes within each mode. To change from FEI mode to FEE or FBE modes, follow this procedure: 1. Enable the external clock source by setting the appropriate bits in C2 register. 2. Write to C1 register to select the clock mode. * If entering FEE mode, set C1[FRDIV] appropriately, clear C1[IREFS] bit to switch to the external reference, and leave C1[CLKS] at 2'b00 so that the output of the FLL is selected as the system clock source. * If entering FBE, clear C1[IREFS] to switch to the external reference and change C1[CLKS] to 2'b10 so that the external reference clock is selected as the system clock source. The C1[FRDIV] bits should also be set appropriately here K22F Sub-Family Reference Manual, Rev. 4, 08/2016 526 NXP Semiconductors Chapter 25 Multipurpose Clock Generator (MCG) according to the external reference frequency to keep the FLL reference clock in the range of 31.25 kHz to 39.0625 kHz. Although the FLL is bypassed, it is still on in FBE mode. * The internal reference can optionally be kept running by setting C1[IRCLKEN]. This is useful if the application will switch back and forth between internal and external modes. For minimum power consumption, leave the internal reference disabled while in an external clock mode. 3. Once the proper configuration bits have been set, wait for the affected bits in the MCG status register to be changed appropriately, reflecting that the MCG has moved into the proper mode. * If the MCG is in FEE, FBE, or BLPE mode, and C2[EREFS] was also set in step 1, wait here for S[OSCINIT0] bit to become set indicating that the external clock source has finished its initialization cycles and stabilized. * If in FEE mode, check to make sure S[IREFST] is cleared before moving on. * If in FBE mode, check to make sure S[IREFST] is cleared and S[CLKST] bits have changed to 2'b10 indicating the external reference clock has been appropriately selected. Although the FLL is bypassed, it is still on in FBE mode. 4. Write to the C4 register to determine the DCO output (MCGFLLCLK) frequency range. * By default, with C4[DMX32] cleared to 0, the FLL multiplier for the DCO output is 640. For greater flexibility, if a mid-low-range FLL multiplier of 1280 is desired instead, set C4[DRST_DRS] bits to 2'b01 for a DCO output frequency of 40 MHz. If a mid high-range FLL multiplier of 1920 is desired instead, set the C4[DRST_DRS] bits to 2'b10 for a DCO output frequency of 60 MHz. If a highrange FLL multiplier of 2560 is desired instead, set the C4[DRST_DRS] bits to 2'b11 for a DCO output frequency of 80 MHz. * When using a 32.768 kHz external reference, if the maximum low-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b00 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 732 will be 24 MHz. * When using a 32.768 kHz external reference, if the maximum mid-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b01 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 1464 will be 48 MHz. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 527 Initialization / Application information * When using a 32.768 kHz external reference, if the maximum mid high-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b10 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 2197 will be 72 MHz. * When using a 32.768 kHz external reference, if the maximum high-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b11 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 2929 will be 96 MHz. 5. Wait for the FLL lock time to guarantee FLL is running at new C4[DRST_DRS] and C4[DMX32] programmed frequency. To change from FEI clock mode to FBI clock mode, follow this procedure: 1. Change C1[CLKS] bits in C1 register to 2'b01 so that the internal reference clock is selected as the system clock source. 2. Wait for S[CLKST] bits in the MCG status register to change to 2'b01, indicating that the internal reference clock has been appropriately selected. 3. Write to the C2 register to determine the IRCS output (IRCSCLK) frequency range. * By default, with C2[IRCS] cleared to 0, the IRCS selected output clock is the slow internal reference clock (32 kHz IRC). If the faster IRC is desired, set C2[IRCS] to 1 for a IRCS clock derived from the 4 MHz IRC source. 25.5.2 Using a 32.768 kHz reference In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL multiplication factor of 640, the DCO output (MCGFLLCLK) frequency is 20.97 MHz at low-range. If C4[DRST_DRS] bits are set to 2'b01, the multiplication factor is doubled to 1280, and the resulting DCO output frequency is 41.94 MHz at mid-low-range. If C4[DRST_DRS] bits are set to 2'b10, the multiplication factor is set to 1920, and the resulting DCO output frequency is 62.91 MHz at mid high-range. If C4[DRST_DRS] bits are set to 2'b11, the multiplication factor is set to 2560, and the resulting DCO output frequency is 83.89 MHz at high-range. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 528 NXP Semiconductors Chapter 25 Multipurpose Clock Generator (MCG) In FBI and FEI modes, setting C4[DMX32] bit is not recommended. If the internal reference is trimmed to a frequency above 32.768 kHz, the greater FLL multiplication factor could potentially push the microcontroller system clock out of specification and damage the part. 25.5.3 MCG mode switching When switching between operational modes of the MCG, certain configuration bits must be changed in order to properly move from one mode to another. Each time any of these bits are changed (C1[IREFS], C1[CLKS], C2[IRCS], or C2[EREFS], the corresponding bits in the MCG status register (IREFST, CLKST, IRCST, or OSCINIT) must be checked before moving on in the application software. Additionally, care must be taken to ensure that the reference clock divider (C1[FRDIV]) is set properly for the mode being switched to. For instance, in FEE mode, if using a 4MHz crystal, C1[FRDIV] must be set to 3'b010 (divide-by-128) to devide the external frequency down to the required frequency between 31.25 and 39.0625 kHz. In FBE, FEE, FBI, and FEI modes, at any time, the application can switch the FLL multiplication factor between 640, 1280, 1920, and 2560 with C4[DRST_DRS] bits. Writes to C4[DRST_DRS] bits will be ignored if C2[LP]=1. The table below shows MCGOUTCLK frequency calculations using C1[FRDIV]settings for each clock mode. Table 25-2. MCGOUTCLK Frequency Calculation Options Clock Mode fMCGOUTCLK1 Note FEI (FLL engaged internal) fint x F Typical fMCGOUTCLK = 21 MHz immediately after reset. FEE (FLL engaged external) (fext / FLL_R) x F fext / FLL_R must be in the range of 31.25 kHz to 39.0625 kHz FBE (FLL bypassed external) OSCCLK OSCCLK / FLL_R must be in the range of 31.25 kHz to 39.0625 kHz FBI (FLL bypassed internal) MCGIRCLK Selectable between slow and fast IRC BLPI (Bypassed low power internal) MCGIRCLK Selectable between slow and fast IRC BLPE (Bypassed low power external) OSCCLK 1. FLL_R is the reference divider selected by the C1[FRDIV] bits, F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32] bits . This section will include several mode switching examples, using an MHz external crystal.. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 529 Initialization / Application information 25.5.3.1 Example 1: Moving from FEI to BLPE mode: External Crystal = 4 MHz, MCGOUTCLK frequency = 4 MHz In this example, the MCG will move through the proper operational modes from FEI to BLPE to achieve 4 MHz MCGOUTCLK frequency from 4 MHz external crystal reference. First, the code sequence will be described. Then there is a flowchart that illustrates the sequence. 1. First, FEI must transition to FBE mode: a. C2 = 0x1C * C2[RANGE0] set to 2'b01 because the frequency of 4 MHz is within the high frequency range. * C2[HGO0] set to 1 to configure the crystal oscillator for high gain operation. * C2[EREFS0] set to 1, because a crystal is being used. b. C1 = 0x90 * C1[CLKS] set to 2'b10 to select external reference clock as system clock source * C1[FRDIV] set to 3'b010, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is in the 31.25 kHz to 39.0625 kHz range required by the FLL * C1[IREFS] cleared to 0, selecting the external reference clock and enabling the external oscillator. c. Loop until S[OSCINIT0] is 1, indicating the crystal selected by C2[EREFS0] has been initialized. d. Loop until S[IREFST] is 0, indicating the external reference is the current source for the reference clock. e. Loop until S[CLKST] is 2'b10, indicating that the external reference clock is selected to feed MCGOUTCLK. 2. Then, transition to BLPE: a. Set C2[LP] to 1. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 530 NXP Semiconductors Chapter 25 Multipurpose Clock Generator (MCG) START IN FEI MODE C2 = 0x1C C1 = 0x40 NO CHECK S[OSCINIT0] = 1? YES CHECK S[IREFST] = 0? NO YES CHECK NO S[CLKST] = %10? YES C2 = 0x1E (C2[LP] = 1) Continue in BLPE mode Figure 25-3. Flowchart of FEI to BLPE mode transition using a 4 MHz crystal K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 531 Initialization / Application information 25.5.3.2 Example 2: Moving from BLPE to BLPI mode: MCGOUTCLK frequency = 2 MHz In this example, the MCG will move through the proper operational modes from BLPE mode with a 4 MHz crystal configured for a 4 MHz MCGOUTCLK frequency (see previous example) to BLPI mode with a 2 MHz MCGOUTCLK frequency. First, the code sequence will be described. Then there is a flowchart that illustrates the sequence. 1. First, BLPE must transition to FBE mode: a. Clear C2[LP] to 0 here to switch to FBE mode. 2. Next, FBE mode transitions into FBI mode: a. C1 = 0x54 * C1[CLKS] set to 2'b01 to switch the system clock to the internal reference clock. * C1[IREFS] set to 1 to select the internal reference clock as the reference clock source. * C1[FRDIV] remain unchanged because the reference divider does not affect the internal reference. b. Loop until S[IREFST] is 1, indicating the internal reference clock has been selected as the reference clock source. c. Loop until S[CLKST] are 2'b01, indicating that the internal reference clock is selected to feed MCGOUTCLK. 3. Lastly, FBI transitions into BLPI mode with IRCS selecting Fast Internal Reference Clock. a. C2 = 0x03 * C2[IRCS] is 1 * C2[LP] is 1 * C2[RANGE], C2[HGO], C2[EREFS], C1[IRCLKEN], and C1[IREFSTEN] bits are ignored when the C1[IREFS] bit is set. They can remain set, or be cleared at this point. b. Loop until S[IRCST] is 1, indicating the internal reference clock is the fast clock. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 532 NXP Semiconductors Chapter 25 Multipurpose Clock Generator (MCG) START IN BLPE MODE C2 = 0x1C (C2[LP] = 0) C1 = 0x64 CHECK S[IREFST] = 0? NO YES CHECK S[CLKST] = %01? NO YES C2 = 0x23 CHECK S[IRCST] = 1? NO YES CONTINUE IN BLPI MODE Figure 25-4. Flowchart of BLPE to BLPI mode transition using an MHz crystal K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 533 Initialization / Application information 25.5.3.3 Example 3: Moving from BLPI to FEE mode In this example, the MCG will move through the proper operational modes from BLPI mode at a 32 kHz MCGOUTCLK frequency running off the internal reference clock (see previous example) to FEE mode using a 4 MHz crystal configured for a 20 MHz MCGOUTCLK frequency. First, the code sequence will be described. Then there is a flowchart that illustrates the sequence. 1. First, BLPI must transition to FBI mode. a. C2 = 0x00 * C2[LP] is 0 2. Next, FBI will transition to FEE mode. a. C2 = 0x1C * C2[RANGE] set to 2'b01 because the frequency of 4 MHz is within the high frequency range. * C2[HGO] set to 1 to configure the crystal oscillator for high gain operation. * C2[EREFS] set to 1, because a crystal is being used. b. C1 = 0x10 * C1[CLKS] set to 2'b00 to select the output of the FLL as system clock source. * C1[FRDIV] remain at 3'b010, or divide-by-128 for a reference of 4 MHz / 128 = 31.25 kHz. * C1[IREFS] cleared to 0, selecting the external reference clock. c. Loop until S[OSCINIT] is 1, indicating the crystal selected by the C2[EREFS] bit has been initialized. d. Loop until S[IREFST] is 0, indicating the external reference clock is the current source for the reference clock. e. Loop until S[CLKST] are 2'b00, indicating that the output of the FLL is selected to feed MCGOUTCLK. f. Now, with a 31.25 kHz reference frequency, a fixed DCO multiplier of 640, MCGOUTCLK = 31.25 kHz * 640 / 1 = 20 MHz. g. At this point, by default, the C4[DRST_DRS] bits are set to 2'b00 and C4[DMX32] is cleared to 0. If the MCGOUTCLK frequency of 40 MHz is desired instead, set the C4[DRST_DRS] bits to 0x01 to switch the FLL K22F Sub-Family Reference Manual, Rev. 4, 08/2016 534 NXP Semiconductors Chapter 25 Multipurpose Clock Generator (MCG) multiplication factor from 640 to 1280. To return the MCGOUTCLK frequency to 20 MHz, set C4[DRST_DRS] bits to 2'b00 again, and the FLL multiplication factor will switch back to 640. START IN BLPI MODE CHECK NO S[IREFST] = 0? C2 = 0x00 YES C2 = 0x1C NO CHECK S[CLKST] = %00? C1 = 0x10 YES CONTINUE CHECK S[OSCINIT] = 1 ? NO IN FEE MODE YES Figure 25-5. Flowchart of BLPI to FEE mode transition using an 4 MHz crystal K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 535 Initialization / Application information K22F Sub-Family Reference Manual, Rev. 4, 08/2016 536 NXP Semiconductors Chapter 26 Oscillator (OSC) 26.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The OSC module is a crystal oscillator. The module, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. 26.2 Features and Modes Key features of the module are listed here. * Supports 32 kHz crystals (Low Range mode) * Supports 3-8 MHz, 8-32 MHz crystals and resonators (High Range mode) * Automatic Gain Control (AGC) to optimize power consumption in high frequency ranges 3-8 MHz, 8-32 MHz using low-power mode * High gain option in frequency ranges: 32 kHz, 3-8 MHz, and 8-32 MHz * Voltage and frequency filtering to guarantee clock frequency and stability * Optionally external input bypass clock from EXTAL signal directly * One clock for MCU clock system * Two clocks for on-chip peripherals that can work in Stop modes Functional Description describes the module's operation in more detail. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 537 Block Diagram 26.3 Block Diagram The OSC module uses a crystal or resonator to generate three filtered oscillator clock signals.Three clocks are output from OSC module: OSCCLK for MCU system, OSCERCLK for on-chip peripherals, and OSC32KCLK. The OSCCLK can only work in run mode. OSCERCLK and OSC32KCLK can work in low power modes. For the clock source assignments, refer to the clock distribution information of this MCU. Refer to the chip configuration details for the external reference clock source in this MCU. The figure found here shows the block diagram of the OSC module. EXTAL XTAL Mux OSC Clock Enable OSC_CLK_OUT OSCERCLK_UNDIV ERCLKEN Range selections Low Power config XTL_CLK Oscillator Circuits ERPS EN DIV OSCERCLK OSC32KCLK ERCLKEN OSC clock selection EREFSTEN OSC_EN 4096 Counter Control and Decoding logic CNT_DONE_4096 OSCCLK STOP Figure 26-1. OSC Module Block Diagram 26.4 OSC Signal Descriptions The table found here shows the user-accessible signals available for the OSC module. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 538 NXP Semiconductors Chapter 26 Oscillator (OSC) Refer to signal multiplexing information for this MCU for more details. Table 26-1. OSC Signal Descriptions Signal Description EXTAL External clock/Oscillator input I Oscillator output O XTAL I/O 26.5 External Crystal / Resonator Connections The connections for a crystal/resonator frequency reference are shown in the figures found here. When using low-frequency, low-power mode, the only external component is the crystal or ceramic resonator itself. In the other oscillator modes, load capacitors (Cx, Cy) and feedback resistor (RF) are required. The following table shows all possible connections. Table 26-2. External Caystal/Resonator Connections Oscillator Mode Connections Low-frequency (32 kHz), low-power Connection 1 Low-frequency (32 kHz), high-gain Connection 2/Connection 31 High-frequency (3~32 MHz), low-power Connection 1/Connection 32,2 High-frequency (3~32 MHz), high-gain Connection 2/Connection 32 1. When the load capacitors (Cx, Cy) are greater than 30 pF, use Connection 3. 2. With the low-power mode, the oscillator has the internal feedback resistor RF. Therefore, the feedback resistor must not be externally with the Connection 3. OSC XTAL VSS EXTAL Crystal or Resonator Figure 26-2. Crystal/Ceramic Resonator Connections - Connection 1 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 539 External Clock Connections OSC EXTAL XTAL VSS RF Crystal or Resonator Figure 26-3. Crystal/Ceramic Resonator Connections - Connection 2 NOTE Connection 1 and Connection 2 should use internal capacitors as the load of the oscillator by configuring the CR[SCxP] bits. OSC EXTAL XTAL VSS Cx Cy RF Crystal or Resonator Figure 26-4. Crystal/Ceramic Resonator Connections - Connection 3 26.6 External Clock Connections In external clock mode, the pins can be connected as shown in the figure found here. NOTE XTAL can be used as a GPIO when the GPIO alternate function is configured for it. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 540 NXP Semiconductors Chapter 26 Oscillator (OSC) OSC XTAL VSS EXTAL Clock Input I/O Figure 26-5. External Clock Connections 26.7 Memory Map/Register Definitions Some oscillator module register bits are typically incorporated into other peripherals such as MCG or SIM. 26.7.1 OSC Memory Map/Register Definition OSC memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4006_5000 OSC Control Register (OSC_CR) 8 R/W 00h 26.7.1.1/ 541 4006_5002 OSC_DIV (OSC_OSC_DIV) 8 R/W 00h 26.7.1.2/ 543 26.7.1.1 OSC Control Register (OSC_CR) NOTE After OSC is enabled and starts generating the clocks, the configurations such as low power and frequency range, must not be changed. Address: 4006_5000h base + 0h offset = 4006_5000h Bit Read Write Reset 7 6 5 4 3 2 1 0 ERCLKEN 0 EREFSTEN 0 SC2P SC4P SC8P SC16P 0 0 0 0 0 0 0 0 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 541 OSC Memory Map/Register Definition OSC_CR field descriptions Field 7 ERCLKEN Description External Reference Enable Enables external reference clock (OSCERCLK) . 0 1 6 Reserved 5 EREFSTEN This field is reserved. This read-only field is reserved and always has the value 0. External Reference Stop Enable Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode. 0 1 4 Reserved 3 SC2P Oscillator 2 pF Capacitor Load Configure Configures the oscillator load. Configures the oscillator load. Disable the selection. Add 4 pF capacitor to the oscillator load. Oscillator 8 pF Capacitor Load Configure Configures the oscillator load. 0 1 0 SC16P Disable the selection. Add 2 pF capacitor to the oscillator load. Oscillator 4 pF Capacitor Load Configure 0 1 1 SC8P External reference clock is disabled in Stop mode. External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. This field is reserved. This read-only field is reserved and always has the value 0. 0 1 2 SC4P External reference clock is inactive. External reference clock is enabled. Disable the selection. Add 8 pF capacitor to the oscillator load. Oscillator 16 pF Capacitor Load Configure Configures the oscillator load. 0 1 Disable the selection. Add 16 pF capacitor to the oscillator load. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 542 NXP Semiconductors Chapter 26 Oscillator (OSC) 26.7.1.2 OSC_DIV (OSC_OSC_DIV) OSC Clock divider register. Address: 4006_5000h base + 2h offset = 4006_5002h Bit Read Write Reset 7 6 ERPS 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC_OSC_DIV field descriptions Field 7-6 ERPS Description ERCLK prescaler. These two bits are used to divide the ERCLK output. The un-divided ERCLK output is not affected by these two bits. 00 01 10 11 The divisor ratio is 1. The divisor ratio is 2. The divisor ratio is 4. The divisor ratio is 8. 5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 26.8 Functional Description Functional details of the module can be found here. 26.8.1 OSC module states The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 543 Functional Description Off Oscillator OFF OSC_CLK_OUT = Static OSCCLK not requested OSCCLK requested OSCCLK requested && && Select OSC internal clock Select clock from EXTAL signal Start-Up External Clock Mode Oscillator ON, not yet stable OSC_CLK_OUT = Static Oscillator ON OSC_CLK_OUT = EXTAL CNT_DONE_4096 Stable Oscillator ON, Stable OSC_CLK_OUT = XTL_CLK Figure 26-6. OSC Module state diagram NOTE XTL_CLK is the clock generated internally from OSC circuits. 26.8.1.1 Off The OSC enters the Off state when the system does not require OSC clocks. Upon entering this state, XTL_CLK is static unless OSC is configured to select the clock from the EXTAL pad by clearing the external reference clock selection bit. For details regarding the external reference clock source in this MCU, refer to the chip configuration details. The EXTAL and XTAL pins are also decoupled from all other oscillator circuitry in this state. The OSC module circuitry is configured to draw minimal current. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 544 NXP Semiconductors Chapter 26 Oscillator (OSC) 26.8.1.2 Oscillator startup The OSC enters startup state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit. In this state, the OSC module is enabled and oscillations are starting up, but have not yet stabilized. When the oscillation amplitude becomes large enough to pass through the input buffer, XTL_CLK begins clocking the counter. When the counter reaches 4096 cycles of XTL_CLK, the oscillator is considered stable and XTL_CLK is passed to the output clock OSC_CLK_OUT. 26.8.1.3 Oscillator Stable The OSC enters stable state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit and the counter reaches 4096 cycles of XTL_CLK (when CNT_DONE_4096 is high). In this state, the OSC module is producing a stable output clock on OSC_CLK_OUT. Its frequency is determined by the external components being used. 26.8.1.4 External Clock mode The OSC enters external clock state when it is enabled and external reference clock selection bit is cleared. For details regarding external reference clock source in this MCU, see the chip configuration details. In this state, the OSC module is set to buffer (with hysteresis) a clock from EXTAL onto the OSC_CLK_OUT. Its frequency is determined by the external clock being supplied. 26.8.2 OSC module modes The OSC is a pierce-type oscillator that supports external crystals or resonators operating over the frequency ranges shown in Table 26-3. These modes assume the following conditions: OSC is enabled to generate clocks (OSC_EN=1), configured to generate clocks internally (MCG_C2[EREFS] = 1), and some or one of the other peripherals (MCG, Timer, and so on) is configured to use the oscillator output clock (OSC_CLK_OUT). Table 26-3. Oscillator modes Mode Frequency Range Low-frequency, high-gain fosc_lo (32.768 kHz) up to fosc_lo (39.0625 kHz) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 545 Functional Description Table 26-3. Oscillator modes (continued) Mode Frequency Range High-frequency mode1, high-gain fosc_hi_1 (3 MHz) up to fosc_hi_1 (8 MHz) High-frequency mode1, low-power High-frequency mode2, high-gain fosc_hi_2 (8 MHz) up to fosc_hi_2 (32 MHz) High-frequency mode2, low-power NOTE For information about low power modes of operation used in this chip and their alignment with some OSC modes, see the chip's Power Management details. 26.8.2.1 Low-Frequency, High-Gain Mode In Low-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. The gain is set to achieve rail-to-rail oscillation amplitudes. The oscillator input buffer in this mode is single-ended. It provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. In this mode, the internal capacitors could be used. 26.8.2.2 Low-Frequency, Low-Power Mode In low-frequency, low-power mode, the oscillator uses a gain control loop to minimize power consumption. As the oscillation amplitude increases, the amplifier current is reduced. This continues until a desired amplitude is achieved at steady-state. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. In this mode, the internal capacitors could be used, the internal feedback resistor is connected, and no external resistor should be used. In this mode, the amplifier inputs, gain-control input, and input buffer input are all capacitively coupled for leakage tolerance (not sensitive to the DC level of EXTAL). Also in this mode, all external components except for the resonator itself are integrated, which includes the load capacitors and feeback resistor that biases EXTAL. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 546 NXP Semiconductors Chapter 26 Oscillator (OSC) 26.8.2.3 High-Frequency, High-Gain Mode In high-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. The gain is set to achieve rail-to-rail oscillation amplitudes. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. In this mode, the internal capacitors could be used. 26.8.2.4 High-Frequency, Low-Power Mode In high-frequency, low-power mode, the oscillator uses a gain control loop to minimize power consumption. As the oscillation amplitude increases, the amplifier current is reduced. This continues until a desired amplitude is achieved at steady-state. In this mode, the internal capacitors could be used, the internal feedback resistor is connected, and no external resistor should be used. The oscillator input buffer in this mode is differential. It provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. 26.8.3 Counter The oscillator output clock (OSC_CLK_OUT) is gated off until the counter has detected 4096 cycles of its input clock (XTL_CLK). After 4096 cycles are completed, the counter passes XTL_CLK onto OSC_CLK_OUT. This counting timeout is used to guarantee output clock stability. 26.8.4 Reference clock pin requirements The OSC module requires use of both the EXTAL and XTAL pins to generate an output clock in Oscillator mode, but requires only the EXTAL pin in External clock mode. The EXTAL and XTAL pins are available for I/O. For the implementation of these pins on this device, refer to the Signal Multiplexing chapter. 26.9 Reset There is no reset state associated with the OSC module. The counter logic is reset when the OSC is not configured to generate clocks. There are no sources of reset requests for the OSC module. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 547 Low power modes operation 26.10 Low power modes operation When the MCU enters Stop modes, the OSC is functional depending on CR[ERCLKEN] and CR[EREFSETN] bit settings. If both these bits are set, the OSC is in operation. In Low Leakage Stop (LLS) modes, the OSC holds all register settings. If CR[ERCLKEN] and CR[EREFSTEN] are set before entry to Low Leakage Stop modes, the OSC is still functional in these modes. After waking up from Very Low Leakage Stop (VLLSx) modes, all OSC register bits are reset and initialization is required through software. 26.11 Interrupts The OSC module does not generate any interrupts. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 548 NXP Semiconductors Chapter 27 RTC Oscillator (OSC32K) 27.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The RTC oscillator module provides the clock source for the RTC. The RTC oscillator module, in conjunction with an external crystal, generates a reference clock for the RTC. 27.1.1 Features and Modes The key features of the RTC oscillator are as follows: * Supports 32 kHz crystals with very low power * Consists of internal feed back resistor * Consists of internal programmable capacitors as the Cload of the oscillator * Automatic Gain Control (AGC) to optimize power consumption The RTC oscillator operations are described in detail in Functional Description . 27.1.2 Block Diagram The following is the block diagram of the RTC oscillator. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 549 RTC Signal Descriptions control Amplitude detector clk out for RTC EXTAL32 gm Rf XTAL32 C2 C1 PAD PAD Figure 27-1. RTC Oscillator Block Diagram 27.2 RTC Signal Descriptions The following table shows the user-accessible signals available for the RTC oscillator. See the chip-level specification to find out which signals are actually connected to the external pins. Table 27-1. RTC Signal Descriptions Signal EXTAL32 XTAL32 Description I/O Oscillator Input I Oscillator Output O 27.2.1 EXTAL32 -- Oscillator Input This signal is the analog input of the RTC oscillator. 27.2.2 XTAL32 -- Oscillator Output This signal is the analog output of the RTC oscillator module. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 550 NXP Semiconductors Chapter 27 RTC Oscillator (OSC32K) 27.3 External Crystal Connections The connections with a crystal is shown in the following figure. External load capacitors and feedback resistor are not required. RTC Oscillator Module XTAL32 VSS EXTAL32 Crystal or Resonator Figure 27-2. Crystal Connections 27.4 Memory Map/Register Descriptions RTC oscillator control bits are part of the RTC registers. Refer to RTC Control Register (RTC_CR) , or RTC_GP_DATA_REG in the chip-specific information section, for more details. 27.5 Functional Description As shown in Figure 27-1, the module includes an amplifier which supplies the negative resistor for the RTC oscillator. The gain of the amplifier is controlled by the amplitude detector, which optimizes the power consumption. A schmitt trigger is used to translate the sine-wave generated by this oscillator to a pulse clock out, which is a reference clock for the RTC digital core. The oscillator includes an internal feedback resistor of approximately 100 M between EXTAL32 and XTAL32. In addition, there are two programmable capacitors with this oscillator, which can be used as the Cload of the oscillator. The programmable range is from 0pF to 30pF. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 551 Reset Overview 27.6 Reset Overview There is no reset state associated with the RTC oscillator. 27.7 Interrupts The RTC oscillator does not generate any interrupts. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 552 NXP Semiconductors Chapter 28 Flash Memory Controller (FMC) 28.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The Flash Memory Controller (FMC) is a memory acceleration unit that provides: * an interface between the device and the nonvolatile memory. * buffers that can accelerate flash memory transfers. 28.1.1 Overview The Flash Memory Controller manages the interface between the device and the flash memory. The FMC receives status information detailing the configuration of the memory and uses this information to ensure a proper interface. The following table shows the supported read/write operations. Flash memory type Program flash memory Read 8-bit, 16-bit, and 32-bit reads Write --1 1. A write operation to program flash memory results in a bus error. In addition, for bank 0, the FMC provides three separate mechanisms for accelerating the interface between the device and the flash memory. A 64-bit speculation buffer can prefetch the next 64-bit flash memory location, and both a 4-way, 4-set cache and a single-entry 64-bit buffer can store previously accessed flash memory data for quick access times. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 553 Modes of operation 28.1.2 Features The FMC's features include: * Interface between the device and the flash memory: * 8-bit, 16-bit, and 32-bit read operations to program flash memory. * For bank 0: Read accesses to consecutive 32-bit spaces in memory return the second read data with no wait states. The memory returns 64 bits via the 32-bit bus access. * Crossbar master access protection for setting no access, read-only access, writeonly access, or read/write access for each crossbar master. * For bank 0: Acceleration of data transfer from program flash memory to the device: * 64-bit prefetch speculation buffer with controls for instruction/data access per master * 4-way, 4-set, 64-bit line size cache for a total of sixteen 64-bit entries with controls for replacement algorithm and lock per way * Single-entry buffer * Invalidation control for the speculation buffer and the single-entry buffer 28.2 Modes of operation The FMC only operates when a bus master accesses the flash memory. For any device power mode where the flash memory cannot be accessed, the FMC is disabled. 28.3 External signal description The FMC has no external signals. 28.4 Memory map and register descriptions The programming model consists of the FMC control registers and the program visible cache (data and tag/valid entries). NOTE Program the registers only while the flash controller is idle (for example, execute from RAM). Changing configuration settings K22F Sub-Family Reference Manual, Rev. 4, 08/2016 554 NXP Semiconductors Chapter 28 Flash Memory Controller (FMC) while a flash access is in progress can lead to non-deterministic behavior. Table 28-1. FMC register access Registers Read access Mode Write access Length Mode Length Control registers: PFAPR, PFB0CR, PFB1CR Supervisor (privileged) mode or user mode 32 bits Supervisor (privileged) mode only 32 bits Cache registers Supervisor (privileged) mode or user mode 32 bits Supervisor (privileged) mode only 32 bits NOTE Accesses to unimplemented registers within the FMC's 4 KB address space return a bus error. The cache entries, both data and tag/valid, can be read at any time. NOTE System software is required to maintain memory coherence when any segment of the flash cache is programmed. For example, all buffer data associated with the reprogrammed flash should be invalidated. Accordingly, cache program visible writes must occur after a programming or erase event is completed and before the new memory image is accessed. The cache is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. The following table elaborates on the tag/valid and data entries. Table 28-2. Program visible cache registers Cache storage Based at offset Contents of 32-bit read Nomenclature Nomenclature example Tag 100h 13'h0, tag[18:5], 4'h0, valid In TAGVDWxSy, x denotes the way and y denotes the set. TAGVDW2S0 is the 14-bit tag and 1-bit valid for cache entry way 2, set 0. Data 200h Upper or lower longword of data In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. DATAW1S0U represents bits [63:32] of data entry way 1, set 0, and DATAW1S0L represents bits [31:0] of data entry way 1, set 0. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 555 Memory map and register descriptions FMC memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4001_F000 Flash Access Protection Register (FMC_PFAPR) 32 R/W 00F8_003Fh 28.4.1/558 4001_F004 Flash Bank 0 Control Register (FMC_PFB0CR) 32 R/W 3002_001Fh 28.4.2/560 4001_F008 Reserved (FMC_Reserved) 32 R/W 3000_0000h 28.4.3/562 4001_F100 Cache Tag Storage (FMC_TAGVDW0S0) 32 R/W 0000_0000h 28.4.4/563 4001_F104 Cache Tag Storage (FMC_TAGVDW0S1) 32 R/W 0000_0000h 28.4.4/563 4001_F108 Cache Tag Storage (FMC_TAGVDW0S2) 32 R/W 0000_0000h 28.4.4/563 4001_F10C Cache Tag Storage (FMC_TAGVDW0S3) 32 R/W 0000_0000h 28.4.4/563 4001_F110 Cache Tag Storage (FMC_TAGVDW1S0) 32 R/W 0000_0000h 28.4.5/564 4001_F114 Cache Tag Storage (FMC_TAGVDW1S1) 32 R/W 0000_0000h 28.4.5/564 4001_F118 Cache Tag Storage (FMC_TAGVDW1S2) 32 R/W 0000_0000h 28.4.5/564 4001_F11C Cache Tag Storage (FMC_TAGVDW1S3) 32 R/W 0000_0000h 28.4.5/564 4001_F120 Cache Tag Storage (FMC_TAGVDW2S0) 32 R/W 0000_0000h 28.4.6/565 4001_F124 Cache Tag Storage (FMC_TAGVDW2S1) 32 R/W 0000_0000h 28.4.6/565 4001_F128 Cache Tag Storage (FMC_TAGVDW2S2) 32 R/W 0000_0000h 28.4.6/565 4001_F12C Cache Tag Storage (FMC_TAGVDW2S3) 32 R/W 0000_0000h 28.4.6/565 4001_F130 Cache Tag Storage (FMC_TAGVDW3S0) 32 R/W 0000_0000h 28.4.7/566 4001_F134 Cache Tag Storage (FMC_TAGVDW3S1) 32 R/W 0000_0000h 28.4.7/566 4001_F138 Cache Tag Storage (FMC_TAGVDW3S2) 32 R/W 0000_0000h 28.4.7/566 4001_F13C Cache Tag Storage (FMC_TAGVDW3S3) 32 R/W 0000_0000h 28.4.7/566 4001_F200 Cache Data Storage (upper word) (FMC_DATAW0S0U) 32 R/W 0000_0000h 28.4.8/566 4001_F204 Cache Data Storage (lower word) (FMC_DATAW0S0L) 32 R/W 0000_0000h 28.4.9/567 4001_F208 Cache Data Storage (upper word) (FMC_DATAW0S1U) 32 R/W 0000_0000h 28.4.8/566 4001_F20C Cache Data Storage (lower word) (FMC_DATAW0S1L) 32 R/W 0000_0000h 28.4.9/567 4001_F210 Cache Data Storage (upper word) (FMC_DATAW0S2U) 32 R/W 0000_0000h 28.4.8/566 4001_F214 Cache Data Storage (lower word) (FMC_DATAW0S2L) 32 R/W 0000_0000h 28.4.9/567 4001_F218 Cache Data Storage (upper word) (FMC_DATAW0S3U) 32 R/W 0000_0000h 28.4.8/566 4001_F21C Cache Data Storage (lower word) (FMC_DATAW0S3L) 32 R/W 0000_0000h 28.4.9/567 4001_F220 Cache Data Storage (upper word) (FMC_DATAW1S0U) 32 R/W 0000_0000h 28.4.10/ 567 4001_F224 Cache Data Storage (lower word) (FMC_DATAW1S0L) 32 R/W 0000_0000h 28.4.11/ 568 4001_F228 Cache Data Storage (upper word) (FMC_DATAW1S1U) 32 R/W 0000_0000h 28.4.10/ 567 4001_F22C Cache Data Storage (lower word) (FMC_DATAW1S1L) 32 R/W 0000_0000h 28.4.11/ 568 4001_F230 Cache Data Storage (upper word) (FMC_DATAW1S2U) 32 R/W 0000_0000h 28.4.10/ 567 4001_F234 Cache Data Storage (lower word) (FMC_DATAW1S2L) 32 R/W 0000_0000h 28.4.11/ 568 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 556 NXP Semiconductors Chapter 28 Flash Memory Controller (FMC) FMC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 32 R/W 0000_0000h 28.4.10/ 567 4001_F23C Cache Data Storage (lower word) (FMC_DATAW1S3L) 32 R/W 0000_0000h 28.4.11/ 568 4001_F240 Cache Data Storage (upper word) (FMC_DATAW2S0U) 32 R/W 0000_0000h 28.4.12/ 568 4001_F244 Cache Data Storage (lower word) (FMC_DATAW2S0L) 32 R/W 0000_0000h 28.4.13/ 569 4001_F248 Cache Data Storage (upper word) (FMC_DATAW2S1U) 32 R/W 0000_0000h 28.4.12/ 568 4001_F24C Cache Data Storage (lower word) (FMC_DATAW2S1L) 32 R/W 0000_0000h 28.4.13/ 569 4001_F250 Cache Data Storage (upper word) (FMC_DATAW2S2U) 32 R/W 0000_0000h 28.4.12/ 568 4001_F254 Cache Data Storage (lower word) (FMC_DATAW2S2L) 32 R/W 0000_0000h 28.4.13/ 569 4001_F258 Cache Data Storage (upper word) (FMC_DATAW2S3U) 32 R/W 0000_0000h 28.4.12/ 568 4001_F25C Cache Data Storage (lower word) (FMC_DATAW2S3L) 32 R/W 0000_0000h 28.4.13/ 569 4001_F260 Cache Data Storage (upper word) (FMC_DATAW3S0U) 32 R/W 0000_0000h 28.4.14/ 569 4001_F264 Cache Data Storage (lower word) (FMC_DATAW3S0L) 32 R/W 0000_0000h 28.4.15/ 570 4001_F268 Cache Data Storage (upper word) (FMC_DATAW3S1U) 32 R/W 0000_0000h 28.4.14/ 569 4001_F26C Cache Data Storage (lower word) (FMC_DATAW3S1L) 32 R/W 0000_0000h 28.4.15/ 570 4001_F270 Cache Data Storage (upper word) (FMC_DATAW3S2U) 32 R/W 0000_0000h 28.4.14/ 569 4001_F274 Cache Data Storage (lower word) (FMC_DATAW3S2L) 32 R/W 0000_0000h 28.4.15/ 570 4001_F278 Cache Data Storage (upper word) (FMC_DATAW3S3U) 32 R/W 0000_0000h 28.4.14/ 569 32 R/W 0000_0000h 28.4.15/ 570 4001_F238 Cache Data Storage (upper word) (FMC_DATAW1S3U) 4001_F27C Cache Data Storage (lower word) (FMC_DATAW3S3L) K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 557 Memory map and register descriptions 28.4.1 Flash Access Protection Register (FMC_PFAPR) Address: 4001_F000h base + 0h offset = 4001_F000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved M2PFD M1PFD M0PFD R Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved W R Reserved Reserved Reserved 0 0 M2AP[1:0] M1AP[1:0] M0AP[1:0] W Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 FMC_PFAPR field descriptions Field Description 31-24 Reserved This field is reserved. 23-20 Reserved This field is reserved. This read-only bitfield is reserved. Do not write to this bitfield or indeterminate results will occur. 19 Reserved This field is reserved. 18 M2PFD Master 2 Prefetch Disable These bits control whether prefetching is enabled, based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 1 17 M1PFD Prefetching for this master is enabled. Prefetching for this master is disabled. Master 1 Prefetch Disable These bits control whether prefetching is enabled, based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 1 Prefetching for this master is enabled. Prefetching for this master is disabled. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 558 NXP Semiconductors Chapter 28 Flash Memory Controller (FMC) FMC_PFAPR field descriptions (continued) Field 16 M0PFD Description Master 0 Prefetch Disable These bits control whether prefetching is enabled, based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 1 Prefetching for this master is enabled. Prefetching for this master is disabled. 15-10 Reserved This field is reserved. This read-only bitfield is reserved and is reset to zero. Do not write to this bitfield or indeterminate results will occur. 9-8 Reserved This field is reserved. 7-6 Reserved This field is reserved. 5-4 M2AP[1:0] Master 2 Access Protection This field controls whether read and write access to the flash is allowed, based on the logical master number of the requesting crossbar switch master. 00 01 10 11 3-2 M1AP[1:0] Master 1 Access Protection This field controls whether read and write access to the flash is allowed, based on the logical master number of the requesting crossbar switch master. 00 01 10 11 M0AP[1:0] No access may be performed by this master Only read accesses may be performed by this master Only write accesses may be performed by this master Both read and write accesses may be performed by this master No access may be performed by this master Only read accesses may be performed by this master Only write accesses may be performed by this master Both read and write accesses may be performed by this master Master 0 Access Protection This field controls whether read and write access to the flash is allowed, based on the logical master number of the requesting crossbar switch master. 00 01 10 11 No access may be performed by this master Only read accesses may be performed by this master Only write accesses may be performed by this master Both read and write accesses may be performed by this master K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 559 Memory map and register descriptions 28.4.2 Flash Bank 0 Control Register (FMC_PFB0CR) Address: 4001_F000h base + 4h offset = 4001_F004h Bit 31 30 29 28 27 26 25 24 23 22 B0RWSC[3:0] R 21 20 19 0 0 CINV_WAY[3:0] S_B_ INV 18 17 B0MW[1:0] 16 0 CLCK_WAY[3:0] Reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B0DCE B0ICE B0DPE B0IPE B0SEBE W 1 1 1 1 1 0 R CRC[2:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 FMC_PFB0CR field descriptions Field 31-28 B0RWSC[3:0] Description Bank 0 Read Wait State Control This read-only field defines the number of wait states required to access the bank 0 flash memory. The relationship between the read access time of the flash array (expressed in system clock cycles) and RWSC is defined as: Access time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates this value based on the ratio of the system clock speed to the flash clock speed. For example, when this ratio is 4:1, the field's value is 3h. 27-24 Cache Lock Way x CLCK_WAY[3:0] These bits determine if the given cache way is locked such that its contents will not be displaced by future misses. The bit setting definitions are for each bit in the field. 0 1 Cache way is unlocked and may be displaced Cache way is locked and its contents are not displaced 23-20 Cache Invalidate Way x CINV_WAY[3:0] Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 560 NXP Semiconductors Chapter 28 Flash Memory Controller (FMC) FMC_PFB0CR field descriptions (continued) Field Description These bits determine if the given cache way is to be invalidated (cleared). When a bit within this field is written, the corresponding cache way is immediately invalidated: the way's tag, data, and valid contents are cleared. This field always reads as zero. Cache invalidation takes precedence over locking. The cache is invalidated by system reset. System software is required to maintain memory coherency when any segment of the flash memory is programmed or erased. Accordingly, cache invalidations must occur after a programming or erase event is completed and before the new memory image is accessed. The bit setting definitions are for each bit in the field. 0 1 19 S_B_INV Invalidate Prefetch Speculation Buffer This bit determines if the FMC's prefetch speculation buffer and the single entry page buffer are to be invalidated (cleared). When this bit is written, the speculation buffer and single entry buffer are immediately cleared. This bit always reads as zero. 0 1 18-17 B0MW[1:0] No cache way invalidation for the corresponding cache Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected Speculation buffer and single entry buffer are not affected. Invalidate (clear) speculation buffer and single entry buffer. Bank 0 Memory Width This read-only field defines the width of the bank 0 memory. 00 01 10 11 32 bits 64 bits Reserved Reserved 16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15-8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7-5 CRC[2:0] Cache Replacement Control This 3-bit field defines the replacement algorithm for accesses that are cached. 000 001 010 011 1xx 4 B0DCE Bank 0 Data Cache Enable This bit controls whether data references are loaded into the cache. 0 1 3 B0ICE LRU replacement algorithm per set across all four ways Reserved Independent LRU with ways [0-1] for ifetches, [2-3] for data Independent LRU with ways [0-2] for ifetches, [3] for data Reserved Do not cache data references. Cache data references. Bank 0 Instruction Cache Enable This bit controls whether instruction fetches are loaded into the cache. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 561 Memory map and register descriptions FMC_PFB0CR field descriptions (continued) Field Description 0 1 2 B0DPE Do not cache instruction fetches. Cache instruction fetches. Bank 0 Data Prefetch Enable This bit controls whether prefetches (or speculative accesses) are initiated in response to data references. 0 1 1 B0IPE Do not prefetch in response to data references. Enable prefetches in response to data references. Bank 0 Instruction Prefetch Enable This bit controls whether prefetches (or speculative accesses) are initiated in response to instruction fetches. 0 1 0 B0SEBE Do not prefetch in response to instruction fetches. Enable prefetches in response to instruction fetches. Bank 0 Single Entry Buffer Enable This bit controls whether the single entry page buffer is enabled in response to flash read accesses. A high-to-low transition of this enable forces the page buffer to be invalidated. 0 1 Single entry buffer is disabled. Single entry buffer is enabled. 28.4.3 Reserved (FMC_Reserved) This register address is reserved. Address: 4001_F000h base + 8h offset = 4001_F008h Bit 31 R 30 29 28 27 26 25 24 22 21 20 19 0 Reserved W 23 18 17 16 Reserved 0 Reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 R 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_Reserved field descriptions Field Description 31-28 Reserved This field is reserved. 27-19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 562 NXP Semiconductors Chapter 28 Flash Memory Controller (FMC) FMC_Reserved field descriptions (continued) Field Description 18-17 Reserved This field is reserved. 16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15-8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7-5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Reserved This field is reserved. This read-only field is reserved and always has the value 0. 28.4.4 Cache Tag Storage (FMC_TAGVDW0Sn) The cache is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all sets in the indicated way. Address: 4001_F000h base + 100h offset + (4d x i), where i=0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0 R 17 16 tag[18:5] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reset 0 tag[18:5] W 0 0 0 0 0 0 0 0 0 0 0 0 0 valid 0 0 0 FMC_TAGVDW0Sn field descriptions Field Description 31-19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18-5 tag[18:5] 14-bit tag for cache entry 4-1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 valid 1-bit valid for cache entry K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 563 Memory map and register descriptions 28.4.5 Cache Tag Storage (FMC_TAGVDW1Sn) The cache is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all sets in the indicated way. Address: 4001_F000h base + 110h offset + (4d x i), where i=0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0 R 17 16 tag[18:5] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reset 0 tag[18:5] W 0 0 0 0 0 0 0 0 0 0 0 0 0 valid 0 0 0 FMC_TAGVDW1Sn field descriptions Field Description 31-19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18-5 tag[18:5] 14-bit tag for cache entry 4-1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 valid 1-bit valid for cache entry K22F Sub-Family Reference Manual, Rev. 4, 08/2016 564 NXP Semiconductors Chapter 28 Flash Memory Controller (FMC) 28.4.6 Cache Tag Storage (FMC_TAGVDW2Sn) The cache is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all sets in the indicated way. Address: 4001_F000h base + 120h offset + (4d x i), where i=0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0 R 17 16 tag[18:5] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reset 0 tag[18:5] W 0 0 0 0 0 0 0 0 0 0 0 0 0 valid 0 0 0 FMC_TAGVDW2Sn field descriptions Field Description 31-19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18-5 tag[18:5] 14-bit tag for cache entry 4-1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 valid 1-bit valid for cache entry K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 565 Memory map and register descriptions 28.4.7 Cache Tag Storage (FMC_TAGVDW3Sn) The cache is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all sets in the indicated way. Address: 4001_F000h base + 130h offset + (4d x i), where i=0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0 R 17 16 tag[18:5] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 tag[18:5] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 valid 0 0 0 0 FMC_TAGVDW3Sn field descriptions Field Description 31-19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18-5 tag[18:5] 14-bit tag for cache entry 4-1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 valid 1-bit valid for cache entry 28.4.8 Cache Data Storage (upper word) (FMC_DATAW0SnU) The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 200h offset + (8d x i), where i=0d to 3d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data[63:32] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 K22F Sub-Family Reference Manual, Rev. 4, 08/2016 566 NXP Semiconductors Chapter 28 Flash Memory Controller (FMC) FMC_DATAW0SnU field descriptions Field Description data[63:32] Bits [63:32] of data entry 28.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all sets in the indicated way. Address: 4001_F000h base + 204h offset + (8d x i), where i=0d to 3d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW0SnL field descriptions Field Description data[31:0] Bits [31:0] of data entry 28.4.10 Cache Data Storage (upper word) (FMC_DATAW1SnU) The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 220h offset + (8d x i), where i=0d to 3d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data[63:32] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW1SnU field descriptions Field data[63:32] Description Bits [63:32] of data entry K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 567 Memory map and register descriptions 28.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all sets in the indicated way. Address: 4001_F000h base + 224h offset + (8d x i), where i=0d to 3d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW1SnL field descriptions Field Description data[31:0] Bits [31:0] of data entry 28.4.12 Cache Data Storage (upper word) (FMC_DATAW2SnU) The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 240h offset + (8d x i), where i=0d to 3d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data[63:32] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW2SnU field descriptions Field data[63:32] Description Bits [63:32] of data entry K22F Sub-Family Reference Manual, Rev. 4, 08/2016 568 NXP Semiconductors Chapter 28 Flash Memory Controller (FMC) 28.4.13 Cache Data Storage (lower word) (FMC_DATAW2SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all sets in the indicated way. Address: 4001_F000h base + 244h offset + (8d x i), where i=0d to 3d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW2SnL field descriptions Field Description data[31:0] Bits [31:0] of data entry 28.4.14 Cache Data Storage (upper word) (FMC_DATAW3SnU) The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 260h offset + (8d x i), where i=0d to 3d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data[63:32] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW3SnU field descriptions Field data[63:32] Description Bits [63:32] of data entry K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 569 Functional description 28.4.15 Cache Data Storage (lower word) (FMC_DATAW3SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all sets in the indicated way. Address: 4001_F000h base + 264h offset + (8d x i), where i=0d to 3d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW3SnL field descriptions Field data[31:0] Description Bits [31:0] of data entry 28.5 Functional description The FMC is a flash acceleration unit with flexible buffers for user configuration. Besides managing the interface between the device and the flash memory, the FMC can be used to restrict access from crossbar switch masters and customize the cache and buffers to provide single-cycle system-clock data-access times. Whenever a hit occurs for the prefetch speculation buffer, the cache, or the single-entry buffer, the requested data is transferred within a single system clock. 28.5.1 Default configuration Upon system reset, the FMC is configured to provide a significant level of buffering for transfers from the flash memory: * Crossbar masters 0, 1, 2 have read access to bank 0. * For bank 0: * Prefetch support for data and instructions is enabled for crossbar masters 0, 1, 2. * The cache is configured for least recently used (LRU) replacement for all four ways. * The cache is configured for data or instruction replacement. * The single-entry buffer is enabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 570 NXP Semiconductors Chapter 28 Flash Memory Controller (FMC) 28.5.2 Configuration options Though the default configuration provides a high degree of flash acceleration, advanced users may desire to customize the FMC buffer configurations to maximize throughput for their use cases. When reconfiguring the FMC for custom use cases, do not program the FMC's control registers while the flash memory is being accessed. Instead, change the control registers with a routine executing from RAM in supervisor mode. The FMC's cache and buffering controls within PFB0CR allow the tuning of resources to suit particular applications' needs. The cache and buffer are each controlled individually. The register controls enable buffering and prefetching per access type (instruction fetch or data reference). The cache also supports 3 types of LRU replacement algorithms: * LRU per set across all 4 ways, * LRU with ways [0-1] for instruction fetches and ways [2-3] for data fetches, and * LRU with ways [0-2] for instruction fetches and way [3] for data fetches. As an application example: if both instruction fetches and data references are accessing flash memory, then control is available to send instruction fetches, data references, or both to the cache or the single-entry buffer. Likewise, speculation can be enabled or disabled for either type of access. If both instruction fetches and data references are cached, then the cache's way resources may be divided in several ways between the instruction fetches and data references. 28.5.3 Speculative reads The FMC has a single buffer that reads ahead to the next word in the flash memory if there is an idle cycle. Speculative prefetching is programmable for each bank for instruction and/or data accesses using the B0DPE and B0IPE fields of PFB0CR. Because many code accesses are sequential, using the speculative prefetch buffer improves performance in most cases. When speculative reads are enabled, the FMC immediately requests the next sequential address after a read completes. By requesting the next word immediately, speculative reads can help to reduce or even eliminate wait states when accessing sequential code and/or data. For example, consider the following scenario: * Assume a system with a 4:1 core-to-flash clock ratio and with speculative reads enabled. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 571 Functional description * The core requests four sequential longwords in back-to-back requests, meaning there are no core cycle delays except for stalls waiting for flash memory data to be returned. * None of the data is already stored in the cache or speculation buffer. In this scenario, the sequence of events for accessing the four longwords is as follows: 1. The first longword read requires 4 to 7 core clocks. See Wait states for more information. 2. Due to the 64-bit data bus of the flash memory, the second longword read takes only 1 core clock because the data is already available inside the FMC. While the data for the second longword is being returned to the core, the FMC also starts reading the third and fourth longwords from the flash memory. 3. Accessing the third longword requires 3 core clock cycles. The flash memory read itself takes 4 clocks, but the first clock overlaps with the second longword read. 4. Reading the fourth longword, like the second longword, takes only 1 clock due to the 64-bit flash memory data bus. 28.5.4 Flash Access Control (FAC) Function The Flash Access Control (FAC) is a configurable memory protection scheme optimized to allow end users to use software libraries while offering programmable restrictions to these libraries. The flash memory is divided into equal size segments that provide protection to proprietary software libraries. The protection of these segments is controlled: the FAC provides a cycle-by-cycle evaluation of the access rights for each transaction routed to the on-chip flash memory. Two levels of vendors can add their proprietary software to a device; FAC protection of segments for each level are defined once, using the PGMONCE command. Flash access control aligns to the 3 privilege levels supported by ARM Cortex-M family products: * Most secure state is supervisor/privileged secure: allows execute-only and provides supervisor-only access control. * Mid-level state is execute-only. * Unsecure state is where no access control states are set. Features: * Lightweight access control logic for on-chip flash memory * Flash address space divided into (32 or 64) equal-sized segments (segment size is defined as flash_size [bytes]/(32 or 64)) * Separate control bits for supervisor-only access and execute-only access per segment * Access control evaluated on each bus cycle routed to the flash K22F Sub-Family Reference Manual, Rev. 4, 08/2016 572 NXP Semiconductors Chapter 28 Flash Memory Controller (FMC) * Access violation errors terminate the bus cycle and return zeroes for read data * Programming model allows 2 levels of protected segments 28.5.4.1 Memory map and register definitions The following table shows the mapping of FAC registers. Descriptions of each register and its bit assignments follow. * The Flash Management Unit (FMU) supports access to its FAC programming model via a 32-bit slave peripheral bus connection. * Unimplemented register bits read as zero. * For implementations supporting only 32 segments, only the 32-bit "low" register is implemented. * Writes to any read-only or reserved registers are ignored; attempts to access flash register space above offset '2B' will generate a transfer error. * The terms supervisor and user modes are equivalent to privileged and unprivileged modes. * In this FAC section, n refers to the segment number, and x is the acronym of the module that the registers are in (which sometimes varies from one device to another). x memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 1C Execute-only Access Register (x_XACC) 32 R See section 28.5.4.1.1/ 573 24 Supervisor-only Access Register (x_SACC) 32 R See section 28.5.4.1.2/ 574 28 Configuration Register (x_CR) 32 R See section 28.5.4.1.3/ 575 28.5.4.1.1 Execute-only Access Register (x_XACC) The XACC register provides a bit map for the flash segments to allow execute only or both data and instruction fetches for each associated segment. By definition, execute-only accesses include instruction fetches or PC-relative data loads from the processor. During the reset sequence the XACC register is loaded with a pre-programmed value from non-volatile space in flash. For more about NVM characteristics, see the functional description. Any change made to an NVM location takes effect on the next system reset. The flash basis for the values is signified by x in the reset value. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 573 Functional description Address: 0h base + 1Ch offset = 1Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XA[31:0] R W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * Pre-programmed flash valuex = Undefined at reset. x_XACC field descriptions Field Description XA[31:0] Execute-only Access Control for segments 31-0 0 1 28.5.4.1.2 Associated segment is accessible in execute mode only (as an instruction fetch) Associated segment is accessible as data or in execute mode Supervisor-only Access Register (x_SACC) The SACC register provides a bit map for the flash segments to allow supervisor only or user and supervisor access to the associated segment. During the reset sequence the SACC register is loaded with a pre-programmed value from non-volatile space in flash. For more about NVM characteristics, see the functional description. Any change made to an NVM location takes effect on the next system reset. The flash basis for the values is signified by x in the reset value. Address: 0h base + 24h offset = 24h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SA[31:0] R W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * Pre-programmed flash valuex = Undefined at reset. x_SACC field descriptions Field SA[31:0] Description Supervisor Access for segments 31-0 0 1 Associated segment is accessible in supervisor mode only Associated segment is accessible in user or supervisor mode K22F Sub-Family Reference Manual, Rev. 4, 08/2016 574 NXP Semiconductors Chapter 28 Flash Memory Controller (FMC) 28.5.4.1.3 Configuration Register (x_CR) The FAC Configuration Register provides basic configuration information including the flash segment size and an indicator of segment divisions. The NUMSG and SGSIZE values are fixed for a device. The chip-specific basis for the values is signified by * in the reset value. Address: 0h base + 28h offset = 28h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NUMSG R 15 14 13 12 11 10 9 8 7 6 5 0 4 3 2 1 0 * * * SGSIZE W Reset * * * * * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * * * * Notes: * NUMSG field: Device specific value * SGSIZE field: Device specific value x_CR field descriptions Field 31-24 NUMSG Description Number of Segments Indicator The NUMSG field indicates the number of equal-sized segments in the flash. 0x20 0x40 23-8 Reserved SGSIZE Flash is divided into 32 segments Flash is divided into 64 segments This field is reserved. This read-only field is reserved and always has the value 0. Segment Size The segment size is a fixed value calculated from the available flash size (rounded up to nearest power of 2) divided by 32 or 64, depending on the amount of available program flash. This field determines which bits in the address are used to index into the x_SACC and x_XACC bitmaps to get the appropriate permission flags. The segment size is defined by the equation 2^(8 + SGSIZE[7:0]). The tables below show a sampling of possible settings. Flash Size Segment Size Segment Size Encoding 32 Segment Encodings 16 KBytes 16 KBytes/32 = 512 Bytes 0x1 32 KBytes 32 KBytes/32 = 1 KBytes 0x2 64 KBytes 64 KBytes/32 = 2 KBytes 0x3 128 KBytes 128 KBytes/32 = 4 KBytes 0x4 64 Segment Encodings 256 KBytes 256 KBytes/64 = 4 KBytes 0x4 512 KBytes 512 KBytes/64 = 8 KBytes 0x5 1 MBytes 1 MBytes/64 = 16 KBytes 0x6 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 575 Functional description x_CR field descriptions (continued) Field Description 2 MBytes 2 MBytes/64 = 32 KBytes 0x7 28.5.4.2 FAC functional description The access control functionality is implemented in 2 separate blocks within the SoC. The Flash Management Unit (FMU) includes non-volatile configuration information that is retrieved during reset and and sent to the platform to control access to the flash array during normal operation. There are (4) 32-bit NVM storage locations to support access control features. These NVM locations are summarized in the table below. Table 28-3. NVM Locations NVM location Description NVSACC1, NVSACC2 Two locations are ANDed together and loaded during reset into the x_SACC register to provide access configuration. Segment-wise control for supervisor-only access vs. supervisor and user access NVXACC1, NVXACC2 Two locations are ANDed together and loaded during reset into the x_XACC register to provide access configuration. Segment-wise control for execute-only vs. data and execute Each of these NVM locations is programmable through a Program Once flash command and can be programmed one time. These NVM locations are unaffected by Erase All Blocks flash command and debug interface initiated mass erase operations. Since the 2 NVXACCx fields are ANDed, the access protection can only be increased. A segment's access controls can be changed from data read and execute (XAn =1) to execute-only (XAn =0), or from supervisor and user mode (SAn = 1) to supervisor-only mode (SAn = 0). The flash is released from reset early while the core continues to be held in reset. The FMU captures the NVM access control information in internal registers. The FMU ANDs the multiple execute-only fields to create a single execute-only field. This execute-only field driven to the platform is static prior to the core being released from reset. The supervisor-only field is handled in the same manner. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 576 NXP Semiconductors Chapter 28 Flash Memory Controller (FMC) The FMU includes the FAC registers that provide control access to the flash address space. During the address phase of every attempted flash transfer, the supervisor access (SAn) and execute access (XAn) bits are examined to either allow or deny access. If access is denied, then the access is aborted and terminates with a bus error; the read data is also zeroed. The next table shows segment assignments relative to the flash location. Table 28-4. Flash Protection Ranges SAn and XAn Bit Protected Segment Address Range Segment Size (Fraction of total Flash) 64 Segment Encodings 0 0x0_0000_0000 - (Flash_size/64-1) 1/64 1 (Flash_size/64) - 2*(Flash_size/64-1) 1/64 63*(Flash_size/64) - 62*(Flash_size/64-1) 1/64 ........ 63 32 Segment Encodings 0 0x0_0000_0000 - (Flash_size/32-1) 1/32 1 (Flash_size/32) - 2*(Flash_size/32-1) 1/32 31*(Flash_size/32) - 30*(Flash_size/32-1) 1/32 ........ 31 Individual segments within the flash memory can be independently protected from user access and data access. Protection is controlled by the individual bits within the x_SACC and x_XACC registers, as shown in the next figure. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 577 Functional description Access Control bits (SAn/XAn) Program flash 0x0000_0000 Program flash size / 32 SA0/XA0 Program flash size / 32 SA1/XA1 Program flash size / 32 SA2/XA2 Program flash size / 32 SA3/XA3 Program flash size / 32 SA29/XA29 Program flash size / 32 SA30/XA30 Program flash size / 32 SA31/XA31 32 segments Last program flash address Figure 28-1. Program flash protection (32 segments) 28.5.4.2.1 Signal Interface Signals Table 28-5. Interface Signals Width From To Description xacc 64 or 32 FMU Platform Direct xacc (execute-only access control) register sacc 64 or 32 FMU Platform Direct sacc (supervisor access control) register numsg 8 FMU Platform NUMSG bit field - Binary encoded number of segments 0x40 for 64 segments 0x20 for 32 segments fac_enable 1 SIM FMU SIM Option bit - derived from an IFR bit and captured in SIM_SOPTx. A way to disable the flash access control for phantom devices without this feature. fac_enable==1 - Access Control feature is enabled fac_enable==0 - Access Control feature is disabled * During the reset sequence, XACC registers are written to all "1"s. * During the reset sequence, SACC registers are written to all 1"s. * Implied protection based on XACC registers is turned off. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 578 NXP Semiconductors Chapter 28 Flash Memory Controller (FMC) 28.5.4.2.2 Flash Command Impact Program Longword/Phrase/ If the targeted flash location is in an execute-only protected segment, then these program Section commands are not allowed unless a Read 1s All Blocks command is executed and returns with a pass code (which means the part has been fully erased). After the Read 1s All Blocks command is executed with a pass code returned, then the protected segment is open to program commands. To close off programmability to execute-only spaces once again, the device must be reset or a Read 1s All Blocks command is executed with a fail result. Attempts to program in a protected segment when not open to program commands causes a Protection Violation flag. PGMCHK The FMU will not execute the PGMCHK command on a segment that has been configured as execute-only. The Flash Protection Violation flag is set if an attempt is made to execute PGMCHK command on an execute-only address. Erase Flash Sector If the targeted flash sector is in an execute-only protected segment, then the Erase Flash Sector command is not allowed, and sets the Protection Violation flag. The only means of erasing protected space is by an Erase All operation. ERSALL The Erase All Blocks command is not affected by Access Control. An Erase All Blocks command will erase any libraries that have been programmed in any execute-only segment. The programmed execute-only assignment is not erased as part of the Erase All Blocks command, and access control regions remain as previously programmed. NOTE: The ERSALL command may be used for field upgrades. Access control states remain programmed. Software must plan accordingly, possibly making extra space available for future use. ERSXA The target regions of the command is controlled by FAC. For ERSXA, if a flash sector is in an execute-only protected segment and it is not protected by flash protection (FPROT), it will be erased. RD1XA The target regions of the command is controlled by FAC. For RD1XA, if a flash sector is in an execute-only protected segment, it will be erase verified. 28.5.4.2.3 Core Platform Impact Platform core caches (Flash If any segment is marked as execute-only, then the caches are hidden from the user. The tag and LMEM caches) is read-only and cannot be written, and the data caches cannot be read or written. Writes to the tag and data arrays are ignored, and reads of the data array return 0's. This will impact debug breakpoints. See the debug section for details. Debug The debugger is a non-processor bus master and cannot step, trace or break in execute-only regions. In supervisor-only mode, the debugger is restricted from changing modes. Debug accesses to any segment of flash space marked as execute-only also terminate with a bus error. PC-relative addressing The PC-relative addressing issue is still being understood and this section will be updated in the future. PC relative re-entry to execute-only segments will be allowed......... Restrictions will be placed on software for PC relative addressing, because hardware cannot determine if PC relative data references are crossing segment boundaries. * If ifetch is executing in a protected segment, then data references will be allowed. * Hardware cannot track speculative ifetches across boundaries. Interrupts If function calls are used to move into an execute-only segment, then this can be tracked by hardware when typical software controls are used (i.e., saving registers and states before executing new code). Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 579 Functional description Reset Vector In the ARM core, the reset vector fetch is supervisor data, which poses issues if the reset vector is located in a segment marked execute-only. Additional logic has been implemented to allow supervisor data fetches to execute-only spaces, after reset until the first valid instruction fetch. After the first valid instruction fetch, the FAC logic follows normal checks. 28.5.4.2.4 Software Impact As implementation, verification and validation continue, there will be more details on software impact that will need to be communicated to tool and library vendors. The hardware cannot see all states of the ARM core and cannot track the software flow, and may require software restrictions to work with the hardware for a robust solution. * Any segment marked as execute-only can see all code in the system. This means that one execute-only segment can read the execute-only code in another segment. Therefore, if we at the factory are sending pre-loaded code to another vendor, then that vendor will have access to our factory code. NDAs and legal agreements might help deal with this issue. * For single pre-loads (for example, if we at the factory are pre-loading for a general purpose (GP) market or if a vendor with a blank part is pre-loading their proprietary code), then both levels of access control must be programmed, to protect the preloaded code. * If any portion of a protected segment is not used by pre-loaded code, then it (the portion of a protected segment that is not used by pre-loaded code) should be programmed with NOPs, to prevent additional code from being programmed in that segment by hackers. 28.5.4.2.5 Access Check Evaluation The flash controller FAC provides a cycle-by-cycle evaluation of the access rights for each data transaction routed to the on-chip flash memory. The entire flash storage capacity is partitioned into equal sized segments. Two registers include a supervisor-only access control indicator and a execute-only access control indicator for each segment. The FAC logic performs the required access control evaluation using the reference address and a 2-bit attribute (or "protection" field) as inputs from the bus cycle plus the contents of the programming model registers. The following code example illustrates C code for FAC evaluation: unsigned unsigned unsigned unsigned long long sacc; long long xacc; int seg_size; int fac_error; // supervisor-only map // execute-only map // 8-bit segment size K22F Sub-Family Reference Manual, Rev. 4, 08/2016 580 NXP Semiconductors Chapter 28 Flash Memory Controller (FMC) fac_evaluation unsigned int unsigned int { unsigned int unsigned int unsigned int (addr, prot) addr; // access address hprot; // encoded 2-bit "protection" field {supv, data} sacc_flag; // sacc flag for this segment xacc_flag; // xacc flag for this segment i; // segment index i = (addr >> (8 + seg_size & 0x0f)) & 0x3f; // form 6-bit segment index sacc_flag = (sacc >> i) & 1; // extract sacc bit for this segment xacc_flag = (xacc >> i) & 1; // extract xacc bit for this segment // create a 4-tuple concatenating the 2-bit protection field + {sacc, xacc} flags switch ((hprot & 3) << 2 | (sacc_flag << 1) | xacc_flag) { // all these combinations are allowed accesses case 0x2: // {user, ifetch} && {supv+user, ifetch-only} case 0x3: // {user, ifetch} && {supv+user, ifetch+data} case 0x7: // {user, data} && {supv+user, ifetch+data} case 0x8: // {supv, ifetch} && {supv-only, ifetch-only} case 0x9: // {supv, ifetch} && {supv-only, ifetch+data} case 0xa: // {supv, ifetch} && {supv+user, ifetch-only} case 0xb: // {supv, ifetch} && {supv+user, ifetch+data} case 0xd: // {supv, data} && {supv-only, ifetch+data} case 0xf: // {supv, data} && {supv+user, ifetch+data} fac_error = 00; break; // all these combinations are case 0x0: // {user, ifetch} case 0x1: // {user, ifetch} case 0x4: // {user, data} case 0x5: // {user, data} case 0x6: // {user, data} case 0xc: // {supv, data} case 0xe: // {supv, data} fac_error = 1; break; unallowed, that is, errored accesses && {supv-only, ifetch-only} && {supv-only, ifetch+data} && {supv-only, ifetch-only} && {supv-only, ifetch+data} && {supv+user, ifetch-only} && {supv-only, ifetch-only} && {supv+user, ifetch-only} } // switch() } // fac_evaluation() 28.5.4.2.6 FAC application tips In one use case, the NVSACC1 and NVXACC1 locations are programmed by NXP and they protect NXP libraries that have been programmed into associated flash segments in a device. Later, the NVSACC2 and NVXACC2 NVM locations can optionally be programmed by a third-party vendor who wants to program their proprietary software and to extend the protection of protected flash segments to include their software libraries before supplying it all to their customers. Their customer would then develop their own code to use the available libraries, and program their code into the remaining available on-chip flash. The device continues to support the end user with standard security features that further limit external access to flash resources. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 581 Initialization and application information 28.6 Initialization and application information The FMC does not require user initialization. Flash acceleration features are enabled by default. The FMC has no visibility into flash memory erase and program cycles because the Flash Memory module manages them directly. As a result, if an application is executing flash memory commands, the FMC's cache might need to be disabled and/or flushed to prevent the possibility of returning stale data. Use the PFB0CR[CINV_WAY] field to invalidate the cache in this manner. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 582 NXP Semiconductors Chapter 29 Flash Memory Module (FTFA) 29.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The flash memory module includes the following accessible memory regions: * Program flash memory for vector space and code store Flash memory is ideal for single-supply applications, permitting in-the-field erase and reprogramming operations without the need for any external high voltage power sources. The flash memory module includes a memory controller that executes commands to modify flash memory contents. An erased bit reads '1' and a programmed bit reads '0'. The programming operation is unidirectional; it can only move bits from the '1' state (erased) to the '0' state (programmed). Only the erase operation restores bits from '0' to '1'; bits cannot be programmed from a '0' to a '1'. CAUTION A flash memory location must be in the erased state before being programmed. Cumulative programming of bits (back-toback program operations without an intervening erase) within a flash memory location is not allowed. Re-programming of existing 0s to 0 is not allowed as this overstresses the device. The standard shipping condition for flash memory is erased with security disabled. Data loss over time may occur due to degradation of the erased ('1') states and/or programmed ('0') states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 583 Introduction 29.1.1 Features The flash memory module includes the following features. NOTE See the device's Chip Configuration details for the exact amount of flash memory available on your device. 29.1.1.1 Program Flash Memory Features * Sector size of 2 KB * Program flash protection scheme prevents accidental program or erase of stored data * Program flash access control scheme prevents unauthorized access to selected code segments * Automated, built-in, program and erase algorithms with verify 29.1.1.2 Other Flash Memory Module Features * Internal high-voltage supply generator for flash memory program and erase operations * Optional interrupt generation upon flash command completion * Supports MCU security mechanisms which prevent unauthorized access to the flash memory contents 29.1.2 Block Diagram The block diagram of the flash memory module is shown in the following figure. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 584 NXP Semiconductors Chapter 29 Flash Memory Module (FTFA) Interrupt Register access Status registers Memory controller To MCU's flash controller Program flash 0 Control registers Figure 29-1. Flash Block Diagram 29.1.3 Glossary Command write sequence -- A series of MCU writes to the flash FCCOB register group that initiates and controls the execution of flash algorithms that are built into the flash memory module. Endurance -- The number of times that a flash memory location can be erased and reprogrammed. FCCOB (Flash Common Command Object) -- A group of flash registers that are used to pass command, address, data, and any associated parameters to the memory controller in the flash memory module. Flash block -- A macro within the flash memory module which provides the nonvolatile memory storage. Flash Memory Module -- All flash blocks plus a flash management unit providing high-level control and an interface to MCU buses. HSRUN -- An MCU power mode enabling high-speed access to the memory resources in the flash module. The user has no access to the flash command set when the MCU is in HSRUN mode. IFR -- Nonvolatile information register found in each flash block, separate from the main memory array. Longword -- 32 bits of data with an aligned longword having byte-address[1:0] = 00. NVM -- Nonvolatile memory. A memory technology that maintains stored data during power-off. The flash array is an NVM using NOR-type flash memory technology. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 585 External Signal Description NVM Normal Mode -- An NVM mode that provides basic user access to flash memory module resources. The CPU or other bus masters initiate flash program and erase operations (or other flash commands) using writes to the FCCOB register group in the flash memory module. NVM Special Mode -- An NVM mode enabling external, off-chip access to the memory resources in the flash memory module. A reduced flash command set is available when the MCU is secured. See the Chip Configuration details for information on when this mode is used. Phrase -- 64 bits of data with an aligned phrase having byte-address[2:0] = 000. Program flash -- The program flash memory provides nonvolatile storage for vectors and code store. Program flash Sector -- The smallest portion of the program flash memory (consecutive addresses) that can be erased. Retention -- The length of time that data can be kept in the NVM without experiencing errors upon readout. Since erased (1) states are subject to degradation just like programmed (0) states, the data retention limit may be reached from the last erase operation (not from the programming time). RWW-- Read-While-Write. The ability to simultaneously read from one memory resource while commanded operations are active in another memory resource. Secure -- An MCU state conveyed to the flash memory module as described in the Chip Configuration details for this device. In the secure state, reading and changing NVM contents is restricted. Word -- 16 bits of data with an aligned word having byte-address[0] = 0. 29.2 External Signal Description The flash memory module contains no signals that connect off-chip. 29.3 Memory Map and Registers This section describes the memory map and registers for the flash memory module. Data read from unimplemented memory space in the flash memory module is undefined. Writes to unimplemented or reserved memory space (registers) in the flash memory module are ignored. K22F Sub-Family Reference Manual, Rev. 4, 08/2016 586 NXP Semiconductors Chapter 29 Flash Memory Module (FTFA) 29.3.1 Flash Configuration Field Description The program flash memory contains a 16-byte flash configuration field that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the flash memory module. Flash Configuration Field Offset Address Size (Bytes) Field Description 0x0_0400-0x0_0407 8 Backdoor Comparison Key. Refer to Verify Backdoor Access Key Command and Unsecuring the Chip Using Backdoor Key Access. 0x0_0408-0x0_040B 4 Program flash protection bytes. Refer to the description of the Program Flash Protection Registers (FPROT0-3). 0x0_040F 1 Reserved 0x0_040E 1 Reserved 0x0_040D 1 Flash nonvolatile option byte. Refer to the description of the Flash Option Register (FOPT). 0x0_040C 1 Flash security byte. Refer to the description of the Flash Security Register (FSEC). 29.3.2 Program Flash IFR Map The program flash IFR is nonvolatile information memory that can be read freely, but the user has no erase and limited program capabilities (see the Read Once, Program Once, and Read Resource commands in Read Once Command, Program Once Command and Read Resource Command). The contents of the program flash IFR are summarized in the table found here and further described in the subsequent paragraphs. The program flash IFR is located within the program flash 0 memory block . Address Range Size (Bytes) Field Description 0x00 - 0x9F 160 Reserved 0xA0 - 0xA3 4 Program Once XACCH-1 Field (index = 0x10) 0xA4 - 0xA7 4 Program Once XACCL-1 Field (index = 0x10) Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 587 Memory Map and Registers Address Range Size (Bytes) 0xA8 - 0xAB 4 0xAC - 0xAF 4 0xB0 - 0xB3 4 Field Description Program Once XACCH-2 Field (index = 0x11) Program Once XACCL-2 Field (index = 0x11) Program Once SACCH-1 Field (index = 0x12) 0xB4 - 0xB7 4 Program Once SACCL-1 Field (index = 0x12) 0xB8 - 0xBB 4 Program Once SACCH-2 Field (index = 0x13) 0xBC - 0xBF 4 Program Once SACCL-2 Field (index = 0x13) 0xC0 - 0xFF 64 Program Once ID Field (index = 0x00 - 0x0F) 29.3.2.1 Program Once Field The Program Once Field in the program flash IFR provides 96 bytes of user data storage separate from the program flash main array. The user can program the Program Once Field one time only as there is no program flash IFR erase mechanism available to the user. The Program Once Field can be read any number of times. This section of the program flash IFR is accessed in 4-byte or 8-Byte records using the Read Once and Program Once commands (see Read Once Command and Program Once Command). 29.3.3 Register Descriptions The flash memory module contains a set of memory-mapped control and status registers. NOTE While a command is running (FSTAT[CCIF]=0), register writes are not accepted to any register except FCNFG and FSTAT. The no-write rule is relaxed during the start-up reset sequence, prior to the initial rise of CCIF. During this initialization period the user may write any register. All register writes are also disabled (except for registers FCNFG and FSTAT) whenever an erase suspend request is active (FCNFG[ERSSUSP]=1). K22F Sub-Family Reference Manual, Rev. 4, 08/2016 588 NXP Semiconductors Chapter 29 Flash Memory Module (FTFA) FTFA memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_0000 Flash Status Register (FTFA_FSTAT) 8 R/W 00h 29.3.3.1/ 590 4002_0001 Flash Configuration Register (FTFA_FCNFG) 8 R/W 00h 29.3.3.2/ 592 4002_0002 Flash Security Register (FTFA_FSEC) 8 R Undefined 29.3.3.3/ 593 4002_0003 Flash Option Register (FTFA_FOPT) 8 R Undefined 29.3.3.4/ 594 4002_0004 Flash Common Command Object Registers (FTFA_FCCOB3) 8 R/W 00h 29.3.3.5/ 595 4002_0005 Flash Common Command Object Registers (FTFA_FCCOB2) 8 R/W 00h 29.3.3.5/ 595 4002_0006 Flash Common Command Object Registers (FTFA_FCCOB1) 8 R/W 00h 29.3.3.5/ 595 4002_0007 Flash Common Command Object Registers (FTFA_FCCOB0) 8 R/W 00h 29.3.3.5/ 595 4002_0008 Flash Common Command Object Registers (FTFA_FCCOB7) 8 R/W 00h 29.3.3.5/ 595 4002_0009 Flash Common Command Object Registers (FTFA_FCCOB6) 8 R/W 00h 29.3.3.5/ 595 4002_000A Flash Common Command Object Registers (FTFA_FCCOB5) 8 R/W 00h 29.3.3.5/ 595 4002_000B Flash Common Command Object Registers (FTFA_FCCOB4) 8 R/W 00h 29.3.3.5/ 595 4002_000C Flash Common Command Object Registers (FTFA_FCCOBB) 8 R/W 00h 29.3.3.5/ 595 4002_000D Flash Common Command Object Registers (FTFA_FCCOBA) 8 R/W 00h 29.3.3.5/ 595 4002_000E Flash Common Command Object Registers (FTFA_FCCOB9) 8 R/W 00h 29.3.3.5/ 595 4002_000F Flash Common Command Object Registers (FTFA_FCCOB8) 8 R/W 00h 29.3.3.5/ 595 4002_0010 Program Flash Protection Registers (FTFA_FPROT3) 8 R/W Undefined 29.3.3.6/ 596 4002_0011 Program Flash Protection Registers (FTFA_FPROT2) 8 R/W Undefined 29.3.3.6/ 596 4002_0012 Program Flash Protection Registers (FTFA_FPROT1) 8 R/W Undefined 29.3.3.6/ 596 4002_0013 Program Flash Protection Registers (FTFA_FPROT0) 8 R/W Undefined 29.3.3.6/ 596 4002_0018 Execute-only Access Registers (FTFA_XACCH3) 8 R Undefined 29.3.3.7/ 598 4002_0019 Execute-only Access Registers (FTFA_XACCH2) 8 R Undefined 29.3.3.7/ 598 Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 589 Memory Map and Registers FTFA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_001A Execute-only Access Registers (FTFA_XACCH1) 8 R Undefined 29.3.3.7/ 598 4002_001B Execute-only Access Registers (FTFA_XACCH0) 8 R Undefined 29.3.3.7/ 598 4002_001C Execute-only Access Registers (FTFA_XACCL3) 8 R Undefined 29.3.3.7/ 598 4002_001D Execute-only Access Registers (FTFA_XACCL2) 8 R Undefined 29.3.3.7/ 598 4002_001E Execute-only Access Registers (FTFA_XACCL1) 8 R Undefined 29.3.3.7/ 598 4002_001F Execute-only Access Registers (FTFA_XACCL0) 8 R Undefined 29.3.3.7/ 598 4002_0020 Supervisor-only Access Registers (FTFA_SACCH3) 8 R Undefined 29.3.3.8/ 599 4002_0021 Supervisor-only Access Registers (FTFA_SACCH2) 8 R Undefined 29.3.3.8/ 599 4002_0022 Supervisor-only Access Registers (FTFA_SACCH1) 8 R Undefined 29.3.3.8/ 599 4002_0023 Supervisor-only Access Registers (FTFA_SACCH0) 8 R Undefined 29.3.3.8/ 599 4002_0024 Supervisor-only Access Registers (FTFA_SACCL3) 8 R Undefined 29.3.3.8/ 599 4002_0025 Supervisor-only Access Registers (FTFA_SACCL2) 8 R Undefined 29.3.3.8/ 599 4002_0026 Supervisor-only Access Registers (FTFA_SACCL1) 8 R Undefined 29.3.3.8/ 599 4002_0027 Supervisor-only Access Registers (FTFA_SACCL0) 8 R Undefined 29.3.3.8/ 599 4002_0028 Flash Access Segment Size Register (FTFA_FACSS) 8 R Undefined 29.3.3.9/ 600 4002_002B Flash Access Segment Number Register (FTFA_FACSN) 8 R Undefined 29.3.3.10/ 601 29.3.3.1 Flash Status Register (FTFA_FSTAT) The FSTAT register reports the operational status of the flash memory module. The CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable. NOTE When set, the Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this register prevent the launch of K22F Sub-Family Reference Manual, Rev. 4, 08/2016 590 NXP Semiconductors Chapter 29 Flash Memory Module (FTFA) any more commands until the flag is cleared (by writing a one to it). Address: 4002_0000h base + 0h offset = 4002_0000h 7 6 5 4 Read Bit CCIF RDCOLERR ACCERR FPVIOL 3 Write w1c w1c w1c w1c Reset 0 0 0 0 2 1 0 0 0 0 MGSTAT0 0 0 FTFA_FSTAT field descriptions Field 7 CCIF Description Command Complete Interrupt Flag Indicates that a flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command, and CCIF stays low until command completion or command violation. CCIF is reset to 0 but is set to 1 by the memory controller at the end of the reset initialization sequence. Depending on how quickly the read occurs after reset release, the user may or may not see the 0 hardware reset value. 0 1 6 RDCOLERR Flash Read Collision Error Flag Indicates that the MCU attempted a read from a flash memory resource that was being manipulated by a flash command (CCIF=0). Any simultaneous access is detected as a collision error by the block arbitration logic. The read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by writing a 1 to it. Writing a 0 to RDCOLERR has no effect. 0 1 5 ACCERR No collision error detected Collision error detected Flash Access Error Flag Indicates an illegal access has occurred to a flash memory resource caused by a violation of the command write sequence or issuing an illegal flash command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to ACCERR while CCIF is set. Writing a 0 to the ACCERR bit has no effect. 0 1 4 FPVIOL Flash command in progress Flash command has completed No access error detected Access error detected Flash Protection Violation Flag Indicates an attempt was made to program or erase an address in a protected area of program flash memory during a command write sequence . While FPVIOL is set, the CCIF flag cannot be cleared to launch a command. The FPVIOL bit is cleared by writing a 1 to FPVIOL while CCIF is set. Writing a 0 to the FPVIOL bit has no effect. 0 1 No protection violation detected Protection violation detected 3-1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 MGSTAT0 Memory Controller Command Completion Status Flag Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 591 Memory Map and Registers FTFA_FSTAT field descriptions (continued) Field Description The MGSTAT0 status flag is set if an error is detected during execution of a flash command or during the flash reset sequence. As a status flag, this field cannot (and need not) be cleared by the user like the other error flags in this register. The value of the MGSTAT0 bit for "command-N" is valid only at the end of the "command-N" execution when CCIF=1 and before the next command has been launched. At some point during the execution of "command-N+1," the previous result is discarded and any previous error is cleared. 29.3.3.2 Flash Configuration Register (FTFA_FCNFG) This register provides information on the current functional state of the flash memory module. The erase control bits (ERSAREQ and ERSSUSP) have write restrictions. The unassigned bits read as noted and are not writable. Address: 4002_0000h base + 1h offset = 4002_0001h Bit Read Write Reset 7 6 5 CCIE RDCOLLIE 0 0 ERSAREQ 0 4 ERSSUSP 0 3 2 1 0 0 0 0 0 0 0 0 0 FTFA_FCNFG field descriptions Field 7 CCIE Description Command Complete Interrupt Enable Controls interrupt generation when a flash command completes. 0 1 6 RDCOLLIE Read Collision Error Interrupt Enable Controls interrupt generation when a flash memory read collision error occurs. 0 1 5 ERSAREQ Command complete interrupt disabled Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. Read collision error interrupt disabled Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]). Erase All Request Issues a request to the memory controller to execute the Erase All Blocks command and release security. ERSAREQ is not directly writable but is under indirect user control. Refer to the device's Chip Configuration details on how to request this command. ERSAREQ sets when an erase all request is triggered external to the flash memory module and CCIF is set (no command is currently being executed). ERSAREQ is cleared by the flash memory module when the operation completes. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 592 NXP Semiconductors Chapter 29 Flash Memory Module (FTFA) FTFA_FCNFG field descriptions (continued) Field Description 0 1 4 ERSSUSP No request or request complete Request to: 1. run the Erase All Blocks command, 2. verify the erased state, 3. program the security byte in the Flash Configuration Field to the unsecure state, and 4. release MCU security by setting the FSEC[SEC] field to the unsecure state. Erase Suspend Allows the user to suspend (interrupt) the Erase Flash Sector command while it is executing. 0 1 No suspend requested Suspend the current Erase Flash Sector command execution. 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 29.3.3.3 Flash Security Register (FTFA_FSEC) This read-only register holds all bits associated with the security of the MCU and flash memory module. During the reset sequence, the register is loaded with the contents of the flash security byte in the Flash Configuration Field located in program flash memory. The flash basis for the values is signified by X in the reset value. Address: 4002_0000h base + 2h offset = 4002_0002h Bit 7 Read 6 5 KEYEN 4 3 MEEN 2 1 FSLACC 0 SEC Write Reset x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. FTFA_FSEC field descriptions Field 7-6 KEYEN Description Backdoor Key Security Enable Enables or disables backdoor key access to the flash memory module. Table continues on the next page... K22F Sub-Family Reference Manual, Rev. 4, 08/2016 NXP Semiconductors 593 Memory Map and Registers FTFA_FSEC field descriptions (continued) Field Description 00 01 10 11 5-4 MEEN Mass Erase Enable Enables and disables mass erase capability of the flash memory module at all times in all NVM modes. 00 01 10 11 3-2 FSLACC Backdoor key access disabled Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) Backdoor key access enabled Backdoor key access disabled Mass erase is enabled Mass erase is enabled Mass erase is disabled Mass erase is enabled Factory Security Level Access Code Enables or disables access to the flash memory contents during returned part failure analysis at NXP. When SEC is secure and FSLACC is denied, access to the program flash contents is denied and any failure analysis performed by NXP factory test must begin with a full erase to unsecure the part. When access is granted (SEC is unsecure, or SEC is secure and FSLACC is granted), NXP factory testing has visibility of the current flash contents. The state of the FSLACC bits is only relevant when SEC is set to secure. When SEC is set to unsecure, the FSLACC setting does not matter. 00 01 10 11 SEC NXP factory access granted NXP factory access denied NXP factory access denied NXP factory access granted Flash Security Defines the security state of the MCU. In the secure state, the MCU limits access to flash memory module resources. The limitations are defined per device and are detailed in the Chip Configuration details. If the flash memory module is unsecured using backdoor key access, SEC is forced to 10b. 00 01 10 11 MCU security status is secure. MCU security status is secure. MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.) MCU security status is secure. 29.3.3.4 Flash Option Register (FTFA_FOPT) The flash option register allows the MCU to customize its operations by examining the state of these read-only bits, which are loaded from NVM at reset. The function of the bits is defined in the device's Chip Configuration details. All bits in the register are read-only . K22F Sub-Family Reference Manual, Rev. 4, 08/2016 594 NXP Semiconductors Chapter 29 Flash Memory Module (FTFA) During the reset sequence, the register is loaded from the flash nonvolatile option byte in the Flash Configuration Field located in program flash memory. The flash basis for the values is signified by X in the reset value. However, the register is written to 0xFF if the contents of the flash nonvolatile option byte are 0x00. Address: 4002_0000h base + 3h offset = 4002_0003h Bit 7 6 5 4 Read 3 2 1 0 x* x* x* x* OPT Write Reset x* x* x* x* * Notes: * x = Undefined at reset. FTFA_FOPT field descriptions Field OPT Description Nonvolatile Option These bits are loaded from flash to this register at reset. Refer to the device's Chip Configuration details for the definition and use of these bits. 29.3.3.5 Flash Common Command Object Registers (FTFA_FCCOBn) The FCCOB register group provides 12 bytes for command codes and parameters. The individual bytes within the set append a 0-B hex identifier to the FCCOB register name: FCCOB0, FCCOB1, ..., FCCOBB. Address: 4002_0000h base + 4h offset + (1d x i), where i=0d to 11d Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 CCOBn 0 0 0 0 FTFA_FCCOBn field descriptions Field Description CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller. The individual registers that compose the FCCOB data set can be written in any order, but you must provide all needed values, which vary from command to command. First, set up all required FCCOB fields and then initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed by the user until the command completes (CCIF returns to 1). No command buffering or queueing is provided; the next command can be loaded only after the curre