K22F Sub-Family Reference Manual
Supports: MK22FN128VDC10, MK22FN128VLL10,
MK22FN128VMP10, MK22FN128VLH10, MK22FN128CAK10R
Document Number: K22P121M100SF9RM
Rev. 4, 08/2016
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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................45
1.1.1 Purpose.........................................................................................................................................................45
1.1.2 Audience...................................................................................................................................................... 45
1.2 Conventions.................................................................................................................................................................. 45
1.2.1 Numbering systems......................................................................................................................................45
1.2.2 Typographic notation................................................................................................................................... 46
1.2.3 Special terms................................................................................................................................................46
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................47
2.2 Module Functional Categories......................................................................................................................................47
2.2.1 ARM® Cortex®-M4 Core Modules............................................................................................................48
2.2.2 System Modules...........................................................................................................................................49
2.2.3 Memories and Memory Interfaces............................................................................................................... 50
2.2.4 Clocks...........................................................................................................................................................50
2.2.5 Security and Integrity modules.................................................................................................................... 50
2.2.6 Analog modules........................................................................................................................................... 51
2.2.7 Timer modules............................................................................................................................................. 51
2.2.8 Communication interfaces........................................................................................................................... 52
2.2.9 Human-machine interfaces.......................................................................................................................... 53
2.3 Orderable part numbers.................................................................................................................................................53
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................55
3.2 Core modules................................................................................................................................................................ 55
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................55
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3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................57
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................63
3.2.4 FPU Configuration.......................................................................................................................................64
3.2.5 JTAG Controller Configuration...................................................................................................................64
3.3 System modules............................................................................................................................................................ 65
3.3.1 SIM Configuration....................................................................................................................................... 65
3.3.2 System Mode Controller (SMC) Configuration...........................................................................................66
3.3.3 PMC Configuration......................................................................................................................................66
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................67
3.3.5 MCM Configuration.................................................................................................................................... 69
3.3.6 Crossbar-Light Switch Configuration..........................................................................................................69
3.3.7 Peripheral Bridge Configuration..................................................................................................................71
3.3.8 DMA request multiplexer configuration......................................................................................................72
3.3.9 DMA Controller Configuration................................................................................................................... 75
3.3.10 External Watchdog Monitor (EWM) Configuration....................................................................................76
3.3.11 Watchdog Configuration..............................................................................................................................78
3.4 Clock modules.............................................................................................................................................................. 79
3.4.1 MCG Configuration..................................................................................................................................... 79
3.4.2 OSC Configuration...................................................................................................................................... 80
3.4.3 RTC OSC configuration...............................................................................................................................81
3.5 Memories and memory interfaces.................................................................................................................................82
3.5.1 Flash Memory Configuration.......................................................................................................................82
3.5.2 Flash Memory Controller Configuration..................................................................................................... 85
3.5.3 SRAM Configuration...................................................................................................................................85
3.5.4 System Register File Configuration.............................................................................................................87
3.5.5 VBAT Register File Configuration..............................................................................................................88
3.5.6 EzPort Configuration................................................................................................................................... 88
3.6 Security......................................................................................................................................................................... 90
3.6.1 CRC Configuration...................................................................................................................................... 90
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3.7 Analog...........................................................................................................................................................................90
3.7.1 16-bit SAR ADC Configuration.................................................................................................................. 90
3.7.2 CMP Configuration......................................................................................................................................97
3.7.3 12-bit DAC Configuration........................................................................................................................... 99
3.7.4 VREF Configuration....................................................................................................................................101
3.8 Timers........................................................................................................................................................................... 102
3.8.1 PDB Configuration...................................................................................................................................... 102
3.8.2 FlexTimer Configuration............................................................................................................................. 105
3.8.3 PIT Configuration........................................................................................................................................ 111
3.8.4 Low-power timer configuration...................................................................................................................112
3.8.5 RTC configuration....................................................................................................................................... 114
3.9 Communication interfaces............................................................................................................................................ 115
3.9.1 Universal Serial Bus (USB) FS Subsystem................................................................................................. 115
3.9.2 SPI configuration......................................................................................................................................... 119
3.9.3 I2C Configuration........................................................................................................................................ 122
3.9.4 UART Configuration................................................................................................................................... 123
3.9.5 LPUART configuration................................................................................................................................126
3.9.6 I2S configuration..........................................................................................................................................126
3.10 Human-machine interfaces........................................................................................................................................... 130
3.10.1 GPIO configuration......................................................................................................................................130
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................133
4.2 System memory map.....................................................................................................................................................133
4.2.1 Aliased bit-band regions.............................................................................................................................. 134
4.2.2 Flash Access Control Introduction...............................................................................................................136
4.3 Flash Memory Map.......................................................................................................................................................136
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................137
4.4 SRAM memory map.....................................................................................................................................................137
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4.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................138
4.5.1 Read-after-write sequence and required serialization of memory operations..............................................138
4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................ 138
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................142
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................145
5.2 Programming model......................................................................................................................................................145
5.3 High-Level device clocking diagram............................................................................................................................145
5.4 Clock definitions...........................................................................................................................................................146
5.4.1 Device clock summary.................................................................................................................................147
5.5 Internal clocking requirements..................................................................................................................................... 149
5.5.1 Clock divider values after reset....................................................................................................................150
5.5.2 VLPR mode clocking...................................................................................................................................151
5.6 Clock Gating.................................................................................................................................................................151
5.7 Module clocks...............................................................................................................................................................151
5.7.1 PMC 1-kHz LPO clock................................................................................................................................153
5.7.2 IRC 48MHz clock........................................................................................................................................ 153
5.7.3 WDOG clocking.......................................................................................................................................... 154
5.7.4 Debug trace clock.........................................................................................................................................155
5.7.5 PORT digital filter clocking.........................................................................................................................155
5.7.6 LPTMR clocking..........................................................................................................................................155
5.7.7 RTC_CLKOUT and CLKOUT32K clocking..............................................................................................156
5.7.8 USB FS OTG Controller clocking...............................................................................................................157
5.7.9 UART clocking............................................................................................................................................158
5.7.10 LPUART0 clocking..................................................................................................................................... 158
5.7.11 I2S/SAI clocking..........................................................................................................................................159
Chapter 6
Reset and Boot
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6.1 Introduction...................................................................................................................................................................161
6.2 Reset..............................................................................................................................................................................161
6.2.1 Power-on reset (POR).................................................................................................................................. 162
6.2.2 System reset sources.................................................................................................................................... 162
6.2.3 MCU Resets................................................................................................................................................. 166
6.2.4 Reset Pin ..................................................................................................................................................... 167
6.2.5 Debug resets.................................................................................................................................................167
6.3 Boot...............................................................................................................................................................................169
6.3.1 Boot sources.................................................................................................................................................169
6.3.2 Boot options................................................................................................................................................. 169
6.3.3 FOPT boot options.......................................................................................................................................169
6.3.4 Boot sequence.............................................................................................................................................. 170
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................173
7.2 Clocking modes............................................................................................................................................................ 173
7.2.1 Partial Stop...................................................................................................................................................173
7.2.2 DMA Wakeup..............................................................................................................................................174
7.2.3 Compute Operation......................................................................................................................................175
7.2.4 Peripheral Doze............................................................................................................................................176
7.2.5 Clock Gating................................................................................................................................................ 177
7.3 Power Modes Description.............................................................................................................................................177
7.4 Entering and exiting power modes............................................................................................................................... 179
7.5 Power mode transitions.................................................................................................................................................180
7.6 Power modes shutdown sequencing............................................................................................................................. 181
7.7 Flash Program Restrictions...........................................................................................................................................182
7.8 Module Operation in Low Power Modes......................................................................................................................182
Chapter 8
Security
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8.1 Introduction...................................................................................................................................................................187
8.2 Flash Security............................................................................................................................................................... 187
8.3 Security Interactions with other Modules.....................................................................................................................188
8.3.1 Security Interactions with EzPort................................................................................................................ 188
8.3.2 Security Interactions with Debug.................................................................................................................188
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................189
9.1.1 References....................................................................................................................................................191
9.2 The Debug Port.............................................................................................................................................................191
9.2.1 JTAG-to-SWD change sequence................................................................................................................. 192
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................192
9.3 Debug Port Pin Descriptions.........................................................................................................................................193
9.4 System TAP connection................................................................................................................................................193
9.4.1 IR Codes.......................................................................................................................................................193
9.5 JTAG status and control registers.................................................................................................................................194
9.5.1 MDM-AP Control Register..........................................................................................................................195
9.5.2 MDM-AP Status Register............................................................................................................................ 197
9.6 Debug Resets................................................................................................................................................................ 198
9.7 AHB-AP........................................................................................................................................................................199
9.8 ITM............................................................................................................................................................................... 199
9.9 Core Trace Connectivity...............................................................................................................................................200
9.10 TPIU..............................................................................................................................................................................200
9.11 DWT............................................................................................................................................................................. 200
9.12 Debug in Low Power Modes........................................................................................................................................ 201
9.12.1 Debug Module State in Low Power Modes.................................................................................................201
9.13 Debug & Security......................................................................................................................................................... 202
Chapter 10
Signal Multiplexing and Signal Descriptions
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10.1 Introduction...................................................................................................................................................................203
10.2 Signal Multiplexing Integration....................................................................................................................................203
10.2.1 Port control and interrupt module features.................................................................................................. 204
10.2.2 Clock gating................................................................................................................................................. 205
10.2.3 Signal multiplexing constraints....................................................................................................................205
10.3 Pinout............................................................................................................................................................................205
10.3.1 K22 Signal Multiplexing and Pin Assignments...........................................................................................205
10.3.2 K22 Pinouts..................................................................................................................................................210
10.4 Module Signal Description Tables................................................................................................................................215
10.4.1 Core Modules...............................................................................................................................................215
10.4.2 System Modules...........................................................................................................................................216
10.4.3 Clock Modules............................................................................................................................................. 216
10.4.4 Memories and Memory Interfaces............................................................................................................... 217
10.4.5 Analog..........................................................................................................................................................217
10.4.6 Timer Modules.............................................................................................................................................218
10.4.7 Communication Interfaces........................................................................................................................... 220
10.4.8 Human-Machine Interfaces (HMI).............................................................................................................. 222
Chapter 11
Port Control and Interrupts (PORT)
11.1 Introduction...................................................................................................................................................................223
11.2 Overview.......................................................................................................................................................................223
11.2.1 Features........................................................................................................................................................ 223
11.2.2 Modes of operation...................................................................................................................................... 224
11.3 External signal description............................................................................................................................................225
11.4 Detailed signal description............................................................................................................................................225
11.5 Memory map and register definition.............................................................................................................................225
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................232
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................235
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................235
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11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................ 236
11.5.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................236
11.5.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................237
11.5.7 Digital Filter Width Register (PORTx_DFWR).......................................................................................... 237
11.6 Functional description...................................................................................................................................................238
11.6.1 Pin control....................................................................................................................................................238
11.6.2 Global pin control........................................................................................................................................ 239
11.6.3 External interrupts........................................................................................................................................239
11.6.4 Digital filter..................................................................................................................................................240
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................243
12.1.1 Features........................................................................................................................................................ 243
12.2 Memory map and register definition.............................................................................................................................244
12.2.1 System Options Register 1 (SIM_SOPT1).................................................................................................. 245
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................246
12.2.3 System Options Register 2 (SIM_SOPT2).................................................................................................. 247
12.2.4 System Options Register 4 (SIM_SOPT4).................................................................................................. 249
12.2.5 System Options Register 5 (SIM_SOPT5).................................................................................................. 251
12.2.6 System Options Register 7 (SIM_SOPT7).................................................................................................. 253
12.2.7 System Options Register 8 (SIM_SOPT8).................................................................................................. 255
12.2.8 System Device Identification Register (SIM_SDID)...................................................................................256
12.2.9 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................258
12.2.10 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................260
12.2.11 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................262
12.2.12 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................265
12.2.13 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................265
12.2.14 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................267
12.2.15 Flash Configuration Register 1 (SIM_FCFG1)........................................................................................... 268
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12.2.16 Flash Configuration Register 2 (SIM_FCFG2)........................................................................................... 270
12.2.17 Unique Identification Register High (SIM_UIDH)..................................................................................... 270
12.2.18 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................271
12.2.19 Unique Identification Register Mid Low (SIM_UIDML)........................................................................... 271
12.2.20 Unique Identification Register Low (SIM_UIDL)...................................................................................... 272
12.3 Functional description...................................................................................................................................................272
Chapter 13
Kinetis Flashloader
13.1 Chip-Specific Information............................................................................................................................................ 273
13.2 Introduction...................................................................................................................................................................273
13.3 Functional Description..................................................................................................................................................275
13.3.1 Memory Maps..............................................................................................................................................275
13.3.2 Start-up Process............................................................................................................................................275
13.3.3 Clock Configuration.....................................................................................................................................276
13.3.4 Flashloader Protocol.................................................................................................................................... 276
13.3.5 Flashloader Packet Types.............................................................................................................................281
13.3.6 Flashloader Command API..........................................................................................................................288
13.4 Peripherals Supported................................................................................................................................................... 307
13.4.1 I2C Peripheral.............................................................................................................................................. 307
13.4.2 SPI Peripheral.............................................................................................................................................. 309
13.4.3 UART Peripheral......................................................................................................................................... 311
13.4.4 USB peripheral.............................................................................................................................................314
13.5 Get/SetProperty Command Properties..........................................................................................................................316
13.5.1 Property Definitions.....................................................................................................................................317
13.6 Kinetis Flashloader Status Error Codes........................................................................................................................ 319
Chapter 14
Reset Control Module (RCM)
14.1 Introduction...................................................................................................................................................................321
14.2 Reset memory map and register descriptions............................................................................................................... 321
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14.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................ 322
14.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................ 323
14.2.3 Reset Pin Filter Control register (RCM_RPFC).......................................................................................... 325
14.2.4 Reset Pin Filter Width register (RCM_RPFW)........................................................................................... 326
14.2.5 Mode Register (RCM_MR)......................................................................................................................... 327
14.2.6 Sticky System Reset Status Register 0 (RCM_SSRS0)...............................................................................328
14.2.7 Sticky System Reset Status Register 1 (RCM_SSRS1)...............................................................................329
Chapter 15
System Mode Controller (SMC)
15.1 Introduction...................................................................................................................................................................331
15.2 Modes of operation....................................................................................................................................................... 331
15.3 Memory map and register descriptions.........................................................................................................................333
15.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................334
15.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................335
15.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................337
15.3.4 Power Mode Status register (SMC_PMSTAT)........................................................................................... 338
15.4 Functional description...................................................................................................................................................339
15.4.1 Power mode transitions................................................................................................................................339
15.4.2 Power mode entry/exit sequencing.............................................................................................................. 342
15.4.3 Run modes....................................................................................................................................................344
15.4.4 Wait modes.................................................................................................................................................. 346
15.4.5 Stop modes...................................................................................................................................................346
15.4.6 Debug in low power modes......................................................................................................................... 349
Chapter 16
Power Management Controller (PMC)
16.1 Introduction...................................................................................................................................................................351
16.2 Features.........................................................................................................................................................................351
16.3 Low-voltage detect (LVD) system................................................................................................................................351
16.3.1 LVD reset operation.....................................................................................................................................352
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16.3.2 LVD interrupt operation...............................................................................................................................352
16.3.3 Low-voltage warning (LVW) interrupt operation....................................................................................... 352
16.4 I/O retention..................................................................................................................................................................353
16.5 Memory map and register descriptions.........................................................................................................................353
16.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................ 354
16.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................ 355
16.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................356
Chapter 17
Low-Leakage Wakeup Unit (LLWU)
17.1 Introduction...................................................................................................................................................................359
17.1.1 Features........................................................................................................................................................ 359
17.1.2 Modes of operation...................................................................................................................................... 360
17.1.3 Block diagram..............................................................................................................................................361
17.2 LLWU signal descriptions............................................................................................................................................ 362
17.3 Memory map/register definition................................................................................................................................... 362
17.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................363
17.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................364
17.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................365
17.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................366
17.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................ 367
17.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................369
17.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................371
17.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................372
17.3.9 LLWU Pin Filter 1 register (LLWU_FILT1).............................................................................................. 374
17.3.10 LLWU Pin Filter 2 register (LLWU_FILT2).............................................................................................. 375
17.4 Functional description...................................................................................................................................................376
17.4.1 LLS mode.....................................................................................................................................................377
17.4.2 VLLS modes................................................................................................................................................ 377
17.4.3 Initialization................................................................................................................................................. 377
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Chapter 18
Miscellaneous Control Module (MCM)
18.1 Introduction...................................................................................................................................................................379
18.1.1 Features........................................................................................................................................................ 379
18.2 Memory map/register descriptions............................................................................................................................... 379
18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................380
18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................ 380
18.2.3 Crossbar Switch (AXBS) Control Register (MCM_PLACR)..................................................................... 381
18.2.4 Interrupt Status and Control Register (MCM_ISCR).................................................................................. 381
18.2.5 Compute Operation Control Register (MCM_CPO)................................................................................... 384
18.3 Functional description...................................................................................................................................................385
18.3.1 Interrupts...................................................................................................................................................... 385
Chapter 19
Crossbar Switch Lite (AXBS-Lite)
19.1 Introduction...................................................................................................................................................................387
19.1.1 Features........................................................................................................................................................ 387
19.2 Memory Map / Register Definition...............................................................................................................................388
19.3 Functional Description..................................................................................................................................................388
19.3.1 General operation.........................................................................................................................................388
19.3.2 Arbitration....................................................................................................................................................389
19.4 Initialization/application information........................................................................................................................... 390
Chapter 20
Peripheral Bridge (AIPS-Lite)
20.1 Introduction...................................................................................................................................................................391
20.1.1 Features........................................................................................................................................................ 391
20.1.2 General operation.........................................................................................................................................391
20.2 Memory map/register definition................................................................................................................................... 392
20.3 Functional description...................................................................................................................................................392
20.3.1 Access support............................................................................................................................................. 392
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Chapter 21
Direct Memory Access Multiplexer (DMAMUX)
21.1 Introduction...................................................................................................................................................................393
21.1.1 Overview......................................................................................................................................................393
21.1.2 Features........................................................................................................................................................ 394
21.1.3 Modes of operation...................................................................................................................................... 394
21.2 External signal description............................................................................................................................................395
21.3 Memory map/register definition................................................................................................................................... 395
21.3.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................ 395
21.4 Functional description...................................................................................................................................................396
21.4.1 DMA channels with periodic triggering capability......................................................................................397
21.4.2 DMA channels with no triggering capability...............................................................................................399
21.4.3 Always-enabled DMA sources.................................................................................................................... 399
21.5 Initialization/application information........................................................................................................................... 401
21.5.1 Reset.............................................................................................................................................................401
21.5.2 Enabling and configuring sources................................................................................................................401
Chapter 22
Enhanced Direct Memory Access (eDMA)
22.1 Introduction...................................................................................................................................................................405
22.1.1 eDMA system block diagram...................................................................................................................... 405
22.1.2 Block parts................................................................................................................................................... 406
22.1.3 Features........................................................................................................................................................ 407
22.2 Modes of operation....................................................................................................................................................... 408
22.3 Memory map/register definition................................................................................................................................... 409
22.3.1 TCD memory............................................................................................................................................... 409
22.3.2 TCD initialization........................................................................................................................................ 409
22.3.3 TCD structure...............................................................................................................................................409
22.3.4 Reserved memory and bit fields...................................................................................................................410
22.3.5 Control Register (DMA_CR).......................................................................................................................414
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22.3.6 Error Status Register (DMA_ES)................................................................................................................ 417
22.3.7 Enable Request Register (DMA_ERQ)....................................................................................................... 419
22.3.8 Enable Error Interrupt Register (DMA_EEI)...............................................................................................420
22.3.9 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................. 421
22.3.10 Set Enable Error Interrupt Register (DMA_SEEI)...................................................................................... 422
22.3.11 Clear Enable Request Register (DMA_CERQ)...........................................................................................423
22.3.12 Set Enable Request Register (DMA_SERQ)...............................................................................................424
22.3.13 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................425
22.3.14 Set START Bit Register (DMA_SSRT)...................................................................................................... 426
22.3.15 Clear Error Register (DMA_CERR)............................................................................................................427
22.3.16 Clear Interrupt Request Register (DMA_CINT)......................................................................................... 428
22.3.17 Interrupt Request Register (DMA_INT)......................................................................................................429
22.3.18 Error Register (DMA_ERR)........................................................................................................................ 430
22.3.19 Hardware Request Status Register (DMA_HRS)........................................................................................ 431
22.3.20 Enable Asynchronous Request in Stop Register (DMA_EARS).................................................................433
22.3.21 Channel n Priority Register (DMA_DCHPRIn).......................................................................................... 434
22.3.22 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................435
22.3.23 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................435
22.3.24 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................436
22.3.25 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................. 437
22.3.26 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................437
22.3.27 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES)..................................................................................................... 439
22.3.28 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................440
22.3.29 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................440
22.3.30 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................441
22.3.31 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................441
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22.3.32 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................ 443
22.3.33 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA).......... 444
22.3.34 TCD Control and Status (DMA_TCDn_CSR)............................................................................................ 444
22.3.35 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................447
22.3.36 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................ 448
22.4 Functional description...................................................................................................................................................449
22.4.1 eDMA basic data flow................................................................................................................................. 449
22.4.2 Fault reporting and handling........................................................................................................................452
22.4.3 Channel preemption..................................................................................................................................... 454
22.4.4 Performance................................................................................................................................................. 454
22.5 Initialization/application information........................................................................................................................... 459
22.5.1 eDMA initialization..................................................................................................................................... 459
22.5.2 Programming errors..................................................................................................................................... 461
22.5.3 Arbitration mode considerations..................................................................................................................461
22.5.4 Performing DMA transfers.......................................................................................................................... 462
22.5.5 Monitoring transfer descriptor status........................................................................................................... 466
22.5.6 Channel Linking...........................................................................................................................................468
22.5.7 Dynamic programming................................................................................................................................ 469
22.5.8 Lockstep.......................................................................................................................................................472
Chapter 23
External Watchdog Monitor (EWM)
23.1 Introduction...................................................................................................................................................................475
23.1.1 Features........................................................................................................................................................ 475
23.1.2 Modes of Operation..................................................................................................................................... 476
23.1.3 Block Diagram............................................................................................................................................. 477
23.2 EWM Signal Descriptions............................................................................................................................................ 478
23.3 Memory Map/Register Definition.................................................................................................................................478
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23.3.1 Control Register (EWM_CTRL)................................................................................................................. 478
23.3.2 Service Register (EWM_SERV)..................................................................................................................479
23.3.3 Compare Low Register (EWM_CMPL)......................................................................................................479
23.3.4 Compare High Register (EWM_CMPH).....................................................................................................480
23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................481
23.4 Functional Description..................................................................................................................................................481
23.4.1 The EWM_out Signal.................................................................................................................................. 481
23.4.2 The EWM_in Signal.................................................................................................................................... 482
23.4.3 EWM Counter..............................................................................................................................................483
23.4.4 EWM Compare Registers............................................................................................................................ 483
23.4.5 EWM Refresh Mechanism...........................................................................................................................483
23.4.6 EWM Interrupt.............................................................................................................................................484
23.4.7 Counter clock prescaler................................................................................................................................484
Chapter 24
Watchdog Timer (WDOG)
24.1 Introduction...................................................................................................................................................................485
24.2 Features.........................................................................................................................................................................485
24.3 Functional overview......................................................................................................................................................486
24.3.1 Unlocking and updating the watchdog.........................................................................................................488
24.3.2 Watchdog configuration time (WCT)..........................................................................................................489
24.3.3 Refreshing the watchdog..............................................................................................................................490
24.3.4 Windowed mode of operation......................................................................................................................490
24.3.5 Watchdog disabled mode of operation.........................................................................................................490
24.3.6 Debug modes of operation........................................................................................................................... 490
24.4 Testing the watchdog.................................................................................................................................................... 491
24.4.1 Quick test..................................................................................................................................................... 492
24.4.2 Byte test........................................................................................................................................................492
24.5 Backup reset generator..................................................................................................................................................493
24.6 Generated resets and interrupts.....................................................................................................................................494
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24.7 Memory map and register definition.............................................................................................................................494
24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)........................................................... 495
24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................ 497
24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................497
24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................498
24.7.5 Watchdog Window Register High (WDOG_WINH).................................................................................. 498
24.7.6 Watchdog Window Register Low (WDOG_WINL)................................................................................... 499
24.7.7 Watchdog Refresh register (WDOG_REFRESH)....................................................................................... 499
24.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................499
24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH)................................................................. 500
24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL).................................................................. 500
24.7.11 Watchdog Reset Count register (WDOG_RSTCNT).................................................................................. 501
24.7.12 Watchdog Prescaler register (WDOG_PRESC).......................................................................................... 501
24.8 Watchdog operation with 8-bit access.......................................................................................................................... 501
24.8.1 General guideline......................................................................................................................................... 501
24.8.2 Refresh and unlock operations with 8-bit access.........................................................................................502
24.9 Restrictions on watchdog operation..............................................................................................................................503
Chapter 25
Multipurpose Clock Generator (MCG)
25.1 Introduction...................................................................................................................................................................505
25.1.1 Features........................................................................................................................................................ 505
25.1.2 Modes of Operation..................................................................................................................................... 507
25.2 External Signal Description.......................................................................................................................................... 508
25.3 Memory Map/Register Definition.................................................................................................................................508
25.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................509
25.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................510
25.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................511
25.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................512
25.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................513
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25.3.5 MCG Control 6 Register (MCG_C6)...........................................................................................................513
25.3.6 MCG Status Register (MCG_S).................................................................................................................. 514
25.3.7 MCG Status and Control Register (MCG_SC)............................................................................................515
25.3.8 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................ 516
25.3.9 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................517
25.3.10 MCG Control 7 Register (MCG_C7)...........................................................................................................517
25.3.11 MCG Control 8 Register (MCG_C8)...........................................................................................................518
25.3.12 MCG Control 12 Register (MCG_C12).......................................................................................................519
25.3.12 MCG Status 2 Register (MCG_S2)............................................................................................................. 519
25.3.12 MCG Test 3 Register (MCG_T3)................................................................................................................ 519
25.4 Functional description...................................................................................................................................................520
25.4.1 MCG mode state diagram............................................................................................................................ 520
25.4.2 Low-power bit usage....................................................................................................................................523
25.4.3 MCG Internal Reference Clocks..................................................................................................................523
25.4.4 External Reference Clock............................................................................................................................ 523
25.4.5 MCG Fixed Frequency Clock .....................................................................................................................524
25.4.6 MCG Auto TRIM (ATM)............................................................................................................................524
25.5 Initialization / Application information........................................................................................................................ 526
25.5.1 MCG module initialization sequence...........................................................................................................526
25.5.2 Using a 32.768 kHz reference......................................................................................................................528
25.5.3 MCG mode switching.................................................................................................................................. 529
Chapter 26
Oscillator (OSC)
26.1 Introduction...................................................................................................................................................................537
26.2 Features and Modes...................................................................................................................................................... 537
26.3 Block Diagram..............................................................................................................................................................538
26.4 OSC Signal Descriptions.............................................................................................................................................. 538
26.5 External Crystal / Resonator Connections.................................................................................................................... 539
26.6 External Clock Connections......................................................................................................................................... 540
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26.7 Memory Map/Register Definitions...............................................................................................................................541
26.7.1 OSC Memory Map/Register Definition.......................................................................................................541
26.8 Functional Description..................................................................................................................................................543
26.8.1 OSC module states.......................................................................................................................................543
26.8.2 OSC module modes..................................................................................................................................... 545
26.8.3 Counter.........................................................................................................................................................547
26.8.4 Reference clock pin requirements................................................................................................................547
26.9 Reset..............................................................................................................................................................................547
26.10 Low power modes operation.........................................................................................................................................548
26.11 Interrupts.......................................................................................................................................................................548
Chapter 27
RTC Oscillator (OSC32K)
27.1 Introduction...................................................................................................................................................................549
27.1.1 Features and Modes..................................................................................................................................... 549
27.1.2 Block Diagram............................................................................................................................................. 549
27.2 RTC Signal Descriptions.............................................................................................................................................. 550
27.2.1 EXTAL32 — Oscillator Input..................................................................................................................... 550
27.2.2 XTAL32 — Oscillator Output..................................................................................................................... 550
27.3 External Crystal Connections....................................................................................................................................... 551
27.4 Memory Map/Register Descriptions.............................................................................................................................551
27.5 Functional Description..................................................................................................................................................551
27.6 Reset Overview.............................................................................................................................................................552
27.7 Interrupts.......................................................................................................................................................................552
Chapter 28
Flash Memory Controller (FMC)
28.1 Introduction...................................................................................................................................................................553
28.1.1 Overview......................................................................................................................................................553
28.1.2 Features........................................................................................................................................................ 553
28.2 Modes of operation....................................................................................................................................................... 554
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28.3 External signal description............................................................................................................................................554
28.4 Memory map and register descriptions.........................................................................................................................554
28.4.1 Flash Access Protection Register (FMC_PFAPR).......................................................................................558
28.4.2 Flash Bank 0 Control Register (FMC_PFB0CR)........................................................................................ 560
28.4.3 Reserved (FMC_Reserved)..........................................................................................................................562
28.4.4 Cache Tag Storage (FMC_TAGVDW0Sn)................................................................................................. 563
28.4.5 Cache Tag Storage (FMC_TAGVDW1Sn)................................................................................................. 564
28.4.6 Cache Tag Storage (FMC_TAGVDW2Sn)................................................................................................. 565
28.4.7 Cache Tag Storage (FMC_TAGVDW3Sn)................................................................................................. 566
28.4.8 Cache Data Storage (upper word) (FMC_DATAW0SnU)..........................................................................566
28.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL).......................................................................... 567
28.4.10 Cache Data Storage (upper word) (FMC_DATAW1SnU)..........................................................................567
28.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL).......................................................................... 568
28.4.12 Cache Data Storage (upper word) (FMC_DATAW2SnU)..........................................................................568
28.4.13 Cache Data Storage (lower word) (FMC_DATAW2SnL).......................................................................... 569
28.4.14 Cache Data Storage (upper word) (FMC_DATAW3SnU)..........................................................................569
28.4.15 Cache Data Storage (lower word) (FMC_DATAW3SnL).......................................................................... 570
28.5 Functional description...................................................................................................................................................570
28.5.1 Default configuration................................................................................................................................... 570
28.5.2 Configuration options.................................................................................................................................. 571
28.5.3 Speculative reads..........................................................................................................................................571
28.5.4 Flash Access Control (FAC) Function.........................................................................................................572
28.6 Initialization and application information.....................................................................................................................582
Chapter 29
Flash Memory Module (FTFA)
29.1 Introduction...................................................................................................................................................................583
29.1.1 Features........................................................................................................................................................ 584
29.1.2 Block Diagram............................................................................................................................................. 584
29.1.3 Glossary....................................................................................................................................................... 585
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29.2 External Signal Description.......................................................................................................................................... 586
29.3 Memory Map and Registers..........................................................................................................................................586
29.3.1 Flash Configuration Field Description.........................................................................................................587
29.3.2 Program Flash IFR Map...............................................................................................................................587
29.3.3 Register Descriptions................................................................................................................................... 588
29.4 Functional Description..................................................................................................................................................602
29.4.1 Flash Protection............................................................................................................................................602
29.4.2 Flash Access Protection............................................................................................................................... 602
29.4.3 Interrupts...................................................................................................................................................... 604
29.4.4 Flash Operation in Low-Power Modes........................................................................................................ 605
29.4.5 Functional Modes of Operation................................................................................................................... 605
29.4.6 Flash Reads and Ignored Writes.................................................................................................................. 605
29.4.7 Read While Write (RWW)...........................................................................................................................606
29.4.8 Flash Program and Erase..............................................................................................................................606
29.4.9 Flash Command Operations.........................................................................................................................606
29.4.10 Margin Read Commands............................................................................................................................. 611
29.4.11 Flash Command Description........................................................................................................................612
29.4.12 Security........................................................................................................................................................ 628
29.4.13 Reset Sequence............................................................................................................................................ 630
Chapter 30
EzPort
30.1 Overview.......................................................................................................................................................................633
30.1.1 Block diagram..............................................................................................................................................633
30.1.2 Features........................................................................................................................................................ 634
30.1.3 Modes of operation...................................................................................................................................... 634
30.2 External signal descriptions.......................................................................................................................................... 635
30.2.1 EzPort Clock (EZP_CK)..............................................................................................................................635
30.2.2 EzPort Chip Select (EZP_CS)......................................................................................................................636
30.2.3 EzPort Serial Data In (EZP_D)....................................................................................................................636
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30.2.4 EzPort Serial Data Out (EZP_Q)................................................................................................................. 636
30.3 Command definition..................................................................................................................................................... 636
30.3.1 Command descriptions.................................................................................................................................637
30.4 Flash memory map for EzPort access...........................................................................................................................644
Chapter 31
Cyclic Redundancy Check (CRC)
31.1 Introduction...................................................................................................................................................................645
31.1.1 Features........................................................................................................................................................ 645
31.1.2 Block diagram..............................................................................................................................................645
31.1.3 Modes of operation...................................................................................................................................... 646
31.2 Memory map and register descriptions.........................................................................................................................646
31.2.1 CRC Data register (CRC_DATA)............................................................................................................... 647
31.2.2 CRC Polynomial register (CRC_GPOLY).................................................................................................. 648
31.2.3 CRC Control register (CRC_CTRL)............................................................................................................648
31.3 Functional description...................................................................................................................................................649
31.3.1 CRC initialization/reinitialization................................................................................................................649
31.3.2 CRC calculations..........................................................................................................................................650
31.3.3 Transpose feature......................................................................................................................................... 651
31.3.4 CRC result complement...............................................................................................................................653
Chapter 32
Analog-to-Digital Converter (ADC)
32.1 Introduction...................................................................................................................................................................655
32.1.1 Features........................................................................................................................................................ 655
32.1.2 Block diagram..............................................................................................................................................656
32.2 ADC signal descriptions............................................................................................................................................... 658
32.2.1 Analog Power (VDDA)............................................................................................................................... 659
32.2.2 Analog Ground (VSSA)...............................................................................................................................659
32.2.3 Voltage Reference Select.............................................................................................................................659
32.2.4 Analog Channel Inputs (ADx)..................................................................................................................... 660
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32.2.5 Differential Analog Channel Inputs (DADx)...............................................................................................660
32.3 Memory map and register definitions...........................................................................................................................660
32.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................662
32.3.2 ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................666
32.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................667
32.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................668
32.3.5 Compare Value Registers (ADCx_CVn)..................................................................................................... 670
32.3.6 Status and Control Register 2 (ADCx_SC2)................................................................................................671
32.3.7 Status and Control Register 3 (ADCx_SC3)................................................................................................673
32.3.8 ADC Offset Correction Register (ADCx_OFS)...........................................................................................674
32.3.9 ADC Plus-Side Gain Register (ADCx_PG).................................................................................................675
32.3.10 ADC Minus-Side Gain Register (ADCx_MG)............................................................................................ 675
32.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD)......................................................... 676
32.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)..........................................................677
32.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4).......................................................... 677
32.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3).......................................................... 678
32.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP2).......................................................... 678
32.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1).......................................................... 679
32.3.17 ADC Plus-Side General Calibration Value Register (ADCx_CLP0).......................................................... 679
32.3.18 ADC Minus-Side General Calibration Value Register (ADCx_CLMD).....................................................680
32.3.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMS)..................................................... 680
32.3.20 ADC Minus-Side General Calibration Value Register (ADCx_CLM4)..................................................... 681
32.3.21 ADC Minus-Side General Calibration Value Register (ADCx_CLM3)..................................................... 681
32.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM2)..................................................... 682
32.3.23 ADC Minus-Side General Calibration Value Register (ADCx_CLM1)..................................................... 682
32.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM0)..................................................... 683
32.4 Functional description...................................................................................................................................................683
32.4.1 Clock select and divide control....................................................................................................................684
32.4.2 Voltage reference selection..........................................................................................................................685
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32.4.3 Hardware trigger and channel selects.......................................................................................................... 685
32.4.4 Conversion control.......................................................................................................................................686
32.4.5 Automatic compare function........................................................................................................................694
32.4.6 Calibration function..................................................................................................................................... 695
32.4.7 User-defined offset function........................................................................................................................ 697
32.4.8 Temperature sensor......................................................................................................................................698
32.4.9 MCU wait mode operation...........................................................................................................................699
32.4.10 MCU Normal Stop mode operation.............................................................................................................699
32.4.11 MCU Low-Power Stop mode operation...................................................................................................... 700
32.5 Initialization information.............................................................................................................................................. 701
32.5.1 ADC module initialization example............................................................................................................ 701
32.6 Application information................................................................................................................................................703
32.6.1 External pins and routing............................................................................................................................. 703
32.6.2 Sources of error............................................................................................................................................705
Chapter 33
Comparator (CMP)
33.1 Introduction...................................................................................................................................................................711
33.1.1 CMP features................................................................................................................................................711
33.1.2 6-bit DAC key features................................................................................................................................ 712
33.1.3 ANMUX key features.................................................................................................................................. 712
33.1.4 CMP, DAC and ANMUX diagram..............................................................................................................713
33.1.5 CMP block diagram..................................................................................................................................... 714
33.2 Memory map/register definitions..................................................................................................................................716
33.2.1 CMP Control Register 0 (CMPx_CR0)....................................................................................................... 716
33.2.2 CMP Control Register 1 (CMPx_CR1)....................................................................................................... 717
33.2.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................719
33.2.4 CMP Status and Control Register (CMPx_SCR).........................................................................................719
33.2.5 DAC Control Register (CMPx_DACCR)....................................................................................................720
33.2.6 MUX Control Register (CMPx_MUXCR).................................................................................................. 721
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33.3 Functional description...................................................................................................................................................722
33.3.1 CMP functional modes.................................................................................................................................722
33.3.2 Power modes................................................................................................................................................731
33.3.3 Startup and operation................................................................................................................................... 732
33.3.4 Low-pass filter............................................................................................................................................. 733
33.4 CMP interrupts..............................................................................................................................................................735
33.5 DMA support................................................................................................................................................................ 735
33.6 CMP Asynchronous DMA support...............................................................................................................................736
33.7 Digital-to-analog converter...........................................................................................................................................737
33.8 DAC functional description.......................................................................................................................................... 737
33.8.1 Voltage reference source select....................................................................................................................737
33.9 DAC resets....................................................................................................................................................................738
33.10 DAC clocks...................................................................................................................................................................738
33.11 DAC interrupts..............................................................................................................................................................738
Chapter 34
12-bit Digital-to-Analog Converter (DAC)
34.1 Introduction...................................................................................................................................................................739
34.2 Features.........................................................................................................................................................................739
34.3 Block diagram...............................................................................................................................................................739
34.4 Memory map/register definition................................................................................................................................... 740
34.4.1 DAC Data Low Register (DACx_DATnL)................................................................................................. 742
34.4.2 DAC Data High Register (DACx_DATnH)................................................................................................ 742
34.4.3 DAC Status Register (DACx_SR)............................................................................................................... 743
34.4.4 DAC Control Register (DACx_C0)............................................................................................................. 744
34.4.5 DAC Control Register 1 (DACx_C1).......................................................................................................... 745
34.4.6 DAC Control Register 2 (DACx_C2).......................................................................................................... 746
34.5 Functional description...................................................................................................................................................746
34.5.1 DAC data buffer operation...........................................................................................................................746
34.5.2 DMA operation............................................................................................................................................ 748
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34.5.3 Resets........................................................................................................................................................... 748
34.5.4 Low-Power mode operation.........................................................................................................................748
Chapter 35
Voltage Reference (VREFV1)
35.1 Introduction...................................................................................................................................................................751
35.1.1 Overview......................................................................................................................................................752
35.1.2 Features........................................................................................................................................................ 752
35.1.3 Modes of Operation..................................................................................................................................... 753
35.1.4 VREF Signal Descriptions...........................................................................................................................753
35.2 Memory Map and Register Definition..........................................................................................................................754
35.2.1 VREF Trim Register (VREF_TRM)............................................................................................................754
35.2.2 VREF Status and Control Register (VREF_SC)..........................................................................................755
35.3 Functional Description..................................................................................................................................................756
35.3.1 Voltage Reference Disabled, SC[VREFEN] = 0......................................................................................... 757
35.3.2 Voltage Reference Enabled, SC[VREFEN] = 1.......................................................................................... 757
35.3.3 Internal voltage regulator.............................................................................................................................758
35.4 Initialization/Application Information..........................................................................................................................759
Chapter 36
Programmable Delay Block (PDB)
36.1 Introduction...................................................................................................................................................................761
36.1.1 Features........................................................................................................................................................ 761
36.1.2 Implementation............................................................................................................................................ 762
36.1.3 Back-to-back acknowledgment connections................................................................................................763
36.1.4 DAC External Trigger Input Connections................................................................................................... 763
36.1.5 Block diagram..............................................................................................................................................763
36.1.6 Modes of operation...................................................................................................................................... 765
36.2 PDB signal descriptions................................................................................................................................................765
36.3 Memory map and register definition.............................................................................................................................765
36.3.1 Status and Control register (PDBx_SC).......................................................................................................767
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36.3.2 Modulus register (PDBx_MOD)..................................................................................................................770
36.3.3 Counter register (PDBx_CNT).....................................................................................................................770
36.3.4 Interrupt Delay register (PDBx_IDLY)....................................................................................................... 771
36.3.5 Channel n Control register 1 (PDBx_CHnC1).............................................................................................771
36.3.6 Channel n Status register (PDBx_CHnS).....................................................................................................772
36.3.7 Channel n Delay 0 register (PDBx_CHnDLY0)..........................................................................................773
36.3.8 Channel n Delay 1 register (PDBx_CHnDLY1)..........................................................................................774
36.3.9 DAC Interval Trigger n Control register (PDBx_DACINTCn)...................................................................774
36.3.10 DAC Interval n register (PDBx_DACINTn)............................................................................................... 775
36.3.11 Pulse-Out n Enable register (PDBx_POEN)................................................................................................776
36.3.12 Pulse-Out n Delay register (PDBx_POnDLY).............................................................................................776
36.4 Functional description...................................................................................................................................................777
36.4.1 PDB pre-trigger and trigger outputs.............................................................................................................777
36.4.2 PDB trigger input source selection.............................................................................................................. 779
36.4.3 Pulse-Out's................................................................................................................................................... 779
36.4.4 Updating the delay registers.........................................................................................................................780
36.4.5 Interrupts...................................................................................................................................................... 782
36.4.6 DMA............................................................................................................................................................ 782
36.5 Application information................................................................................................................................................782
36.5.1 Impact of using the prescaler and multiplication factor on timing resolution............................................. 782
Chapter 37
FlexTimer Module (FTM)
37.1 Introduction...................................................................................................................................................................785
37.1.1 FlexTimer philosophy..................................................................................................................................785
37.1.2 Features........................................................................................................................................................ 786
37.1.3 Modes of operation...................................................................................................................................... 787
37.1.4 Block diagram..............................................................................................................................................788
37.2 FTM signal descriptions............................................................................................................................................... 790
37.3 Memory map and register definition.............................................................................................................................790
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37.3.1 Memory map................................................................................................................................................790
37.3.2 Register descriptions....................................................................................................................................791
37.3.3 Status And Control (FTMx_SC).................................................................................................................. 796
37.3.4 Counter (FTMx_CNT)................................................................................................................................. 797
37.3.5 Modulo (FTMx_MOD)................................................................................................................................798
37.3.6 Channel (n) Status And Control (FTMx_CnSC)..........................................................................................799
37.3.7 Channel (n) Value (FTMx_CnV).................................................................................................................802
37.3.8 Counter Initial Value (FTMx_CNTIN)........................................................................................................802
37.3.9 Capture And Compare Status (FTMx_STATUS)........................................................................................803
37.3.10 Features Mode Selection (FTMx_MODE).................................................................................................. 805
37.3.11 Synchronization (FTMx_SYNC)................................................................................................................. 807
37.3.12 Initial State For Channels Output (FTMx_OUTINIT).................................................................................809
37.3.13 Output Mask (FTMx_OUTMASK)............................................................................................................. 810
37.3.14 Function For Linked Channels (FTMx_COMBINE)...................................................................................812
37.3.15 Deadtime Insertion Control (FTMx_DEADTIME)..................................................................................... 817
37.3.16 FTM External Trigger (FTMx_EXTTRIG)................................................................................................. 818
37.3.17 Channels Polarity (FTMx_POL)..................................................................................................................820
37.3.18 Fault Mode Status (FTMx_FMS).................................................................................................................822
37.3.19 Input Capture Filter Control (FTMx_FILTER)........................................................................................... 824
37.3.20 Fault Control (FTMx_FLTCTRL)............................................................................................................... 825
37.3.21 Quadrature Decoder Control And Status (FTMx_QDCTRL)......................................................................828
37.3.22 Configuration (FTMx_CONF).....................................................................................................................830
37.3.23 FTM Fault Input Polarity (FTMx_FLTPOL)...............................................................................................831
37.3.24 Synchronization Configuration (FTMx_SYNCONF)..................................................................................832
37.3.25 FTM Inverting Control (FTMx_INVCTRL)................................................................................................834
37.3.26 FTM Software Output Control (FTMx_SWOCTRL)..................................................................................835
37.3.27 FTM PWM Load (FTMx_PWMLOAD)..................................................................................................... 838
37.4 Functional description...................................................................................................................................................839
37.4.1 Clock source.................................................................................................................................................840
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