ADC1175
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ADC1175 8-Bit, 20MHz, 60mW A/D Converter
Check for Samples: ADC1175
1FEATURES DESCRIPTION
The ADC1175 is a low power, 20 Msps analog-to-
2• Internal Sample-and-Hold Function digital converter that digitizes signals to 8 bits while
• Single +5V Operation consuming just 60 mW of power (typ). The ADC1175
• Internal Reference Bias Resistors uses a unique architecture that achieves 7.5 Effective
Bits. Output formatting is straight binary coding.
• Industry Standard Pinout
• TRI-STATE Outputs The excellent DC and AC characteristics of this
device, together with its low power consumption and
+5V single supply operation, make it ideally suited for
APPLICATIONS many video, imaging and communications
• Video Digitization applications, including use in portable equipment.
• Digital Still Cameras Furthermore, the ADC1175 is resistant to latch-up
and the outputs are short-circuit proof. The top and
• Personal Computer Video Cameras bottom of the ADC1175's reference ladder is
• CCD Imaging available for connections, enabling a wide range of
• Electro-Optics input possibilities.
The ADC1175 is offered in a TSSOP. It is designed
KEY SPECIFICATIONS to operate over the commercial temperature range of
• Resolution 8Bits -20°C to +75°C.
• Maximum Sampling Frequency 20Msps (min)
• DNL 0.75 LSB (max)
• ENOB 7.5 Bits (typ)
• Ensured No Missing Codes
• Power Consumption (excluding IREF) 60mW
(typ)
PIN CONFIGURATION
ADC1175 Pin Configuration
TSSOP Package
See Package Number PW
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADC1175
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BLOCK DIAGRAM
Figure 1.
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Pin Symbol Equivalent Circuit Description
No.
19 VIN Analog signal input. Conversion range is VRB to VRT.
Reference Top Bias with internal pull-up resistor. Short this
16 VRTS pin to VRT to self bias the reference ladder.
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DVDD
DVSS
1
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PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)
Pin Symbol Equivalent Circuit Description
No.
Analog Input that is the high (top) side of the reference ladder
of the ADC. Nominal range is 1.0V to AVDD. Voltage on VRT
17 VRT and VRB inputs define the VIN conversion range. Bypass well.
See REFERENCE INPUTS for more information.
Analog Input that is the low (bottom) side of the reference
ladder of the ADC. Nominal range is 0V to 4.0V. Voltage on
23 VRB VRT and VRB inputs define the VIN conversion range. Bypass
well. See REFERENCE INPUTS for more information.
Reference Bottom Bias with internal pull down resistor. Short
22 VRBS to VRB to self bias the reference ladder.
CMOS/TTL compatible Digital input that, when low, enables
1 OE the digital outputs of the ADC1175. When high, the outputs
are in a high impedance state.
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DVDD
DVSS
12
DVDD
DVSS
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PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)
Pin Symbol Equivalent Circuit Description
No.
CMOS/TTL compatible digital clock Input. VIN is sampled on
12 CLK the falling edge of CLK input.
Conversion data digital Output pins. D0 is the LSB, D7 is the
3 thru D0-D7 MSB. Valid data is output just after the rising edge of the CLK
10 input. These pins are enabled by bringing the OE pin low.
Positive digital supply pin. Connect to a clean voltage source
of +5V. AVDD and DVDD should have a common source and
13 DVDD be separately bypassed with a 10µF capacitor and a 0.1µF
ceramic chip capacitor. See POWER SUPPLY
CONSIDERATIONS for more information.
This digital supply pin supplies power for the digital output
11 DVDD drivers. This pin should be connected to a supply source in
the range of 2.5V to the Pin 13 potential.
The ground return for the digital supply. AVSS and DVSS
2, 24 DVSS should be connected together close to the ADC1175.
Positive analog supply pin. Connected to a quiet voltage
source of +5V. AVDD and DVDD should have a common
14, 15, AVDD source and be separately bypassed with a 10 µF capacitor
18 and a 0.1 µF ceramic chip capacitor. See POWER SUPPLY
CONSIDERATIONS for more information.
The ground return for the analog supply. AVSS and DVSS
20, 21 AVSS should be connected together close to the ADC1175
package.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)(3)
AVDD, DVDD 6.5V
Voltage on Any Pin −0.3V to 6.5V
VRT, VRB AVSS to AVDD
CLK, OE Voltage −0.5 to (AVDD + 0.5V)
Digital Output Voltage DVSS to DVDD
Input Current (4) ±25mA
Package Input Current (4) ±50mA
Package Dissipation at 25°C See (5)
ESD Susceptibility (6) Human Body Model 2000V
Machine Model 200V
Soldering Temp., Infrared, 10 sec. 300°C
Storage Temperature −65°C to +150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see
CONVERTER ELECTRICAL CHARACTERISTICS. The ensured specifications apply only for the test conditions listed. Some
performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = AVSS = DVSS = 0V, unless otherwise specified.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(4) When the input voltage at any pin exceeds the power supplies (that is, less than AVSS or DVSS, or greater than AVDD or DVDD), the
current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can
safely exceed the power supplies with an input current of 25 mA to two.
(5) The absolute maximum junction temperatures (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance θJA, and the ambient temperature, TA, and can be calculated using the formula
PDMAX = (TJmax - TA)/θJA. The values for maximum power dissipation listed above will be reached only when the ADC1175 is
operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply
polarity is reversed). Obviously, such conditions should always be avoided.
(6) Human body model is 100 pF capacitor discharged through a 1.5kΩresistor. Machine model is 220 pF discharged through ZERO Ω.
OPERATING RATINGS(1)(2)
Operating Temperature Range −20°C ≤TA≤+75°C
Supply voltage (AVDD, DVDD) +4.75V to +5.25V
AVDD −DVDD <0.5V
|AVSS - DVSS| 0V to 100 mV
Pin 13 - Pin 11 Voltage <0.5V
VRT 1.0V to VDD
VRB 0V to 4.0V
VRT - VRB 1V to 2.8V
VIN Voltage Range VRB to VRT
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see
CONVERTER ELECTRICAL CHARACTERISTICS. The ensured specifications apply only for the test conditions listed. Some
performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = AVSS = DVSS = 0V, unless otherwise specified.
PACKAGE THERMAL RESISTANCE
Package θJA
TSSOP-24 92°C / W
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CONVERTER ELECTRICAL CHARACTERISTICS
The following specifications apply for AVDD = DVDD = +5.0VDC, OE = 0V, VRT = +2.6V, VRB = 0.6V, CL= 20 pF, fCLK = 20MHz
at 50% duty cycle. Boldface limits apply for TA= TMIN to TMAX;all other limits TA= 25°C (1)(2)
Symbol Parameter Conditions Typical(3) Limits(3) Units
DC Accuracy
INL Integral Non Linearity f CLK = 20 MHz ±0.5 ±1.3 LSB ( max)
INL Integral Non Linearity f CLK = 30 MHz ±1.0 LSB ( max)
DNL Differential Non Linearity f CLK = 20 MHz ±0.35 ±0.75 LSB ( max)
DNL Differential Non Linearity f CLK = 30 MHz ±1.0 LSB ( max)
Missing Codes 0(max)
EOT Top Offset −24 mV
EOB Bottom Offset +37 mV
Video Accuracy
fin = 4.43 MHz sine wave
DP Differential Phase Error 0.5 Degree
fCLK = 17.7 MHz
fin = 4.43 MHz sine wave
DG Differential Gain Error 0.4 %
fCLK = 17.7 MHz
Analog Input and Reference Characteristics
VRB V (min)
VIN Input Range 2.0 VRT V (max)
(CLK LOW) 4
CIN VIN Input Capacitance VIN = 1.5V + 0.7Vrms pF
(CLK HIGH) 11
RIN RIN Input Resistance >1 MΩ
BW Analog Input Bandwidth 120 MHz
RRT Top Reference Resistor 360 Ω
200 Ω(min)
RREF Reference Ladder Resistance VRT to VRB 300 400 Ω(max)
RRB Bottom Reference Resistor 90 Ω
4.8 mA (min)
VRT =VRTS, VRB =VRBS 79.3 mA (max)
IREF Reference Ladder Current 5.4 mA (min)
VRT =VRTS,VRB =AVSS 810.5 mA (max)
VRT connected to VRTS
VRT Reference Top Self Bias Voltage 2.6 V
VRB connected to VRBS
VRT connected to VRTS V (min)
Reference Bottom Self Bias 0.55
VRB 0.6
Voltage 0.65
VRB connected to VRBS V (max)
VRT connected to VRTS 1.89 V (min)
2
VRB connected to VRBS 2.15 V (max)
VRTS -Self Bias Voltage Delta
VRBS VRT connected to VRTS 2.3 V
VRB connected to AVSS 1.0 V (min)
VRT - VRB Reference Voltage Delta 2 2.8 V (max)
(1) The analog inputs are protected as shown below. Input voltage magnitudes up to 6.5V or to 500 mV below GND will not damage this
device. However, errors in the A/D conversion can occur if the input goes above VDD or below GND by more than 50 mV. As an
example, if AVDD is 4.75VDC, the full-scale input voltage must be ≤4.80VDC to ensure accurate conversions. See Figure 2.
(2) To ensure accuracy, it is required that AVDD and DVDD be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors.
(3) Typical figures are at TJ= 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing
Quality Level).
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CONVERTER ELECTRICAL CHARACTERISTICS (continued)
The following specifications apply for AVDD = DVDD = +5.0VDC, OE = 0V, VRT = +2.6V, VRB = 0.6V, CL= 20 pF, fCLK = 20MHz
at 50% duty cycle. Boldface limits apply for TA= TMIN to TMAX;all other limits TA= 25°C (1)(2)
Symbol Parameter Conditions Typical(3) Limits(3) Units
Power Supply Characteristics
IADD Analog Supply Current DVDD = AVDD =5.25V 9.5 mA
IDDD Digital Supply Current DVDD = AVDD =5.25V 2.5 mA
DVDD AVDD =5.25V, fCLK = 20 MHz 12 17 mA (max)
IAVDD +Total Operating Current DVDD AVDD =5.25V, fCLK = 30 MHz 13
IDVDD DVDD = AVDD =5.25V, CLK Low(4) 9.6 mA
DVDD = AVDD =5.25V, fCLK = 20 MHz 60 85 mW (max)
Power Consumption DVDD = AVDD =5.25V, fCLK = 30 MHz 65 mW
CLK, OE Digital Input Characteristics
VIH Logical High Input Voltage DVDD = AVDD = +5.25V 3.0 V (min)
VIL Logical Low Input Voltage DVDD = AVDD = +5.25V 1.0 V (max)
IIH Logical High Input Current VIH = DVDD = AVDD = +5.25V 5 µA
IIL Logic Low Input Current VIL = 0V, DVDD = AVDD = +5.25V −5 µA
CIN Logic Input Capacitance 5 pF
Digital Output Characteristics
IOH High Level Output Current DVDD = 4.75V, VOH = 2.4V −1.1 mA (max)
IOL Low Level Output Current DVDD = 4.75V, VOL = 0.4V 1.6 mA (min)
DVDD = 5.25V
IOZH,Tri-State Leakage Current OE = DVDD, VOL ±20 µA
IOZL = 0V or VOH = DVDD
AC Electrical Characteristics
fC1 Maximum Conversion Rate 30 20 MHz (min)
fC2 Minimum Conversion Rate 1 MHz
CLK rise to data rising 19.5 ns
tOD Output Delay CLK rise to data falling 16 ns
Pipeline Delay (Latency) 2.5 Clock Cycles
tDS Sampling (Aperture) Delay CLK low to acquisition of data 3 ns
tAJ Aperture Jitter 30 ps rms
tOH Output Hold Time CLK high to data invalid 10 ns
tEN OE Low to Data Valid Loaded as in Figure 18 11 ns
tDIS OE High to High Z State Loaded as in Figure 18 15 ns
fIN = 1.31 MHz, VIN = FS - 2 LSB 7.5
fIN = 4.43 MHz, VIN = FS - 2 LSB 7.3 7.0
ENOB Effective Number of Bits Bits (min)
fIN = 9.9 MHz, VIN = FS - 2 LSB 7.2
fIN = 4.43 MHz, fCLK = 30 MHz 6.5
fIN = 1.31 MHz, VIN = FS - 2 LSB 46.9
fIN = 4.43 MHz, VIN = FS - 2 LSB 45.7 43
SINAD Signal-to- Noise & Distortion dB (min)
fIN = 9.9 MHz, VIN = FS - 2 LSB 45.1
fIN = 4.43 MHz, fCLK = 30 MHz 40.9
fIN = 1.31 MHz, VIN = FS - 2 LSB 47.6
fIN = 4.43 MHz, VIN = FS - 2 LSB 46 44
SNR Signal-to- Noise Ratio dB (min)
fIN = 9.9 MHz, VIN = FS - 2 LSB 46.1
fIN = 4.43 MHz, fCLK = 30 MHz 42.1
(4) At least two clock cycles must be presented to the ADC1175 after power up. See THE ADC1175 CLOCK for details.
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CONVERTER ELECTRICAL CHARACTERISTICS (continued)
The following specifications apply for AVDD = DVDD = +5.0VDC, OE = 0V, VRT = +2.6V, VRB = 0.6V, CL= 20 pF, fCLK = 20MHz
at 50% duty cycle. Boldface limits apply for TA= TMIN to TMAX;all other limits TA= 25°C (1)(2)
Symbol Parameter Conditions Typical(3) Limits(3) Units
fIN = 1.31 MHz, VIN = FS - 2 LSB 56
fIN = 4.43 MHz, VIN = FS - 2 LSB 58
SFDR Spurious Free Dynamic Range dB
fIN = 9.9 MHz, VIN = FS - 2 LSB 53
fIN = 4.43 MHz, fCLK = 30 MHz 47
fIN = 1.31 MHz, VIN = FS - 2 LSB −55
fIN = 4.43 MHz, VIN = FS - 2 LSB −57
THD Total Harmonic Distortion dB
fIN = 9.9 MHz, VIN = FS - 2 LSB −52
fIN = 4.43 MHz, fCLK = 30 MHz −47
Figure 2.
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TYPICAL PERFORMANCE CHARACTERISTICS
INL vs. Temp at fCLK DNL vs. Temp at fCLK
Figure 3. Figure 4.
SNR vs. Temp at fCLK SNR vs. Temp at fCLK
Figure 5. Figure 6.
THD vs. Temp THD vs. Temp
Figure 7. Figure 8.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
SINAD/ENOB vs. Temp SINAD/ENOB vs. Temp
Figure 9. Figure 10.
SINAD and ENOB vs. Clock Duty Cycle SFDR vs. Temp and fIN
Figure 11. Figure 12.
SFDR vs. Temp and fIN Differential Gain vs. Temperature
Figure 13. Figure 14.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Differential Phase vs. Temperature Spectral Response at fCLK = 20 MSPS
Figure 15. Figure 16.
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SPECIFICATION DEFINITIONS
ANALOG INPUT BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input. The test is performed with fIN equal to 100 kHz
plus integer multiples of fCLK. The input frequency at which the output is −3 dB relative to the low frequency input
signal is the full power bandwidth.
APERTURE JITTER is the time uncertainty of the sampling point (tDS), or the range of variation in the sampling
delay.
BOTTOM OFFSET is the difference between the input voltage that just causes the output code to transition to
the first code and the negative reference voltage. Bottom offset is defined as EOB = VZT - VRB, where VZT is the
first code transition input voltage. Note that this is different from the normal Zero Scale Error.
DIFFERENTIAL GAIN ERROR is the percentage difference between the output amplitudes of a high frequency
reconstructed sine wave at two different d.c. levels.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DIFFERENTIAL PHASE ERROR is the difference in the output phase of a reconstructed small signal sine wave
at two different d.c. levels.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion Ratio, or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
zero scale (½LSB below the first code transition) through positive full scale (½LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code value.
The end point test method is used.
OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the
output pins.
OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data
is presented to the output stage. Data for any give sample is available the Pipeline Delay plus the Output Delay
after that sample is taken. New data is available at every clock cycle, but the data lags the conversion by the
pipeline delay.
SAMPLING (APERTURE) DELAY is that time required after the fall of the clock input for the sampling switch to
open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the "hold" mode tDS after
the clock goes low.
SIGNAL TO NOISE RATIO (SNR) is the ratio of the rms value of the input signal to the rms value of the other
spectral components below one-half the sampling frequency, not including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio of the rms value of the input signal to
the rms value of all of the other spectral components below half the clock frequency, including harmonics but
excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum
that is not present at the input.
TOP OFFSET is the difference between the positive reference voltage and the input voltage that just causes the
output code to transition to full scale and is defined as EOT = VFT −VRT. Where VFT is the full scale transition
input voltage. Note that this is different from the normal Full Scale Error.
TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first six harmonic components, to the
rms value of the input signal.
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FUNCTIONAL DESCRIPTION
The ADC1175 uses a new, unique architecture to achieve 7.2 effective bits at and maintains superior dynamic
performance up to ½ the clock frequency.
The analog signal at VIN that is within the voltage range set by VRT and VRB are digitized to eight bits at up to 30
MSPS. Input voltages below VRB will cause the output word to consist of all zeroes. Input voltages above VRT will
cause the output word to consist of all ones. VRT has a range of 1.0 Volt to the analog supply voltage, AVDD,
while VRB has a range of 0 to 4.0 Volts. VRT should always be between 1.0 Volt and 2.8 Volts more positive than
VRB.
If VRT and VRTS are connected together and VRB and VRBS are connected together, the nominal values of VRT and
VRB are 2.6V and 0.6V, respectively. If VRT and VRTS are connected together and VRB is grounded, the nominal
value of VRT is 2.3V.
Data is acquired at the falling edge of the clock and the digital equivalent of the data is available at the digital
outputs 2.5 clock cycles plus tOD later. The ADC1175 will convert as long as the clock signal is present at pin 12.
The Output Enable pin OE, when low, enables the output pins. The digital outputs are in the high impedance
state when the OE pin is high.
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APPLICATIONS INFORMATION
THE ANALOG INPUT
The analog input of the ADC1175 is a switch followed by an integrator. The input capacitance changes with the
clock level, appearing as 4 pF when the clock is low, and 11 pF when the clock is high. Since a dynamic
capacitance is more difficult to drive than a fixed capacitance, choose an amplifier that can drive this type of load.
The LMH6702, LMH6609, LM6152, LM6154, LM6181 and LM6182 have been found to be excellent devices for
driving the ADC1175. Do not drive the input beyond the supply rails. Figure 19 shows an example of an input
circuit using the LMH6702.
Driving the analog input with input signals up to 2.8 VP-P will result in normal behavior where signals above VRT
will result in a code of FFh and input voltages below VRB will result in an output code of zero. Input signals above
2.8 VP-P may result in odd behavior where the output code is not FFh when the input exceeds VRT.
REFERENCE INPUTS
The reference inputs VRT (Reference Top) and VRB (Reference Bottom) are the top and bottom of the reference
ladder. Input signals between these two voltages will be digitized to 8 bits. External voltages applied to the
reference input pins should be within the range specified in Operating Ratings (1.0V to AVDD for VRT and 0V to
(AVDD - 1.0V) for VRB). Any device used to drive the reference pins should be able to source sufficient current
into the VRT pin and sink sufficient current from the VRB pin.
The reference ladder can be self-biased by connecting VRT to VRTS and connecting VRB to VRBS to provide top
and bottom reference voltages of approximately 2.6V and 0.6V, respectively, with VCC = 5.0V. This connection is
shown in Figure 19. If VRT and VRTS are tied together, but VRB is tied to analog ground, a top reference voltage of
approximately 2.3V is generated. The top and bottom of the ladder should be bypassed with 10µF tantalum
capacitors located close to the reference pins.
The reference self-bias circuit of Figure 19 is very simple and performance is adequate for many applications.
Superior performance can generally be achieved by driving the reference pins with a low impedance source.
By forcing a little current into or out of the top and bottom of the ladder, as shown in Figure 20, the top and
bottom reference voltages can be trimmed and performance improved over the self-bias method of Figure 19.
The resistive divider at the amplifier inputs can be replaced with potentiometers. The LMC662 amplifier shown
was chosen for its low offset voltage and low cost. Note that a negative power supply is needed for these
amplifiers if their outputs are required to go slightly negative to force the required reference voltages.
If reference voltages are desired that are more than a few tens of millivolts from the self-bias values, the circuit of
Figure 21 will allow forcing the reference voltages to whatever levels are desired. This circuit provides the best
performance because of the low source impedance of the transistors. Note that the VRTS and VRBS pins are left
floating.
VRT can be anywhere between VRB + 1.0V and the analog supply voltage, and VRB can be anywhere between
ground and 1.0V below VRT. To minimize noise effects and ensure accurate conversions, the total reference
voltage range (VRT - VRB) should be a minimum of 1.0V and a maximum of about 2.8V. If VRB is not required to
be below about +700mV, the -5V points in Figure 21 can be returned to ground and the negative supply
eliminated.
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20 2 24
AVSS DVSS
D7 10
D6 9
D5 8
1
D0 3
D1 4
D2 5
D3 6
D4 7
to
19
to
110
AVDD
17
+
-6
2
3
237,
1%
150,
1%
237,
1%
57.6,
1%
21 12
CLK
AVSS
16
23
22
VRTS
VRT
VRB
VRBS
62 pF
Analog
Input
10 PF
10 PF
0.1 PF
10 PF
+
+
131815 1114
0.1 PF
10 PF
DVDD
AVDD
Choke
+5V
ADC1175
LMH6702
150
1%
OE
ADC1175
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Because of resistor tolerances, the reference voltages can vary by as much as 6%. Choose an amplifier that can
drive a dynamic capacitance (see text).
Figure 19. Simple, Low Component Count, Self-Bias Reference Application
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Self-bias is still used, but the reference voltages are trimmed by providing a small trim current with the operational
amplifiers.
Figure 20. Better Defining the ADC Reference Voltage
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Driving the reference to force desired values requires driving with a low impedance source, provided by the
transistors. Pins 16 and 22 are not connected.
Figure 21.
POWER SUPPLY CONSIDERATIONS
Many A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately
bypassed. A 10µF tantalum or aluminum electrolytic capacitor should be placed within an inch (2.5 centimeters)
of the A/D power pins, with a 0.1 µF ceramic chip capacitor placed as close as possible to the converter's power
supply pins. Leadless chip capacitors are preferred because they have low lead inductance.
While a single voltage source should be used for the analog and digital supplies of the ADC1175, these supply
pins should be well isolated from each other to prevent any digital noise from being coupled to the analog power
pins. A wideband choke, such as the JW Miller FB20010-3B, is recommended between the analog and digital
supply lines, with a ceramic capacitor close to the analog supply pin. Avoid inductive components in the analog
supply line.
The converter digital supply should not be the supply that is used for other digital circuitry on the board. It should
be the same supply used for the A/D analog supply.
As is the case with all high speed converters, the ADC1175 should be assumed to have little a.c. power supply
rejection, especially when self-biasing is used by connecting VRT and VRTS together.
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No pin should ever have a voltage on it that is in excess of the supply voltages or below ground, not even on a
transient basis. This can be a problem upon application of power to a circuit. Be sure that the supplies to circuits
driving the CLK, OE, analog input and reference pins do not come up any faster than does the voltage at the
ADC1175 power pins.
Pins 11 and 13 are both labeled DVDD. Pin 11 is the supply point for the digital core of the ADC, where pin 13 is
used only to provide power to the ADC output drivers. As such, pin 11 may be connected to a voltage source
that is less than the +5V used for AVDD and DVDD to ease interfacing to low voltage devices. Pin 11 should never
exceed the pin 13 potential by more than 0.5V.
THE ADC1175 CLOCK
Although the ADC1175 is tested and its performance is ensured with a 20MHz clock, it typically will function with
clock frequencies from 1MHz to 30MHz.
If continuous conversions are not required, power consumption can be reduced somewhat by stopping the clock
at a logic low when the ADC1175 is not being used. This reduces the current drain in the ADC1175's digital
circuitry from a typical value of 2.5mA to about 100µA.
Note that powering up the ADC1175 without the clock running may not save power, as it will result in an
increased current flow (by as much as 170%) in the reference ladder. In some cases, this may increase the
ladder current above the specified limit. Toggling the clock twice at 1MHz or higher and returning it to the low
state will eliminate the excess ladder current.
An alternative power-saving technique is to power up the ADC1175 with the clock active, then halt the clock in
the low state after two or more clock cycles. Stopping the clock in the high state is not recommended as a
power-saving technique.
LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals is essential to ensure accurate conversion. Separate analog
and digital ground planes that are connected beneath the ADC1175 may be used, but best EMI practices require
a single ground plane. However, it is important to keep analog signal lines away from digital signal lines and
away from power supply currents. This latter requirement requires the careful separation and placement of power
planes. The use of power traces rather than one or more power planes is not recommended as higher
frequencies are not well filtered with lumped capacitances. To filter higher frequency noise components it is
necessary to have sufficient capacitance between the power and ground planes.
If separate analog and digital ground planes are used, the analog and digital grounds may be in the same layer,
but should be separated from each other. If separate analog and digital ground layers are used, they should
never overlap each other.
Capacitive coupling between a typically noisy digital ground plane and the sensitive analog circuitry can lead to
poor performance that may seem impossible to isolate and remedy. The solution is to keep the analog circuity
well separated from the digital circuitry.
Digital circuits create substantial supply and ground current transients. The logic noise thus generated could
have significant impact upon system noise performance. The best logic family to use in systems with A/D
converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the
74HC(T) and 74AC(T)Q families. The worst noise generators are logic families that draw the largest supply
current transients during clock or signal edges, like the 74F and the 74AC(T) families. In general, slower logic
families will produce less high frequency noise than do high speed logic families.
Since digital switching transients are composed largely of high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area
is more important than is total ground plane volume.
An effective way to control ground noise is by using a single, solid ground plane, splitting the power plane into
analog and digital areas and having power and ground planes in adjacent board layers. There should be no
traces within either the power or the ground layers of the board. The analog and digital power planes should
reside in the same board layer so that they can not overlap each other. The analog and digital power planes
define the analog and digital areas of the board.
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Generally, analog and digital lines should cross each other at 90 degrees to avoid getting digital noise into the
analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether. Clock lines
should be isolated from ALL other lines, analog and digital. Even the generally accepted 90 degree crossing
should be avoided as even a little coupling can cause problems at high frequencies. Best performance at high
frequencies and at high resolution is obtained with a straight signal path.
Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit
in which they are used. Inductors should not be placed side by side, not even with just a small part of their
bodies being beside each other.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
Any external component (e.g., a filter capacitor) connected between the converter's input and ground should be
connected to a very clean point in the ground return.
DYNAMIC PERFORMANCE
The ADC1175 is a.c. tested and its dynamic performance is ensured. To meet the published specifications, the
clock source driving the CLK input must be free of jitter. For best a.c. performance, isolating the ADC clock from
any digital circuitry should be done with adequate buffers, as with a clock tree. See Figure 22.
Figure 22. Isolating the ADC clock from Digital Circuitry.
It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other
signals. Other signals can introduce jitter into the clock signal.
COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should
not go more than 50mV below the ground pins or 50mV above the supply pins. Exceeding these limits on even a
transient basis can cause faulty or erratic operation. It is not uncommon for high speed digital circuits to exhibit
undershoot that goes more than a volt below ground due to improper line termination. A resistor of 50Ωto 100Ω
in series with the offending digital input, located close to the signal source, will usually eliminate the problem.
Care should be taken not to overdrive the inputs of the ADC1175. Such practice may lead to conversion
inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must
charge for each conversion, the more instantaneous digital current is required from DVDD and DGND. These
large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the
digital data outputs (with an 74AC541, for example) may be necessary if the data bus to be driven is heavily
loaded. Dynamic performance can also be improved by adding 47Ωto 100Ωseries resistors at each digital
output, reducing the energy coupled back into the converter output pins.
Using an inadequate amplifier to drive the analog input. As explained in THE ANALOG INPUT, the
capacitance seen at the input alternates between 4 pF and 11 pF with the clock. This dynamic capacitance is
more difficult to drive than is a fixed capacitance, and should be considered when choosing a driving device. The
LMH6702, LMH6609, LM6152, LM6154, LM6181 and LM6182 have been found to be excellent devices for
driving the ADC1175 analog input.
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Driving the VRT pin or the VRB pin with devices that can not source or sink the current required by the
ladder. As mentioned in REFERENCE INPUTS, care should be taken to see that any driving devices can source
sufficient current into the VRT pin and sink sufficient current from the VRB pin. If these pins are not driven with
devices than can handle the required current, these reference pins will not be stable, resulting in a reduction of
dynamic performance.
Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other
signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive
output noise and a reduction in SNR performance. Simple gates with RC timing is generally inadequate as a
clock source.
Input test signal contains harmonic distortion that interferes with the measurement of dynamic signal to
noise ratio. Harmonic and other interfering signals can be removed by inserting a filter at the signal input.
Suitable filters are shown in Figure 23 and Figure 24. The circuit of Figure 23 has cutoff of about 5.5 MHz and is
suitable for input frequencies of 1 MHz to 5 MHz. The circuit of Figure 24 has a cutoff of about 11 MHz and is
suitable for input frequencies of 5 MHz to 10 MHz. These filters should be driven by a generator of 75 Ohm
source impedance and terminated with a 75 ohm resistor.
Figure 23. 5.5 MHz Low Pass Filter to Eliminate Harmonics at the Signal Input
Use at input frequencies of 5 MHz to 10 MHz.
Figure 24. 11 MHz Low Pass Filter to Eliminate Harmonics at the Signal Input
Not considering the effect on a driven CMOS digital circuit(s) when the ADC1175 is in the power down
mode. Because the ADC1175 output goes into a high impedance state when in the power down mode, any
CMOS device connected to these outputs will have their inputs floating when the ADC is in power down. Should
the inputs of the circuit being driven by the ADC digital outputs float to a level near 2.5V, a CMOS device could
exhibit relative large supply currents as the input stage toggles rapidly. The solution is to use pull-down resistors
at the ADC outputs. The value of these resistors is not critical, as long as they do not cause excessive currents
in the outputs of the ADC1175. Low pull-down resistor values could result in degraded SNR and SINAD
performance of the ADC1175. Values between 5 kΩand 100 kΩshould work well.
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REVISION HISTORY
Changes from Revision G (April 2013) to Revision H Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 21
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PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ADC1175CIMTC/NOPB ACTIVE TSSOP PW 24 61 RoHS & Green SN Level-1-260C-UNLIM -20 to 75 ADC1175
CIMTC
ADC1175CIMTCX/NOPB ACTIVE TSSOP PW 24 2500 RoHS & Green SN Level-1-260C-UNLIM -20 to 75 ADC1175
CIMTC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADC1175CIMTCX/NOPB TSSOP PW 24 2500 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADC1175CIMTCX/NOPB TSSOP PW 24 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
22X 0.65
2X
7.15
24X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
BNOTE 4
4.5
4.3
A
NOTE 3
7.9
7.7
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0024A
SMALL OUTLINE PACKAGE
4220208/A 02/2017
1
12 13
24
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
24X (1.5)
24X (0.45)
22X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0024A
SMALL OUTLINE PACKAGE
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
12 13
24
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
24X (1.5)
24X (0.45)
22X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0024A
SMALL OUTLINE PACKAGE
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
12 13
24
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