CY7C144AV
CY7C006AV
3.3 V 8 K / 16 K × 8
Asynchronous Dual-Port Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-06051 Rev. *H Revised August 1, 2012
3.3 V 8 K / 16 K × 8 Dual-Port Static RAM
Features
■True dual-ported memory cells which allow simultaneous
access of the same memory location
■8 K / 16 K × 8 organizations (CY7C144AV/CY7C006AV)
■0.35-micron complementary metal oxide semiconductor
(CMOS) for optimum speed/power
■High-speed access: 25 ns
■Low operating power
❐Active: ICC = 115 mA (typical)
❐Standby: ISB3 = 10 A (typical)
■Fully asynchronous operation
■Automatic power-down
■Expandable data bus to 16 bits or more using Master/ Slave
chip select when using more than one device
■On-chip arbitration logic
■Semaphores included to permit software handshaking
between ports
■INT flag for port-to-port communication
■Pin select for Master or Slave
■Available in 64-pin thin quad flat pack (TQFP) (7C006AV and
7C144AV)
■Pb-free packages available
I/O
Control
Address
Decode
A0L–A12–13L
CEL
OEL
R/WL
BUSYL
I/O
Control
Interrupt
Semaphore
Arbitration
SEML
INTL
M/S
A0L–A12–13L
True Dual-Ported
RAM Array
A0R–A12–13R
CER
OER
R/WR
BUSYR
SEMR
INTR
Address
Decode A0R–A12–13R
[1] [1]
[3] [3]
R/WL
OEL
I/O0L–I/O7L
CEL
R/WR
OER
I/O0R–I/O7R
CER
13–14
8
13–14
8
13–14 13–14
[2]
[2]
[2]
[2]
Logic Block Diagram
Notes
1. I/O0–I/O7 for × 8 devices
2. A0–A12 for 8K devices; A0–A13 for 16K devices
3. BUSY is an output in master mode and an input in slave mode.
CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016A V CY7C007AV CY7C017AV 3.3 V 8 K / 16 K × 8
Asynchronous Dual-Port Static RAM
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 2 of 21
Contents
Pin Configurations ...........................................................3
Selection Guide ................................................................4
Pin Definitions ..................................................................4
Architecture ......................................................................4
Functional Description .....................................................4
Read and Write Operations .........................................4
Interrupts ..................................................................... 5
Busy ............................................................................5
Master/Slave ...............................................................5
Semaphore Operation ................................................. 5
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
Electrical Characteristics .................................................6
Capacitance ...................................................................... 6
AC Test Loads and Waveforms .......................................7
Data Retention Mode ........................................................ 7
Timing ................................................................................ 7
Switching Characteristics ................................................ 8
Switching Waveforms .................................................... 10
Ordering Information ...................................................... 17
8 K × 8 3.3 V Asynchronous Dual-Port SRAM .......... 17
16 K × 8 3.3 V Asynchronous Dual-Port SRAM ........ 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC Solutions ......................................................... 21
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 3 of 21
Pin Configurations
Figure 1. 64-pin TQFP pinout (Top View)
Figure 2. 64-pin TQFP pinout (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 50
32 49
16
GND
OER
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
GND
VCC
A4L
A3L
A2L
A1L
A0L
GND
BUSYL
BUSYR
M/S
A0R
A1R
A2R
A3R
A4R
INTL
INTR
I/O7R
A5R
A12R
A11R
A10R
A9R
A8R
A7R
A6R
NC
CER
SEMR
R/WR
VCC
OEL
I/O1L
I/O0L
A5L
A12L
A11L
A10L
A9L
A8L
A7L
A6L
NC
CEL
SEML
R/WL
CY7C144AV (8 K × 8)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 50
32 49
16
GND
OER
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
GND
VCC
A4L
A3L
A2L
A1L
A0L
GND
BUSYL
BUSYR
M/S
A0R
A1R
A2R
A3R
A4R
INTL
INTR
I/O7R
A5R
A12R
A11R
A10R
A9R
A8R
A7R
A6R
A13R
CER
SEMR
R/WR
VCC
OEL
I/O1L
I/O0L
A5L
A12L
A11L
A10L
A9L
A8L
A7L
A6L
A13L
CEL
SEML
R/WL
CY7C006AV (16 K × 8)
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 4 of 21
Architecture
The CY7C144AV and CY7C006AV consist of an array of 8K and
16K words of 8 bits each of dual-port RAM cells, I/O and address
lines, and control signals (CE, OE, R/W). These control pins
permit independent access for reads or writes to any location in
memory. To handle simultaneous writes/reads to the same
location, a BUSY pin is provided on each port. Two interrupt
(INT) pins can be utilized for port-to-port communication. Two
semaphore (SEM) control pins are used for allocating shared
resources. With the M/S pin, the device can function as a master
(BUSY pins are outputs) or as a slave (BUSY pins are inputs).
The device also has an automatic power-down feature controlled
by CE. Each port is provided with its own output enable control
(OE), which allows data to be read from the device.
Functional Description
The CY7C144AV and CY7C006AV are low-power CMOS
8 K / 16 K × 8 dual-port static RAMs. Various arbitration
schemes are included on the devices to handle situations when
multiple processors access the same piece of data. Two ports
are provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The devices can be
utilized as standalone 8-bit dual-port static RAMs or multiple
devices can be combined in order to function as a 16-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 16-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include
interprocessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power-down feature is controlled independently on
each port by a Chip Select (CE) pin.
Read and Write Operations
When writing data must be set up for a duration of tSD before the
rising edge of R/W in order to guarantee a valid write. A write
operation is controlled by either the R/W pin (see Write Cycle No.
1 waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summarized
in Table 1 on page 16.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
Selection Guide
Description CY7C144AV/CY7C006AV
-25
Maximum access time (ns) 25
Typical operating current (mA) 115
Typical standby current for ISB1 (mA) (Both ports TTL level) 30
Typical standby current for ISB3 (A) (Both ports CMOS level) 10
Pin Definitions
Left Port Right Port Description
CELCERChip enable
R/WLR/WRRead/Write enable
OELOEROutput enable
A0L–A12/13L A0R–A12/13R Address (A0–A12 for 8K devices; A0–A13 for 16K devices)
I/O0L–I/O7L I/O0R–I/O7R Data bus input/output (I/O0–I/O7 for × 8 devices)
SEML SEMRSemaphore Enable
INTLINTRInterrupt flag
BUSYLBUSYRBusy flag
M/S Master or Slave select
VCC Power
GND Ground
NC No connect
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 5 of 21
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port tDDD
after the data is presented on the other port.
When reading the device, the user must assert both the OE and
CE pins. Data will be available tACE after CE or tDOE after OE is
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin and OE must
also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (1FFF for the
CY7C144AV and 3FFF for the CY7C006AV) is the mailbox for
the right port and the second-highest memory location (1FFE for
the CY7C144AV and 3FFE for the CY7C006AV) is the mailbox
for the left port. When one port writes to the other port’s mailbox,
an interrupt is generated to the owner. The interrupt is reset when
the owner reads the contents of the mailbox. The message is
user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it. If an application
does not require message passing, do not connect the interrupt
pin to the processor’s interrupt request input pin. The operation
of the interrupts and their interaction with Busy are summarized
in Table 2 on page 16.
Busy
The CY7C144AV and CY7C006AV provide on-chip arbitration to
resolve simultaneous memory location access (contention). If
both ports’ CEs are asserted and an address match occurs within
tPS of each other, the busy logic will determine which port has
access. If tPS is violated, one port will definitely gain permission
to the location, but it is not predictable which port will get that
permission. BUSY will be asserted tBLA after an address match
or tBLC after CE is taken LOW.
Master/Slave
An M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the slave.
This will allow the device to interface to a master device with no
external components. Writing to slave devices must be delayed
until after the BUSY input has settled (tBLC or tBLA), otherwise,
the slave chip may begin a write cycle during a contention
situation. When tied HIGH, the M/S pin allows the device to be
used as a master and, therefore, the BUSY line is an output.
BUSY can then be used to send the arbitration outcome to a
slave.
Semaphore Operation
The CY7C144AV and CY7C006AV provide eight semaphore
latches, which are separate from the dual-port memory locations.
Semaphores are used to reserve resources that are shared
between the two ports. The state of the semaphore indicates that
a resource is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a zero to a semaphore
location. The left port then verifies its success in setting the latch
by reading it. After writing to the semaphore, SEM or OE must
be deasserted for tSOP before attempting to read the semaphore.
The semaphore value will be available tSWRD + tDOE after the
rising edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control of the shared resource,
otherwise (reads a one) it assumes the right port has control and
continues to poll the semaphore. When the right side has
relinquished control of the semaphore (by writing a one), the left
side will succeed in gaining control of the semaphore. If the left
side no longer requires the semaphore, a one is written to cancel
its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore will be set to
one for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port would immediately own the semaphore as soon as the
left port released it. Table 3 on page 16 shows sample
semaphore operations.
When reading a semaphore, all data lines output the semaphore
value. The read value is latched in an output register to prevent
the semaphore from changing state during a write from the other
port. If both ports attempt to access the semaphore within tSPS
of each other, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control
the semaphore.
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 6 of 21
Maximum Ratings
Exceeding maximum ratings [4] may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
Power applied .......................................... –55 °C to +125 °C
Supply voltage to ground potential ..............–0.5 V to +4.6 V
DC voltage applied to
Outputs in High Z state ........................ –0.5 V to VCC+ 0.5 V
DC input voltage [5] ............................. –0.5 V to VCC + 0.5 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage .......................................... > 2001 V
Latch-up current .................................................... > 200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0 °C to +70 °C 3.3 V 300 mV
Electrical Characteristics
Over the Operating Range
Parameter Description
CY7C144AV/CY7C006AV
-25 Unit
Min Typ Max
VOH Output HIGH voltage (VCC = 3.3 V) 2.4 – – V
VOL Output LOW voltage – 0.4 V
VIH Input HIGH voltage 2.0 – V
VIL Input LOW voltage – 0.8 V
IOZ Output leakage current –10 10 A
ICC Operating current (VCC = Max., IOUT =0mA)
Outputs Disabled
Commercial – 115 165 mA
ISB1 Standby current (Both ports TTL level)
CEL & CER VIH, f = fMAX [6] Commercial – 30 40 mA
ISB2 Standby current (One port TTL level)
CEL | CER VIH, f = fMAX [6] Commercial – 65 95 mA
ISB3 Standby current (Both ports CMOS level)
CEL & CER VCC – 0.2 V, f = 0 [6] Commercial – 10 500 A
ISB4 Standby current (One port CMOS level)
CEL | CER VIH, f = fMAX [6] Commercial – 60 80 mA
Capacitance
Parameter [7] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz, VCC = 3.3 V 10 pF
COUT Output capacitance 10 pF
Notes
4. The Voltage on any input or I/O pin can not exceed the power pin during power-up.
5. Pulse width < 20 ns.
6. fMAX = 1/tRC. All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
7. Tested initially and after any design or process changes that may affect these parameters.
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 7 of 21
Data Retention Mode
The CY7C144AV and CY7C006AV are designed with battery
backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules ensure data
retention:
1. Chip enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2 V.
2. CE must be kept between VCC – 0.2 V and 70% of VCC during
the power-up and power-down transitions.
3. The RAM can begin operation > tRC after VCC reaches the
minimum operating voltage (3.0 Volts).
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.0V
GND 90% 90%
10%
3ns 3ns
10%
ALL INPUT PULSES
(a) Normal Load (Load 1)
R1 = 590
3.3 V
OUTPUT
R2 = 435
C= 30pF VTH =1.4 V
OUTPUT
C
=
30 pF
(b) Thévenin Equivalent (Load 1) (c) Three-State Delay(Load 2)
R1 = 590
R2 = 435
3.3 V
OUTPUT
C= 5pF
RTH = 250
including scope and jig)
(Used for tLZ, tHZ, tHZWE & tLZWE
Timing
Figure 4. Timing
Parameter Test Conditions [8] Max Unit
ICCDR1 @ VCCDR = 2 V 50 A
Data Retention Mode
3.0 V 3.0 V
VCC 2.0 V
VCC to VCC –0.2 V
VCC
CE
tRC
VIH
Note
8. CE = VCC, VIN = GND to VCC, TA = 25 °C. This parameter is guaranteed but not tested.
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 8 of 21
Switching Characteristics
Over the Operating Range
Parameter [9] Description
CY7C144AV/CY7C006AV
Unit
-25
Min Max
READ CYCLE
tRC Read cycle time 25 – ns
tAA Address to data valid – 25 ns
tOHA Output hold from address change 3 – ns
tACE[10] CE LOW to data valid – 25 ns
tDOE OE LOW to data valid – 13 ns
tLZOE[11, 12] OE Low to Low Z 3 – ns
tHZOE[11, 12] OE HIGH to High Z – 15 ns
tLZCE[11, 12] CE LOW to Low Z 3 – ns
tHZCE[11, 12] CE HIGH to High Z – 15 ns
tPU CE LOW to power-up 0 – ns
tPD CE HIGH to power-down – 25 ns
WRITE CYCLE
tWC Write cycle time 25 – ns
tSCE[10] CE LOW to write end 20 – ns
tAW Address valid to write end 20 – ns
tHA Address hold from write end 0 – ns
tSA[10] Address set-up to write start 0 – ns
tPWE Write pulse width 20 – ns
tSD Data set-up to write end 15 – ns
tHD Data hold from write end 0 – ns
tHZWE R/W LOW to High Z – 15 ns
tLZWE R/W HIGH to Low Z 3 – ns
tWDD[13] Write pulse to data delay – 50 ns
tDDD[13] Write data valid to read data valid – 35 ns
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 9 of 21
BUSY TIMING
tBLA BUSY LOW from address match – 20 ns
tBHA BUSY HIGH from address mismatch – 20 ns
tBLC BUSY LOW from CE LOW – 20 ns
tBHC BUSY HIGH from CE HIGH – 17 ns
tPS Port set-up for priority 5 – ns
tWB R/W HIGH after BUSY (Slave) 0 – ns
tWH R/W HIGH after BUSY HIGH (Slave) 17 – ns
tBDD[14] BUSY HIGH to data valid – 25 ns
INTERRUPT TIMING
tINS INT set time – 20 ns
tINR INT reset time – 20 ns
SEMAPHORE TIMING
tSOP SEM flag update pulse (OE or SEM)12–ns
tSWRD SEM flag write to read time 5 – ns
tSPS SEM flag contention window 5 – ns
tSAA SEM address access time – 25 ns
Switching Characteristics (continued)
Over the Operating Range
Parameter [9] Description
CY7C144AV/CY7C006AV
Unit
-25
Min Max
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 10 of 21
Switching Waveforms
Figure 5. Read Cycle No. 1 (Either Port Address Access) [15, 16, 17]
Figure 6. Read Cycle No. 2 (Either Port CE/OE Access) [15, 18, 19]
Figure 7. Read Cycle No. 3 (Either Port) [15, 17, 18, 19]
tRC
tAA
tOHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
tOHA
tACE
tLZOE
tDOE
tHZOE
tHZCE
DATA VALID
tLZCE
tPU tPD
ISB
ICC
DATA OUT
OE
CE
CURRENT
DATA OUT
tRC
ADDRESS
tAA tOHA
CE
tLZCE
tABE
tHZCE
tACE
tLZCE
Notes
15. R/W is HIGH for read cycles.
16. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads.
17. OE = VIL.
18. Address valid prior to or coincident with CE transition LOW.
19. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 11 of 21
Figure 8. Write Cycle No. 1 (R/W Controlled Timing) [20, 21, 22, 23]
Figure 9. Write Cycle No. 2 (CE Controlled Timing) [20, 21, 22, 27]
Switching Waveforms (continued)
tAW
tWC
tPWE
tHD
tSD
tHA
CE
R/W
OE
DATA OUT
DATA IN
ADDRESS
tHZOE
tSA
tHZWE tLZWE
[24]
[24]
[23]
[25]
Note 26 Note 26
tAW
tWC
tSCE
tHD
tSD
tHA
CE
R/W
DATA IN
ADDRESS
tSA
[25]
Notes
20. R/W must be HIGH during all address transitions.
21. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM.
22. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as
short as the specified tPWE.
24. Transition is measured 500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
25. To access RAM, CE = VIL, SEM = VIH.
26. During this period, the I/O pins are in the output state, and input signals must not be applied.
27. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 12 of 21
Figure 10. Semaphore Read after Write Timing, either Side [28]
Figure 11. Timing Diagram of Semaphore Contention [29, 30, 31]
Switching Waveforms (continued)
tSOP
tSAA
VALID ADRESS VALID ADRESS
tHD
DATAIN VALID DATAOUT VALID
tOHA
tAW
tHA
tACE
tSOP
tSCE
tSD
tSA tPWE
tSWRD tDOE
WRITE CYCLE READ CYCLE
OE
R/W
I/O 0
SEM
A0–A 2
MATCH
tSPS
A0L–A2L
MATCH
R/WL
SEML
A0R–A2R
R/WR
SEM R
Notes
28. CE = HIGH for the duration of the above timing (both write and read cycle).
29. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
30. Semaphores are reset (available to both ports) at cycle start.
31. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 13 of 21
Figure 12. Timing Diagram of Read with BUSY (M/S = HIGH) [32]
Figure 13. Write Timing with Busy Input (M/S = LOW)
Switching Waveforms (continued)
VALID
tDDD
tWDD
MATCH
MATCH
R/WR
DATA INR
DATAOUTL
tWC
ADDRESSR
tPWE
VALID
tSD tHD
ADDRESSL
tPS
tBLA tBHA
tBDD
BUSYL
tPWE
R/W
BUSY
tWB tWH
Note
32. CEL = CER = LOW.
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 14 of 21
Figure 14. Busy Timing Diagram No.1 (CE Arbitration) [33]
Figure 15. Busy Timing Diagram No.2 (Address Arbitration) [33]
Switching Waveforms (continued)
ADDRESS MATCH
tPS
tBLC tBHC
ADDRESS MATCH
tPS
tBLC tBHC
CERValid First:
ADDRESS L,R
BUSY
R
CEL
CER
BUSYL
CER
CE L
ADDRESSL,R
CELValid First:
ADDRESS MATCH
tPS
ADDRESSL
BUSYR
ADDRESS MISMATCH
tRC or tWC
tBLA tBHA
ADDRESSR
ADDRESS MATCH ADDRESS MISMATCH
tPS
ADDRESSL
BUSY L
tRC or tWC
tBLA tBHA
ADDRESSR
Right Address Valid First:
Left Address Valid First
Note
33. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 15 of 21
Figure 16. Interrupt Timing Diagrams
Switching Waveforms (continued)
WRITE 1FFF/3FFF (See Functional Description)
tWC
Right Side Clears INTR:
tHA
READ 1FFF/3FFF
tRC
tINR
WRITE 1FFE/3FFE (See Functional Description)
tWC
Right Side Sets INTL:
Left Side Sets INTR:
Left Side Clears INT L:
READ 1FFE/3FFE
tINR
tRC
ADDRESSR
CE L
R/W L
INT L
OE L
ADDRESSR
R/WR
CE R
INTL
ADDRESSR
CER
R/WR
INTR
OE R
ADDRESSL
R/WL
CE L
INTR
tINS
tHA
tINS
(See Functional Description)
(See Functional Description)
[34]
[35]
[35]
[35]
[34]
[35]
Notes
34. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
35. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 16 of 21
Table 1. Non-Contending Read/Write
Inputs Outputs Operation
CE R/W OE SEM I/O0–I/O7
H X X H High Z Deselected: Power-down
H H L L Data out Read data in semaphore flag
X X H X High Z I/O lines disabled
H X L Data in Write into semaphore flag
L H L H Data out Read
L L X H Data in Write
L X X L Not allowed
Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)
Function Left Port Right Port
R/WLCELOELA0L–13LINTLR/WRCEROERA0R–13R INTR
Set Right INTR flag L L X 1FFF/3FFF[36] XXXX X L
[37]
Reset Right INTR flagXXX X XXL L1FFF/3FFF
[36] H[38]
Set Left INTL flag X X X X L[38] LLX1FFE/3FFE
[36] X
Reset Left INTL flag X L L 1FFE/3FFE[36] H[37] XXXXX
Table 3. Semaphore Operation Example
Function I/O0–I/O7 Left I/O0–I/O7 Right Status
No action 1 1 Semaphore free
Left port writes 0 to semaphore 0 1 Left Port has semaphore token
Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore
Left port writes 1 to semaphore 1 0 Right port obtains semaphore token
Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore
Right port writes 1 to semaphore 0 1 Left port obtains semaphore token
Left port writes 1 to semaphore 1 1 Semaphore free
Right port writes 0 to semaphore 1 0 Right port has semaphore token
Right port writes 1 to semaphore 1 1 Semaphore free
Left port writes 0 to semaphore 0 1 Left port has semaphore token
Left port writes 1 to semaphore 1 1 Semaphore free
Notes
36. See Functional Description for specific addresses by device part number.
37. If BUSYL = L, then no change.
38. If BUSYR = L, then no change.
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 17 of 21
Ordering Information
Ordering Code Definitions
8 K × 8 3.3 V Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
25 CY7C144AV-25AXC A65 64-pin TQFP (Pb-free) Commercial
16 K × 8 3.3 V Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
25 CY7C006AV-25AXC A65 64-pin TQFP (Pb-free) Commercial
Temperature Range:
C = Commercial
X = Pb-free (RoHS Compliant)
Package Type:
A = 64-pin TQFP
Speed Grade: 25 ns
AV = 3.3 V
Part Identifier: XXX = 144 or 006
144 = 8 K × 8
006 = 16 K × 8
Technology Code: C = CMOS
Marketing Code: 7 = Dual Port SRAM
Company ID: CY = Cypress
CCY XXX - 25 CA XAV7
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 18 of 21
Package Diagrams
Figure 17. 64-pin TQFP (14 × 14 × 1.4 mm) A64SA Package Outline, 51-85046
51-85046 *E
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 19 of 21
Acronyms Document Conventions
Units of Measure
Acronym Description
CE chip enable
CMOS complementary metal oxide semiconductor
I/O input/output
OE output enable
SRAM static random access memory
TQFP thin quad flat pack
TTL transistor-transistor logic
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
Amicroampere
mA milliampere
mm millimeter
mV millivolt
ns nanosecond
ohm
% percent
pF picofarad
Vvolt
Wwatt
CY7C144AV
CY7C006AV
Document Number: 38-06051 Rev. *H Page 20 of 21
Document History Page
Document Title: CY7C144AV/CY7C006AV, 3.3 V 8 K / 16 K × 8 Asynchronous Dual-Port Static RAM
Document Number: 38-06051
Rev. ECN No. Issue Date Orig. of
Change Description of Change
** 110203 12/02/01 SZV Change from Spec number: 38-00837 to 38-06051
*A 122301 12/27/02 RBI Updated Maximum Ratings (Added Power up requirements to Maximum
Ratings Information).
*B 237623 See ECN YDT Updated Features (Removed cross information).
*C 373615 See ECN PCX Added Pb-Free Logo
Updated Ordering Information (Added Pb-free parts to ordering information
namely CY7C144AV-25AXC, CY7C144AV-25JXC, CY7C006AV-25AXC).
*D 2896210 03/22/2010 RAME Updated Ordering Information.
Updated Package Diagrams.
*E 3161515 02/04/2011 ADMU Removed information for parts namely CY7C138AV, CY7C139AV,
CY7C145AV, CY7C016AV, CY7C007AV, CY7C017AV across the document.
Updated Ordering Information (Removed CY7C145AV-20JC).
Updated Package Diagrams.
*F 3352067 08/23/2011 ADMU Updated Features.
Updated Operating Range (Removed industrial specification rows).
Updated Electrical Characteristics (Removed industrial specification rows).
Updated in new template.
*G 3402091 10/12/2011 ADMU Updated Ordering Information (Removed pruned part CY7C144AV-25AC).
Updated Package Diagrams.
*H 3699185 08/01/2012 SMCH Updated title to read as “CY7C144AV/CY7C006AV, 3.3 V 8 K / 16 K × 8
Asynchronous Dual-Port Static RAM”.
Updated Switching Characteristics (Removed the Note “Test conditions used
are Load 3.” and its reference, removed the Note “Test conditions used are
Load 2.” and its reference, removed the Note “This parameter is guaranteed
but not tested. For information on port-to-port delay through RAM cells from
writing port to reading port, refer to Read Timing with Busy waveform.” and
its reference).
Updated Switching Waveforms (Updated Figure 14).
Document Number: 38-06051 Rev. *H Revised August 1, 2012 Page 21 of 21
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C144AV
CY7C006AV
© Cypress Semiconductor Corporation, 2001-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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