March 2008 Rev 3 1/53
1
STW81103
Multi-band RF frequency synthesizer with integrated VCOs
Features
■Integer-N frequency synthesizer
■Dual differential integrated VCOs with
automatic center frequency calibration:
– 2500 - 3050 MHz (direct output)
– 4350 - 5000 MHz (direct output)
– 1250 - 1525 MHz (internal divider by 2)
– 2175 - 2500 MHz (internal divider by 2)
– 625 - 762.5 MHz (internal divider by 4)
– 1087.5 - 1250 MHz (internal divider by 4)
■Excellent integrated phase noise
■Fast lock time: 150µs
■Dual modulus programmable prescaler
(16/17 or 19/20)
■2 programmable counters to achieve a
feedback division ratio from 256 to 65551
(prescaler 16/17) and from 361 to 77836
(prescaler 19/20).
■Programmable reference frequency divider
(10 bits)
■Phase frequency comparator and charge pump
■Programmable charge pump current
■Digital lock detector
■Dual digital bus interface: SPI and I2C bus (fast
mode) with 3 bit programmable address
(1100A2A1A0)
■3.3 V power supply
■Power down mode (hardware and software)
■Small size exposed pad VFQFPN28 package
5 mm x 5 mm x 1.0 mm
■Process: BICMOS 0.35 µm SiGe
Applications
■2.5G and 3G Cellular infrastructure equipment
■CATV equipment
■Instrumentation and test equipment
■Other wireless communication systems
Description
The STMicroelectronics STW81103 is an
integrated RF synthesizer with voltage controlled
oscillators (VCOs). Showing high performance,
high integration, low power, and multi-band
performances, STW81103 is a low cost one chip
alternative to discrete PLL and VCOs solutions.
STW81103 includes an Integer-N frequency
synthesizer and two fully integrated VCOs
featuring low phase noise performance and a
noise floor of -155dBc/Hz. The combination of
wide frequency range VCOs (thanks to center-
frequency calibration over 32 sub-bands) and
multiple output options (direct output, divided by 2
or divided by 4) allows to cover the
625 MHz-762.5 MHz, the 1087.5 MHz-1525 MHz,
the 2175 MHz-3050 MHz and the
4350 MHz-5000 MHz bands.
The STW81103 is designed with
STMicroelectronics advanced 0.35 µm SiGe
process.
www.st.com
Contents STW81103
2/53
Contents
1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5 Phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 Reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 Reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4 A and B counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.5 Phase frequency detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.6 Lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.7 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.8 Voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.8.1 VCO selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.8.2 VCO frequency calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.8.3 VCO voltage amplitude control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.9 Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.9.1 Output buffer control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.10 External VCO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6I
2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STW81103 Contents
3/53
6.1.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.2 START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.3 Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.4 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.5 Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.6 Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.7 Current byte address read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.1 Write-only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.2 Read-only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3.3 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4 VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4.1 VCO calibration auto-restart feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7 SPI digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.3 Bit tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.3.1 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.4 VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.4.1 VCO calibration auto-restart feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.1 Direct output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.2 Divided by 2 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.3 Divided by 4 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.4 Evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
List of tables STW81103
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List of tables
Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. Phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Current value vs. selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. VCO A performances versus amplitude setting (Freq = 2.8 GHz) . . . . . . . . . . . . . . . . . . . 24
Table 9. VCO B performances vs. amplitude setting (Freq = 4.7 GHz) . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. EXT_PD pin function setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 12. Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 13. Current byte address read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 14. Data and clock timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 15. Start and stop timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 16. Ack timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 17. Write-only registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 18. Functional modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 19. SPI data structure (MSB is sent first) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 20. Address decoder and outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 21. SPI timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 22. Bits at 00h and ST1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 23. Bits at 01h and ST2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 24. Order code of the evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 25. Package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 26. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 27. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
STW81103 List of figures
5/53
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. VCO A (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4. VCO B (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. VCO A (direct output) closed loop phase noise at 2.775 GHz
(FSTEP=200 kHz; FPFD=200 kHz; ICP=2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. VCO B (direct output) closed loop phase noise at 4.675 GHz
(FSTEP=200 kHz; FPFD=200 kHz; ICP=3 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. VCO A (div. by 2 output) closed loop phase noise at 1.3876 GHz
(FSTEP=200 kHz; FPFD=400 kHz; ICP=1.5 mA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. VCO B (div. by 2 output) closed loop phase noise at 2.3376 GHz
(FSTEP=200 kHz; FPFD=400 kHz; ICP=2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. VCO A (div. by 4 output) closed loop phase noise at 693.8 MHz
(FSTEP=200 kHz; FPFD=800 kHz; ICP=1 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. VCO B (div. by 4 output) closed loop phase noise at 1168.8 MHz
(FSTEP=200 kHz; FPFD=800 kHz; ICP=1.5 mA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. PFD frequency spurs (direct output; FPFD=200 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. PFD frequency spurs (div. by 2 output; FPFD=400 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. PFD frequency spurs (div. by 4 output; FPFD=800 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. Settling time (final frequency=2.4 GHz; FPFD=400 kHz; ICP=2.5 mA) . . . . . . . . . . . . . . . 17
Figure 15. Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. VCO divider diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17. PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 19. VCO sub-bands frequency characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 20. Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 21. START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 22. Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 23. Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 24. Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 25. Ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 26. SPI input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 27. SPI timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 28. Differential/single-ended output network (MATCH_LC_LUMP_4G_DIFF.dsn) . . . . . . . . . 41
Figure 29. LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn) . . . . . . . . . . . . . . 42
Figure 30. Evaluation board (EVB4G) matching network (MATCH_EVB4G.dsn) . . . . . . . . . . . . . . . . 43
Figure 31. Differential/single-ended output network (MATCH_LC_LUMP_2G_DIFF.dsn) . . . . . . . . . 43
Figure 32. LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) . . . . . . . . . . . . . . 44
Figure 33. Evaluation board (EVB2G) matching network (MATCH_EVB2G.dsn) . . . . . . . . . . . . . . . . 44
Figure 34. LC lumped balun for divided by 4 output (MATCH_LC_LUMP_1G.dsn) . . . . . . . . . . . . . . 45
Figure 35. Evaluation board (EVB1G) matching network (MATCH_EVB1G.dsn) . . . . . . . . . . . . . . . . 46
Figure 36. Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 37. Ping-pong architecture diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 38. Application diagram with external VCO (LO output from STW81103) . . . . . . . . . . . . . . . . 49
Figure 39. Application diagram with external VCO (LO output from VCO) . . . . . . . . . . . . . . . . . . . . . 49
Figure 40. VFQFPN28 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Block diagram and pin configuration STW81103
6/53
1 Block diagram and pin configuration
1.1 Block diagram
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STW81103 Block diagram and pin configuration
7/53
1.2 Pin configuration
Figure 2. Pin connection (top view)
Table 1. Pin description
Pin No Name Description Observation
1 VDD_VCOA VCO A power supply
2 VDD_DIV2 Divider by 2 power supply
3 VDD_OUTBUF Output buffer power supply
4 OUTBUFP LO buffer positive output Open collector
5 OUTBUFN LO buffer negative output Open collector
6 VDD_DIV4 Divider by 4 power supply
7 VDD_VCOB VCO B power supply
8 VDD_ESD ESD positive rail power supply
9 VCTRL VCO control voltage
QFN 28
VDD_VCOA
ADD2
SCL/CLK
VDD_DBUS
SDA/DATA
EXT_PD
ADD1
ADD0/LOAD
VDD_ESD
REXT
LOCK_DET
VDD_CP
TEST1
VCTRL
ICP
VDD_DIV2
VDD_OUTBUF
OUTBUFP
OUTBUFN
VDD_DIV4
VDD_VCOB
DBUS_SEL
VDD_BUFVCO
EXTVCO_INP
EXTVCO_INN
VDD_PLL
REF_CLK
TEST2
Block diagram and pin configuration STW81103
8/53
10 ICP PLL charge pump output
11 REXT External resistance connection for PLL
charge pump
12 VDD_CP Power supply for charge pump
13 TEST1 Test input 1
For test purposes only;
must be connected to
GND
14 LOCK_DET Lock detector CMOS output
(IOUT=4mA)
15 TEST2 Test input 2
For test purposes only;
must be connected to
GND
16 REF_CLK Reference clock input
17 VDD_PLL PLL digital power supply
18 EXTVCO_INN External VCO negative input
For test purposes only;
must be connected to
GND
19 EXTVCO_INP External VCO positive input
For test purposes only;
must be connected to
GND
20 VDD_BUFVCO VCO buffer power supply
21 DBUS_SEL Digital Bus Interface select CMOS input
22 VDD_DBUS SPI and I2C bus power supply
23 EXT_PD Power down hardware
‘0’ device ON; ‘1’ device OFF CMOS input
24 SDA/DATA I2CBUS/SPI data line CMOS Bidir Schmitt
triggered (IOUT=4mA)
25 SCL/CLK I2CBUS/SPI clock line CMOS input Schmitt
triggered
26 ADD0/LOAD I2CBUS address select pin/ SPI load line CMOS input
27 ADD1 I2CBUS address select pin
CMOS input; must be
connected to GND in SPI
mode
28 ADD2 I2CBUS address select pin
CMOS input; must be
connected to GND in SPI
mode
Table 1. Pin description (continued)
Pin No Name Description Observation
STW81103 Electrical specifications
9/53
2 Electrical specifications
2.1 Absolute maximum ratings
2.2 Operating conditions
Table 2. Absolute maximum ratings
Symbol Parameter Values Unit
AVCC Analog supply voltage 0 to 4.6 V
DVCC Digital supply voltage 0 to 4.6 V
Tstg Storage temperature +150 °C
ESD
Electrical static discharge
- HBM(1)
- CDM-JEDEC standard
- MM
4
1.5
0.2
kV
1. The maximum rating of the ESD protection circuitry on pin 4 and pin 5 is 800 V.
Table 3. Operating conditions (1)
Symbol Parameter Test conditions Min. Typ. Max. Units
AVCC Analog supply voltage 3.0 3.3 3.6 V
DVCC Digital supply voltage 3.0 3.3 3.6 V
IVDD1
VDD1 current
consumption 90 mA
IVDD2
VDD2 current
consumption 12 mA
Tamb
Operating ambient
temperature -40 85 °C
Tj
Maximum junction
temperature 125 °C
Rth j-a
Junction to ambient
package thermal
resistance
Multilayer JEDEC board 44 °C/W
Rth j-b
Junction to board
package thermal
resistance
Multilayer JEDEC board 26.3 °C/W
Rth j-c
Junction to case
package thermal
resistance
Multilayer JEDEC board 6.3 °C/W
1. Refer to
Figure 36: Typical application diagram
.
Electrical specifications STW81103
10/53
2.3 Digital logic levels
2.4 Electrical specifications
All electrical specifications are intended for a 3.3 V supply voltage.
l
Table 4. Digital logic levels
Symbol Parameter Test conditions Min. Typ. Max. Units
Vil Low-level input voltage 0.2*Vdd V
Vih High-level input voltage 0.8*Vdd V
Vhyst Schmitt trigger hysteresis 0.8 V
Vol Low-level output voltage 0.4 V
Voh High-level output voltage 0.85*Vdd V
Table 5. Electrical specifications
Symbol Parameter Condition Min. Typ. Max. Unit
Output frequency range
FOUTA
Output frequency range with
VCOA
Direct output 2500 3050 MHz
Divider by 2 1250 1525 MHz
Divider by 4 625 762.5 MHz
FOUTB
Output frequency range with
VCOB
Direct output 4350 5000 MHz
Divider by 2 2175 2500 MHz
Divider by 4 1087.5 1250 MHz
VCO dividers
N VCO divider ratio Prescaler 16/17 256 65551
Prescaler 19/20 361 77836
Reference clock and phase frequency detector
Fref Reference input frequency 10 200 MHz
Reference input sensitivity(1) 0.35 1 1.5 Vpeak
R Reference divider ratio 2 1023
FPFD PFD input frequency 16 MHz
FSTEP Frequency step(2)
Prescaler 16/17 FOUT/
65551
FOUT/
256 Hz
Prescaler 19/20 FOUT/
77836
FOUT/
361 Hz
STW81103 Electrical specifications
11/53
Charge pump
ICP ICP sink/source(3) 3-bit programmable 5 mA
VOCP
Output voltage compliance
range 0.4 Vdd-0.3 V
Spurious(4)
Direct output (FPFD=200 kHz) -76 dBc
Divider by 2 (FPFD=400 kHz) -82 dBc
Divider by 4 (FPFD=800 kHz) -88 dBc
VCOs
KVCOA VCOA sensitivity(5)
Lower frequency range 45 65 85 MHz/V
Intermediate frequency range 60 80 105 MHz/V
Higher frequency range 85 105 145 MHz/V
KVCOB VCOB sensitivity(5)
Lower frequency range 45 65 85 MHz/V
Intermediate frequency range 60 80 100 MHz/V
Higher frequency range 85 100 130 MHz/V
ΔTLK
Maximum temperature
variation for continuous
lock(5) (6)
VCO A 125 °C
VCO B 95 °C
VCOA pushing(5) 47MHz/V
VCOB pushing(5) 15 21 MHz/V
VCTRL VCO control voltage(5) 0.4 3 V
LO harmonic spurious(5) -20 dBc
IVCOA VCOA current consumption FVCO=2.8 GHz; amplitude[11] 30 mA
FVCO=2.8 GHz; amplitude[00] 16 mA
IVCOB VCOB current consumption FVCO=4.7 GHz; amplitude[11] 24 mA
FVCO=4.7 GHz; amplitude[00] 13 mA
IVCOBUF VCO buffer consumption 15 mA
IDIV2 Divider by 2 consumption 17 mA
IDIV4 Divider by 4 consumption 14 mA
LO output buffer
PLO Output level 0 dBm
RLReturn loss Matched to 50 ohms 15 dB
IOUTBUF Current consumption
DIV4 Buff 26 mA
DIV2 Buff 23 mA
Direct output 39 mA
Table 5. Electrical specifications (continued)
Symbol Parameter Condition Min. Typ. Max. Unit
Electrical specifications STW81103
12/53
External VCO
Frequency range 0.625 5.0 GHz
Input level -10 +6 dBm
Current consumption VCO internal buffer 28 mA
PLL miscellaneous
IPLL Current consumption Input buffer, prescaler, digital
dividers, misc. 12 mA
tlock Lockup time(5) (7) 25 kHz PLL bandwidth; within
1 ppm of frequency error 150 μs
1. In order to achieve best phase noise performance 1 V peak level is suggested.
2. The frequency step is related to the PFD input frequency as follows:
- Fstep = FPFD for direct output
- Fstep = FPFD/2 for divided by 2 output
- Fstep = FPFD/4 for divided by 4 output
3. See relationship between ICP and REXT in
Section 5.7: Charge pump
.
4. The level of the spurs may change depending on PFD frequency, charge pump current, selected channel and PLL loop
BW.
5. Guaranteed by design and specification.
6. When setting a specified output frequency, the VCO calibration procedure must be run in order to select the best sub-range
for the VCO covering the desired frequency. Once programmed at the initial temperature T0 inside the operating
temperature range (-40 °C to +85 °C), the synthesizer is able to maintain the lock status only if the temperature drift (in
either direction) is within the limit specified by ΔTLK, provided that the final temperature T1 is still inside the nominal range.
If higher ΔT are required the ”VCO calibration auto-restart“ feature can be enabled, thus allowing to re-start the VCO
calibration procedure automatically when the part loose the lock condition (trigger on lock detector signal).
7. Frequency jump from 2250 to 2400 MHz; it includes the time required by the VCO calibration procedure (7 FPFD cycles with
FPFD=400 kHz).
Table 5. Electrical specifications (continued)
Symbol Parameter Condition Min. Typ. Max. Unit
STW81103 Electrical specifications
13/53
2.5 Phase noise specification
Table 6. Phase noise specification (1)
Parameter Test conditions Min. Typ. Max. Unit
In-band phase noise floor – closed loop(2)
Normalized inband phase noise
floor
ICP=4 mA, PLL BW=50 kHz;
including reference clock contribution
-222 dBc/Hz
Inband phase noise floor
direct output -222+20log(N)+10log(FPFD)dBc/Hz
Inband phase noise floor
divider by 2 -228+20log(N)+10log(FPFD)dBc/Hz
Inband phase noise floor
divider by 4 -234+20log(N)+10log(FPFD)dBc/Hz
PLL integrated phase noise – direct output
Integrated phase noise
100 Hz to 40 MHz
FOUT=4.675 GHz,
FPFD=200 kHz, FSTEP=200 kHz,
PLL BW = 15 kHz, ICP=3 mA
-34.6 dBc
1.5 ° rms
PLL integrated phase noise – divider by 2
Integrated phase noise
100 Hz to 40 MHz
FOUT=2.3376 GHz,
FPFD=400 kHz, FSTEP=200 kHz,
PLL BW=25 kHz, ICP=2 mA
-42.6 dBc
0.6 ° rms
PLL integrated phase noise – divider by 4
Integrated phase noise
100 Hz to 40 MHz
FOUT=1.1688 GHz,
FPFD=800 kHz, FSTEP=200 kHz,
PLL BW=35 kHz, ICP=1.5 mA
-49.5 dBc
0.27 ° rms
VCO A direct (2500 MHz-3050 MHz) – open loop(3)
Phase noise @ 1 kHz -59 dBc/Hz
Phase noise @ 10 kHz -87 dBc/Hz
Phase noise @ 100 kHz -109 dBc/Hz
Phase noise @ 1 MHz -131 dBc/Hz
Phase noise @ 10 MHz -151 dBc/Hz
Phase noise @ 40 MHz -161 dBc/Hz
VCO B direct (4350 MHz-5000 MHz) – open loop(3)
Phase noise @ 1 kHz -54 dBc/Hz
Phase noise @ 10 kHz -82 dBc/Hz
Phase noise @ 100 kHz -105 dBc/Hz
Phase noise @ 1 MHz -127 dBc/Hz
Phase noise @ 10 MHz -147 dBc/Hz
Phase noise @ 40 MHz -157 dBc/Hz
Electrical specifications STW81103
14/53
An evaluation kit is available upon request, including a powerful simulation tool
(STWPLLSim) that allows a very accurate estimation of the device’s phase noise according
to the desired project parameters (VCO frequency, selected output stage, reference clock,
frequency step, and so on); refer to
Section 8: Application information
for more details.
VCO A with divider by 2 (1250 MHz-1525 MHz) – open loop(3)
Phase noise @ 1 kHz -65 dBc/Hz
Phase noise @ 10 kHz -93 dBc/Hz
Phase noise @ 100 kHz -115 dBc/Hz
Phase noise @ 1 MHz -137 dBc/Hz
Phase noise @ 10 MHz -153 dBc/Hz
Phase noise floor @ 40 MHz -155 dBc/Hz
VCO B with divider by 2 (2175 MHz-2500 MHz) – open loop(3)
Phase noise @ 1 kHz -60 dBc/Hz
Phase noise @ 10 kHz -88 dBc/Hz
Phase noise @ 100 kHz -111 dBc/Hz
Phase noise @ 1 MHz -132 dBc/Hz
Phase noise @ 10 MHz -150 dBc/Hz
Phase noise floor @ 40 MHz -154 dBc/Hz
VCO A with divider by 4 (625 MHz-762.5 MHz) – open loop(3)
Phase noise @ 1 kHz -71 dBc/Hz
Phase noise @ 10 kHz -99 dBc/Hz
Phase noise @ 100 kHz -121 dBc/Hz
Phase noise @ 1 MHz -142 dBc/Hz
Phase noise @ 10 MHz -154 dBc/Hz
Phase noise floor @ 40 MHz -155 dBc/Hz
VCO B with divider by 4 (1087.5 MHz-1250 MHz) – open loop(3)
Phase noise @ 1 kHz -66 dBc/Hz
Phase noise @ 10 kHz -94 dBc/Hz
Phase noise @ 100 kHz -117 dBc/Hz
Phase noise @ 1 MHz -138 dBc/Hz
Phase noise @ 10 MHz -153 dBc/Hz
Phase noise floor @ 40 MHz -154 dBc/Hz
1. Phase Noise SSB. VCO amplitude setting to value [11]. All closed-loop performances are specified using a reference clock
signal at 76.8 MHz with a phase noise of -135 dBc/Hz @1 kHz offset, -145dBc/Hz @10kHz offset and -149.5 dBc/Hz of
noise floor.
2. Normalized PN = Measured PN – 20log(N) – 10log(FPFD), where N is the VCO divider ratio (N=B*P+A) and FPFD is the
comparison frequency at the PFD input.
3. Typical phase noise at centre band frequency.
Table 6. Phase noise specification (1) (continued)
Parameter Test conditions Min. Typ. Max. Unit
STW81103 Typical performance characteristics
15/53
3 Typical performance characteristics
Phase noise is measured with the Agilent E5052A Signal Source Analyzer. All closed-loop
measurements are done with FSTEP=200 kHz, with the FPFD and charge pump current
properly set. The loop filter configuration is depicted in
Figure 36: Typical application
diagram
, and the reference clock signal is at 76.8 MHz with a phase noise of -135 dBc/Hz
@1 kHz offset, -145 dBc/Hz @10 kHz offset and -149.5 dBc/Hz of noise floor.
Figure 3. VCO A (direct output) open loop
phase noise
Figure 4. VCO B (direct output) open loop
phase noise
Figure 5. VCO A (direct output) closed loop
phase noise at 2.775 GHz
(FSTEP=200 kHz; FPFD=200 kHz;
ICP=2 mA)
Figure 6. VCO B (direct output) closed loop
phase noise at 4.675 GHz
(FSTEP=200 kHz; FPFD=200 kHz;
ICP=3 mA)
1.0° rms
1.5° rms
Typical performance characteristics STW81103
16/53
Figure 7. VCO A (div. by 2 output) closed
loop phase noise at 1.3876 GHz
(FSTEP=200 kHz; FPFD=400 kHz;
ICP=1.5 mA)
Figure 8. VCO B (div. by 2 output) closed
loop phase noise at 2.3376 GHz
(FSTEP=200 kHz; FPFD=400 kHz;
ICP=2 mA)
0
.
4
°
rm
s
0
.6
°
rm
s
Figure 9. VCO A (div. by 4 output) closed
loop phase noise at 693.8 MHz
(FSTEP=200 kHz; FPFD=800 kHz;
ICP=1 mA)
Figure 10. VCO B (div. by 4 output) closed
loop phase noise at 1168.8 MHz
(FSTEP=200 kHz; FPFD=800 kHz;
ICP=1.5 mA)
0
.19
°
rm
s
0
.2
7
°
rm
s
STW81103 Typical performance characteristics
17/53
Figure 11. PFD frequency spurs (direct
output; FPFD=200 kHz)
Figure 12. PFD frequency spurs (div. by 2
output; FPFD=400 kHz)
-76 dBc
@200KHz
-84 dBc
@400KHz
Figure 13. PFD frequency spurs (div. by 4
output; FPFD=800 kHz)
Figure 14. Settling time (final frequency=2.4
GHz; FPFD=400 kHz; ICP=2.5 mA)
< -90 dBc
@800KHz
General description STW81103
18/53
4 General description
Figure 1: Block diagram
shows the separate blocks that, when integrated, form an Integer-N
PLL frequency synthesizer.
The STW81103 consists of two internal low-noise VCOs with buffer blocks, a divider by 2, a
divider by 4, a low-noise PFD (phase frequency detector), a precise charge pump, a 10-bit
programmable reference divider, two programmable counters and a programmable dual-
modulus prescaler. The 5-bit A-counter and 12-bit B-counter, in conjunction with the dual-
modulus prescaler P/P+1 (16/17 or 19/20), implement an N integer divider, where N = B*P
+A. The division ratio of both reference and VCO dividers is controlled through the selected
digital interface (I2C bus or SPI).
The digital interface type is selected through the proper hardware connection of pin
DBUS_SEL (0 V for I2C bus, 3.3 V for SPI).
All devices operate with a power supply of 3.3 V, and can be powered down when not in use.
STW81103 Circuit description
19/53
5 Circuit description
5.1 Reference input
stage
The reference input stage is shown in
Figure 15
. The resistor network feeds a DC bias at the
Fref input, while the inverter used as the frequency reference buffer is AC coupled.
Figure 15. Reference frequency input buffer
5.2 Reference divider
The 10-bit programmable reference counter allows division of the input reference frequency
to produce the input clock to the PFD. The division ratio is programmed through the digital
interface.
5.3 Prescaler
The dual-modulus prescaler P/P+1 takes the CML clock from the VCO buffer and divides it
down to a manageable frequency for the CMOS A and B counters. The modulus P is
programmable and can be set to 16 or 19. The prescaler is based on a synchronous 4/5
core whose division ratio depends on the state of the modulus input.
INV BUF
VDD
Fref
Power Down
Circuit description STW81103
20/53
5.4 A and B counters
The 5-bit A-counter and 12-bit B-counter, in conjunction with the selected dual modulus
(16/17 or 19/20) prescaler, allow the generation of output frequencies that are spaced only
by the reference frequency divided by the reference division ratio. The division ratio and the
VCO output frequency are given by the following formulas:
N = B x P + A
where
FVCO: output frequency of VCO
P: modulus of dual modulus prescaler (16 or 19 selected through the digital interface)
B: division ratio of the main counter
A: division ratio of the swallow counter
Fref: input reference frequency
R: division ratio of the reference counter
N: division ratio of the PLL
For the VCO divider to work correctly, B absolutely must be greater than A, which can take
any value ranging from 0 to 31. The value range of N is either from 256 to 65551 (if P=16) or
from 361 to 77836 (P=19).
Figure 16. VCO divider diagram
FVCO
BPA+×()
R
------------------------------ Fref
×=
5-bit 12-bit
To PFD
modulus
VCOBUF+
VCOBUF-
Prescaler
16/17 or 19/20
B-counter
A-counter