MAX1875AEEG-T - Maxim Integrated Products, Inc.

General Description

The MAX1858A/MAX1875A/MAX1876A dual, synchro-

nized, step-down controllers generate two outputs from

input supplies ranging from 4.5V to 23V. Each output is

adjustable from sub-1V to 18V and supports loads of 10A

or higher. Input voltage ripple and total RMS input ripple

current are reduced by synchronized 180° out-of-phase

operation.

The switching frequency is adjustable from 100kHz to

600kHz with an external resistor. Alternatively, the con-

troller can be synchronized to an external clock gener-

ated by another MAX1858A/MAX1875A/MAX1876A or a

system clock. One MAX1858A/MAX1875A/MAX1876A

can be set to generate an in-phase, or 90° out-of-

phase, clock signal for synchronization with additional

controllers. This allows two controllers to operate either

as an interleaved two- or four-phase system with each

output shifted by 90°. The MAX1858A/MAX1875A/

MAX1876A feature soft-start. The MAX1858A also fea-

tures first-on/last-off power sequencing and soft-stop.

The MAX1858A/MAX1875A/MAX1876A eliminate the

need for current-sense resistors by utilizing the low-side

MOSFET’s on-resistance as a current-sense element.

This protects the DC-DC components from damage dur-

ing output-overload conditions or output short-circuit

faults without requiring a current-sense resistor.

Adjustable foldback current limit reduces power dissipa-

tion during short-circuit conditions. The MAX1858A/

MAX1876A include a power-on reset (POR) output to sig-

nal the system when both outputs reach regulation.

The MAX1858A/MAX1875A/MAX1876A ensure that the

output voltage does not swing negative when the input

power is removed or when EN is driven low. The

MAX1875A/MAX1876A also allow prebias startup with-

out discharging the output.

The MAX1858A/MAX1875A/MAX1876A are available in a

24-pin QSOP package. Use the MAX1875 evaluation kit

or the MAX1858 evaluation kit to evaluate the

MAX1858A/MAX1875A/MAX1876A.

Applications

Network Power Supplies

Telecom Power Supplies

DSP, ASIC, and FPGA Power Supplies

Set-Top Boxes

Broadband Routers

Servers

Desknote Computers

Features

♦4.5V to 23V Input Supply Range

♦0 to 18V Output Voltage Range (Up to 10A)

♦Adjustable Lossless Foldback Current Limit

♦Adjustable 100kHz to 600kHz Switching

Frequency

♦Optional Synchronization

♦Clock Output for Master/Slave Synchronization

♦4 x 90° Out-of-Phase Step-Down Converters

(Using Two Controllers, Figure 7)

♦Prebias Startup (MAX1875A/MAX1876A)

♦Power Sequencing (MAX1858A)

♦RST Output with 140ms Minimum Delay

(MAX1858A/MAX1876A)

♦Fixed-Frequency Pulse-Width Modulation (PWM)

Operation

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

________________________________________________________________ Maxim Integrated Products 1

LX2

DH2

BST2OSC

ILIM2

FB2

COMP2

TOP VIEW

DL2

PGND

DL1CKO

GND

REF

V+

BST1

DH1

LX1

COMP1

FB1

ILIM1

SYNC

QSOP

MAX1858A

MAX1875A

MAX1876A

RST (N.C.)

() ARE FOR THE MAX1875A ONLY

Pin Configuration

Ordering Information

19-2966; Rev 0; 10/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN-PACKAGE

MAX1858AEEG -40°C to +85°C 24 QSOP

MAX1875AEEG -40°C to +85°C 24 QSOP

MAX1876AEEG -40°C to +85°C 24 QSOP

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

V+ to GND ..............................................................-0.3V to +25V

PGND to GND .......................................................-0.3V to +0.3V

VLto GND ..................-0.3V to the lower of +6V and (V+ + 0.3V)

BST1, BST2 to GND ...............................................-0.3V to +30V

LX1 to BST1..............................................................-6V to +0.3V

LX2 to BST2..............................................................-6V to +0.3V

DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V)

DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V)

DL1, DL2 to PGND........................................-0.3V to (VL+ 0.3V)

CKO, REF, OSC, ILIM1, ILIM2,

COMP1, COMP2 to GND ..........................-0.3V to (VL+ 0.3V)

FB1, FB2, RST, SYNC, EN to GND...........................-0.3V to +6V

VL to GND Short Circuit .............................................Continuous

REF to GND Short Circuit ...........................................Continuous

Continuous Power Dissipation (TA= +70°C)

24-Pin QSOP (derate 9.4mW/°C above +70°C)...........762mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

ELECTRICAL CHARACTERISTICS

(V+ = 12V, EN = ILIM_ = VL, SYNC = GND, IVL = 0mA, PGND = GND, CREF = 0.22µF, CVL = 4.7µF (ceramic), ROSC = 60kΩ,

compensation components for COMP_ are from Figure 1, TA= -40°C to +85°C (Note 1), unless otherwise noted.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

GENERAL

(Note 2) 4.5 23.0

V+ Operating Range VL = V+ (Note 2) 4.5 5.5

V+ Operating Supply Current VL unloaded, no MOSFETs connected 3.5 6 mA

V+ Standby Supply Current EN = LX_ = FB_ = 0V 0.3 0.6 mA

Thermal Shutdown Rising temperature, typical hysteresis = 10°C +160 °C

ILIM_ = VL 75 100 125

RILIM_ = 100kΩ 32 50 62

Current-Limit Threshold PGND - LX_

RILIM_ = 600kΩ 225 300 375

VL REGULATOR

Output Voltage 5.5V < V+ < 23V, 1mA < ILOAD < 50mA 4.75 5 5.25 V

VL Undervoltage Lockout Rising

Trip Level 4.1 4.2 4.3 V

VL Undervoltage Lockout

Hysteresis (Note 3) 100 mV

REFERENCE

Output Voltage IREF = 0µA 1.98 2.00 2.02 V

Reference Load Regulation 0µA < IREF < 50µA 0 4 10 mV

SOFT-START

Digital Ramp Period Internal 6-bit DAC for one converter to ramp from 0V to

full scale (Note 4) 1024

DC-DC

clocks

Soft-Start Steps 64 Steps

FREQUENCY

0°C to +85°C 84 100 115

Low End of Range ROSC = 60kΩ -40°C to +85°C 80 100 120

kHz

High End of Range ROSC = 10kΩ 540 600 660 kHz

DH_ Minimum Off-Time ROSC = 10kΩ 250 303 ns

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(V+ = 12V, EN = ILIM_ = VL, SYNC = GND, IVL = 0mA, PGND = GND, CREF = 0.22µF, CVL = 4.7µF (ceramic), ROSC = 60kΩ,

compensation components for COMP_ are from Figure 1, TA= -40°C to +85°C (Note 1), unless otherwise noted.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

SYNC Range Switching frequency must be set to half of the SYNC

frequency 200 1200 kHz

High 100

SYNC Input Pulse Width (Note 4) Low 100

SYNC Rise/Fall Time (Note 4) 100 ns

ERROR AMPLIFIER

FB_ Input Bias Current 250 nA

0°C to +85°C 0.985 1.00 1.015

FB_ Input Voltage Set Point -40°C to +85°C 0.98 1.00 1.02

0°C to +85°C 1.25 1.8 2.70

FB_ to COMP_ Transconductance -40°C to +85°C 1.2 1.8 2.9

DRIVERS

DL_, DH_ Break-Before-Make Time CLOAD = 5nF 30 ns

Low 1.5 2.5

DH_ On-Resistance High 3 5

Ω

Low 0.6 1.5

DL_ On-Resistance High 3 5

Ω

LOGIC INPUTS (EN, SYNC)

Input Low Level Typical 15% hysteresis, VL = 4.5V 0.8 V

Input High Level VL = 5.5V 2.4 V

Input High/Low Bias Current VEN = 0 or 5.5V -1 +0.1 +1 µA

LOGIC OUTPUTS (CKO)

Output Low Level VL = 5V, sinking 5mA 0.4 V

Output High Level VL = 5V, sourcing 5mA 4.0 V

COMP_

Pulldown Resistance During

Shutdown and Current Limit 17 Ω

RST OUTPUT (MAX1858A/MAX1876A ONLY)

Output-Voltage Trip Level Both FBs must be over this to allow the reset timer to

start; there is no hysteresis 0.87 0.9 0.93 V

VL = 5V, sinking 3.2mA 0.4

Output Low Level VL = 1V, sinking 0.4mA 0.3

Output Leakage V+ = VL = 5V, V RST = 5.5V, VFB = 1V 1 µA

Reset Timeout Period VFB_ = 1V 140 315 560 ms

FB_ to Reset Delay FB_ overdrive from 1V to 0.85V 4 µs

Note 1: Specifications to -40°C are guaranteed by design and not production tested.

Note 2: Operating supply range is guaranteed by VLline regulation test. Connect V+ to VLfor 5V operation.

Note 3: When VLfalls and UVLO is tripped, the device is latched and VLmust be discharged below 2.5V before normal operation

can resume.

Note 4: Guaranteed by design and not production tested.

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

4 _______________________________________________________________________________________

Typical Operating Characteristics

(Circuit of Figure 1, VIN = 12V, TA = +25°C, unless otherwise noted.)

EFFICIENCY vs. LOAD

MAX1858A/75A/76A toc01

LOAD (A)

EFFICIENCY (%)

101

100

0.1 100

OUT2

OUT1

OUTPUT VOLTAGE ACCURACY vs. LOAD

MAX1858A/75A/76A toc02

LOAD (A)

OUTPUT VOLTAGE ACCURACY (%)

105

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-1.0

015

OUT2

OUT1

VL VOLTAGE ACCURACY

vs. LOAD CURRENT

MAX1858A/75A/76A toc03

LOAD CURRENT (mA)

VL VOLTAGE ACCURACY

10050

-1.5

-1.0

-0.5

0.5

-2.0

0150

SWITCHING FREQUENCY vs. ROSC

MAX1858A/75A/76A toc04

ROSC (kΩ)

SWITCHING FREQUENCY (kHz)

5040302010

100

200

300

400

500

600

060

LOAD TRANSIENT RESPONSE (OUTPUT 1)

MAX1858A/75A/76A toc05

10µs/div

IOUT1

10A

VOUT1

50mV/div

AC-COUPLED

VOUT2

50mV/div

AC-COUPLED

LOAD TRANSIENT RESPONSE (OUTPUT 2)

MAX1858A/75A/76A toc06

10µs/div

IOUT2

10A

VOUT1

50mV/div

AC-COUPLED

VOUT2

50mV/div

AC-COUPLED

SOFT-START AND SOFT-STOP WAVEFORM

(MAX1858A ONLY)

MAX1858A/75A/76A toc07

2ms/div

VOUT1

1V/div

IOUT1 = 300mA

VOUT2

1V/div

IOUT2 = 300mA

10V

SOFT-START AND SOFT-STOP WAVEFORM

(MAX1858A ONLY)

MAX1858A/75A/76A toc08

2ms/div

VOUT1

1V/div

IOUT1 = 300mA

VOUT2

1V/div

IOUT2 = 300mA

EN PULLED HIGH BEFORE VOUT1 REACHES 0V.

START AND STOP WAVEFORM

(MAX1875A/MAX1876A ONLY)

MAX1858A/75A/76A toc09

2ms/div

10V

VOUT1

1V/div

IOUT1 = 300mA

VOUT2

1V/div

IOUT2 = 300mA

PREBIAS STARTUP

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

_______________________________________________________________________________________ 5

INPUT POWER REMOVAL

MAX1858A/75A/76A toc10

5ms/div

VIN

10V/div

VOUT1

1V/div

IOUT1 = 300mA

VOUT2

1V/div

IOUT2 = 300mA

CKO OUTPUT WAVEFORM

MAX1858A/75A/76A toc14

400ns/div

VOUT1

10mV/div

AC-COUPLED

VCK0

VLX1

10V

SYNC = GND

CKO OUTPUT WAVEFORM

MAX1858A/75A/76A toc15

400ns/div

VOUT1

10mV/div

VCK0

VLX1

10V

SYNC = VL

Typical Operating Characteristics (continued)

(Circuit of Figure 1, VIN = 12V, TA = +25°C, unless otherwise noted.)

SHORT-CIRCUIT CURRENT FOLDBACK

AND RECOVERY

MAX1858A/75A/76A toc16

4ms/div

IOUT1 = 10A (5A/div)

VOUT1 = 1.8V (1V/div)

VOUT2 = 2.5V (1V/div)

IOUT2 = 10A (5A/div)

VOUT2

SHORT

RESET TIMEOUT

(MAX1858A/MAX1876A ONLY)

MAX1858A/75A/76A toc11

100ms/div, 5V/div

VOUT1

VOUT2

VRST

OUT-OF-PHASE WAVEFORM

MAX1858A/75A/76A toc12

1µs/div

VOUT1

20mV/div

VOUT2

20mV/div

12V

VLX1

VLX2

12V

EXTERNALLY SYNCHRONIZED

SWITCHING WAVEFORM

MAX1858A/75A/76A toc13

400ns/div

VOUT1

10mV/div

AC-COUPLED

VSYNC

VCK0

VLX1

10V

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

6 _______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1 COMP2

Compensation Pin for Regulator 2 (REG2). Compensate REG2’s control loop by connecting a series resistor

(RCOMP2) and capacitor (CCOMP2A) to GND in parallel with a second compensation capacitor (CCOMP2B) as

shown in Figure 1.

2 FB2

Feedback Input for Regulator 2 (REG2). Connect FB2 to a resistive divider between REG2’s output and GND to

adjust the output voltage between 1V and 18V. To set the output voltage below 1V, connect FB2 to a resistive

voltage-divider from REF to REG2’s output. See the Setting the Output Voltage section.

3 ILIM2

Current-Limit Adjustment for Regulator 2 (REG2). The PGND–LX2 current-limit threshold defaults to 100mV if

ILIM2 is connected to VL. Connect a resistor (RILIM2) from ILIM2 to GND to adjust the REG2’s current-limit

threshold (VITH2) from 50mV (RILIM2 = 100kΩ) to 300mV (RILIM2 = 600kΩ). See the Setting the Valley Current

Limit section.

4 OSC

Oscillator Frequency Set Input. Connect a resistor from OSC to GND (ROSC) to set the switching frequency from

100kHz (ROSC = 60kΩ) to 600kHz (ROSC = 10kΩ). The controller still requires ROSC when an external clock is

connected to SYNC. When using an external clock, select ROSC as described above, and set the external clock

frequency to twice the desired switching frequency.

5 V+ Input Supply Voltage. 4.5V to 23V.

6 REF 2V Reference Output. Bypass to GND with a 0.22µF or greater ceramic capacitor.

7 GND Analog Ground

8 CKO Clock Output. Clock output for external 2- or 4-phase synchronization (see the Clock Synchronization (SYNC,

CKO) section).

9 SYNC

Synchronization Input or Clock Output Selection Input. SYNC has three operating modes. Connect SYNC to a

200kHz to 1200kHz clock for external synchronization. Connect SYNC to GND for 2-phase operation as a master

controller. Connect SYNC to VL for 4-phase operation as a master controller (see the Clock Synchronization

(SYNC, CKO) section).

10 ILIM1

Current-Limit Adjustment for Regulator 1 (REG1). The PGND–LX1 current-limit threshold defaults to 100mV if

ILIM1 is connected to VL. Connect a resistor (RILIM1) from ILIM1 to GND to adjust REG1’s current-limit threshold

(VITH1) from 50mV (RILIM1 = 100kΩ) to 300mV (RILIM1 = 600kΩ). See the Setting the Valley Current Limit section.

11 FB1

Feedback Input for Regulator 1 (REG1). Connect FB1 to a resistive divider between REG1’s output and GND to

adjust the output voltage between 1V and 18V. To set the output voltage below 1V, connect FB1 to a resistive

voltage-divider from REF and REG1’s output. See the Setting the Output Voltage section.

12 COMP1

Compensation Pin for Regulator 1 (REG1). Compensate REG1’s control loop by connecting a series resistor

(RCOMP1) and capacitor (CCOMP1A) to GND in parallel with a second compensation capacitor (CCOMP1B) as

shown in Figure 1.

RST

Open-Drain Reset Output (MAX1858A/MAX1876A Only). RST is low when either output voltage is more than 10%

below its regulation point. After soft-start is completed and both outputs exceed 90% of their nominal output

voltage (VFB_ > 0.9V), RST becomes high impedance after a 140ms delay and remains high impedance as long

as both outputs maintain regulation. Connect a resistor between RST and the logic supply for logic-level

voltages.

N.C. Connect to GND or leave unconnected for the MAX1875A.

Detailed Description

DC-DC PWM Controller

The MAX1858A/MAX1875A/MAX1876A step-down con-

verters use a PWM voltage-mode control scheme (Figure

2) for each out-of-phase controller. The controller gener-

ates the clock signal by dividing down the internal oscil-

lator or SYNC input when driven by an external clock, so

each controller’s switching frequency equals half the

oscillator frequency (fSW = fOSC/2). An internal transcon-

ductance error amplifier produces an integrated error

voltage at the COMP pin, providing high DC accuracy.

The voltage at COMP sets the duty cycle using a PWM

comparator and a ramp generator. At each rising edge

of the clock, REG1’s high-side N-channel MOSFET turns

on and remains on until either the appropriate duty cycle

or until the maximum duty cycle is reached. REG2 oper-

ates out-of-phase, so the second high-side MOSFET

turns on at each falling edge of the clock. During each

high-side MOSFET’s on-time, the associated inductor

current ramps up.

During the second-half of the switching cycle, the high-

side MOSFET turns off and the low-side N-channel

MOSFET turns on. Now the inductor releases the stored

energy as its current ramps down, providing current to

the output. Under overload conditions, when the induc-

tor current exceeds the selected valley current limit (see

the Current-Limit Circuit (ILIM_) section), the high-side

MOSFET does not turn on at the appropriate clock edge

and the low-side MOSFET remains on to let the inductor

current ramp down.

Synchronized Out-of-Phase Operation

The two independent regulators in the MAX1858A/

MAX1875A/MAX1876A operate 180° out-of-phase to

reduce input filtering requirements, reduce electromag-

netic interference (EMI), and improve efficiency. This

effectively lowers component cost and saves board

space, making the MAX1858A/MAX1875A/MAX1876A

ideal for cost-sensitive applications.

Dual-switching regulators typically operate both

controllers in-phase, and turn on both high-side

MOSFETs at the same time. The input capacitor must

then support the instantaneous current requirements of

both controllers simultaneously, resulting in increased

ripple voltage and current when compared to a single

switching regulator. The higher RMS ripple current

lowers efficiency due to power loss associated with the

input capacitor’s effective series resistance (ESR). This

typically requires more low-ESR input capacitors in

parallel to minimize input voltage ripple and ESR-related

losses, or to meet the necessary ripple-current rating.

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

_______________________________________________________________________________________ 7

Pin Description (continued)

PIN NAME FUNCTION

14 DH1 High-Side Gate-Driver Output for Regulator 1 (REG1). DH1 swings from LX1 to BST1. DH1 is low during UVLO.

15 LX1 External Inductor Connection for Regulator 1 (REG1). Connect LX1 to the switched side of the inductor. LX1

serves as the lower supply rail for the DH1 high-side gate driver.

16 BST1 Boost Flying-Capacitor Connection for Regulator 1 (REG1). Connect BST1 to an external ceramic capacitor and

diode according to Figure 1.

17 DL1 Low-Side Gate-Driver Output for Regulator 1 (REG1). DL1 swings from PGND to VL. DL1 is low during UVLO.

18 PGND Power Ground

19 VLInternal 5V Linear-Regulator Output. Supplies the regulators and powers the low-side gate drivers and external

boost circuitry for the high-side gate drivers.

20 DL2 Low-Side Gate-Driver Output for Regulator 2 (REG2). DL2 swings from PGND to VL. DL2 is low during UVLO.

21 BST2 Boost Flying-Capacitor Connection for Regulator 2 (REG2). Connect BST2 to an external ceramic capacitor and

diode according to Figure 1.

22 LX2 External Inductor Connection for Regulator 2 (REG2). Connect LX2 to the switched side of the inductor. LX2

serves as the lower supply rail for the DH2 high-side gate driver.

23 DH2 High-Side Gate-Driver Output for Regulator 2 (REG2). DH2 swings from LX2 to BST2. DH2 is low during UVLO.

24 EN Active-High Enable Input. A logic low shuts down both controllers. Connect to VL for always-on operation.

MAX1858A/MAX1875A/MAX1876A

With dual, synchronized, out-of-phase operation, the

MAX1858A/MAX1875A/MAX1876As’ high-side MOSFETs

turn on 180° out-of-phase. The instantaneous input cur-

rent peaks of both regulators no longer overlap, resulting

in reduced RMS ripple current and input voltage ripple.

This reduces the required input capacitor ripple-current

rating, allowing fewer or less expensive capacitors, and

reduces shielding requirements for EMI. The Out-of-

Phase Waveforms in the Typical Operating Charac-

teristics demonstrate synchronized 180° out-of-phase

operation.

Internal 5V Linear Regulator (VL)

All MAX1858A/MAX1875A/MAX1876A functions are

internally powered from an on-chip, low-dropout 5V

regulator. The maximum regulator input voltage (V+) is

23V. Bypass the regulator’s output (VL) with a 4.7µF

ceramic capacitor to PGND. The VLdropout voltage is

typically 500mV, so when V+ is greater than 5.5V, VLis

typically 5V. The MAX1858A/MAX1875A/MAX1876A

also employs an undervoltage lockout circuit that dis-

ables both regulators when VLfalls below 4.2V. VL

should also be bypassed to GND with a 0.1µF capaci-

tor. When VLfalls and UVLO is tripped, the device is

latched and VLmust be discharged below 2.5V before

normal operation can resume.

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

8 _______________________________________________________________________________________

V+

BST1

DH1

LX1

DL1

BST2

DH2

LX2

DL2

FB1

COMP1

*IRF7811W

**OPTIONAL

FB2

COMP2

PGND

REF

GND

OSC

SYNC

CKO

ILIM1

ILIM2EN

OFF

RESET OUTPUT

CLOCK OUTPUT

RST (MAX1858A/

MAX1876A ONLY)

MAX1858A

MAX1875A

MAX1876A

CV+

0.22µF

CIN1

2 × 10µF

COUT1

4 × 220µF

NH1*

NL1*

1.1µH

OUTPUT1

VOUT = 1.8V

VIN

6V - 23V

CBST1

0.1µF

R1A

8.06kΩ

R1B

10kΩ

RCOMP1

5.9kΩ

CCOMP1A

0.01µF

CCOMP1B

100pF

CREF

0.22µF

CCOMP2A

6800pF

CCOMP2B

100pF

RCOMP2

8.2kΩR2B

10kΩ

96.5kΩ

140kΩ

R2A

15kΩ

4.7Ω

RV+

4.7Ω

NL2* **

NH2* L2

1.1µH

CMPSH-3A

COUT2

4 × 220µF

CIN2

2 × 10µF

OUTPUT2

VOUT = 2.5V

CBST2

0.1µF

CVL

4.7µF

0.1µF

118kΩ

CMSSH-3

84.5kΩ

CMSSH-3

Figure 1. Standard 600kHz Application Circuit

The internal VLlinear regulator can source over 50mA to

supply the IC, power the low-side gate driver, charge the

external boost capacitor, and supply small external

loads. When driving large FETs, little or no regulator cur-

rent may be available for external loads.

For example, when switched at 600kHz, a single large

FET with 18nC total gate charge requires 18nC ✕600kHz

= 11mA. To drive larger MOSFETs, or deliver larger

loads, connect VLto an external power supply from 4.5V

to 5.5V.

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

_______________________________________________________________________________________ 9

CONVERTER 1

ILIM1

DL1

PGND

LX1

DH1

BST1

VL - 0.5V

FB1

COMP1

SOFT-START DAC

(SEQUENCING—

MAX1858A ONLY)

OSCILLATOR

OSC

1VP-P

SYNC

CK0

V+

5V LINEAR

REGULATOR

GND

REF

DL2

LX2

DH2

BST2

ILIM2FB2

COMP2

CONVERTER 2

RESET

UVLO

AND

SHUTDOWN

VREF

2.0V

MAX1858A

MAX1875A

MAX1876A

RST

(MAX1858A/

MAX1876A ONLY)

VREF

5µA

Figure 2. Functional Diagram

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

10 ______________________________________________________________________________________

DH_

DL_

MAX1875A/MAX1876A POWER-ON-OFF SEQUENCING DEFINITIONS

SYMBOL DEFINITION

SS_

VOUT_

UVLO ABCDEFGHI JKL

Undervoltage lockout trip level is provided in the Electrical Characteristics table.

Internal 5V Linear-Regulator Output

Active-High Enable Input

Output Voltage

Internal Soft-Start Input Signal into Error Amplifier

High-Side Gate-Driver Output

Low-Side Gate-Driver Output

VL rising while below the UVLO threshold. EN is low.

VL is greater than the UVLO threshold. EN is low.

EN is pulled high.

Normal operation

VL enters UVLO.

VL exits UVLO.

Resumes normal operation

EN is pulled low.

EN is pulled high.

Resumes normal operation

VL drops below UVLO threshold while EN is high.

Resumes normal operation

UVLO is activated and DL_ is latched low.

Exiting UVLO: DL_ remains latched low until the first fall of DH_ is detected.

DL_ is low after EN is pulled low.

UVLO

VOUT_

SS_

DH_

DL_

Figure 3. MAX1875A/MAX1876A Detailed Power-On-Off Sequencing

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

______________________________________________________________________________________ 11

VOUT1

SS1

VOUT2

SS2

DH1

DL1

DH2

DL2

UVLO ABCDEFGHIJKM

MAX1858A POWER-ON-OFF SEQUENCING DEFINITIONS

SYMBOL DEFINITION

VOUT1

SS1

VOUT2

SS2

DH1

DL1

DH2

DL2

Internal 5V Linear-Regulator Output

Active-High Enable Input

Regulator 1 Output Voltage

Regulator 1: Internal Soft-Start Input Signal into Error Amplifier

Regulator 2 Output Voltage

Regulator 2: Internal Soft-Start Input Signal into Error Amplifier

Regulator 1: High-Side Gate-Driver Output

Regulator 1: Low-Side Gate-Driver Output

Regulator 2: High-Side Gate-Driver Output

Regulator 2: Low-Side Gate-Driver Output

VL rising while below the UVLO threshold. EN is low.

VL is greater than the UVLO threshold. EN is low.

SYMBOL DEFINITION

Normal operation

VL enters UVLO.

VL exits UVLO.

UVLO Undervoltage threshold value is provided in the

Electrical Characteristics table.

EN is pulled high. DH1 and DL1 start switching. DH2 and

DL2 are off.

Resumes normal operation. DH1 and DL1 start switching.

DH2 and DL2 are off.

EN is pulled low and then high.

VOUT1 must reach 0V before restarting due to the cycling

of the enable in region H (above).

VOUT1 recovers.

VOUT2 recovers.

VL enters UVLO before VOUT2 fully recovers.

VL exits UVLO.

UVLO latches DL_ low.

Exiting UVLO: DL_ remains latched low until the first fall

of DH_ is detected.

DL_ is high after EN is pulled low and soft-stop is complete.

Figure 4. MAX1858A Detailed Power-On-Off Sequencing

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

12 ______________________________________________________________________________________

High-Side Gate-Drive Supply (BST_)

Gate-drive voltages for the high-side N-channel switch-

es are generated by the flying-capacitor boost circuits

(Figure 5). A boost capacitor (connected from BST_ to

LX_) provides power to the high-side MOSFET driver.

On startup, the synchronous rectifier (low-side MOSFET)

forces LX_ to ground and charges the boost capacitor to

5V. On the second half-cycle, after the low-side MOSFET

turns off, the high-side MOSFET is turned on by closing

an internal switch between BST_ and DH_. This provides

the necessary gate-to-source voltage to turn on the high-

side switch, an action that boosts the 5V gate-drive

signal above VIN. The current required to drive the high-

side MOSFET gates (fSWITCH ✕ QG) is ultimately drawn

from VL.

MOSFET Gate Drivers (DH_, DL_)

The DH and DL drivers are optimized for driving moder-

ate-size N-channel high-side and larger low-side power

MOSFETs. This is consistent with the low duty factor

seen with large VIN - VOUT differential. The DL_ low-side

drive waveform is always the complement of the DH_

high-side drive waveform (with controlled dead time to

prevent cross-conduction or “shoot-through”). An adap-

tive dead-time circuit monitors the DL_ output and pre-

vents the high-side FET from turning on until DL_ is fully

off. There must be a low-resistance, low-inductance path

from the DL_ driver to the MOSFET gate in order for the

adaptive dead-time circuit to work properly. Otherwise,

the sense circuitry in the MAX1858A/MAX1875A/

MAX1876A interprets the MOSFET gate as “off” while

there is actually charge still left on the gate. Use very

short, wide traces (50mils to 100mils wide if the MOSFET

is 1in from the device). The dead time at the DH-off edge

is determined by a fixed 30ns internal delay.

Synchronous rectification reduces conduction losses in

the rectifier by replacing the normal low-side Schottky

catch diode with a low-resistance MOSFET switch.

Additionally, the MAX1858A/MAX1875A/MAX1876A use

the synchronous rectifier to ensure proper startup of the

boost gate-driver circuit and to provide the current-limit

signal.

The internal pulldown transistor that drives DL_ low is

robust, with a 0.5Ω(typ) on-resistance. This low on-

resistance helps prevent DL_ from being pulled up dur-

ing the fast rise time of the LX_ node, due to capacitive

coupling from the drain to the gate of the low-side syn-

chronous-rectifier MOSFET. However, for high-current

applications, some combinations of high- and low-side

FETs can cause excessive gate-drain coupling, leading

to poor efficiency, EMI, and shoot-through currents.

This can be remedied by adding a resistor (typically

less than 5Ω) in series with BST_, which increases the

turn-on time of the high-side FET without degrading the

turn-off time (Figure 5).

Current-Limit Circuit (ILIM_)

The current-limit circuit employs a “valley” current-sens-

ing algorithm that uses the on-resistance of the low-side

MOSFET as a current-sensing element. If the current-

sense signal is above the current-limit threshold, the

MAX1858A/MAX1875A/MAX1876A do not initiate a new

cycle (Figure 6). Since valley current sensing is

employed, the actual peak current is greater than the

current-limit threshold by an amount equal to the induc-

tor ripple current. Therefore, the exact current-limit char-

acteristic and maximum load capability are a function of

the low-side MOSFET’s on-resistance, current-limit

threshold, inductor value, and input voltage. The reward

for this uncertainty is robust, lossless overcurrent sens-

ing that does not require costly sense resistors.

BST_

DH_

LX_

4.7Ω

INPUT

(VIN)

MAX1875A

Figure 5. Reducing the Switching-Node Rise Time

INDUCTOR CURRENT

ILIMIT

ILOAD

0 TIME

-IPEAK

Figure 6. “Valley” Current-Limit Threshold Point

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

______________________________________________________________________________________ 13

The adjustable current limit accommodates MOSFETs

with a wide range of on-resistance characteristics (see

the Design Procedure section). The current-limit thresh-

old is adjusted with an external resistor at ILIM_ (Figure

1). The adjustment range is from 50mV to 300mV, cor-

responding to resistor values of 100kΩto 600kΩ. In

adjustable mode, the current-limit threshold across the

low-side MOSFET is precisely 1/10th the voltage seen

at ILIM_. However, the current-limit threshold defaults

to 100mV when ILIM is tied to VL. The logic threshold

for switchover to this 100mV default value is approxi-

mately VL- 0.5V.

Adjustable foldback current limit reduces power dissi-

pation during short-circuit conditions (see the Design

Procedure section).

Carefully observe the PC board layout guidelines to

ensure that noise and DC errors do not corrupt the cur-

rent-sense signals seen by LX_ and PGND. The IC

must be mounted close to the low-side MOSFET with

short, direct traces making a Kelvin-sense connection

so that trace resistance does not add to the intended

sense resistance of the low-side MOSFET.

Undervoltage Lockout and Startup

IF VLdrops below 4.2V, the MAX1858A/MAX1875A/

MAX1876A assume that the input supply and reference

voltages are too low to make valid decisions and activate

the undervoltage lockout (UVLO) circuitry, which latches

DL and DH low to inhibit switching. RST is also forced

low during UVLO. To reset the latch and be ready for the

next VLrise, VLmust be pulled below 2.5V.

In addition, to ensure proper startup, the value of the

capacitor at REF to GND must meet the following con-

dition:

CREF > ((8.29 x 10-4) / V+_SLOPE) - (1.97 x 10-1 / fS_MAX)

where V+_SLOPE is the actual input-voltage rise time’s

slew rate.

For example, if the switching frequency is set at

600kHz nominal, which is 660kHz (max), and the input-

voltage rise time’s slew rate is 1.6V/mS, then CREF

should be greater than 0.22µF. Make sure CREF is cho-

sen large enough to cover for worst-case capacitance

tolerances and temperature coefficient.

Enable (EN), Soft-Start, and Soft-Stop

Pull EN high to enable or low to shut down both regula-

tors. See the timing diagrams, Figures 3 and 4, for

more detail.

Output-Voltage Sequencing

After the startup circuitry enables the controller, the

MAX1858A begins the startup sequence. Regulator 1

(OUT1) powers up with soft-start enabled. Once the first

converter’s soft-start sequence ends, regulator 2 (OUT2)

powers up with soft-start enabled. Finally, when both con-

verters complete soft-start and both output voltages

exceed 90% of their nominal values, the reset output

(RST) goes high (see the Reset Output section). Soft-stop

is initiated by pulling EN low. Soft-stop occurs in reverse

order of soft-start, allowing last-on/first-off operation.

Reset Output (

RRSSTT

) (MAX1858A/

MAX1876A Only)

RST is an open-drain output. RST pulls low when either

output falls below 90% of its nominal regulation voltage.

Once both outputs exceed 90% of their nominal regulation

voltages and both soft-start cycles are completed, RST

goes high impedance. To obtain a logic-voltage output,

connect a pullup resistor from RST to the logic supply volt-

age. A 100kΩresistor works well for most applications. If

unused, leave RST grounded or unconnected.

Clock Synchronization (SYNC, CKO)

SYNC serves two functions: SYNC selects the clock out-

put (CKO) type used to synchronize slave controllers, or it

serves as a clock input so the MAX1858A/MAX1875A/

MAX1876A can be synchronized with an external clock

signal. This allows the MAX1858A/MAX1875A/MAX1876A

to function as either a master or slave. CKO provides a

clock signal synchronized to the MAX1858A/MAX1875A/

MAX1876As’ switching frequency, allowing either in-

phase (SYNC = GND) or 90° out-of-phase (SYNC = VL)

synchronization of additional DC-DC controllers (Figure 7).

The MAX1858A/MAX1875A/MAX1876A support the fol-

lowing three operating modes:

•SYNC = GND: The CKO output frequency equals

REG1’s switching frequency (fCKO = fDH1) and the

CKO signal is in phase with REG1’s switching fre-

quency. This provides 2-phase operation when syn-

chronized with a second slave controller.

•SYNC = VL:The CKO output frequency equals two

times REG1’s switching frequency (fCKO = 2fDH1)

and the CKO signal is phase shifted by 90° with

respect to REG1’s switching frequency. This pro-

vides 4-phase operation when synchronized with a

second MAX1858A/MAX1875A/MAX1876A (slave

controller).

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

14 ______________________________________________________________________________________

•SYNC Driven by External Oscillator: The controller

generates the clock signal by dividing down the

SYNC input signal, so that the switching frequency

equals half the synchronization frequency (fSW =

fSYNC/2). REG1’s conversion cycles initiate on the ris-

ing edge of the internal clock signal. The CKO output

frequency and phase match REG1’s switching fre-

quency (fCKO = fDH1) and the CKO signal is in

phase. Note that the MAX1858A/MAX1875A/

MAX1876A still require ROSC when SYNC is external-

ly clocked and the internal oscillator frequency should

be set to 50% of the synchronization frequency (fSW

= 0.5 fSYNC).

Thermal Overload Protection

Thermal overload protection limits total power dissipation

in the MAX1858A/MAX1875A/MAX1876A. When the

device’s die-junction temperature exceeds TJ= +160°C,

an on-chip thermal sensor shuts down the device, forcing

DL_ and DH_ low, allowing the IC to cool. The thermal

sensor turns the part on again after the junction tempera-

ture cools by 10°C. During thermal shutdown, the regula-

tors shut down, RST goes low, and soft-start is reset. If

the VLlinear-regulator output is short circuited, thermal-

overload protection is triggered.

Design Procedure

Effective Input Voltage Range

Although the MAX1858A/MAX1875A/MAX1876A con-

trollers can operate from input supplies ranging from

4.5V to 23V, the input voltage range can be effectively

limited by the MAX1858A/MAX1875A/MAX1876As’

duty-cycle limitations. The maximum input voltage is

limited by the minimum on-time (tON(MIN)):

where tON(MIN) is 100ns. The minimum input voltage is

limited by the switching frequency and minimum off-

time, which determine the maximum duty cycle

(DMAX = 1 - fSWtOFF(MIN)):

where VDROP1 is the sum of the parasitic voltage drops

in the inductor discharge path, including synchronous

rectifier, inductor, and PC board resistances. VDROP2 is

the sum of the resistances in the charging path, includ-

ing high-side switch, inductor, and PC board resis-

tances.

VVV

ft VV

IN MIN OUT DROP

SW OFF MIN DROP DROP() ()

⎡

⎣

⎢

⎤

⎦

⎥

⎥+

121

1- -

IN MAX OUT

ON MIN SW

()

≤

SYNC

SLAVE

OSC

SYNC

CK0

MASTER

4-OUTPUT APPLICATION3-OUTPUT APPLICATION

DH1

DH2

MASTER

SLAVE

180° PHASE SHIFT 90° PHASE SHIFT

DH1

DH2

DH1

DH2

MASTER

SLAVE

MAX1858A

MAX1875A

MAX1876A

MAX1858A

MAX1875A

MAX1876A

MAX1858A

MAX1875A

MAX1876A

SYNC

SLAVE

OSC OSC

SYNC

CK0

MASTER

Figure 7. Synchronized Controllers

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

______________________________________________________________________________________ 15

Setting the Output Voltage

For 1V or greater output voltages, set the MAX1858A/

MAX1875A/MAX1876A output voltage by connecting a

voltage-divider from the output to FB_ to GND (Figure

8). Select R_B (FB_ to GND resistor) to between 1kΩ

and 10kΩ. Calculate R_A (OUT_ to FB_ resistor) with

the following equation:

where VSET = 1V (see the Electrical Characteristics)

and VOUT can range from VSET to 18V.

For output voltages below 1V, set the MAX1858A/

MAX1875A/MAX1876A output voltage by connecting a

voltage-divider from the output to FB_ to REF (Figure

8). Select R_C (FB to REF resistor) in the 1kΩto 10kΩ

range. Calculate R_A with the following equation:

where VSET = 1V, VREF = 2V (see the Electrical

Characteristics), and VOUT can range from 0 to VSET.

Setting the Switching Frequency

The controller generates the clock signal by dividing

down the internal oscillator or SYNC input signal when

driven by an external oscillator, so the switching frequen-

cy equals half the oscillator frequency (fSW = fOSC/2).

The internal oscillator frequency is set by a resistor

(ROSC) connected from OSC to GND. The relationship

between fSW and ROSC is:

where fSW is in Hz and ROSC is in Ω. For example, a

600kHz switching frequency is set with ROSC = 10kΩ.

Higher frequencies allow designs with lower inductor

values and less output capacitance. Consequently,

peak currents and I2R losses are lower at higher

switching frequencies, but core losses, gate-charge

currents, and switching losses increase.

A rising clock edge on SYNC is interpreted as a syn-

chronization input. If the SYNC signal is lost, the inter-

nal oscillator takes control of the switching rate,

returning the switching frequency to that set by ROSC.

This maintains output regulation even with intermittent

SYNC signals. When an external synchronization signal

is used, ROSC should set the switching frequency to

one-half SYNC rate (fSYNC).

Inductor Selection

Three key inductor parameters must be specified for

operation with the MAX1858A/MAX1875A/MAX1876A:

inductance value (L), peak-inductor current (IPEAK), and

DC resistance (RDC). The following equation assumes a

constant ratio of inductor peak-to-peak AC current to DC

average current (LIR). For LIR values too high, the RMS

currents are high, and therefore I2R losses are high.

Large inductances must be used to achieve very low LIR

values. Typically, inductance is proportional to resis-

tance (for a given package type), which again makes I2R

losses high for very low LIR values. A good compromise

between size and loss is a 30% peak-to-peak ripple cur-

rent to average-current ratio (LIR = 0.3). The switching

frequency, input voltage, output voltage, and selected

LIR determine the inductor value as follows:

where VIN, VOUT, and IOUT are typical values (so that

efficiency is optimum for typical conditions). The switch-

ing frequency is set by ROSC (see the Setting the

Switching Frequency section). The exact inductor value

is not critical and can be adjusted in order to make

trade-offs among size, cost, and efficiency. Lower

inductor values minimize size and cost, but also

improve transient response and reduce efficiency due

to higher peak currents. On the other hand, higher

inductance increases efficiency by reducing the RMS

current. However, resistive losses due to extra wire turns

can exceed the benefit gained from lower AC current

levels, especially when the inductance is increased

without also allowing larger inductor dimensions.

Find a low-loss inductor having the lowest possible DC

resistance that fits in the allotted dimensions. The

LVVV

V f I LIR

OUT IN OUT

IN SW OUT

=()-

RHz

OSC SW

=×610

9()Ω-

RA RC VV

SET OUT

REF SET

__=⎛

⎝

⎜⎞

⎠

⎟

RA RB V

OUT

SET

__=⎛

⎝

⎜⎞

⎠

⎟

⎡

⎣

⎢

⎤

⎦

⎥

-1

MAX1858A

MAX1875A

MAX1876A

MAX1858A

MAX1875A

MAX1876A

OUT_

R_A

R_B

FB_

VOUT_ > 1V

OUT_

R_C

R_A

FB_

REF

VOUT_ < 1V

Figure 8. Adjustable Output Voltage

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

16 ______________________________________________________________________________________

inductor’s saturation rating must exceed the peak-

inductor current at the maximum defined load current

(ILOAD(MAX)):

Setting the Valley Current Limit

The minimum current-limit threshold must be high

enough to support the maximum expected load current

with the worst-case low-side MOSFET on-resistance

value since the low-side MOSFET’s on-resistance is

used as the current-sense element. The inductor’s valley

current occurs at ILOAD(MAX) minus half of the ripple

current. The current-sense threshold voltage (VITH)

should be greater than voltage on the low-side MOSFET

during the ripple-current valley:

where RDS(ON) is the on-resistance of the low-side

MOSFET (NL). Use the maximum value for RDS(ON)

from the low-side MOSFET’s data sheet, and additional

margin to account for RDS(ON) rise with temperature is

also recommended. A good general rule is to allow

0.5% additional resistance for each °C of the MOSFET

junction temperature rise.

Connect ILIM_ to VL for the default 100mV (typ) cur-

rent-limit threshold. For an adjustable threshold, con-

nect a resistor (RILIM_) from ILIM_ to GND. The

relationship between the current-limit threshold (VITH_)

and RILIM_ is:

where RILIM_ is in Ωand VITH_ is in V.

An RILIM resistance range of 100kΩto 600kΩcorre-

sponds to a current-limit threshold of 50mV to 300mV.

When adjusting the current limit, 1% tolerance resistors

minimize error in the current-limit threshold.

For foldback current limit, a resistor (RFBI) is added

from ILIM pin to output. The value of RILIM and RFBI

can then be calculated as follows:

First select the percentage of foldback, PFB, from 15%

to 30%, then:

If RILIM_ results in a negative number, select a low-side

MOSFET with lower RDS(ON) or increase PFB_ or a com-

bination of both for the best compromise of cost, effi-

ciency, and lower power dissipation during short circuit.

Input Capacitor

The input filter capacitor reduces peak currents drawn

from the power source and reduces noise and voltage

ripple on the input caused by the circuit’s switching.

The input capacitor must meet the ripple current

requirement (IRMS) imposed by the switching currents

as defined by the following equation:

IRMS has a maximum value when the input voltage equals

twice the output voltage (VIN = 2VOUT), so IRMS(MAX) =

ILOAD / 2. For most applications, nontantalum capacitors

(ceramic, aluminum, polymer, or OS-CON) are preferred

at the input due to their robustness with high inrush cur-

rents typical of systems that can be powered from very

low impedance sources. Additionally, two (or more)

smaller-value low-ESR capacitors can be connected in

parallel for lower cost. Choose an input capacitor that

exhibits less than +10°C temperature rise at the RMS

input current for optimal long-term reliability.

Output Capacitor

The key selection parameters for the output capacitor

are capacitance value, ESR, and voltage rating. These

parameters affect the overall stability, output ripple volt-

age, and transient response. The output ripple has two

components: variations in the charge stored in the out-

put capacitor, and the voltage drop across the capaci-

tor’s ESR caused by the current flowing into and out of

the capacitor:

VV V

RIPPLE RIPPLE ESR RIPPLE C

≅+

() ()

II VVV

RMS LOAD OUT IN OUT

=()-

RPV

and

RVPR

VVP

FBI FB OUT

ILIM ITH FB FBI

OUT ITH FB

=×

=××

[]

510 1

10 1

6- -

()

ILIM ITH

=µ05

VR I LIR

ITH DS ONMAX LOAD MAX

>××

⎛

⎝

⎜⎞

⎠

⎟

(, ) ( ) 12

II LIR I

PEAK LOAD MAX LOAD MAX

⎛

⎝

⎜⎞

⎠

⎟

() ()

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

______________________________________________________________________________________ 17

The output voltage ripple as a consequence of the ESR

and output capacitance is:

where IP-P is the peak-to-peak inductor current (see the

Inductor Selection section). These equations are suitable

for initial capacitor selection, but final values should be

verified by testing in a prototype or evaluation circuit.

As a general rule, a smaller inductor ripple current results

in less output ripple voltage. Since inductor ripple current

depends on the inductor value and input voltage, the out-

put ripple voltage decreases with larger inductance and

increases with higher input voltages. However, the induc-

tor ripple current also impacts transient-response perfor-

mance, especially at low VIN - VOUT differentials. Low

inductor values allow the inductor current to slew faster,

replenishing charge removed from the output filter capac-

itors by a sudden load step. The amount of output-volt-

age sag is also a function of the maximum duty factor,

which can be calculated from the minimum off-time and

switching frequency:

where tOFF(MIN) is the minimum off-time (see the

Electrical Characteristics), and fSW is set by ROSC (see

the Setting the Switching Frequency section).

Compensation

Each voltage-mode controller section employs a

transconductance error amplifier whose output is the

compensation point of the control loop. The control loop

is shown in Figure 9. For frequencies much lower than

Nyquist, the PWM block can be simplified to a voltage

amplifier. Connect RCOMP_ and CCOMP_A from COMP

to GND to compensate the loop (Figure 9). The inductor,

output capacitor, compensation resistor, and compen-

sation capacitors determine the loop stability. Since the

inductor and output capacitor are chosen based on per-

formance, size, and cost, select the compensation resis-

tor and capacitors to optimize control-loop stability.

To determine the loop gain (AL), consider the gain from

FB to COMP (ACOMP/FB), from COMP to LX (ALX/COMP),

and from LX to FB (AFB/LX). The total loop gain is:

where:

assuming an ideal integrator, and assuming that

CCOMP_B is much less than CCOMP_A:

where VRAMP = 1VP-P:

Therefore:

For an ideal integrator, this loop gain approaches infinity

at DC. In reality the gMamplifier has a finite output

impedance, which imposes a finite, but large, loop gain.

It is this large loop gain that provides DC load accuracy.

The dominant pole occurs due to the integrator, and for

this analysis, it can be approximated to occur at DC.

RCOMP creates a zero at:

The inductor and capacitor form a double pole at:

OUT

2π

Z COMP A

COMP COMP A

2π

SR C

SLC

LM COMP

COMP A

COMP COMP A

COMP COMP B

RAMP

SET

OUT

ESR OUT

OUT

≅×+

+×

××

sR C

SLC SR C

SR C

VSLC

FB LX FB

SET

OUT

ESR OUT

OUT ESR OUT

SET

OUT

ESR OUT

OUT OUT

/== +

≅+

LX COMP LX

COMP

RAMP

/==

sR C

COMP FB COMP

M COMP

COMP

COMP COMP A

COMP COMP B

=≅×

AAAA

L COMP FB LX COMP FB LX

=××

// /

LI I V

Vf t

CV VV

Vf t

SAG

LOAD LOAD OUT

IN SW OFF MIN

OUT OUT IN OUT

IN SW OFF MIN

⎛

⎝

⎜⎞

⎠

⎟+

⎡

⎣

⎢

⎤

⎦

⎥

⎛

⎝

⎜⎞

⎠

⎟

⎡

⎣

⎢

⎤

⎦

⎥

() ()

()

VIR

IVV

RIPPLE ESR P P ESR

RIPPLE C PP

OUT SW

PP IN OUT

OUT

()

=⎛

⎝

⎜⎞

⎠

⎟⎛

⎝

⎜⎞

⎠

⎟

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

18 ______________________________________________________________________________________

At some higher frequency, the output capacitor’s

impedance becomes insignificant compared to its ESR,

and the LC system becomes more like an LR system,

turning a double pole into a single pole. This zero

occurs at:

A final pole is added using CCOMP_B to reduce the

gain and attenuate noise after crossover. This pole

(fCOMP_B) occurs at:

Figure 10 shows a Bode plot of the poles and zeros in

their relative locations.

Near crossover, the following approximations can be

made to simplify the loop-gain equation:

•R

COMP has much higher impedance than CCOMP.

This is true if, and only if, crossover occurs above

fZ_COMP_A. If this is true, CCOMP_A can be ignored

(as a short to ground).

•R

ESR is much higher impedance than COUT. This is

true if, and only if, crossover occurs well after the out-

put capacitor’s ESR zero. If this is true, COUT

becomes an insignificant part of the loop gain and can

be ignored (as a short to ground).

•C

COMP_B is much higher impedance than RCOMP

and can be ignored (as an open circuit). This is true

if, and only if, crossover occurs far below fCOMP_B.

The following loop-gain equation can be found by using

these previous approximations with Figure 9:

Setting the loop gain to 1 and solving for the crossover

frequency yields:

To ensure stability, select RCOMP to meet the following

criteria:

• Unity-gain crossover must occur below 1/5th of the

switching frequency.

• For reasonable phase margin using type 1 compen-

sation, fCO must be larger than 5 ✕ fESR.

Choose CCOMP_A so that fZ_COMP_A equals half fLC

using the following equation:

Choose CCOMP_B so that fCOMP_B occurs at 3 times

fCO using the following equation:

COMP B

CO COMP

××

()

23π

CLC

COMP A OUT

COMP

_=×2

f GBW V

gRR

CO IN

RAMP

SET

OUT

M COMP COMP ESR

== ×

×××

2π

gRR

LIN

RAMP

SET

OUT

M COMP COMP ESR

≅×× ××

COMP B

COMP COMP B

2π

ESR

ESR OUT

2π

COMP_

RCOMP_

CCOMP_A

CCOMP_B

gM_COMP

VSET

VOUT

RESR

COUT COMP_

RCOMP_

CCOMP_A CCOMP_B

gM_COMP

VSET

RESR

COUT

GAIN = +VIN/VRAMP

Figure 9. Fixed-Frequency Voltage-Mode Control Loop

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

______________________________________________________________________________________ 19

MOSFET Selection

The MAX1858A/MAX1875A/MAX1876As’ step-down

controller drives two external logic-level N-channel

MOSFETs as the circuit switch elements. The key

selection parameters are:

• On-resistance (RDS(ON))

• Maximum drain-to-source voltage (VDS(MAX))

• Minimum threshold voltage (VTH(MIN))

• Total gate charge (Qg)

• Reverse transfer capacitance (CRSS)

• Power dissipation

All four N-channel MOSFETs must be a logic-level type

with guaranteed on-resistance specifications at VGS ≥

4.5V. For maximum efficiency, choose a high-side

MOSFET (NH_) that has conduction losses equal to the

switching losses at the optimum input voltage. Check to

ensure that the conduction losses at minimum input

voltage do not exceed MOSFET package thermal limits,

or violate the overall thermal budget. Also, check to

ensure that the conduction losses plus switching losses

at the maximum input voltage do not exceed package

ratings or violate the overall thermal budget.

Ensure that the MAX1858A/MAX1875A/MAX1876A DL_

gate drivers can drive NL_. In particular, check that the

dv/dt caused by NH_ turning on does not pull up the NL_

gate through NL_’s drain-to-gate capacitance. This is the

most frequent cause of cross-conduction problems.

Gate-charge losses are dissipated by the driver and do

not heat the MOSFET. All MOSFETs must be selected

so that their total gate charge is low enough that VLcan

power all four drivers without overheating the IC:

MOSFET package power dissipation often becomes a

dominant design factor. I2R power losses are the great-

est heat contributor for both high-side and low-side

MOSFETs. I2R losses are distributed between NH_ and

NL_ according to duty factor as shown in the equations

below. Switching losses affect only the high-side

MOSFET, since the low-side MOSFET is a zero-voltage

switched device when used in the buck topology.

Calculate MOSFET temperature rise according to pack-

age thermal-resistance specifications to ensure that

both MOSFETs are within their maximum junction tem-

perature at high ambient temperature. The worst-case

dissipation for the high-side MOSFET (PNH) occurs at

both extremes of input voltage, and the worst-case dis-

sipation for the low-side MOSFET (PNL) occurs at maxi-

mum input voltage.

IGATE is the average DH driver-output current capability

determined by:

where RDS(ON)DH is the high-side MOSFET driver’s on-

resistance (5Ωmax), RGATE is any series resistance

between DH and BST (Figure 5), and RGMOSFET is the

internal gate resistance of the external MOSFET:

where PNH(CONDUCTION) is the conduction power loss

in the high-side MOSFET, and PNL is the total low-side

power loss.

To reduce EMI caused by switching noise, add a 0.1µF

ceramic capacitor from the high-side switch drain to

the low-side switch source or add resistors in series

with DL_ and DH_ to increase the MOSFETs’ turn-on

and turn-off times.

PIR

PP P

PI R V

NH CONDUCTION LOAD DS ON NH OUT

NH TOTAL NH SWITCHING NH CONDUCTION

NL LOAD DS ON NL OUT

()()

()( )( )

()

=⎛

⎝

⎜⎞

⎠

⎟

=⎛

⎝

⎜⎞

⎠

⎟

⎛

⎝

⎜

⎞

⎠

⎟

21-

RRR

GATE L

DS ON DH GATE GMOSFET

=++

()

2()

PVIf

NH SWITCHING IN LOAD SW GS GD

GATE

()

⎛

⎝

⎜⎞

⎠

⎟

PVQ f

VL IN G TOTAL SW

=× ×

BODE PLOT FOR VOLTAGE-

MODE CONTROLLERS

FREQUENCY (MHz)

GAIN (dB)

0.10.01

-40

-30

-20

-10

0.001 1

fZ-COMP_A

fCOMP_B

fLC

fCO

fESR

fSWITCH

Figure 10. Voltage-Mode Loop Analysis

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

20 ______________________________________________________________________________________

Applications Information

Dropout Performance

When working with low input voltages, the output-volt-

age adjustable range for continuous-conduction opera-

tion is restricted by the minimum off-time (tOFF(MIN)).

For best dropout performance, use the lowest (100kHz)

switching-frequency setting. Manufacturing tolerances

and internal propagation delays introduce an error to

the switching frequency and minimum off-time specifi-

cations. This error is more significant at higher frequen-

cies. Also, keep in mind that transient response

performance of buck regulators operated close to

dropout is poor, and bulk output capacitance must

often be added (see the VSAG equation in the Design

Procedure section).

The absolute point of dropout is when the inductor cur-

rent ramps down during the minimum off-time (∆IDOWN)

as much as it ramps up during the maximum on-time

(∆IUP). The ratio h = ∆IUP/∆IDOWN is an indicator of the

ability to slew the inductor current higher in response to

increased load, and must always be greater than 1. As

h approaches 1, the absolute minimum dropout point,

the inductor current cannot increase as much during

each switching cycle and VSAG greatly increases

unless additional output capacitance is used.

A reasonable minimum value for h is 1.5, but adjusting

this up or down allows tradeoffs between VSAG, output

capacitance, and minimum operating voltage. For a

given value of h, the minimum operating voltage can be

calculated as:

where VDROP1 is the sum of the parasitic voltage drops

in the inductor discharge path, including synchronous

rectifier, inductor, and PC board resistances; VDROP2 is

the sum of the resistances in the charging path, includ-

ing high-side switch, inductor, and PC board resis-

tances; and tOFF(MIN) is from the Electrical

Characteristics. The absolute minimum input voltage is

calculated with h = 1.

If the calculated V+(MIN) is greater than the required

minimum input voltage, then reduce the operating fre-

quency or add output capacitance to obtain an accept-

able VSAG. If operation near dropout is anticipated,

calculate VSAG to be sure of adequate transient

response.

Dropout design example:

VOUT = 5V

fSW = 600kHz

tOFF(MIN) = 250ns

VDROP1 = VDROP2 = 100mV

h = 1.5

Calculating again with h = 1 gives the absolute limit of

dropout:

Therefore, VIN must be greater than 6V, even with very

large output capacitance, and a practical input voltage

with reasonable output capacitance would be 6.58V.

Improving Noise Immunity

Applications where the MAX1858A/MAX1875A/

MAX1876A must operate in noisy environments can

typically adjust their controller’s compensation to

improve the system’s noise immunity. In particular,

high-frequency noise coupled into the feedback loop

causes jittery duty cycles. One solution is to lower the

crossover frequency (see the Compensation section).

PC Board Layout Guidelines

Careful PC board layout is critical to achieve low switch-

ing losses and clean, stable operation. This is especially

true for dual converters where one channel can affect

the other. Refer to the MAX1858 EV kit or MAX1875 EV

kit data sheet for specific layout examples.

If possible, mount all the power components on the top

side of the board with their ground terminals flush

against one another. Follow these guidelines for good

PC board layout:

• Isolate the power components on the top side from

the analog components on the bottom side with a

ground shield. Use a separate PGND plane under

the OUT1 and OUT2 sides (referred to as PGND1

and PGND2). Avoid the introduction of AC currents

into the PGND1 and PGND2 ground planes. Run the

power plane ground currents on the top side only.

VVmV

kHz ns

mV mV V

IN MIN() ()()

⎡

⎣

⎢⎤

⎦

⎥

−

5 100

1 600 250

100 100 6

VVmV

kHz ns

mV mV V

IN MIN() . ( )( )

⎡

⎣

⎢⎤

⎦

⎥

−

5 100

1 1 5 600 250

100 100 6 58

VVV

hf t VV

IN MIN OUT DROP

SW OFF MIN DROP DROP() ()

⎡

⎣

⎢

⎤

⎦

⎥

⎥+

121

1- -

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

______________________________________________________________________________________ 21

• Use a star-ground connection on the power plane to

minimize the crosstalk between OUT1 and OUT2.

• Keep the high-current paths short, especially at the

ground terminals. This practice is essential for sta-

ble, jitter-free operation.

• Connect GND and PGND together close to the IC.

Do not connect them together anywhere else.

Carefully follow the grounding instructions under

step 4 of the Layout Procedure section.

• Keep the power traces and load connections short.

This practice is essential for high efficiency. Use

thick copper PC boards (2oz vs. 1oz) to enhance

full-load efficiency by 1% or more.

• LX_ and PGND connections to the synchronous rec-

tifiers for current limiting must be made using Kelvin-

sense connections to guarantee the current-limit

accuracy. With 8-pin SO MOSFETs, this is best done

by routing power to the MOSFETs from outside

using the top copper layer, while connecting PGND

and LX_ underneath the 8-pin SO package.

• When trade-offs in trace lengths must be made,

allow the inductor-charging path to be made longer

than the discharge path. Since the average input

current is lower than the average output current in

step-down converters, this minimizes the power dis-

sipation and voltage drops caused by board resis-

tance. For example, allow some extra distance

between the input capacitors and the high-side

MOSFET rather than to allow distance between the

inductor and the low-side MOSFET or between the

inductor and the output filter capacitor.

• Ensure that the feedback connection to COUT_ is

short and direct.

• Route high-speed switching nodes (BST_, LX_, DH_,

and DL_) away from the sensitive analog areas

(REF, COMP_, ILIM_, and FB_). Use PGND1 and

PGND2 as EMI shields to keep radiated noise away

from the IC, feedback dividers, and analog bypass

capacitors.

• Make all pin-strap control input connections (ILIM_,

SYNC, and EN) to analog ground (GND) rather than

power ground (PGND).

Layout Procedure

1) Place the power components first, with ground termi-

nals adjacent (NL_ source, CIN_, and COUT_). Make

all these connections on the top layer with wide, cop-

per-filled areas (2oz copper recommended).

2) Mount the controller IC adjacent to the synchronous-

rectifier MOSFETs (NL_), preferably on the back

side in order to keep LX_, PGND_, and DL_ traces

short and wide. The DL_ gate trace must be short

and wide, measuring 50mils to 100mils wide if the

low-side MOSFET is 1in from the controller IC.

3) Group the gate-drive components (BST_ diodes and

capacitors, and VLbypass capacitor) together near

the controller IC.

4) Make the DC-DC controller ground connections as

follows: create a small analog ground plane near the

IC. Connect this plane to GND and use this plane for

the ground connection for the reference (REF) V+

bypass capacitor, compensation components, feed-

back dividers, OSC resistor, and ILIM_ resistors (if

any). Connect GND and PGND together under the

IC (this is the only connection between GND and

PGND).

5) On the board’s top side (power planes), make a star

ground to minimize crosstalk between the two sides.

Chip Information

TRANSISTOR COUNT: 6688

PROCESS: BiCMOS

MAX1858A/MAX1875A/MAX1876A

Dual 180° Out-of-Phase Buck Controllers with

Sequencing/Prebias Startup and POR

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

QSOP.EPS

21-0055

PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information

go to www.maxim-ic.com/packages.)