®
Alt er a Cor pora t ion 1
APEX II
Programmable Logic
Device Family
Aug us t 2002, ver. 3.0 Data Sheet
DS-APEXII-3.0
Features... ■Programmab le logic devic e (PLD ) manufact ured us ing a 0.15 -µm a ll-
layer copper-metal fabrication process (up to eight layers of metal)
– 1-gigabit per second (Gbps) True-LVDSTM, LVPECL, pseu do
current mode log ic (P CML), and HyperTransportTM interface
– Clock-data synchronization (CDS) in True-LVDS interface to
correct any fixed clock-to-data skew
– Enables common networking and communications bus I/O
standard s such as Rapid IOTM, CSIX, Utopia IV, and POS-PHY
Level 4
– Support for high -spee d external memory int erfa ces, including
zero bus turnaround (ZBT), quad data rate (QDR), and double
data rate (DDR) static RAM (SRAM), and single data rate (SDR)
and DDR synchronous dynamic RAM (SDRAM)
–30% to 40% faster design performance than APEXTM 20KE
devices on av erage
– Enhanced 4,096-bit embedded system blocks (ESBs)
implementing first-in first-out (FIFO) buffers, Dual-Port+ RAM
(bidirectional dual-port RAM), and content-addressable
memory (CAM)
– Hig h-per for manc e, low-powe r copper inte rconn ect
– Fast parallel byte-wide synchronous device configuration
– Look-up table (LUT) logic available for register-intensive
functions
■High-density architecture
– 1,900,000 to 5,2 50, 000 maximum system gates (see Table 1)
– Up to 67,200 logic elements (LEs)
– Up to 1,146,880 RAM bits that can be used without reducing
available logic
■Low-power oper ati on design
– 1.5-V supply voltage
– Copper int erc o nnect reduce s p o we r con sumption
– MultiVoltTM I/O support for 1.5-V, 1.8-V, 2.5-V, and 3.3-V
interfaces
– ESBs offer programmable power-saving mode
2Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Notes to Table 1:
(1) Each dev ice has 36 in p ut c ha n nels an d 36 ou tpu t chan n els.
(2) EP2A15 and EP2A25 devices have 56 input and 56 output channels; EP2A40 and EP2A70 devices have 88 input and
88 output chan n el s.
(3) PLL: phase-locked loop. True-LVDS PLLs are dedicated to implement True-LVDS functionality.
(4) Two internal outputs per PLL are available. Additionally, the device has one external output per PLL pair (two
external outputs per device).
...and More
Features
■I/O features
– Up to 380 Gbps of I/O capability
– 1-Gbps True-LVDS, LVPECL , PCML, and Hyper Transport
support on 36 input and 36 output channels that feature clock
syn chroni zat ion cir cui try and ind ep ende nt clock multipl icat ion
and serialization/deserialization factors
– Common networking and communications bus I/O standards
such as RapidIO, CSIX, Utopia IV, and POS-PHY Level 4 enabled
– 400-megabits per second (Mbps) Flexible-LVDS and
HyperTransport support on up to 88 input and 88 output
chan nels (input cha nne ls als o suppor t L VPECL)
– Support for high-speed external memories, including ZBT, QDR,
and DDR SRAM, and SDR and DD R SDRAM
– Compliant with peripheral component interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 f or 3. 3-V o per atio n at 3 3 or 66 MH z an d 32 or 6 4 bi ts
– Compliant with 133-MHz PCI-X specifications
– Support for other advanced I/O standards, including AGP, CTT,
SSTL-3 and SSTL-2 Class I a nd II, GTL+, and HSTL Class I and II
– Six dedicated registers in each I/O element (IOE): two input
registers, two out put registers, and two outpu t-e nable registers
– Programmable bus hold feature
– Programmable pull-up resistor on I/O pins available during
user mode
Table 1. APEX II Devi ce F eatures
Feature EP2A15 EP2A25 EP2A40 EP2A70
Maximu m ga tes 1,900,000 2,750,000 3,000,000 5,250 ,00 0
Typical ga tes 600, 000 900,00 0 1,500,000 3,000,000
LEs 16,640 24,320 38,400 67,200
RAM ESBs 104 152 160 280
Maximu m RAM bit s 425, 984 622,59 2 655,360 1,146,880
True-LVDS channels 36 (1) 36 (1) 36 (1) 36 (1)
Flexible-LVDSTM ch annels (2) 56 56 88 88
T rue-LVDS PL Ls (3) 4444
General-purpose PLL outputs (4) 8888
Maximu m user I /O pins 492 612 735 1,06 0
Altera Corporation 3
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
– Programmable output drive for 3.3-V LVTTL at 4 mA, 12 mA,
24 mA, or I/O standard levels
– Pr og rammable outp ut slew-rate cont rol r educe s s wit chin g no ise
– Hot-socketing operation supported
– Pull-up resistor on I/O pins before and during configuration
■Enhanced internal memory structure
– High-density 4,096-bit ESBs
– Dual-Port+ RAM w ith bi di rec tional read and write ports
– Support for many other memory functions, including CAM,
FIFO, and ROM
– ESB packing mode partitions one ESB into two 2,048-bit blocks
■Device configur a tion
– Fast byte-wide synchronous configuration minimizes in-circuit
reconfiguration time
– Device configuration supports multiple voltages (either 3.3 V
and 2.5 V or 1.8 V)
■Fl exib le clo ck mana gem en t ci rcui tr y w ith ei ght g en eral -p urpo se PLL
outputs
– Four general-purpose PLLs with two outputs per PLL
– Built-in low-skew clock tree
– Eight global clock signals
– ClockLockTM feature reducing clock dela y an d skew
– ClockBoostTM feature providing clock multiplication (by 1 to 160)
and division (by 1 to 256)
– ClockShiftTM feature providing programmable clock phase and
delay shifting with coarse (90°, 180°, or 270°) and fine (0.5 to
1.0 ns) resolution
■Advanced interconnect structure
– All-layer cop per interconn ec t for high performance
– Four-level hierarchical FastTrack® interconnect structure for fast,
predictable interconnect delays
– Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
– Dedicated cascade chain that imp lements high-sp e ed,
high-fan-in logic functions (automatically used by software tools
and meg afun c ti ons)
– I nte rlea ve d local int ercon nec t all owing one LE to drive 29 other
LEs through the fast local interconnect
■Advanced software support
– Software design support and automatic place-and-route
provided by the Altera® QuartusTM II development system for
Windows-based PCs, Sun SPARCstations, and HP 9000
Series 700/800 workstations
–Altera MegaCore
® functions and Altera Megafuncti on Part ners
Program (AMPPSM) megafunctions optimized for APEX II
architecture
4Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
– LogicLockTM incremental design for intellectual property (IP)
int egrati on and team- based design
– NativeLinkTM integration with popular synthesis, simulation,
and timing analysis tools
–SignalTap
® embedded l ogic analyzer simplifies in-sys tem design
evaluation by giving access to internal nodes during device
operation
– Support for popular revision-control software packages,
including PVCS, RCS, and SC CS
Tables 2 and 3 show the APEX II ball-grid array (BGA) and
FineLine BGATM device package sizes, options, and I/O pin counts.
Notes to Table 3:
(1) All APEX II devices support vertical migration within the same package (e.g., the designer can migrate between the
EP2A15, E P2 A 25, and EP2A4 0 d evices in the 672 -pi n FineL i n e B GA pa c ka ge ). V ert ical mig r ation means t ha t
designers can mig rate to devices whose dedicate d pins, c onfiguration pi ns, LVDS pins, and power pins are the same
for a given package across device den sities. Migration of I/O pins across densities requires the designer to cross
refer ence th e av ailabl e I/ O pi ns using th e d ev ice pin-o uts. T h is must be d o n e for all pla n ned d ensities fo r a giv en
package type to identify which I/O pins are migratable.
(2) I/O pin counts include dedicated clock and fast I/O pins.
Table 2. APEX II Pack age Sizes
Feature 672-Pin
FineLine BGA 724-Pin BGA 1,020-Pin
FineLine BGA 1,508-Pin
FineLine BGA
Pitch (mm) 1.00 1.27 1.00 1.00
Area (mm2) 729 1,225 1,089 1,600
Length × Width (mm ×mm) 27 × 27 35 × 35 33 × 33 40 × 40
Table 3. APEX II Package Options & I / O Pin Coun t Notes (1) , (2)
Feature 672-Pin
FineLine BGA 724-Pin BGA 1,020-Pin
FineLine BGA 1,508-Pin
FineLine BGA
EP2A15 492 492
EP2A25 492 536
EP2A40 492 536 735
EP2A70 536 1,060
Altera Corporation 5
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
General
Description
APEX II devices integrate high-speed differential I/O support using the
True-LVDS int erfa ce. The dedicated serializer, deseri ali ze r, and CDS
circuitry in the True-LVDS interface support the LVDS, LVPECL,
HyperTransport, and PCM L I/O standards. Flexible-LVDS pi ns l ocated
in reg ular user I/O banks o ffer addit ional diffe rential supp ort, i ncreasin g
the total device bandwidth. This circuitry, together with enhanced IOEs
and sup port for num erous I/O stan dards, al lows APEX II de vices to meet
high-speed interface requ ireme nts.
APEX II devices also include other high-performance features such as
bidirectional dual-port RAM, CAM, general-purpose PLLs, and
numerous global clocks.
Configuration
The logic, circuitry, and interconnects in the APEX II architecture are
configured with CMOS SRAM elements. APEX II devices are
reconfigurabl e an d are 100% tested prior to shipment. As a result, test
vectors do not have to be generated for fault coverage. Instead, the
desig ne r ca n focus on simula tio n a nd de sig n verific ation. In a ddit ion, the
designer does not need to manage inventories of different ASIC designs;
APEX II devices can be configured on the board for the specific
functionality required.
APEX II devices are configured at system power-up with data either
stored in an Altera configuration device or provided by a system
controller. Altera offers in-system programmability (ISP)-capable
configuration devices, which configure APEX II devices via a serial data
stream. The enhanced configuration devices can configure any APEX II
device in under 100 ms. Moreover, APEX II devices contain an optimized
interface that permits microprocessors to configure APEX II devices
serially or in parallel, synchronously or asynchronously. This interface
also en ab les micr op r oce ssor s to treat AP EX II device s as mem or y and to
config ure the device by writ ing to a virtual memory loca tion, simplifying
reconfiguration.
APEX II devices also support a new byte-wide, synchronous
configuration scheme at speeds of up to 66 MHz using EPC16
configuration devices or a microprocessor. This parallel configuration
reduce s configurat ion time by usi ng eig ht data lines to send configur ation
data versus one data line in serial configuration.
APEX II devices support multi-voltage configuration; device
configuration can be performed at 3.3 V and 2.5 V or 1.8 V.
6Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
After an APEX II device has been configured, it can be reconfigured in-
circuit by resettin g the device and l oading new dat a. Rea l-time cha ng es
can be made during system operation, enabling innovative reconfigurable
computing applications.
Software
APEX II devices are supported by the Altera Quartus II development
system: a single, integrated package that offers hardware description
language (HDL) and schematic design entry, compilation and logic
synth esis, full simulation and wor st-case timing analy sis, SignalT ap logic
analysis, and device configuration. The Quartus II software runs on
Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800
workstations.
The Quartus II software includes the LogicLock incremental design
feature. The LogicLock feature allows the designer to make pin and
timing assignments, verify functionality and performance, and then set
constraints to lock down the placement and performance of a specific
block of logic using LogicLock constraints. Constraints set by the
LogicL ock function gua rant ee re peat ab le plac eme nt w he n imple men ting
a block of logic in a current project or exporting the block to another
project. The constraints set by the LogicLock feature can lock down logic
to a fixed location in the device. The LogicLock feature can also lock the
logic down to a flo ating lo cat ion, and th e Q ua rt us I I sof t war e dete r mine s
the best relative placement of the block to meet design requirements.
Adding additional logic to a project will not affect the performance of
blocks locked down with LogicLock constraints.
The Qua rtus II softwa re provi des Nat iveLin k inter face s to othe r indust ry-
standard PC- and UNIX workstation-based EDA tools. For example,
designers can open the Quartus II software from within third-party
design tools. The Quartus II software also contains built-in optimized
synthesis libraries; synthesis tools can use these libraries to optimize
design s for APE X II de vices. For exam ple, the Synop sys Desig n Compil er
library, supplied with the Quartus II development system, includes
DesignWare functions optimized for the APEX II architecture.
Functional
Description
APEX II devices incorporate LUT-based logic, product-term-based logic,
memory, and high-speed I/O standards into one device. Signal
interconnections within APEX II devices (as well as to and from device
pins) are provided by the FastTrack interconnect—a series of fast,
continuous row and column channels that run the entire length and width
of the device.
Altera Corporation 7
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Each I/O pin is fed by an IOE located at the end of each row and column
of the FastTrack interconnect. Each IOE contains a bidirectional I/O buffer
and six registers that can be used for registering input, output, and
output-enable signals. When used with a dedicated clock pin, these
registers provide exceptional performance and interface support with
external memory devices such as DDR SDRAM and ZBT and QDR SRAM
devices.
IOEs provide a variety of features such as: 3.3-V, 64-bit, 66-MHz PCI
compliance, 3.3-V, 64-bit, 133-MHz PCI-X compliance, Joint Test Action
Group (JTAG) boundary-scan test (BST) support, output drive strength
control, slew-rate control, tri-state buffers, bus-hold circuitry,
progra mmable pull-up r esistor s, programmab le input and outp ut delays,
and open-drain outputs.
APEX II devices offer e nhance d I/O supp ort, includ ing sup port for 1.5 V,
1.8 V, 2.5 V, 3.3 V, LV CMOS, LVTTL, HS TL, LVDS, LVP ECL,
Hype rTransp ort, PCML, 3.3-V PCI, PCI-X, GTL+, SSTL -2, SSTL -3, CTT,
and 3.3 -V AGP I/ O standards. High-speed ( up to 1.0 Gbp s) d iff erential
transfers are supported with True-LVDS circuitry for LVDS, LVPECL,
HyperTran spo rt, and PCML I/O standards. The optiona l CDS fea ture
corrects any clock -to- data skew at th e Tr ue- LVDS rece iver chann els,
allowing for flexible board topologies. Up to 88 Flexible-LVDS channels
support differential transfer at up to 400 Mbps (DDR) for LVDS and
HyperTransport I/O standards.
An ESB can implement many types of memory, including Dual-Port+
RAM, CAM, R OM, and FI FO f u n ctio n s . E m bed d i ng the memo r y di rect l y
into the die improves pe rfo rmance and reduces di e ar ea comp are d to
distributed-RAM implementations. The abundance of cascadable ESBs
ensures that the APEX II device can implement multiple wide memory
blocks for high-density designs. The ESB’s high speed ensures it can
implement small memory blocks without any speed penalty. The
abundance of ESBs, in conjunction with the ability for one ESB to
implement two sep arate memory blocks, ensures that designers can create
as many different-sized memory blocks as the system requires.
Figure 1 shows an overview of the APEX II device.
8Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Figure 1. APEX II Device Block Diagram
Table 4 lists the resources available in APEX II devices.
APEX II de vic es provide eight dedicat ed clock i nput pins and fou r
dedicated fast I/O pins that globally drive register control inputs,
including clocks. These signals ensure efficient distribution of high-speed,
low-skew control signals. The control signals use dedicated routing
channe ls to prov ide sh ort delays a nd low sk ew. The de dicated fa st signal s
can also be driven by interna l logic, providing an ideal solution for a clock
divider or internally-generated asynchronous control signal with high
fan-out. The dedicated clock and fast I/O pins on APEX II devices can also
feed logic. Dedicated clocks can also be used with the APEX II general-
purpose PLLs for clock management.
LUT
LUT
LUT
LUT
LUT
Memory
Memory
Memory
Memory
IOE
IOE
IOE IOE
IOE
IOE
IOE IOE
LUT
LUT
Memory
Memory
IOE
IOE
Product Term
Product Term
LUT
LUT
Memory
Memory
IOE
IOE
Product Term
Product Term Product Term
Product Term Product Term
Product Term
FastTrack
Interconnect
Clock Management Circuitry
IOEs support
PCI, GTL+,
SSTL-3, LVDS,
and other
standards.
ClockLock
Four-input LUT
for data path and
DSP functions.
Product-term
integration for
high-speed
control logic and
state machines.
Flexible integration
of embedded
memory, including
CAM, RAM,
ROM, FIFO, and
other memory
functions.
Table 4. APEX II D evice Re sou rces
Device MegaLAB Rows MegaLAB
Columns ESBs
EP2A15 26 4 104
EP2A25 38 4 152
EP2A40 40 4 160
EP2A70 70 4 280
Altera Corporation 9
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
MegaLA B Stru c ture
APE X II devic es are constructed from a serie s of Meg aLAB TM structure s.
Each MegaLAB structure contains a group of logic array block s (LABs),
one ESB, and a MegaLAB interconnect, which routes signals within the
MegaLAB structure. EP2A15 and EP2A25 devices have 16 LABs an d
EP2A40 and EP 2A70 devices have 24 LABs. Signa l s are routed between
MegaLAB structures and I/O pins via the FastTrack interconnect. In
addition, edge LABs can be driven by I/O pins through the local
interconnect. Figure 2 shows the MegaLAB structure.
Figure 2. MegaLAB Structure
Logic Array Bloc k
Each LAB consists of 10 LEs, the LEs’ associated carry and cascade chains,
LAB control signals, and the local interconnect. The loca l interconnect
transfers signals between LEs in the same or adjacent LABs, IOEs, or ESBs.
The Quartus II Co mpile r place s asso ciate d logi c withi n a LA B or adjac en t
LABs, allowing the use of a fast local interconnect for high performance.
APEX II devices use an interleaved LAB structure, so that ea ch LAB can
drive tw o lo cal int ercon nec t a r eas. Ev ery oth er L E d rives to eithe r the left
or right local in terconnect area, alternating by LE. The local interconnect
can drive LEs within the s ame LAB or adjacent LABs . This feature
minimizes th e use of the row and column inter connects, provi ding highe r
performance and flexibility. Each LAB structure can drive 30 LEs through
fast local interconnects.
ESB
MegaLAB Interconnect
Local
Interconnect
T
o Adjacent
L
AB or IOEs
LABs
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
10 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Figure 3 shows the APEX II LA B.
Figu r e 3. AP EX II LA B St ructure
Each LAB contains dedicated logic for driving control signals to its LEs
and ESBs. The control signals include clock, clock enable, asynchronous
clear, asynchronous pres et, asynchronous load, synchronous clear, and
synchronous load signals. A maximum of six control signals can be used
at a ti me. Althou gh synchron ous load an d clear sig nals are g enerally us ed
when implementing counters, they can also be used with other functions.
Each LAB can use tw o cl o cks and two cl o ck enable signals. The LAB’s
clock and clock enable s ig nals a re linked (e .g., a ny LE in a p artic ula r L AB
using CLK1 w ill also use CLKENA1). LEs w ith the s ame cloc k bu t diffe rent
clock enable sig nals e ither u se both cloc k signal s in one LAB or are pla ced
into separat e LABs. If both the rising and fall ing edges of a cloc k are used
in an LAB, both LAB-wide clock signals are used.
To/From
Adjacent LA
B,
ESB, or IOE
s
To/From
Adjacent LAB,
ESB, or IOEs
The 10 LEs in the LAB are driven by
two local interconnect areas. These LEs
can drive two local interconnect areas.
Local Interconnect
LEs drive local,
MegaLAB, row,
and column
interconnects.
Column
Interconnect
Row
Interconnect
MegaLAB Interconnect
Altera Corporation 11
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
The LAB-w id e c ontrol signals can be ge nerated from the LA B l ocal
interconnect, global signals, an d dedicated clock pins. The inherent low
skew of the FastTrack interconnect e nables it to be used for clock
distribution. Figure 4 shows the LAB control signal generation circuit.
Figure 4. LAB Control Signal Generation
Notes to Figure 4:
(1) The LABCLR1 and LABCLR2 signals also contr ol asyn c h ro no us lo ad an d as ynch ro no us p res et for LE s with in t he
LAB.
(2) The SYNCCLR signal can be generated by the local interconnect or global signals.
Logic Element
The LE is the smallest unit of logic in the APEX II architecture. Each LE
conta ins a four-input LUT, which is a func tion generato r tha t can quickl y
impleme nt any function of four varia b les . In a d dition, ea ch LE c onta ins a
programmable register and carry and cascade chains. Each LE drives the
local interconnect, M egaLAB interconnect, and FastTrack interconnect
routing st ructure s. S ee Figure 5.
SYNCCLR
or LABCLK2 (2)
SYNCLOAD
or LABCLKENA2
LABCLK1
LABCLKENA1
LABCLR2 (1)
LABCLR1 (
1)
Dedicated
Clocks
Fast Global
Signals
L
ocal
I
nterconnect
L
ocal
I
nterconnect
L
ocal
I
nterconnect
L
ocal
I
nterconnect
4
8
12 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Figure 5. APEX II Logic Element
Each LE’s programmable regist e r can be configured for D, T, JK, or SR
operation. The register’s clock and clear control signals can be driven by
global signals, general-purpose I/O pins, or any internal logic. For
combinatoria l functions, the regis ter is bypasse d and the output of the
LUT drives the outputs of the LE.
labclk1
labclk2
labclr1
labclr2
Carry-In
Clock &
Clock Enable
Select
Carry-Out
Look-Up
Table
(LUT)
Carry
Chain Cascade
Chain
Cascade-In
Cascade-Out
To F
astTrack Interconnec
t,
MegaLAB Interconnect,
or Local Interconnect
To F
astTrack Interconnec
t,
MegaLAB Interconnect,
or Local Interconnect
Programmable
Register
PRN
CLRN
DQ
ENA
Register Bypass
Packed
Register Select
Chip-Wide
Reset
labclkena1
l
abclkena2
Synchronous
Load & Clear
Logic
LAB-wide
Synchronous
Load
LAB-wide
Synchronous
Clear
Asynchronous
Clear/Preset/
Load Logic
data1
data2
data3
data4
Altera Corporation 13
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Each LE has two outputs that dr i ve th e local, MegaLAB, o r FastTrack
inte r conn ect routing str uc ture . Ea ch out put can be dr iven indepe nd ently
by the LUT’s or register’s output. For example, the LUT can drive one
output while the register drives the other output. This feature, called
regis te r pa ck ing , imp r oves dev ice utilization be cau se the r e gi ste r and the
LUT can be used for unrelated functio ns. The LE can also dr ive out
registere d and unregistered versi o ns o f the LU T o utput. The APEX II
archite cture provides two types of dedicated high-speed data paths that
conne ct a dja ce nt L Es w ithout using loca l in te r conn ect p ath s: carry c hain s
and cascade chains. A carry chain supports high-spee d arithm et ic
functions such as counters and adders, while a cascade chain implements
wide-input functions such as equality comparators with minimum delay.
Carry and c as cade chains connec t LEs 1 t hrough 10 in an LAB and all
LABs in the same MegaLAB structure.
Carr y Ch ain
The carry chain provides a fast carry-forward function between LEs. The
carry-in signal from a lower-order bit drives forward into the higher-
order bit via the carry chain, and feeds into both the LUT and the next
portion of the ca r ry c hain . This fea ture allo ws t he APE X I I ar ch ite ctu re to
imple ment high-spe ed count e rs, adders, and comp arator s of arbitrary
wid th. The Quartu s II Compi ler can crea te carry chain logic au tomatically
during the design process, or the designer can create it manually during
design entry. Parameterized functions such as DesignWare functions
from Synopsys and library of parameterized modules (LPM) functions
autom atical ly take advantage of carry ch ains for the app ropria te
functions.
The Quartus I I Compiler creates ca rry chains longer than 10 LEs by
linking LABs together automatically. For enhanced fitting, a long carry
chain skips alte rn ate LABs in a Meg a LA B s tr uct ur e. A c ar r y ch ain longe r
than one LAB skips either from an even-numbered LAB to the next even-
numbered LAB, or from an odd-nu mbered LAB to th e next odd-
numbered LAB. For example, the last LE of the first LAB in the upper-left
MegaLAB str ucture carrie s to the first LE of the third LAB in the
MegaLAB str uc ture.
Figure 6 shows how an n-bit full a dder can b e impleme nted in n + 1 LEs
with the car ry chain. One port ion of th e LUT gene rates the sum of t wo bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register can be bypassed for simple adders or used
for accumulator functions. Another po rtion of the LUT and the carry chain
logic generates the carry -out signal, whi ch i s rou te d directly t o th e carry-
in signal of the next-higher-order bit. The final carry-out signal is routed
to an LE, where it is driven onto the local, MegaLAB, or FastTrack
interconnect routing structures.
14 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Figure 6. APEX II Carry Chain
LUT
a1
b1
Carry Chain
s1
LE1
Register
a2
b2
Carry Chain
s2
LE2
Register
Carry Chain
sn
LEn
Register
an
bn
Carry Chain
Carry-Ou
t
LEn + 1
Register
Carry-In
LUT
LUT
LUT
Altera Corporation 15
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Cascade Chain
Wit h the casca de chain, the APE X II ar chitectu re can imple ment func tions
with a very wide fan-in. Adjacent LUTs can compute portions of a
function in parallel; the cascade chain serially connects the intermediate
values. The cascade chain can use a logical AND or logical OR (via
DeMorgan’s inversion) to connect the outputs of adjacent LEs. Each
additional LE provides four more inputs to the effective w idth of a
function, with a short cascade delay. The Quartus II Compiler can create
cascade chain logic automatically during the design process, or the
desig ne r ca n creat e it manual ly du ring design entry.
Cascade chains longer than 10 LEs are implemented automatically by
linking LABs tog ether. For enhanced fitting, a long cascade chain skips
alte r nat e L ABs in a MegaL AB str uc tur e . A ca sca d e ch ain longer than one
LAB skips either from an even-numbered LAB to the next even-numbered
LAB, or from an odd-numbered LAB to the next odd-numbered LAB. For
ex ample, the last LE of the firs t LAB in the uppe r-le ft MegaLA B structu re
carries to the first LE of the third LAB in the MegaLAB structure. Figure 7
shows how the casc ade function can connect adjacent LEs to form
functions with a wide fan-in.
Figure 7. APEX II Cascade Chain
LE1
LUT
LE2
LUT
d[3..0]
d[7..4]
d[(4n — 1)..(4n — 4)]
d[3..0]
d[7..4]
LEn
LE1
LE2
LEn
LUT
LUT
LUT
LUT
AND Cascade Chain OR Cascade Chain
d[(4n — 1)..(4n — 4)]
16 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
LE Operating Modes
The APEX II LE can operate in one of the following three modes:
■Normal mode
■Arithmetic mode
■Counter mode
Each mode uses LE resources differently. In each mode, seven available
inputs to the LE—the four data inputs from the LAB local in terconnect,
th e feedback fr om the pro g r amm abl e register, and the car r y-in and
casca de-in from t he pre vious L E—are d irecte d to d ifferent destin ations to
implement the desired logic function. L AB-wide signals provide clock,
asynchronous clear, asynchronous preset, asynchronous load,
synchronous clear, synchronous load, and clock enable control for the
regis te r. These LAB-wide signal s a re a vailable in a ll LE modes.
The Quartus II software, in conjunction with parameterized functions
such as LPM and DesignWare functions, automatically chooses the
appropriat e mode for common function s su ch as counters, adders, and
multipliers. If required, the designer can also create special-purpose
functions that spec ify which LE operating mode to use for optimal
performance. Figure 8 shows the LE operating modes.
Altera Corporation 17
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Figure 8. A PEX II LE O perating Modes
Notes to Figure 8:
(1) LEs in normal mode support register packing.
(2) There are two LAB-wide clock enables per LAB.
(3) When usin g the car r y-in in nor mal m od e, the packed register feat u r e is unav ailable.
(4) A r egist er fe edback mu lt ipl ex er is av aila ble on LE1 of eac h L A B .
(5) The DATA1 and DATA2 input signals can supply counter enable, up or down control, or r egister feedback signals for
LEs other than the second LE in a LAB.
(6) The LAB-wide synchronous clear and LAB-wide synchronous load affect all registers in a LAB.
PRN
CLRN
DQ
4-Input
LUT
Carry-In (3)
Cascade-Out
Cascade-In LE-Out
Normal Mode (1)
PRN
CLRN
DQ
Cascade-Out
Cascade-In
3-Input
LUT
Carry-In
3-Input
LUT
Carry-Out
Arithmetic Mode
Counter Mode
d
ata1 (5)
d
ata2 (5)
PRN
CLRN
DQ
Carry-In
LUT
3-Input
3-Input
LUT
Carry-Out
data3
Cascade-Out
Cascade-In
LAB-Wide
Synchronous
Load (6)
LAB-Wide
Synchronous
Clear (6)
(4)
LE-Out
LE-Out
LE-Out
LE-Ou
t
LE-Ou
t
ENA
LAB-Wide
Clock Enable (2)
ENA
LAB-Wide
Clock Enable (2)
ENA
LAB-Wide
Clock Enable (2)
data1
data2
data1
data2
data3
data4
18 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Normal Mode
The normal mod e is s uitabl e for g eneral log ic a pplic ations , c ombi nator ial
function s, or wide decodin g funct ions that can take adv ant age of a
cascade chain. In normal mode, four data inputs from the LAB local
interconnect and the carry-in are inputs to a four-input LUT. The
Quartus II Compiler automatically selects the carry-in or the DATA3 signal
as one of the inputs to the L UT. T he LUT output can be c ombined with the
casca d e-in signal to form a cascade chain through t he ca sc ad e- o ut sig nal.
LEs in nor ma l mode su pport packed regi sters.
Arithmetic Mode
The arithmetic mod e is ideal for imp lementin g adders, accumul ators, and
comparat ors. An LE in arithm etic mode uses two 3-inp ut LUTs. One LUT
computes a three-inpu t function; the other generate s a ca rry o u tput. As
shown in Figure 8, the first LUT uses the carry-in signal and two data
inputs from the LAB local interconnect to generate a combinatorial or
registered output. For example, when implementing an adder, th is output
is the sum of th re e sign als : DATA1, DATA2, and carr y -in. T he sec ond LUT
uses the same three signals to genera te a car ry-out si gnal, the reby cre ating
a carry ch ain. The arithme tic mod e also supports si mu lta neo us use of t he
cascade chain. LEs in arith met ic mode can dri ve out registered and
unregistered versions of the LUT output.
The Quar tus II so ftware imple ments para meteriz ed functions tha t use the
arithmetic mode automatically where appropriate; the designer does not
need to specify how the carry chain will be used.
Counter Mode
The counte r mode offers clock enable, counter enable, synchronous
up/down co ntrol, synchron ous cle ar, and synchro nous load op tions. T he
counter enable and synchronous up/down control signals are generated
from the data inpu ts of the LAB local inter connect. The synch ronous clear
and synchronous load options are LAB-wide signals that affect all
registers in the LAB. Consequently, if any of the LEs in an LAB use the
counter mode, other LEs in that LAB must be used as part of the same
counter or be used for a combinatorial function. The Quartus II software
automatically places any registers that are not used by the counter into
other LA Bs.
Altera Corporation 19
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
The counter mode uses two three-input L UTs: one generates the counter
data, and the other generates the fast carry bit. A 2-to-1 multiplexer
provides synchronous loading, and another AND gate provides
syn chrono us cle ar ing . If the casc ade func tion is used b y an LE in count er
mode, the synchronous clear or load overrides any signal carried on th e
cascade chain. The synchronous clear overrides the synchronous load.
LEs in arithmetic mode can drive out registered and unregistered versions
of the LUT output.
Clear & Preset Logic Control
Logic for the re gis te r’s c lea r a nd p rese t sig na ls is controlled by L AB- wi de
signals. The LE directly supports an asynchronous clear function. The
Qua rtus II Com piler ca n use a NOT-g ate pu sh-b ack tech niqu e to emul ate
an asynchronous preset. Moreove r, the Quartus II Compiler can use a
programmable NOT-gate push-back technique to emulate simultaneous
preset and clear or asynchronous load. However, this t echnique uses three
additional LEs per register. All emulation is performed automatically
whe n the d esi gn i s com pi l ed . Reg i s ter s that emul ate si mu l t an eous preset
and load will enter an unknown sta te upon powe r-up or when the chip-
wide reset is asserted.
In ad dition t o the two cl ear and pres et mo des, APE X II devic es pr ovide a
chip-w ide reset pin ( DEV_CLRn) that rese ts all r egis ters i n the devic e. Use
of this pin is cont rolled throu gh an opti on in the Quartus II soft ware that
is set before compilation. The chip-wide reset overrides all other control
signals. Registers using an asynchronous preset are preset when the chip-
wide reset is assert ed; this effect results from the inversion technique used
to implement the async hronou s preset.
FastTrack Inte rconnect
In the APEX II architecture, connections between LEs, ESBs, and I/O pins
are p rovided b y th e FastTr ack i nterconn ect. The Fas tTrack in terconne ct is
a series of continuous horizontal and vertical routing channels that
traverse the device. This global routing structure provides predictable
performance, even in complex designs. In contrast, the segmented routing
in FPGAs requires switch matrices to connect a variable number of
routing paths, increasing the delays between logic resources and reduc ing
performance.
20 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
The FastTr ac k inter conn ect consists of row and column intercon nec t
channels that span the entire device. The row interconnect routes signals
throughout a row of MegaLAB structures; the column interconnect routes
signals throughout a column of MegaLAB structu res. When using the row
and column interconnect, an LE, IOE, or ESB can drive any other LE, IOE,
or ESB in a device. See Figure 9.
Figure 9. APEX II Interconnect Structure
A row line can be driven directly by LEs, IOEs, or ESBs in that row.
Further, a column line can drive a ro w line, allowing an LE, IOE, or E SB to
drive elements in a different row via the column and row interconnect.
The row interconnect drives the MegaLAB interconnect to drive LEs,
IOEs, or ES Bs in a particular MegaL AB structure.
MegaLAB MegaLAB MegaLAB MegaLAB I/O
I/O I/OI/OI/O
I/O
I/O
I/O
MegaLAB MegaLAB MegaLAB MegaLAB I/O
MegaLAB MegaLAB MegaLAB MegaLAB I/O
I/O I/OI/OI/O
Column
Interconnect
Row
Interconnect
Altera Corporation 21
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
A column line can be directly driven by the LEs, IOEs, or ESBs in that
column. Row IOEs can driv e a column line on a devic e’s left or right edge.
The column line is used to route signals from one row to another. A
column line can drive a row line; it can also drive the MegaLAB
interconnect directly, allowing faster connections between rows.
Figure 10 shows how the FastTrack interconnect uses the local
intercon ne ct to drive LEs withi n MegaLAB s tructures .
Figure 10. FastTra ck Co nnection t o Local Inte rconnec t
Figure 11 shows the inte rsection of a row and column interconnect and
how these forms of interconnects a nd LEs drive each other.
L
A
B
L
A
B
L
A
B
L
A
B
E
S
B
L
A
B
L
A
B
I/O
I/O
MegaLAB
Column
Row
MegaLAB
MegaLAB
Interconnect
Row & Column
Interconnect Drives
MegaLAB Interconnect
MegaLAB
Interconnect Drives
Local Interconnect
E
S
B
22 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Figur e 11. D rivin g t he Fast Track I nt erconnect
APEX II devices feature FastRowTM lines for quickly routing input signals
with high fan-out. Column I/O pins can drive the FastRow interconnect,
which rout es signals direct ly into the local int erconnect w ithout having to
drive th ro ugh the MegaLAB interconn ec t. FastRow lin es traverse two
MegaLAB structures. The FastRow interconnect drives the four
MegaLABs in the top row and the four MegaLA Bs in the bottom row of
the device. The FastRow interconnect drives all local interconnects in the
appropriate MegaLABs. Column pins using the FastRow interconnect
achieve a faster set-up time, because the signal does not need to use a
MegaLab interconnect line to reach the destination LE. Figure 12 shows
the FastRow interconnect.
LE
Column
Interconnec
t
Row
Interconnect
MegaLAB
Interconnect
Local
Interconnect
Altera Corporation 23
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Figure 12. APEX II Fast R ow I ntercon nec t
IOE IOE IOE IOE
FastRow Interconnect
Drives Local Interconnect
in Two MegaLAB Structures
MegaLAB MegaLAB
Local
Interconnect
Select Vertical I/O Pins
Drive Local Interconnec
t
and FastRow
Interconnect
FastRow
Interconnect
LEs
LABs
24 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Table 5 summarizes how elements of the APEX II architecture drive each
other.
Produc t- Term Logic
The product-term portion of the MultiCore architecture is implemented
with th e ESB. Th e ESB can be conf igured to act a s a block of macroce lls on
an ESB-by-ESB basis. 32 inputs from the adjacent local interconnect feed
each ESB; therefore, the either MegaLAB or the adjacent LAB can drive the
ESB. Al so, nine ES B macrocells feed back into the ES B thro ugh the local
intercon nect for higher performance. D edicate d clock pins, g lobal signals,
and additional inputs from the local interconnect drive the ESB control
signals.
In product-term mode, each ESB contains 16 macrocells. Each macrocell
consists of two product terms and a programmable registe r. Figure 13
shows the ESB in product -te rm mo de.
Table 5. APEX II R outing Sc hem e
Source Destination
Row
I/O Pin Column
I/O Pin LE ESB Local
Interconnect MegaLAB
Interconnect Row
FastTrack
Interconnect
Column
FastTrack
Interconnect
FastRow
Interconnect
Ro w I/O p i n vvvv
Co l u mn I/ O
pin
vv
LE vvvv
ESB vvvv
Local
interconnect
vvvv
MegaLAB
interconnect
v
Row
FastTrack
interconnect
v v
Column
FastTrack
interconnect
vv
FastRow
interconnect
v
Altera Corporation 25
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Figure 13 . Product-Term Logic i n ESB
Note ot Figure 13:
(1) PLL outputs cannot drive data input ports.
Macrocells
APEX II macrocells can be configured individually for either sequential or
combinatorial logic operation. The macrocell consists of three functional
blocks: the logic array, the product-term select matrix, and the
progra mma ble reg iste r.
Combinatorial logic is implemented in the product terms. The product-
term se lec t matr ix alloca te s th es e product terms for use as eithe r primary
logic inputs (to the OR and XOR gates) to implement combinatorial
functions, or as parallel expanders to be used to increase the logic
available to another macroce ll. One product term can be inverted; the
Quartus II software uses this feature to perform DeMorgan’s inversion for
more efficient implementation of wide OR functions. The Quartus II
Compiler can use a NOT-gate push-back technique to emulate an
asynchronous preset. Figure 14 shows the APEX II macrocell.
Global Signals
Dedicated Clocks
Macrocell
Inputs (1 to 16)
CLK[1..0]
ENA[1..0]
CLRN[1..0]
From
Adjacent
LAB
MegaLAB Interconnect
To Row
and Column
Interconnect
216
32
2
2
48
65
Local
Interconnect
9
(1)
26 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Figure 14. APEX II Macrocell
For registered functions, each macrocell register can be programmed
individually to implement D, T, JK, or SR operation with programmable
clock control. The register ca n be bypassed for combinatorial operat ion.
During design entry, the designer specifies the desired register type ; the
Quartus II s oftware then sel ects the most efficien t reg is ter operat ion for
each registered function to optimize resource utilization. The Quartus II
software or ot he r sy nth esi s t ools c an als o sele ct the most efficie nt re giste r
operation automatically when synthesizing HDL designs.
Each pro grammable register ca n be clocked by one o f two ESB-wide
clocks. The ESB-wide clocks can be generated from device dedicated clock
pins, global signals, or local interconnect. Each clock also has an
associated clock enable, generated from the local interconnect. The clock
and clock enable signals are related for a particular ESB; any macrocell
using a clock also uses the associated clock enable.
If both the rising and falling edges of a clock are used in an ESB, both
ESB-wide clock sign als are use d.
Clock/
Enable
Select
Product-
Term
Select
Matrix
Parallel Logic
Expanders
(From Other
Macrocells)
ESB-Wide
Clears ESB-Wide
Clock Enables ESB-Wide
Clocks
32 Signals
from Local
Interconnect Clear
Select
ESB
Outp
ut
Programmable
Register
222
ENA
D
CLRN
Q
Altera Corporation 27
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
The programmable register also supports an asynchronous clear function.
Within the ESB, two asynchronous clears are generated from global
signals and the local interconne ct. Each macrocell can either choose
between the two asynchronous clear signals or choose to not be cleared.
Either of the two clear signals can be inver ted within the ESB. Figure 15
shows the ESB control logic when implementing product-terms.
Figure 15. ESB Product-Term Mode Control Logic
Parallel Expanders
Parallel expand ers are unus ed pro du ct terms tha t can be alloca te d to a
neighboring macrocell to imple ment fast, complex logic functions.
Parall el expa nd e rs allow up to 32 produc t te rms to feed the macroc ell OR
logic directly, with two product terms provided by the macrocell and
30 parallel ex pan ders pr ovi ded by the ne ighbo ri ng macr oce lls in the ESB.
The Quartus II Compiler can allocate up to 15 sets of up to two parallel
expan ders per se t to the macro cells autom atical ly. Each se t of two pa ralle l
expanders incurs a small, i ncremental timing delay . Figure 16 shows the
APEX II parallel expand e rs.
CLK2 CLKENA2 CLK1 CLKENA1 CLR2 CLR
1
Dedicated
Clocks
Global
Signals
L
ocal
I
nterconnect
L
ocal
I
nterconnect
L
ocal
I
nterconnect
L
ocal
I
nterconnect
8
4
28 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Figure 16. APEX II Parallel Expanders
Embedded
System Block
The ESB ca n imple ment var iou s ty pe s of memory blo cks , inc luding Dua l-
Port+ RAM (bidirectional dual-port RAM), dual- and single-port RAM,
ROM, FIFO, and CAM blo cks.
The ESB includes input and output registers; the input registers
synchronize writes, and the output registers ca n pipeline designs to
improve system performance. The ESB offers a bidirectional, dual-port
mode, which supports any combination of two port operations: two reads,
two writes, or one read and one write at two different clock frequencies.
Figure 17 shows the ESB block diagram.
32 Signals from
Local Interconnect To Next
Macrocell
From
Previous
Macrocell
Product-
Term
Select
Matrix
Product-
Term
Select
Matrix
Macrocell
Product-
Term Logic
Macrocell
Product-
Term Logic
Parallel Expander
Switch
Parallel Expander
Switch
Altera Corporation 29
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Figure 17. Bi dir ectional Dual-Port Memory Con fig urat i on
In addition to bidirectional dual-port memory, the ESB also supports
dual-port, and single-port RAM. Dual-port memory supports a
simulta neo us re ad a nd wr ite. Single-po rt memory sup por ts indep en dent
read and wri te . Figure 18 show s these d ifferent RAM memory por t
configurations for an ESB.
Figure 18. Dual- & Single-Port Memory Configurations
Note to Figure 18:
(1) Two single - por t memo ry bl o cks can be impleme nted in a single ESB.
data
A
[ ]
address
A
[ ]
wren
A
clock
A
clocken
A
q
A
[ ]
aclr
A
data
B
[ ]
address
B
[ ]
wren
B
clock
B
clocken
B
q
B
[ ]
aclr
B
AB
data[ ]
wraddress[ ]
wren
inclock
inclocken
inaclr
rdaddress[ ]
rden
q[ ]
outclock
outclocken
outaclr
data[ ]
address[ ]
wren
inclock
inclocken
inaclr
q[ ]
outclock
outclocken
outaclr
Single-Port Memory
(1)
Dual-Port Memory
30 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
The ESB also enables variable width data ports for reading and writing to
the RAM por ts in dual-port RA M configuration. For example, th e ESB can
be wri tten in 1× mode at port A while being read in 16× mode from port B.
Table 6 lists the supported variable width configurations for an ESB in
dual-port mo de.
ESBs can implement synchronous RAM, which is easier to use than
asynchronous RAM. A cir cuit using asynchronous RAM must generate
the RAM write enable (WE) sign al while en suring th at its da ta and add ress
signals meet setup and hold time specifications relative to the WE signal.
In contrast, the ESB’s synchronous RAM generates its own WE signal and
is self-timed w ith resp ec t to the g lob al clock . Cir c uits usin g t he ESB ’s se lf-
timed RAM only need to meet the setup and hold time specifications of
the global clock.
ESB in puts are driv en b y the adjacent lo cal inter connect, w hich in t urn can
be driv en by the MegaLAB or FastTrack i nterconn ects. Because the ES B
can be driven by t he local inte rconnect, a n adjacent LE can drive it directly
for fast memory access. ES B out puts drive the MegaLAB and FastTrack
interconnects and the local interconnect for fast connection to adjacent LEs
or for fast feedback product-term logic.
When im plem enting m emory, each ESB can be config ured in any of the
following siz es: 512 × 8, 1,024 × 4, 2,04 8 × 2, or 4,0 96 × 1. For dual-port and
single-port modes, the ESB can be configured for 256 × 16 in addition to
the list above.
The ESB can also be split in half and used for two independent 2,048-bit
single-port RAM blocks. The two independent RAM blocks must have
identical configurations with a maximum width of 2 56 ×8. For ex ample,
one half of the E SB can be us ed as a 256 × 8 s ing le-por t memor y whil e t he
other half is also us e d for a 256 × 8 single-port memory. This effectively
doubles t he numb er of RAM block s an A PEX II dev ice c an imple men t fo r
its given number of ESBs. The Quartus II software automatically merges
two logical memory functions in a design into an ESB; the designer does
not need to merge the functions manually.
Tabl e 6. Vari a bl e Wi dt h Conf i gu r at i o ns fo r Dua l -Po r t RAM
Read Port Width Write Port Width
1 bit 2 bits, 4 bits, 8 bits , or 16 bits
2 bits, 4 bits, 8 bits, or 16 bits 1 bit
Altera Corporation 31
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
By combining multiple ESBs, th e Quartus II software implements larger
memory blocks aut omatically. For exampl e, two 256 × 16 RAM blocks ca n
be combined to form a 256 x 32 RAM block, and two 512 ×8 RAM blocks
can be combine d to for m a 5 12 × 16 RAM block. Memory performance
does not degrade for memory blocks up to 4,096 words deep . Each ESB
can impl ement a 4,096-word -deep memory; the ESBs are used in parallel,
eliminating the need for any external control logic that would increase
delays. To cr eate a high - speed m emory bloc k m ore tha n 4,09 6-wo rds
deep, the Quartus II software automatically combines ESBs with LE
control logic.
Input/Output Clock Mode
The ESB implements input/output clock mode for both dual-port and
bidire ctio nal d ual -port memory . An ESB us ing inpu t/out put cloc k mode
can use up to two clocks. On each of the two ports, A or B, one clock
controls all registers for inputs into the ESB: data input, WREN, read
address, and write address. The other clock controls the ESB data output
registers. Each ESB port, A or B, also supports in dep en dent read cloc k
ena ble, wr ite clock enable, and a synchronous clea r signa l s. In put /outp ut
clock mod e is commonly used for applica tions w here the rea ds and write s
occur at the same system frequency, but require different clock enable
signals for the input and output registers. Figure 19 shows the ESB in
input /output clock mode.
32 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Figure 19. ESB in Input/Output Clock Mode Note (1)
Notes to Figure 19:
(1) All register s ca n b e clea re d a synchro nously b y ESB l o cal int erconn ect signals, gl obal si gnals, or the chip-w ide re set .
(2 ) Thi s conf ig uration is not s upp o r t ed f o r bidir e c t iona l dua l-por t confi gurat ion.
Eight Dedicated Clocks
84
D
ENA Q
D
ENA
Q
D
ENA
Q
dataA[ ]
addressA[ ]
RAM/ROM
256 × 16
(2)
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
Data In
Address A
Write/Read
Enable
Data Out[]
Data In
Address B
Write/Read
Enable
Data Out[]
outclkenA
inclkenA
inclock
outclock
D
ENA Q
Write
Pulse
Generator
wrenA
Four Dedicated Inputs & Global Signals
qA[]
46
ENA
dataB[ ]
wraddressB
[ ]
outclkenB
inclkenB
inclock
outclock
Write
Pulse
Generator
wrenB
qB[]
ENA
ENA
ENA
AB
DQ
DQ
DQ
DQ
Altera Corporation 33
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
In addition to the input/output mode clocking sche me, the clock
connections to the various ESB input/output registers are customizable in
the MegaWi zard® Plug-In Manager.
Single-Por t M ode
The APE X II ESB also supports a single-port mode, which is used when
simulta ne ous rea ds and writes are not requ ired . See Figure 20. A single
ESB can support up to two single-port mode RAMs.
Figure 20. ESB in Single -Port Mode Note (1)
Note to Figure 20:
(1) A l l registers can be asynchronou sly cleared by ESB local interconnect signals, global signals, or chip-w ide reset.
Dedicated Clocks
84
D
ENA Q
D
ENA Q
D
ENA Q
D
ENA Q
data[ ]
a
ddress[ ]
RAM/ROM
256 × 16
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
Data In
Address
Write Enable
Data Out
outclken
inclken
inclock
outclock
Write
Pulse
Generator
wren
Dedicated Fast
Global Signals
To FastTrac
k
Interconnec
t
34 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Content-Addressable Memory
APEX II devices can implement CAM in ESBs. CAM can be thought of as
the inverse of RAM. RAM stores data in a specific loca t ion; when the
system submits an address, the RAM block provides the data. Conversely,
when the system submits data to CAM, the CAM block provides the
address where the data is foun d. For example, if the data FA12 is stored
in addr es s 14, the CAM outputs 14 when FA12 is driven into it.
CAM is used for high-speed search operations. When searching for data
within a RAM block, the search is performed serially. Thus, finding a
particul ar data word can ta ke man y cycles. CAM searc hes all add resses in
paralle l and out puts t he addres s storing a pa rticular w ord. Whe n a match
is found, a ma tch flag is set high. CAM is ideally suited for applications
such as Ethernet address lookup, data compression, pattern recognition,
cache tag s, fast routing table lookup, and high-bandwidth address
filtering. Figure 21 shows the CAM block diagram.
Fig ure 21. CAM Bl o ck Diagram
The APEX II on-chip C AM provides faster system performance than
traditional discrete CAM. Integrating CAM and logic into the APEX II
device eliminates off-chip and on-chip delays, improving system
performance.
When in CAM mod e, the ESB imple men ts a 32-w ord, 32-b it CAM. Wider
or deeper CAM, such as a 32-word, 64-bit or 128-word, 32-bit block, can
be impleme nt ed by combining multi ple CAM block s with some a ncil lary
logic implemented in LEs. The Quartus II software automatically
combines ESBs and LEs to create larger CAM blocks.
CAM supports writing “don’t care” bits into words of the memory. The
don’t- ca r e bit can be used as a m as k for CAM com pa risons; any bit set to
don’t- ca re has no effe ct on matches.
data[ ]
wraddress[ ]
wren
inclock
inclocken
inaclr
data_address[ ]
match
outclock
outclocken
outaclr
Altera Corporation 35
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
CAM can generate outputs in three different modes: single-match mode,
multiple-match mode, and fast multiple-match mode. In each mode, the
ESB outputs the ma tc h ed data’s loca tio n as an encoded o r unencoded
ad dre ss. Whe n e ncod ed, the ESB ou tput s an enc ode d a ddre ss o f t he data ’s
locat ion. For instance, if the dat a is locate d in address 12, the ESB output
is 12. When unencoded, each ESB port uses its 16 outputs to show the
locat ion of the data over two clo ck cycles. In this case, if th e data is located
in address 12, the 12th output line g oes hig h. Figures 21 and 22 show the
encoded CAM outputs and unencode d CAM outpu ts , respectively.
Figure 22. Encoded CAM Add ress Outputs
Figure 23. Unenco ded CAM A ddress Outputs
Notes to Figures 22 and 23:
(1) For an unencoded output, the ESB only supports 31 input data bits. One input bit
is us ed by the select line to choose on e of the two ban k s of 16 ou tpu t s.
(2) If the select input is a 1, then CAM outputs odd words between 1 through 15. If
the select input is a 0, CAM outputs even words between 0 through 14.
In single-match mode, it takes two clock cycles to write into CAM, but
only one clock cycle to read from CAM. In this mode, both encoded and
unencoded outputs are available without external logic. Single-match
mode is better suited for designs without duplicate data in the memory.
CAM
data[31..0] = 45 addr[15..0] = 12 Encoded Outp
ut
match = 1
AddressData
10
11
12
13
15
27
45
85
CAM
data[30..0] =45 (1)
select (2)
q0
Unencoded outputs.
q12 goes high to
signify a match.
q12
q13
q14
q15
AddressData
10
11
12
13
15
27
45
85
36 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
If the same data is written into multiple locations in the memory, a CAM
block can be used in multiple-match or fast multiple-match modes. The
ESB outpu ts the matched dat a’s locati ons as an en coded or unencoded
address. I n multi ple -match mod e, it takes two c lock cycle s to writ e int o a
CAM block . For r eading, th ere ar e 16 outp uts from ea ch ES B at each c lock
cycle. Therefo re, i t tak es tw o clo ck cycles to represent the 32 words from
a single ESB p ort. In this mod e, en coded and unencoded outputs are
available. To implement the encoded version, the Quartus II softw are
adds a prior ity enco de r wi th L Es. Fast mult iple -match is identi cal t o the
multiple ma tch mode , h owe ver, it on ly ta kes one clock cy cle t o re ad from
a CAM block and gener ate v alid outputs. To do this , the en tire ESB is used
to represent 16 outputs. In fast multiple-match mode, the ESB can
implement a maximum CAM block size of 16 words.
A CAM bl ock ca n be p re- loa ded w i th data d uring confi gura tion, or it can
be written during system operation. I n most cases, two clock cycles are
required to write each word into CAM. When don’t-care bits are used, a
third clock cycle is required.
fFor more information on CAM, see Application Note 119 (Implementing
High-S peed Search Applications with APEX CA M) .
Drivi ng Si gnals to the ESB
ESBs provide flexib le option s for d riving cont r ol sig nals. D iffere nt c lock s
can be used for the ESB inputs and outputs. Registers can be inserted
independently on the data input, data output, read address, write
address, WE, a nd RE s ign als . The g lobal sig nals an d the l oca l inte r con nect
can driv e the WE and RE signa ls. The glo bal sig na ls, d edic at ed clock pins,
and local interconnects can drive the ESB clock signals. Because the LEs
drive th e local intercon nect, the LEs can co ntrol the WE and RE signals an d
the ESB clock, clock enable, and synchronous cle ar signals. Figure 24
shows the ESB control signal generation logic.
Altera Corporation 37
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Figure 24. ESB Contro l Si gnal Ge neration
An ESB is fed by the local interconnect, which is driven by adjacent LEs
(for high -spe ed co nnecti on to the E SB) or the M ega LAB i nter conn ect. T he
ESB can drive the local, MegaLAB, or FastTrack interconnect routing
structure to drive LEs and IOEs i n the same MegaLAB structure or
anywhere in the device.
Implementing Logic in ROM
In addition to implementing logic with product terms, the ESB can
implement logic functions when it is programmed with a read-only
pattern during configuration, creating a large LUT. With LUTs,
combinatorial functions are implemented by looking up the results, rather
than b y compu ting them. T his implementat ion of combinator ial functions
can be faster than using algorithms implemented in general logic, a
performance advantage that is further e nha nced by the fast access times
of ESBs. The large capacity of ESBs enables designers to implement
complex functions in one logic level without the routing delays associated
with linked LEs or distributed RAM blocks. Parameterized functions such
as LPM functions can take advantage of the ESB automatically. Further,
the Quartus II software can implement portions of a design with ESBs
where appro priate.
RDEN WREN INCLOCK
INCLKENA
OUTCLOCK
OUTCLKENA
Dedicated
Clocks
Fast Global
Signals
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
8
4
Local
Interconnect
Local
Interconnect INCLR OUTCL
R
38 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Programmab le Sp eed/ Po wer C ontro l
APEX II E SB s offe r a high-spe ed m od e tha t su ppor t s fast operation on a n
ESB-by-ESB basis. When high speed is not required, this feature ca n be
turned off to reduce the ESB’s power dissipation by up to 50%. ESBs th a t
run at low pow er incur a nominal timing delay adde r. This Turbo BitTM
option is available for ESBs that implement product-term logic or memory
functions. An ESB that is not used will be powered down so that it does
not consume DC current.
Design er s can program each ESB in the APEX II d evice for either high-
speed or low-power operation. As a result, spe ed-critical pa ths in the
design can run at high sp e ed, while the remaining paths operate at
reduced power.
I/O Structure The IOE in APEX II devices con tains a bidirectional I/O buffer, six
regis te rs, and a latch for a complete embe dded bidirectional single data
rate or DDR IOE. Figure 25 shows the structure of the APEX II IOE. The
IOE contains two input registers (plus a latch), two output registers, and
two outp ut enable r egisters . Both in put regist ers and th e latch can be used
for capt ur ing D DR inp ut. Both output r egis te rs c an b e us ed t o d rive DD R
outputs. The output enable (OE) register can be used for fast clock-to-
output enable timing. The negative edge-clocked OE register is used for
DDR SDRAM interfacing. The Quartus II software automatically
duplicat es a single OE register that controls multiple output or
bidirectional pins.
Altera Corporation 39
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Figure 25. APEX II IOE Structure
The IOEs are locate d ar ound the periph ery o f the APEX II device. Each
IOE drive s a row, colu mn, MegaL AB, or local int ercon ne ct when use d as
an inp ut or bidirectiona l pin. A r ow IOE can drive a loca l, MegaLAB, row ,
and column interconnect; a column IOE can drive the FastTrack or column
interconnect. Figure 26 shows how a row IOE connects to the
interconnect.
DQ
Output Register
Output A
DQ
Output Register
DQ
OE Register
OE
DQ
OE Register
DQ
Input Register
DQ
Input Register
DQ
Input Latch
Logic Array
CLK
ENA
Output B
Input A
Input B
40 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Figure 26. Row IOE Connection to the Interconnect
Figure 27 shows how a column IOE connects to the interconnect.
Row Interconnect MegaLAB Interconnect
Any LE can drive a
pin through the row,
column, and MegaLAB
interconnect.
An LE can drive a pin through the
local interconnect for faster
clock-to-output times.
IOE
IOE
Each IOE can drive local,
MegaLAB, row, and column
interconnect. Each IOE data
and OE signal is driven by
the local interconnect.
LAB
Altera Corporation 41
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Figure 27. Column I O E Connection to the Interconnec t
FastRow interconnec ts connect a colu mn I/O pin dire ctly to the LAB l ocal
interconnect within two MegaLAB structures. This feature provides fast
setup time s for pins that drive high fan-outs with complex logic, such as
PC I designs. For fast bidirecti ona l I/ O tim in g , LE reg ist ers using l ocal
routing can improve setup times and OE timing.
APEX II devices have a peripheral control bus made up of 12 signals that
drive the IOE control signals. The peripheral bus is composed of six
output enables, OE[5:0] and six clock enab les, CE[5:0]. Th ese twelv e
signals can be driven from internal logic or from the Fast I/O signals.
Table 7 lists the peripheral control signal destinations.
Row Interconnect
Column Interconnec
t
Each IOE can drive column and FastRow
interconnects. Each IOE data and
OE signal is driven by local interconnect.
Any LE or ESB can drive
a column pin through a
row, column, and MegaLAB
interconnect.
IOE IOE
LAB
An LE or ESB can drive a
pin through a local
interconnect for faster
clock-to-output times.
MegaLAB Interconnect
42 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
In norma l bidi rectiona l operati on, t he inpu t regist er can be used for input
data requiring fas t se tup tim e s. T he input reg ist er can have its own clock
input and clock enable separate from the OE and output registers. The
output register can be used for data requiring fast clock-to-output
performan ce. The OE r egiste r can be used fo r fast clock-to-output ena b le
timing. The OE and output register share the same clock source and the
same clock enable source from local interconnect in the associated LAB,
fast global signals, or row global signals. Figure 28 shows the IOE in
bidirectional configuration.
Table 7. Peripheral Control Bus Destina t ions
Peripheral Bus I/O Control Signal
Output Enable 0 [OE0] OE
Output Enable 1 [OE1] OE
Output Enable 2 [OE2] OE
Output Enable 3 [OE3] OE
Output Enable 4 [OE4] OE
Output Enable 5 [OE5] OE
Clo ck Enable 0 [CE0] CE, CLK
Clo ck Enable 1 [CE1] CE, OE
Clo ck Enable 2 [CE2] CE, CLK
Clo ck Enable 3 [CE3] CE, OE
Clo ck Enable 4 [CE4] CE, CLR
Clo ck Enable 5 [CE5] CE, CLR
Altera Corporation 43
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Figure 28. APEX II IOE in Bidirectio nal I/O Configuratio n
The APE X II IOE includes programmable delays that can be activated to
ensure zero hold times, minimum clock-to-output times, input IOE
register-to-logic array register transfers, or logic array-to-output IOE
register transfers.
CLRN/PRN
DQ
ENA
Chip-Wide Reset
OE Register
CLRN/PRN
DQ
ENA
Output Register
VCCIO
VCCIO
Optional
PCI Clamp
Programmabl
e
Pull-Up
Column, Row
or Local
Interconnect
12 Peripheral
Signals
Eight
Dedicated
Clocks
Bus-Hold
Circuit
Output Clock
Enable Delay
Logic Array
to Output
Register Delay
Output
tZX Delay
OE Register
tCO Delay
Output
Pin
Delay
CLRN/PRN
DQ
ENA
Input Register
Input Clock
Enable Delay
Input Pin to
Input Register Delay
Input Pin to
Logic Array Delay
Drive Strength Control
Open-Drain Output
Slew Control
44 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
A path in which a pin directly drives a registe r may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinatorial logic may not require the delay. Programmable
delays e xis t for decre as ing inp ut pin to log ic a rr ay an d IO E input registe r
delays. Th e Quartus I I Comp iler can pr og ram th ese dela ys auto matic all y
to min imi ze se tup time while providi ng a ze r o hold t im e. Delays are al so
program mable for increa sing the registe r to pin de lays for o utput and/ or
output enable registers. A programmable delay exists for increasing the
tZX delay to the output pin, w hich is required for ZBT interfaces. Table 8
shows the programmable delays for APEX II devices.
Note to Table 8:
(1) This delay has four settings: off and three levels of delay.
The IO E registers in APEX II d ev ice s sha re the sa me sour ce f or cl ear or
prese t. The desi gne r can pr ogram preset and clear f or each individual
IOE. The registers can be p ro grammed to power up high or low after
configuration is complete. If programmed to power up low, an
asynchronous clear can control the registers. If programmed to power up
high, an asynchronous preset can control the registers. This feature
prevents the inadvertent activation of another device’s active-low input
upon power-up. If one register in an IOE uses a preset or clear signal then
all registers in the IOE must use that preset or clear signal.
Double Data Rate I/O
APEX II devices hav e six-re gister IOEs w hich su pport DDR i nterfaci ng by
clocking data on both positive and ne gative clock edges. The IOEs in
APEX II devices support DDR inputs, DDR outputs, and bidirectional
DDR modes.
Table 8. APEX II Programmable D el ay C hain
Programma ble Delays Quar tus II Logic Optio n
Input pin to log ic arr ay de lay (1) Decreas e input delay to inte rnal c ells
Input pin to inp ut reg is ter delay Decreas e input delay to input regis t er
Output propagation delay Increas e delay to outp ut pin
Output enable regist er tCO delay Increas e delay to outp ut en able pin
Output t ZX del ay I ncreas e tZX delay to output pin
Output clo ck enable dela y Increas e out put clock enable delay
Input clock enable delay Increas e input clo ck enable dela y
Logic arra y to out put regis te r delay Decreas e input delay to out put regis te r
Altera Corporation 45
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
When using the IOE for DDR inputs, the two input registers are used to
clock double rate input data on alternating edges. An input latch is also
used within the IOE for DDR input acquisition. T he latch holds the data
that is prese nt during the clock high times. This allow s both bits of data to
be s ync hronous to the sa me cloc k edg e (ei the r r isi ng or fa llin g). Figure 29
shows an IOE configured for DDR input.
Figure 29 . APEX II IO E in DDR Input I/O Co nfiguration
When using the IOE for DDR outputs, the two output registers are
config ur ed to clock tw o da ta pat hs from LEs on r isin g clo ck edge s. The se
register outputs are multiplexed by the clock to drive the output pin at a
×2 rate . O ne outp ut r egister clocks th e fi rst bi t out on the clock high tim e,
while the other output register clocks the second b it out on the clock low
time. Figure 30 shows the I OE conf igured f or DDR output.
Chip-Wide Reset
Input Register
Input Register
VCCIO
VCCIO
Optional
PCI Clamp
Programmable
Pull-Up
C
olumn, Row
or Local
Interconnect
12 Peripheral
Signals
Eight
Dedicated
Clocks
Bus-Hold
Circuit
Input Clock
Enable Delay
Latch
Input Pin to Input
Register Delay
CLRN/PRN
DQ
ENA CLRN/PRN
DQ
ENA
CLRN/PRN
DQ
ENA
46 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Figure 30. APEX II IOE in DDR Output I/O Configuration
The APEX II IOE operates in bidirectional DDR mode by combining the
DDR input and DDR output configurations.
APEX I I I/O pins transfer d ata on a DDR bidirect ional b us t o suppo rt
DDR SDRAM at 167 MHz (334 Mb ps). The negative-edge-clocked OE
regist er is us ed to hol d the OE sig nal in active until the falling edg e of the
clock. This is done to meet DDR SDRAM timing requirements. QDR
SRAMs a re also s upported w ith DD R I/O pins on separat e read an d write
ports.
CLRN/PRN
DQ
ENA
Chip-Wide Reset
OE Register
CLRN/PRN
DQ
ENA
OE Register
CLRN/PRN
DQ
ENA
Output Register
VCCIO
VCCIO
Optional
PCI Clamp
Programmabl
e
Pull-Up
Column, Row
or Local
Interconnect
12 Peripheral
Signals
Eight
Dedicated
Clocks
Bus-Hold
Circuit
Output Clock
Enable Delay
Logic Array
to Output
Register Delay
Output
tZX Delay
OE Register
tCO Delay
Output
Propagation
Delay
CLRN/PRN
DQ
ENA
Output Register
Logic Array
to Output
Register Delay
Drive Strength Control
Open-Drain Output
Slew Control
Used for
DDR SDRAM
clk
Altera Corporation 47
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Zero Bus Turnaround S R A M Int er face Su ppor t
In addition to DDR SDRAM support, APEX II device I/O pins also
support interfacing with ZBT SRAM devices at up to 200 MHz. ZBT
SRAM blocks are designed to elimina t e dead bus cycles whe n turning a
bidirectional bus around between reads and writes, or writes and reads.
ZBT allows for 100% bus utilization because ZBT SRAM can be read or
written on every clock cycle.
To avoid bus contention, the output clock-to-low-impedance time (tZX)
delay ensures that the tZX is greater than the clock-to-high-impedance
time (tXZ). Phase delay control of clocks to the OE/output and input
registers using two general-purpose PLLs enable the APEX II device to
meet ZBT tCO and tSU times.
Programmable Drive Strength
The output buffer for each APEX II device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL standard has
several levels of drive strength that the user can control. SSTL-3 class I
and II, SSTL-2 class I and II, HSTL class I and II, 3.3-V GTL+, PCI, and
PCI-X support a minimum setting. The minimum setting is the lowest
drive strength that guarantees the IOH/IOL of the standard. Using
minimum settings provides signal slew rate control to reduce system
noise and signal overshoot. Table 9 shows the possible setti ngs for the I/O
standards with drive strength cont ro l.
48 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Open-Dr ain Out put
APEX II devices provide an optional open-drain (eq uivalent to an open-
collector) output for each I/O pin. This open-drain output enables the
device to provide system-level control signals (e.g., interrupt and write-
enable signals) that can be asserted by any of several devices.
Slew-Rate Control
The output buffer for each APEX II device I/O pin has a programmable
output slew rate control that can be configured for low-noise or high-
speed performance. A faster slew rate provides high-speed transitions for
high-performance systems. However, these fast transitions may introduce
noise transients into the system. A slow slew rate reduces system noise,
but ad ds a nomina l d elay t o ri s ing a nd fa llin g edges . E a ch I/O pin ha s an
individua l slew rate control, allow ing the design er to specify the slew r ate
on a pin-by-pin basis. T he slew rate control affects both the rising and
falling edges.
Table 9. Programmable Drive Strength
I/O Standard IOH/IOL Current Strength
Setting
LVT TL (3. 3 V) 4 mA
12 mA
24 mA (de fau lt)
LVT TL (2. 5 V) 2 mA
16 mA (de fau lt)
LVT TL (1. 8 V) 2 mA
8mA (de fau lt)
LVTTL (1.5 V) 2 mA (default)
SSTL-3 class I and II
SSTL-2 class I and II
HSTL class I and II
GTL+ (3.3 V)
PCI
PCI-X
Minimum (default)
Altera Corporation 49
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Bu s H o ld
Each APEX II device I/O pin provides an optional bus-hold feature. When
this feature is e nabled for an I/O p in, the bus -hold ci rcuitry we akly holds
the signal a t its l ast dr iven st ate. By h olding th e las t driven s tate of the pin
until the next input signal is present, the bus-hold feature eliminat e s the
need to add ex te rnal pull-up or pull-d ow n resistors to hold a signal leve l
when th e bus is tri-st ated. T he bus -hold ci rcuitry a lso pulls undrive n pins
away from the input thr eshold vo ltage w here noise can c ause unin tend ed
high-frequency switching. This feature can be selected individually for
each I/O pin. The bus-hold output will drive no higher than VCCIO to
prevent overdriving signals. If the bus-hold feature is enabled, the
programmable pull-up option cannot be used. The bus-hold feature
should also be disable d if open-drain ou tputs are use d with the GTL+ I/O
standard.
The bu s-hold cir cuitry weakly pulls the sig nal level to the la st driven sta te
thr ough a resist or with a nominal res istance (R BH) of approximately 7 kΩ.
Table 41 on page 74 gives specific sustaining current that will be driven
through thi s resistor and overdrive current that w i ll identify the ne xt
driven input level. This information is provided for each VCCIO voltage
level.
The bus-hold circuitr y is active only after configu ration. Whe n going into
use r mod e, the bus-hold ci r cuit captures t he value o n the pin pres ent at
the end of configuration.
Programmable Pull-Up Resistor
Each AP EX II device I/O pin pr ovides an optional p rogrammable pull-up
resistor during user mode. When this feature is enabled for an I/O pin, the
pull-up resistor (typically 25 kΩ) weakly holds the output to the VCCIO
level of the bank that the output pin resides in.
Dedicated Fas t I/O Pins
APE X II d e vice s in cor pora te ded ica te d bidir e cti onal pins for sig na ls w ith
high internal fanout, such as PCI control sig nals. These pins are called
dedicated fast I/O pins ( FAST1, FAST2, FAST3, and FAST4) and can
drive the four g lobal fast lines throughout the device, ideal for fast clock,
clock enable, preset, clear, or high fanout logic signal distribution. The
dedicated fast I/O pins have one output register and one OE register, but
they do not have input registers. The dedicated fast lines can also be
driven by a LE local interconnect to generate internal global signals.
50 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Advanc ed I/ O Sta ndar d S upport
APEX II device IOEs support the following I/O standards:
■LVTTL
■LVCMOS
■1.5-V
■1.8-V
■2.5-V
■3.3-V PCI
■3.3-V PCI-X
■3.3-V AGP (1×, 2×)
■LVDS
■LVPECL
■PCML
■HyperTransport
■GTL+
■HSTL class I and II
■SS T L-3 class I and II
■SS T L-2 class I and II
■CTT
■Differential HSTL
Altera Corporation 51
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Table 10 descri bes the I/O stand ar ds supported by APEX II devices.
Note to Table 10:
(1) Differential HSTL is only supported on th e eight dedicated global clock pins and four dedicated high-speed PLL
clock pins.
fFor more informat i o n on I/O standards sup ported by AP EX II devices,
see Application Note 117 (Using Se lectable I/O Standards in Altera Devic es).
APEX II devices contain eight I/O bank s, as shown in Figure 31. Two
blocks within t he right I/O bank s contai n circ uitry to s upport high-sp eed
True -LV DS, LVPE CL, PCML, and HyperT r an sport inputs, and anothe r
two blocks within the left I/O banks support high-speed True-LVDS,
LVPECL, PC ML, an d HyperTr an spo rt outputs . Al l other standards are
supported by all I/O banks.
Table 10. APEX II Supported I/O Standards
I/O Standard Type Input
Reference
Voltage (V REF)
(V)
Output
Supply
Voltage
(VCCIO) (V)
Board
Termination
Voltage
(VTT) (V)
LVTTL Single-ended N/A 3.3 N/A
LVCMOS Single-ended N/A 3.3 N/A
2.5 V Single-ended N/A 2.5 N / A
1.8 V Single-ended N/A 1.8 N / A
1.5 V Single-ended N/A 1.5 N / A
3.3-V PCI Single-ended N/A 3.3 N / A
3.3-V PCI -X Single-ended N/A 3.3 N / A
LVDS Differential N/A 3.3 N/A
LVPECL Differential N/A 3.3 N/A
PCML Differential N/A 3.3 N/A
HyperTransport Differential N/A 2.5 N/A
Differential HSTL (1) Differential N/A 1.5 N/A
GTL+ Voltage referenced 1.0 N/A 1.5
HSTL cla ss I and II Voltage refer enc ed 0.75 1.5 0.75
SSTL-2 class I and II Voltage referenced 1.25 2.5 1.25
SSTL-3 class I and II Voltage referenced 1.5 3.3 1.5
AGP (1× and 2×) Voltage referenced 1.32 3.3 N/A
CTT Voltage referenced 1.5 3.3 1.5
52 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Figure 31. APEX II I/O Banks
Notes to Figure 31:
(1) Fo r more infor matio n o n placing I/O pin s withi n LVDS blocks , r e fer to t he “ High- Spee d In te r f ac e Pin Locat io n ”
sect io n in Applica tio n No te 166 (U s i ng High -S pee d I/ O Stan da rd s in A P EX II Device s).
(2) If the True-LVDS pins or the F lexible-LVDS p in s are no t used for high -sp eed differential signallin g , they ca n
support all of the I/O standards and can be used as input, output, or bidirectional pins with VCCIO set t o 3. 3 V, 2 .5 V,
1.8 V, or 1.5 V. However, True-LVDS pins do not support the HSTL Class II output.
Each I /O bank has its own VCCIO pins. A single d evice can sup port 1.5- V,
1.8-V , 2.5-V, and 3.3 -V in terf aces; each bank can suppor t a di fferent
standard independently. Each bank can also use a separate VREF level to
support any one of the terminated standards (such as SSTL-3)
independently.
(1)
(1)
Regular I/O Pins Support
■
3.3-V, 2.5-V, 1.8-V, and
1.5-V LVTTL
■
3.3-V PCI and PCI-X
■
GTL+
■
AGP
■
SSTL-2 Class I and II
■
SSTL-3 Class I and II
■
HSTL Class I and II
■
CTT
Individual
Power Bus
I/O Bank 1 I/O Bank 2
I/O Bank 3
I/O Bank 4
True-LVDS, LVPECL,
PCML, and HyperTransport
Output Block (2)
True-LVDS, LVPECL,
PCML, and HyperTransport
Output Block (2)
True-LVDS, LVPECL,
PCML, and HyperTransport
Input Block (2)
True-LVDS, LVPECL,
PCML, and HyperTransport
Input Block (2)
(1)
(1)
I/O Bank 8
I/O Bank 7
I/O Bank 5I/O Bank 6
I/O banks 1 and 2 support Flexible-LVDS,
HyperTransport, and LVPECL inputs, and
regular I/O pin standards.
I/O banks 5 and 6 support Flexible-LVDS and
HyperTransport outputs and regular I/O pin standards.
Altera Corporation 53
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Each b ank can supp ort multip le standa rds with the same VCCIO for input
and output pins. Each bank can su pport one voltage-referenced I/O
sta ndard, but it ca n support mult iple I/O stan dards with the same VCCIO
voltage level. For example, when VCCIO is 3.3 V, a b ank can support
LVTTL, LVCMOS, 3.3-V PC I, an d SSTL-3 for inputs and ou tputs. When
the True-LVDS banks are not used for LVDS I/O pins, they support all of
the o the r I/O s tandards ex cep t HST L Clas s II ou tput.
True- LVDS Int erfac e
APEX II devices contain dedi ca ted circuit ry fo r sup porting differential
standards at spee ds up to 1.0 Gbps. APEX II devices ha ve dedicated
differentia l buffe rs and circuitry to support LVDS, LVPECL,
HyperTransport, and PCML I/O standards. Four dedicated high-speed
PLLs (sepa rate from the general-p urpose PLLs) multip ly reference clock s
and drive high-speed differential serializer/deserializer channels. In
addition, CDS circuitry at each receiver channel corrects any fixed clock-
to-data skew. All APEX II devices support 36 input channels, 36 output
channels, tw o dedicated receiver PLLs, and tw o dedicated transmitter
PLLs.
The True-LVDS circuitry supports the following standards and
applications:
■RapidIO
■POS-PHY Level 4
■Utopia IV
■HyperTransport
APEX II devices support source-synchronous interfacing with LVDS,
LVPECL,P CML, or Hype rTransport signa ling at up to 1 Gbps. S eri al
chan ne ls are trans mitte d and rece ive d along wit h a low-spe ed clock. The
rece iving device then multi plies the clock by a factor of 1, 2, or 4 to 10. The
serialization/deserialization rate can be any number from 1, 2, or 4 to 10
and does not have to equal the clock multiplication value.
For example, an 840-Mbps LVDS channel can be received along with an
84-MHz clock. The 84-MHz clock is multiplied by 10 to drive the serial
shift r egist er, but the r egi ste r c an b e cloc ked out in pa r all el at 8 - or 1 0-b it s
wid e at 84 or 105 MH z. See Figures 32 and 33.
54 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Figure 32. True-LVDS Receiver Diagram Notes (1), (2)
Notes to Figure 32:
(1) Two sets of 18 receiver channels are located in each APEX II device. Each set of 18 channels has one receiver PLL.
(2) W = 1, 2, 4 to 10
J = 1, 2, 4 to 10
W does not hav e to equa l J. Whe n J = 1 or 2, the dese r ial ize r is by passe d. W he n J = 2, DDR I/O registers are use d.
(3) These clock pins dri ve recei ver P LLs only. The y do not dri ve dire ctl y to the l ogic array. H owever, the re ceiver PLL
can drive the logic array via a global clock line.
+
–
Receiver
Channel
+
–
Receiver
Channel
+
–
Receiver
Channel
R
X_CLK1
(3)
Receiver
PLL1
×W
W
J
Deserializer Data to
LEs
To Glob
al
Clock
Receiver Channel 1
Receiver Channel 18
Receiver Channel 2
J Bits Wide
×
Altera Corporation 55
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Figure 33. True-LVD S Transmitter Diagram Notes (1), (2)
Notes to Figure 33:
(1) Two sets of 18 transmitter channel s are locate d in each APEX II device. Each se t of 18 channe l s has one transmitte r
PLL.
(2) W = 1, 2, 4 t o 10
J = 1, 2, 4 t o 10
W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, DDR I/ O r egisters ar e u s ed .
Clock-Data Synchronization
In addit ion to dedica ted serial-to-pa rallel conve rters, APEX II True-LVDS
circuitry contains CDS circuitry in every receiver channel. The CDS
feature can be turned on or off independently for each receiver cha n nel.
There are two modes for the CDS circuitry: single-bit mode, which
corrects a fixed clock-to-data skew of up to ±50% of the da ta bit pe riod,
and multi-bit mode, which corrects any fixed clock-to-data skew.
Transmitter
Channel
G
lobal Clock
f
rom Receiver
o
r System Clock Transmitter
PLL1
×W
W
J
Serializer Data fro
m
LEs
Transmitter Channel 1
J Bits Wide
T
ransmitter
C
hannel Transmitter Channel 2
T
ransmitter
C
hannel Transmitter Channel 18
T
XOUTCLOCK1
×
56 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Single-Bit Mode
Single-bit CDS corrects a fixed clock-to-data skew of up to ±50% of the
data bit period, which allows receiver input skew margin (RSKM) to
increas e by 50% of the data period. To use single-bit CDS, the
deserial ization fac tor, J, must be equal to t he mult iplicatio n facto r, W. The
combination of allowable W/J factors and the associated CDS training
patte r ns aut om ati cally determi ne byte alig nm en t (s ee Table 11).
Multi-Bit Mode
Multi-bit CDS corr e cts any fixed cloc k-t o-data skew . This fe at ur e enable s
flexible board topologies, such as an N:1 topology (see Figure 34), a switch
topology, or a matrix topology. Multi-bit CDS corrects for the skews
inherent with these topologies, making them possible to use.
Table 11. Single-Bit CDS Training Patterns
W/J Fa ctor Single-Bit CDS Pattern
10 0000011111
9000001111
800001111
70000111
6000111
500011
40011
Altera Corporation 57
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Figure 34. Multi-Bit CD S Supports N:1 Topology
When usin g multi-bit CDS, the J and W factors do not need to be the same
value. The byte boundary cannot be distinguished with multi-bit CDS
patterns (see Table 12). Therefor e, the byte must be aligned usin g inte rnal
logic. Table 12 shows the possible training patterns for multi-bit CDS.
Either pattern can be used.
Pre-Programmed CDS
When the fixed clock-to-data skew is known, CDS can be pre-
programmed into the device during configuration. If CDS is pre-
programmed into the device, the training patterns do not need to be
transmitted to the receiver channels. The resolution of each pre-
progra mmed set ting is 25% of the data period , to compen sate for sk ew up
to ± 50% of the data period.
Table 12. Multi-Bit CDS Pa tterns
W Factor J Fac tor Multi-Bit CDS Pattern
1, 2, 4 to 10 4 to 10 3 × J-bits of 010101 pattern
1, 2, 4 to 10 4 to 10 3 × J-bits of 101010 pattern
APEX II
Device
APEX II
Device APEX II
Device
APEX II
Device
Clock
Clock
Clock
Clock
Data Data
58 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Pre-programmed CDS may also be used to resolve clock-to-data skew
gr eater than 50% of the bit period. However, internal logic must be used
to implement the byte alignment circuitry for this operation.
Flexible-LVDS I/O Pins
A subset of pins in the top two I/O banks supports interfacing with
Flexible-LVDS, LV PE CL, and HyperTra nsport inputs. These
Flexible-LVDS input pins include de di cated LVDS , LVPECL, and
HyperTransport input buffers. A subset of pins in the bottom two I/O
banks supp orts inte r fac ing with Flexible -L VDS and HyperT ran sport
outputs. These Flexible-LVDS output pins include dedicated LVDS and
HyperT ransport outpu t buffers. The Flexibl e-LVDS pins do not require
any external components except for 100-Ω termination resis tor s on
receiver channels. These pi ns do not contain dedicated
serialization/deserialization circuitry; therefore, internal logic is used to
perform serialization/deserialization functions.
The EP2A15 and EP2A25 devices support 56 input and 56 output
Flexible-LVD S channe ls. The EP2A4 0 and larger devic es support 88 input
and 88 output Flexible-LVDS channels. All APEX II devices support the
Flexible-LVDS interface up to 400 Mbps (DDR) per channel. Flexible-
LVDS pins along with the True-LVDS pins provide up to 144-Gbps total
device bandwidth. Table 13 shows the Flexible-LVDS timing
specification.
MultiVolt I/O
Interface
The APEX II architecture supports the MultiVolt I/O interface feature,
which all ows APEX II dev ices in all pa ckages to interface with syst ems of
different supp ly volta g es. The devices have one set of VCC pins for
internal ope ration and input buffers (VCCINT), and another set fo r I/O
output driv ers ( VCCIO).
Table 13. APEX II Flexible-LVDS Tim ing Spe cification
Symbol Timing Parameter Definition Speed Grade Unit
-7 -8 -9
MinMaxMinMaxMinMax
Data Rate Maximu m op erat ing s peed 400 311 311 Mbps
TCCS Transm itter c hannel-to-c hannel
skew 700 900 900 ps
SW Receiver sampling window 1,100 1,400 1,400 ps
Altera Corporation 59
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
The APEX II VCCINT pins must always be connected to a 1.5-V power
supply. With a 1. 5-V VCCINT level, input pins are 1.5-V, 1.8- V, 2.5 -V and
3.3-V tolerant . The VCCIO pins can b e co nne cted to eit her a 1.5-V, 1.8-V,
2.5-V or 3.3-V power supply, depending on the output requirements. The
output levels are compatible with systems of the same voltage as the
power supply (i.e., when VCCIO pins are connected to a 1.5-V power
supply, the output levels are compatible with 1.5-V systems). Whe n
VCCIO pins are connected to a 3.3-V power supply, the output high is
3.3 V and is comp atible with 3.3- V or 5.0 -V syste m s.
Table 14 summarizes APEX II MultiVolt I/O support.
Notes to Table 14:
(1) The PCI clamping diode must be disabled to drive an input with voltages higher than VCCIO, except for with a 5.0-V
input.
(2) These input levels are only allowed if the input standard is set to any VREF standard (i.e., SSTL-3, SSTL-2, HSTL,
GTL+, and AGP 2×). The VREF standard inputs are powered by VCCINT. LVTTL, PCI, PCI-X, and AGP 1× standard
inputs are powered by VCCIO. As a res ult, input le v els below t he VCCIO setting cannot drive these standards.
(3) When VCCIO = 1.8 V, an AP E X II device c an d ri ve a 1. 5-V device with 1.8 -V tol er an t in pu ts .
(4) When VCCIO = 2.5 V, an AP EX II device c an d riv e a 1. 5-V or 1.8- V dev i c e with 2.5-V to le ra nt inputs.
(5) APEX II devices can be 5.0-V tolerant with the use of an external seri es resistor and enabling the PCI clamping diode.
(6) When VCCIO = 3.3 V, an AP EX II device c an d riv e a 1. 5-V , 1.8-V, or 2.5- V device wi t h 3.3-V t ole ra nt in p uts .
Open-drain output pins with a pull-up resistor to the 5.0-V supply and a
seri es reg ister to t he I/ O pin can drive 5.0-V CMO S input pi ns that requir e
a VIH of 3 .5 V. When the pin is in active , the trac e will be p ulled up to 5 .0 V
by the resistor. The open-drain pin will only drive low or tri-state; it will
never drive high. The rise time is dependent on the value of the pull-up
resistor and load impedance. The IOL current spe cification should be
considered when selecting a pull-up resistor.
Power
Sequenc i ng &
Hot Socketing
Because APEX II devices can be used in a mixed-voltage environment,
the y have been d esign ed spec ifica lly for any p ossibl e power- up sequ ence.
Therefore, the VCCIO and VCCINT power supplie s may be powere d in any
order.
Table 1 4. APEX II Mu ltiVolt I/O Support Note (1)
VCCIO (V) Input Signal Output Signal
1.5 V 1.8 V 2 .5 V 3.3 V 5.0 V 1.5 V 1.8 V 2.5 V 3.3 V 5 .0 V
1.5 vvvv v
1.8 v (2) vvv v (3) v
2.5 v (2) v (2) vv v (4) v (4) v
3.3 v (2) v (2) vv
v (5) v (6) v (6) v (6) vv
60 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Signals can be driven into APEX II devices before and du ring power-up
withou t da maging the device. In addition, APEX II devices do not dri v e
out during power-up. Once operating conditions are reached an d the
device is configured, APEX II devices operate as specified by the user.
General-
P urpose PLLs
APEX II devices have ClockLock, ClockBoost, an d ClockShift features,
which use four general-purpose PLLs (separate from the four dedicated
True-LVDS PLLs) to provide clock management and clock-frequency
synthesis. These PLLs allow designers to increase performance and
provi de cl ock -frequency synthesis. The PLL reduces the clock delay
within a device. This reduction minimizes clock-to-output and setup
times while maintaining zero hold times. The PLLs, which provide
programmable multiplication, allow the designer to distribute a low-
speed cl ock and mult iply tha t cloc k on -devic e. A PEX II devic es includ e a
high-speed clock tree: unlike ASICs, the user does not have to design and
optimize the clock tree. The PLLs work in conjunction with the APEX II
device’s hig h-sp eed c lock to provide signific ant improve men ts in sy ste m
perfor man ce and bandwidt h .
The PLL s in APEX II dev ices are enab led throug h the Quartu s II softwa re.
Ext ernal d evices ar e not requir ed to us e thes e feat ures. Table 15 shows the
general -purp o se PLL features for APEX II devices. Figure 35 shows an
APEX II ge neral-purpose PLL.
Figure 35. APEX II General-Purpose PLL Note (1)
Table 15. APEX II General-Purpose PLL Features
Numb er of PLL s ClockBoost
Feature Number of External
Clock Out puts N um ber of
Feed ba ck In puts
4m/(n × k, v) 8 2
m
n
k
v
Phase
Comparator Voltage-Controlled
Oscillator
i
nclock
f
bin
clock
0
clock
1
Phase Shift
Circuitry
Altera Corporation 61
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Note to Figure 35:
(1) n repre sents the pr escal e divi der f or the PLL input. m represents the multiplier. k and v represent the dif ferent post
scale dividers for the two possible PLL outputs. m and k are integers th at ra nge fr om 1 to 160. n and v ar e in tegers
that range from 1 to 16.
Advanced ClockBoost Multiplication & Division
APEX II PLLs include circuitry that provides clock synthesis for eight
internal outputs and two external outputs using m/(n × output divider)
sca ling. When a PLL is loc ked, the locked ou tput cloc k aligns to the ris ing
edge of th e input clock. The closed loop equation for Figure 35 gives an
outpu t freque ncy fclock0 = (m/(n × k))fIN an d fclock1 = (m/(n × v))fIN. Thes e
equation s allow the multiplication or division of clocks by a
programmable number. T he Quartus II software automatically chooses
the appr opriate scalin g factors accor ding to the frequenc y, multiplica tion,
and division values entered.
A single PLL in an APEX II device allows for multiple user-defined
multipl ication and d ivision ratios th at are not pos sible eve n with mult iple
delay-locked loops (DLLs). For example, if a frequency scaling factor of
3.75 is needed for a given input clock, a multiplication factor of 15 and a
division factor of 4 can be entered. This advanced multiplication scaling
can be performed with a single PLL, making it unnecessary to cascade
PLL outputs.
External Clock Outputs
APEX II devices have tw o low-jitter external clocks available for external
clock sources. Other devices on the board can use these outputs as clock
sources.
The re ar e thr e e mode s for ex ternal cloc k outputs.
■Zero Delay Buffer: The external clock output pin is phase aligned
with the clock input pin for zero delay. Multiplication,
programmable phase shift, and time delay shift are not allowed in
this configuration. The MegaWizard inte rface for altclklock
should be used to verify possible clock settings.
■External Feedback: The external feedback input pin is phase aligned
with clock input pin. By aligning these clocks, you can actively
remove clock delay and skew between devices. This mode has the
same restrictions as zero dela y buff er mode .
■Normal Mode: The external clock output pin will have phase delay
relative to the clock input pin. If an internal clock is used in this mode,
the IOE register clock will be phase aligned to the input clock pin.
Multiplication is allowed with the normal mode.
62 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
ClockShift Circuitry
General-purpose PLLs in APEX II devices have ClockShift circuitry that
provides programmable phase shift. Users can enter a phase shift (in
degrees or time units) that affects all PLL outputs. Phase shifts of 90°, 180°,
and 270° can be implemented exactly. Other values of phase shifting, or
delay shifting in time units, are allowed with a resolution range of 0.5 ns
to 1.0 ns. This resolut ion varies wit h frequency inp ut and the us er-ente red
multiplica tion and division fa ctors. The phase shift ability is only possibl e
on a multiplied or divided clock if the input and output frequency have
an integer multiple relationship (i.e., fIN/fOUT or fOUT/fIN must be an
integer).
Clock Enable Signal
APEX II PLLs have a CLKLK_ENA pin for enabling/disabling all device
PLLs. When the CLKLK_ENA pin is high, the PLL drives a clock to all its
output port s. When the CLKLK_ENA pin is low , the clock0, clock1, and
extclock ports are driven by GND and all of the PLLs go out of lock.
When the CLKLK_ENA pin goe s high again, the PLL relocks.
The individual enable port for each PLL is programmable. If more than
one PLL is inst antia ted, each one does not have to use the clock enable . To
enable/disable the device PLLs with the CLKLK_ENA pin, the inclocken
port on the altclklock instanc e must be co nne cte d to the CLKLK_ENA
input pin.
Lock Si gnals
The APEX II de vice PLL circuits support i ndividual LOCK signal s. Th e
LOCK signal drives high when the PLL has locked onto the input clock .
LOCK rema ins high as long as the input remains within specification. It
will go low if the input is out of specification. A LOCK pin is optional for
each PLL used in the APEX II devices; when not used, they are I/O pins.
This sign al is not availab le internally; if it is used in th e logic array, it mus t
be fed back in with an input pin.
SignalTap
Embedded
Logic Analyzer
APEX II devices include device enhancements to support the SignalTap
embedded logic analyzer. By including this circuitry, the APEX II device
provides the ability to monitor design operat ion over a period of time
throug h the IEEE Std. 11 49.1 (JTAG) circuitry; a desi gner can ana l yze
interna l logic at spe ed without bringin g inte r nal signa ls to the I/O pins .
This feature is particularly important for advanced packages such as
FineLine BGA packages because adding a connection to a pin during the
debugging process ca n be difficult a fter a board is designed and
manufactured.
Altera Corporation 63
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
All APEX II devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1-1990 speci f i cation. JTAG bo undary-scan te sting can be
perfor med before or after config urat ion, bu t not during config urat ion.
APEX II device s can also use the JTAG port for configuration with the
Quartus II software or with hardware using either JamTM Sta nd ard Test
and Progra mming Language (ST APL) Files ( .jam) or Jam Byte-Code Files
(.jbc). Finally, APEX II devices use the JTAG port to monitor the logic
operation of the device with the Sign alTap embedded logic analyzer.
APEX II devices support the JTAG instructions shown in Table 16.
Note to Table 16:
(1) Bus hol d and w eak pu ll -up features overrid e the high -im pedanc e stat e of HIGHZ, CLAMP, an d EXTEST.
The APEX II device instruction register length is 10 bits. The APEX II
device USERCODE register length is 32 bits. Tables 17 and 18 show th e
boundary-scan register length and device IDCODE i n for mat i o n for
APEX II devices.
Table 16. APEX I I JTAG Instructions
JTA G Inst ruc t io n Des cri pt ion
SAMP LE/ PR ELOAD Allows a snaps hot of signa ls at the dev ice pins to be capt ured and exam ined during
normal device operation, and permits an initial data pattern to be output at the device pins.
Also used by the SignalTap em bedded logic ana lyzer.
EXTEST (1) Allows the external circuitry and board-level interconnections to be tested by forcing a test
pattern at the output pins and capturing test results at the input pins.
BYPASS Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through selected devices to adjacent devices during normal device
operation.
USERC OD E Selects the 32-bit US ER CO D E regis t er and places it between the TDI and TDO pins,
allowin g th e USE R CO D E to be serially shifted out of TDO.
IDCO DE Selec ts the IDCO D E regis t er and places it between TDI and TDO, allowing the IDCODE
to be serially shi fted out of TDO.
HIGHZ (1) Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through selected devices to adjacent devices during normal device
operat ion, wh ile tri -stat ing all of th e I/O pins .
CLAMP (1) Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through selected devices to adjacent devices during normal device
operat ion w hile holding I/O pins to a state def ined by the data in th e boundary-s ca n
register.
ICR instr uc tio ns Used wh en co nf iguring an APE X II dev ice via the JTAG port with a Ma sterBlaste rTM or
ByteBlasterMVTM download cable, or when using a Jam File or Jam Byte-Code File via an
embedded processor.
SignalTap
instructions Monitors internal device operation with the SignalTap embedded logic analyzer.
64 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Notes to Tables 17 and 18:
(1) The most significant bit (MSB) is on the left.
(2 ) The IDCOD E ’ s leas t signi fic a n t bit (LSB) is alway s 1 .
Figure 36 shows the timing r equirements for the JTAG sig nals.
Table 17 . APEX II JTAG Boun dary-Scan R egister Lengt h
Device Boundary-Scan Register Length
EP2A15 1,524
EP2A25 1,884
EP2A40 2,328
EP2A70 3,228
Table 18 . 32 -Bit APEX II Device I DCOD E
De vice IDCODE (32 B it s) (1)
Version
(4 Bits) Part Numbe r (16 Bits ) Ma nu facturer
Identity (11 Bits) 1 (1 Bit)
(2)
EP2A15 0000 1100 0100 0000 0000 000 0110 1110 1
EP2A25 0000 1100 0110 0000 0000 000 0110 1110 1
EP2A40 0000 1101 0000 0000 0000 000 0110 1110 1
EP2A70 0000 1110 0000 0000 0000 000 0110 1110 1
Altera Corporation 65
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Figure 36. APEX II JTAG Waveforms
Table 19 shows the JTAG timing parameters and values for APEX II
devices.
Tabl e 19 . APEX I I JTAG Timin g Pa r ameters & Val ues
Symbol Parameter Min Max Unit
tJCP TCK clock per iod 100 ns
tJCH TCK clock hig h time 50 ns
tJCL TCK clock low time 50 ns
tJPSU J T AG port setup ti me 20 ns
tJPH JTAG port hold time 45 ns
tJPCO JTAG port clock to output 25 ns
tJPZX J T AG port high im pedance to valid output 25 ns
tJPXZ J T AG port valid outp ut to high im pedance 25 ns
tJSSU C apture regis t er se tu p time 20 ns
tJSH Ca ptu re regis t er hold time 45 ns
tJSCO U pdate regis t er clo ck to outp ut 35 ns
tJSZX U pdate regis t er high im pedance t o vali d out put 35 ns
tJSXZ U pdate regis t er va lid out put to hig h imp edance 35 ns
TDO
TCK
tJPZX tJPCO
tJPH
tJPXZ
tJCP tJPSU
tJCL
tJCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
tJSZX
tJSSU tJSH
tJSCO tJSXZ
66 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
fFor more information, see the following documents:
■Appl ication Note 39 (IEEE Std . 1149.1 (JTAG) Bounda r y-Scan Testin g in
Altera Devices)
■Jam Pr og ramming & Test Language Specification
Generic Testin g Each APEX II device is functionally tested. Complete testing of each
configurable static random access memory (SRAM) bit and all logic
functionality ensures 100% yield. AC test measurements for APEX II
devices are made under conditions equivalent to those shown in
Figure 37. Multiple test patterns can be used to configure devices during
all stages of the production flow. AC test criteria include:
■Power supply transients can affect AC measurements.
■Simultaneous transitions of multiple outputs should be avoided for
accurate measurement.
■Threshold tests must not be performed under AC conditions.
■Large-amplitude, fast-ground-current transients normally occur as
the device outputs discharge the load capacitances. When these
trans ie nts flow thr oug h the par asi tic ind uct ance betw ee n the device
ground pin and the test system ground, significant reductions in
observable noise immunity can result.
Figure 37. APEX II AC Test Conditions
Operating
Conditions
APEX II de vices are offered in both commercial and indus trial grades.
Howev er, i ndustrial- gr ad e devic es may have limite d spee d-gr ad e
availability.
Syste
m
C1 (includes
jig capacitance)
Device input
rise and fall
times < 3 ns
D
evice
O
utput To Te
st
Altera Corporation 67
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Tables 20 through 41 provid e i nformat ion on absol ute maximum r ating s,
recommended operating conditions, and DC operating conditions for
1.5-V APEX I I d e vices.
Table 2 0. APEX II Dev ice Absolu te Maximu m Ra tings Notes (1), (2)
Symbol Parameter Conditions Minimum Maximum Unit
VCCINT Suppl y volt age With respect to ground (3) –0.5 2.4 V
VCCIO –0.5 4.6 V
VIDC input vo lta ge –0.5 4. 6 V
IOUT DC output cur rent , pe r pin –25 25 m A
TSTG Sto rage t em perature N o bias –65 150 ° C
TAMB Am bient te mp erat ure Under bias –65 135 ° C
TJJun ction temper atu re BGA packa ges under bias 135 ° C
Table 2 1. APEX II Dev ice Recomme nded Operating Conditions
Symbol Parameter Conditions Minimum Maximum Unit
VCCINT Supply volta ge fo r inte rnal logic
and input buffers (4) 1.425 1.575 V
VCCIO Supply voltage for output buffers,
3.3-V operation (4), (5) 3.00 (3.135) 3.60 (3.465) V
Supply voltage for output buffers,
2.5-V operation (4) 2.375 2.625 V
Supply voltage for output buffers,
1.8-V operation (4) 1.71 1.89 V
Supply voltage for output buffers,
1.5-V operation (4) 1.4 1.6 V
VIInput vo lta ge (3), (6) –0.5 4.1 V
VOOutp ut volt age 0 VCCIO V
TJOperating junction temperature For commercial
use 085° C
For industrial use –40 100 ° C
tRInput rise time 40 ns
tFInput fall time 40 ns
68 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Table 22. APEX II D evice DC Op erat i ng Condi t ions Note (7)
Symbol Parameter Conditions Minimum Typical Maximum Unit
IIInput pin leakage
current VI = VCCIO to 0 V (8) –10 10 µA
IOZ Tri-stated I/O pin
leakage current VO = VCCIO to 0 V (8) –10 10 µA
ICC0 VCC supply current
(standby) (All ESBs
in power- dow n
mode)
VI = ground, no load,
no togglin g input s , -7
speed gra de
10 mA
VI = ground , no loa d,
no togglin g input s , -8,
-9 speed gra des
5mA
RCONF Value of I/O pin pull-
up resistor before
and during
configuration
VCCIO = 3. 0 V (9) 20 50 kΩ
VCCIO = 2.375 V (9) 30 80 kΩ
VCCIO = 1.7 1 V (9) 60 150 kΩ
Table 23 . LVTTL Specific ations
Symbol Parameter Conditions Minimum Maximum Units
VCCIO Outpu t supply vo lta ge 3.0 3.6 V
VIH High-level input voltage 1.7 4.1 V
VIL Low-level input voltage –0.5 0.8 V
IIInput pin leak age current VIN = 0 V or VCCIO –5 5 µA
VOH High-level output voltage IOH = –4 to –24 mA (10) 2.4 V
VOL Low-level output voltage IOL = 4 to 24 mA (10) 0.45 V
Table 24 . LVCMOS Spec i f ications
Symbol Parameter Conditions Minimum Maximum Units
VCCIO Outpu t supply vo lta ge 3.0 3.6 V
VIH High-level input voltage 1.7 4.1 V
VIL Low-level input voltage –0.5 0.7 V
IIInput pin leak age current VIN = 0 V or VCCIO –10 10 µA
VOH High-level output voltage VCCIO = 3.0,
IOH = –0.1 mA VCCIO – 0.2 V
VOL Low-level output voltage VCCIO = 3.0,
IOL = 0.1 mA 0.2 V
Altera Corporation 69
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Table 25. 2.5-V I/O Specification s Note (10)
Symbol Parameter Conditions Minimum Maximum Units
VCCIO Output supply voltage 2.375 2.625 V
VIH High -lev el input voltage 1. 7 4.1 V
VIL Low -lev el input voltage –0.5 0.7 V
IIInput pin leaka ge c urrent VIN = 0 V or VCCIO –10 10 µA
VOH High -lev el out put vo lta ge IOH = –0.1 mA 2. 1 V
IOH = –1 mA 2.0 V
IOH = –2 to –16 mA 1. 7 V
VOL Low -lev el out put vo lta ge IOL = 0.1 mA 0.2 V
IOL = 1 mA 0.4 V
IOL = 2 to 16 mA 0.7 V
Table 26. 1.8-V I/O Specification s
Symbol Parameter Conditions Minimum Maximum Units
VCCIO Output supply voltage 1.65 1.95 V
VIH High -lev el input voltage 0.6 5 × VCCIO 4.1 V
VIL Low -lev el input voltage –0.5 0.35 × VCCIO V
IIInput pin leaka ge c urrent VIN = 0 V or VCCIO –10 10 µA
VOH High -lev el out put vo lta ge IOH = –2 to –8 mA (10) VCCIO – 0.45 V
VOL Low -lev el out put vo lta ge IOL = 2 to 8 mA (10) 0.45 V
Table 27. 1.5-V I/O Specification s
Symbol Parameter Conditions Minimum Maximum Units
VCCIO Output supply voltage 1.4 1.6 V
VIH High -lev el input voltage 0.6 5 × VCCIO 4.1 V
VIL Low -lev el input voltage –0.5 0.35 × VCCIO V
IIInput pin leaka ge c urrent VIN = 0 V or VCCIO –10 10 µA
VOH High -lev el out put vo lta ge IOH = –2 mA (10) 0.75 × VCCIO V
VOL Low -lev el out put vo lta ge IOL = 2 mA (10) 0.25 × VCCIO V
70 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Table 28. 3 .3-V PCI Spe cificat ion s
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO Outpu t supply vo lta ge 3.0 3. 3 3. 6 V
VIH High-level input voltage 0.5 ×
VCCIO
VCCIO +
0.5 V
VIL Low-level input voltage –0.5 0.3 ×
VCCIO
V
IIInput pin leak age current 0 < VIN < VCCIO –10 10 µA
VOH High-level output voltage IOUT = –500 µA0.9 ×
VCCIO
V
VOL Low-level output voltage IOUT = 1,500 µA0.1 ×
VCCIO
V
Table 29. P CI-X Spec ifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO Outpu t supply vo lta ge 3.0 3. 6 V
VIH High-level input voltage 0.5 ×
VCCIO
VCCIO +
0.5 V
VIL Low-level input voltage –0.5 0.35 ×
VCCIO
V
VIPU Input pull-up voltage 0.7 ×
VCCIO
V
IIL Input leakage current 0 < VIN < V CCIO –10 10 µA
VOH High-level output voltage IOUT = –500 µA0.9 ×
VCCIO
V
VOL Low-level output voltage IOUT = 1,500 µA0.1 ×
VCCIO
V
LPIN Pin induc tance 15 nH
Table 30. GTL+ I/O Specificati on s
Symbol Parameter Conditions Minimum Typical Maximum Units
VTT Termination voltage 1.35 1.5 1.65 V
VREF Referenc e v olt age 0.88 1.0 1.12 V
VIH High-level input voltage VREF + 0.1 V
VIL Low-level input voltage VREF – 0. 1 V
VOL Low-level output voltage IOL = 36 mA (10) 0.65 V
Altera Corporation 71
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Table 31. SSTL-2 Class I Speci fications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO Output supply voltage 2.375 2.5 2.625 V
VTT Termination volta ge VREF – 0.0 4 VREF VREF + 0. 04 V
VREF Reference voltage 1.15 1.25 1.35 V
VIH High -lev el input voltage VREF + 0.18 3. 0 V
VIL Low -lev el input voltage –0.3 VREF – 0.1 8 V
VOH High -lev el out put vo lta ge IOH = –7.6 m A
(10) VTT + 0.57 V
VOL Low -lev el out put vo lta ge IOL = 7.6 mA (10) VTT – 0.57 V
Table 3 2. SSTL- 2 Class II Spe cifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO Output supply voltage 2.3 2.5 2.7 V
VTT Termination volta ge VREF – 0.0 4 VREF VREF + 0. 04 V
VREF Reference voltage 1.15 1.25 1.35 V
VIH High -lev el input voltage VREF + 0.18 VCCIO + 0.3 V
VIL Low -lev el input voltage –0.3 VREF – 0.1 8 V
VOH High -lev el out put vo lta ge IOH = –15 .2 mA
(10) VTT + 0.76 V
VOL Low -lev el out put vo lta ge IOL = 15.2 mA
(10) VTT – 0.76 V
Table 33. SSTL-3 Class I Speci fications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO Output supply voltage 3.0 3.3 3.6 V
VTT Termination volta ge VREF – 0.0 5 VREF VREF + 0. 05 V
VREF Reference voltage 1.3 1.5 1.7 V
VIH High -lev el input voltage VREF + 0 .2 VCCIO + 0.3 V
VIL Low -lev el input voltage –0.3 V REF – 0. 2 V
VOH High -lev el out put vo lta ge IOH = –8 mA (10) VTT + 0. 6 V
VOL Low -lev el out put vo lta ge IOL = 8 m A (10) VTT – 0.6 V
72 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Table 34 . SSTL-3 Class II Speci f ications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO Outpu t supply vo lta ge 3. 0 3.3 3. 6 V
VTT Termination voltage VREF – 0.05 VREF VREF + 0. 05 V
VREF Referenc e v olt age 1. 3 1. 5 1. 7 V
VIH High-level input voltage VREF + 0.2 VCCIO + 0.3 V
VIL Low-level input voltage –0.3 VREF – 0.2 V
VOH High-level output voltage IOH = –16 mA
(10) VTT + 0.8 V
VOL Low-level output voltage IOL = 16 mA (10) VTT – 0.8 V
Table 35 . 3.3-V AG P 2× Specificatio ns
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO Outpu t supply vo lta ge 3.1 5 3.3 3.45 V
VREF Referenc e v olt age 0. 39 × VCCIO 0.41 × VCCIO V
VIH High-level input voltage
(11) 0.5 × VCCIO VCCIO + 0.5 V
VIL Low-level input voltage (11) 0.3 × VCCIO V
VOH High-level output voltage IOUT = –20 µA0.9 × VCCIO 3.6 V
VOL Low-level output voltage IOUT = 20 µA0.1 × VCCIO V
IIInput pin leak age current 0 < VIN < VCCIO –10 10 µA
Table 36 . 3.3-V AG P 1× Specificatio ns
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO Outpu t supply vo lta ge 3.1 5 3. 3 3. 45 V
VIH High-level input voltage
(11) 0.5 × VCCIO VCCIO + 0.5 V
VIL Low-level input voltage (11) 0.3 × VCCIO V
VOH High-level output voltage IOUT = –20 µA0.9 × VCCIO 3.6 V
VOL Low-level output voltage IOUT = 20 µA0.1 × VCCIO V
IIInput pin leak age current 0 < VIN < VCCIO –10 10 µA
Altera Corporation 73
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Table 3 7. 1.5-V HSTL Class I Specificatio ns
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO Output supply voltage 1.4 1.5 1.6 V
VREF I nput referenc e voltage 0. 68 0.75 0.9 V
VTT Termination vo lta ge 0.7 0.75 0.8 V
VIH (DC) D C high-level input vo lta ge VREF + 0 .1 V
VIL (DC) DC low-lev el input voltage –0.3 V REF – 0. 1 V
VIH (AC) AC hig h-lev el input voltage VREF + 0.2 V
VIL (AC) AC low-level input voltage VREF – 0. 2 V
VOH High -lev el out put vo lta ge IOH = 8 mA (10) VCCIO – 0.4 V
VOL Low -lev el out put vo lta ge IOL = –8 mA (10) 0.4 V
Table 3 8. 1.5-V HSTL Class II Specificatio ns
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO Output supply voltage 1.4 1.5 1.6 V
VREF I nput referenc e voltage 0. 68 0.75 0.9 V
VTT Termination vo lta ge 0.7 0.75 0.8 V
VIH (DC) D C high-level input vo lta ge VREF + 0 .1 V
VIL (DC) DC low-lev el input voltage –0.3 V REF – 0. 1 V
VIH (AC) AC hig h-lev el input voltage VREF + 0.2 V
VIL (AC) AC low-level input voltage VREF – 0. 2 V
VOH High -lev el out put vo lta ge IOH = 16 mA (10) VCCIO – 0.4 V
VOL Low -lev el out put vo lta ge IOL = –16 mA
(10) 0.4 V
Table 39. 1.5-V Differe ntial HSTL Specifica tions
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply voltage 1.4 1 .5 1.6 V
VDIF (DC) DC input dif fer ent ial
voltage 0.2 V
VCM (DC) DC common mode input
voltage 0.68 0.9 V
VDIF (AC) AC differential input
voltage 0.4 V
74 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Notes to Tables 20 – 41:
(1) See the Operat ing Requirements for Altera Devices Data Sheet.
(2) Conditions beyond those listed in Table 20 may cause permanent damage to a device. Additionall y, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
(3) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to - 2 V or overshoot to 4.6 V for input
currents less than 100 mA and per iods sh or ter than 20 n s.
(4) Maxi mu m VCC rise time is 100 ms, and VCC must rise monotonically.
(5) VCCIO maximum and minimum conditions for LVPECL, LVDS, RapidIO, and PCML are shown in parentheses.
(6) All pins, i ncluding dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(7 ) Typ ic al va lues ar e for TA = 25° C, VCCINT = 1.5 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, an d 3.3 V.
(8) This v alue is sp ec ified for n or mal dev ice operation . The val ue may v ar y d u ri n g powe r- up.
(9) Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO.
(10) Dri ve strength is programmable according to values in Table 9 on page 48.
(11) VREF specifies the center point of the switching range.
Table 40 . CTT I/O Spec i fications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO Outpu t supply vo lta ge 3. 0 3.3 3. 6 V
VTT/VREF Termination and input
reference voltage 1.35 1.5 1.65 V
VIH High-level input voltage VREF + 0.2 V
VIL Low-level input voltage VREF – 0.2 V
IIInput pin leak age current 0 < VIN < VCCIO –10 10 µA
VOH High-level output voltage IOH = –8 mA VREF + 0.4 V
VOL Low-level output voltage IOL = 8 mA VREF – 0.4 V
IOOutpu t leakage current
(when outp ut is high Z)GN D ð V OUT ð
VCCIO
–10 10 µA
Table 41. Bus Hold Para meters
Parameter Conditions VCCIO Level Un i ts
1.5 V1.8 V2.5 V3.3 V
Min Max Min Max Min Max Min Max
Low sustaining
current VIN > VIL
(maximum) 30 50 70 µA
High sustaining
current VIN < VIH
(minimum) –30 –50 –70 µA
Low overdrive
current 0 V < VIN <
VCCIO
200 300 500 µA
High overdriv e
current 0 V < VIN <
VCCIO
–200 –300 –500 µA
Altera Corporation 75
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Figures 38 and 39 show receive r input and transmitter output wave forms,
respective ly, for al l differen tial I/O standards (LV DS, 3.3-V PCML,
LVPECL, and Hy pe rTransport te chnology).
Figure 38. Receiver Input Waveforms for Differential I/O Standards
Figure 39. Transmitte r Output Waveforms for Differential I/O Standards
Note to Figure 39:
(1) VSS: steady-state differential output voltage.
Tables 42 through 45 provid e i nformat ion on absol ute maximum r ating s,
recommended operating conditions, and DC operating conditions for
1.5-V APEX I I d e vices.
Single-Ended Waveform
Differential W aveform
Positive Channel (p) = VIH
Negative Channel (n) = VIL
Ground
±VID
+VID
− VID
VID (Peak-to-Peak)
VCM
p − n = 0 V
Single-Ended Waveform
Differential W aveform
Positive Channel (p) = VOH
Negative Channel (n) = VOL
Ground
±VOD
+VOD
− VOD
VSS
(1)
p − n = 0 V
VCM
76 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Table 42. 3.3-V LV D S I /O S pecification s
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supp ly volt age 3.13 5 3.3 3.465 V
VOD Differe nt ial out put vol tag e RL = 100 Ω250 850 (1) mV
∆ VOD Change in VOD bet w een
high and low RL = 100 Ω50 mV
VOS Outpu t Offset vo lta ge RL = 100 Ω1.125 1.25 1.375 V
∆ VOS Change in VOS bet w een
high and low RL = 100 Ω50 mV
VTH Differe nt ial input th res hold VCM = 1.2 V –100 100 mV
VIN Receiv er input voltage
range 0.0 2.4 V
RLReceiv er dif fe rent ial input
resistor (external to
APEX II devices)
90 100 110 Ω
Table 43. 3 .3-V PCML Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supp ly volt age 3.13 5 3.3 3.465 V
VIL Low-level input voltage VCCIO –
0.3 V
VIH High-level input voltage VCCIO V
VOL Low-level output voltage VCCIO –
0.6 VCCIO –
0.3 V
VOH High-level output voltage VCCIO VCCIO –
0.3 V
VTOutpu t term inat ion voltage VCCIO V
VOD Differe nt ial out put vol tag e 300 450 600 mV
tRRise time (20 to 80%) 85 325 ps
tFFall time (20 to 80%) 85 325 ps
ROOutput load 100 Ω
RLReceiv er dif fe rent ial input
resistor 45 50 55 Ω
Altera Corporation 77
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Notes to Tables 42 – 45:
(1) Maximum VOD is measur ed un der static cond iti on s .
(2) When APEX II devices drive LVPECL signals, the APEX II LVPECL outputs must be terminated with a resistor
network.
Capacitance Table 46 an d Figure 40 provide informat ion on APEX II device
capacitance.
Table 44. LVPECL Spe cificat ion s Note (2)
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I / O sup ply voltage 3.135 3.3 3 .4 65 V
VIL Low -lev el input voltage 800 2,000 mV
VIH High -lev el input voltage 2,100 VCCIO mV
VOL Low -lev el out put vo lta ge 1,450 1,650 mV
VOH High -lev el out put vo lta ge 2,275 2,420 mV
VID Diffe rent ial input voltage 100 600 2,5 00 mV
VOD Diffe rent ial output volt age 625 800 970 mV
tRRise ti me (20 to 80%) 85 325 ps
tFFall time (20 to 80%) 85 325 ps
Table 45. HyperTransport Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I / O sup ply voltage 2.375 2.5 2 .6 25 V
VOD Diffe rent ial output volt age 380 600 820 mV
VOCM Output common mode
voltage RTT = 100 Ω500 600 700 mV
VID Diffe rent ial input voltage 300 600 900 mV
VICM I nput comm on m ode
voltage 450 600 750 mV
RLReceiv er dif f erential input
resistor 90 100 110 Ω
78 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Note to Table 46:
(1) See Figure 40.
Figure 40. APEX II Maximum Input & Output Pin Capacita nce
Table 46. APEX II Device Capacitance
Symbol Parameter Conditions Minimum Maximum Unit
CIN Input cap ac ita nc e VIN = 0 V ,
f = 1.0 MHz (1) pF
CINCLK I nput cap ac ita nc e on
dedicated c loc k pin VIN = 0 V ,
f = 1.0 MHz 12 pF
COUT Output capacit anc e VIN = 0 V,
f = 1.0 MHz (1) pF
I/O Bank 1 I/O Bank 2
I/O Bank 3
I/O Bank 4
I/O Bank 8
I/O Bank 7
I/O Bank 5I/O Bank 6
C
IN
= 15 pF
C
IN
= 12 pF C
IN
= 7 pF
C
IN
= 10 pF
Altera Corporation 79
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
T i mi ng Model The high-performance FastTrack and MegaLAB interconnect routing
structures ensure predictable performance, and accurate simulation and
timing analysis. In contrast, the unpredictable performance of FPGAs is
caused by their segmented connection scheme.
All specifications are always representative of worst-case supply volta ge
and junction temperature conditions. All output-pin-timing specifications
are reported for maxi mum dri ve strength.
Figure 41 shows the fMAX timing model for APEX II devices. These
parameters can be used to estimate fMAX for multiple levels of logic.
Howe ver, the Q uartus II softw are timing analysis pr ovides mor e accurate
timing information because the Quartus II software usually has more up-
to-date timing information than the data sheet until the timing model is
final. Also, the Quartus II software can model delays caused by loading
and dista nce effec ts more accurately th an by using the numb er s in t his
da ta she et .
80 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Fig ure 41. fMAX Timi ng M odel
SU
H
CO
LUT
t
t
t
t
F1—4
F5—20
F20+
LE
ESB
Routing Delay
t
t
t
t
ESBARC
t
ESBSRC
t
ESBAWC
t
ESBSWC
t
ESBWASU
t
ESBWDSU
t
ESBSRASU
t
ESBWESU
t
ESBDATASU
t
ESBWADDRSU
t
ESBRADDRSU
t
ESBDATACO1
t
ESBDATACO2
t
ESBDD
t
PD
t
PTERMSU
t
PTERMCO
Altera Corporation 81
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Figure 42 shows the timing model for bi-directional, input, and output
IOE timing.
Figure 42. Synchronous External TIming Mode l
Notes to Figure 42:
(1) The output e nable register is in the IOE and is controlled by the
“Fast Out put Enable Registe r = ON” option in the Qu ar t us II soft war e .
(2) The outpu t re gi s t er is in th e IOE and is c on t r o lled by the
“Fast Output R egister = ON” option in the Quartus II software.
(3) The input register is in the IOE and is controlled by the “Fast Input Register = ON”
option in the Quartus II software.
Tables 47 through 50 sho w AP E X II LE, ESB, an d r o u ti ng de l ays and
minimum pulse-width timing parameters for the fMAX timing model.
PRN
CLRN
DQ
PRN
CLRN
DQ
OE Register (1)
Bidirectional P
in
D
edicated
C
lock
PRN
CLRN
DQ
Input Register (3)
XZ
t
ZX
t
OUTCO
t
INSU
t
INH
t
Output IOE Register (2)
Table 47. APEX II fMAX LE Timing Parameters
Symbol Parameter
tSU LE register setup t ime befo re cl ock
tHLE register hold time before clo ck
tCO LE register clock -to -out put delay
tLUT LUT delay for data-in to data-out
82 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Figure shows t he dual-port R AM tim ing mic roparamete r wavef orm .
Table 48 . APE X I I fMAX ESB Timing Parameters
Symbol Parameter
tESBARC ESB asy nc hronous read c ycle t im e
tESBSRC ESB syn ch ronous read cyc le time
tESBAWC E SB asynchronous write cycle time
tESBSWC ESB syn ch ronous write cyc le time
tESBWASU ESB write addre ss se tu p tim e w ith resp ec t to WE
tESBWAH ESB writ e address hold tim e wi th respect to WE
tESBWDSU ESB data setup time with respect to WE
tESBWDH ESB d ata h ol d ti me with respect to WE
tESBRASU ESB read addre ss se tu p time w i th resp ec t to RE
tESBRAH ESB read address hold time wi th respect to RE
tESBWESU ESB WE setup tim e bef ore clock wh en us ing input register
tESBDATASU E SB data setup time before clock when using inp ut regis te r
tESBWADDRSU E SB w rit e address setup tim e bef ore clock whe n us ing input registers
tESBRADDRSU E SB read address se tu p time bef ore clock whe n us ing input registers
tESBDATACO1 E SB c loc k- to- out put delay w hen us ing output reg isters
tESBDATACO2 E SB c loc k- to- out put delay w itho ut outp ut regis ter s
tESBDD ESB data-in to data-out delay for RAM mode
tPD ESB m ac roc ell input to non-r egis t ered output
tPTERMSU ESB macrocell register set up time before clo ck
tPTERMCO E SB m ac roc ell register cloc k -to -out put delay
Altera Corporation 83
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Figur e 43. D ual-Port RAM Timing Mi croparameter Waveform
wrclock
wren
wraddress
data-in
reg_data-out
an-1 an a0 a1 a2 a3 a4 a5
din-1 din din4 din5
rdclock
a6
din6
unreg_data-out
rden
rdaddress bn b0 b1 b2 b3
doutn-2 doutn-1 doutn
doutn-1 doutn dout0
tESBRESU tESBREH
tESBDATACO1
tESBDATACO2
tESBDATASU
tESBDATAH
tESBWEH tESBWESU
tESBADDRSU tESBADDRH
dout0
tESBSRC
din0 din1 din2 din3
Table 49. APEX II fMAX Routing De lays
Symbol Parameter
tF1-4 Fan-out delay estimate using local interconnect; use to estimate routing delay for a signal
with fan-out of 1 to 4
tF5-20 Fan-out delay estimate using MegaLab interconnect; use to estimate routing delay for a
signal with fan -out of 5 to 20
tF20+ Fan-out delay estimate using FastTrack interconnect; use to estimate routing delay for a
signal with fan-out greater than 20
84 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Note to Table 51:
(1) External timing parameters are factory tested, worst-case values specified by Altera. These timing parameters are
sample-tested only.
Table 50. APEX II Minimum Pulse Width Timing Parameters
Symbol Parameter
tCH Minimum clock high time from clock pin
tCL Minimum cl o ck low ti me fr om clock p in
tCLRP LE clear pulse w idt h
tPREP LE preset puls e w idth
tESBCH C lock high time
tESBCL Clock low time
tESBWP W rite pulse width
tESBRP R ead pulse w idt h
Table 51 . APEX II Exte rnal Timing Parameters Note (1)
Symbol Parameter Conditions
tINSU Set up ti me with global clock at IOE input register
tINH Ho ld time w ith global clock at IOE input register
tOUTCO Clock-to-output delay with global clock at IOE output register C1 = 35 pF
tXZ Clo ck-t o-output bu ffer dis able delay
tZX Clo ck-t o-output bu ffer enable delay Slow sle w ra te = OFF
tINSUPLL Setup ti me with PLL c loc k at IOE input regis t er
tINHPLL H old time with PLL cl oc k at IOE input regis te r
tOUTCOPLL C lock-to-output de lay with PLL c loc k at IOE out put regis t er C1 = 35 pF
tXZPLL PLL clock-to-output buffer disable delay
tZXPLL PLL cloc k- to- out put buf fer enable delay Slow slew rate = OFF
Altera Corporation 85
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Tables 52 through 67 show the APEX II device fMAX and f unction al timin g
parameters.
Table 52. EP2A15 fMAX LE Timing Par ame t er s
Symbol -7 Speed Gra de -8 Speed Grade -9 Speed Gr ade Uni t
Min Max Min Max Min Max
tSU 0.25 0.29 0.33 ns
tH0.25 0.29 0.33 ns
tCO 0.18 0.20 0.23 ns
tLUT 0.53 0.61 0.70 ns
Table 53. EP2A15 fMAX ESB Timing Paramet ers
Symbol -7 Speed Gra de -8 Speed Grade -9 Speed Gr ade Uni t
Min Max Min Max Min Max
tESBARC 1.28 1.47 1.69 ns
tESBSRC 2.49 2.86 3.29 ns
tESBAWC 2.20 2.53 2.91 ns
tESBSWC 3.02 3.47 3.99 ns
tESBWASU −0.55 −0.64 −0.73 ns
tESBWAH 0.15 0.18 0.20 ns
tESBWDSU 0.37 0.43 0.49 ns
tESBWDH 0.16 0.18 0.21 ns
tESBRASU 0.84 0.96 1.11 ns
tESBRAH 0.00 0.00 0.00 ns
tESBWESU 0.14 0.16 0.19 ns
tESBDATASU −0.02 −0.03 −0.03 ns
tESBWADDRSU −0.40 −0.46 −0.53 ns
tESBRADDRSU −0.38 −0.44 −0.51 ns
tESBDATACO1 1.30 1.50 1.72 ns
tESBDATACO2 1.84 2.12 2.44 ns
tESBDD 2.42 2.78 3.19 ns
tPD 1.69 1.94 2.23 ns
tPTERMSU 1.10 1.26 1.45 ns
tPTERMCO 0.82 0.94 1.08 ns
86 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Table 54 . EP2 A15 fMAX Rout i n g De la ys
Symbol -7 Speed Grade -8 Speed Grade -9 Speed Grade Unit
Min Max Min Max Min Max
tF1-4 0.19 0.21 0.25 ns
tF5-20 0.64 0.73 0.84 ns
tF20+ 1.18 1.35 1.56 ns
Table 55. EP2A15 Minimum Pulse Width Timing Parameters
Symbol -7 Speed Grade -8 Speed Grade -9 Speed Grade Unit
Min Max Min Max Min Max
tCH 1.00 1.15 1.32 ns
tCL 1.00 1.15 1.32 ns
tCLRP 0.13 0.15 0.17 ns
tPREP 0.13 0.15 0.17 ns
tESBCH 1.00 1.15 1.32 ns
tESBCL 1.00 1.15 1.32 ns
tESBWP 1.12 1.28 1.48 ns
tESBRP 0.88 1.02 1.17 ns
Table 56 . EP2 A25 fMAX LE Timing Parameters
Symbol -7 Speed Grade -8 Speed Grade -9 Speed Grade Unit
Min Max Min Max Min Max
tSU 0.25 0.29 0.33 ns
tH0.25 0.29 0.33 ns
tCO 0.18 0.20 0.23 ns
tLUT 0.53 0.61 0.70 ns
Altera Corporation 87
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Table 57. EP2A25 fMAX ESB Timing Paramet ers
Symbol -7 Speed Gra de -8 Speed Grade -9 Speed Gr ade Uni t
Min Max Min Max Min Max
tESBARC 1.28 1.47 1.69 ns
tESBSRC 2.49 2.86 3.29 ns
tESBAWC 2.20 2.53 2.91 ns
tESBSWC 3.02 3.47 3.99 ns
tESBWASU 0.07 0.07 0.09 ns
tESBWAH 0.15 0.18 0.20 ns
tESBWDSU 0.37 0.43 0.49 ns
tESBWDH 0.16 0.18 0.21 ns
tESBRASU 0.84 0.96 1.11 ns
tESBRAH 0.00 0.00 0.00 ns
tESBWESU 0.14 0.16 0.19 ns
tESBDATASU −0.02 −0.03 −0.03 ns
tESBWADDRSU −0.40 −0.46 −0.53 ns
tESBRADDRSU −0.38 −0.44 −0.51 ns
tESBDATACO1 1.30 1.50 1.72 ns
tESBDATACO2 1.84 2.12 2.44 ns
tESBDD 2.42 2.78 3.19 ns
tPD 1.69 1.94 2.23 ns
tPTERMSU 1.10 1.26 1.45 ns
tPTERMCO 0.82 0.94 1.08 ns
Table 58. EP2A25 fMAX Routing De lays
Symbol -7 Speed Gra de -8 Speed Grade -9 Speed Gr ade Uni t
Min Max Min Max Min Max
tF1-4 0.19 0.21 0.25 ns
tF5-20 0.65 0.75 0.86 ns
tF20+ 1.11 1.27 1.46 ns
88 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Table 59. EP2A25 Minimum Pulse Width Timing Parameters
Symbol -7 Speed Grade -8 Speed Grade -9 Speed Grade Unit
Min Max Min Max Min Max
tCH 1.00 1.50 2.12 ns
tCL 1.00 1.50 2.12 ns
tCLRP 0.13 0.15 0.17 ns
tPREP 0.13 0.15 0.17 ns
tESBCH 1.00 1.50 2.12 ns
tESBCL 1.00 1.50 2.12 ns
tESBWP 1.12 1.28 1.48 ns
tESBRP 0.88 1.02 1.17 ns
Table 60 . EP2 A40 fMAX LE Timing Parameters
Symbol -7 Speed Grade -8 Speed Grade -9 Speed Grade Unit
Min Max Min Max Min Max
tSU 0.22 0.26 0.29 ns
tH0.22 0.26 0.29 ns
tCO 0.16 0.18 0.21 ns
tLUT 0.48 0.55 0.63 ns
Altera Corporation 89
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Table 61. EP2A40 fMAX ESB Timing Paramet ers
Symbol -7 Speed Gra de -8 Speed Grade -9 Speed Gr ade Uni t
Min Max Min Max Min Max
tESBARC 2.28 2.62 3.01 ns
tESBSRC 2.23 2.56 2.95 ns
tESBAWC 3.13 3.60 4.13 ns
tESBSWC 2.76 3.18 3.65 ns
tESBWASU 1.19 1.37 1.57 ns
tESBWAH 0.00 0.00 0.00 ns
tESBWDSU 1.44 1.66 1.91 ns
tESBWDH 0.00 0.00 0.00 ns
tESBRASU 1.88 2.17 2.49 ns
tESBRAH 0.00 0.00 0.00 ns
tESBWESU 1.60 1.85 2.12 ns
tESBDATASU 0.74 0.85 0.98 ns
tESBWADDRSU 0.82 0.94 1.08 ns
tESBRADDRSU 0.73 0.84 .97 ns
tESBDATACO1 1.09 1.25 1.44 ns
tESBDATACO2 1.73 1.99 2.29 ns
tESBDD 3.26 3.75 4.32 ns
tPD 1.55 1.78 2.05 ns
tPTERMSU 0.99 1.13 1.30 ns
tPTERMCO 0.79 0.90 1.04 ns
Table 62. EP2A40 fMAX Routing De lays
Symbol -7 Speed Gra de -8 Speed Grade -9 Speed Gr ade Uni t
Min Max Min Max Min Max
tF1-4 0.17 0.19 0.22 ns
tF5-20 1.12 1.28 1.48 ns
tF20+ 1.49 1.72 1.98 ns
90 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Table 63. EP2A40 Minimum Pulse Width Timing Parameters
Symbol -7 Speed Grade -8 Speed Grade -9 Speed Grade Unit
Min Max Min Max Min Max
tCH 0.89 1.33 1.88 ns
tCL 0.89 1.33 1.88 ns
tCLRP 0.12 0.14 0.16 ns
tPREP 0.12 0.14 0.16 ns
tESBCH 0.89 1.33 1.88 ns
tESBCL 0.89 1.33 1.88 ns
tESBWP 1.05 1.20 1.38 ns
tESBRP 0.78 0.90 1.03 ns
Table 64 . EP2 A70 fMAX LE Timing Parameters
Symbol -7 Speed Grade -8 Speed Grade -9 Speed Grade Unit
Min Max Min Max Min Max
tSU 0.30 0.34 0.39 ns
tH0.30 0.34 0.39 ns
tCO 0.22 0.25 0.29 ns
tLUT 0.66 0.76 0.87 ns
Altera Corporation 91
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Table 65. EP2A70 fMAX ES B Ti ming Parameters
Symbol -7 Spee d G rade -8 Spee d G rade -9 Spee d G rade Unit
Min Max Min Max Min Max
tESBARC 3.12 3.58 4.12 ns
tESBSRC 3.11 3.58 4.11 ns
tESBAWC 4.41 5.07 5.83 ns
tESBSWC 3.82 4.39 5.05 ns
tESBWASU 1.73 1.99 2.28 ns
tESBWAH 0.00 0.00 0.00 ns
tESBWDSU 1.87 2.15 2.47 ns
tESBWDH 0.00 0.00 0.00 ns
tESBRASU 2.76 3.17 3.65 ns
tESBRAH 0.00 0.00 0.00 ns
tESBWESU 1.98 2.27 2.61 ns
tESBDATASU 1.06 1.22 1.40 ns
tESBWADDRSU 1.17 1.34 1.54 ns
tESBRADDRSU 1.02 1.17 1.35 ns
tESBDATACO1 1.52 1.75 2.01 ns
tESBDATACO2 2.35 2.71 3.11 ns
tESBDD 4.43 5.10 5.87 ns
tPD 2.17 2.49 2.87 ns
tPTERMSU 1.40 1.62 1.86 ns
tPTERMCO 1.08 1.24 1.42 ns
Table 66. EP2A70 fMAX Routing De lays
Symbol -7 Spee d G rade -8 Spee d G rade -9 Spee d G rade Unit
Min Max Min Max Min Max
tF1-4 0.15 0.18 0.20 ns
tF5-20 1.21 1.39 1.60 ns
tF20+ 1.87 2.15 2.55 ns
92 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Tables 68 through 77 show the IOE external timing parameter values for
APEX II de vic es.
Table 67. EP2A70 Minimum Pulse Width Timing Parameters
Symbol -7 Speed Grade -8 Speed Grade -9 Speed Grade Unit
Min Max Min Max Min Max
tCH 1.19 1.78 2.53 ns
tCL 1.19 1.78 2.53 ns
tCLRP 0.16 0.19 0.21 ns
tPREP 0.16 0.19 0.21 ns
tESBCH 1.19 1.78 2.53 ns
tESBCL 1.19 1.78 2.53 ns
tESBWP 1.35 1.56 1.79 ns
tESBRP 1.13 1.30 1.50 ns
Table 68 . EP2A15 Ext ernal Timing Paramete rs for Row I/O Pi ns
Symbol -7 Speed Grade -8 Speed Grade -9 Speed Grade Unit
Min Max Min Max Min Max
tINSU 2.06 2.25 2.46 ns
tINH 0.00 0.00 0.00 ns
tOUTCO 2.00 4.05 2.00 4.45 2.00 4.90 ns
tXZ 4.98 5.59 6.26 ns
tZX 4.98 5.59 6.26 ns
tINSUPLL 1.15 1.28 1.42 ns
tINHPLL 0.00 0.00 0.00 ns
tOUTCOPLL 0.50 2.60 0.50 2.87 0.50 3.16 ns
tXZPLL 3.53 4.00 4.52 ns
tZXPLL 3.53 4.00 4.52 ns
Altera Corporation 93
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Table 69. EP2A15 External Timing Parameters for Column I/O Pins
Sym bol -7 Speed G rade -8 Sp eed Grade -9 Sp eed Grad e Unit
Min Max Min Max Min Max
tINSU 2.16 2.34 2.53 ns
tINH 0.00 0.00 0.00 ns
tOUTCO 2.00 4.36 2.00 4.75 2.00 5.18 ns
tXZ 5.57 6.24 6.97 ns
tZX 5.57 6.24 6.97 ns
tINSUPLL 1.24 1.37 1.52 ns
tINHPLL 0.00 0.00 0.00 ns
tOUTCOPLL 0.50 2.90 0.50 3.16 0.50 3.45 ns
tXZPLL 4.12 4.65 5.23 ns
tZXPLL 4.12 4.65 5.23 ns
Table 70. EP2A25 External Timing Parameters for Row I/O Pins
Sym bol -7 Speed G rade -8 Sp eed Grade -9 Sp eed Grad e Unit
Min Max Min Max Min Max
tINSU 1.92 2.08 2.26 ns
tINH 0.00 0.00 0.00 ns
tOUTCO 2.00 4.29 2.00 4.62 2.00 4.98 ns
tXZ 5.24 5.73 6.26 ns
tZX 5.24 5.73 6.26 ns
tINSUPLL 1.17 1.27 1.40 ns
tINHPLL 0.00 0.00 0.00 ns
tOUTCOPLL 0.50 2.61 0.50 2.83 0.50 3.07 ns
tXZPLL 3.55 3.93 4.35 ns
tZXPLL 3.55 3.93 4.35 ns
94 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Table 71 . EP2A25 Ext ernal Timing Paramete rs for Col umn I /O Pins
Symbol -7 Speed Grade -8 Speed Grade -9 Speed Grade Unit
Min Max Min Max Min Max
tINSU 2.27 2.45 2.64 ns
tINH 0.00 0.00 0.00 ns
tOUTCO 2.00 4.57 2.00 4.89 2.00 5.24 ns
tXZ 5.87 6.42 7.01 ns
tZX 5.87 6.42 7.01 ns
tINSUPLL 1.23 1.35 1.47 ns
tINHPLL 0.00 0.00 0.00 ns
tOUTCOPLL 0.50 2.89 0.50 3.10 0.50 3.33 ns
tXZPLL 4.18 4.62 5.09 ns
tZXPLL 4.18 4.62 5.09 ns
Table 72 . EP2A40 Ext ernal Timing Paramete rs for Row I/O Pi ns
Symbol -7 Speed Grade -8 Speed Grade -9 Speed Grade Unit
Min Max Min Max Min Max
tINSU 1.57 1.72 1.88 ns
tINH 0.00 0.00 0.00 ns
tOUTCO 2.00 4.90 2.00 5.24 2.00 5.61 ns
tXZ 6.47 6.98 7.53 ns
tZX 6.47 6.98 7.53 ns
tINSUPLL 1.15 1.26 1.38 ns
tINHPLL 0.00 0.00 0.00 ns
tOUTCOPLL 0.50 2.60 0.50 2.82 0.50 3.06 ns
tXZPLL 4.17 4.56 4.97 ns
tZXPLL 4.17 4.56 4.97 ns
Altera Corporation 95
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Table 73. EP2A40 External Timing Parameters for Column I/O Pins
Sym bol -7 Speed G rade -8 Sp eed Grade -9 Sp eed Grad e Unit
Min Max Min Max Min Max
tINSU 2.00 2.16 2.33 ns
tINH 0.00 0.00 0.00 ns
tOUTCO 2.00 4.96 2.00 5.29 2.00 5.64 ns
tXZ 7.04 7.59 8.19 ns
tZX 7.04 7.59 8.19 ns
tINSUPLL 1.20 1.31 1.43 ns
tINHPLL 0.00 0.00 0.00 ns
tOUTCOPLL 0.50 2.66 0.50 2.87 0.50 3.09 ns
tXZPLL 4.74 5.17 5.64 ns
tZXPLL 4.74 5.17 5.64 ns
Table 74. EP2A70 External Timing Parameters for Row I/O Pins
Sym bol -7 Speed G rade -8 Sp eed Grade -9 Sp eed Grad e Unit
Min Max Min Max Min Max
tINSU 2.48 2.68 2.90 ns
tINH 0.00 0.00 0.00 ns
tOUTCO 2.00 4.76 2.00 5.12 2.00 5.51 ns
tXZ 5.68 6.19 6.76 ns
tZX 5.68 6.19 6.76 ns
tINSUPLL 1.19 1.30 1.43 ns
tINHPLL 0.00 0.00 0.00 ns
tOUTCOPLL 0.50 2.52 0.50 2.74 0.50 2.98 ns
tXZPLL 3.44 3.82 4.23 ns
tZXPLL 3.44 3.82 4.23 ns
96 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Table 75 . EP2A70 Ext ernal Timing Paramete rs for Col umn I /O Pins
Symbol -7 Speed Grade -8 Speed Grade -9 Speed Grade Unit
Min Max Min Max Min Max
tINSU 2.79 2.99 3.22 ns
tINH 0.00 0.00 0.00 ns
tOUTCO 2.00 4.91 2.00 5.24 2.00 5.60 ns
tXZ 6.16 6.71 7.32 ns
tZX 6.16 6.71 7.32 ns
tINSUPLL 1.19 1.30 1.43 ns
tINHPLL 0.00 0.00 0.00 ns
tOUTCOPLL 0.50 2.67 0.50 2.86 0.50 3.08 ns
tXZPLL 3.92 4.34 4.79 ns
tZXPLL 3.92 4.34 4.79 ns
Altera Corporation 97
APEX II Pro grammabl e Log i c Dev ic e Fa mi ly Data Sh eet
Table 76. APEX II Selectable I/O Standards Input Adder Delays
Sym bol -7 Speed G rade -8 Sp eed Grade -9 Sp eed Grad e Unit
Min Max Min Max Min Max
LVCMOS 0.00 0.00 0.00 ns
LVTTL 0.00 0.00 0.00 ns
1.5 V 0.10 0.11 0.12 ns
1.8 V 0.00 0.00 0.00 ns
2.5 V 0.00 0.00 0.00 ns
3.3- V PCI 0 .0 0 0.00 0.00 ns
3.3- V PCI- X 0.00 0.00 0.00 ns
GTL+ −0.20 −0.22 −0.24 ns
SSTL -3 Cla ss I −0.17 −0.19 −0.20 ns
SSTL -3 Cla ss II −0.17 −0.19 −0.20 ns
SSTL -2 Cla ss I −0.24 −0.26 −0.29 ns
SSTL -2 Cla ss II −0.24 −0.26 −0.29 ns
HSTL Cl ass I −0.03 −0.03 −0.03 ns
HSTL Cl ass II −0.03 −0.03 −0.03 ns
LVDS −0.23 −0.26 −0.28 ns
LVPECL −0.23 −0.26 −0.28 ns
PCML −0.23 −0.26 −0.28 ns
CTT 0.00 0.00 0.00 ns
3.3-V AGP 1×0.00 0.00 0.00 ns
3.3-V AGP 2×0.00 0.00 0.00 ns
HyperTransport −0.23 −0.26 −0.28 ns
Differential
HSTL −0.23 −0.26 −0.28 ns
98 Altera Corporation
APE X II Pr ogr ammable Logic D evi ce F ami l y Da ta Sh eet
Power
Consumption
Detailed power consumption information for APEX II devices will be
released v ia a future interactive power estimato r on the Alt era we b site.
Device Pin-
Outs
See the Alte r a web site (http://www.altera.com) or the Altera Digital
Library for pin-out information.
Table 77. A PEX II Selectable I/O Stand ards Output Ad der Delays
Symbol -7 Speed Grade -8 Speed Grade -9 Speed Grade Unit
Min Max Min Max Min Max
LVCMOS 0.00 0.00 0.00 ns
LVTTL 0.00 0.00 0.00 ns
1.5 V 3.32 3.82 4.20 ns
1.8 V 2.65 3.05 3.36 ns
2.5 V 1.20 1.38 1.52 ns
3.3-V PCI −0.68 −0.78 −0.85 ns
3.3-V PCI- X −0.68 −0.78 −0.85 ns
GTL+ −0.45 −0.52 −0.57 ns
SSTL-3 Class I −0.52 −0.60 −0.66 ns
SSTL-3 Class II −0.52 −0.60 −0.66 ns
SSTL-2 Class I −0.68 −0.78 −0.86 ns
SSTL-2 Class II −0.81 −0.93 −1.02 ns
HST L Cla ss I −0.08 −0.09 −0.10 ns
HST L Cla ss II −0.23 −0.27 −0.30 ns
LVDS −1.41 −1.62 −1.79 ns
LVPECL −1.38 −1.58 −1.74 ns
PCML −1.30 −1.50 −1.65 ns
CTT 0.00 0.00 0.00 ns
3.3-V AGP 1×0.00 0.00 0.00 ns
3.3-V AGP 2×0.00 0.00 0.00 ns
HyperTransport −1.22 −1.41 −1.55 ns
Differential
HSTL −1.41 −1.62 −1.79 ns
®
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APEX II Programmable Logic Device Family Data Sheet
99 Altera Corporation
Revision
History
The information cont ained in the APEX II Programmable Logic Device
Fami ly Data Shee t version 3. 0 supersedes information published in
previous versions. The following changes were made to the APEX II
Programmable Logic Device Family Data Sheet version 3.0:
■Change d the value f rom 624 t o 400 M b ps t hro ughout the do cument.
■Deleted the pin count (612) for the EP2A25 device in the 1,020-pin
Fine Li ne BG A pack ag e ( se e Table 3).
■Added Table 13.
■Changed the m aximu m valu e of 3. 6 to 2.4 in Table 20.
■Updated Tables 60 through 67 and Tables 72 through 75.
■Updated Figures 25, 28, and 30.
■Added Note (1) to Figure 13.
■Added Figure 43.