Revised March 2002 CD4010C Hex Buffers (Non-Inverting) General Description Features The CD4010C hex buffers are monolithic complementary MOS (CMOS) integrated circuits. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage. This results in high noise immunity over a wide supply voltage range. No DC power other than that caused by leakage current is consumed during static conditions. All inputs are protected against static discharge. These gates may be used as hex buffers, CMOS to DTL or TTL interface or as CMOS current drivers. Conversion ranges are from 3V to 15V providing VCC VDD. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. Wide supply voltage range: Low power: 3.0V to 15V 100 nW (typ.) High noise immunity: 0.45 VDD (typ.) High current sinking: 8 mA (min.) at VO = 0.5V capability: and VDD = 10V Applications * Automotive * Data terminals * Instrumentation * Medical electronics * Alarm system * Industrial controls * Remote metering * Computers Ordering Code: Order Number Package Number Package Description CD4010CM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4010CN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram Schematic Diagram Hex COS/MOS to DTL or TTL converter (inverting). Connect VCC to DTL or TTL supply. Connect VDD to COS/MOS supply. Top View (c) 2002 Fairchild Semiconductor Corporation DS005945 www.fairchildsemi.com CD4010C Hex Buffers (Non-Inverting) October 1987 CD4010C Absolute Maximum Ratings(Note 1) Voltage at Any Pin (Note 2) VSS - 0.3V to VSS +15.5V Operating Temperature Range -55C to +125C Storage Temperature Range (TS) -65C to +150C Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW Note 1: "Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits." 260C Note 2: This device should not be connected to circuits with the power on because high transient voltage may cause permanent damage. Lead Temperature (TL) (Soldering, 10 seconds) Operating Range (VDD) VSS + 3V to VSS + 15V DC Electrical Characteristics Limits Symbol Characteristics -55C Conditions Min ICC PD VOL VOH VNL VNH IDN IDP II +25C Max Min Typ +125C Max Min Units Max Quiescent Device VDD = 5.0V 0.3 0.01 0.3 20 Current VDD = 10V 0.5 0.01 0.5 30 Quiescent Device VDD = 5.0V 1.5 0.05 1.5 100 Dissipation/Package VDD = 10V 5.0 0.1 5.0 300 Output Voltage VDD = 5.0V 0.01 0 0.01 0.05 LOW Level VDD = 10V 0.01 0 0.01 0.05 Output Voltage VDD = 5.0V 4.99 4.99 5 4.95 HIGH Level VDD = 10V 9.99 9.99 10 9.95 Noise Immunity VDD = 5.0V, VO 1.5 1.6 1.5 2.25 1.4 (All Inputs) VDD = 10V, VO 3.0 3.2 3 4.5 2.9 Noise Immunity VDD = 5.0V, VO 3.5 1.4 1.5 2.25 1.5 (All Inputs) VDD = 10V, VO 7.0 2.9 3 4.5 3 Output Drive Current VDD = 5.0V, 0.4 = V0 3.75 3 4 2.1 N-Channel (Note 3) VDD = 10V, 0.5 = V0 10 8 10 5.6 Output Drive Current VDD = 5.0V, 2.5 = V0 -1.85 -1.25 -1.75 -0.9 P-Channel (Note 3) VDD = 10V, 9.5 = V0 -0.9 -0.6 -0.8 -0.4 Input Current 10 Note 3: IDN and IDP are tested one output at a time. www.fairchildsemi.com 2 A W V V V V mA mA pA (Note 4) TA= 25c, CL= 15 pF, unless otherwise noted. Typical Temperature coefficient for all values of VDD= 0.3%/C Test Conditions Symbol Limits VDD Characteristics Min Typ Max Units 5 -- 15 70 10 -- 10 40 -- 10 35 5 -- 50 100 10 -- 25 70 -- 15 40 ns ns (Volts) tPHL Propagation Delay Time: tPLH HIGH-to-LOW Level (tPHL) VCC = VDD VDD = 10V ns VCC = 5V LOW-to-HIGH Level (tPLH) VCC = VDD VDD = 10V VCC = 5V tTHL Transition Time: tTLH HIGH-to-LOW Level (tTHL) LOW-to-HIGH Level (tTLH) Input Capacitance (CI) VCC = VDD VCC = VDD Any Input 5 -- 20 60 10 -- 16 50 5 -- 80 160 10 -- 50 120 -- 5 -- ns pF Note 4: AC Parameters are guaranteed by DC correlated testing. Typical Application 3 www.fairchildsemi.com CD4010C AC Electrical Characteristics CD4010C Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A www.fairchildsemi.com 4 CD4010C Hex Buffers (Non-Inverting) Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 5 www.fairchildsemi.com