Data Sheet, Rev. 1.2, Feb. 2004 HYB25D256400B[T/C](L) HYB25D256800B[T/C](L) HYB25D256160B[T/C](L) 256 Mbit Double Data Rate SDRAM DDR SDRAM Memory Products N e v e r s t o p t h i n k i n g . Edition 2004-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Data Sheet, Rev. 1.2, Feb. 2004 HYB25D256400B[T/C](L) HYB25D256800B[T/C](L) HYB25D256160B[T/C](L) 256 Mbit Double Data Rate SDRAM DDR SDRAM Memory Products N e v e r s t o p t h i n k i n g . HYB25D256400B[T/C](L), HYB25D256800B[T/C](L), HYB25D256160B[T/C](L) Revision History: Rev. 1.2 2004-02 Previous Version: V1.1 2003-01 Page Subjects (major changes since last revision) Rev 1.2 All Added Products HYB25D256800BT-5, HYB25D256160BT-5, HYB25D256400BC-5 62-66 Corrected AC Timing values in table 19 and 20 to be conform with Jedec All Editorial changes We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com Template: mp_a4_v2.2_2003-10-07.fm HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM 1 1.1 1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.3 3.3.1 3.3.2 3.4 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bank/Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 16 17 17 18 19 20 20 20 21 24 24 25 33 47 48 53 4 4.1 4.2 4.3 4.4 4.4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Strength Pull-down and Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Weak Strength Pull-down and Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDD Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 54 56 58 60 68 5 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Data Sheet 5 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW 256 Mbit Double Data Rate SDRAM DDR SDRAM 1 Overview 1.1 Features * * * * * * * * * * * * * * * * * * HYB25D256400B[T/C](L) HYB25D256800B[T/C](L) HYB25D256160B[T/C](L) Double data rate architecture: two data transfers per clock cycle. Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver. DQS is edge-aligned with data for reads and is center-aligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst Lengths: 2, 4, or 8 CAS Latency: 2, 2.5, 3 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 7.8 s Maximum Average Periodic Refresh Interval (8K refresh) 2.5V (SSTL_2 compatible) I/O VDDQ = 2.5 V 0.2 V (DDR200, DDR266, DDR333); VDDQ = 2.6 V 0.1 V (DDR400) VDD = 2.5 V 0.2 V (DDR200, DDR266, DDR333); VDD = 2.6 V 0.1 V (DDR400) P-TSOPII-66-1 package P-TFBGA-60-2 package with 3 depopulated rows (12 mm x 8 mm2). Table 1 Performance Part Number Speed Code -5 -6 -7F -7 -8 Unit Speed Grade Component DDR400B DDR333B DDR266 DDR266A DDR200 -- Module PC32003033 PC2700- 2533 PC21002022 PC21002033 PC16002022 -- 166 - - - MHz 166 143 143 125 MHz 133 133 133 100 MHz max. Clock Frequency 1.2 fCK3 200 @CL2.5 fCK2.5 166 @CL2 fCK2 133 @CL3 Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-halfclock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with data for Reads and center-aligned with data for Writes. Data Sheet 6 Rev. 1.2, 2004-02 HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Overview The 256Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. Data Sheet 7 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Overview Table 2 Ordering Information Part Number 1) Org. CAS-RCD-RP Clock CAS-RCD-RP Clock Speed Latencies (MHz) Latencies (MHz) HYB25D256800BT(L)-5 x8 3-3-3 200 2.5 - 3 - 3 166 DDR400B P-TSOPII-66-1 HYB25D256160BT(L)-5 x16 2.5 - 3 - 3 166 2-3-3 133 DDR333 HYB25D256400BT(L)-6 x4 HYB25D256800BT(L)-6 x8 HYB25D256160BT(L)-6 x16 HYB25D256400BT(L)-7 x4 133 DDR266A HYB25D256800BT(L)-7 x8 HYB25D256160BT(L)-7 x16 HYB25D256400BT(L)-7F x4 133 DDR266 HYB25D256800BT(L)-7F x8 HYB25D256160BT(L)-7F x16 HYB25D256400BT(L)-8 x4 100 DDR200 HYB25D256800BT(L)-8 x8 HYB25D256160BT(L)-8 x16 HYB25D256400BC(L)-5 x4 3-3-3 200 2.5 - 3 - 3 166 DDR400B P-TFBGA-60-2 HYB25D256400BC(L)-6 x4 2.5 - 3 - 3 166 2-3-3 133 DDR333 HYB25D256800BC(L)-6 x8 HYB25D256160BC(L)-6 x16 HYB25D256400BC(L)-7 x4 133 DDR266A HYB25D256800BC(L)-7 x8 HYB25D256160BC(L)-7 x16 HYB25D256400BC(L)-7F x4 HYB25D256800BC(L)-7F x8 HYB25D256160BC(L)-7F x16 HYB25D256400BC(L)-8 x4 HYB25D256800BC(L)-8 x8 HYB25D256160BC(L)-8 x16 143 143 2-2-2 125 143 143 2-2-2 125 Package DDR266 100 DDR200 1) HYB: designator for memory components, 25D: DDR-I SDRAMs at Vddq=2.5V, 256: 256Mb density, 400/800/160: Product variations x4, x8 and x16, B: Die revision B, C/T: Package type FBGA and TSOP, L: Low power version (optional) - these components are specifically selected for low IDD6 Self Refresh currents. Data Sheet 8 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Pin Configuration 2 Pin Configuration 1 2 3 7 8 9 1 2 3 7 8 9 VSSQ NC VSS A VDD NC VDDQ VSSQ DQ7 VSS A VDD DQ0 VDDQ NC VDDQ DQ3 B DQ0 VSSQ NC NC VDDQ DQ6 B DQ1 VSSQ NC NC VSSQ NC C NC VDDQ NC NC VSSQ DQ5 C DQ2 VDDQ NC NC VDDQ DQ2 D DQ1 VSSQ NC NC VDDQ DQ4 D DQ3 VSSQ NC NC VSSQ DQS E NC VDDQ NC NC VSSQ DQS E NC VDDQ NC VREF VSS DM F NC VDD NC VREF VSS DM F NC VDD NC CLK CLK G WE CAS CLK CLK G WE CAS A12 CKE H RAS CS A12 CKE H RAS CS A11 A9 J BA1 BA0 A11 A9 J BA1 BA0 A8 A7 K A0 A10/AP A8 A7 K A0 A10/AP A6 A5 L A2 A1 A6 A5 L A2 A1 A4 VSS M VDD A3 A4 VSS M VDD A3 (x4) ( x8 ) 1 2 7 8 9 A VDD DQ0 VDDQ DQ14 VDDQ DQ13 B DQ2 VSSQ DQ1 DQ12 VSSQ DQ11 C DQ4 VDDQ DQ3 DQ10 VDDQ D DQ6 VSSQ DQ5 LDQS VDDQ DQ7 VSSQ DQ15 DQ8 VREF 3 VSS DQ9 VSSQ UDQS E VSS UDM F LDM VDD CLK CLK G WE CAS A12 CKE H RAS CS A11 A9 J BA1 BA0 A8 A7 K A0 A10/AP A6 A5 L A2 A1 A4 VSS M VDD A3 NC ( x 16 ) Figure 1 Data Sheet Pin Configuration P-TFBGA-60-2 (Top View - see the balls through the package) 9 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Pin Configuration VDD VDD VDD 1 66 VSS VSS VSS NC VDDQ NC DQ0 DQ0 VDDQ NC DQ1 DQ0 VDDQ DQ1 DQ2 2 3 4 65 64 63 DQ15 VSSQ DQ14 DQ7 VSSQ NC NC VSSQ NC 5 62 DQ13 DQ6 DQ3 6 7 8 9 10 61 60 59 58 57 VDDQ DQ12 DQ11 VSSQ DQ10 VDDQ NC DQ5 VSSQ NC VDDQ NC NC VSSQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 11 56 DQ9 DQ4 DQ2 VSSQ VSSQ VSSQ 12 55 VDDQ VDDQ VDDQ NC NC NC NC DQ7 NC VDDQ NC NC VDD NC NC VDDQ NC NC VDD NC NC VDDQ LDQS NC VDD NC LDM 13 14 15 16 17 18 19 20 54 53 52 51 50 49 48 47 DQ8 NC VSSQ UDQS NC VREF VSS UDM NC NC VSSQ DQS NC VREF VSS DM NC NC VSSQ DQS NC VREF VSS DM WE CAS RAS WE CAS RAS WE CAS RAS 21 22 23 46 45 44 CK CK CKE CK CK CKE CK CK CKE CS NC CS NC CS NC 24 25 43 42 NC A12 NC A12 NC A12 BA0 BA1 A10/AP BA0 BA1 A10/AP BA0 BA1 A10/AP A0 A1 A2 A0 A1 A2 A0 A1 A2 26 27 28 29 41 40 39 38 A11 A9 A8 A7 A11 A9 A8 A7 A11 A9 A8 A7 30 31 37 36 A6 A5 A6 A5 A6 A5 A3 VDD A3 VDD A3 VDD 32 33 35 34 A4 VSS A4 VSS A4 VSS VSSQ NC NC VDDQ NC 16Mb x 16 32Mb x 8 64Mb x 4 Figure 2 Data Sheet Pin Configuration P-TSOPII-66-1 10 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Pin Configuration Table 3 Input/Output Functional Description Symbol Type Function CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). CKE Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. The standard pinout includes one CS pin. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 and BA1 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. A0 - A12 Input Address Inputs: Provide the row address for Active commands, and the column address and Auto Precharge bit for Read/Write commands, to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode Register Set command. DQ Input/Output Data Input/Output: Data bus. DQS Input/Output Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. NC - No Connect: No internal electrical connection is present. VDDQ VSSQ VDD VSS VREF Supply DQ Power Supply: 2.5 V 0.2 V/ 2.6V 0.1V. Supply DQ Ground Supply Power Supply: 2.5 V 0.2 V / 2.6V 0.1V Supply Ground Supply SSTL_2 reference voltage: (VDDQ / 2) Data Sheet 11 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Control Logic 2 Bank2 Bank3 CK, CK DLL 2 8192 4 8 8 1024 (x8) Write FIFO & Drivers 1 DQS Generator Column-Address Counter/Latch CK, CK COL0 DQS Input Register 1 Mask 1 2 1 1 4 4 8 4 clk clk out in Data 10 4 DQ0-DQ3, DM DQS 1 4 COL0 1 1 Figure 3 4 COL0 I/O Gating DM Mask Logic Column Decoder 11 Drivers 8 Sense Amplifiers Data 4 MUX Bank0 Memory Array (8192 x 1024 x 8) Read Latch 8192 Receivers 15 Address Register A0-A12, BA0, BA1 Refresh Counter 13 13 13 Bank Control Logic Mode Registers Bank0 Row-Address Latch & Decoder Bank1 Row-Address MUX CKE CK CK CS WE CAS RAS Command Decode Pin Configuration Block Diagram (64Mb x 4) Notes: 1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 2. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals. Data Sheet 12 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Control Logic 2 Bank2 Bank3 CK, CK DLL 2 8192 8 16 16 512 (x16) Write FIFO & Drivers 9 Column-Address Counter/Latch CK, CK COL0 DQS Input Register 1 Mask 1 2 1 1 8 8 8 DQ0-DQ7, DM DQS 1 8 COL0 1 1 Figure 4 1 DQS Generator 16 8 clk clk out in Data Column Decoder 10 8 COL0 I/O Gating DM Mask Logic Drivers 16 Sense Amplifiers Data 8 MUX Bank0 Memory Array (8192 x 512x 16) Read Latch 8192 Receivers 15 Address Register A0-A12, BA0, BA1 Refresh Counter 13 13 13 Bank Control Logic Mode Registers Bank0 Row-Address Latch & Decoder Bank1 Row-Address MUX CKE CK CK CS WE CAS RAS Command Decode Pin Configuration Block Diagram (32Mb x 8) Notes: 1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 2. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals. Data Sheet 13 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Control Logic Bank2 Bank3 CK, CK DLL 2 2 8192 16 16 32 32 256 (x32) Write FIFO & Drivers 1 1 16 16 16 clk clk out in Data 16 2 8 Column-Address Counter/Latch LDQS, UDQS 1 16 COL0 CK, CK COL0 2 1 Figure 5 N Thi F i l Bl k Di Block Diagram (16Mb x 16) i i DQ0-DQ15, DM DQS Input Register 1 Mask 1 32 Column Decoder 9 1 DQS Generator COL0 I/O Gating DM Mask Logic Drivers 32 Sense Amplifiers Data 16 MUX Bank0 Memory Array (8192 x 256x 32) Read Latch 8192 Receivers 15 Address Register A0-A11, BA0, BA1 Refresh Counter 13 13 13 Bank Control Logic Mode Registers Bank0 Row-Address Latch & Decoder Bank1 Row-Address MUX CKE CK CK CS WE CAS RAS Command Decode Pin Configuration d d f ili d di f h i f Notes: 1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 2. UDM and LDM are unidirectional signals (input only), but is internally loaded to match the load of the bidirectional DQ, UDQS and LDQS signals. Data Sheet 14 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description 3 Functional Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-datarate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. 3.1 Initialization DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following criteria must be met: No power sequencing is specified during power up or power down given the following criteria: * * * * * * VDD and VDDQ are driven from a single power converter output VTT meets the specification A minimum resistance of 42 limits the input current from the VTT supply into any pin and VREF tracks VDDQ/2 or the following relationship must be followed: VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3 V VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3 V VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3 V The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200s delay prior to applying an executable command. Once the 200s delay has been satisfied, a Deselect or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a Precharge ALL command should be applied. Next a Mode Register Set command should be issued for the Extended Mode Register, to enable the DLL, then a Mode Register Set command should be issued for the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and any executable command. During the 200 cycles of clock for DLL locking, a Deselect or NOP command must be applied. After the 200 clock cycles, a Precharge ALL command should be applied, placing the device in the "all banks idle" state. Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a Mode Register Set command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation. Data Sheet 15 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description 3.2 Mode Register Definition The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4A6 specify the CAS latency, and A7-A12 specify the operating mode. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements results in unspecified operation. MR Mode Register Definition BA1 BA0 0 0 A12 (BA[1:0] = 00B) A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 OPERATING MODE CL BT BL w w w w reg. addr A0 Field Bits Type Description BL [2:0] w Burst Length Number of sequential bits per DQ related to one read/write command; see Chapter 3.2.1. Note: All other bit combinations are RESERVED. 001 2 010 4 011 8 BT 3 w Burst Type See Table 4 for internal address sequence of low order address bits; see Chapter 3.2.2. 0 Sequential 1 Interleaved CL [6:4] w CAS Latency Number of full clocks from read command to first data valid window; see Chapter 3.2.3. Note: All other bit combinations are RESERVED. 010 011 101 110 MODE [12:3] w 2 (3.0 Optional, not covered by this data sheet) 2.5 1.5 for DDR200 components only Operating Mode Note: All other bit combinations are RESERVED. 0 Data Sheet Normal Operation 16 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description 3.2.1 Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both Read and Write bursts. 3.2.2 Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 4. Table 4 Burst Length Burst Definition Starting Column Address A2 A1 A0 Type = Sequential Type = Interleaved 0 0-1 0-1 1 1-0 1-0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 2 4 8 Data Sheet Order of Accesses Within a Burst 17 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description Notes: 1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block. 3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 3.2.3 Read Latency The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2, 2.5 or 3 clocks. CAS latency of 1.5 is an optional feature on this device. If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m (see Figure 6). Reserved states should not be used as unknown operation or incompatibility with future versions may result. Data Sheet 18 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description 3.2.4 Operating Mode The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set command to select normal operating mode. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used as unknown operation or incompatibility with future versions may result. CAS Latency = 2, BL = 4 CK CK Command Read NOP NOP NOP NOP NOP CL=2 DQS DQ CAS Latency = 2.5, BL = 4 CK CK Command Read NOP NOP NOP NOP NOP CL=2.5 DQS DQ Don't Care Shown with nominal tAC, tDQSCK, and tDQSQ. Figure 6 Data Sheet Required CAS Latencies 19 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description 3.3 Extended Mode Register The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, and output drive strength selection (optional). These functions are controlled via the bits shown in the Extended Mode Register Definition. The Extended Mode Register is programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in unspecified operation. 3.3.1 DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur before a Read command can be issued. This is the reason 200 clock cycles must occur before issuing a Read or Write command upon exit of self refresh operation. 3.3.2 Output Drive Strength The normal drive strength for all outputs is specified to be SSTL_2, Class II. In addition this design version supports a weak driver mode for lighter load and/or point-to-point environments which can be activated during mode register set. I-V curves for the normal and weak drive strength are included in this document. EMR Extended Mode Register Definition BA1 BA0 0 1 A12 A11 A10 (BA[1:0] = 01B) A9 A8 A2 A1 A0 OPERATING MODE 0 DS DLL w w w w reg. addr A7 A6 A5 A4 Field Bits Type Description DLL 0 w DLL Status See Chapter 3.3.1. 0 Enabled 1 Disabled DS 1 w Drive Strength See Chapter 3.3.2, Chapter 4.2 and Chapter 4.3. 0 Normal 1 Weak 0 2 w 0 MODE [12:3] w Operating Mode A3 must be set to 0 Note: All other bit combinations are RESERVED. 0 Data Sheet Normal Operation 20 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description 3.4 Commands Deselect The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. No Operation (NOP) The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Mode Register Set The mode registers are loaded via inputs A0-A12, BA0 and BA1. See mode register descriptions in the Register Definition section. The Mode Register Set command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met. Active The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and completed before opening a different row in the same bank. Read The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 8, j = don't care] for x 16, [i = 9, j = don't care] for x 8 and [i = 9, j = 11] for x 4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Write The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don't care] for x 8; where [i = 9, j = 11] for x 4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if the DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that byte/column location. Precharge The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the Precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write commands being issued to that bank. A precharge command is treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging. Data Sheet 21 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description Auto Precharge Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific Read or Write command. A precharge of the bank/row that is addressed with the Read or Write command is automatically performed upon completion of the Read or Write burst. Auto Precharge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge (tRP) is completed. This is determined as if an explicit Precharge command was issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet. Burst Terminate The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most recently registered Read command prior to the Burst Terminate command is truncated, as shown in the Operation section of this data sheet. Auto Refresh Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an Auto Refresh command. The 1 Gb DDR SDRAM requires Auto Refresh cycles at an average periodic interval of 7.8 s (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Auto Refresh commands can be posted in the system, meaning that the maximum absolute interval between any Auto Refresh command and the next Auto Refresh command is 9 x 7.8 s (70.2 s). This maximum absolute interval is short enough to allow for DLL updates internal to the DDR SDRAM to be restricted to Auto Refresh cycles, without allowing too much drift in tAC between updates. Self Refresh The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The DLL is automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before a Read command can be issued). Input signals except CKE (low) are "Don't Care" during Self Refresh operation. The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE returning high. Once CKE is high, the SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command. Data Sheet 22 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description Table 5 Truth Table 1a: Commands Name (Function) CS RAS CAS WE Address MNE Notes Deselect (NOP) H X X X X NOP 1)9) No Operation (NOP) L H H H X NOP 1)9)2) Active (Select Bank And Activate Row) L L H H Bank/Row ACT 1)3) Read (Select Bank And Column, And Start Read Burst) L H L H Bank/Col Read 1)4) Write (Select Bank And Column, And Start Write Burst) L H L L Bank/Col Write 1)4)5) Burst Terminate L H H L X BST 1)8)6) Precharge (Deactivate Row In Bank Or Banks) L L H L Code PRE 1)5)7) Auto Refresh Or Self Refresh (Enter Self Refresh Mode) L L L H X AR/ SR 1)6)7)8) Mode Register Set L L L L Op-Code MRS 1)2)9) 1) CKE is HIGH for all commands shown except Self Refresh. 2) Deselect and NOP are functionally interchangeable. 3) BA0-BA1 provide bank address and A0-A12 provide row address. 4) BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8 for x16, i = 9 for x8 and 9, 11 for x4); A10 HIGH enables the Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature. 5) Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto Precharge enabled or for write bursts. 6) A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are "Don't Care". 7) This command is AUTO REFRESH if CKE is HIGH; Self Refresh if CKE is LOW. 8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are "Don't Care" except for CKE. 9) BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode Register). Table 6 Truth Table 1b: DM Operation Name (Function) DM DQs Notes Write Enable L Valid 1) Write Inhibit H X 1) 1) Used to mask write data; provided coincident with the corresponding data. Data Sheet 23 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description 3.5 Operations 3.5.1 Bank/Row Activation Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be "opened" (activated). This is accomplished via the Active command and addresses A0-A13, BA0 and BA1 (see Figure 7), which decode and select both the bank and the row to be activated. After opening a row (issuing an Active command), a Read or Write command may be issued to that row, subject to the tRCD specification. A subsequent Active command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive Active commands to the same bank is defined by tRC. A subsequent Active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive Active commands to different banks is defined by tRRD. CK CK CKE HIGH CS RAS CAS WE Figure 7 A0-A12 RA BA0, BA1 BA RA = row address. BA = bank address. Don't Care Activating a Specific Row in a Specific Bank CK CK NOP ACT NOP ACT A0-A12 ROW ROW COL BA0, BA1 BA x BA y BA y tRRD NOP RD/WR Command NOP NOP tRCD Don't Care Figure 8 Data Sheet tRCD and tRRD Definition 24 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description 3.5.2 Reads Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a Read command, as shown on Figure 9 "Read Command" on Page 25. The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion of the burst, provided tRAS has been satisfied. For the generic Read commands used in the following illustrations, Auto Precharge is disabled. During Read bursts, the valid data-out element from the starting column address is available following the CAS latency after the Read command. Each subsequent data-out element is valid nominally at the next positive or negative clock edge (i.e. at the next crossing of CK and CK). Figure 10 "Read Burst: CAS Latencies (Burst Length = 4)" on Page 26 shows general timing for each supported CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial low state on DQS is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble. Upon completion of a burst, assuming no other commands have been initiated, the DQs goes High-Z. Data from any Read burst may be concatenated with or truncated with data from a subsequent Read command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new Read command should be issued x cycles after the first Read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown on Figure 11 "Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8)" on Page 27. A Read command can be initiated on any clock cycle following a previous Read command. Nonconsecutive Read data is illustrated on Figure 12 "Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)" on Page 28. Full-speed Figure 13 "Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)" on Page 29 within a page (or pages) can be performed as shown on Figure 13. CK CK CKE HIGH CS RAS CAS WE x4: A0-A9, A11 x8: A0-A9 x16: A0-A8 CA EN AP A10 DIS AP BA0, BA1 CA = column address BA = bank address EN AP = enable Auto Precharge DIS AP = disable Auto Precharge BA Don't Care Figure 9 Data Sheet Read Command 25 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description CAS Latency = 2 CK CK Command Address Read NOP NOP NOP NOP NOP BA a,COL n CL=2 DQS DOa-n DQ CAS Latency = 2.5 CK CK Command Address Read NOP NOP NOP NOP NOP BA a,COL n CL=2.5 DQS DOa-n DQ DO a-n = data out from bank a, column n. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal tAC, tDQSCK, and tDQSQ. Figure 10 Data Sheet Don't Care Read Burst: CAS Latencies (Burst Length = 4) 26 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description CAS Latency = 2 CK CK Command Address Read NOP Read BAa, COL n NOP NOP NOP BAa, COL b CL=2 DQS DQ DOa-b DOa-n CAS Latency = 2.5 CK CK Command Address Read NOP Read BAa, COL n NOP NOP NOP BAa,COL b CL=2.5 DQS DOa- n DQ DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). When burst length = 4, the bursts are concatenated. When burst length = 8, the second burst interrupts the first. 3 subsequent elements of data out appear in the programmed order following DO a-n. 3 (or 7) subsequent elements of data out appear in the programmed order following DO a-b. Shown with nominal tAC, tDQSCK, and tDQSQ. Figure 11 Data Sheet DOa- b Don't Care Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8) 27 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description CAS Latency = 2 CK CK Read Command Address NOP NOP Read BAa, COL n NOP NOP BAa, COL b CL=2 DQS DO a-n DQ DOa- b CAS Latency = 2.5 CK CK Command Address Read NOP BAa, COL n NOP Read NOP NOP NOP BAa, COL b CL=2.5 DQS DQ DO a-n DOa- b DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). 3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b). Shown with nominal tAC, tDQSCK, and tDQSQ. Figure 12 Data Sheet Don't Care Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4) 28 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description CAS Latency = 2 CK CK Command Address Read Read Read Read BAa, COL n BAa, COL x BAa, COL b BAa, COL g NOP NOP CL=2 DQS DQ DOa-n DOa-n' DOa-x DOa-x' DOa-b DOa-b' DOa-g CAS Latency = 2.5 CK CK Command Address Read Read Read Read BAa, COL n BAa, COL x BAa, COL b BAa, COL g NOP NOP CL=2.5 DQS DQ DOa-n DOa-n' DOa-x DOa-x' DO a-n, etc. = data out from bank a, column n etc. n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted). Reads are to active rows in any banks. Shown with nominal tAC, tDQSCK, and tDQSQ. Figure 13 DOa-b DOa-b' Don't Care Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8) Data from any Read burst may be truncated with a Burst Terminate command, as shown on Figure 14 "Terminating a Read Burst: CAS Latencies (Burst Length = 8)" on Page 30. The Burst Terminate latency is equal to the read (CAS) latency, i.e. the Burst Terminate command should be issued x cycles after the Read command, where x equals the number of desired data element pairs. Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If truncation is necessary, the Burst Terminate command must be used, as shown on Figure 15 "Read to Write: CAS Latencies (Burst Length = 4 or 8)" on Page 31. The example is shown for tDQSS (min). The tDQSS (max) case, not shown here, has a longer bus idle time. tDQSS (min) and tDQSS (max) are defined in the section on Writes. A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto Precharge was not activated). The Precharge command should be issued x cycles after the Read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown on Figure 16 "Read to Precharge: CAS Latencies (Burst Length = 4 or 8)" on Page 32 for Read latencies of 2 and 2.5. Following the Precharge command, a subsequent command to the same bank cannot be Data Sheet 29 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data elements. In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as described above) provides the same operation that would result from the same Read burst with Auto Precharge enabled. The disadvantage of the Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to truncate bursts. CAS Latency = 2 CK CK Command Address Read NOP BST NOP NOP NOP BAa, COL n CL=2 DQS DQ DOa-n No further output data after this point. DQS tristated. CAS Latency = 2.5 CK CK Command Address Read NOP BST NOP NOP NOP BAa, COL n CL=2.5 DQS DQ DOa-n No further output data after this point. DQS tristated. DO a-n = data out from bank a, column n. Cases shown are bursts of 8 terminated after 4 data elements. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal tAC, tDQSCK, and tDQSQ. Figure 14 Data Sheet Don't Care Terminating a Read Burst: CAS Latencies (Burst Length = 8) 30 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description CAS Latency = 2 CK CK Command Address Read BST NOP Write BAa, COL n NOP NOP BAa, COL b CL=2 tDQSS (min) DQS DQ DI a-b DOa-n DM CAS Latency = 2.5 CK CK Command Address Read BST NOP NOP BAa, COL n Write NOP BAa, COL b CL=2.5 tDQSS (min) DQS DOa-n DQ Dla-b DM DO a-n = data out from bank a, column n .DI a-b = data in to bank a, column b 1 subsequent elements of data out appear in the programmed order following DO a-n. Data In elements are applied following Dl a-b in the programmed order, according to burst length. Shown with nominal tAC, tDQSCK, and tDQSQ. Figure 15 Data Sheet Don't Care Read to Write: CAS Latencies (Burst Length = 4 or 8) 31 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description CAS Latency = 2 CK CK Command Read NOP PRE NOP NOP ACT tRP Address BA a or all BA a, COL n BA a, ROW CL=2 DQS DQ DOa-n CAS Latency = 2.5 CK CK Command Read NOP PRE NOP NOP ACT tRP Address BA a or all BA a, COL n BA a, ROW CL=2.5 DQS DQ DOa-n DO a-n = data out from bank a, column n. Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal tAC, tDQSCK, and tDQSQ. Figure 16 Data Sheet Don't Care Read to Precharge: CAS Latencies (Burst Length = 4 or 8) 32 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description 3.5.3 Writes Write bursts are initiated with a Write command, as shown on Figure 17 "Write Command" on Page 34. The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic Write commands used in the following illustrations, Auto Precharge is disabled. During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the write command, and subsequent data elements are registered on successive edges of DQS. The Low state on DQS between the Write command and the first rising edge is known as the write preamble; the Low state on DQS following the last data-in element is known as the write postamble. The time between the Write command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75% to 125% of one clock cycle), so most of the Write diagrams that follow are drawn for the two extreme cases (i.e. tDQSS (min) and tDQSS (max)). Figure 18 "Write Burst (Burst Length = 4)" on Page 35 shows the two extremes of tDQSS for a burst of four. Upon completion of a burst, assuming no other commands have been initiated, the DQs and DQS enters High-Z and any additional input data is ignored. Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case, a continuous flow of input data can be maintained. The new Write command can be issued on any positive edge of clock following the previous Write command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new Write command should be issued x cycles after the first Write command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). Figure 19 "Write to Write (Burst Length = 4)" on Page 36 shows concatenated bursts of 4. An example of non-consecutive Writes is shown on Figure 20 "Write to Write: Max. DQSS, Non-Consecutive (Burst Length = 4)" on Page 37. Full-speed random write accesses within a page or pages can be performed as shown on Figure 21 "Random Write Cycles (Burst Length = 2, 4 or 8)" on Page 38. Data for any Write burst may be followed by a subsequent Read command. To follow a Write without truncating the write burst, tWTR (Write to Read) should be met as shown on Figure 22 "Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)" on Page 39. Data for any Write burst may be truncated by a subsequent Read command, as shown in the figures on Figure 23 "Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8)" on Page 40 to Figure 25 "Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)" on Page 42. Note that only the data-in pairs that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in must be masked with DM, as shown in the diagrams noted previously. Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without truncating the write burst, tWR should be met as shown on Figure 26 "Write to Precharge: Non-Interrupting (Burst Length = 4)" on Page 43. Data for any Write burst may be truncated by a subsequent Precharge command, as shown in the figures on Figure 27 "Write to Precharge: Interrupting (Burst Length = 4 or 8)" on Page 44 to Figure 29 "Write to Precharge: Nominal DQSS (2-bit Write), Interrupting (Burst Length = 4 or 8)" on Page 46. Note that only the data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data in should be masked with DM. Following the Precharge command, a subsequent command to the same bank cannot be issued until tRP is met. In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time (as described above) provides the same operation that would result from the same burst with Auto Precharge. The disadvantage of the Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to truncate bursts. Data Sheet 33 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description CK CK CKE HIGH CS RAS CAS WE x4: A0-A9, A11 x8: A0-A9 x16: A0-A8 CA EN AP A10 DIS AP BA0, BA1 CA = column address BA = bank address EN AP = enable Auto Precharge DIS AP = disable Auto Precharge BA Don't Care Figure 17 Data Sheet Write Command 34 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description Maximum DQSS T1 T2 T3 T4 CK CK Command Address Write NOP NOP NOP BA a, COL b tDQSS (max) DQS Dla-b DQ DM Minimum DQSS T1 T2 T3 T4 CK CK Command Address Write NOP NOP NOP BA a, COL b tDQSS (min) DQS DQ Dla-b DM DI a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following DI a-b. A non-interrupted burst is shown. A10 is Low with the Write command (Auto Precharge is disabled). Don't Care Figure 18 Data Sheet Write Burst (Burst Length = 4) 35 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description Maximum DQSS T1 T2 T3 T4 T5 T6 CK CK Command Address Write NOP Write BAa, COL b NOP NOP NOP BAa, COL n tDQSS (max) DQS DI a-b DQ DI a-n DM Minimum DQSS T1 T2 T3 T4 T5 T6 CK CK Command Address Write NOP BA, COL b Write NOP NOP NOP BA, COL n tDQSS (min) DQS DQ DI a-b DI a-n DM DI a-b = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following DI a-b. 3 subsequent elements of data in are applied in the programmed order following DI a-n. A non-interrupted burst is shown. Each Write command may be to any bank. Figure 19 Data Sheet Don't Care Write to Write (Burst Length = 4) 36 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description T1 T2 T3 T4 T5 CK CK Command Address Write NOP NOP BAa, COL b Write NOP BAa, COL n tDQSS (max) DQS DQ DI a-b DI a-n DM DI a-b, etc. = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following DI a-b. 3 subsequent elements of data in are applied in the programmed order following DI a-n. A non-interrupted burst is shown. Each Write command may be to any bank. Figure 20 Data Sheet Don't Care Write to Write: Max. DQSS, Non-Consecutive (Burst Length = 4) 37 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description Maximum DQSS T1 T2 T3 T4 T5 CK CK Command Address Write Write BAa, COL b Write BAa, COL x Write BAa, COL n Write BAa, COL a BAa, COL g tDQSS (max) DQS DQ DI a-b DI a-b' DI a-x DI a-x' DI a-n DI a-n' DI a-a DI a-a' DM Minimum DQSS T1 T2 T3 T4 T5 CK CK Command Address Write Write BAa, COL b Write BAa, COL x Write BAa, COL n Write BAa, COL a BAa, COL g tDQSS (min) DQS DQ DI a-b DI a-b' DI a-x DI a-x' DI a-n DI a-n' DI a-a DI a-a' DI a-g DM DI a-b, etc. = data in for bank a, column b, etc. b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted). Each Write command may be to any bank. Figure 21 Data Sheet Don't Care Random Write Cycles (Burst Length = 2, 4 or 8) 38 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description Maximum DQSS T1 T2 T3 T4 T5 T6 CK CK Command Write NOP NOP NOP Read NOP tWTR Address BAa, COL b BAa, COL n CL = 2 tDQSS (max) DQS DQ DI a-b DM Minimum DQSS T1 T2 T3 T4 T5 T6 CK CK Command Write NOP NOP NOP Read NOP tWTR Address BAa, COL n BAa, COL b CL = 2 tDQSS (min) DQS DQ DI a-b DM DI a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following DI a-b. A non-interrupted burst is shown. tWTR is referenced from the first positive CK edge after the last data in pair. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands may be to any bank. Figure 22 Data Sheet Don't Care Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4) 39 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description Maximum DQSS T1 T2 T3 T4 T5 T6 CK CK Command Write NOP NOP NOP Read NOP tWTR Address BAa, COL n BAa, COL b CL = 2 tDQSS (max) DQS DQ DIa- b 1 DM 1 Minimum DQSS T1 T2 T3 T4 T5 T6 CK CK Command Write NOP NOP NOP Read NOP tWTR Address BAa, COL n BAa, COL b CL = 2 tDQSS (min) DQS DQ DI a-b 1 DM 1 DI a-b = data in for bank a, column b. An interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following DI a-b. tWTR is referenced from the first positive CK edge after the last data in pair. The Read command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands are not necessarily to the same bank. 1 = These bits are incorrectly written into the memory array if DM is low. Figure 23 Data Sheet Don't Care Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8) 40 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description T1 T2 T3 T4 T5 T6 CK CK Command Write NOP NOP NOP Read NOP tWTR Address BAa, COL n BAa, COL b CL = 2 tDQSS (min) DQS DQ DI a-b 1 DM 2 2 DI a-b = data in for bank a, column b. An interrupted burst is shown, 3 data elements are written. 2 subsequent elements of data in are applied in the programmed order following DI a-b. tWTR is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element) The Read command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands are not necessarily to the same bank. 1 = This bit is correctly written into the memory array if DM is low. Don't Care 2 = These bits are incorrectly written into the memory array if DM is low. Figure 24 Data Sheet Write to Read: Minimum DQSS, Odd Number of Data (3-bit Write), Interrupting (CAS Latency = 2; Burst Length = 8) 41 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description T1 T2 T3 T4 T5 T6 CK CK Command Write NOP NOP NOP Read NOP tWTR Address BAa, COL n BAa, COL b CL = 2 tDQSS (nom) DQS DQ DI a-b DM 1 1 DI a-b = data in for bank a, column b. An interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following DI a-b. tWTR is referenced from the first positive CK edge after the last desired data in pair. The Read command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands are not necessarily to the same bank. 1 = These bits are incorrectly written into the memory array if DM is low. Figure 25 Data Sheet Don't Care Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8) 42 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description Maximum DQSS T1 T2 T3 T4 T5 T6 CK CK Command Write NOP NOP NOP NOP PRE tWR Address BA (a or all) BA a, COL b tRP tDQSS (max) DQS DQ DI a-b DM Minimum DQSS T1 T2 T3 T4 T5 T6 CK CK Command Write NOP NOP NOP NOP PRE tWR Address BA (a or all) BA a, COL b tRP tDQSS (min) DQS DQ DI a-b DM DI a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following DI a-b. A non-interrupted burst is shown. tWR is referenced from the first positive CK edge after the last data in pair. A10 is Low with the Write command (Auto Precharge is disabled). Figure 26 Data Sheet Don't Care Write to Precharge: Non-Interrupting (Burst Length = 4) 43 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description Maximum DQSS T1 T2 T3 T4 T5 T6 CK CK Command Write NOP NOP NOP PRE NOP tWR Address BA (a or all) BA a, COL b tDQSS (max) tRP 2 DQS DQ DI a-b 3 DM 1 3 1 Minimum DQSS T1 T2 T3 T4 T5 T6 CK CK Command Write NOP NOP NOP PRE NOP tWR Address BA a, COL b BA (a or all) tDQSS (min) tRP 2 DQS DQ DM DI a-b 3 3 1 1 DI a-b = data in for bank a, column b. An interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following DI a-b. tWR is referenced from the first positive CK edge after the last desired data in pair. The Precharge command masks the last 2 data elements in the burst, for burst length = 8. A10 is Low with the Write command (Auto Precharge is disabled). 1 = Can be don't care for programmed burst length of 4. 2 = For programmed burst length of 4, DQS becomes don't care at this point. 3 = These bits are incorrectly written into the memory array if DM is low. Figure 27 Data Sheet Don't Care Write to Precharge: Interrupting (Burst Length = 4 or 8) 44 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description T1 T2 T3 T4 T5 T6 CK CK Command Write NOP NOP NOP PRE NOP tWR Address BA (a or all) BA a, COL b tDQSS (min) tRP 2 DQS DQ DM DI a-b 3 4 4 1 1 DI a-b = data in for bank a, column b. An interrupted burst is shown, 1 data element is written. tWR is referenced from the first positive CK edge after the last desired data in pair. The Precharge command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). 1 = Can be don't care for programmed burst length of 4. 2 = For programmed burst length of 4, DQS becomes don't care at this point. 3 = This bit is correctly written into the memory array if DM is low. 4 = These bits are incorrectly written into the memory array if DM is low. Figure 28 Data Sheet Don't Care Write to Precharge: Minimum DQSS, Odd Number of Data (1-bit Write), Interrupting (Burst Length = 4 or 8) 45 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description T1 T2 T3 T4 T5 T6 CK CK Command Write NOP NOP NOP PRE NOP tWR Address BA a, COL b BA (a or all) tDQSS (nom) tRP 2 DQS DQ DM DI a-b 3 3 1 1 DI a-b = Data In for bank a, column b. An interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following DI a-b. tWR is referenced from the first positive CK edge after the last desired data in pair. The Precharge command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). 1 = Can be don't care for programmed burst length of 4. 2 = For programmed burst length of 4, DQS becomes don't care at this point. 3 = These bits are incorrectly written into the memory array if DM is low. Figure 29 Data Sheet Don't Care Write to Precharge: Nominal DQSS (2-bit Write), Interrupting (Burst Length = 4 or 8) 46 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description 3.5.4 Precharge The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the Precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write commands being issued to that bank. CK CK CKE HIGH CS RAS CAS WE A0-A9, A11, A12 All Banks A10 One Bank BA BA0, BA1 BA = bank address (if A10 is Low, otherwise Don't Care). Don't Care Figure 30 Data Sheet Precharge Command 47 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description 3.5.5 Power-Down Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK and CKE. The DLL is still running in Power Down mode, so for maximum power savings, the user has the option of disabling the DLL prior to entering Power-down. In that case, the DLL must be enabled after exiting power-down, and 200 clock cycles must occur before a Read command can be issued. In power-down mode, CKE Low and a stable clock signal must be maintained at the inputs of the DDR SDRAM, and all other input signals are "Don't Care". However, power-down duration is limited by the refresh requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled power-down mode. The power-down state is synchronously exited when CKE is registered HIGH (along with a Nop or Deselect command). A valid, executable command may be applied one clock cycle later. CK CK tIS CKE Command VALID tIS NOP NOP No column access in progress Exit power down mode Enter Power Down mode (Burst Read or Write operation must not be in progress) Figure 31 Data Sheet VALID Don't Care Power Down 48 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description Table 7 Truth Table 2: Clock Enable (CKE) Current State CKE n-1 Self Refresh CKEn Previous Cycle Current Cycle L L Command n Action n Notes X Maintain Self-Refresh - Self Refresh L H Deselect or NOP Exit Self-Refresh 1) Power Down L L X Maintain Power-Down - Power Down L H Deselect or NOP Exit Power-Down - All Banks Idle H L Deselect or NOP Precharge Power-Down Entry - All Banks Idle H L AUTO REFRESH Self Refresh Entry - Bank(s) Active H L Deselect or NOP Active Power-Down Entry - H H - See "Truth Table 3: Current State Bank n Command to Bank n (same bank)" on Page 49 - 1) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock. 1. 2. 3. 4. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge. Current state is the state of the DDR SDRAM immediately prior to clock edge n. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n. All states and sequences not shown are illegal or reserved. Table 8 Truth Table 3: Current State Bank n - Command to Bank n (same bank) Current State CS RAS CAS WE Command Action Notes Any H X X X Deselect NOP. Continue previous operation 1) to 6) L H H H No Operation NOP. Continue previous operation 1) to 6)2) L L H H Active Select and activate row 1) to 6)3) L L L H AUTO REFRESH - 1) to 7)4) L L L L MODE REGISTER SET - 1) to 7)5) L H L H Read Select column and start Read burst 1) to 6), 10) L H L L Write Select column and start Write burst 1) to 6), 10)7) L L H L Precharge Deactivate row in bank(s) 1) to 6), 8) L H L H Read Select column and start new Read burst 1) to 6), 10)9) L L H L Precharge Truncate Read burst, start Precharge 1) to 6), 8)10) L H H L BURST TERMINATE BURST TERMINATE 1) to 6), 9)11) L H L H Read Select column and start Read burst 1) to 6), 10), 11) L H L L Write Select column and start Write burst 1) to 6), 10) L L H L Precharge Truncate Write burst, start Precharge 1) to 6), 8), 11) Idle Row Active Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) 1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been met (if the previous state was self refresh). Data Sheet 49 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description 2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3) Current state definitions: Idle:The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4) The following states must not be interrupted by a command issued to the same bank. Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle state. Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the "row active" state. Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state& according to Truth Table 4. 5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR SDRAM is in the "all banks idle" state. Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM is in the "all banks idle" state. Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle state. 6) All states and sequences not shown are illegal or reserved. 7) Not bank-specific; requires that all banks are idle. 8) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. 9) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank. 10) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 11) Requires appropriate DM masking. Data Sheet 50 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description Table 9 Truth Table 4: Current State Bank n - Command to Bank m (different bank) Current State CS RAS CAS WE Command Action Notes Any H X X X Deselect NOP. Continue previous operation. 1) to 6)2)3)4)5)6) L H H H No Operation NOP. Continue previous operation. 1) to 6) Idle X X X X Any Command Otherwise Allowed to Bank m - 1) to 6) Row Activating, Active, or Precharging L L H H Active Select and activate row 1) to 6) L H L H Read Select column and start Read burst 1) to 7) L H L L Write Select column and start Write burst 1) to 7) L L H L Precharge - 1) to 6) L L H H Active Select and activate row 1) to 6) L H L H Read Select column and start new Read burst 1) to 7) L L H L Precharge - 1) to 6) L L H H Active Select and activate row 1) to 6) L H L H Read Select column and start Read burst 1) to 8) L H L L Write Select column and start new Write burst 1) to 7) L L H L Precharge - 1) to 6) Read (With Auto L Precharge) L L H H Active Select and activate row 1) to 6) H L H Read Select column and start new Read burst 1) to 7), 10)9) L H L L Write Select column and start Write burst 1) to 7), 9), 10) L L H L Precharge - 1) to 6) Write (With Auto L Precharge) L L H H Active Select and activate row 1) to 6) H L H Read Select column and start Read burst 1) to 7), 9) L H L L Write Select column and start new Write burst 1) to 7), 9) L L H L Precharge - 1) to 6) Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) 1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 7: Clock Enable (CKE) and after tXSNR/tXSRD has been met (if the previous state was self refresh). 2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. Data Sheet 51 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description 3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Read with Auto Precharge Enabled: See 10). Write with Auto Precharge Enabled: See 10). 4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle. 5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6) All states and sequences not shown are illegal or reserved. 7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8) Requires appropriate DM masking. 9) Concurrent Auto Precharge: This device supports "Concurrent Auto Precharge". When a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The minimum delay from a read or write command with auto precharge enable, to a command to a different banks is summarized in Table 10. 10) A Write command may be applied after the completion of data output. Table 10 Truth Table 5: Concurrent Auto Precharge From Command To Command (different bank) Minimum Delay with Concurrent Auto Precharge Support Unit WRITE w/AP Read or Read w/AP 1 + (BL/2) + tWTR Write to Write w/AP BL/2 Precharge or Activate 1 Read or Read w/AP BL/2 Write or Write w/AP CL (rounded up) + BL/2 Precharge or Activate 1 tCK tCK tCK tCK tCK tCK Read w/AP Data Sheet 52 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Functional Description 3.6 Simplified State Diagram Power Applied Power On Self Refresh Precharge PREALL REFS REFSX MRS EMRS MRS Auto Refresh REFA Idle CKEL CKEH Active Power Down ACT Precharge Power Down CKEH CKEL Burst Stop Row Active Write Write A Write Read Read A Read Read Read A Write A Read A PRE Write A PRE PRE PRE Read A Precharge PREALL Automatic Sequence Command Sequence PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh Figure 32 Data Sheet CKEL = Enter Power Down CKEH = Exit Power Down ACT = Active Write A = Write with Autoprecharge Read A = Read with Autoprecharge PRE = Precharge Simplified State Diagram 53 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Electrical Characteristics 4 Electrical Characteristics 4.1 Operating Conditions Table 11 Absolute Maximum Ratings Parameter Symbol Voltage on I/O pins relative to VSS VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT Values Unit Note/ Test Condition min. typ. max. Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current -0.5 - VDDQ+0.5 V - -1 - +3.6 V - -1 - +3.6 V - -1 - +3.6 V - 0 - +70 C - -55 - +150 C - - 1.5 - W - - 50 - mA - Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. Table 12 Input and Output Capacitances Parameter Input Capacitance: CK, CK Delta Input Capacitance Input Capacitance: All other input-only pins Delta Input Capacitance: All other input-only pins Symbol CI1 CdI1 CI2 CdIO Input/Output Capacitance: DQ, DQS, DM CIO Delta Input/Output Capacitance: DQ, DQS, DM CdIO Values Unit Note/ Test Condition Min. Typ. Max. 1.5 -- 2.5 pF TSOPII 1) 2.0 -- 3.0 pF TFBGA 1) -- -- 0.25 pF 1) 1.5 -- 2.5 pF TFBGA 1) 2.0 -- 3.0 pF TSOPII 1) -- -- 0.5 pF 1) 3.5 -- 4.5 pF TFBGA 1)2) 4.0 -- 5.0 pF TSOPII 1)2) -- -- 0.5 pF 1) 1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V 0.2 V, f = 100 MHz, TA = 25 C, VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground. 2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the board level. Data Sheet 54 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Electrical Characteristics Table 13 Electrical Characteristics and DC Operating Conditions Parameter Symbol VDD Device Supply Voltage VDD Output Supply Voltage VDDQ Output Supply Voltage VDDQ Supply Voltage, I/O Supply VSS, Voltage VSSQ VREF Input Reference Voltage I/O Termination Voltage VTT Device Supply Voltage Unit Note/Test Condition 1) Values Min. Typ. Max. 2.3 2.5 2.7 V 2.5 2.6 2.7 V 2.3 2.5 2.7 V 2.5 2.6 2.7 V fCK 166 MHz fCK > 166 MHz 2) fCK 166 MHz 3) fCK > 166 MHz 2)3) 0 V -- 0 0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V 4) VREF - 0.04 VREF + 0.04 V 5) Input High (Logic1) Voltage VIH(DC) VREF + 0.15 8) Input Low (Logic0) Voltage VIL(DC) -0.3 Input Voltage Level, CK and CK Inputs VIN(DC) -0.3 VDDQ + 0.3 V VREF - 0.15 V VDDQ + 0.3 V Input Differential Voltage, CK and CK Inputs VID(DC) 0.36 VDDQ + 0.6 V 8)6) VI-Matching Pull-up Current to Pull-down Current VIRatio 0.71 1.4 -- 7) Input Leakage Current II -2 2 A Any input 0 V VIN VDD; All other pins not under test = 0 V 8)9) Output Leakage Current IOZ -5 5 A DQs are disabled; 0 V VOUT VDDQ Output High Current, Normal Strength Driver IOH -- -16.2 mA VOUT = 1.95 V Output Low Current, Normal Strength Driver IOL 16.2 -- mA VOUT = 0.35 V (System) 8) 8) 1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400); 2) DDR400 conditions apply for all clock frequencies above 166 MHz 3) Under all conditions, VDDQ must be less than or equal to VDD. 4) Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. 5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 6) VID is the magnitude of the difference between the input level on CK and the input level on CK. 7) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 8) Inputs are not recognized as valid until VREF stabilizes. 9) Values are shown per component Data Sheet 55 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Electrical Characteristics 4.2 Normal Strength Pull-down and Pull-up Characteristics 1. The nominal pulldown V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve. 2. The full variation in driver pulldown current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the V-I curve. 3. The nominal pullup V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve. 4. The full variation in driver pullup current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the V-I curve. 5. The full variation in the ratio of the maximum to minimum pullup and pulldown current does not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 6. The full variation in the ratio of the nominal pullup to pulldown current should be unity 10%, for device drain to source voltages from 0.1 to 1.0 V. 140 Maximum 1OUT (mA) 120 100 Nominal High 80 60 Nominal Low 40 Minimum 20 0 Figure 33 0 0.5 1 1.5 VDDQ - VOUT (V) 2 2.5 Normal Strength Pull-down Characteristics 0 -20 Minimum IOUT (mA) -40 Nominal Low -60 -80 -100 -120 -140 Nominal High -160 Maximum 0 Figure 34 Data Sheet 0.5 1 1.5 VDDQ - Vout(V) 2 2.5 Normal Strength Pull-up Characteristics 56 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Electrical Characteristics Table 14 Normal Strength Pull-down and Pull-up Currents Voltage (V) Pulldown Current (mA) Pullup Current (mA) Nominal Low Nominal High min. max. Nominal Low Nominal High min. max. 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0 0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0 0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8 0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8 0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8 0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4 0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8 0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5 0.9 47.5 55.2 39.6 69.9 -43.8 -59.4 -38.2 -77.3 1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2 1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0 1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6 1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1 1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5 1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0 1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4 1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7 1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2 1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5 2.0 62.5 97.2 49.4 123.3 -51.6 -124.0 -40.5 -156.9 2.1 62.9 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2 2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6 2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0 2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3 2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6 2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2 Table 15 Pull-down and Pull-up Process Variations and Conditions Parameter Nominal Minimum Maximum Operating Temperature 25 C 0 C 70 C VDD/VDDQ 2.5 V 2.3 V 2.7 V Process Corner typical slow-slow fast-fast Data Sheet 57 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Electrical Characteristics 4.3 Weak Strength Pull-down and Pull-up Characteristics 1. The weak pulldown V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve 2. The weak pullup V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve. 3. The full variation in driver pullup current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the V-I curve. 4. The full variation in the ratio of the maximum to minimum pullup and pulldown current does not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 5. The full variation in the ratio of the nominal pullup to pulldown current should be unity 10%, for device drain to source voltages from 0.1 to 1.0V. 80 Maximum 70 Iout [mA] 60 Typical high 50 Typical low 40 30 Minimum 20 10 0 0,0 0,5 1,0 1,5 2,0 2,5 Vout [V] Figure 35 Weak Strength Pull-down Characteristics 0,0 0,0 0,5 1,0 1,5 2,0 2,5 -10,0 Minimum -20,0 Iout [V] -30,0 Typical low -40,0 -50,0 Typical high -60,0 -70,0 Maximum -80,0 Vout [V] Figure 36 Data Sheet Weak Strength Pull-up Characteristics 58 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Electrical Characteristics Table 16 Weak Strength Driver Pull-down and Pull-up Characteristics Voltage (V) Pulldown Current (mA) Pullup Current (mA) Nominal Low Nominal High min. max. Nominal Low Nominal High min. max. 0.1 3.4 3.8 2.6 5.0 -3.5 -4.3 -2.6 -5.0 0.2 6.9 7.6 5.2 9.9 -6.9 -8.2 -5.2 -9.9 0.3 10.3 11.4 7.8 14.6 -10.3 -12.0 -7.8 -14.6 0.4 13.6 15.1 10.4 19.2 -13.6 -15.7 -10.4 -19.2 0.5 16.9 18.7 13.0 23.6 -16.9 -19.3 -13.0 -23.6 0.6 19.6 22.1 15.7 28.0 -19.4 -22.9 -15.7 -28.0 0.7 22.3 25.0 18.2 32.2 -21.5 -26.5 -18.2 -32.2 0.8 24.7 28.2 20.8 35.8 -23.3 -30.1 -20.4 -35.8 0.9 26.9 31.3 22.4 39.5 -24.8 -33.6 -21.6 -39.5 1.0 29.0 34.1 24.1 43.2 -26.0 -37.1 -21.9 -43.2 1.1 30.6 36.9 25.4 46.7 -27.1 -40.3 -22.1 -46.7 1.2 31.8 39.5 26.2 50.0 -27.8 -43.1 -22.2 -50.0 1.3 32.8 42.0 26.6 53.1 -28.3 -45.8 -22.3 -53.1 1.4 33.5 44.4 26.8 56.1 -28.6 -48.4 -22.4 -56.1 1.5 34.0 46.6 27.0 58.7 -28.7 -50.7 -22.6 -58.7 1.6 34.3 48.6 27.2 61.4 -28.9 -52.9 -22.7 -61.4 1.7 34.5 50.5 27.4 63.5 -28.9 -55.0 -22.7 -63.5 1.8 34.8 52.2 27.7 65.6 -29.0 -56.8 -22.8 -65.6 1.9 35.1 53.9 27.8 67.7 -29.2 -58.7 -22.9 -67.7 2.0 35.4 55.0 28.0 69.8 -29.2 -60.0 -22.9 -69.8 2.1 35.6 56.1 28.1 71.6 -29.3 -61.2 -23.0 -71.6 2.2 35.8 57.1 28.2 73.3 -29.5 -62.4 -23.0 -73.3 2.3 36.1 57.7 28.3 74.9 -29.5 -63.1 -23.1 -74.9 2.4 36.3 58.2 28.3 76.4 -29.6 -63.8 -23.2 -76.4 2.5 36.5 58.7 28.4 77.7 -29.7 -64.4 -23.2 -77.7 2.6 36.7 59.2 28.5 78.8 -29.8 -65.1 -23.3 -78.8 2.7 36.8 59.6 28.6 79.7 -29.9 -65.8 -23.3 -79.7 Table 17 Evaluation Conditions for I/O Driver Characteristics Parameter Nominal Minimum Maximum Operating Temperature 25 70 0 VDD/VDDQ 2.5 2.3 2.7 Process Corner typ. slow-slow fast-fast Data Sheet 59 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Electrical Characteristics 4.4 AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD Specifications and Conditions, and Electrical Characteristics and AC Timing.) Notes: 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Figure 37 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level). 6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR SDRAM Slew Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the latest JEDEC specification for DDR components. VTT 50 Output (VOUT) Timing Reference Point 30 pF Figure 37 Data Sheet AC Output Load Circuit Diagram / Timing Reference Load 60 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Electrical Characteristics Table 18 AC Operating Conditions1) Parameter Symbol Values Min. VIH(AC) VIL(AC) VID(AC) VIX(AC) Input High (Logic 1) Voltage, DQ, DQS and DM Signals Input Low (Logic 0) Voltage, DQ, DQS and DM Signals Input Differential Voltage, CK and CK Inputs Input Closing Point Voltage, CK and CK Inputs Unit Note/ Test Condition Max. VREF + 0.31 -- -- VREF - 0.31 0.7 VDDQ + 0.6 0.5 x VDDQ 0.5 x VDDQ - 0.2 V 2)3) V 2)3) V 2)3)4) V 2)3)5) + 0.2 1) VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR200 - DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400); 0 C TA 70 C 2) Input slew rate = 1 V/ns. 3) Inputs are not recognized as valid until VREF stabilizes. 4) VID is the magnitude of the difference between the input level on CK and the input level on CK. 5) The value of VIX is expected to equal 0.5 x VDDQ of the transmitting device and must track variations in the DC level of the same. Table 19 AC Timing - Absolute Specifications for DDR333 and DDR400B Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time Symbol tAC tDQSCK tCH tCL tHP tCK -6 -5 DDR333 DDR400B Unit Note/ Test Condition 1) Min. Max. Min. Max. -0.7 +0.7 -0.5 +0.5 ns 2)3)4)5) -0.6 +0.6 -0.6 +0.6 ns 2)3)4)5) 0.45 0.55 0.45 0.55 2)3)4)5) 0.45 0.55 0.45 0.55 tCK tCK ns 2)3)4)5) min. (tCL, tCH) -- -- min. (tCL, tCH) 5 8 ns 2)3)4)5) CL = 3.0 2)3)4)5) 7.5 12 6 12 ns CL = 2.5 2)3)4)5) 7.5 12 7.5 12 ns CL = 2.0 2)3)4)5) tDH tDS tIPW 0.45 -- 0.4 -- ns 2)3)4)5) 0.45 -- 0.4 -- ns 2)3)4)5) 2.2 -- 2.2 -- ns 2)3)4)5)6) DQ and DM input pulse width (each input) tDIPW 1.75 -- 1.75 -- ns 2)3)4)5)6) Data-out high-impedance time from CK/CK tHZ -0.7 +0.7 -0.7 +0.7 ns 2)3)4)5)7) Data-out low-impedance time from CK/CK tLZ -0.7 +0.7 -0.7 +0.7 ns 2)3)4)5)7) Write command to 1st DQS latching transition tDQSS 0.75 1.25 0.75 1.25 tCK 2)3)4)5) DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input) Data Sheet 61 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Electrical Characteristics Table 19 AC Timing - Absolute Specifications for DDR333 and DDR400B Parameter Symbol DDR333 DDR400B Max. Min. Max. +0.45 -- +0.40 tDQSQ -- Data hold skew factor tQHS -- tQH DQS input low (high) pulse width (write tDQSL,H -5 Min. DQS-DQ skew (DQS and associated DQ signals) DQ/DQS output hold time -6 Unit ns Note/ Test Condition 1) TSOPII 2)3)4)5) +0.55 -- +0.50 ns TSOPII 2)3)4)5) tHP -tQHS tHP -tQHS ns 2)3)4)5) 0.35 -- 0.35 -- tCK 2)3)4)5) cycle) DQS falling edge to CK setup time (write cycle) tDSS 0.2 -- 0.2 -- tCK 2)3)4)5) DQS falling edge hold time from CK (write cycle) tDSH 0.2 -- 0.2 -- tCK 2)3)4)5) 2 -- 2 -- tCK 2)3)4)5) 0 -- 0 -- ns 2)3)4)5)8) 0.40 0.60 0.40 0.60 2)3)4)5)9) 0.25 -- 0.25 -- tCK tCK 0.75 -- 0.6 -- ns fast slew rate Mode register set command cycle time tMRD Write preamble setup time Write postamble Write preamble Address and control input setup time tWPRES tWPST tWPRE tIS 2)3)4)5) 3)4)5)6)10) 0.8 -- 0.7 -- ns slow slew rate 3)4)5)6)10) Address and control input hold time tIH 0.75 -- 0.6 -- ns fast slew rate 3)4)5)6)10) 0.8 -- 0.7 -- ns slow slew rate 3)4)5)6)10) tRPRE Read postamble tRPST Active to Precharge command tRAS Active to Active/Auto-refresh command tRC Read preamble 2)3)4)5) 0.60 tCK tCK 40 70E+3 ns 2)3)4)5) -- 55 -- ns 2)3)4)5) 0.9 1.1 0.9 1.1 0.40 0.60 0.40 42 70E+3 60 2)3)4)5) period Auto-refresh to Active/Auto-refresh command period tRFC 72 -- 70 -- ns 2)3)4)5) Active to Read or Write delay tRCD tRP tRAP tRRD 18 -- 15 -- ns 2)3)4)5) 18 -- 15 -- ns 2)3)4)5) tWR tDAL Precharge command period Active to Autoprecharge delay Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time tWTR Exit self-refresh to non-read command tXSNR Internal write to read command delay Data Sheet tRCD - tRASmin tRCD - tRASmin ns 2)3)4)5) 12 -- 10 -- ns 2)3)4)5) 15 -- 15 -- ns 2)3)4)5) tCK 2)3)4)5)11) 1 -- 1 -- tCK 2)3)4)5) 75 -- 75 -- ns 2)3)4)5) 62 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Electrical Characteristics Table 19 AC Timing - Absolute Specifications for DDR333 and DDR400B Parameter Symbol Exit self-refresh to read command Average Periodic Refresh Interval tXSRD tREFI -6 -5 DDR333 DDR400B Unit Note/ Test Condition 1) Min. Max. Min. Max. 200 -- 200 -- tCK 2)3)4)5) -- 7.8 -- 7.8 s 2)3)4)5)12) 1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400) 2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VIH(ac) and VIL(ac). 11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. Table 20 AC Timing - Absolute Specifications DDR266A, DDR266 and DDR200 Parameter Symbol -7 DDR266A Min. Max. -7F -8 DDR266 Min. Max. DDR200 Min. Max. Unit Note/ Test Condition 1) DQ output access time from CK/CK tAC -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 2)3)4)5) DQS output access time from CK/CK tDQSCK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 2)3)4)5) 0.45 0.55 0.45 0.55 0.45 0.55 2)3)4)5) 0.45 0.55 0.45 0.55 0.45 0.55 tCK tCK ns 2)3)4)5) CL = 2.5 2)3)4)5) tCH CK low-level width tCL Clock Half Period tHP Clock cycle time tCK2.5 tCK2 DQ and DM input hold time tDH DQ and DM input setup tDS CK high-level width min. (tCL, tCH) min. (tCL, tCH) min. (tCL, tCH) 2)3)4)5) 7.5 12 7.5 12 10 12 ns 7.5 12 7.5 12 10 12 ns CL = 2.0 2)3)4)5) 0.5 -- 0.5 -- 0.6 -- ns 2)3)4)5) 0.5 -- 0.5 -- 0.6 -- ns 2)3)4)5) time Data Sheet 63 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Electrical Characteristics Table 20 AC Timing - Absolute Specifications DDR266A, DDR266 and DDR200 Parameter Symbol -7 -7F -8 DDR266A DDR266 DDR200 Min. Max. Min. Max. Min. Max. Unit Note/ Test Condition 1) Control and Addr. input pulse width (each input) tIPW 2.2 -- 2.2 -- 2.5 -- ns 2)3)4)5)6) DQ and DM input pulse width (each input) tDIPW 1.75 -- 1.75 -- 2 -- ns 2)3)4)5)6) Data-out high-impedance time from CK/CK tHZ -0.75 +0.75 -0.75 +0.75 -- +0.8 ns 2)3)4)5)7) Data-out low-impedance time from CK/CK tLZ -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 2)3)4)5)7) 0.75 1.25 0.75 1.25 0.75 1.25 tCK 2)3)4)5) -- +0.5 -- +0.5 -- +0.6 ns FBGA2)3)4)5) -- +0.5 -- +0.5 -- +0.6 ns TSOP2)3)4)5) -- +0.75 -- +0.75 -- +1.0 ns FBGA2)3)4)5) -- +0.75 -- +0.75 -- +1.0 ns TSOP2)3)4)5) ns 2)3)4)5) Write command to 1st DQS tDQSS latching transition DQS-DQ skew (DQS and associated DQ signals) tDQSQ Data hold skew factor tQHS tQH DQS input low (high) pulse tDQSL,H tHP - tQHS tHP -tQHS tHP -tQHS 0.35 -- 0.35 -- 0.35 -- tCK 2)3)4)5) tDSS 0.2 -- 0.2 -- 0.2 -- tCK 2)3)4)5) DQS falling edge hold time tDSH from CK (write cycle) 0.2 -- 0.2 -- 0.2 -- tCK 2)3)4)5) 2 -- 2 -- 2 -- tCK 2)3)4)5) 0 -- 0 -- 0 -- ns 2)3)4)5)8) 0.40 0.60 0.40 0.60 0.40 0.60 2)3)4)5)9) 0.25 -- 0.25 -- 0.25 -- tCK tCK 0.9 -- 0.9 -- 1.1 -- ns fast slew rate DQ/DQS output hold time width (write cycle) DQS falling edge to CK setup time (write cycle) Mode register set command cycle time tMRD Write preamble setup time tWPRES Write postamble Write preamble Address and control input setup time tWPST tWPRE tIS 2)3)4)5) 3)4)5)6)10) 1.0 -- 1.0 -- 1.1 -- ns slow slew rate 3)4)5)6)10) Address and control input hold time tIH 0.9 -- 0.9 -- 1.1 -- ns fast slew rate 3)4)5)6)10) 1.0 -- 1.0 -- 1.1 -- ns slow slew rate 3)4)5)6)10) 2)3)4)5) 0.40 0.60 tCK tCK 120E +3 50 120E+ ns 3 2)3)4)5) 65 -- 70 -- ns 2)3)4)5) 75 -- 80 -- ns 2)3)4)5) tRPRE tRPST tRAS 0.9 1.1 0.9 1.1 0.9 1.1 0.40 0.60 0.40 0.60 45 120E 45 +3 Active to Active/Autorefresh command period tRC 65 -- Auto-refresh to Active/Auto-refresh command period tRFC 75 -- Read preamble Read postamble Active to Precharge command Data Sheet 64 2)3)4)5) Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Electrical Characteristics Table 20 AC Timing - Absolute Specifications DDR266A, DDR266 and DDR200 Parameter Symbol -7 -7F -8 DDR266A DDR266 DDR200 Min. Max. Min. Max. Min. Max. Unit Note/ Test Condition 1) Active to Read or Write delay tRCD 20 -- 20 -- 20 -- ns 2)3)4)5) Precharge command period tRP 20 -- 20 -- 20 -- ns 2)3)4)5) Active to Autoprecharge delay tRAP tRCD or tRASmin tRCD or tRASmin tRCD or tRASmin ns 2)3)4)5) Active bank A to Active bank B command tRRD 15 -- 15 -- 15 -- ns 2)3)4)5) Write recovery time tWR tDAL 15 -- 15 -- 15 -- ns 2)3)4)5) tCK 2)3)4)5)11) Internal write to read command delay tWTR 1 -- 1 -- 1 -- tCK 2)3)4)5) Exit self-refresh to nonread command tXSNR 75 -- 75 -- 80 -- ns 2)3)4)5) Exit self-refresh to read command tXSRD 200 -- 200 -- 200 -- tCK 2)3)4)5) Average Periodic Refresh Interval tREFI -- 7.8 -- 7.8 -- 7.8 s 2)3)4)5)12) Auto precharge write recovery + precharge time (tWR/tCK) + (tRP/tCK) 1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V 2) Input slew rate 1 V/ns for DDR266, DDR266A 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VIH(ac) and VIL(ac). 11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. Data Sheet 65 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Electrical Characteristics Table 21 IDD Conditions Parameter Symbol Operating Current: one bank; active/ precharge; tRC = tRCMIN; tCK = tCKMIN; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. IDD0 Operating Current: one bank; active/read/precharge; Burst = 4; Refer to the following page for detailed test conditions. IDD1 Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VILMAX; tCK = IDD2P tCKMIN Precharge Floating Standby Current: CS VIHMIN, all banks idle; IDD2F CKE VIHMIN; tCK = tCKMIN, address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current: CS VIHMIN, all banks idle; CKE VIHMIN; tCK = tCKMIN, address and other control inputs stable at VIHMIN or VILMAX; VIN = VREF for DQ, DQS and DM. IDD2Q Active Power-Down Standby Current: one bank active; power-down mode; CKE VILMAX; tCK = tCKMIN; VIN = VREF for DQ, DQS and DM. IDD3P Active Standby Current: one bank active; CS VIHMIN; CKE VIHMIN; tRC = tRASMAX; tCK = tCKMIN; DQ, IDD3N DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs IDD4R changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A, CL = 3 for DDR333; tCK = tCKMIN; IOUT = 0 mA Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs IDD4W changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A, CL = 3 for DDR333; tCK = tCKMIN Auto-Refresh Current: tRC = tRFCMIN, burst refresh Self-Refresh Current: CKE 0.2 V; external clock on; tCK = tCKMIN Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for detailed test conditions. Data Sheet 66 IDD5 IDD6 IDD7 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Electrical Characteristics Table 22 IDD Specifications Symbol DDR200 -8 IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 DDR266A -7 DDR266 -7F DDR333 -6 DDR400B -5 Unit Note/Test Condition1) 2) typ. max. typ. max. typ. max. typ. max. typ. max. 70 90 75 100 83 110 85 110 70 90 mA x4/x8 3) 72 95 77 105 86 115 88 115 75 90 mA x16 3) 80 100 90 110 98 120 100 120 80 100 mA x4/x8 3) 83 105 94 115 102 125 104 125 95 110 mA x16 3) 5 7 6 8 6 8 6 9 4 5 mA 3) 30 35 35 40 35 40 45 55 30 36 mA 3) 18 22 20 25 20 25 25 28 20 28 mA 3) 13 16 15 18 15 18 18 21 13 18 mA 3) 40 45 50 55 50 55 60 65 38 45 mA 3) 42 50 52 60 52 60 63 70 43 54 mA x16 3) 79 95 95 115 95 115 110 140 85 100 mA x4/x8 3) 89 110 107 130 107 130 124 160 100 120 mA x16 3) 85 105 105 125 105 125 125 145 90 105 mA x4/x8 3) 96 120 119 140 119 140 141 165 100 130 mA x16 3) 126 170 135 180 135 180 144 190 140 190 mA 3) 1.5 2.5 1.5 2.5 1.5 2.5 1.5 2.5 1.4 2.8 mA standard power3)4) 1.20 1.25 1.20 1.25 1.20 1.25 1.20 1.25 -- -- mA low power 150 210 171 225 171 225 208 270 210 250 mA x4/x8 3) 158 220 180 235 180 235 218 285 210 250 mA x16 3) 1) Test conditions for typical values: VDD = 2.5 V (DDR333), VDD = 2.6 V (DDR400), TA = 25 C, test conditions for maximum values: VDD = 2.7 V, TA = 10 C 2) IDD specifications are tested after the device is properly initialized and measured at 100 MHz for DDR200, 133 MHz for DDR266, 166 MHz for DDR333, and 200 MHz for DDR400. 3) Input slew rate = 1 V/ns. 4) Enables on-chip refresh and address counters. Data Sheet 67 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Electrical Characteristics 4.4.1 IDD Current Measurement Conditions IDD1: Operating Current: One Bank Operation 1. Only one bank is accessed with tRC(min) , Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0 mA. 2. Timing patterns a) DDR200 (100MHz, CL=2) : tCK = 10 ns, CL=2, BL=4, tRCD = 2 x tCK, tRAS = 5 x tCK Setup: A0 N R0 N N P0 N Read : A0 N R0 N N P0 N - repeat the same timing with random address changing 50% of data changing at every burst changing at every burst b) DDR266 (133MHz, CL=2) : tCK = 7.5 ns, CL=2, BL=4, tRCD = 3 x tCK, tRC = 9 x tCK, tRAS = 5 x tCK Setup: A0 N N R0 N P0 N N N Read : A0 N N R0 N P0 N NN - repeat the same timing with random address changing 50% of data changing at every burst c) DDR333 (166MHz, CL=2.5) : tCK = 6 ns, CL=2.5, BL=4, tRCD = 3 x tCK, tRC = 9 x tCK, tRAS = 5 x tCK Setup: A0 N N R0 N P0 N N N Read : A0 N N R0 N P0 N N N - repeat the same timing with random address changing 50% of data changing at every burst d) DDR400B (200 MHz, CL = 3): tCK = 5 ns, BL = 4, tRCD = 3 x tCK, tRC = 11 x tCK, tRAS = 8 x tCK Setup:A0 N N R0 N N N N P0 N N Read: A0 N N R0 N N N N P0 N N -repeat the same timing with random address changing 3. Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP IDD7: Operating Current: Four Bank Operation 1. Four banks are being interleaved with tRCMIN. Burst Mode, Address and Control inputs on NOP edge are not changing. IOUT = 0 mA. 2. Timing patterns a) DDR200 (100 MHz, CL = 2): tCK = 10 ns, CL = 2, BL = 4, tRRD = 2 x tCK, tRCD = 3 x tCK, Read with autoprecharge Setup: A0 N A1 R0 A2 R1 A3 R2 Read: A0 R3 A1 R0 A2 R1 A3 R2 - repeat the same timing with random address changing 50% of data changing at every burst b) DDR266A (133 MHz, CL = 2): tCK = 7.5 ns, CL = 2, BL = 4, tRRD = 2 x tCK, tRCD = 3 x tCK Setup: A0 N A1 R0 A2 R1 A3 R2 N R3 Read: A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing 50% of data changing at every burst c) DDR333 (166 MHz, CL = 2.5): tCK = 6 ns, CL = 2.5, BL = 4, tRRD = 2 x tCK, tRCD = 3 x tCK Setup: A0 N A1 R0 A2 R1 A3 R2 N R3 Read: A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing 50% of data changing at every burst d) DDR400B (200 MHz, CL = 3): tCK = 5 ns, BL = 4, tRRD = 2 x tCK, tRCD = 3 *x tCK, tRAS = 8 x tCK Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N - repeat the same timing with random address 3. Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP Data Sheet 68 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Timing Diagrams 5 Timing Diagrams tDQSL tDQSH DQS tDH tDS DI n DQ tDH tDS DM DI n = Data In for column n. 3 subsequent elements of data in are applied in programmed order following DI n. Figure 38 Don't Care Data Input (Write), Timing Burst Length = 4 DQS tDQSQ max tQH DQ tQH (Data output hold time from DQS) tDQSQ and tQH are only shown once and are shown referenced to different edges of DQS, only for clarify of illustration. t.DQSQ and tQH both apply to each of the four relevant edges of DQS. tDQSQ max. is used to determine the worst case setup time for controller data capture. tQH is used to determine the worst case hold time for controller data capture. Figure 39 Data Sheet Data Output (Read), Timing Burst Length = 4 69 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW Figure 40 Data Sheet 70 tVTD High-Z High-Z 200s Power-up: VDD and CK stable LVCMOS LOW LEVEL Don't Care DQ DQS BA0, BA1 A10 A0-A9, A11 DM Command CKE CK CK VREF VTT (System*) VDDQ VDD Initialize and Mode Register Sets tIH tIH NOP tIS tIS tCH tIH PRE tIS tCL tIH tIH tIH BA1=L BA0=H tIS CODE tIS CODE tIS EMRS tMRD Extended Mode Register Set ALL BANKS tCK tIH CODE CODE MRS Load Mode Register, Reset DLL tMRD Load Mode Register (with A8 = L) BA0=L AR tRFC BA1=L AR tRFC 200 cycles of CK** BA0=L ALL BANKS tIS PRE tRP BA1=L CODE CODE MRS tMRD The two Autorefresh commands may be moved to follow the first MRS, but precede the second Precharge All command. ** tMRD is required before any command can be applied and 200 cycles of CK are required before a Read command can be applied. * VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latchup. BA RA RA ACT HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Timing Diagrams Initialize and Mode Register Sets Rev. 1.2, 2004-02 02102004-TSR1-4ZWW Figure 41 Data Sheet 71 tIH tIH tIH VALID tIS VALID* tIS tIS tCK NOP Enter Power Down Mode tIS tCH tCL No column accesses are allowed to be in progress at the time power down is entered. * = If this command is a Precharge (or if the device is already in the idle state) then the power down mode shown is Precharge power down. If this command is an Active (or if at least one row is already active), then the power down mode shown is Active power down. DM DQ DQS ADDR Command CKE CK CK NOP Exit Power Down Mode tIS Don't Care VALID VALID HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Timing Diagrams Power Down Mode Rev. 1.2, 2004-02 02102004-TSR1-4ZWW Figure 42 Data Sheet tIH tIH NOP AR NOP AR NOP VALID tRFC NOP ACT 72 tIH BANK(S) tIS ONE BANK PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address; AR = Autorefresh. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. DM, DQ, and DQS signals are all don't care/high-Z for operations shown. DM DQ DQS BA0, BA1 A10 Don't Care BA RA RA ALL BANKS NOP tRFC A9, A11-A13 PRE VALID tCL RA NOP tIS tIS tCK tRP A0-A8 Command CKE CK CK tCH HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Timing Diagrams Auto Refresh Mode Rev. 1.2, 2004-02 02102004-TSR1-4ZWW Figure 43 Data Sheet 73 DM DQ DQS ADDR Command CKE CK CK NOP tIH tIH tCH tCK tIS AR Enter Self Refresh Mode tCL * = Device must be in the all banks idle state before entering Self Refresh Mode. ** = tXSNR is required before any non-read command can be applied, and tXSRD (200 cycles of CK). are required before a Read command can be applied. tIS tIS tRP* NOP Exit Self Refresh Mode tXSRD, tXSRN tIS 200 cycles tIS tIH Don't Care VALID VALID Clock must be stable before exiting Self Refresh Mode HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Timing Diagrams Self Refresh Mode Rev. 1.2, 2004-02 02102004-TSR1-4ZWW Figure 44 Data Sheet 74 DQ DQS DQ tIH tIH NOP tIS tIS tIH tIH tIH BA x tIS DIS AP tIS COL n tIS Read tLZ (max) tAC (min) BA x* ONE BANK ALL BANKS PRE tCL DO n tAC (max) DO n tLZ (max) tRPRE CL=1.5 tRPRES tLZ (min) tRPRE NOP tCH NOP tIH tHZ (max) tRPST tHZ (min) tDQSCK (max) tDQSCK (min) tRPST NOP tRP BA x RA RA ACT NOP commands are shown for ease of illustration; other commands may be valid at these times. DIS AP = Disable Auto Precharge. * = Don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address. 3 subsequent elements of data out are provided in the programmed order following DO n. DO n = data out from column n. Case 2: tAC/tDQSCK = max Case 1: tAC/tDQSCK = min DQS DM BA0, BA1 A10 A0-A9, A11, A12 Command CKE CK CK tCK NOP VALID NOP VALID Don't Care NOP VALID HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Timing Diagrams Read without Auto Precharge (Burst Length = 4) Rev. 1.2, 2004-02 09222003-A8PO-81BB Figure 45 Data Sheet 75 Case 2: tAC/tDQSCK = max Case 1: tAC/tDQSCK = min tIH tIH NOP tIS tIS tIH tIH tIH BA x tIS DIS AP tIS COL n tIS Read CL=2 PRE tLZ (max) tLZ (max) tRPRE DO n tAC (max) DO n tAC (min) BA x* ONE BANK ALL BANKS tCL tLZ (min) tRPRE NOP tCH NOP tDQSCK (max) NOP commands are shown for ease of illustration; other commands may be valid at these times. DIS AP = Disable Auto Precharge. * = Don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address. BA x RA RA ACT tHZ (max) tRPST tHZ (min) tIH NOP tDQSCK (min) tRPST tRP 3 subsequent elements of data out are provided in the programmed order following DO n. DO n = data out from column n. DQ DQS DQ DQS DM BA0, BA1 A10 A0-A9, A11, A12 Command CKE CK CK tCK Read Without Auto Precharge (CAS Latency = 2, Burst Length = 4) NOP VALID NOP VALID Don't Care NOP VALID HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Timing Diagrams Read with Auto Precharge (Burst Length = 4) Rev. 1.2, 2004-02 09222003-A8PO-81BB Figure 46 Data Sheet 76 Case 2: tAC/tDQSCK = max Case 1: tAC/tDQSCK = min DQ DQS DQ DQS DM BA0, BA1 A10 A0-A9, A11, A12 Command CKE CK CK tIH tIH tIH tIH tIH BA x tIS EN AP tIS COL n tIS Read tLZ (max) tRPRE tLZ (max) CL=2 tLZ (min) DO n tAC (max) DO n tAC (min) NOP tCL tLZ (min) tRPRE NOP tCH NOP BA x RA RA ACT tDQSCK (max) tHZ (max) tRPST tHZ (min) tIH NOP tDQSCK (min) tRPST tRP NOP VALID DO n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following DO n. EN AP = enable Auto Precharge. ACT = active; RA = row address. NOP commands are shown for ease of illustration; other commands may be valid at these times. NOP tIS tIS tCK Read Without Auto Precharge (CAS Latency = 2, Burst Length = 4) NOP VALID Don't Care NOP VALID HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Timing Diagrams Bank Read Access (Burst Length = 4) Rev. 1.2, 2004-02 09222003-A8PO-81BB Figure 47 Data Sheet tIH tIH 77 DQ DQS DQ BA x tIH tCK tRCD NOP tCH tIH tRAS BA x DIS AP tIS COL n Read tCL tRC CL=2 tLZ (max) DO n tAC (max) DO n tAC (min) BA x* ONE BANK tLZ (max) tRPRE tLZ (min) PRE ALL BANKS tLZ (min) tRPRE NOP DO n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following DO n. DIS AP = disable Auto Precharge. * = Don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address. NOP commands are shown for ease of illustration; other commands may be valid at these times. Case 2: tAC/tDQSCK = max Case 1: tAC/tDQSCK = min DQS DM BA0, BA1 tIS RA tIH A10 tIS ACT RA NOP tIS tIS A0-A9, A11, A12 Command CKE CK CK Read Without Auto Precharge (CAS Latency = 2, Burst Length = 4) NOP BA x RA RA ACT tHZ (max) tHZ (min) tRPST tDQSCK (max) tDQSCK (min) tRPST tRP NOP Don't Care NOP VALID HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Timing Diagrams Write without Auto Precharge (Burst Length = 4) Rev. 1.2, 2004-02 09222003-A8PO-81BB Figure 48 Data Sheet 78 DM DQ DQS BA0, BA1 A10 A0-A9, A11, A12 Command CKE CK CK tIH tIH tIH tIH tIH tWPRES BA x tIS tDQSS DIS AP tIS COL n tIS Write DIn tDQSH tWPRE NOP tCH tDQSL tCL NOP tWPST tDSH NOP tIH NOP tWR PRE BA x* ONE BANK ALL BANKS tDQSS = min. DIn = Data in for column n. 3 subsequent elements of data in are applied in the programmed order following DIn. DIS AP = Disable Auto Precharge. * = Don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. NOP tIS tIS tCK Write without Auto Precharge (Burst Length = 4) NOP VALID tRP NOP Don't Care BA RA RA ACT HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Timing Diagrams Write with Auto Precharge (Burst Length = 4) Rev. 1.2, 2004-02 09222003-A8PO-81BB Figure 49 Data Sheet 79 DM DQ DQS BA0, BA1 A10 A0-A9, A11, A12 Command CKE CK CK tIH tIH tIH tIH BA x tIS RA RA tIS ACT tRCD NOP tCH tIH tWPRES BA x tDQSS DIS AP tIS Col n Write tCL DIn tDSH tDQSL tWPRE tDQSH NOP tRAS NOP tWPST NOP tDQSS = min. DI n = data in for column n. 3 subsequent elements of data in are applied in the programmed order following DI n. DIS AP = Disable Auto Precharge. * = don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. NOP tIS tIS tCK tWR NOP BA x ONE BANK ALL BANKS PRE Don't Care NOP VALID HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Timing Diagrams Bank Write Access (Burst Length = 4) Rev. 1.2, 2004-02 09222003-A8PO-81BB Figure 50 Data Sheet 80 DM DQ DQS BA0, BA1 A10 A0-A9, A11, A12 Command CKE CK CK tIH tIH tIH tIH tIH tWPRES BA x tIS tDQSS DIS AP tIS COL n tIS Write DIn tDQSH NOP tCH tDQSL tCL NOP tWPST tDSH tDSS NOP tWR NOP BA x* ONE BANK ALL BANKS PRE NOP VALID DI n = data in for column n. 3 subsequent elements of data in are applied in the programmed order following DI n (the second element of the 4 is masked). DIS AP = Disable Auto Precharge. * = Don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. tDQSS = min. NOP tIS tIS tCK tRP NOP Don't Care BA RA RA ACT HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Timing Diagrams Write DM Operation (Burst Length = 4) Rev. 1.2, 2004-02 09222003-A8PO-81BB HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM Package Outlines 6 Package Outlines 11 x 1 = 11 0.18 MAX. B 3) 4) A 5) 5) 8 x 0.8 = 6.4 1.8 MAX. 0.8 1 0.05 2) 1) 0.1 C 1.2 MAX. 0.25 MIN. 0.1 C o0.4 0.05 60x o0.15 o0.08 M M C C SEATING PLANE A B 1.5 2) 4.25 8 2.24 0.2 12 1) A1 Marking Ballside 2) A1 Marking Chipside 3) Dummy Pads without Ball 4) Bad Unit Marking (BUM) 5) Middle of Packages Edges Figure 51 Data Sheet P-TFBGA-60-2 (Plastic Thin Fine-Pitch Ball Grid Array Package) 81 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM 0.25 0.65 15 5 32 x 0.65 = 20.8 0.1 66x 0.12 0.3 0.08 3) 34 1 2.5 MAX. 33 11.76 0.2 66x 6 MAX. 66 M 0.5 0.1 0.15 +0.06 -0.03 10.16 0.13 2) 1 0.05 15 5 0.1 0.05 Package Outlines 22.22 0.13 1) Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include plastic protrusion of 0.25 max. per side 3) Does not include dambar protrusion of 0.13 max. Figure 52 Data Sheet P-TSOPII-66-1 (Plastic Thin Small Outline Package Type II) 82 Rev. 1.2, 2004-02 02102004-TSR1-4ZWW http://www.infineon.com Published by Infineon Technologies AG