1Gb: x4, x8, x16 DDR3 SDRAM Features DDR3 SDRAM MT41J256M4 - 32 Meg x 4 x 8 banks MT41J128M8 - 16 Meg x 8 x 8 banks MT41J64M16 - 8 Meg x 16 x 8 banks Features * * * * * * * * * * * * * * * * * * * * Options1 VDD = VDDQ = +1.5V 0.075V 1.5V center-terminated push/pull I/O Differential bidirectional data strobe 8n-bit prefetch architecture Differential clock inputs (CK, CK#) 8 internal banks Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals CAS (READ) latency (CL): 5, 6, 7, 8, 9, 10, or 11 POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2 CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on tCK Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) Selectable BC4 or BL8 on-the-fly (OTF) Self refresh mode TC of 0C to 95C - 64ms, 8,192 cycle refresh at 0C to 85C - 32ms at 85C to 95C Clock frequency range of 300-800 MHz Self refresh temperature (SRT) Automatic self refresh (ASR) Write leveling Multipurpose register Output driver calibration Marking * Configuration - 256 Meg x 4 - 128 Meg x 8 - 64 Meg x 16 * FBGA package (Pb-free) - x4, x8 - 78-ball (8mm x 11.5mm) Rev. E, F - 78-ball (9mm x 11.5mm) Rev. D - 86-ball (9mm x 15.5mm) Rev. B * FBGA package (Pb-free) - x16 - 96-ball (8mm x 14mm) Rev. E - 96-ball (9mm x 15.5mm) Rev. B * Timing - cycle time - 1.25ns @ CL = 11 (DDR3-1600) - 1.25ns @ CL = 10 (DDR3-1600) - 1.5ns @ CL = 10 (DDR3-1333) - 1.5ns @ CL = 9 (DDR3-1333) - 1.87ns @ CL = 8 (DDR3-1066) - 1.87ns @ CL = 7 (DDR3-1066) * Operating temperature - Commercial (0C TC 95C) - Industrial (-40C TC 95C; - Automotive (-40C TC 105C; * Revision 256M4 128M8 64M16 JP HX BY JT LA -125 -125E -15 -15E -187 -187E None IT AT :B/:D/:E/:F Notes: 1. Not all options listed can be combined to define an offered product. Use the Part Catalog Search on www.micron.com for available offerings. Table 1: Key Timing Parameters Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL -125 1600 11-11-11 13.75 13.75 13.75 -125E 1600 10-10-10 12.5 12.5 12.5 -15 1333 10-10-10 15 15 15 -15E 1333 9-9-9 13.5 13.5 13.5 -187 1066 8-8-8 15 15 15 -187E 1066 7-7-7 13.1 13.1 13.1 PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D1.fm - Rev G 2/09 EN 1 tRCD (ns) tRP (ns) CL (ns) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 1Gb: x4, x8, x16 DDR3 SDRAM Features Table 2: Addressing Parameter Configuration 256 Meg x 4 128 Meg x 8 64 Meg x 16 32 Meg x 4 x 8 banks 16 Meg x 8 x 8 banks 8 Meg x 16 x 8 banks Refresh count 8K 8K 8K Row addressing 16K (A[13:0]) 16K (A[13:0]) 8K (A[12:0]) Bank addressing 8 (BA[2:0]) 8 (BA[2:0]) 8 (BA[2:0]) 2K (A[11, 9:0]) 1K (A[9:0]) 1K (A[9:0]) Column addressing Figure 1: 1Gb DDR3 Part Numbers Example Part Number: M T 4 1 J 2 5 6 M 4 B Y- 1 5 : B Package Configuration Speed Revision { MT41J : :B/:D/:E/:F Temperature Configuration 256 Meg x 4 256M4 128 Meg x 8 128M8 64 Meg x 16 Notes: Revision Commercial 64M16 IT Automotive temperature AT Mark -125 Speed Grade tCK = 1.25ns, CL = 11 E, F JP -125E tCK = 1.25ns, CL = 10 D HX -15 tCK = 1.5ns, CL = 10 86-ball 9mm x 15.5mm FBGA B BY -15E tCK = 1.5ns, CL = 9 96-ball 8mm x 14mm FBGA E JP -187 tCK = 1.87ns, CL = 8 96-ball 9mm x 15.5mm FBGA B LA -187E tCK = 1.87ns, CL = 7 Package Rev. 78-ball 8mm x 11.5mm FBGA 78-ball 9mm x 11.5mm FBGA None Industrial temperature 1. Not all options listed can be combined to define an offered product. Use the Part Catalog Search on www.micron.com for available offerings. FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron's Web site: www.micron.com. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D1.fm - Rev G 2/09 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Industrial Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Automotive Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Input/Output Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Electrical Specifications - IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Electrical Characteristics - IDD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Electrical Specifications - DC and AC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Input Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 AC Overshoot/Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Slew Rate Definitions for Single-Ended Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Slew Rate Definitions for Differential Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 ODT Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 ODT Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 ODT Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 ODT Timing Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Output Driver Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 34 Ohm Output Driver Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 34 Ohm Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 34 Ohm Driver Output Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Alternative 40 Ohm Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 40 Ohm Driver Output Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Output Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Reference Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Slew Rate Definitions for Single-Ended Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Slew Rate Definitions for Differential Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Speed Bin Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Command and Address Setup, Hold, and Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Data Setup, Hold, and Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 DESELECT (DES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 ZQ CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 ACTIVATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 DLL Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_TOC.fm - Rev G 2/09 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Table of Contents Input Clock Frequency Change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register 0 (MR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register 1 (MR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register 2 (MR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register 3 (MR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE REGISTER SET (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZQ CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACTIVATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Temperature Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Die Termination (ODT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Representation of ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nominal ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous ODT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT Off During READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous ODT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry). . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_TOC.fm - Rev G 2/09 EN 4 101 103 108 108 110 111 115 118 121 128 128 129 131 141 150 150 152 153 159 161 161 161 163 168 171 173 175 177 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Figure 55: Figure 56: 1Gb DDR3 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 256 Meg x 4 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 128 Meg x 8 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 64 Meg x 16 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 78-Ball FBGA - x4, x8 Ball Assignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 86-Ball FBGA - x4, x8 Ball Assignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 96-Ball FBGA - x16 Ball Assignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 78-Ball FBGA - x4, x8; "JP" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 78-Ball FBGA - x4, x8; "HX" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 86-Ball FBGA - x4, x8; "BY" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 96-Ball FBGA - x16; "JT" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 96-Ball FBGA - x16; "LA" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Thermal Measurement Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Vix for Differential Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Single-Ended Requirements for Differential Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Definition of Differential AC-Swing and tDVAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Nominal Slew Rate Definition for Single-Ended Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# . . . . . . . . . . . . . . . . . .51 ODT Levels and I-V Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 ODT Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 t AON and tAOF Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 t AONPD and tAOFPD Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 tADC Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 DQ Output Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Differential Output Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Reference Output Load for AC Timing and Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Nominal Slew Rate Definition for Single-Ended Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Nominal Differential Output Slew Rate Definition for DQS, DQS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Nominal Slew Rate and tVAC for tIS (Command and Address - Clock) . . . . . . . . . . . . . . . . . . . . . . . . .82 Nominal Slew Rate for tIH (Command and Address - Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Tangent Line for tIS (Command and Address - Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Tangent Line for tIH (Command and Address - Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Nominal Slew Rate and tVAC for tDS (DQ - Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Nominal Slew Rate for tDH (DQ - Strobe). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Tangent Line for tDS (DQ - Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Tangent Line for tDH (DQ - Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Refresh Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 DLL Enable Mode to DLL Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 DLL Disable Mode to DLL Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 DLL Disable tDQSCK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Change Frequency During Precharge Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Write Leveling Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Write Leveling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Exit Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 MRS-to-MRS Command Timing (tMRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 MRS-to-nonMRS Command Timing (tMOD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Mode Register 0 (MR0) Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 READ Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Mode Register 1 (MR1) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 READ Latency (AL = 5, CL = 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_LOF.fm - Rev G 2/09 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM List of Figures Figure 57: Figure 58: Figure 59: Figure 60: Figure 61: Figure 62: Figure 63: Figure 64: Figure 65: Figure 66: Figure 67: Figure 68: Figure 69: Figure 70: Figure 71: Figure 72: Figure 73: Figure 74: Figure 75: Figure 76: Figure 77: Figure 78: Figure 79: Figure 80: Figure 81: Figure 82: Figure 83: Figure 84: Figure 85: Figure 86: Figure 87: Figure 88: Figure 89: Figure 90: Figure 91: Figure 92: Figure 93: Figure 94: Figure 95: Figure 96: Figure 97: Figure 98: Figure 99: Figure 100: Figure 101: Figure 102: Figure 103: Figure 104: Figure 105: Figure 106: Figure 107: Figure 108: Figure 109: Figure 110: Figure 111: Figure 112: Mode Register 2 (MR2) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAS Write Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register 3 (MR3) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multipurpose Register (MPR) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPR System Read Calibration with BL8: Fixed Burst Order Single Readout. . . . . . . . . . . . . . . . . . . MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout . . . . . . . . . . . MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble. . . . . . . . . . . . . . . . . . MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble. . . . . . . . . . . . . . . . . . ZQ Calibration Timing (ZQCL and ZQCS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example: Meeting tRRD (MIN) and tRCD (MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example: tFAW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Consecutive READ Bursts (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Consecutive READ Bursts (BC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ (BL8) to WRITE (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ (BC4) to WRITE (BC4) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ to PRECHARGE (BL8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ to PRECHARGE (BC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ to PRECHARGE (AL = 5, CL = 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ with Auto Precharge (AL = 4, CL = 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Output Timing - tDQSQ and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Strobe Timing - READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Method for Calculating tLZ and tHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t RPRE Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tRPST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t WPRE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t WPST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Consecutive WRITE (BL8) to WRITE (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Consecutive WRITE (BC4) to WRITE (BC4) via MRS or OTF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nonconsecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE (BL8) to READ (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE to READ (BC4 Mode Register Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE (BC4 OTF) to READ (BC4 OTF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE (BL8) to PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE (BC4 Mode Register Setting) to PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE (BC4 OTF) to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Refresh Entry/Exit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Power-Down Entry and Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precharge Power-Down (Fast-Exit Mode) Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precharge Power-Down (Slow-Exit Mode) Entry and Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Down Entry After READ or READ with Auto Precharge (RDAP) . . . . . . . . . . . . . . . . . . . . . . . Power-Down Entry After WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Down Entry After WRITE with Auto Precharge (WRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REFRESH to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACTIVATE to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PRECHARGE to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MRS Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Down Exit to Refresh to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic ODT: Without WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 . . . . PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_LOF.fm - Rev G 2/09 EN 6 118 119 121 122 124 125 126 127 129 130 130 131 133 133 134 134 135 135 136 136 136 138 139 139 140 140 142 142 143 144 144 145 145 146 147 148 148 149 149 151 154 155 155 156 156 157 157 158 158 159 159 160 161 165 165 166 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM List of Figures Figure 113: Figure 114: Figure 115: Figure 116: Figure 117: Figure 118: Figure 119: Figure 120: Figure 121: Figure 122: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4. . . . . . . . . . . . . Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4. . . . . . . . . . . . . Synchronous ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous ODT (BC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT During READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous ODT Timing with Fast ODT Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry . . . . Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit. . . . . . Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping . . . . . . . . . Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping. . . . . . . . . PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_LOF.fm - Rev G 2/09 EN 7 167 167 169 170 172 174 176 178 180 180 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Table 34: Table 35: Table 36: Table 37: Table 38: Table 39: Table 40: Table 41: Table 42: Table 43: Table 44: Table 45: Table 46: Table 47: Table 48: Table 49: Table 50: Table 51: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 78-Ball FBGA - x4, x8 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 86-Ball FBGA - x4, x8 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 96-Ball FBGA - x16 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Input/Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Timing Parameters used for IDD Measurements - Clock Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 IDD0 Measurement Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 IDD1 Measurement Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 IDD Measurement Conditions for Power-Down Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 IDD2N and IDD3N Measurement Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 IDD2NT Measurement Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 IDD4R Measurement Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 IDD4W Measurement Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 IDD5B Measurement Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 IDD7 Measurement Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 IDD Maximum Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 DC Electrical Characteristics and Input Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Input Switching Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Control and Address Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Clock, Data, Strobe, and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Differential Input Operating Conditions (CK, CK# and DQS, DQS#) . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Allowed Time Before Ringback (tDVAC) for CK - CK# and DQS - DQS#. . . . . . . . . . . . . . . . . . . . . . . . .48 Single-Ended Input Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Differential Input Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 On-Die Termination DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 RTT Effective Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 ODT Sensitivity Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 ODT Temperature and Voltage Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 ODT Timing Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Reference Settings for ODT Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 34 Driver Impedance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 34 Driver Pull-Up and Pull-Down Impedance Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 34 Driver IOH/IOL Characteristics: VDD = VDDQ = 1.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 34 Driver IOH/IOL Characteristics: VDD = VDDQ = 1.575V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 34 Driver IOH/IOL Characteristics: VDD = VDDQ = 1.425V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 34 Output Driver Sensitivity Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 34 Output Driver Voltage and Temperature Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 40 Driver Impedance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 40 Output Driver Sensitivity Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 40 Output Driver Voltage and Temperature Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Single-Ended Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Differential Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Single-Ended Output Slew Rate Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Differential Output Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 DDR3-800 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 DDR3-1066 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_LOT.fm - Rev G 2/09 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM List of Tables Table 52: Table 53: Table 55: Table 56: Table 57: Table 58: Table 59: Table 60: Table 61: Table 62: Table 63: Table 64: Table 65: Table 66: Table 67: Table 68: Table 69: Table 70: Table 71: Table 72: Table 73: Table 74: Table 75: Table 76: Table 77: Table 78: Table 79: Table 80: Table 81: Table 82: Table 84: DDR3-1333 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 DDR3-1600 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Command and Address Setup and Hold Values Referenced at 1 V/ns - AC/DC-Based . . . . . . . . . . .79 Derating Values for tIS/tIH - AC175/DC100-Based. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Derating Values for tIS/tIH - AC150/DC100-Based. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Minimum Required Time tVAC Above VIH(AC) for Valid Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) - AC/DC-Based . . . . . . . . . . . . . . . . . .86 Derating Values for tDS/tDH - AC175/DC100-Based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Derating Values for tDS/tDH - AC150/DC100-Based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Required Time tVAC Above VIH(AC) (Below VIL[AC]) for Valid Transition. . . . . . . . . . . . . . . . . . . . . . . .88 Truth Table - Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Truth Table - CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 READ Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 WRITE Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 READ Electrical Characteristics, DLL Disable Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Write Leveling Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Burst Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 MPR Functional Description of MR3 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 MPR Readouts and Burst Order Bit Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Self Refresh Temperature and Auto Self Refresh Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Self Refresh Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Command to Power-Down Entry Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Power-Down Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Truth Table - ODT (Nominal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 ODT Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Dynamic ODT Specific Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Mode Registers for Rtt_nom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Mode Registers for Rtt_wr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Timing Diagrams for Dynamic ODT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Synchronous ODT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period . . . . . . . . . . . . . . . . 176 PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_LOT.fm - Rev G 2/09 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM State Diagram State Diagram Figure 2: Simplified State Diagram CKE L Power applied Power on Reset procedure MRS, MPR, write leveling Initialization Self refresh SRE ZQCL From any state RESET ZQ calibration MRS SRX REF ZQCL/ZQCS Idle Refreshing PDE ACT PDX Active powerdown Precharge powerdown Activating PDX CKE L CKE L PDE Bank active WRITE WRITE READ WRITE AP READ AP READ Writing READ WRITE Reading READ AP WRITE AP WRITE AP READ AP PRE, PREA Writing PRE, PREA PRE, PREA Precharging Reading Automatic sequence Command sequence ACT = ACTIVATE MPR = Multipurpose register MRS = Mode register set PDE = Power-down entry PDX = Power-down exit PRE = PRECHARGE PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN PREA = PRECHARGE ALL READ = RD, RDS4, RDS8 READ AP = RDAP, RDAPS4, RDAPS8 REF = REFRESH RESET = START RESET PROCEDURE SRE = Self refresh entry 10 SRX = Self refresh exit WRITE = WR, WRS4, WRS8 WRITE AP = WRAP, WRAPS4, WRAPS8 ZQCL = ZQ LONG CALIBRATION ZQCS = ZQ SHORT CALIBRATION Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Functional Description Functional Description The DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clockcycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. DDR3 SDRAM use READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode. Industrial Temperature The industrial temperature (IT) device requires the case temperature not exceed -40C or +95C. JEDEC specifications require the refresh rate to double when TC exceeds +85C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance and the input/output impedance must be derated when the TC is < 0C or > +95C. Automotive Temperature The automotive temperature (AT) device requires the case temperature not exceed -40C or +105C. JEDEC specifications require the refresh rate to double when TC exceeds +85C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance and the input/output impedance must be derated when the TC is < 0C or > +95C. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Functional Description General Notes * The functionality and the timing specifications discussed in this data sheet are for the DLL enable mode of operation (normal operation). * Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. * The terms "DQS" and "CK" found throughout the data sheet are to be interpreted as DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise. * Complete functionality may be described throughout the entire document, and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. * Any specific requirement takes precedence over a general statement. * Any functionality not specifically stated herewithin is considered undefined, illegal, and not supported and can result in unknown operation. * Row addressing is denoted as A[n:0](1Gb: n = 12 [x16]; 1Gb: n = 13 [x4, x8]). PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Functional Block Diagrams Functional Block Diagrams DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally configured as an 8-bank DRAM. Figure 3: 256 Meg x 4 Functional Block Diagram ODT control ODT ZQ RZQ ZQCL, ZQCS CKE VSSQ To pull-up/pull-down networks ZQ CAL RESET# Control logic A12 VDDQ/2 CK, CK# BC4 (burst chop) Command decode CS# RAS# CAS# WE# Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 OTF Mode registers Refresh counter 17 Columns 0, 1, and 2 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 14 14 Bank 0 rowaddress latch and decoder 16,384 RTT_WR CK, CK# sw2 sw1 DLL (1 . . . 4) 13 Rowaddress MUX RTT_NOM Bank 0 memory array (16,384 x 256 x 32) 32 READ FIFO and data MUX 4 DQ[3:0] READ drivers DQ[3:0] DQS, DQS# VDDQ/2 Sense amplifiers 32 BC4 RTT_NOM 8,192 BC4 OTF I/O gating DM mask logic 3 A[13:0] BA[2:0] 17 Address register 3 sw1 (1, 2) Columnaddress counter/ latch DQS, DQS# VDDQ/2 32 Data interface Column decoder 4 Data WRITE drivers and input logic 8 RTT_NOM sw1 RTT_WR sw2 DM 3 Columns 0, 1, and 2 CK, CK# PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN sw2 DM Bank control logic 256 (x32) 11 RTT_WR 13 Column 2 (select upper or lower nibble for BC4) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Functional Block Diagrams Figure 4: 128 Meg x 8 Functional Block Diagram ODT control ODT ZQ Control logic CKE VSSQ To ODT/output drivers ZQ CAL RESET# RZQ ZQCL, ZQCS A12 CK, CK# VDDQ/2 BC4 (burst chop) Command decode CS# RAS# CAS# WE# Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 OTF Mode registers Refresh counter Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 17 14 14 sw2 sw1 DLL (1 . . . 8) Bank 0 memory array (16,384 x 128 x 64) Bank 0 rowaddress 16,384 latch and decoder RTT_WR CK, CK# 13 Rowaddress MUX RTT_NOM Columns 0, 1, and 2 64 DQ8 READ FIFO and data MUX 8 TDQS# DQ[7:0] READ drivers DQ[7:0] DQS, DQS# VDDQ/2 Sense amplifiers 64 BC4 8,192 17 Address register (1, 2) Bank control logic 3 64 8 Data interface Data Column decoder Columnaddress counter/ latch 10 RTT_NOM RTT_WR sw2 sw1 DM/TDQS (shared pin) 3 Columns 0, 1, and 2 Column 2 (select upper or lower nibble for BC4) 64 Meg x 16 Functional Block Diagram ODT control ODT ZQ ZQ CAL RESET# Control logic CKE VSSQ WRITE drivers and input logic 7 CK, CK# RZQ DQS, DQS# VDDQ/2 (128 x64) Figure 5: RTT_WR sw2 sw1 I/O gating DM mask logic 3 A[13:0] BA[2:0] BC4 OTF RTT_NOM To ODT/output drivers ZQCL, ZQCS A12 VDDQ/2 CK, CK# BC4 (burst chop) Command decode CS# RAS# CAS# WE# Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 OTF Mode registers Refresh counter 16 13 13 Bank 0 rowaddress latch and decoder 8,192 RTT_WR CK, CK# sw2 sw1 DLL (1 . . . 16) 13 Rowaddress MUX RTT_NOM Column 0, 1, and 2 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0 memory array (8,192 x 128 x 128) 128 READ FIFO and data MUX 16 DQ[15:0] READ drivers LDQS, LDQS#, UDQS, UDQS# DQ[15:0] VDDQ/2 Sense amplifiers BC4 128 16,384 Address register 3 LDQS, LDQS# I/O gating DM mask logic 3 16 Bank control logic (1 . . . 4) 128 Data interface Column decoder Columnaddress counter/ latch 16 Data WRITE drivers and input logic RTT_NOM sw1 RTT_WR sw2 7 (1, 2) LDM/UDM 3 Columns 0, 1, and 2 CK, CK# PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN UDQS, UDQS# VDDQ/2 (128 x128) 10 RTT_WR sw2 sw1 BC4 OTF A[12:0] BA[2:0] RTT_NOM 14 Column 2 (select upper or lower nibble for BC4) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 6: 78-Ball FBGA - x4, x8 Ball Assignments (Top View) 1 2 3 VSS VDD VSS VDDQ 4 5 6 7 8 9 NC NF, NF/TDQS# VSS VDD VSSQ DQ0 DM, DM/TDQS VSSQ VDDQ DQ2 DQS DQ1 DQ3 VSSQ NF, DQ6 DQS# VDD VSS VSSQ A B C D VSSQ E VREFDQ NF, DQ7 NF, DQ5 VDDQ VDDQ NF, DQ4 F NC VSS RAS# CK VSS NC ODT VDD CAS# CK# VDD CKE NC CS# WE# A10/AP ZQ NC VSS BA0 BA2 NC VREFCA VSS VDD A3 A0 A12/BC# BA1 VDD VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS RESET# A13 NC A8 VSS G H J K L M N Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 1. Ball descriptions listed in Table 3 on page 18 are listed as "x4, x8" if unique; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only--selectable between NF or TDQS# via MRS (symbols are defined in Table 3 on page 18). 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Figure 7: 86-Ball FBGA - x4, x8 Ball Assignments (Top View) 1 2 3 4 5 6 7 8 9 A NC NC NC NC B C D VSS VDD NC NF, NF/TDQS# VSS VDD VSS VSSQ DQ0 DM, DM/TDQS VSSQ VDDQ VDDQ DQ2 DQS DQ1 DQ3 VSSQ NF, DQ6 DQS# VDD VSS VSSQ E F G VSSQ H VREFDQ NF, DQ7 NF, DQ5 VDDQ NF, DQ4 VDDQ J NC VSS RAS# CK VSS NC ODT VDD CAS# CK# VDD CKE NC CS# WE# A10/AP ZQ NC VSS BA0 BA2 NC VREFCA VSS VDD A3 A0 A12/BC# BA1 VDD VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS RESET# A13 NC A8 VSS NC NC K L M N P R T U V W NC Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN NC 1. Ball descriptions listed in Table 4 on page 20 are listed as "x4, x8" if unique; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only--selectable between NF or TDQS# via MRS (symbols are defined in Table 4 on page 20). 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Figure 8: 96-Ball FBGA - x16 Ball Assignments (Top View) 1 2 3 VDDQ DQ13 VSSQ 4 5 6 7 8 9 DQ15 DQ12 VDDQ VSS VDD VSS UDQS# DQ14 VSSQ VDDQ DQ11 DQ9 UDQS DQ10 VDDQ VSSQ VDDQ UDM DQ8 VSSQ VDD VSS VSSQ DQ0 LDM VSSQ VDDQ VDDQ DQ2 LDQS DQ1 DQ3 VSSQ VSSQ DQ6 LDQS# VDD VSS VSSQ VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ NC VSS RAS# CK VSS NC ODT VDD CAS# CK# VDD CKE NC CS# WE# A10/AP ZQ NC VSS BA0 BA2 NC VREFCA VSS VDD A3 A0 A12/BC# BA1 VDD VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS RESET# NC NC A8 VSS A B C D E F G H J K L M N P R T Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 1. Ball descriptions listed in Table 5 on page 22 are listed as "x4, x8" if unique; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only--selectable between NF or TDQS# via MRS (symbols are defined in Table 5 on page 22). 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Table 3: 78-Ball FBGA - x4, x8 Ball Descriptions Ball Assignments Symbol Type Description K3, L7, L3, K2, L8, L2, M8, M2, N8, M3, H7, M7, K7, N3 A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10/AP, A11, A12/BC#, A13 Input J2, K8, J3 BA0, BA1, BA2 Input F7, G7 CK, CK# Input G9 CKE Input H2 CS# Input B7 DM Input G1 ODT Input F3, G3, H3 RAS#, CAS#, WE# Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop). See Table 63 on page 93. Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on the x8. On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA. Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Table 3: 78-Ball FBGA - x4, x8 Ball Descriptions (continued) Ball Assignments Symbol Type Description N2 RESET# Input B3, C7, C2, C8 B3, C7, C2, C8, E3, E8, D2, E7 C3, D3 DQ0, DQ1, DQ2, DQ3 DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7 DQS, DQS# I/O Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 0.8 x VDD and DC LOW 0.2 x VDDQ. RESET# assertion and desertion are asynchronous. Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are referenced to VREFDQ. Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are referenced to VREFDQ. I/O B7, A7 TDQS, TDQS# Output A2, A9, D7, G2, G8, K1, K9, M1, M9 B9, C1, E2, E9 VDD Supply VDDQ Supply J8 VREFCA Supply E1 VREFDQ Supply A1, A8, B1, D8, F2, F8, J1, J9, L1, L9, N1, N9 B2, B8, C9, D1, D9 H8 VSS Supply A3, J7, N7, F9, H1, F1, H9 A7, D2, E3, E7, E8 PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN VSSQ ZQ NC NF I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resistance. Power supply: 1.5V 0.075V. DQ power supply: 1.5V 0.075V. Isolated on the device for improved noise immunity. Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. Reference voltage for data: VREFDQ must be maintained at all times (excluding self refresh) for proper device operation. Ground. Supply DQ ground: Isolated on the device for improved noise immunity. Reference External reference ball for output drive calibration: This ball is tied to an external 240 resistor (RZQ), which is tied to VSSQ. - No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). - No function: When configured as a x4 device, these balls are NF. When configured as a x8 device, these balls are defined as TDQS#, DQ[7:4]. 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Table 4: 86-Ball FBGA - x4, x8 Ball Descriptions Ball Assignments Symbol Type Description N3, P7, P3, N2, P8, P2, R8, R2, T8, R3, L7, R7, N7, T3 A0, A1, A2, A3, A4, A5, A6, A7, A8, A9 A10/AP, A11, A12/BC#, A13 Input M2, N8, M3 BA0, BA1, BA2 Input J7, K7 CK, CK# Input K9 CKE Input L2 CS# Input E7 DM Input K1 ODT Input J3, K3, L3 RAS#, CAS#, WE# Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop). See Table 63 on page 93. Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on the x8. On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA. Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Table 4: 86-Ball FBGA - x4, x8 Ball Descriptions (continued) Ball Assignments Symbol Type Description T2 RESET# Input E3, F7, F2, F8 E3, F7, F2, F8, H3, H8, G2, H7 F3, G3 DQ0, DQ1, DQ2, DQ3 DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7 DQS, DQS# I/O Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 0.8 x VDD and DC LOW 0.2 x VDDQ. RESET# assertion and desertion are asynchronous. Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are referenced to VREFDQ. Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are referenced to VREFDQ. I/O E7, D7 TDQS, TDQS# Output D2, D9, G7, K2, K8, N1, N9, R1, R9 E9, F1, H2, H9 VDD Supply VDDQ Supply M8 VREFCA Supply H1 VREFDQ Supply D1, D8, E1, G8, J2, J8, M1, M9, P1, P9, T1, T9 E2, E8, F9, G1, G9 L8 VSS Supply A1, A3, A7, A9, D3, J1, J9, L1, L9, M7, T7, W1, W3, W7, W9 D7, G2, H3, H7, H8 PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN VSSQ ZQ NC NF I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resistance. Power supply: 1.5V 0.075V. DQ power supply: 1.5V 0.075V. Isolated on the device for improved noise immunity. Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. Reference voltage for data: VREFDQ must be maintained at all times (excluding self refresh) for proper device operation. Ground. Supply DQ ground: Isolated on the device for improved noise immunity. Reference External reference ball for output drive calibration: This ball is tied to an external 240 resistor (RZQ), which is tied to VSSQ. - No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). - No function: When configured as a x4 device, these balls are NF. When configured as a x8 device, these balls are defined as TDQS#, DQ[7:4]. 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Table 5: 96-Ball FBGA - x16 Ball Descriptions Ball Assignments Symbol Type Description N3, P7, P3, N2, P8, P2, R8, R2, T8, R3, L7, R7, N7 A0, A1, A2, A3, A4, A5, A6, A7, A8, A9 A10/AP, A11, A12/BC# Input M2, N8, M3 BA0, BA1, BA2 Input J7, K7 CK, CK# Input K9 CKE Input L2 CS# Input E7 LDM Input K1 ODT Input J3, K3, L3 RAS#, CAS#, WE# Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop). See Table 63 on page 93. Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle),or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte input data is masked when LDM is sampled HIGH along with the input data during a write access. Although the LDM ball is input-only, the LDM loading is designed to match that of the DQ and DQS balls. LDM is referenced to VREFDQ. On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS, and NF/ TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA. Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Table 5: 96-Ball FBGA - x16 Ball Descriptions (continued) Ball Assignments Symbol Type Description T2 RESET# Input D3 UDM Input E3, F7, F2, F8, H3, H8, G2, H7 D7, C3, C8, C2, A7, A2, B8, A3 F3, G3 DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7 DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15 LDQS, LDQS# I/O Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 0.8 x VDD and DC LOW 0.2 x VDDQ. RESET# assertion and desertion are asynchronous. Input data mask: UDM is an upper-byte, input mask signal for write data. Upper-byte input data is masked when UDM is sampled HIGH along with that input data during a WRITE access. Although the UDM ball is input-only, the UDM loading is designed to match that of the DQ and DQS balls. UDM is referenced to VREFDQ. Data input/output: Lower byte of bidirectional data bus for the x16 configuration. DQ[7:0] are referenced to VREFDQ. I/O Data input/output: Upper byte of bidirectional data bus for the x16 configuration. DQ[15:8] are referenced to VREFDQ. I/O C7, B7 UDQS, UDQS# I/O B2, D9, G7, K2, K8, N1, N9, R1, R9 A1, A8, C1, C9, D2, E9, F1, H2, H9 M8 VDD Supply Lower byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. Upper byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. DQS is center-aligned to write data. Power supply: 1.5V 0.075V. VDDQ Supply VREFCA Supply H1 VREFDQ Supply A9, B3, E1, G8, J2, J8, M1, M9, P1, P9, T1, T9 B1, B9, D1, D8, E2, E8, F9, G1, G9 L8 VSS Supply DQ power supply: 1.5V 0.075V. Isolated on the device for improved noise immunity. Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. Reference voltage for data: VREFDQ must be maintained at all times (excluding self refresh) for proper device operation. Ground. VSSQ Supply DQ ground: Isolated on the device for improved noise immunity. J1, J9, L1, L9, M7, T3, T7 PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN ZQ NC Reference External reference ball for output drive calibration: This ball is tied to an external 240 resistor (RZQ), which is tied to VSSQ. - No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Package Dimensions Figure 9: 78-Ball FBGA - x4, x8; "JP" 0.8 0.1 Seating plane 0.12 A A 78X O0.45 Dimensions apply to solder balls postreflow on O0.33 NSMD ball pads. 8 0.15 9 8 7 3 2 Ball A1 ID 1 Ball A1 ID A B C D 0.8 TYP E F 9.6 CTR G 11.5 0.15 H J K L M N 0.8 TYP Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 1.2 MAX 6.4 CTR 0.25 MIN 1. All dimensions are in millimeters. 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Figure 10: 78-Ball FBGA - x4, x8; "HX" 0.8 0.1 Seating plane 0.12 A A 78X O0.45 Solder ball material: SAC305. Dimensions apply to solder balls postreflow on O0.33 NSMD ball pads. Ball A1 ID 9 8 7 Ball A1 ID 3 2 1 A B C D E F 9.6 CTR G 11.5 0.15 H J K L M 0.8 TYP N 0.8 TYP 1.2 MAX 0.25 MIN 6.4 CTR 9 0.15 Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 1. All dimensions are in millimeters. 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Figure 11: 86-Ball FBGA - x4, x8; "BY" 0.8 0.1 Seating plane 0.12 A A 86X O0.45 Dimensions apply to solder balls post-reflow on O0.33 NSMD ball pads. Ball A1 ID 9 8 7 Ball A1 ID 3 2 1 A D 0.8 TYP E F G H J 14.4 CTR K 15.5 0.15 L M N P R T 2.4 TYP W 0.8 TYP 1.2 MAX 0.25 MIN 6.4 CTR 9 0.15 Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 1. All dimensions are in millimeters. 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Figure 12: 96-Ball FBGA - x16; "JT" 0.8 0.1 Seating plane 0.12 A A 96X O0.45 Solder ball material: SAC305. Dimensions apply to solder balls postreflow on O0.4 SMD ball pads. 9 8 7 3 2 Ball A1 ID Ball A1 ID 1 A B C D E F G H 12 CTR 14 0.15 J K L 0.8 TYP M N P R T 0.8 TYP 1.2 MAX 0.25 MIN 6.4 CTR 8 0.15 Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 1. All dimensions are in millimeters. 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Figure 13: 96-Ball FBGA - x16; "LA" 0.8 0.1 Seating plane 0.12 A A 96X O0.45 Solder ball material: SAC305. Dimensions apply to solder balls post-reflow on O0.33 NSMD ball pads. Ball A1 ID Ball A1 ID 9 8 7 3 2 1 A B C D E F G H 12 CTR 15.5 0.15 J K L M N P R 0.8 TYP S 0.8 TYP 1.2 MAX 0.25 MIN 6.4 CTR 9 0.15 Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 1. All dimensions are in millimeters. 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications Electrical Specifications Absolute Ratings Stresses greater than those listed in Table 6 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 6: Absolute Maximum Ratings Symbol Parameter Min Max Units Notes VDD VDDQ VIN, VOUT TC TSTG VDD supply voltage relative to VSS VDD supply voltage relative to VSSQ Voltage on any pin relative to VSS Operating case temperature Storage temperature -0.4 -0.4 -0.4 0 -55 1.975 1.975 1.975 95 150 V V V C C 1 Notes: 2, 3 1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be greater than 0.6 x VDDQ. When VDD and VDDQ are less than 500mV, VREF may be 300mV. 2. MAX operating case temperature. TC is measured in the center of the package (see Figure 14 on page 30). 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation. Input/Output Capacitance Table 7: Input/Output Capacitance Note 1 applies to the entire table Capacitance Parameters CK and CK# C: CK to CK# Single-end I/O: DQ, DM Differential I/O: DQS, DQS#, TDQS, TDQS# C: DQS to DQS#, TDQS, TDQS# C: DQ to DQS Inputs (CTRL, CMD, ADDR) C: CTRL to CK C: CMD_ADDR to CK Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Symbol Min Max Min Max Min Max Min Max Units Notes CCK CDCK CIO CIO 0.8 0 1.5 1.5 1.6 0.15 3.0 3.0 0.8 0 1.5 1.5 1.6 0.15 3.0 3.0 0.8 0 1.5 1.5 1.4 0.15 2.5 2.5 0.8 0 1.5 1.5 1.4 0.15 2.3 2.3 pF pF pF pF 2 3 0 CDDQS -0.5 CDIO 0.75 CI CDI_CTRL -0.5 CDI_CMD_ADDR -0.5 0.2 0.3 1.4 0.3 0.5 0 -0.5 0.75 -0.5 -0.5 0.2 0.3 1.35 0.3 0.5 0 -0.5 0.75 -0.4 -0.4 0.15 0.3 1.3 0.2 0.4 0 -0.5 0.75 -0.4 -0.4 0.15 0.3 1.3 0.2 0.4 pF pF pF pF pF 3 4 5 6 7 1. VDD = +1.5V 0.075mV, VDDQ = VDD, VREF = VSS, f = 100 MHz, TC = 25C. VOUT(DC) = 0.5 x VDDQ, VOUT (peak-to-peak) = 0.1V. 2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 3. Includes TDQS, TDQS#. CDDQS is for DQS vs. DQS# and TDQS vs. TDQS# separately. 4. CDIO = CIO (DQ) - 0.5 x (CIO [DQS] + CIO [DQS#]). 5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR = A[n:0], BA[2:0]. 6. CDI_CTRL = CI (CTRL) - 0.5 x (CCK [CK] + CCK [CK#]). 7. CDI_CMD_ADDR = CI (CMD_ADDR) - 0.5 x (CCK [CK] + CCK [CK#]). 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Thermal Characteristics Thermal Characteristics Table 8: Thermal Characteristics Parameter/Condition Value Units Symbol Notes Operating case temperature 0 to 85 C TC 1, 2, 3 Junction-to-case (TOP) Notes: 0 to 95 C TC 1, 2, 3, 4 78-ball "HX" 3.2 C/W JC 5 78-ball "JP" TBD 86-ball "BY" 2.8 96-ball "LA" 2.8 96-ball "JT TBD 1. MAX operating case temperature. TC is measured in the center of the package (see Figure 14). 2. A thermal solution must be designed to ensure the DRAM device does not exceed the maximum TC during operation. 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation. 4. If TC exceeds 85C, the DRAM must be refreshed externally at 2X refresh, which is a 3.9s interval refresh rate. The use of SRT or ASR (if available) must be enabled. 5. The thermal resistance data is based off of a number of samples from multiple lots and should be viewed as a typical number. Figure 14: Thermal Measurement Point (L/2) Tc test point L (W/2) W PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions Electrical Specifications - IDD Specifications and Conditions Within the following Idd measurement tables (Table 9 through Table 19), the following definitions and conditions are used, unless stated otherwise: * LOW: VIN VIL(AC) MAX; HIGH: VIN VIH(AC) MIN * Mid-level: Inputs are VREF = VDD/2 * RON set to RZQ/7, that is, 34 * RTT_NOM set to RZQ/6, that is, 40. * RTT_WR set to RZQ/2, that is, 120. * QOFF is enabled in MR1 * ODT is enabled in MR1 (RTT_NOM) and MR2 (RTT_WR) * TDQS is disabled in MR1 * External DQ/DQS/DM load resister is 25 to VDDQ/2 * Burst lengths are BL8 fixed * AL equals 0 (except in IDD7) * IDD specifications are tested after the device is properly initialized * Input slew rate is specified by AC parametric test conditions * Optional ASR is disabled * READ burst type uses nibble sequential (MR0 [3] 0) * Loop patterns must be executed at least once prior to current measurements begin Table 9: Timing Parameters used for IDD Measurements - Clock Units DDR3-800 IDD Parameter DDR3-1333 DDR3-1600 -25E -25 -187E -187 -15E -15 -125E -125 5-5-5 6-6-6 7-7-7 8-8-8 9-9-9 10-10-10 10-10-10 11-11-11 6 6 21 15 6 16 20 4 4 44 7 7 27 20 7 20 27 4 6 59 tCK (MIN) IDD CL IDD tRCD (MIN) IDD tRC (MIN) IDD tRAS (MIN) IDD t RP (MIN) tFAW x4, x8 x16 tRRD IDD x4, x8 x16 t RFC 1Gb DDR3-1066 2.5 5 5 20 15 5 16 20 4 4 44 PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 1.875 1.5 8 8 28 20 8 20 27 4 6 59 9 9 33 24 9 20 30 4 5 74 31 1.25 10 10 34 24 10 20 30 4 5 74 10 10 38 28 10 24 32 5 6 88 11 11 39 28 11 24 32 5 6 88 Units ns CK CK CK CK CK CK CK CK CK CK Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions Data A[2:0] A[6:3] A[9:7] A[10] A[15:11] BA[2:0] ODT WE# 1 2 x nRC 0 0 1 1 0 0 0 0 0 0 0 - 1 0 0 0 0 0 0 0 0 0 0 - 1 0 0 0 0 0 0 0 0 0 0 - 1 1 1 1 0 0 0 0 0 0 0 - 1 1 1 1 0 0 0 0 0 0 0 - Repeat cycles 1 through 4 until nRAS - 1, truncate if needed PRE 0 0 1 0 0 0 0 0 0 0 0 - Repeat cycles 1 through 4 until nRC - 1, truncate if needed ACT 0 0 1 1 0 0 0 0 0 F 0 - D 1 0 0 0 0 0 0 0 0 F 0 - D 1 0 0 0 0 0 0 0 0 F 0 - D# 1 1 1 1 0 0 0 0 0 F 0 - D# 1 1 1 1 0 0 0 0 0 F 0 - Repeat cycles nRC + 1 through nRC + 4 until nRC - 1 + nRAS -1, truncate if needed PRE 0 0 1 0 0 0 0 0 0 F 0 - Repeat cycles nRC + 1 through nRC + 4 until 2 x RC - 1, truncate if needed Repeat sub-loop 0, use BA[2:0] = 1 2 4 x nRC Repeat sub-loop 0, use BA[2:0] = 2 3 6 x nRC Repeat sub-loop 0, use BA[2:0] = 3 4 8 x nRC Repeat sub-loop 0, use BA[2:0] = 4 5 10 x nRC Repeat sub-loop 0, use BA[2:0] = 5 6 12 x nRC Repeat sub-loop 0, use BA[2:0] = 6 7 14 x nRC Repeat sub-loop 0, use BA[2:0] = 7 nRAS Static HIGH 0 Toggling CAS# ACT D D D# D# RAS# Command 0 1 2 3 4 CS# Cycle Number IDD0 Measurement Loop Sub-loop CKE CK, CK# Table 10: nRC nRC + 1 nRC + 2 nRC + 3 nRC + 4 nRC + nRAS Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 1. DQs, DQS, DQS# are mid-level. 2. DM is LOW. 3. Only selected bank (single) active. 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions nRCD nRAS Static HIGH Toggling 0 nRC nRC + 1 nRC + 2 nRC + 3 nRC + 4 nRC + nRCD nRC + nRAS 2 x nRC 2 4 x nRC Repeat sub-loop 0, use BA[2:0] = 2 3 6 x nRC Repeat sub-loop 0, use BA[2:0] = 3 4 8 x nRC Repeat sub-loop 0, use BA[2:0] = 4 5 10 x nRC Repeat sub-loop 0, use BA[2:0] = 5 6 12 x nRC Repeat sub-loop 0, use BA[2:0] = 6 7 14 x nRC Repeat sub-loop 0, use BA[2:0] = 7 PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 1. 2. 3. 4. Data3 A[2:0] 0 0 1 1 0 0 0 0 0 0 0 - 1 0 0 0 0 0 0 0 0 0 0 - 1 0 0 0 0 0 0 0 0 0 0 - 1 1 1 1 0 0 0 0 0 0 0 - 1 1 1 1 0 0 0 0 0 0 0 - Repeat cycles 1 through 4 until nRCD - 1, truncate if needed RD 0 1 0 1 0 0 0 0 0 0 0 00000000 Repeat cycles 1 through 4 until nRAS - 1, truncate if needed PRE 0 0 1 0 0 0 0 0 0 0 0 - Repeat cycles 1 through 4 until nRC - 1, truncate if needed ACT 0 0 1 1 0 0 0 0 0 F 0 - D 1 0 0 0 0 0 0 0 0 F 0 - D 1 0 0 0 0 0 0 0 0 F 0 - D# 1 1 1 1 0 0 0 0 0 F 0 - D# 1 1 1 1 0 0 0 0 0 F 0 - Repeat cycles nRC + 1 through nRC + 4 until nRC + nRCD - 1, truncate if needed RD 0 1 0 1 0 0 0 0 0 F 0 00110011 Repeat cycles nRC + 1 through nRC + 4 until nRC + nRAS - 1, truncate if needed PRE 0 0 1 0 0 0 0 0 0 F 0 - Repeat cycle nRC + 1 through nRC + 4 until 2 x nRC - 1, truncate if needed Repeat sub-loop 0, use BA[2:0] = 1 1 Notes: A[6:3] A[9:7] A[10] A[15:11] BA[2:0] ODT WE# CAS# ACT D D D# D# RAS# Command 0 1 2 3 4 CS# Cycle Number IDD1 Measurement Loop Sub-loop CKE CK, CK# Table 11: DQs, DQS, DQS# are mid-level unless driven as required by the READ (RD) command. DM is LOW. Burst sequence is driven on each DQ signal by the RD command. Only selected bank (single) active. 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions TableI 12: IDD Measurement Conditions for Power-Down Currents Name Timing pattern CKE External clock tCK t RC t RAS t RCD tRRD t RC CL AL CS# Command inputs Row/column addr Bank addresses DM Data I/O Output buffer DQ, DQS ODT2 Burst length Active banks Idle banks Special notes Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN IDD2P0 Precharge Power-Down Current (Slow Exit)1 IDD2P1 Precharge Power-Down Current (Fast Exit)1 IDD2Q Precharge Quiet Standby Current IDD3P Active PowerDown Current n/a LOW Toggling t CK (MIN) IDD n/a n/a n/a n/a n/a n/a n/a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, off 8 None All n/a n/a LOW Toggling t CK(MIN) IDD n/a n/a n/a n/a n/a n/a n/a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, off 8 None All n/a n/a HIGH Toggling t CK(MIN) IDD n/a n/a n/a n/a n/a n/a n/a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, off 8 None All n/a n/a LOW Toggling t CK (MIN) IDD n/a n/a n/a n/a n/a n/a n/a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, off 8 All None n/a 1. MR0[12] defines DLL on/off behavior during precharge power-down only; DLL on (fast exit, MR0[12] = 1) and DLL off (slow exit, MR0[12] = 0). 2. "Enabled, off" means the MR bits are enabled, but the signal is LOW. 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions A[9:7] A[6:3] A[2:0] Data A[10] A[15:11] CAS# BA[2:0] RAS# - - - - ODT CS# 0 0 0 0 WE# Command 0 0 F F 8-11 Repeat sub-loop 0, use BA[2:0] = 2 3 12-15 Repeat sub-loop 0, use BA[2:0] = 3 4 16-19 Repeat sub-loop 0, use BA[2:0] = 4 5 20-23 Repeat sub-loop 0, use BA[2:0] = 5 6 24-27 Repeat sub-loop 0, use BA[2:0] = 6 7 28-31 Repeat sub-loop 0, use BA[2:0] = 7 1. DQs, DQS, DQS# are mid-level. 2. DM is LOW. 3. All banks closed during IDDD2N, all banks open during IDD3N. A[2:0] Data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 F 1 1 0 0 0 0 0 F Repeat sub-loop 0, use BA[2:0] = 1; ODT = 0 0 0 0 0 - - - - A[10] A[9:7] A[15:11] BA[2:0] 0 0 1 1 ODT 1 1 1 1 WE# RAS# D D D# D# CAS# CS# Cycle Number Sub-loop IDD2NT Measurement Loop A[6:3] Static HIGH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 Repeat sub-loop 0, use BA[2:0] = 1 Command Static HIGH CKE CK, CK# 0 0 1 1 2 1 0 1 2 3 4-7 2 8-11 Repeat sub-loop 0, use BA[2:0] = 2; ODT = 1 3 12-15 Repeat sub-loop 0, use BA[2:0] = 3; ODT = 1 4 16-19 Repeat sub-loop 0, use BA[2:0] = 4; ODT = 0 5 20-23 Repeat sub-loop 0, use BA[2:0] = 5; ODT = 0 6 24-27 Repeat sub-loop 0, use BA[2:0] = 6; ODT = 1 7 28-31 Repeat sub-loop 0, use BA[2:0] = 7; ODT = 1 0 Toggling 1 1 1 1 1 Notes: Table 14: D D D# D# 0 1 2 3 4-7 0 Toggling Cycle Number IDD2N and IDD3N Measurement Loop Sub-loop CKE CK, CK# Table 13: Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 1. DQs, DQS, DQS# are mid-level. 2. DM is LOW. 3. All banks closed. 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions A[9:7] A[6:3] A[2:0] Data3 0 0 0 0 0 0 0 0 00000000 - - - 00110011 - - - A[10] 0 0 0 0 F F F F A[15:11] CAS# 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 Repeat sub-loop 0, use BA[2:0] = 1 BA[2:0] RAS# 1 0 1 1 1 0 1 1 ODT CS# 0 1 1 1 0 1 1 1 WE# Command Static HIGH RD D D# D# RD D D# D# 1 0 1 2 3 4 5 6 7 8-15 2 16-23 Repeat sub-loop 0, use BA[2:0] = 2 3 24-31 Repeat sub-loop 0, use BA[2:0] = 3 4 32-39 Repeat sub-loop 0, use BA[2:0] = 4 5 40-47 Repeat sub-loop 0, use BA[2:0] = 5 6 48-55 Repeat sub-loop 0, use BA[2:0] = 6 7 56-63 Repeat sub-loop 0, use BA[2:0] = 7 0 Toggling Cycle Number IDD4R Measurement Loop Sub-loop CKE CK, CK# Table 15: Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 1. 2. 3. 4. DQs, DQS, DQS# are mid-level when not driving in burst sequence. DM is LOW. Burst sequence is driven on each DQ signal by the RD command. All banks open. 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions A[9:7] A[6:3] A[2:0] Data3 0 0 0 0 0 0 0 0 00000000 - - - 00110011 - - - A[10] 0 0 0 0 F F F F A[15:11] CAS# 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 Repeat sub-loop 0, use BA[2:0] = 1 BA[2:0] RAS# 1 0 1 1 1 0 1 1 ODT CS# 0 1 1 1 0 1 1 1 WE# Command Static HIGH WR D D# D# WR D D# D# 1 0 1 2 3 4 5 6 7 8-15 2 16-23 Repeat sub-loop 0, use BA[2:0] = 2 3 24-31 Repeat sub-loop 0, use BA[2:0] = 3 4 32-39 Repeat sub-loop 0, use BA[2:0] = 4 5 40-47 Repeat sub-loop 0, use BA[2:0] = 5 6 48-55 Repeat sub-loop 0, use BA[2:0] = 6 7 56-63 Repeat sub-loop 0, use BA[2:0] = 7 0 Toggling Cycle Number IDD4W Measurement Loop Sub-loop CKE CK, CK# Table 16: Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 1. 2. 3. 4. DQs, DQS, DQS# are mid-level when not driving in burst sequence. DM is LOW. Burst sequence is driven on each DQ signal by the WRITE (WR) command. All banks open. 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions Cycle Number Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data IDD5B Measurement Loop Sub-loop CKE CK, CK# Table 17: 0 0 REF 0 0 0 1 0 0 0 0 0 0 0 - D D D# D# 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 Repeat sub-loop 1a, use BA[2:0] = 1 0 0 F F 0 0 0 0 - - - - 1b 1 2 3 4 5-8 1c 9-12 Repeat sub-loop 1a, use BA[2:0] = 2 1d 13-16 Repeat sub-loop 1a, use BA[2:0] = 3 1e 17-20 Repeat sub-loop 1a, use BA[2:0] = 4 1f 21-24 Repeat sub-loop 1a, use BA[2:0] = 5 1g 25-28 Repeat sub-loop 1a, use BA[2:0] = 6 1h 29-32 Repeat sub-loop 1a, use BA[2:0] = 7 2 33-nRFC - 1 Repeat sub-loop 1a through 1h until nRFC - 1, truncate if needed Static HIGH Toggling 1a Notes: Table 18: 1. DQs, DQS, DQS# are mid-level. 2. DM is LOW. IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 IDD Test CKE External clock t CK t RC tRAS tRCD tRRD t RC CL AL CS# Command inputs Row/column addresses Bank addresses Data I/O Output buffer DQ, DQS ODT1 Burst length PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN IDD6: Self Refresh Current Normal Temperature Range TC = 0C to 85C IDD6ET: Self Refresh Current Extended Temperature Range TC = 0C to 95C IDD8: Reset2 LOW Off, CK and CK# = LOW n/a n/a n/a n/a n/a n/a n/a n/a Mid-level Mid-level Mid-level Mid-level Mid-level Enabled Enabled, mid-level n/a LOW Off, CK and CK# = LOW n/a n/a n/a n/a n/a n/a n/a n/a Mid-level Mid-level Mid-level Mid-level Mid-level Enabled Enabled, mid-level n/a Mid-level Mid-level n/a n/a n/a n/a n/a n/a n/a n/a Mid-level Mid-level Mid-level Mid-level Mid-level Mid-level Mid-level n/a 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions Table 18: IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 IDD Test Active banks Idle banks SRT ASR Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN IDD6: Self Refresh Current Normal Temperature Range TC = 0C to 85C IDD6ET: Self Refresh Current Extended Temperature Range TC = 0C to 95C IDD8: Reset2 n/a n/a disabled (normal) disabled n/a n/a enabled (extended) disabled None All n/a n/a 1. Enabled, mid-level" means the MR command is enabled, but the signal is mid-level. 2. During a cold boot RESET (initialization), the current reading is valid once power is stable and RESET has been LOW for 1ms; during a warm boot RESET (while operating), the current reading is valid after RESET has been LOW for 200ns + tRFC. 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions 1 Static HIGH 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 1. 2. 3. 4. ACT RDA D D D ACT RDA D ACT RDA D D D Data3 A[2:0] A[6:3] A[9:7] A[10] 1 0 0 A[15:11] 0 1 0 BA[2:0] CAS# 0 0 1 ODT RAS# ACT RDA D WE# CS# 0 1 2 3 nRRD nRRD + 1 nRRD + 2 nRRD + 3 2 x nRRD 3 x nRRD 4 x nRRD 4 x nRRD + 1 nFAW nFAW + nRRD nFAW + 2 x nRRD nFAW + 3 x nRRD nFAW + 4 x nRRD nFAW + 4 x nRRD + 1 2 x nFAW 2 x nFAW + 1 2 x nFAW + 2 2 x nFAW + 3 2 x nFAW + nRRD 2 x nFAW + nRRD + 1 2 x nFAW + nRRD + 2 2 x nFAW + nRRD + 3 2 x nFAW + 2 x nRRD 2 x nFAW + 3 x nRRD 2 x nFAW + 4 x nRRD 2 x nFAW + 4 x nRRD + 1 3 x nFAW 3 x nFAW + nRRD 3 x nFAW + 2 x nRRD 3 x nFAW + 3 x nRRD 3 x nFAW + 4 x nRRD 3 x nFAW + 4 x nRRD + 1 Command 0 Toggling Cycle Number IDD7 Measurement Loop Sub-loop CKE CK, CK# Table 19: 1 0 0 0 0 0 0 0 - 1 0 0 0 1 0 0 0 00000000 0 0 0 0 0 0 0 0 - Repeat cycle 2 until nRRD - 1 0 0 1 1 0 1 0 0 0 F 0 - 0 1 0 1 0 1 0 1 0 F 0 00110011 1 0 0 0 0 1 0 0 0 F 0 - Repeat cycle nRRD + 2 until 2 x nRRD - 1 Repeat sub-loop 0, use BA[2:0] = 2 Repeat sub-loop 1, use BA[2:0] = 3 1 0 0 0 0 3 0 0 0 F 0 - Repeat cycle 4 x nRRD until nFAW - 1, if needed Repeat sub-loop 0, use BA[2:0] = 4 Repeat sub-loop 1 use BA[2:0] = 5 Repeat sub-loop 0, use BA[2:0] = 6 Repeat sub-loop 1 use BA[2:0] = 7 1 0 0 0 0 7 0 0 0 F 0 - Repeat cycle nFAW + 4 x nRRD until 2 x nFAW - 1, if needed 0 0 1 1 0 0 0 0 0 F 0 - 0 1 0 1 0 0 0 1 0 F 0 00110011 1 0 0 0 0 0 0 0 0 F 0 - Repeat cycle 2 x nFAW + 2 until 2 x nFAW + nRRD - 1 0 0 1 1 0 1 0 0 0 0 0 - 0 1 0 1 0 1 0 1 0 0 0 00000000 1 0 0 0 0 1 0 0 0 0 0 - Repeat cycle 2 x nFAW + nRRD + 2 until 2 x nFAW + 2 x nRRD - 1 Repeat sub-loop 10, use BA[2:0] = 2 Repeat sub-loop 11, use BA[2:0] = 3 1 0 0 0 0 3 0 0 0 0 0 - Repeat cycle 2 x nFAW + 4 x nRRD until 3 x nFAW - 1, if needed Repeat sub-loop 10, use BA[2:0] = 4 Repeat sub-loop 11 use BA[2:0] = 5 Repeat sub-loop 10, use BA[2:0] = 6 Repeat sub-loop 11 use BA[2:0] = 7 1 0 0 0 0 7 0 0 0 0 0 - Repeat cycle 3 x nFAW + 4 x nRRD until 4 x nFAW - 1, if needed DQs, DQS, DQS# are mid-level unless driven as required by the RD command. DM is LOW. Burst sequence is driven on each DQ signal by the RD command. AL = CL - 1. 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics - IDD Specifications Electrical Characteristics - IDD Specifications IDD values are for full operating range of voltage and temperature unless otherwise noted. Table 20: IDD Maximum Limits Speed Bin IDD Width DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Notes IDD0 x4 x8 x16 x4 x8 x16 All All All All x4, x8 x16 All x4, x8 x16 x4 x8 x16 x4 x8 x16 All All All x4 x8 x16 All 65 90 90 85 110 110 12 30 46 50 65 80 30 52 50 130 130 230 160 160 240 200 6 9 230 350 350 IDD2P + 2mA 75 100 100 95 120 130 12 35 53 55 75 95 35 57 55 160 160 260 190 190 290 220 6 9 250 390 380 IDD2P + 2mA 85 110 110 105 130 150 12 40 60 65 85 105 40 62 60 200 200 290 220 220 355 240 6 9 315 490 420 IDD2P + 2mA 95 120 120 115 140 170 12 45 67 70 95 115 45 67 65 250 250 320 250 250 430 260 6 9 400 600 460 IDD2P + 2mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2, 3, 4 2, 5 1, 2 1, 2 1, 2 1, 2 IDD1 IDD2P0 (slow) IDD2P1 (fast) IDD2Q IDD2N IDD2NT IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD6ET IDD7 IDD8 Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D2.fm - Rev G 2/09 EN 1. 2. 3. 4. 5. 6. TC = 85C; SRT and ASR are disabled. Enabling ASR could increase IDDx by up to an additional 2mA. Restricted to TC (MAX) = 85C. Rev B, x4 and x8 maximum limit is 7mA. TC = 85C; ASR and ODT are disabled; SRT is enabled. The IDD values must be derated (increased) on IT-option and AT-option devices when operated outside of the range 0C TC 85C: 6a. When TC < 0C: IDD2P and IDD3P must be derated by 4%; IDD4R and IDD5W must be derated by 2%; and IDD6 and IDD7 must be derated by 7%. 6b. When TC > 85C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5W must be derated by 2%; IDD2Px must be derated by 30%; and IDD6 must be derated by 80%. 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC Electrical Specifications - DC and AC DC Operating Conditions Table 21: DC Electrical Characteristics and Operating Conditions All voltages are referenced to VSS Parameter/Condition Supply voltage I/O supply voltage Input leakage current Any input 0V VIN VDD, VREF pin 0V VIN 1.1V (All other pins not under test = 0V) VREF supply leakage current VREFDQ = VDD/2 or VREFCA = VDD/2 (All other pins not under test = 0V) Notes: Symbol Min Nom Max Units Notes VDD VDDQ II 1.425 1.425 -2 1.5 1.5 - 1.575 1.575 2 V V A 1, 2 1, 2 IVREF -1 - 1 A 3, 4 1. VDD and VDDQ must track one another. VDDQ must be less than or equal to VDD. VSS = VSSQ. 2. VDD and VDDQ may include AC noise of 50mV (250 kHz to 20 MHz) in addition to the DC (0Hz to 250 kHz) specifications. VDD and VDDQ must be at same level for valid AC timing parameters. 3. VREF (see Table 22). 4. The minimum limit requirement is for testing purposes. The leakage current on the VREF pin should be minimal. Input Operating Conditions Table 22: DC Electrical Characteristics and Input Conditions All voltages are referenced to VSS Parameter/Condition Symbol VIN low; DC/commands/address busses VIN high; DC/commands/address busses Input reference voltage command/address bus I/O reference voltage DQ bus I/O reference voltage DQ bus in SELF REFRESH Command/address termination voltage (system level, not direct DRAM input) Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN VIL VIH VREFCA(DC) VREFDQ(DC) VREFDQ(SR) VTT Min Nom VSS n/a See Table 21 n/a 0.49 x VDD 0.5 x VDD 0.49 x VDD 0.5 x VDD VSS 0.5 x VDD - 0.5 x VDDQ Max Units Notes See Table 21 VDD 0.51 x VDD 0.51 x VDD VDD - V V V V V V 1, 2 2, 3 4 5 1. VREFCA(DC) is expected to be approximately 0.5 x VDD and to track variations in the DC level. Externally generated peak noise (noncommon mode) on VREFCA may not exceed 1% x VDD around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not exceed 2% of VREFCA(DC). 2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifications if the DRAM induces additional AC noise greater than 20 MHz in frequency. 3. VREFDQ(DC) is expected to be approximately 0.5 x VDD and to track variations in the DC level. Externally generated peak noise (noncommon mode) on VREFDQ may not exceed 1% x VDD around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not exceed 2% of VREFDQ(DC). 4. VREFDQ(DC) may transition to VREFDQ(SR) and back to VREFDQ(DC) when in SELF REFRESH, within restrictions outlined in the SELF REFRESH section. 5. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors. MIN and MAX values are system-dependent. 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC Table 23: Input Switching Conditions Parameter/Condition DDR3-800 DDR3-1066 Symbol DDR3-1333 DDR3-1600 Units +175 +150 +100 -100 -150 -175 175 +150 +100 -100 -150 -175 mV mV mV mV mV mV +175 +150 +100 -100 -150 -175 - +150 +100 -100 -150 - mV mV mV mV mV mV Command and Address Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high DC voltage: Logic 1 Input low DC voltage: Logic 0 Input low AC voltage: Logic 0 Input low AC voltage: Logic 0 VIH(AC175) MIN VIH(AC150) MIN VIH(DC100) MIN VIL(DC100) MAX VIL(AC150) MAX VIL(AC175) MAX Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high DC voltage: Logic 1 Input low DC voltage: Logic 0 Input low AC voltage: Logic 0 Input low AC voltage: Logic 0 VIH(AC175) MIN VIH(AC150) MIN VIH(DC100) MIN VIL(DC100) MAX VIL(AC150) MAX VIL(AC)175 MAX DQ and DM Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 1. All voltages are referenced to VREF. VREF is VREFCA for control, command, and address. All slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ and DM inputs. 2. Input setup timing parameters (tIS and tDS) are referenced at VIL(AC)/VIH(AC), not VREF(DC). 3. Input hold timing parameters (tIH and tDH) are referenced at VIL(DC)/VIH(DC), not VREF(DC). 4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is 900mV (peak-to-peak). 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC Figure 15: Input Signal VIL and VIH levels with ringback 1.90V VDDQ + 0.4V narrow pulse width 1.50V VDDQ 0.925V VIH(AC) 0.850V VIH(DC) Minimum VIL and VIH levels 0.925V 0.850V VIH(AC) VIH(DC) 0.780V 0.765V 0.750V 0.735V 0.720V 0.780V 0.765V 0.750V 0.735V 0.720V 0.650V 0.575V VIL(DC) VIL(AC) VREF + AC noise VREF + DC error VREF - DC error VREF - AC noise 0.650V VIL(DC) 0.575V VIL(AC) 0.0V VSS VSS - 0.4V narrow pulse width -0.40V Notes: 1. Numbers in diagrams reflect nominal values. AC Overshoot/Undershoot Specification Table 24: Control and Address Pins Parameter Maximum peak amplitude allowed for overshoot area (see Figure 16 on page 45) Maximum peak amplitude allowed for undershoot area (see Figure 17 on page 45) Maximum overshoot area above VDD (see Figure 16 on page 45) Maximum undershoot area below VSS (see Figure 17 on page 45) PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 44 DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.67 Vns 0.67 Vns 0.5 Vns 0.5 Vns 0.4 Vns 0.4 Vns 0.33 Vns 0.33 Vns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC Table 25: Clock, Data, Strobe, and Mask Pins Parameter Maximum peak amplitude allowed for overshoot area (see Figure 16 on page 45) Maximum peak amplitude allowed for undershoot area (see Figure 17 on page 45) Maximum overshoot area above VDD/VDDQ (see Figure 16 on page 45) Maximum undershoot area below VSS/VSSQ (see Figure 17 on page 45) Figure 16: DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.25 Vns 0.19 Vns 0.15 Vns 0.13 Vns 0.25 Vns 0.19 Vns 0.15 Vns 0.13 Vns Overshoot Maximum amplitude Overshoot area Volts (V) VDD/VDDQ Time (ns) Figure 17: Undershoot VSS/VSSQ Volts (V) Undershoot area Maximum amplitude Time (ns) PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 45 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC Table 26: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) Parameter/Condition Differential input voltage logic high - slew Differential input voltage logic low - slew Differential input voltage logic high Differential input voltage logic low Differential input crossing voltage relative to VDD/2 for DQS, DQS#; CK, CK# Differential input crossing voltage relative to VDD/2 for CK, CK# Single-ended high level for strobes Single-ended high level for CK, CK# Single-ended low level for strobes Single-ended low level for CK, CK# Notes: Figure 18: Symbol Min Max Units Notes VIHDIFF(AC)slew VILDIFF(AC)slew VIHDIFF(AC) VILDIFF(AC) +200 n/a 2 x (VIH(AC)-VREF) VSS/VSSQ VREF(DC) - 150 n/a -200 VDD/VDDQ 2 x (VREF - VIL(AC)) VREF(DC) + 150 mV mV mV mV mV 4 4 5 6 7 VREF(DC) - 175 VREF(DC) + 175 mV 7, 8 VDDQ/2 + VIH(AC) VDD/2 + VIH(AC) VSSQ VSS VDDQ VDD VDDQ/2 - VIL(AC) VDD/2 - VIL(AC) mV mV mV mV 5 5 6 6 VIX VIX (175) VSHE VSEL 1. 2. 3. 4. 5. 6. 7. Clock is referenced to VDD and VSS. Data strobe is referenced to VDDQ and VSSQ. Reference is VREFCA(DC) for clock and for VREFDQ(DC) for strobe. Differential input slew rate = 2 V/ns Defines slewrate reference points, relative to input crossing voltages. MAX limit is relative to single-ended signals, the overshoot specifications are applicable. MIN limit is relative to single-ended signals, the undershoot specifications are applicable. The typical value of VIX(AC) is expected to be about 0.5 x VDD of the transmitting device, and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which differential input signals must cross. 8. The VIX extended range (175mV) is allowed only for the clock, and this VIX extended range is only allowed when the following conditions are met: The single-ended input signals are monotonic, have the single-ended swing VSEL, VSEH of at least VDD/2 250mV, and the differential slew rate of CK, CK# is greater than 3 V/ns. Vix for Differential Signals Vdd, Vddq Vdd, Vddq CK#, DQS# CK#, DQS# X Vix Vix Vdd/2, Vddq/2 X X Vdd/2, Vddq/2 Vix X CK, DQS CK, DQS Vss, Vssq PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN Vix Vss, Vssq 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC Figure 19: Single-Ended Requirements for Differential Signals VDD or VDDQ VSEH (MIN) VDD/2 or VDDQ/2 VSEH CK or DQS VSEL (MAX) VSEL VSS or VSSQ PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 47 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC Figure 20: Definition of Differential AC-Swing and tDVAC tDVAC VIHDIFF(AC) MIN VIHDIFF (MIN) VIHDIFF(DC) MIN CK - CK# DQS - DQS# 0.0 VILDIFF(DC) MAX VILDIFF (MAX) VILDIFF(AC) MAX tDVAC half cycle Table 27: Allowed Time Before Ringback (tDVAC) for CK - CK# and DQS - DQS# Below VIL(AC) tDVAC PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN (ps) at |VIHDIFF(AC) to VILDIFF(AC)| Slew Rate (V/ns) 350mV 300mV >4.0 75 175 4.0 57 170 3.0 50 167 2.0 38 163 1.9 34 162 1.6 29 161 1.4 22 159 1.2 13 155 1.0 0 150 <1.0 0 150 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC Slew Rate Definitions for Single-Ended Input Signals Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF and the first crossing of VIH(AC) MIN. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF and the first crossing of VIL(AC) MAX (see Figure 21 on page 50). Hold (tIH and tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing of VREF (see Figure 21 on page 50). Table 28: Single-Ended Input Slew Rate Definition Input Slew Rates (Linear Signals) Measured Input Edge From To Calculation Setup Rising VREF VIH(AC) MIN VIH(AC) MIN - VREF TRS Falling VREF VIL(AC) MAX VREF - VIL(AC) MAX TFS Hold Rising VIL(DC) MAX VREF VREF - VIL(DC) MAX TFH Falling VIH(DC) MIN VREF VIH(DC) MIN - VREF TRSH PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 49 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC Figure 21: Nominal Slew Rate Definition for Single-Ended Input Signals TRS Setup Single-ended input voltage (DQ, CMD, ADDR) VIH(AC) MIN VIH(DC) MIN VREFDQ or VREFCA VIL(DC) MAX VIL(AC) MAX TFS TRH Hold Single-ended input voltage (DQ, CMD, ADDR) VIH(AC) MIN VIH(DC) MIN VREFDQ or VREFCA VIL(DC) MAX VIL(AC) MAX TFH PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 50 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured, as shown in Table 29 and Figure 22. The nominal slew rate for a rising signal is defined as the slew rate between VIL(DIFF ) MAX and VIH(DIFF ) MIN. The nominal slew rate for a falling signal is defined as the slew rate between VIH(DIFF ) MIN and VIL(DIFF ) MAX. Table 29: Differential Input Slew Rate Definition Differential Input Slew Rates (Linear Signals) Measured Input Edge From To Calculation CK and DQS reference Rising VIL(DIFF) MAX VIH(DIFF) MIN VIH(DIFF) MIN - VIL(DIFF) MAX TR(DIFF) Falling VIH(DIFF) MIN VIL(DIFF) MAX VIH(DIFF) MIN - VIL(DIFF) MAX TF(DIFF) Figure 22: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# Differential input voltage (DQS, DQS#; CK, CK#) TRDIFF VIH(DIFF) MIN 0 VIL(DIFF) MAX TFDIFF PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 51 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics ODT Characteristics ODT effective resistance RTT is defined by MR1[9, 6, and 2]. ODT is applied to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls (x8 devices only). The ODT target values are listed in Table 30 and Table 31 on page 53. A functional representation of the ODT is shown in Figure 23. The individual pull-up and pull-down resistors (RTTPU and RTTPD) are defined as follows: * RTTPU = (VDDQ - VOUT)/|IOUT|, under the condition that RTTPD is turned off * RTTPD = (VOUT)/|IOUT|, under the condition that RTTPU is turned off Figure 23: ODT Levels and I-V Characteristics Chip in termination mode ODT VDDQ IPU IOUT = IPD - IPU To other circuitry such as RCV, . . . RTTPU DQ IOUT RTTPD VOUT IPD VSSQ Table 30: On-Die Termination DC Electrical Characteristics Parameter/Condition RTT effective impedance Deviation of VM with respect to VDDQ/2 Notes: Symbol Min RTT_EFF VM -5 Nom Max See Table 31 on page 53 +5 Units Notes % 1, 2 1, 2, 3 1. Tolerance limits are applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). Refer to "ODT Sensitivity" on page 53 if either the temperature or voltage changes after calibration. 2. Measurement definition for RTT: Apply VIH(AC) to pin under test and measure current I[VIH(AC)], then apply VIL(AC) to pin under test and measure current I[VIL(AC)]: V IH ( AC ) - V IL ( AC ) R TT = -------------------------------------------------------------|I ( V IH ( AC ) ) - I ( V IL ( AC ) )| 3. Measure voltage (VM) at the tested pin with no load: 2 x VM VM = ------------------ - 1 x 100 V DD Q 4. For IT and AT devices, the minimum values are derated by 6% when the device operates between -40C and 0C (TC). ODT Resistors Table 31 on page 53 provides an overview of the ODT DC electrical characteristics. The values provided are not specification requirements; however, they can be used as design guidelines to indicate what RTT is targeted to provide: * RTT 120 is made up of RTT120PD240 and RTT120PU240 * RTT 60 is made up of RTT60PD120 and RTT60PU120 * RTT 40 is made up of RTT40PD80 and RTT40PU80 * RTT 30 is made up of RTT30PD60 and RTT30PU60 * RTT 20 is made up of RTT20PD40 and RTT20PU40 PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 52 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics Table 31: RTT Effective Impedances MR1 [9, 6, 2] RTT Resistor VOUT Min Nom Max Units 0, 1, 0 120 RTT120PD240 0.2 x VDDQ 0.5 x VDDQ 0.8 x VDDQ 0.2 x VDDQ 0.5 x VDDQ 0.8 x VDDQ VIL(AC) to VIH(AC) 0.2 x VDDQ 0.5 x VDDQ 0.8 x VDDQ 0.2 x VDDQ 0.5 x VDDQ 0.8 x VDDQ VIL(AC) to VIH(AC) 0.2 x VDDQ 0.5 x VDDQ 0.8 x VDDQ 0.2 x VDDQ 0.5 x VDDQ 0.8 x VDDQ VIL(AC) to VIH(AC) 0.2 x VDDQ 0.5 x VDDQ 0.8 x VDDQ 0.2 x VDDQ 0.5 x VDDQ 0.8 x VDDQ VIL(AC) to VIH(AC) 0.2 x VDDQ 0.5 x VDDQ 0.8 x VDDQ 0.2 x VDDQ 0.5 x VDDQ 0.8 x VDDQ VIL(AC) to VIH(AC) 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 RZQ/1 RZQ/1 RZQ/1 RZQ/1 RZQ/1 RZQ/1 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/4 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/6 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/8 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/12 RTT120PU240 0, 0, 1 60 120 RTT60PD120 RTT60PU120 60 0, 1, 1 40 RTT40PD80 RTT40PU80 40 1, 0, 1 30 RTT30PD60 RTT30PU60 30 1, 0, 0 20 RTT20PD40 RTT20PU40 20 Notes: 1. Values assume an RZQ of 240 (1%). ODT Sensitivity If either the temperature or voltage changes after I/O calibration, the tolerance limits listed in Table 30 on page 52 and Table 31 can be expected to widen according to Tables 32 and 33 on page 54. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 53 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics Table 32: ODT Sensitivity Definition Symbol Min Max Units RTT 0.9 - dRTTdT x |DT| - dRTTdV x |DV| 1.6 + dRTTdT x |DT| + dRTTdV x |DV| RZQ/(2, 4, 6, 8, 12) Notes: Table 33: 1. T = T - T(@ calibration), V = VDDQ - VDDQ(@ calibration) and VDD = VDDQ. ODT Temperature and Voltage Sensitivity Notes: Change Min Max Units dRTTdT 0 1.5 %/C dRTTdV 0 0.15 %/mV 1. T = T - T(@ calibration), V = VDDQ - VDDQ(@ calibration) and VDD = VDDQ. ODT Timing Definitions ODT loading differs from that used in AC timing measurements. The reference load for ODT timings is shown in Figure 24. Two parameters define when ODT turns on or off synchronously, two define when ODT turns on or off asynchronously, and another defines when ODT turns on or off dynamically. Table 34 outlines and provides definition and measurement reference settings for each parameter (see Figure 35 on page 55). ODT turn-on time begins when the output leaves High-Z and ODT resistance begins to turn on. ODT turn-off time begins when the output leaves Low-Z and ODT resistance begins to turn off. Figure 24: ODT Timing Reference Load DUT CK, CK# VREF DQ, DM DQS, DQS# TDQS, TDQS# ZQ VDDQ/2 RTT = 25 VTT = VSSQ Timing reference point RZQ = 240 VSSQ Table 34: Symbol t AON t AOF t AONPD t AOFPD tADC ODT Timing Definitions Begin Point Definition End Point Definition Figure Rising edge of CK - CK# defined by the end point of ODTL on Rising edge of CK - CK# defined by the end point of ODTL off Rising edge of CK - CK# with ODT first being registered HIGH Rising edge of CK - CK# with ODT first being registered LOW Rising edge of CK - CK# defined by the end point of ODTLCNW, ODTLCWN4, or ODTLCWN8 Extrapolated point at VSSQ Figure 25 on page 55 Extrapolated point at VRTT_NOM Figure 25 on page 55 Extrapolated point at VSSQ Figure 26 on page 56 Extrapolated point at VRTT_NOM Figure 26 on page 56 Extrapolated points at VRTT_WR and VRTT_NOM Figure 27 on page 56 PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 54 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics Table 35: Reference Settings for ODT Timing Measurements Measured Parameter t AON t AOF t AONPD t AOFPD t ADC Notes: RTT_NOM Setting RTT_WR Setting VSW1 VSW2 RZQ/4 (60) RZQ/12 (20) RZQ/4 (60) RZQ/12 (20) RZQ/4 (60) RZQ/12 (20) RZQ/4 (60) RZQ/12 (20) RZQ/12 (20) n/a n/a n/a n/a n/a n/a n/a n/a RZQ/2 (120) 50mV 100mV 50mV 100mV 50mV 100mV 50mV 100mV 200mV 100mV 200mV 100mV 200mV 100mV 200mV 100mV 200mV 300mV 1. Assume an RZQ of 240 (1%) and that proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). t AON and tAOF Definitions Figure 25: tAON tAOF Begin point: Rising edge of CK - CK# defined by the end point of ODTL off Begin point: Rising edge of CK - CK# defined by the end point of ODTL on CK CK VDDQ/2 CK# CK# tAON tAOF End point: Extrapolated point at VRTT_NOM TSW2 VRTT_NOM TSW1 TSW1 DQ, DM TSW1 DQS, DQS# TDQS, TDQS# VSW2 VSSQ VSW2 VSW1 VSW1 VSSQ End point: Extrapolated point at VSSQ PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics Figure 26: t AONPD and tAOFPD Definition tAONPD tAOFPD Begin point: Rising edge of CK - CK# with ODT first registered HIGH Begin point: Rising edge of CK - CK# with ODT first registered LOW CK CK VDDQ/2 CK# CK# tAONPD tAOFPD End point: Extrapolated point at VRTT_NOM VRTT_NOM TSW2 TSW2 TSW1 DQ, DM DQS, DQS# TDQS, TDQS# TSW1 VSW2 VSW2 VSSQ VSW1 VSW1 VSSQ End point: Extrapolated point at VSSQ Figure 27: t ADC Definition Begin point: Rising edge of CK - CK# defined by the end point of ODTLCNW Begin point: Rising edge of CK - CK# defined by the end point of ODTLCWN4 or ODTLCWN8 CK VDDQ/2 CK# tADC VRTT_NOM DQ, DM DQS, DQS# TDQS, TDQS# End point: Extrapolated point at VRTT_NOM tADC VRTT_NOM TSW21 TSW11 VSW2 TSW22 TSW12 VSW1 VRTT_WR End point: Extrapolated point at VRTT_WR VSSQ PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 56 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Output Driver Impedance The output driver impedance is selected by MR1[5,1] during initialization. The selected value is able to maintain the tight tolerances specified if proper ZQ calibration is performed. Output specifications refer to the default output driver unless specifically stated otherwise. A functional representation of the output buffer is shown in Figure 28 on page 57. The output driver impedance RON is defined by the value of the external reference resistor RZQ as follows: * RONx = RZQ/y (with RZQ = 240 1%; x = 34 or 40 with y = 7 or 6, respectively) The individual pull-up and pull-down resistors (RONPU and RONPD) are defined as follows: * RONPU = (VDDQ - VOUT)/|IOUT|, when RONPD is turned off * RONPD = (VOUT)/|IOUT|, when RONPU is turned off Figure 28: Output Driver Chip in drive mode Output driver VDDQ IPU To other circuitry such as RCV, . . . RONPU DQ IOUT RONPD VOUT IPD VSSQ 34 Ohm Output Driver Impedance The 34 driver (MR1[5, 1] = 01) is the default driver. Unless otherwise stated, all timings and specifications listed herein apply to the 34 driver only. Its impedance RON is defined by the value of the external reference resistor RZQ as follows: RON34 = RZQ/7 (with nominal RZQ = 240 1%) and is actually 34.3 1%. The 34 output driver impedance characteristics are listed in Table 36 on page 58. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 57 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Table 36: 34 Driver Impedance Characteristics MR1[5,1] RON Resistor VOUT Min Nom Max Units Notes 0,1 34.3 RON34PD 0.2/VDDQ 0.5/VDDQ 0.8/VDDQ 0.2/VDDQ 0.5/VDDQ 0.8/VDDQ 0.5/VDDQ 0.6 0.9 0.9 0.9 0.9 0.6 -10% 1.0 1.0 1.0 1.0 1.0 1.0 n/a 1.1 1.1 1.4 1.4 1.1 1.1 10 RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 % 1 1 1 1 1 1 1, 2 RON34PU Pull-up/pull-down mismatch (MMPUPD) Notes: 1. Tolerance limits assume RZQ of 240 (1%) and are applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). Refer to "34 Ohm Driver Output Sensitivity" on page 59 if either the temperature or the voltage changes after calibration. 2. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Measure both RONPU and RONPD at 0.5 x VDDQ: R ON PU - R ON PD MM PUPD = -----------------------------------X 100 R ON N OM 3. For IT and AT devices, the minimum values are derated by 6% when the device operates between -40C and 0C (TC ). 34 Ohm Driver The 34 driver's current range has been calculated and summarized in Table 38 on page 59 for VDD = 1.5V, Table 39 on page 59 for VDD = 1.575V, and Table 40 on page 59 for VDD = 1.425V. The individual pull-up and pull-down resistors (RON34PD and RON34PU) are defined as follows: * RON34PD = (VOUT)/|IOUT|; RON34PU is turned off * RON34PU = (VDDQ - VOUT)/|IOUT|; RON34PD is turned off Table 37: 34 Driver Pull-Up and Pull-Down Impedance Calculations RON Min Nom Max Units RZQ = 240 1% RZQ/7 = (240 1%)/7 237.6 33.9 240 34.3 242.4 34.6 MR1[5,1] RON Resistor VOUT Min Nom Max Units 0, 1 34.3 RON34PD 0.2 x VDDQ 0.5 x VDDQ 0.8 x VDDQ 0.2 x VDDQ 0.5 x VDDQ 0.8 x VDDQ 20.4 30.5 30.5 30.5 30.5 20.4 34.3 34.3 34.3 34.3 34.3 34.3 38.1 38.1 48.5 48.5 38.1 38.1 RON34PU PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 58 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Table 38: 34 Driver IOH/IOL Characteristics: VDD = VDDQ = 1.5V MR1[5,1] RON Resistor VOUT Max Nom Min Units 0, 1 34.3 RON34PD IOL @ 0.2 x VDDQ IOL @ 0.5 x VDDQ IOL @ 0.8 x VDDQ IOH @ 0.2 x VDDQ IOH @ 0.5 x VDDQ IOH @ 0.8 x VDDQ 14.7 24.6 39.3 39.3 24.6 14.7 8.8 21.9 35.0 35.0 21.9 8.8 7.9 19.7 24.8 24.8 19.7 7.9 mA mA mA mA mA mA RON34PU Table 39: 34 Driver IOH/IOL Characteristics: VDD = VDDQ = 1.575V MR1[5,1] RON Resistor VOUT Max Nom Min Units 0, 1 34.3 RON34PD IOL @ 0.2 x VDDQ IOL @ 0.5 x VDDQ IOL @ 0.8 x VDDQ IOH @ 0.2 x VDDQ IOH @ 0.5 x VDDQ IOH @ 0.8 x VDDQ 15.5 25.8 41.2 41.2 25.8 15.5 9.2 23 36.8 36.8 23 9.2 8.3 20.7 26 26 20.7 8.3 mA mA mA mA mA mA RON34PU Table 40: 34 Driver IOH/IOL Characteristics: VDD = VDDQ = 1.425V MR1[5,1] RON Resistor VOUT Max Nom Min Units 0, 1 34.3 RON34PD IOL @ 0.2 x VDDQ IOL @ 0.5 x VDDQ IOL @ 0.8 x VDDQ IOH @ 0.2 x VDDQ IOH @ 0.5 x VDDQ IOH @ 0.8 x VDDQ 14.0 23.3 37.3 37.3 23.3 14.0 8.3 20.8 33.3 33.3 20.8 8.3 7.5 18.7 23.5 23.5 18.7 7.5 mA mA mA mA mA mA RON34PU 34 Ohm Driver Output Sensitivity If either the temperature or the voltage changes after ZQ calibration, the tolerance limits listed in Table 36 on page 58 can be expected to widen according to Table 41 and Table 42 on page 60. Table 41: 34 Output Driver Sensitivity Definition Symbol Min Max Units RON @ 0.8 x VDDQ RON @ 0.5 x VDDQ RON @ 0.2 x VDDQ 0.9 - dRONdTH x |T| - dRONdVH x |V| 0.9 - dRONdTM x |T| - dRONdVM x |V| 0.9 - dRONdTL x |T| - dRONdVL x |V| 1.1 + dRONdTH x |T| + dRONdVH x |V| 1.1 + dRONdTM x |T| + dRONdVM x |V| 1.1 + dRONdTL x |T| + dRONdVL x |V| RZQ/7 RZQ/7 RZQ/7 Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 1. T = T - T(@ calibration), V = VDDQ - VDDQ(@ calibration), and VDD = VDDQ. 59 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Table 42: 34 Output Driver Voltage and Temperature Sensitivity Change Min Max Units dRONdTM 0 1.5 %/C dRONdVM 0 0.13 %/mV dRONdTL 0 1.5 %/C dRONdVL 0 0.13 %/mV dRONdTH 0 1.5 %/C dRONdVH 0 0.13 %/mV Alternative 40 Ohm Driver Table 43: 40 Driver Impedance Characteristics MR1[5,1] RON Resistor VOUT Min Nom Max Units Notes 0,0 40 RON40PD 0.2 x VDDQ 0.5 x VDDQ 0.8 x VDDQ 0.2 x VDDQ 0.5 x VDDQ 0.8 x VDDQ 0.5 x VDDQ 0.6 0.9 0.9 0.9 0.9 0.6 -10% 1.0 1.0 1.0 1.0 1.0 1.0 n/a 1.1 1.1 1.4 1.4 1.1 1.1 10 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 % 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 RON40PU Pull-up/pull-down mismatch (MMPUPD) Notes: 1. Tolerance limits assume RZQ of 240 (1%) and are applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). Refer to "40 Ohm Driver Output Sensitivity" on page 60 if either the temperature or the voltage changes after calibration. 2. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Measure both RONPU and RONPD at 0.5 x VDDQ: R ON P U - R ON P D - x 100 MM P UP D = -----------------------------------R ON Nom 3. For IT and AT devices, the minimum values are derated by six% when the device operates between -40C and 0C (TC ). 40 Ohm Driver Output Sensitivity If either the temperature or the voltage changes after I/O calibration, the tolerance limits listed in Table 43 can be expected to widen according to Table 44 and Table 45 on page 61. Table 44: 40 Output Driver Sensitivity Definition Symbol Min Max Units RON @ 0.8 x VDDQ RON @ 0.5 x VDDQ RON @ 0.2 x VDDQ 0.9 - dRONdTH x |T| - dRONdVH x |V| 0.9 - dRONdTM x |T| - dRONdVM x |V| 0.9 - dRONdTL x |T| - dRONdVL x |V| 1.1 + dRONdTH x |T| + dRONdVH x |V| 1.1 + dRONdTM x |T| + dRONdVM x |V| 1.1 + dRONdTL x |T| + dRONdVL x |V| RZQ/6 RZQ/6 RZQ/6 Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 1. T = T - T(@ calibration), V = VDDQ - VDDQ(@ calibration), and VDD = VDDQ. 60 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Output Characteristics and Operating Conditions Table 45: 40 Output Driver Voltage and Temperature Sensitivity Change Min Max Unit dRONdTM 0 1.5 %/C dRONdVM 0 0.15 %/mV dRONdTL 0 1.5 %/C dRONdVL 0 0.15 %/mV dRONdTH 0 1.5 %/C dRONdVH 0 0.15 %/mV Output Characteristics and Operating Conditions The DRAM uses both single-ended and differential output drivers. The single-ended output driver is summarized in Table 46 while the differential output driver is summarized in Table 47 on page 62. Table 46: Single-Ended Output Driver Characteristics All voltages are referenced to Vss Parameter/Condition Output leakage current: DQ are disabled; 0V VOUT VDDQ; ODT is disabled; ODT is HIGH Output slew rate: Single-ended; For rising and falling edges, measure between VOL(AC) = VREF - 0.1 x VDDQ and VOH(AC) = VREF + 0.1 x VDDQ Single-ended DC high-level output voltage Single-ended DC mid-point level output voltage Single-ended DC low-level output voltage Single-ended AC high-level output voltage Single-ended AC low-level output voltage Delta RON between pull-up and pull-down for DQ/DQS Test load for AC timing and output slew rates Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN Symbol Min Max Units Notes IOZ -5 +5 A 1 SRQSE 2.5 6 V/ns 1, 2, 3, 4 0.8 x VDDQ V VOH(DC) 0.5 x VDDQ V VOM(DC) 0.2 x VDDQ V VOL(DC) VOH(AC) VTT + 0.1 x VDDQ V VTT - 0.1 x VDDQ V VOL(AC) MMPUPD -10 +10 % Output to VTT (VDDQ/2) via 25 resistor 1, 2, 5 1, 2, 5 1, 2, 5 1, 2, 3, 6 1, 2, 3, 6 1, 7 3 1. RZQ of 240 (1%) with RZQ/7 enabled (default 34 driver) and is applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). 2. VTT = VDDQ/2. 3. See Figure 31 on page 63 for the test load configuration. 4. The 6 V/ns maximum is applicable for a single DQ signal when it is switching from either HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are either all static or all switching the opposite direction. For all other DQ signal switching combinations, the maximum limit of 6 V/ns is reduced to 5V/ns. 5. See Table 36 on page 58 for IV curve linearity. Do not use AC test load. 6. See Table 48 on page 64 for output slew rate. 7. See Table 36 on page 58 for additional information. 8. See Figure 29 on page 62 for an example of a single-ended output signal. 61 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Output Characteristics and Operating Conditions Table 47: Differential Output Driver Characteristics All voltages are referenced to Vss Parameter/Condition Output leakage current: DQ are disabled; 0V VOUT VDDQ; ODT is disabled; ODT is HIGH Output slew rate: Differential; For rising and falling edges, measure between VOLDIFF(AC) = -0.2 x VDDQ and VOHDIFF(AC) = +0.2 x VDDQ Output differential cross-point voltage Differential high-level output voltage Differential low-level output voltage Delta RON between pull-up and pull-down for DQ/DQS Test load for AC timing and output slew rates Notes: Figure 29: Symbol Min Max Units Notes IOZ -5 +5 A 1 SRQDIFF 5 12 V/ns 1 mV V V % 1, 2, 3 1, 4 1, 4 1, 5 3 VOX(AC) VREF - 150 VREF + 150 VOHDIFF(AC) +0.2 x VDDQ -0.2 x VDDQ VOLDIFF(AC) MMPUPD -10 +10 Output to VTT (VDDQ/2) via 25 resistor 1. RZQ of 240 (1%) with RZQ/7 enabled (default 34 driver) and is applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). 2. VREF = VDDQ/2. 3. See Figure 31 on page 63 for the test load configuration. 4. See Table 49 on page 65 for the output slew rate. 5. See Table 36 on page 58 for additional information. 6. See Figure 30 on page 63 for an example of a differential output signal. DQ Output Signal MAX output VOH(AC) VOL(AC) MIN output PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 62 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Output Characteristics and Operating Conditions Figure 30: Differential Output Signal MAX output VOH(DIFF) X X VOX(AC) MAX X VOX(AC) MIN X VOL(DIFF) MIN output Reference Output Load Figure 31 represents the effective reference load of 25 used in defining the relevant device AC timing parameters (except ODT reference timing) as well as the output slew rate measurements. It is not intended to be a precise representation of a particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Figure 31: Reference Output Load for AC Timing and Output Slew Rate DUT VREF DQ DQS DQS# VDDQ/2 RTT = 25 VTT = VDDQ/2 Timing reference point ZQ RZQ = 240 VSS PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 63 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Output Characteristics and Operating Conditions Slew Rate Definitions for Single-Ended Output Signals The single-ended output driver is summarized in Table 46 on page 61. With the reference load for timing measurements, the output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single-ended signals, as shown in Table 48 and Figure 32. Table 48: Single-Ended Output Slew Rate Definition Single-Ended Output Slew Rates (Linear Signals) Measured Output Edge From To Calculation DQ Rising VOL(AC) VOH(AC) VOH(AC) - VOL(AC) TRSE Falling VOH(AC) VOL(AC) VOH(AC) - VOL(AC) TFSE Figure 32: Nominal Slew Rate Definition for Single-Ended Output Signals TRSE VOH(AC) VTT VOL(AC) TFSE PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 64 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Output Characteristics and Operating Conditions Slew Rate Definitions for Differential Output Signals The differential output driver is summarized in Table 47 on page 62. With the reference load for timing measurements, the output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for differential signals, as shown in Table 49 and Figure 33. Table 49: Differential Output Slew Rate Definition Differential Output Slew Rates (Linear Signals) Measured Output Edge From To DQS, DQS# Rising VOLDIFF(AC) VOHDIFF(AC) Calculation VOHDIFF(AC) - VOLDIFF(AC) TRDIFF Falling VOHDIFF(AC) VOLDIFF(AC) VOHDIFF(AC) - VOLDIFF(AC) TFDIFF Figure 33: Nominal Differential Output Slew Rate Definition for DQS, DQS# TRDIFF VOH(DIFF)AC 0 VOL(DIFF)AC TFDIFF PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 65 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Speed Bin Tables Table 50: DDR3-800 Speed Bins DDR3-800 Speed Bin t t CL- RCD- RP Parameter Symbol ACTIVATE to internal READ or WRITE delay time PRECHARGE command period ACTIVATE-to-ACTIVATE or REFRESH command period ACTIVATE-to-PRECHARGE command period CL = 5 CWL = 5 CL = 6 CWL = 5 Supported CL settings Supported CWL settings Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN -25E -25 5-5-5 6-6-6 Min Max Min Max Units RCD 12.5 - 15 - ns t RP RC 12.5 50 - - 15 52.5 - - ns ns RAS (AVG) tCK (AVG) 37.5 2.5 2.5 60ms 3.3 3.3 37.5 3.0 2.5 60ms 3.3 3.3 ns ns ns CK CK t t t tCK 5, 6 5 5, 6 5 Notes 1 2, 3 2 1. tREFI depends on TOPER. 2. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. 3. Reserved settings are not allowed. 66 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Table 51: DDR3-1066 Speed Bins DDR3-1066 Speed Bin -187E -187 CL-tRCD-tRP 7-7-7 8-8-8 Parameter Symbol Min Max Min Max Units RCD 13.125 - 15 - ns PRECHARGE command period t RP 13.125 - 15 - ns ACTIVATE-to-ACTIVATE or REFRESH command period t RC 50.625 - 52.5 - ns tRAS 37.5 60ms 37.5 60ms ns 1 3.0 3.3 3.0 3.3 ACTIVATE to internal READ or WRITE delay time ACTIVATE-to-PRECHARGE command period CL = 5 CL = 6 CL = 7 CL = 8 t CWL = 5 tCK (AVG) CWL = 6 tCK (AVG) CWL = 5 tCK (AVG) CWL = 6 tCK (AVG) Reserved CWL = 5 tCK (AVG) Reserved CWL = 6 tCK (AVG) CWL = 5 tCK (AVG) CWL = 6 tCK (AVG) Supported CL settings Reserved 2.5 1.875 Reserved PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 2, 3 3 ns 2 Reserved ns 2, 3 Reserved ns 3 Reserved ns 2, 3 Reserved ns 3 <2.5 ns 2 2.5 3.3 1.875 <2.5 5, 6, 7, 8 5, 6, 8 CK 5, 6 5, 6 CK Supported CWL settings Notes: <2.5 1.875 ns ns Reserved 3.3 Notes 1. tREFI depends on TOPER. 2. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. 3. Reserved settings are not allowed. 67 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Table 52: DDR3-1333 Speed Bins DDR3-1333 Speed Bin -15E -15 CL-tRCD-tRP 9-9-9 10-10-10 Parameter Symbol Min Max Min Max Units RCD 13.125 - 15 - ns PRECHARGE command period t RP 13.125 - 15 - ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 49.5 - 51 - ns ACTIVATE-to-PRECHARGE command period tRAS 36 60ms 36 60ms ns 1 3.0 3.3 3.0 3.3 ns 2, 3 ns 3 ns 2 ACTIVATE to internal READ or WRITE delay time CL = 5 CL = 6 CL = 7 CL = 8 CL = 9 CL = 10 t Notes CWL = 5 tCK (AVG) CWL = 6, 7 tCK (AVG) CWL = 5 tCK (AVG) CWL = 6 tCK (AVG) Reserved Reserved ns 2, 3 CWL = 7 tCK (AVG) Reserved Reserved ns 3 CWL = 5 tCK (AVG) Reserved Reserved ns 3 CWL = 6 tCK (AVG) Reserved ns 2, 3 CWL = 7 tCK (AVG) Reserved Reserved ns 2, 3 CWL = 5 tCK (AVG) Reserved Reserved ns 3 CWL = 6 tCK (AVG) ns 2 CWL = 7 tCK (AVG) Reserved Reserved ns 2, 3 CWL = 5, 6 tCK (AVG) Reserved Reserved ns 3 CWL = 7 tCK (AVG) Reserved ns 2, 3 CWL = 5, 6 tCK (AVG) Reserved ns 3 CWL = 7 tCK (AVG) ns CK 2 Supported CL settings Reserved 2.5 PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN <2.5 1.875 <2.5 <1.875 Reserved 1.5 <1.875 5, 6, 7, 8, 9, 10 Supported CWL settings Notes: 3.3 1.875 1.5 Reserved 5, 6, 7 2.5 3.3 1.875 <2.5 1.5 <1.875 5, 6, 8, 10 5, 6, 7 CK 1. tREFI depends on TOPER. 2. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. 3. Reserved settings are not allowed. 68 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Table 53: DDR3-1600 Speed Bins DDR3-1600 Speed Bin CL-tRCD-tRP Parameter Symbol -125E -125 10-10-10 11-11-11 Min Max Min Max Units RCD 12.5 - 13.125 - ns PRECHARGE command period t RP 12.5 - 13.125 - ns ACTIVATE-to-ACTIVATE or REFRESH command period t RC 47.5 - 48.75 - ns tRAS 35 60ms 35 60ms ns 1 3.3 3.0 ACTIVATE to internal READ or WRITE delay time ACTIVATE-to-PRECHARGE command period CL = 5 CL = 6 CL = 7 CL = 8 CL = 9 CL = 10 CL = 11 t CWL = 5 tCK (AVG) CWL = 6, 7, 8 tCK (AVG) CWL = 5 tCK (AVG) CWL = 6 tCK (AVG) Reserved CWL = 7, 8 tCK (AVG) CWL = 5 tCK (AVG) CWL = 6 tCK (AVG) CWL = 7 tCK (AVG) Reserved CWL = 8 tCK (AVG) CWL = 5 tCK (AVG) CWL = 6 tCK (AVG) CWL = 7 tCK (AVG) Reserved CWL = 8 tCK (AVG) CWL = 5, 6 tCK (AVG) CWL = 7 tCK (AVG) CWL = 8 tCK (AVG) CWL = 5, 6 tCK (AVG) CWL = 7 tCK (AVG) 1.5 <1.875 CWL = 8 tCK (AVG) 1.25 <1.5 CWL = 5, 6, 7 tCK (AVG) tCK (AVG) CWL = 8 Supported CL settings Supported CWL settings Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 2.5 ns 2, 3 ns 3 ns 2 Reserved ns 2, 3 Reserved Reserved ns 3 Reserved Reserved ns 3 ns 2, 3 Reserved ns 2, 3 Reserved Reserved ns 3 Reserved Reserved ns 3 ns 2 Reserved ns 2, 3 Reserved Reserved ns 2, 3 Reserved Reserved ns 3 ns 2, 3 Reserved ns 2, 3 Reserved ns 3 ns 2 Reserved ns 2, 3 Reserved Reserved ns 3 1.25 <1.5 5, 6, 7, 8, 9, 10, 11 1.25 <1.5 5, 6, 7, 8, 9, 10, 11 ns CK 2 5, 6, 7, 8 5, 6, 7, 8 CK Reserved 2.5 Reserved 3.3 1.875 1.875 1.5 3.3 Notes <2.5 <2.5 <1.875 Reserved Reserved 2.5 3.3 1.875 1.875 1.5 1.5 <2.5 <2.5 <1.875 <1.875 1. tREFI depends on TOPER. 2. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. 3. Reserved settings are not allowed. 69 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN Table 54: Electrical Characteristics and AC Operating Conditions (Sheet 1 of 6) Notes: 1-8 apply to the entire table; notes appear on page 76 DDR3-800 Parameter Symbol Min tCKDLL_DIS 8 8 DDR3-1066 Max Min Max DDR3-1333 Min Max DDR3-1600 Min Max Units Notes Clock Timing TC = 0C to 85C TC = >85C to 95C Clock period average: DLL enable mode High pulse width average Low pulse width average Clock period jitter DLL locked DLL locking Clock absolute period Clock absolute high pulse width Clock period average: DLL disable mode Clock absolute low pulse width Cycle-to-cycle jitter 70 Cumulative error across (AVG) (AVG) tCL (AVG) tJITPER tJITPER, LCK tCK(ABS) tCH (ABS) tCL (ABS) 0.43 tJITCC tJITCC, LCK tERR 2PER tERR 3PER tERR 4PER tERR 5PER tERR 6PER tERR 7PER tERR 8PER tERR 9PER tERR 10PER tERR 11PER tERR 12PER tERR nPER - 0.43 200 180 -147 -175 -194 -209 -222 -232 -241 -249 -257 -263 -269 - 180 160 147 175 194 209 222 232 241 249 257 263 269 0.43 - 0.43 160 140 -132 132 -118 118 -103 -157 157 -140 140 -122 -175 175 -155 155 -136 -188 188 -168 168 -147 -200 200 -177 177 -155 -209 209 -186 186 -163 -217 217 -193 193 -169 -224 224 -200 200 -175 -231 231 -205 205 -180 -237 237 -210 210 -184 -242 242 -215 215 -188 tERRnPER MIN = (1 + 0.68ln[n]) x tJITPER MIN tERRnPER MAX = (1 + 0.68ln[n]) x tJITPER MAX - 140 120 103 122 136 147 155 163 169 175 180 184 188 ns ns ns CK CK ps ps ps tCK (AVG) tCK (AVG) ps ps ps ps ps ps ps ps ps ps ps ps ps ps 9, 42 42 10, 11 12 12 13 13 14 15 16 16 17 17 17 17 17 17 17 17 17 17 17 17 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. DLL locked DLL locking 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles 9 cycles 10 cycles 11 cycles 12 cycles n = 13, 14 . . . 49, 50 cycles tCK tCH 7,800 8 7,800 8 7,800 8 7,800 3,900 8 3,900 8 3,900 8 3,900 See "Speed Bin Tables" on page 66 for tCK range allowed 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 -100 100 -90 90 -80 80 -70 70 -90 90 -80 80 -70 70 -60 60 MIN = tCK (AVG) MIN + tJITPER MIN; MAX = tCK (AVG) MAX + tJITPER MAX 0.43 - 0.43 - 0.43 - 0.43 - PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN Table 54: Electrical Characteristics and AC Operating Conditions (Sheet 2 of 6) Notes: 1-8 apply to the entire table; notes appear on page 76 DDR3-800 Parameter Symbol Min tDS 75 250 125 275 150 250 600 Max DDR3-1066 Min DDR3-1333 DDR3-1600 Max Min Max Min Max Units Notes - - - - - - - - - 30 180 65 165 400 - - - - - - - - - 10 160 45 145 360 - - - - - - - ps ps ps ps ps ps ps 150 - - 0.38 125 - - 0.38 100 - tCK 21 22, 23 22, 23 DQ Input Timing Data setup time to DQS, DQS# Base (specification) VREF @ 1 V/ns Data setup time to Base (specification) DQS, DQS# VREF @ 1 V/ns Data hold time from Base (specification) DQS, DQS# VREF @ 1 V/ns Minimum data pulse width AC175 tDS AC150 tDH AC100 tDIPW - - - - - - - 25 200 75 250 100 200 490 18, 19 19, 20 18, 19 19, 20 18, 19 19, 20 41 DQ Output Timing DQS, DQS# to DQ skew, per access DQ output hold time from DQS, DQS# DQ Low-Z time from CK, CK# DQ High-Z time from CK, CK# tDQSQ tQH tLZ tHZ (DQ) (DQ) - 0.38 -800 - 200 - 400 400 - 0.38 -600 - ps 71 -500 - 250 250 -450 - 225 225 0.25 0.55 0.55 - - - - -0.25 0.45 0.45 0.2 0.2 0.9 0.3 0.25 0.55 0.55 - - - - -0.27 0.45 0.45 0.18 0.18 0.9 0.3 0.27 0.55 0.55 - - - - CK CK CK CK CK CK CK 25 DQ Strobe Input Timing DQS, DQS# rising to CK, CK# rising DQS, DQS# differential input low pulse width DQS, DQS# differential input high pulse width DQS, DQS# falling setup to CK, CK# rising DQS, DQS# falling hold from CK, CK# rising DQS, DQS# differential WRITE preamble DQS, DQS# differential WRITE postamble tDQSS tDQSL tDQSH tDSS tDSH tWPRE tWPST -0.25 0.45 0.45 0.2 0.2 0.9 0.3 0.25 0.55 0.55 - - - - -0.25 0.45 0.45 0.2 0.2 0.9 0.3 25 25 DQ Strobe Output Timing DQS, DQS# rising to/from rising CK, CK# DQS, DQS# rising to/from rising CK, CK# when DLL is disabled DQS, DQS# differential output high time DQS, DQS# differential output low time DQS, DQS# Low-Z time (RL - 1) DQS, DQS# High-Z time (RL + BL/2) DQS, DQS# differential READ preamble DQS, DQS# differential READ postamble tDQSCK tDQSCK -400 1 400 10 -300 1 300 10 -255 1 255 10 -225 1 225 10 ps ns 23 26 DLL_DIS tQSH tQSL tLZ (DQS) tHZ (DQS) t RPRE t RPST 0.38 0.38 -800 - 0.9 0.3 - - 400 400 Note 24 Note 27 0.38 0.38 -600 - 0.9 0.3 - - 300 300 Note 24 Note 27 0.40 0.40 -500 - 0.9 0.3 - - 250 250 Note 24 Note 27 0.40 0.40 -450 - 0.9 0.3 - - 225 225 Note 24 Note 27 CK CK ps ps CK CK 21 21 22, 23 22, 23 23, 24 23, 27 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 300 300 (AVG) ps ps PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN Table 54: Electrical Characteristics and AC Operating Conditions (Sheet 3 of 6) Notes: 1-8 apply to the entire table; notes appear on page 76 DDR3-800 Parameter Symbol Min Max DDR3-1066 Min Max DDR3-1333 Min Max DDR3-1600 Min Max Units Notes Command and Address Timing DLL locking time CTRL, CMD, ADDR setup to CK,CK# 72 Delay from start of internal WRITE transaction to internal READ command READ-to-PRECHARGE time CAS#-to-CAS# command delay Auto precharge write recovery + precharge time MODE REGISTER SET command cycle time MODE REGISTER SET command update delay MULTIPURPOSE REGISTER READ burst end to mode register set for multipurpose register exit CK ps ps ps ps ps ps ps ns ns ns ns CK 28 29, 30 20, 30 29, 30 20, 30 29, 30 20, 30 41 31 31 31, 32 31 31 tWR 512 - 512 - 512 - 125 - 65 - 45 - 300 - 240 - 220 - 275 - 190 - 170 - 425 - 340 - 320 - 200 - 140 - 120 - 300 - 240 - 220 - 780 - 620 - 560 - See "Speed Bin Tables" on page 66 for tRCD See "Speed Bin Tables" on page 66 for tRP See "Speed Bin Tables" on page 66 for tRAS See "Speed Bin Tables" on page 66 for tRC MIN = greater of MIN = greater of MIN = greater of MIN = greater of 4CK or 10ns 4CK or 7.5ns 4CK or 6ns 4CK or 6ns MIN = greater of 4CK or 10ns MIN = greater of 4CK or 7.5ns 40 - 37.5 - 30 - 30 - 50 - 50 - 45 - 40 - MIN = 15ns; MAX = n/a CK ns ns ns tWTR MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31 31 31 31, 32, 33 31, 34 tRTP MIN = greater of 4CK or 7.5ns; MAX = n/a MIN = 4CK; MAX = n/a MIN = WR + tRP/tCK (AVG); MAX = n/a CK CK CK MIN = 4CK; MAX = n/a MIN = greater of 12CK or 15ns; MAX = n/a MIN = 1CK; MAX = n/a CK CK CK tIS AC175 tIS AC150 tIH DC100 tIPW tRCD tRP tRAS tRC tRRD tFAW tCCD tDAL tMRD tMOD tMPRR 512 200 375 350 500 275 375 900 - - - - - - - - 31, 32 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Base (specification) VREF @ 1 V/ns CTRL, CMD, ADDR Base (specification) setup to CK,CK# VREF @ 1 V/ns CTRL, CMD, ADDR Base (specification) hold from CK,CK# VREF @ 1 V/ns Minimum CTRL, CMD, ADDR pulse width ACTIVATE to internal READ or WRITE delay PRECHARGE command period ACTIVATE-to-PRECHARGE command period ACTIVATE-to-ACTIVATE command period ACTIVATE-to1KB page size ACTIVATE minimum command period 2KB page size Four ACTIVATE windows for 1KB page size Four ACTIVATE windows for 2KB page size Write recovery time tDLLK PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN Table 54: Electrical Characteristics and AC Operating Conditions (Sheet 4 of 6) Notes: 1-8 apply to the entire table; notes appear on page 76 DDR3-800 Parameter Symbol Min Max tZQINIT 512 - tZQOPER 256 64 - - DDR3-1066 Min DDR3-1333 DDR3-1600 Max Min Max Min Max Units Notes 512 - 512 - 512 - CK 256 64 - - 256 64 - - 256 64 - - CK CK Calibration Timing ZQCL command: Long POWER-UP and RESET calibration time operation Normal operation ZQCS command: Short calibration time tZQCS Initialization and Reset Timing Exit reset from CKE HIGH to a valid command Begin power supply ramp to power supplies stable RESET# LOW to power supplies stable RESET# LOW to I/O and RTT High-Z tXPR MIN = greater of 5CK or tRFC + 10ns; MAX = n/a MIN = n/a; MAX = 200 CK ms MIN = 0; MAX = 200 MIN = n/a; MAX = 20 ms ns tRFC MIN = 110; MAX = 9 x tREFI (REFRESH-to-REFRESH command period) ns - 64 (1X) 32 (2X) 7.8 (64ms/8,192) 3.9 (32ms/8,192) ms ms s s tXS MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK tXSDLL MIN = tDLLK (MIN); MAX = n/a CK tCKESR MIN = tCKE (MIN) + CK; MAX = n/a CK tCKSRE MIN = greater of 5CK or 10ns; MAX = n/a CK tCKSRX MIN = greater of 5CK or 10ns; MAX = n/a CK tVDDPR tRPS tIOz 35 Refresh Timing 73 tREFI 36 36 36 36 Self Refresh Timing Exit self refresh to commands not requiring a locked DLL Exit self refresh to commands requiring a locked DLL Minimum CKE low pulse width for self refresh entry to self refresh exit timing Valid clocks after self refresh entry or powerdown entry Valid clocks before self refresh exit, powerdown exit, or reset exit 28 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. REFRESH-to-ACTIVATE or REFRESH command period Maximum refresh TC 85C period TC > 85C Maximum average TC 85C periodic refresh TC > 85C PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN Table 54: Electrical Characteristics and AC Operating Conditions (Sheet 5 of 6) Notes: 1-8 apply to the entire table; notes appear on page 76 DDR3-800 Parameter Symbol Min Max DDR3-1066 Min Max DDR3-1333 Min Max DDR3-1600 Min Max Units Notes Power-Down Timing CKE MIN pulse width Command pass disable delay Power-down entry to power-down exit timing Begin power-down period prior to CKE registered HIGH Power-down entry period: ODT either synchronous or asynchronous Power-down exit period: ODT either synchronous or asynchronous tCKE (MIN) Greater of 3CK or Greater of 3CK or Greater of 3CK or Greater of 3CK or 7.5ns 5.625ns 5.625ns 5ns tCPDED MIN = 1; MAX = n/a tPD MIN = tCKE (MIN); MAX = 60ms tANPD WL - 1CK PDE Greater of tANPD or tRFC - REFRESH command to CKE LOW time tANPD PDX + tXPDLL CK CK CK CK CK CK Power-Down Entry Minimum Timing tACTPDEN 74 MIN = 1 MIN = 1 CK CK MIN = 1 MIN = tMOD (MIN) MIN = RL + 4 + 1 CK CK CK MIN = WL + 4 + tWR/tCK (AVG) CK MIN = WL + 2 + tWR/tCK (AVG) MIN = WL + 4 + WR + 1 CK CK MIN = WL + 2 + WR + 1 CK 37 Power-Down Exit Timing DLL on, any valid command, or DLL off to commands not requiring locked DLL Precharge power-down with DLL off to commands requiring a locked DLL tXP tXPDLL MIN = greater of 3CK or 7.5ns; MIN = greater of 3CK or 6ns; MAX = n/a MAX = n/a MIN = greater of 10CK or 24ns; MAX = n/a CK CK 28 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. ACTIVATE command to power-down entry tPRPDEN PRECHARGE/PRECHARGE ALL command to power-down entry tREFPDEN REFRESH command to power-down entry tMRSPDEN MRS command to power-down entry READ/READ with auto precharge command to tRDPDEN power-down entry tWRPDEN WRITE command to BL8 (OTF, MRS) power-down entry BC4OTF tWRPDEN BC4MRS t WRITE with auto BL8 (OTF, MRS) WRAPDEN precharge command BC4OTF tWRAPDEN to power-down entry BC4MRS PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN Table 54: Electrical Characteristics and AC Operating Conditions (Sheet 6 of 6) Notes: 1-8 apply to the entire table; notes appear on page 76 DDR3-800 Parameter Symbol RTT synchronous turn-on delay RTT synchronous turn-off delay RTT turn-on from ODTL on reference RTT turn-off from ODTL off reference Asynchronous RTT turn-on delay (power-down with DLL off) Asynchronous RTT turn-off delay (power-down with DLL off) ODT HIGH time with WRITE command and BL8 ODT HIGH time without WRITE command or with WRITE command and BC4 ODTL on ODTL off tAON tAOF tAONPD Min Max DDR3-1066 Min Max DDR3-1333 Min Max DDR3-1600 Min Max Units Notes ODT Timing -400 0.3 400 0.7 CWL + AL - 2CK CWL + AL - 2CK -300 300 -250 0.3 0.7 0.3 MIN = 2; MAX = 8.5 250 0.7 -225 0.3 225 0.7 CK CK ps CK ns 38 40 23, 38 39, 40 38 40 tAOFPD MIN = 2; MAX = 8.5 ns ODTH8 MIN = 6; MAX = n/a CK ODTH4 MIN = 4; MAX = n/a CK WL - 2CK 4CK + ODTL off 6CK + ODTL off 0.7 0.3 Dynamic ODT Timing 75 RTT_NOM-to-RTT_WR change skew RTT_WR-to-RTT_NOM change skew - BC4 RTT_WR-to-RTT_NOM change skew - BL8 RTT dynamic change skew ODTLCNW ODTLCNW4 ODTLCNW8 tADC 0.3 0.7 0.3 0.7 0.3 0.7 CK CK CK CK 39 First DQS, DQS# rising edge DQS, DQS# delay Write leveling setup from rising CK, CK# crossing to rising DQS, DQS# crossing Write leveling hold from rising DQS, DQS# crossing to rising CK, CK# crossing Write leveling output delay Write leveling output error tWLS 40 25 325 - - - 40 25 245 - - - 40 25 195 - - - 40 25 165 - - - CK CK ps tWLH 325 - 245 - 195 - 165 - ps tWLO 0 0 9 2 0 0 9 2 0 0 9 2 0 0 7.5 2 ns ns tWLDQSEN tWLOE 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Write Leveling Timing tWLMRD 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN Parameters are applicable with 0C TC +95C and VDD/VDDQ = +1.5V 0.075V. All voltages are referenced to VSS. Output timings are only valid for RON34 output buffer selection. Unit "tCK (AVG)" represents the actual tCK (AVG) of the input clock under operation. Unit "CK" represents one clock cycle of the input clock, counting the actual clock edges. AC timing and IDD tests may use a VIL-to-VIH swing of up to 900mV in the test environment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the AC/DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum slew rate for the input signals used to test the device is 1 V/ns for singleended inputs and 2 V/ns for differential inputs in the range between VIL(AC) and VIH(AC). All timings that use time-based values (ns, s, ms) should use tCK (AVG) to determine the correct number of clocks (Table 54 on page 70 uses "CK" or "tCK [AVG]" interchangeably). In the case of noninteger results, all minimum limits are to be rounded up to the nearest whole integer, and all maximum limits are to be rounded down to the nearest whole integer. The use of "strobe" or "DQSDIFF " refers to the DQS and DQS# differential crossing point when DQS is the rising edge. The use of "clock" or "CK" refers to the CK and CK# differential crossing point when CK is the rising edge. This output load is used for all AC timing (except ODT reference timing) and slew rates. The actual test load may be different. The output signal voltage reference point is VDDQ/2 for single-ended signals and the crossing point for differential signals (see Figure 31 on page 63). When operating in DLL disable mode, Micron does not warrant compliance with normal mode timings or functionality. The clock's tCK (AVG) is the average clock over any 200 consecutive clocks and tCK(AVG) MIN is the smallest clock rate allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20-60 kHz with an additional 1% of tCK (AVG) as a long-term jitter component; however, the spread-spectrum may not use a clock rate below tCK (AVG) MIN. The clock's tCH (AVG) and tCL (AVG) are the average half clock period over any 200 consecutive clocks and is the smallest clock half period allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. The period jitter (tJITPER) is the maximum deviation in the clock period from the average or nominal clock. It is allowed in either the positive or negative direction. t CH(ABS) is the absolute instantaneous clock high pulse width as measured from one rising edge to the following falling edge. t CL(ABS) is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising edge. The cycle-to-cycle jitter (tJITCC) is the amount the clock period can deviate from one cycle to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL locking time. 76 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables 17. The cumulative jitter error (tERRnPER), where n is the number of clocks between 2 and 50, is the amount of clock time allowed to accumulate consecutively away from the average clock over n number of clock cycles. t 18. DS (base) and tDH (base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns differential DQS, DQS# slew rate. 19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transition edge to its respective data strobe signal (DQS, DQS#) crossing. 20. The setup and hold times are listed converting the base specification values (to which derating tables apply) to VREF when the slew rate is 1 V/ns. These values, with a slew rate of 1 V/ns, are for reference only. 21. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJITPER (larger of tJITPER(MIN) or tJITPER(MAX) of the input clock (output deratings are relative to the SDRAM input clock). 22. Single-ended signal parameter. 23. The DRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by the actual jitter error when input clock jitter is present, even when within specification. This results in each parameter becoming larger. The following parameters are required to be derated by subtracting tERR10PER (MAX): t DQSCK (MIN), tLZ (DQS) MIN, tLZ (DQ) MIN, and tAON (MIN). The following parameters are required to be derated by subtracting tERR10PER (MIN): t DQSCK (MAX), tHZ (MAX), tLZ (DQS) MAX, tLZ (DQ) MAX, and tAON (MAX). The parameter tRPRE (MIN) is derated by subtracting tJITPER (MAX), while tRPRE (MAX) is derated by subtracting tJITPER (MIN). 24. The maximum preamble is bound by tLZDQS (MAX). 25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its respective clock signal (CK, CK#) crossing. The specification values are not affected by the amount of clock jitter applied, as these are relative to the clock signal crossing. These parameters should be met whether clock jitter is present. 26. The tDQSCK DLL_DIS parameter begins CL + AL - 1 cycles after the READ command. 27. The maximum postamble is bound by tHZDQS (MAX). 28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT commands. In addition, after any change of latency tXPDLL, timing must be met. 29. tIS (base) and tIH (base) values are for a single-ended 1 V/ns control/command/ address slew rate and 2 V/ns CK, CK# differential slew rate. 30. These parameters are measured from a command/address signal transition edge to its respective clock (CK, CK#) signal crossing. The specification values are not affected by the amount of clock jitter applied as the setup and hold times are relative to the clock signal crossing that latches the command/address. These parameters should be met whether clock jitter is present. 31. For these parameters, the DDR3 SDRAM device supports tnPARAM (nCK) = RU(tPARAM [ns]/tCK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP (nCK) = RU(tRP/tCK[AVG]) if all input clock jitter specifications are met. This means for DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP = RU(tRP/tCK[AVG]) = 6 as long as the input clock jitter specifications are met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are valid even if six clocks are less than 15ns due to input clock jitter. 32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the internal PRECHARGE command until tRAS (MIN) has been satisfied. 33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for tWR. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 77 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables 34. The start of the write recovery time is defined as follows: - For BL8 (fixed by MRS and OTF): Rising clock edge four clock cycles after WL - For BC4 (OTF): Rising clock edge four clock cycles after WL - For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL 35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in excessive current, depending on bus activity. 36. The refresh period is 64ms when TC is less than or equal to 85oC. This equates to an average refresh rate of 7.8125s. However, nine REFRESH commands should be asserted at least once every 70.3s. When TC is greater than 85oC, the refresh period is 32ms. 37. Although CKE is allowed to be registered LOW after a REFRESH command when t REFPDEN (MIN) is satisfied, there are cases where additional time such as t XPDLL (MIN) is required. 38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT reference load is shown in Figure 23 on page 52. 39. Half-clock output parameters must be derated by the actual tERR10PER and tJITDTY when input clock jitter is present. This results in each parameter becoming larger. The parameters tADC (MIN) and tAOF (MIN) are each required to be derated by subtracting both tERR10PER (MAX) and tJITDTY (MAX). The parameters tADC (MAX) and t AOF (MAX) are required to be derated by subtracting both tERR10PER (MAX) and t JITDTY (MAX). 40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT turn-off time maximum is when the DRAM buffer is in High-Z. The ODT reference load is shown in Figure 24 on page 54. This output load is used for ODT timings (see Figure 31 on page 63). 41. Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the consecutive crossing of VREF(DC). 42. Should the clock rate be larger than tRFC (MIN), an AUTO REFRESH command should have at least one NOP command between it and another AUTO REFRESH command. Additionally, if the clock rate is slower than 40ns (25 MHz) all REFRESH commands should be followed by a PRECHARGE All command. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 78 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Command and Address Setup, Hold, and Derating The total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS (base) and tIH (base) values (see Table 55; values come from Table 54 on page 70) to the tIS and tIH derating values (see Table 56 on page 80 and Table 57 on page 80), respectively. Example: tIS (total setup time) = tIS (base) + tIS. For a valid transition, the input signal has to remain above/below VIH(AC)/VIL(AC) for some time tVAC (see Table 57 on page 80). Although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transition), a valid input signal is still required to complete the transition and to reach VIH(AC)/ VIL(AC) (see Figure 15 on page 44 for input signal requirements). For slew rates which fall between the values listed in Table 57 on page 80 and Table 58 on page 81, the derating values may be obtained by linear interpolation. Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC) MIN. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between the shaded "VREF(DC)-to-AC region," use the nominal slew rate for derating value (see Figure 34 on page 82). If the actual signal is later than the nominal slew rate line anywhere between the shaded "VREF(DC)-to-AC region," the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for derating value (see Figure 36 on page 84). Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF(DC). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between the shaded "DC-to-VREF(DC) region," use the nominal slew rate for derating value (see Figure 35 on page 83). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded "DC-to-VREF(DC) region," the slew rate of a tangent line to the actual signal from the DC level to the VREF(DC) level is used for derating value (see Figure 37 on page 85). Table 55: Command and Address Setup and Hold Values Referenced at 1 V/ns - AC/DC-Based Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Reference IS (base) AC175 (base) AC150 tIH (base) DC100 200 350 275 125 275 200 65 190 140 45 170 120 ps ps ps VIH(AC)/VIL(AC) VIH(AC)/VIL(AC) VIH(DC)/VIL(DC) t tIS PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 79 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Table 56: Derating Values for tIS/tIH - AC175/DC100-Based tIS, tIH Derating (ps) - AC/DC-Based AC175 Threshold: VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV CK, CK# Differential Slew Rate CMD/ ADDR Slew Rate V/ns t IS t IH t IS t IH t IS t IH t IS t IH t IS t IH t IH t IH t IS t IH tIS tIH 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 88 59 0 -2 -6 -11 -17 -35 -62 50 34 0 -4 -10 -16 -26 -40 -60 88 59 0 -2 -6 -11 -17 -35 -62 50 34 0 -4 -10 -16 -26 -40 -60 88 59 0 -2 -6 -11 -17 -35 -62 50 34 0 -4 -10 -16 -26 -40 -60 96 67 8 6 2 -3 -9 -27 -54 58 42 8 4 -2 -8 -18 -32 -52 104 75 16 14 10 5 -1 -19 -46 66 50 16 12 6 0 -10 -24 -44 112 83 24 22 18 13 7 -11 -38 74 58 24 20 14 8 -2 -16 -36 120 91 32 30 26 21 15 -2 -30 84 68 34 30 24 18 8 -6 -26 128 99 40 38 34 29 23 5 -22 100 84 50 46 40 34 24 10 -10 Table 57: 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns Derating Values for tIS/tIH - AC150/DC100-Based tIS, tIH Derating (ps) - AC/DC-Based AC150 Threshold: VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV CK, CK# Differential Slew Rate CMD/ ADDR Slew Rate V/ns tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIH tIH tIS tIH tIS tIH 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 75 50 0 0 0 0 -1 -10 -25 50 34 0 -4 -10 -16 -26 -40 -60 75 50 0 0 0 0 -1 -10 -25 50 34 0 -4 -10 -16 -26 -40 -60 75 50 0 0 0 0 -1 -10 -25 50 34 0 -4 -10 -16 -26 -40 -60 83 58 8 8 8 8 7 -2 -17 58 42 8 4 -2 -8 -18 -32 -52 91 66 16 16 16 16 15 6 -9 66 50 16 12 6 0 -10 -24 -44 99 74 24 24 24 24 23 14 -1 74 58 24 20 14 8 -2 -16 -36 107 82 32 32 32 32 31 22 7 84 68 34 30 24 18 8 -6 -26 115 90 40 40 40 40 39 30 15 100 84 50 46 40 34 24 10 -10 4.0 V/ns PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 3.0 V/ns 2.0 V/ns 1.8 V/ns 80 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Table 58: Minimum Required Time tVAC Above VIH(AC) for Valid Transition Below VIL(AC) t Slew Rate (V/ns) PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN VAC at 175mV (ps) t VAC at 150mV (ps) >2.0 75 175 2.0 57 170 1.5 50 167 1.0 38 163 0.9 34 162 0.8 29 161 0.7 22 159 0.6 13 155 0.5 0 150 <0.5 0 150 81 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Figure 34: Nominal Slew Rate and tVAC for tIS (Command and Address - Clock) tIS tIS tIH tIH CK CK# DQS# DQS VDDQ tVAC VIH(AC) MIN VREF to AC region VIH(DC) MIN Nominal slew rate VREF(DC) Nominal slew rate VIL(DC) MAX VREF to AC region VIL(DC) MAX tVAC VSS TF Setup slew rate falling signal = Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN TR VREF(DC) - VIL(AC) MAX TF Setup slew rate = rising signal VIH(AC) MIN - VREF(DC) TR 1. Both the clock and the strobe are drawn on different time scales. 82 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Figure 35: Nominal Slew Rate for tIH (Command and Address - Clock) tIS tIH tIS tIH CK CK# DQS# DQS VDDQ VIH(AC) MIN VIH(DC) MIN Nominal slew rate DC to VREF region VREF(DC) Nominal slew rate DC to VREF region VIL(DC) MAX VIL(AC) MAX VSS TF TR Hold slew rate rising signal = Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN VREF(DC) - VIL(DC) MAX TR Hold slew rate falling signal = VIH(DC) MIN - VREF(DC) TF 1. Both the clock and the strobe are drawn on different time scales. 83 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Figure 36: Tangent Line for tIS (Command and Address - Clock) tIS tIH tIS tIH CK CK# DQS# DQS VDDQ tVAC Nominal line VIH(AC) MIN VREF to AC region VIH(DC) MIN Tangent line VREF(DC) Tangent line VIL(DC) MAX VREF to AC region VIL(AC) MAX Nominal line tVAC TR VSS Setup slew rate rising signal = TF Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN Tangent line (VIH[DC] MIN - VREF[DC]) TR Tangent line (VREF[DC] - VIL[AC] MAX) Setup slew rate falling signal = TF 1. Both the clock and the strobe are drawn on different time scales. 84 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Figure 37: Tangent Line for tIH (Command and Address - Clock) tIS tIH tIS tIH CK CK# DQS# DQS VDDQ VIH(AC) MIN Nominal line VIH(DC ) MIN DC to VREF region Tangent line VREF(DC ) DC to VREF region Tangent line Nominal line VIL( DC ) MAX VIL( AC ) MAX VSS TR TR Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN Hold slew rate rising signal = Tangent line (VREF[DC] - VIL[DC] MAX) Hold slew rate falling signal = Tangent line (VIH[DC] MIN - VREF[DC]) TR TF 1. Both the clock and the strobe are drawn on different time scales. 85 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Data Setup, Hold, and Derating The total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS (base) and tDH (base) values (see Table 59; values come from Table 54 on page 70) to the tDS and tDH derating values (see Table 60 on page 87), respectively. Example: tDS (total setup time) = tDS (base) + tDS. For a valid transition, the input signal has to remain above/below VIH(AC)/VIL(AC) for some time tVAC (see Table 62 on page 88). Although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached VIH[AC]/VIL[AC]) at the time of the rising clock transition), a valid input signal is still required to complete the transition and to reach VIH/ VIL(AC). For slew rates which fall between the values listed in Table 61 on page 87, the derating values may obtained by linear interpolation. Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC) MIN. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between the shaded "VREF(DC)-to-AC region," use the nominal slew rate for derating value (see Figure 38 on page 89). If the actual signal is later than the nominal slew rate line anywhere between the shaded "VREF(DC)-to-AC region," the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for derating value (see Figure 40 on page 91). Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF(DC). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between the shaded "DC-to-VREF(DC) region," use the nominal slew rate for derating value (see Figure 39 on page 90). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded "DC-to-VREF(DC) region," the slew rate of a tangent line to the actual signal from the "DC-to-VREF(DC) region" is used for derating value (see Figure 41 on page 92). Table 59: Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) - AC/DC-Based Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Reference (base) AC175 (base) AC150 tDH (base) DC100 75 125 150 25 75 100 - 30 65 - 10 45 ps ps ps VIH(AC)/VIL(AC) VIH(AC)/VIL(AC) VIH(DC)/VIL(DC) tDS tDS PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 86 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Table 60: Derating Values for tDS/tDH - AC175/DC100-Based Shaded cells indicate slew rate combinations not supported tDS, tDH Derating (ps) - AC/DC-Based DQS, DQS# Differential Slew Rate DQ Slew Rate V/ns 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 Table 61: 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH 88 59 0 50 34 0 88 59 0 -2 50 34 0 -4 88 59 0 -2 -6 50 34 0 -4 -10 67 8 6 2 -3 42 8 4 -2 -8 16 14 10 5 -1 16 12 6 0 -10 22 18 13 7 -11 20 14 8 -2 -16 26 21 15 -2 -30 24 18 8 -6 -26 29 23 5 -22 34 24 10 -10 Derating Values for tDS/tDH - AC150/DC100-Based Shaded cells indicate slew rate combinations not supported tDS, tDH Derating (ps) - AC/DC-Based DQS, DQS# Differential Slew Rate DQ Slew Rate V/ns 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH 75 50 0 50 34 0 PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN 75 50 0 0 50 34 0 -4 75 50 0 0 0 50 34 0 -4 -10 58 8 8 8 8 42 8 4 -2 -8 87 16 16 16 16 15 16 12 6 0 -10 24 24 24 23 14 20 14 8 -2 -16 32 32 31 22 7 24 18 8 -6 -26 40 39 30 15 34 24 10 -10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Table 62: Required Time tVAC Above VIH(AC) (Below VIL[AC]) for Valid Transition t VAC at 175mV (ps) PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN t VAC at 150mV (ps) Slew Rate (V/ns) Min Min >2.0 75 175 2.0 57 170 1.5 50 167 1.0 38 163 0.9 34 162 0.8 29 161 0.7 22 159 0.6 13 155 0.5 0 150 <0.5 0 150 88 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Figure 38: Nominal Slew Rate and tVAC for tDS (DQ - Strobe) CK CK# DQS# DQS tDS tDS tDH tDH VDDQ tVAC VIH(AC) MIN VREF to AC region VIH(DC) MIN Nominal slew rate VREF(DC) Nominal slew rate VIL(DC) MAX VREF to AC region VIL(AC) MAX tVAC VSS TF Setup slew rate = falling signal Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN TR VREF(DC) - VIL(AC) MAX TF Setup slew rate = rising signal VIH(AC) MIN - VREF(DC) TR 1. Both the clock and the strobe are drawn on different time scales. 89 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Figure 39: Nominal Slew Rate for tDH (DQ - Strobe) CK CK# DQS# DQS tDS tDH tDS tDH VDDQ VIH(AC) MIN VIH(DC) MIN Nominal slew rate DC to VREF region VREF(DC) Nominal slew rate DC to VREF region VIL(DC) MAX VIL(AC) MAX VSS TF TR Hold slew rate = rising signal Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN VREF(DC) - VIL(DC) MAX TR Hold slew rate = falling signal VIH(DC) MIN - VREF(DC) TF 1. Both the clock and the strobe are drawn on different time scales. 90 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Figure 40: Tangent Line for tDS (DQ - Strobe) CK CK# DQS# DQS tDS tDH tDS tDH VDDQ Nominal line tVAC VIH(AC) MIN VREF to AC region VIH(DC) MIN Tangent line VREF(DC) Tangent line VIL(DC) MAX VREF to AC region VIL(AC) MAX Nominal line TR tVAC VSS TF Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN Setup slew rate rising signal = Tangent line (VIH[AC] MIN - VREF[DC]) Setup slew rate falling signal = Tangent line (VREF[DC] - VIL[AC] MAX) TR TF 1. Both the clock and the strobe are drawn on different time scales. 91 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Figure 41: Tangent Line for tDH (DQ - Strobe) CK CK# DQS# DQS tDS tDH tDS tDH VDDQ VIH(AC) MIN Nominal line VIH(DC) MIN DC to VREF region Tangent line VREF(DC) DC to VREF region Tangent line Nominal line VIL(DC) MAX VIL(AC) MAX VSS TR Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D3.fm - Rev G 2/09 EN TF Hold slew rate rising signal = Tangent line (VREF[DC] - VIL[DC] MAX) Hold slew rate falling signal = Tangent line (VIH[DC] MIN - VREF[DC]) TR TF 1. Both the clock and the strobe are drawn on different time scales. 92 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands Commands Truth Tables Table 63: Truth Table - Command Notes 1-5 apply to the entire table CKE Prev Next BA Symbol Cycle Cycle CS# RAS# CAS# WE# [2:0] Function An A12 A10 A[11, 9:0] Notes MODE REGISTER SET MRS H H L L L L BA REFRESH REF H H L L L H V V V V V Self refresh entry SRE H L L L L H V V V V V 6 Self refresh exit SRX L H H V V V V V V V V 6, 7 L H H H Single-bank PRECHARGE OP code PRE H H L L H L BA V V L V PRECHARGE all banks PREA H H L L H L V V V H V Bank ACTIVATE ACT H H L L H H BA WRITE WR H H L H L L BA BL8MRS, BC4MRS READ with auto precharge RFU V L CA 8 BC4OTF WRS4 H H L H L L BA RFU L L CA 8 BL8OTF WRS8 H H L H L L BA RFU H L CA 8 WRAP H H L H L L BA RFU V H CA 8 WRITE with BL8MRS, auto BC4MRS precharge BC4OTF READ Row address (RA) WRAPS4 H H L H L L BA RFU L H CA 8 BL8OTF WRAPS8 H H L H L L BA RFU H H CA 8 BL8MRS, BC4MRS RD H H L H L H BA RFU V L CA 8 BC4OTF RDS4 H H L H L H BA RFU L L CA 8 BL8OTF RDS8 H H L H L H BA RFU H L CA 8 BL8MRS, BC4MRS RDAP H H L H L H BA RFU V H CA 8 BC4OTF RDAPS4 H H L H L H BA RFU L H CA 8 BL8OTF RDAPS8 H H L H L H BA RFU H H CA 8 NO OPERATION NOP H H L H H H V V V V V 9 Device DESELECTED DES H H H X X X X X X X X 10 Power-down entry PDE H L V V V V V 6 V V V V V 6, 11 12 L H H H H V V V L H H H Power-down exit PDX L H H V V V ZQ CALIBRATION LONG ZQCL H H L H H L X X X H X ZQ CALIBRATION SHORT ZQCS H H L H H L X X X L X Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 1. Commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock. The MSB of BA, RA, and CA are device-density and configuration-dependent. 2. RESET# is LOW enabled and used only for asynchronous reset. Thus, RESET# must be held HIGH during any normal operation. 3. The state of ODT does not affect the states described in this table. 93 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands 4. Operations apply to the bank defined by the bank address. For MRS, BA selects one of four mode registers. 5. "V" means "H" or "L" (a defined logic level), and "X" means "Don't Care." 6. See Table 64 for additional information on CKE transition. 7. Self refresh exit is asynchronous. 8. Burst READs or WRITEs cannot be terminated or interrupted. MRS (fixed) and OTF BL/BC are defined in MR0. 9. The purpose of the NOP command is to prevent the DRAM from registering any unwanted commands. A NOP will not terminate an operation that is executing. 10. The DES and NOP commands perform similarly. 11. The power-down mode does not perform any REFRESH operations. 12. ZQ CALIBRATION LONG is used for either ZQINIT (first ZQCL command during initialization) or ZQOPER (ZQCL command after initialization). Table 64: Truth Table - CKE Notes 1-2 apply to the entire table; see Table 63 on page 93 for additional command details CKE Current State3 Previous Cycle4 (n - 1) Power-down Self refresh Present Cycle4 Command5 (n) (RAS#, CAS#, WE#, CS#) Action5 L L "Don't Care" Maintain power-down L H DES or NOP Power-down exit L L "Don't Care" Maintain self refresh L H DES or NOP Self refresh exit Bank(s) active H L DES or NOP Active power-down entry Reading H L DES or NOP Power-down entry Writing H L DES or NOP Power-down entry Precharging H L DES or NOP Power-down entry Refreshing H L DES or NOP Precharge power-down entry All banks idle H L DES or NOP Precharge power-down entry H L REFRESH Self refresh Notes: Notes 6 1. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 2. tCKE (MIN) means CKE must be registered at multiple consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the required number of registration clocks. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + tCKE (MIN) + tIH. 3. Current state = The state of the DRAM immediately prior to clock edge n. 4. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the previous clock edge. 5. COMMAND is the command registered at the clock edge (must be a legal command as defined in Table 63 on page 93). Action is a result of COMMAND. ODT does not affect the states described in this table and is not listed. 6. Idle state = All banks are closed, no data bursts are in progress, CKE is HIGH, and all timings from previous operations are satisfied. All self refresh exit and power-down exit parameters are also satisfied. DESELECT (DES) The DES command (CS# HIGH) prevents new commands from being executed by the DRAM. Operations already in progress are not affected. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 94 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands NO OPERATION (NOP) The NOP command (CS# LOW) prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ZQ CALIBRATION ZQ CALIBRATION LONG (ZQCL) The ZQCL command is used to perform the initial calibration during a power-up initialization and reset sequence (see Figure 50 on page 109). This command may be issued at any time by the controller depending on the system environment. The ZQCL command triggers the calibration engine inside the DRAM. After calibration is achieved, the calibrated values are transferred from the calibration engine to the DRAM I/O, which are reflected as updated RON and ODT values. The DRAM is allowed a timing window defined by either tZQINIT or tZQOPER to perform the full calibration and transfer of values. When ZQCL is issued during the initialization sequence, the timing parameter tZQINIT must be satisfied. When initialization is complete, subsequent ZQCL commands require the timing parameter tZQOPER to be satisfied. ZQ CALIBRATION SHORT (ZQCS) The ZQCS command is used to perform periodic calibrations to account for small voltage and temperature variations. The shorter timing window is provided to perform the reduced calibration and transfer of values as defined by timing parameter tZQCS. A ZQCS command can effectively correct a minimum of 0.5% RON and RTT impedance error within 64 clock cycles, assuming the maximum sensitivities specified in Table 41 on page 59 and Table 42 on page 60. ACTIVATE The ACTIVATE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA[2:0] inputs selects the bank, and the address provided on inputs A[n:0] selects the row. This row remains open (or active) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The address provided on inputs A[2:0] selects the starting column address depending on the burst length and burst type selected (see Table 69 on page 113 for additional information). The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. If auto precharge is not selected, the row will remain open for subsequent accesses. The value on input A12 (if enabled in the mode register) when the READ command is issued determines whether BC4 (chop) or BL8 is used. After a READ command is issued, the READ burst may not be interrupted. A summary of READ commands is shown in Table 65 on page 96. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 95 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands Table 65: READ Command Summary CKE Function READ Symbol Previous Next BA Cycle Cycle CS# RAS# CAS# WE# [3:0] An A12 A10 A[11, 9:0] V L CA BL8MRS, BC4MRS RD H L H L H BA RFU BC4OTF RDS4 H L H L H BA RFU L L CA BL8OTF RDS8 H L H L H BA RFU H L CA H L H L H BA RFU V H CA H L H L H BA RFU L H CA H L H L H BA RFU H H CA READ BL8MRS, BC4MRS RDAP with auto BC4OTF RDAPS4 precharge BL8OTF RDAPS8 WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA[2:0] inputs selects the bank. The value on input A10 determines whether or not auto precharge is used. The value on input A12 (if enabled in the MR) when the WRITE command is issued determines whether BC4 (chop) or BL8 is used. The WRITE command summary is shown in Table 66. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory. If the DM signal is registered HIGH, the corresponding data inputs will be ignored and a WRITE will not be executed to that byte/column location. Table 66: WRITE Command Summary CKE Prev Next BA Symbol Cycle Cycle CS# RAS# CAS# WE# [3:0] Function WRITE WRITE with auto precharge An A12 A10 A[11, 9:0] V L CA CA BL8MRS, BC4MRS WR H L H L L BA RFU BC4OTF WRS4 H L H L L BA RFU L L BL8OTF WRS8 H L H L L BA RFU H L CA BL8MRS, BC4MRS WRAP H L H L L BA RFU V H CA BC4OTF WRAPS4 H L H L L BA RFU L H CA BL8OTF WRAPS8 H L H L L BA RFU H H CA PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or in all banks. The bank(s) are available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued, except in the case of concurrent auto precharge. A READ or WRITE command to a different bank is allowed during concurrent auto precharge as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 determines whether one or all banks are precharged. In the case where only one bank is precharged, inputs BA[2:0] select the bank; otherwise, BA[2:0] are treated as "Don't Care." After a bank is precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is treated as a NOP if PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 96 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the precharge period is determined by the last PRECHARGE command issued to the bank. REFRESH REFRESH is used during normal operation of the DRAM and is analogous to CAS#before-RAS# (CBR) refresh or auto refresh. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "Don't Care" during a REFRESH command. The DRAM requires REFRESH cycles at an average interval of 7.8s (maximum when TC 85C or 3.9s MAX when TC 95C). The REFRESH period begins when the REFRESH command is registered and ends tRFC (MIN) later. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight REFRESH commands can be posted to any given DRAM, meaning that the maximum absolute interval between any REFRESH command and the next REFRESH command is nine times the maximum average interval refresh rate. Self refresh may be entered with up to eight REFRESH commands being posted. After exiting self refresh (when entered with posted REFRESH commands) additional posting of REFRESH commands is allowed to the extent the maximum number of cumulative posted REFRESH commands (both pre and post self refresh) does not exceed eight REFRESH commands. The posting limit of eight REFRESH commands is a JEDEC specification; however, as long as all the required number of REFRESH commands are issued within the refresh period (64ms), exceeding the eight posted REFRESH commands is allowed. Figure 42: Refresh Mode T0 T2 T1 CK# CK tCK T3 tCH T4 Ta1 Valid1 NOP1 PRE Tb0 Tb1 Valid1 Valid1 NOP1 NOP1 Tb2 tCL CKE Command Ta0 NOP1 NOP1 REF NOP1 REF2 Address ACT RA All banks A10 RA One bank Bank(s)3 BA[2:0] BA DQS, DQS#4 DQ4 DM4 tRP tRFC (MIN) tRFC2 Indicates A Break in Time Scale Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Don't Care 1. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH commands, but may be inactive at other times (see "Power-Down Mode" on page 153). 97 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands 2. The second REFRESH is not required but depicts two back-to-back REFRESH commands. 3. "Don't Care" if A10 is HIGH at this point; however, A10 must be HIGH if more than one bank is active (must precharge all active banks). 4. For operations shown, DM, DQ, and DQS signals are all "Don't Care"/High-Z. SELF REFRESH The SELF REFRESH command is used to retain data in the DRAM, even if the rest of the system is powered down. When in the self refresh mode, the DRAM retains data without external clocking. The self refresh mode is also a convenient method used to enable/ disable the DLL (see "DLL Disable Mode" on page 98) as well as to change the clock frequency within the allowed synchronous operating range (see "Input Clock Frequency Change" on page 101). All power supply inputs (including VREFCA and VREFDQ) must be maintained at valid levels upon entry/exit and during self refresh mode operation. All power supply inputs (including VREFCA and VREFDQ) must be maintained at valid levels upon entry/exit and during self refresh mode operation. VREFDQ may float or not drive VDDQ/2 while in the self refresh mode under certain conditions: * VSS < VREFDQ < VDD is maintained * VREFDQ is valid and stable prior to CKE going back HIGH * The first WRITE operation may not occur earlier than 512 clocks after VREFDQ is valid * All other self refresh mode exit timing requirements are met. DLL Disable Mode If the DLL is disabled by the mode register (MR1[0] can be switched during initialization or later), the DRAM is targeted, but not guaranteed, to operate similarly to the normal mode with a few notable exceptions: * The DRAM supports only one value of CAS latency (CL = 6) and one value of CAS WRITE latency (CWL = 6). * DLL disable mode affects the read data clock-to-data strobe relationship (tDQSCK), but not the read data-to-data strobe relationship (tDQSQ, tQH). Special attention is needed to line the read data up with the controller time domain when the DLL is disabled. * In normal operation (DLL on), tDQSCK starts from the rising clock edge AL + CL cycles after the READ command. In DLL disable mode, tDQSCK starts AL + CL - 1 cycles after the READ command. Additionally, with the DLL disabled, the value of tDQSCK could be larger than tCK. The ODT feature is not supported during DLL disable mode (including dynamic ODT). The ODT resistors must be disabled by continuously registering the ODT ball LOW by programming RTT_NOM MR1[9, 6, 2] and RTT_WR MR2[10, 9] to "0" while in the DLL disable mode. Specific steps must be followed to switch between the DLL enable and DLL disable modes due to a gap in the allowed clock rates between the two modes (tCK [AVG] MAX and tCK [DLL disable] MIN, respectively). The only time the clock is allowed to cross this clock rate gap is during self refresh mode. Thus, the required procedure for switching from the DLL enable mode to the DLL disable mode is to change frequency during self refresh (see Figure 43 on page 99): 1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is turned off, and RTT_NOM and RTT_WR are High-Z), set MR1[0] to "1" to disable the DLL. 2. Enter self refresh mode after tMOD has been satisfied. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 98 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands 3. After tCKSRE is satisfied, change the frequency to the desired clock rate. 4. Self refresh may be exited when the clock is stable with the new frequency for tCKSRX. After tXS is satisfied, update the mode registers with appropriate values. 5. The DRAM will be ready for its next command in the DLL disable mode after the greater of tMRD or tMOD has been satisfied. A ZQCL command should be issued with appropriate timings met as well. Figure 43: DLL Enable Mode to DLL Disable Mode T0 T1 Ta0 Ta1 Tb0 Tc0 Td0 Td1 Te0 Te1 Tf0 CK# CK Valid1 CKE Command MRS2 6 SRE3 NOP tMOD SRX4 NOP tCKSRE 7 tCKSRX8 NOP tXS MRS5 NOP Valid1 tMOD tCKESR ODT9 Valid1 Indicates a Break in Time Scale Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. Don't Care Any valid command. Disable DLL by setting MR1[0] to "1." Enter SELF REFRESH. Exit SELF REFRESH. Update the mode registers with the DLL disable parameters setting. Starting with the idle state, RTT is in the High-Z state. Change frequency. Clock must be stable tCKSRX. Static LOW in case RTT_NOM or RTT_WR is enabled; otherwise, static LOW or HIGH. A similar procedure is required for switching from the DLL disable mode back to the DLL enable mode. This also requires changing the frequency during self refresh mode (see Figure 44 on page 100). 1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is turned off, and RTT_NOM and RTT_WR are High-Z), enter self refresh mode. 2. After tCKSRE is satisfied, change the frequency to the new clock rate. 3. Self refresh may be exited when the clock is stable with the new frequency for tCKSRX. After tXS is satisfied, update the mode registers with the appropriate values. At a minimum, set MR1[0] to "0" to enable the DLL. Wait tMRD, then set MR0[8] to "1" to enable DLL RESET. 4. After another tMRD delay is satisfied, then update the remaining mode registers with the appropriate values. 5. The DRAM will be ready for its next command in the DLL enable mode after the greater of tMRD or tMOD has been satisfied. However, before applying any command or function requiring a locked DLL, a delay of tDLLK after DLL RESET must be satisfied. A ZQCL command should be issued with the appropriate timings met as well. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 99 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands Figure 44: DLL Disable Mode to DLL Enable Mode T0 Ta0 Ta1 Tb0 Tc0 Tc1 Td0 Te0 Tf0 Tg0 Th0 CK# CK CKE Valid tDLLK Command SRE1 NOP SRX2 NOP tCKSRE 7 tCKSRX9 8 MRS3 tXS MRS4 tMRD MRS5 Valid6 tMRD ODTL off + 1 x tCK tCKESR ODT10 Indicates a Break in Time Scale Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Don't Care Enter SELF REFRESH. Exit SELF REFRESH. Wait tXS, then set MR1[0] to "0" to enable DLL. Wait tMRD, then set MR0[8] to "1" to begin DLL RESET. Wait tMRD, update registers (CL, CWL, and write recovery may be necessary). Wait tMOD, any valid command. Starting with the idle state. Change frequency. Clock must be stable at least tCKSRX. Static LOW in case RTT_NOM or RTT_WR is enabled; otherwise, static LOW or HIGH. The clock frequency range for the DLL disable mode is specified by the parameter t CKDLL_DIS. Due to latency counter and timing restrictions, only CL = 6 and CWL = 6 are supported. DLL disable mode will affect the read data clock to data strobe relationship (tDQSCK) but not the data strobe to data relationship (tDQSQ, tQH). Special attention is needed to line up read data to the controller time domain. Compared to the DLL on mode where tDQSCK starts from the rising clock edge AL + CL cycles after the READ command, the DLL disable mode tDQSCK starts AL + CL - 1 cycles after the READ command (see Figure 45 on page 101). WRITE operations function similarly between the DLL enable and DLL disable modes; however, ODT functionality is not allowed with DLL disable mode. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 100 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands Figure 45: DLL Disable tDQSCK Timing T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Command READ NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Address Valid CK# CK RL = AL + CL = 6 (CL = 6, AL = 0) CL = 6 DQS, DQS# DLL on DI b DQ BL8 DLL on DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 RL (DLL disable) = AL + (CL - 1) = 5 tDQSCK (DLL_DIS) MIN DQS, DQS# DLL off DI b DQ BL8 DLL disable DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 DI b+3 DI b+4 DI b+5 DI b+6 tDQSCK (DLL_DIS) MAX DQS, DQS# DLL off DI b DQ BL8 DLL disable DI b+1 DI b+2 DI b+7 Transitioning Data Table 67: Don't Care READ Electrical Characteristics, DLL Disable Mode Parameter Access window of DQS from CK, CK# Symbol Min Max Units tDQSCK (DLL_DIS) 1 10 ns Input Clock Frequency Change When the DDR3 SDRAM is initialized, it requires the clock to be stable during most normal states of operation. This means that after the clock frequency has been set to the stable state, the clock period is not allowed to deviate except what is allowed for by the clock jitter and spread spectrum clocking (SSC) specifications. The input clock frequency can be changed from one stable clock rate to another under two conditions: self refresh mode and precharge power-down mode. Outside of these two modes, it is illegal to change the clock frequency. For the self refresh mode condition, when the DDR3 SDRAM has been successfully placed into self refresh mode and t CKSRE has been satisfied, the state of the clock becomes a "Don't Care." When the clock becomes a "Don't Care," changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting self refresh mode for the sole purpose of changing the clock frequency, the self refresh entry and exit specifications must still be met. The precharge power-down mode condition is when the DDR3 SDRAM is in precharge power-down mode (either fast exit mode or slow exit mode). Either ODT must be at a logic LOW or RTT_NOM and RTT_WR must be disabled via MR1 and MR2. This ensures RTT_NOM and RTT_WR are in an off state prior to entering precharge power-down mode, and CKE must be at a logic LOW. A minimum of tCKSRE must occur after CKE goes LOW before the clock frequency can change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade (tCK [AVG] MIN to tCK [AVG] MAX). During the input clock frequency change, CKE must be held at a stable LOW level. When the input clock frequency is changed, a stable clock must be provided to the DRAM tCKSRX before precharge power-down may be exited. After precharge power-down is exited and tXP has PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 101 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands been satisfied, the DLL must be reset via the MRS. Depending on the new clock frequency, additional MRS commands may need to be issued. During the DLL lock time, RTT_NOM and RTT_WR must remain in an off state. After the DLL lock time, the DRAM is ready to operate with a new clock frequency. This process is depicted in Figure 46. Figure 46: Change Frequency During Precharge Power-Down Previous clock frequency T0 T1 T2 New clock frequency Ta0 Tb0 Tc1 Tc0 Td0 Td1 Te0 Te1 CK# CK tCH tCL tCH tCH b tIS tCL b tCH b tCK b tCL b tCK b tCKSRX tCKSRE tCKE tIH CKE tIS tCPDED Command tCL b tCK b tCK tIH b NOP NOP NOP NOP NOP Address MRS NOP Valid DLL RESET tAOFPD/tAOF tXP Valid tIH tIS ODT DQS, DQS# High-Z DQ High-Z DM tDLLK Enter precharge power-down mode Frequency change Exit precharge power-down mode Indicates a Break in Time Scale Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Don't Care 1. Applicable for both slow-exit and fast-exit precharge power-down modes. 2. tAOFPD and tAOF must be satisfied and outputs High-Z prior to T1 (see "On-Die Termination (ODT)" on page 161 for exact requirements). 3. If the RTT_NOM feature was enabled in the mode register prior to entering precharge power-down mode, the ODT signal must be continuously registered LOW ensuring RTT is in an off state. If the RTT_NOM feature was disabled in the mode register prior to entering precharge power-down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case. 102 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands Write Leveling For better signal integrity, DDR3 SDRAM memory modules adopted fly-by topology for the commands, addresses, control signals, and clocks. Write leveling is a scheme for the memory controller to adjust or deskew the DQS strobe (DQS, DQS#) to CK relationship at the DRAM with a simple feedback feature provided by the DRAM. Write leveling is generally used as part of the initialization process, if required. For normal DRAM operation, this feature must be disabled. This is the only DRAM operation where the DQS functions as an input (to capture the incoming clock) and the DQ function as outputs (to report the state of the clock). Note that nonstandard ODT schemes are required. The memory controller using the write leveling procedure must have adjustable delay settings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins. This is accomplished when the DRAM asynchronously feeds back the CK status via the DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the DQS strobe until a CK transition from "0" to "1" is detected. The DQS delay established through this procedure helps ensure tDQSS, tDSS, and tDSH specifications in systems that use fly-by topology by deskewing the trace length mismatch. A conceptual timing of this procedure is shown in Figure 47. Figure 47: Write Leveling Concept T0 T1 T2 T3 T5 T4 T6 T7 CK# CK Source Differential DQS T0 Tn T1 T2 T3 T4 T5 T6 T4 T5 T6 CK# CK Destination Differential DQS 0 DQ Destination Tn T0 T1 0 T2 T3 CK# CK Push DQS to capture 0-1 transition Differential DQS DQ 1 1 Don't Care PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 103 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQ outputs the sampled CK's status. The prime DQ for a x4 or x8 configuration is DQ0 with all other DQ (DQ[7:1]) driving LOW. The prime DQ for a x16 configuration is DQ0 for the lower byte and DQ8 for the upper byte. It outputs the status of CK sampled by LDQS and UDQS. All other DQ (DQ[7:1], DQ[15:9]) continue to drive LOW. Two prime DQ on a x16 enable each byte lane to be leveled independently. The write leveling mode register interacts with other mode registers to correctly configure the write leveling functionality. Besides using MR1[7] to disable/enable write leveling, MR1[12] must be used to enable/disable the output buffers. The ODT value, burst length, and so forth need to be selected as well. This interaction is shown in Table 68. It should also be noted that when the outputs are enabled during write leveling mode, the DQS buffers are set as inputs, and the DQ are set as outputs. Additionally, during write leveling mode, only the DQS strobe terminations are activated and deactivated via the ODT ball. The DQ remain disabled and are not affected by the ODT ball (see Table 68). Table 68: Write Leveling Matrix Note 1 applies to the entire table MR1[7] MR1[12] MR1[3, 6, 9] Write Leveling Output Buffers RTT_NOM Value Disabled Enabled (1) DRAM RTT_NOM DRAM ODT Ball DQS DQ See normal operations Disabled (1) Case Notes Write leveling not enabled 0 DQS not receiving: not terminated Prime DQ High-Z: not terminated Other DQ High-Z: not terminated 1 n/a Low Off 20, 30, 40, 60, or 120 High On DQS not receiving: terminated by RTT Prime DQ High-Z: not terminated Other DQ High-Z: not terminated 2 n/a Low Off DQS receiving: not terminated Prime DQ driving CK state: not terminated Other DQ driving LOW: not terminated 3 40, 60, or 120 High On DQS receiving: terminated by RTT Prime DQ driving CK state: not terminated Other DQ driving LOW: not terminated 4 Enabled (0) Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Off DRAM State 2 3 1. Expected usage if used during write leveling: Case 1 may be used when DRAM are on a dual-rank module and on the rank not being levelized or on any rank of a module not being levelized on a multislotted system. Case 2 may be used when DRAM are on any rank of a module not being levelized on a multislotted system. Case 3 is generally not used. Case 4 is generally used when DRAM are on the rank that is being leveled. 2. Since the DRAM DQS is not being driven (MR1[12] = 1), DQS ignores the input strobe, and all RTT_NOM values are allowed. This simulates a normal standby state to DQS. 3. Since the DRAM DQS is being driven (MR1[12] = 0), DQS captures the input strobe, and only some RTT_NOM values are allowed. This simulates a normal write state to DQS. 104 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands Write Leveling Procedure A memory controller initiates the DRAM write leveling mode by setting MR1[7] to a "1," assuming the other programable features (MR0, MR1, MR2, and MR3) are first set and the DLL is fully reset and locked. The DQ balls enter the write leveling mode going from a High-Z state to an undefined driving state, so the DQ bus should not be driven. During write leveling mode, only the NOP or DES commands are allowed. The memory controller should attempt to level only one rank at a time; thus, the outputs of other ranks should be disabled by setting MR1[12] to a "1" in the other ranks. The memory controller may assert ODT after a tMOD delay as the DRAM will be ready to process the ODT transition. ODT should be turned on prior to DQS being driven LOW by at least ODTL on delay (WL - 2 tCK), provided it does not violate the aforementioned tMOD delay requirement. The memory controller may drive DQS LOW and DQS# HIGH after tWLDQSEN has been satisfied. The controller may begin to toggle DQS after tWLMRD (one DQS toggle is DQS transitioning from a LOW state to a HIGH state with DQS# transitioning from a HIGH state to a LOW state, then both transition back to their original states). At a minimum, ODTL on and tAON must be satisfied at least one clock prior to DQS toggling. After tWLMRD and a DQS LOW preamble (tWPRE) have been satisfied, the memory controller may provide either a single DQS toggle or multiple DQS toggles to sample CK for a given DQS-to-CK skew. Each DQS toggle must not violate tDQSL (MIN) and t DQSH (MIN) specifications. tDQSL (MAX) and tDQSH (MAX) specifications are not applicable during write leveling mode. The DQS must be able to distinguish the CK's rising edge within tWLS and tWLH. The prime DQ will output the CK's status asynchronously from the associated DQS rising edge CK capture within tWLO. The remaining DQ that always drive LOW when DQS is toggling must be LOW within tWLOE after the first tWLO is satisfied (the prime DQ going LOW). As previously noted, DQS is an input and not an output during this process. Figure 48 on page 106 depicts the basic timing parameters for the overall write leveling procedure. The memory controller will likely sample each applicable prime DQ state and determine whether to increment or decrement its DQS delay setting. After the memory controller performs enough DQS toggles to detect the CK's "0-to-1" transition, the memory controller should lock the DQS delay setting for that DRAM. After locking the DQS setting, leveling for the rank will have been achieved, and the write leveling mode for the rank should be disabled or reprogrammed (if write leveling of another rank follows). PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 105 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands Figure 48: Write Leveling Sequence T1 T2 tWLS tWLH CK# CK Command MRS1 NOP2 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP tMOD ODT tWLDQSEN tDQSL3 tDQSH3 tDQSL3 tDQSH3 Differential DQS4 tWLMRD tWLO tWLO Prime DQ5 tWLO tWLOE Early remaining DQ tWLO Late remaining DQ Indicates a Break in Time Scale Notes: Undefined Driving Mode Don't Care 1. MRS: Load MR1 to enter write leveling mode. 2. NOP: NOP or DES. 3. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH (MIN) and tDQSL (MIN) as defined for regular writes. The maximum pulse width is system-dependent. 4. Differential DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. The solid line represents DQS; the dotted line represents DQS#. 5. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ are driven LOW and remain in this state throughout the leveling procedure. Write Leveling Mode Exit Procedure After the DRAM are leveled, they must exit from write leveling mode before the normal mode can be used. Figure 49 on page 107 depicts a general procedure in exiting write leveling mode. After the last rising DQS (capturing a "1" at T0), the memory controller should stop driving the DQS signals after tWLO (MAX) delay plus enough delay to enable the memory controller to capture the applicable prime DQ state (at ~Tb0). The DQ balls become undefined when DQS no longer remains LOW, and they remain undefined until t MOD after the MRS command (at Te1). The ODT input should be deasserted LOW such that ODTL off (MIN) expires after the DQS is no longer driving LOW. When ODT LOW satisfies tIS, ODT must be kept LOW (at ~Tb0) until the DRAM is ready for either another rank to be leveled or until the normal mode can be used. After DQS termination is switched off, write level mode should be disabled via the MRS command (at Tc2). After tMOD is satisfied (at Te1), any valid command may be registered by the DRAM. Some MRS commands may be issued after t MRD (at Td1). PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 106 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Commands Figure 49: Exit Write Leveling T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Tc2 Td0 Td1 Te0 Te1 NOP NOP NOP NOP NOP NOP NOP MRS NOP tMRD Valid NOP Valid CK# CK Command Address MR1 tIS Valid Valid tMOD ODT ODTL off RTT DQS, RTT DQS# tAOF (MIN) RTT_NOM tAOF (MAX) DQS, DQS# RTT_DQ tWLO + tWLOE DQ CK = 1 Indicates a Break in Time Scale Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Undefined Driving Mode Transitioning Don't Care 1. The DQ result, "= 1," between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing CK HIGH just after the T0 state. 107 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Operations Initialization The following sequence is required for power up and initialization, as shown in Figure 50 on page 109: 1. Apply power. RESET# is recommended to be below 0.2 x VDDQ during power ramp to ensure the outputs remain disabled (High-Z) and ODT off (RTT is also High-Z). All other inputs, including ODT, may be undefined. During power up, either of the following conditions may exist and must be met: * Condition A: - VDD and VDDQ are driven from a single-power converter output and are ramped with a maximum delta voltage between them of V 300mV. Slope reversal of any power supply signal is allowed. The voltage levels on all balls other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side, and must be greater than or equal to VSSQ and VSS on the other side. - Both VDD and VDDQ power supplies ramp to VDD (MIN) and VDDQ (MIN) within t VDDPR = 200ms. - VREFDQ tracks VDD x 0.5, VREFCA tracks VDD x 0.5. - VTT is limited to 0.95V when the power ramp is complete and is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latchup. * Condition B: - VDD may be applied before or at the same time as VDDQ. - VDDQ may be applied before or at the same time as VTT, VREFDQ, and VREFCA. - No slope reversals are allowed in the power supply ramp for this condition. 2. Until stable power, maintain RESET# LOW to ensure the outputs remain disabled (High-Z). After the power is stable, RESET# must be LOW for at least 200s to begin the initialization process. ODT will remain in the High-Z state while RESET# is LOW and until CKE is registered HIGH. 3. CKE must be LOW 10ns prior to RESET# transitioning HIGH. 4. After RESET# transitions HIGH, wait 500s (minus one clock) with CKE LOW. 5. After this CKE LOW time, CKE may be brought HIGH (synchronously) and only NOP or DES commands may be issued. The clock must be present and valid for at least 10ns (and a minimum of five clocks) and ODT must be driven LOW at least tIS prior to CKE being registered HIGH. When CKE is registered HIGH, it must be continuously registered HIGH until the full initialization process is complete. 6. After CKE is registered HIGH and after tXPR has been satisfied, MRS commands may be issued. Issue an MRS (LOAD MODE) command to MR2 with the applicable settings (provide LOW to BA2 and BA0 and HIGH to BA1). 7. Issue an MRS command to MR3 with the applicable settings. 8. Issue an MRS command to MR1 with the applicable settings, including enabling the DLL and configuring ODT. 9. Issue an MRS command to MR0 with the applicable settings, including a DLL RESET command. tDLLK (512) cycles of clock input are required to lock the DLL. 10. Issue a ZQCL command to calibrate RTT and RON values for the process voltage temperature (PVT). Prior to normal operation, tZQINIT must be satisfied. 11. When tDLLK and tZQINIT have been satisfied, the DDR3 SDRAM will be ready for normal operation. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 108 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 50: Initialization Sequence T (MAX) = 200ms VDD VDDQ VTT See power-up conditions in the initialization sequence text, set up 1 VREF Power-up ramp tVTD Stable and valid clock T0 T1 tCK Tc0 Tb0 Ta0 Td0 CK# CK tCKSRX tCL tCL tIOz = 20ns RESET# tIS T (MIN) = 10ns CKE Valid ODT Valid tIS Command NOP MRS MRS MRS MRS ZQCL Address Code Code Code Code A10 Code Code Code Code BA0 = L BA1 = H BA2 = L BA0 = H BA1 = H BA2 = L BA0 = H BA1 = L BA2 = L BA0 = L BA1 = L BA2 = L Valid DM BA[2:0] Valid Valid A10 = H Valid DQS DQ RTT T = 200s (MIN) T = 500s (MIN) MR2 All voltage supplies valid and stable tMRD tMRD tMRD tXPR MR3 MR1 with DLL enable tMOD MR0 with DLL reset tZQINIT ZQ calibration tDLLK DRAM ready for external commands Normal operation Indicates a Break in Time Scale PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 109 Don't Care Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Mode Registers Mode registers (MR0-MR3) are used to define various modes of programmable operations of the DDR3 SDRAM. A mode register is programmed via the MODE REGISTER SET (MRS) command during initialization, and it retains the stored information (except for MR0[8] which is self-clearing) until it is either reprogrammed, RESET# goes LOW, or until the device loses power. Contents of a mode register can be altered by reexecuting the MRS command. If the user chooses to modify only a subset of the mode register's variables, all variables must be programmed when the MRS command is issued. Reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. The MRS command can only be issued (or reissued) when all banks are idle and in the precharged state (tRP is satisfied and no data bursts are in progress). After an MRS command has been issued, two parameters must be satisfied: tMRD and tMOD. The controller must wait tMRD before initiating any subsequent MRS commands (see Figure 51). Figure 51: MRS-to-MRS Command Timing (tMRD) T0 T1 T2 Ta0 Ta1 Ta2 MRS1 NOP NOP NOP NOP MRS2 CK# CK Command tMRD Address Valid Valid CKE3 Indicates a Break in Time Scale Notes: Don't Care 1. Prior to issuing the MRS command, all banks must be idle and precharged, tRP (MIN) must be satisfied, and no data bursts can be in progress. 2. tMRD specifies the MRS-to-MRS command minimum cycle time. 3. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN) (see "PowerDown Mode" on page 153). 4. For a CAS latency change, tXPDLL timing must be met before any nonMRS command. The controller must also wait tMOD before initiating any nonMRS commands (excluding NOP and DES), as shown in Figure 52 on page 111. The DRAM requires tMOD in order to update the requested features, with the exception of DLL RESET, which requires additional time. Until tMOD has been satisfied, the updated features are to be assumed unavailable. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 110 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 52: MRS-to-nonMRS Command Timing (tMOD) T0 T1 T2 Ta0 Ta1 Ta2 MRS NOP NOP NOP NOP non MRS CK# CK Command tMOD Address Valid Valid Valid CKE Old setting New setting Updating setting Indicates a Break in Time Scale Notes: Don't Care 1. Prior to issuing the MRS command, all banks must be idle (they must be precharged, tRP must be satisfied, and no data bursts can be in progress). 2. Prior to Ta2 when tMOD (MIN) is being satisfied, no commands (except NOP/DES) may be issued. 3. If RTT was previously enabled, ODT must be registered LOW at T0 so that ODTL is satisfied prior to Ta1. ODT must also be registered LOW at each rising CK edge from T0 until tMOD (MIN) is satisfied at Ta2. 4. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN), at which time power-down may occur (see "Power-Down Mode" on page 153). Mode Register 0 (MR0) The base register, MR0, is used to define various DDR3 SDRAM modes of operation. These definitions include the selection of a burst length, burst type, CAS latency, operating mode, DLL RESET, write recovery, and precharge power-down mode, as shown in Figure 53 on page 112. Burst Length Burst length is defined by MR0[1: 0] (see Figure 53 on page 112). Read and write accesses to the DDR3 SDRAM are burst-oriented, with the burst length being programmable to "4" (chop mode), "8" (fixed), or selectable using A12 during a READ/WRITE command (on-the-fly). The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. When MR0[1:0] is set to "01" during a READ/WRITE command, if A12 = 0, then BC4 (chop) mode is selected. If A12 = 1, then BL8 mode is selected. Specific timing diagrams, and turnaround between READ/WRITE, are shown in the READ/WRITE sections of this document. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A[i:2] when the burst length is set to "4" and by A[i:3] when the burst length is set to "8" (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 111 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 53: Mode Register 0 (MR0) Definitions BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus 16 15 14 13 12 11 10 0 0 01 PD WR Mode register 0 (MR0) 9 01 M15 M14 8 7 6 5 4 3 2 DLL 01 CAS# latency BT 01 1 0 BL M1 M0 Mode Register 0 0 Mode register 0 (MR0) 0 1 Mode register 1 (MR1) M12 Precharge PD 1 0 Mode register 2 (MR2) 0 DLL off (slow exit) 0 1 1 Mode register 3 (MR3) 1 DLL on (fast exit) 1 Notes: 0 Fixed BL8 0 1 4 or 8 (on-the-fly via A12) No 1 0 Fixed BC4 (chop) Yes 1 1 Reserved M8 DLL Reset M11 M10 M9 Write Recovery Burst Length 0 CAS Latency M3 READ Burst Type 0 0 0 Reserved M6 M5 M4 0 0 0 Reserved 0 Sequential (nibble) 0 0 1 5 0 0 1 5 1 Interleaved 0 1 0 6 0 1 0 6 0 1 1 7 0 1 1 7 1 0 0 8 1 0 0 8 1 0 1 10 1 0 1 9 1 1 0 12 1 1 0 10 1 1 1 Reserved 1 1 1 11 1. MR0[16, 13, 7, 2] are reserved for future use and must be programmed to "0." Burst Type Accesses within a given burst may be programmed to either a sequential or an interleaved order. The burst type is selected via MR0[3], as shown in Figure 53. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 69 on page 113. DDR3 only supports 4-bit burst chop and 8-bit burst access modes. Full interleave address ordering is supported for READs, while WRITEs are restricted to nibble (BC4) or word (BL8) boundaries. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 112 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Table 69: Burst Order Burst Length READ/ WRITE Starting Column Address (A[2, 1, 0]) Burst Type = Sequential (Decimal) Burst Type = Interleaved (Decimal) Notes 4 chop READ 000 0, 1, 2, 3, Z, Z, Z, Z 0, 1, 2, 3, Z, Z, Z, Z 1, 2 001 1, 2, 3, 0, Z, Z, Z, Z 1, 0, 3, 2, Z, Z, Z, Z 1, 2 010 2, 3, 0, 1, Z, Z, Z, Z 2, 3, 0, 1, Z, Z, Z, Z 1, 2 011 3, 0, 1, 2, Z, Z, Z, Z 3, 2, 1, 0, Z, Z, Z, Z 1, 2 100 4, 5, 6, 7, Z, Z, Z, Z 4, 5, 6, 7, Z, Z, Z, Z 1, 2 101 5, 6, 7, 4, Z, Z, Z, Z 5, 4, 7, 6, Z, Z, Z, Z 1, 2 110 6, 7, 4, 5, Z, Z, Z, Z 6, 7, 4, 5, Z, Z, Z, Z 1, 2 WRITE 8 READ WRITE Notes: 111 7, 4, 5, 6, Z, Z, Z, Z 7, 6, 5, 4, Z, Z, Z, Z 1, 2 0VV 0, 1, 2, 3, X, X, X, X 0, 1, 2, 3, X, X, X, X 1, 3, 4 1VV 4, 5, 6, 7, X, X, X, X 4, 5, 6, 7, X, X, X, X 1, 3, 4 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 1 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 1 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 1 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 1 VVV 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 1, 3 1. Internal READ and WRITE operations start at the same point in time for BC4 as they do for BL8. 2. Z = Data and strobe output drivers are in tri-state. 3. V = A valid logic level (0 or 1), but the respective input buffer ignores level-on input pins. 4. X = "Don't Care." DLL RESET DLL RESET is defined by MR0[8] (see Figure 53 on page 112). Programming MR0[8] to "1" activates the DLL RESET function. MR0[8] is self-clearing, meaning it returns to a value of "0" after the DLL RESET function has been initiated. Anytime the DLL RESET function is initiated, CKE must be HIGH and the clock held stable for 512 (tDLLK) clock cycles before a READ command can be issued. This is to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in invalid output timing specifications, such as tDQSCK timings. Write Recovery WRITE recovery time is defined by MR0[11:9] (see Figure 53 on page 112). Write recovery values of 5, 6, 7, 8, 10, or 12 may be used by programming MR0[11:9]. The user is required to program the correct value of write recovery and is calculated by dividing tWR (ns) by tCK (ns) and rounding up a noninteger value to the next integer: WR (cycles) = roundup (tWR [ns]/tCK [ns]). PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 113 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Precharge Power-Down (Precharge PD) The precharge PD bit applies only when precharge power-down mode is being used. When MR0[12] is set to "0," the DLL is off during precharge power-down providing a lower standby current mode; however, tXPDLL must be satisfied when exiting. When MR0[12] is set to "1," the DLL continues to run during precharge power-down mode to enable a faster exit of precharge power-down mode; however, tXP must be satisfied when exiting (see "Power-Down Mode" on page 153). CAS Latency (CL) The CL is defined by MR0[6:4], as shown in Figure 53 on page 112. CAS latency is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The CL can be set to 5, 6, 7, 8, 9, or 10. DDR3 SDRAM do not support half-clock latencies. Examples of CL = 6 and CL = 8 are shown in Figure 54. If an internal READ command is registered at clock edge n, and the CAS latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 50 on page 66 through Table 52 on page 68 indicate the CLs supported at various operating frequencies. Figure 54: READ Latency T0 T1 T2 T3 T4 T5 T6 T7 T8 READ NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command AL = 0, CL = 6 DQS, DQS# DI n DQ DI n+1 DI n+2 DI n+3 DI n+4 T0 T1 T2 T3 T4 T5 T6 T7 T8 READ NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command AL = 0, CL = 8 DQS, DQS# DI n DQ Transitioning Data Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Don't Care 1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible. 2. Shown with nominal tDQSCK and nominal tDSDQ. 114 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Mode Register 1 (MR1) The mode register 1 (MR1) controls additional functions and features not available in the other mode registers: Q OFF (OUTPUT DISABLE), TDQS (for the x8 configuration only), DLL ENABLE/DLL DISABLE, RTT_NOM value (ODT), WRITE LEVELING, POSTED CAS ADDITIVE latency, and OUTPUT DRIVE STRENGTH. These functions are controlled via the bits shown in Figure 55. The MR1 register is programmed via the MRS command and retains the stored information until it is reprogrammed, until RESET# goes LOW, or until the device loses power. Reprogramming the MR1 register will not alter the contents of the memory array, provided it is performed correctly. The MR1 register must be loaded when all banks are idle and no bursts are in progress. The controller must satisfy the specified timing parameters tMRD and tMOD before initiating a subsequent operation. Figure 55: Mode Register 1 (MR1) Definition BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus 16 15 14 13 12 11 10 9 8 7 6 5 01 0 1 01 Q Off TDQS 01 RTT 01 WL RTT ODS M15 M14 4 3 AL 2 1 0 Mode register 1 (MR1) RTT ODS DLL Mode Register 0 0 Mode register set 0 (MR0) M12 Q Off M11 TDQS 0 1 Mode register set 1 (MR1) 0 Enabled 0 Disabled 1 0 Mode register set 2 (MR2) 1 Disabled 1 Enabled 1 1 Mode register set 3 (MR3) M0 DLL Enable 0 Enable (normal) 1 Disable M5 M1 Output Drive Strength RTT_NOM (ODT)2 RTT_NOM (ODT)3 M9 M6 M2 Non-Writes Writes 0 0 0 0 RTT_NOM disabled RTT_NOM disabled 1 0 0 1 RZQ/4 (60 [NOM]) RZQ/4 (60 [NOM]) M7 Write Levelization Disable (normal) Enable 0 0 RZQ/6 (40 [NOM]) 0 1 RZQ/7 (34 [NOM]) 1 0 Reserved 1 1 Reserved 0 1 0 RZQ/2 (120 [NOM]) RZQ/2 (120 [NOM]) 0 1 1 Notes: RZQ/6 (40 [NOM]) RZQ/6 (40 [NOM]) M4 M3 Additive Latency (AL) 1 0 0 RZQ/12 (20 [NOM]) n/a 0 0 Disabled (AL = 0) 1 0 1 RZQ/8 (30 [NOM]) n/a 0 1 AL = CL - 1 1 1 0 Reserved Reserved 1 0 AL = CL - 2 1 1 1 Reserved Reserved 1 1 Reserved 1. MR1[16, 13, 10, 8] are reserved for future use and must be programmed to "0." 2. During write leveling, if MR1[7] and MR1[12] are "1" then all RTT_NOM values are available for use. 3. During write leveling, if MR1[7] is a "1," but MR1[12] is a "0," then only RTT_NOM write values are available for use. DLL Enable/DLL Disable The DLL may be enabled or disabled by programming MR1[0] during the LOAD MODE command, as shown in Figure 55. The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL should always be followed by resetting the DLL using the appropriate LOAD MODE command. If the DLL is enabled prior to entering self refresh mode, the DLL is automatically disabled when entering SELF REFRESH operation and is automatically reenabled and reset upon exit of SELF REFRESH operation. If the DLL is disabled prior to entering self refresh mode, the DLL remains disabled even upon exit of SELF REFRESH operation until it is reenabled and reset. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 115 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations The DRAM is not tested to check--nor does Micron warrant compliance with--normal mode timings or functionality when the DLL is disabled. An attempt has been made to have the DRAM operate in the normal mode where reasonably possible when the DLL has been disabled; however, by industry standard, a few known exceptions are defined: 1. ODT is not allowed to be used. 2. The output data is no longer edge-aligned to the clock. 3. CL and CWL can only be six clocks. When the DLL is disabled, timing and functionality can vary from the normal operation specifications when the DLL is enabled (see "DLL Disable Mode" on page 98). Disabling the DLL also implies the need to change the clock frequency (see "Input Clock Frequency Change" on page 101). Output Drive Strength The DDR3 SDRAM uses a programmable impedance output buffer. The drive strength mode register setting is defined by MR1[5, 1]. RZQ/7 (34 [NOM]) is the primary output driver impedance setting for DDR3 SDRAM devices. To calibrate the output driver impedance, an external precision resistor (RZQ) is connected between the ZQ ball and VSSQ. The value of the resistor must be 240 1%. The output impedance is set during initialization. Additional impedance calibration updates do not affect device operation, and all data sheet timings and current specifications are met during an update. To meet the 34 specification, the output drive strength must be set to 34 during initialization. To obtain a calibrated output driver impedance after power-up, the DDR3 SDRAM needs a calibration command that is part of the initialization and reset procedure. OUTPUT ENABLE/DISABLE The OUTPUT ENABLE function is defined by MR1[12], as shown in Figure 55 on page 115. When enabled (MR1[12] = 0), all outputs (DQ, DQS, DQS#) function when in the normal mode of operation. When disabled (MR1[12] = 1), all DDR3 SDRAM outputs (DQ and DQS, DQS#) are tri-stated. The output disable feature is intended to be used during IDD characterization of the READ current and during tDQSS margining (write leveling) only. TDQS Enable Termination data strobe (TDQS) is a feature of the x8 DDR3 SDRAM configuration, which provides termination resistance (RTT), that may be useful in some system configurations. TDQS is not supported in x4 or x16 configurations. When enabled via the mode register (MR1[11]), the RTT that is applied to DQS and DQS# is also applied to TDQS and TDQS#. In contrast to the RDQS function of DDR2 SDRAM, TDQS provides the termination resistance RTT only. The OUTPUT DATA STROBE function of RDQS is not provided by TDQS; thus, RON does not apply to TDQS and TDQS#. The TDQS and DM functions share the same ball. When the TDQS function is enabled via the mode register, the DM function is not supported. When the TDQS function is disabled, the DM function is provided, and the TDQS# ball is not used. The TDQS function is available in the x8 DDR3 SDRAM configuration only and must be disabled via the mode register for the x4 and x16 configurations. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 116 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations On-Die Termination ODT resistance RTT_NOM is defined by MR1[9, 6, 2] (see Figure 55 on page 115). The RTT termination value applies to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls. DDR3 supports multiple RTT termination values based on RZQ/n where n can be 2, 4, 6, 8, or 12 and RZQ is 240. Unlike DDR2, DDR3 ODT must be turned off prior to reading data out and must remain off during a READ burst. RTT_NOM termination is allowed any time after the DRAM is initialized, calibrated, and not performing read access, or when it is not in self refresh mode. Additionally, write accesses with dynamic ODT enabled (RTT_WR) temporarily replaces RTT_NOM with RTT_WR. The actual effective termination, RTT_EFF, may be different from the RTT targeted due to nonlinearity of the termination. For RTT_EFF values and calculations (see "On-Die Termination (ODT)" on page 161). The ODT feature is designed to improve signal integrity of the memory channel by enabling the DDR3 SDRAM controller to independently turn on/off ODT for any or all devices. The ODT input control pin is used to determine when RTT is turned on (ODTL on) and off (ODTL off ), assuming ODT has been enabled via MR1[9, 6, 2]. Timings for ODT are detailed in "On-Die Termination (ODT)" on page 161. WRITE LEVELING The WRITE LEVELING function is enabled by MR1[7], as shown in Figure 55 on page 115. Write leveling is used (during initialization) to deskew the DQS strobe to clock offset as a result of fly-by topology designs. For better signal integrity, DDR3 SDRAM memory modules adopted fly-by topology for the commands, addresses, control signals, and clocks. The fly-by topology benefits from a reduced number of stubs and their lengths. However, fly-by topology induces flight time skews between the clock and DQS strobe (and DQ) at each DRAM on the DIMM. Controllers will have a difficult time maintaining tDQSS, t DSS, and tDSH specifications without supporting write leveling in systems which use fly-by topology-based modules. Write leveling timing and detailed operation information is provided in "Write Leveling" on page 103. POSTED CAS ADDITIVE Latency (AL) AL is supported to make the command and data bus efficient for sustainable bandwidths in DDR3 SDRAM. MR1[4, 3] define the value of AL as shown in Figure 56 on page 118. MR1[4, 3] enable the user to program the DDR3 SDRAM with an AL = 0, CL - 1, or CL - 2. With this feature, the DDR3 SDRAM enables a READ or WRITE command to be issued after the ACTIVATE command for that bank prior to tRCD (MIN). The only restriction is ACTIVATE to READ or WRITE + AL tRCD (MIN) must be satisfied. Assuming tRCD (MIN) = CL, a typical application using this feature sets AL = CL - 1tCK = tRCD (MIN) - 1 tCK. The READ or WRITE command is held for the time of the AL before it is released internally to the DDR3 SDRAM device. READ latency (RL) is controlled by the sum of the AL and CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum of CAS WRITE latency and AL, WL = AL + CWL (see "Mode Register 2 (MR2)" on page 118). Examples of READ and WRITE latencies are shown in Figure 56 on page 118 and Figure 58 on page 119. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 117 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 56: READ Latency (AL = 5, CL = 6) BC4 T0 T1 ACTIVE n READ n T2 T6 T11 T12 T13 T14 NOP NOP NOP NOP NOP NOP CK# CK Command tRCD (MIN) DQS, DQS# AL = 5 CL = 6 DO n DQ DO n+1 DO n+2 DO n+3 RL = AL + CL = 11 Indicates a Break in Time Scale Transitioning Data Don't Care Mode Register 2 (MR2) The mode register 2 (MR2) controls additional functions and features not available in the other mode registers. These additional functions are CAS WRITE latency (CWL), AUTO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC ODT (RTT_WR). These functions are controlled via the bits shown in Figure 57. The MR2 is programmed via the MRS command and will retain the stored information until it is programmed again or until the device loses power. Reprogramming the MR2 register will not alter the contents of the memory array, provided it is performed correctly. The MR2 register must be loaded when all banks are idle and no data bursts are in progress, and the controller must wait the specified time tMRD and tMOD before initiating a subsequent operation. Figure 57: Mode Register 2 (MR2) Definition BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus 16 15 14 13 12 11 10 9 8 7 6 0 01 01 01 RTT_WR 01 SRT ASR Mode register 2 (MR2) 5 01 1 M15 M14 Mode Register 2 1 0 01 01 01 M5 M4 M3 CAS Write Latency (CWL) 5 CK (tCK 2.5ns) 0 Mode register set 0 (MR0) 0 Normal (0C to 85C) 0 0 0 0 1 Mode register set 1 (MR1) 1 Extended (0C to 95C) 0 0 1 1 0 Mode register set 2 (MR2) 0 1 0 6 CK (2.5ns > tCK 1.875ns) 7 CK (1.875ns > tCK 1.5ns) 1 1 Mode register set 3 (MR3) 0 1 1 8 CK (1.5ns > tCK 1.25ns) 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved 0 PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 3 0 M10 M9 Notes: M7 Self Refresh Temperature 4 CWL 0 Dynamic ODT ( RTT_WR ) M6 0 RTT_WR disabled 1 1 0 RZQ/2 1 1 Reserved Disabled: Manual 1 Enabled: Automatic RZQ/4 0 Auto Self Refresh (Optional) 1. MR2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to "0." 118 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations CAS Write Latency (CWL) CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the internal write to the latching of the first data in. CWL must be correctly set to the corresponding operating clock frequency (see Figure 57 on page 118). The overall WRITE latency (WL) is equal to CWL + AL (Figure 55 on page 115), as shown in Figure 58. Figure 58: CAS Write Latency BC4 T0 T1 ACTIVE n WRITE n T2 T6 T11 T12 T13 T14 NOP NOP NOP NOP NOP NOP CK# CK Command tRCD (MIN) DQS, DQS# AL = 5 CWL = 6 DI n DQ DI n+1 DI n+2 DI n+3 WL = AL + CWL = 11 Indicates A Break in Time Scale Transitioning Data Don't Care AUTO SELF REFRESH (ASR) Mode register MR2[6] is used to disable/enable the ASR function. When ASR is disabled, the self refresh mode's refresh rate is assumed to be at the normal 85C limit (sometimes referred to as 1X refresh rate). In the disabled mode, ASR requires the user to ensure the DRAM never exceeds a TC of 85C while in self refresh unless the user enables the SRT feature listed below when the TC is between 85C and 95C. Enabling ASR assumes the DRAM self refresh rate is changed automatically from 1X to 2X when the case temperature exceeds 85C. This enables the user to operate the DRAM beyond the standard 85C limit up to the optional extended temperature range of 95C while in self refresh mode. The standard self refresh current test specifies test conditions to normal case temperature (85C) only, meaning if ASR is enabled, the standard self refresh current specifications do not apply (see "Extended Temperature Usage" on page 152). SELF REFRESH TEMPERATURE (SRT) Mode register MR2[7] is used to disable/enable the SRT function. When SRT is disabled, the self refresh mode's refresh rate is assumed to be at the normal 85C limit (sometimes referred to as 1X refresh rate). In the disabled mode, SRT requires the user to ensure the DRAM never exceeds a TC of 85C while in self refresh mode unless the user enables ASR. When SRT is enabled, the DRAM self refresh is changed internally from 1X to 2X, regardless of the case temperature. This enables the user to operate the DRAM beyond the standard 85C limit up to the optional extended temperature range of 95C while in self refresh mode. The standard self refresh current test specifies test conditions to normal case temperature (85C) only, meaning if SRT is enabled, the standard self refresh current specifications do not apply (see "Extended Temperature Usage" on page 152). PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 119 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations SRT vs. ASR If the normal case temperature limit of 85C is not exceeded, then neither SRT nor ASR is required, and both can be disabled throughout operation. However, if the extended temperature option of 95C is needed, the user is required to provide a 2X refresh rate during (manual) refresh and to enable either the SRT or the ASR to ensure self refresh is performed at the 2X rate. SRT forces the DRAM to switch the internal self refresh rate from 1X to 2X. Self refresh is performed at the 2X refresh rate regardless of the case temperature. ASR automatically switches the DRAM's internal self refresh rate from 1X to 2X. However, while in self refresh mode, ASR enables the refresh rate to automatically adjust between 1X to 2X over the supported temperature range. One other disadvantage with ASR is the DRAM cannot always switch from a 1X to a 2X refresh rate at an exact case temperature of 85C. Although the DRAM will support data integrity when it switches from a 1X to a 2X refresh rate, it may switch at a lower temperature than 85C. Since only one mode is neccesary, SRT and ASR cannot be enabled at the same time. DYNAMIC ODT The dynamic ODT (RTT_WR) feature is defined by MR2[10, 9]. Dynamic ODT is enabled when a value is selected. This new DDR3 SDRAM feature enables the ODT termination value to change without issuing an MRS command, essentially changing the ODT termination "on-the-fly." With dynamic ODT (RTT_WR) enabled, the DRAM switches from normal ODT (RTT_NOM) to dynamic ODT (RTT_WR) when beginning a WRITE burst and subsequently switches back to ODT (RTT_NOM) at the completion of the WRITE burst. If RTT_NOM is disabled, the RTT_NOM value will be High-Z. Special timing parameters must be adhered to when dynamic ODT (RTT_WR) is enabled: ODTLCNW, ODTLCNW4, ODTLCNW8, ODTH4, ODTH8, and tADC. Dynamic ODT is only applicable during WRITE cycles. If ODT (RTT_NOM) is disabled, dynamic ODT (RTT_WR) is still permitted. RTT_NOM and RTT_WR can be used independent of one other. Dynamic ODT is not available during write leveling mode, regardless of the state of ODT (RTT_NOM). For details on dynamic ODT operation, refer to "On-Die Termination (ODT)" on page 161. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 120 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Mode Register 3 (MR3) The mode register 3 (MR3) controls additional functions and features not available in the other mode registers. Currently defined is the MULTIPURPOSE REGISTER (MPR). This function is controlled via the bits shown in Figure 59. The MR3 is programmed via the LOAD MODE command and retains the stored information until it is programmed again or until the device loses power. Reprogramming the MR3 register will not alter the contents of the memory array, provided it is performed correctly. The MR3 register must be loaded when all banks are idle and no data bursts are in progress, and the controller must wait the specified time tMRD and tMOD before initiating a subsequent operation. Figure 59: Mode Register 3 (MR3) Definition BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 16 A4 A3 A2 A1 A0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 01 01 01 01 01 01 01 01 01 01 01 MPR MPR_RF 01 Mode Register M2 0 0 Mode register set (MR0) 0 MPR Enable Normal DRAM operations2 0 1 Mode register set 1 (MR1) 1 Dataflow from MPR 1 0 Mode register set 2 (MR2) 1 1 Mode register set 3 (MR3) M15 M14 Notes: A7 A6 A5 M1 M0 Address bus Mode register 3 (MR3) MPR READ Function 0 0 Predefined pattern3 0 1 Reserved 1 0 Reserved 1 1 Reserved 1. MR3[16 and 13:4] are reserved for future use and must all be programmed to "0." 2. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored. 3. Intended to be used for READ synchronization. MULTIPURPOSE REGISTER (MPR) The MULTIPURPOSE REGISTER function is used to output a predefined system timing calibration bit sequence. Bit 2 is the master bit that enables or disables access to the MPR register, and bits 1 and 0 determine which mode the MPR is placed in. The basic concept of the multipurpose register is shown in Figure 60 on page 122. If MR3[2] is a "0," then the MPR access is disabled, and the DRAM operates in normal mode. However, if MR3[2] is a "1," then the DRAM no longer outputs normal read data but outputs MPR data as defined by MR3[0, 1]. If MR3[0, 1] is equal to "00," then a predefined read pattern for system calibration is selected. To enable the MPR, the MRS command is issued to MR3, and MR3[2] = 1 (see Table 70 on page 122). Prior to issuing the MRS command, all banks must be in the idle state (all banks are precharged, and tRP is met). When the MPR is enabled, any subsequent READ or RDAP commands are redirected to the multipurpose register. The resulting operation when either a READ or a RDAP command is issued, is defined by MR3[1:0] when the MPR is enabled (see Table 71 on page 123). When the MPR is enabled, only READ or RDAP commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3[2] = 0). Power-down mode, self refresh, and any other nonREAD/RDAP command is not allowed during MPR enable mode. The RESET function is supported during MPR enable mode. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 121 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 60: Multipurpose Register (MPR) Block Diagram Memory core MR3[2] = 0 (MPR off) Multipurpose register predefined data for READs MR3[2] = 1 (MPR on) DQ, DM, DQS, DQS# Notes: Table 70: 1. A predefined data pattern can be read out of the MPR with an external READ command. 2. MR3[2] defines whether the data flow comes from the memory core or the MPR. When the data flow is defined, the MPR contents can be read out continuously with a regular READ or RDAP command. MPR Functional Description of MR3 Bits MR3[2] MR3[1:0] MPR MPR READ Function Function 0 "Don't Care" Normal operation, no MPR transaction All subsequent READs come from the DRAM memory array All subsequent WRITEs go to the DRAM memory array 1 A[1:0] (see Table 71 on page 123) Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and 2 MPR Functional Description The MPR JEDEC definition allows for either a prime DQ (DQ0 on a x4 and a x8; on a x16, DQ0 = lower byte and DQ8 = upper byte) to output the MPR data with the remaining DQs driven LOW or for all DQs to output the MPR data . The MPR readout supports fixed READ burst and READ burst chop (MRS and OTF via A12/BC#) with regular READ latencies and AC timings applicable, provided the DLL is locked as required. MPR addressing for a valid MPR read is as follows: * A[1:0] must be set to "00" as the burst order is fixed per nibble * A2 selects the burst order: - BL8, A2 is set to "0," and the burst order is fixed to 0, 1, 2, 3, 4, 5, 6, 7 * For burst chop 4 cases, the burst order is switched on the nibble base and: - A2 = 0; burst order = 0, 1, 2, 3 - A2 = 1; burst order = 4, 5, 6, 7 * Burst order bit 0 (the first bit) is assigned to LSB, and burst order bit 7 (the last bit) is assigned to MSB * A[9:3] are a "Don't Care" * A10 is a "Don't Care" PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 122 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations * * * * A11 is a "Don't Care" A12: Selects burst chop mode on-the-fly, if enabled within MR0 A13 is a "Don't Care" BA[2:0] are a "Don't Care" MPR Register Address Definitions and Bursting Order The MPR currently supports a single data format. This data format is a predefined read pattern for system calibration. The predefined pattern is always a repeating 0-1 bit pattern. Examples of the different types of predefined READ pattern bursts are shown in Figure 61 on page 124, Figure 62 on page 125, Figure 63 on page 126, and Figure 64 on page 127. Table 71: MPR Readouts and Burst Order Bit Mapping MR3[2] MR3[1:0] Function 1 00 READ predefined pattern for system calibration 1 1 1 01 10 11 Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN RFU RFU RFU Burst Length Read A[2:0] BL8 000 Burst order: 0, 1, 2, 3, 4, 5, 6, 7 Predefined pattern: 0, 1, 0, 1, 0, 1, 0, 1 BC4 000 Burst order: 0, 1, 2, 3 Predefined pattern: 0, 1, 0, 1 BC4 100 Burst order: 4, 5, 6, 7 Predefined pattern: 0, 1, 0, 1 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a Burst Order and Data Pattern n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 1. Burst order bit 0 is assigned to LSB, and burst order bit 7 is assigned to MSB of the selected MPR agent. 123 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Figure 61: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout T0 Ta0 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 Tc10 PREA MRS READ1 NOP NOP NOP NOP NOP NOP NOP NOP MRS NOP NOP Valid CK# CK Command tRP tMPRR tMOD tMOD Bank address 3 Valid 3 A[1:0] 0 02 Valid A2 1 02 0 A[9:3] 00 Valid 00 0 Valid 0 A11 0 Valid 0 A12/BC# 0 Valid1 0 A[15:13] 0 Valid 0 A10/AP 1 124 RL DQS, DQS# Indicates a Break in Time Scale Notes: 1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0]. Don't Care 1Gb: x4, x8, x16 DDR3 SDRAM Operations Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. DQ PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Figure 62: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout T0 Ta Tb Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 READ1 NOP NOP NOP NOP NOP NOP NOP NOP NOP Tc10 Td CK# CK Command PREA READ1 MRS tRP tCCD tMOD MRS Bank address 3 Valid Valid 3 A[1:0] 0 02 02 Valid A2 1 02 12 0 A[9:3] 00 Valid Valid 00 0 Valid Valid 0 A11 0 Valid Valid 0 A12/BC# 0 Valid Valid1 0 A[15:13] 0 Valid Valid 0 A10/AP 1 Valid tMOD tMPRR RL 125 DQS, DQS# RL Indicates a Break in Time Scale Notes: 1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0]. Don't Care 1Gb: x4, x8, x16 DDR3 SDRAM Operations Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. DQ PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Figure 63: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble T0 Ta Tb MRS READ1 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 READ1 NOP NOP NOP NOP NOP NOP NOP Tc8 Tc9 MRS NOP Tc10 Td NOP Valid CK# CK Command PREA tRF tMPRR tCCD tMOD tMOD Bank address 3 Valid Valid 3 A[1:0] 0 02 02 Valid A2 1 03 14 0 A[9:3] 00 Valid Valid 00 0 Valid Valid 0 A11 0 Valid Valid 0 A12/BC# 0 Valid1 Valid1 0 A[15:13] 0 Valid Valid 0 A10/AP 1 RL 126 DQS, DQS# RL DQ Notes: 1. 2. 3. 4. READ with BC4 either by MRS or OTF. Memory controller must drive 0 on A[1:0]. A2 = 0 selects lower 4 nibble bits 0 . . . 3. A2 = 1 selects upper 4 nibble bits 4 . . . 7. Don't Care 1Gb: x4, x8, x16 DDR3 SDRAM Operations Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Indicates a Break in Time Scale PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Figure 64: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble T0 Ta Tb Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 PREA MRS READ1 READ1 NOP NOP NOP NOP NOP NOP NOP Tc8 Tc9 MRS NOP Tc10 Td NOP Valid CK# CK Command tRF tCCD tMOD tMPRR tMOD Bank address 3 Valid Valid 3 A[1:0] 0 02 02 Valid A2 1 13 04 0 A[9:3] 00 Valid Valid 00 0 Valid Valid 0 A11 0 Valid Valid 0 A12/BC# 0 Valid1 Valid1 0 A[15:13] 0 Valid Valid 0 A10/AP 1 RL 127 DQS, DQS# RL DQ Notes: 1. 2. 3. 4. READ with BC4 either by MRS or OTF. Memory controller must drive 0 on A[1:0]. A2 = 1 selects upper 4 nibble bits 4 . . . 7. A2 = 0 selects lower 4 nibble bits 0 . . . 3. Don't Care 1Gb: x4, x8, x16 DDR3 SDRAM Operations Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Indicates a Break in Time Scale 1Gb: x4, x8, x16 DDR3 SDRAM Operations MPR Read Predefined Pattern The predetermined read calibration pattern is a fixed pattern of 0, 1, 0, 1, 0, 1, 0, 1. The following is an example of using the read out predetermined read calibration pattern. The example is to perform multiple reads from the multipurpose register in order to do system level read timing calibration based on the predetermined and standardized pattern. The following protocol outlines the steps used to perform the read calibration: * Precharge all banks * After tRP is satisfied, set MRS, MR3[2] = 1 and MR3[1:0] = 00. This redirects all subsequent reads and loads the predefined pattern into the MPR. As soon as tMRD and t MOD are satisfied, the MPR is available * Data WRITE operations are not allowed until the MPR returns to the normal DRAM state * Issue a read with burst order information (all other address pins are "Don't Care"): - A[1:0] = 00 (data burst order is fixed starting at nibble) - A2 = 0 (for BL8, burst order is fixed as 0, 1, 2, 3, 4, 5, 6, 7) - A12 = 1 (use BL8) * After RL = AL + CL, the DRAM bursts out the predefined read calibration pattern (0, 1, 0, 1, 0, 1, 0, 1) * The memory controller repeats the calibration reads until read data capture at memory controller is optimized * After the last MPR READ burst and after tMPRR has been satisfied, issue MRS, MR3[2] = 0, and MR3[1:0] = "Don't Care" to the normal DRAM state. All subsequent read and write accesses will be regular reads and writes from/to the DRAM array * When tMRD and tMOD are satisfied from the last MRS, the regular DRAM commands (such as activate a memory bank for regular read or write access) are permitted MODE REGISTER SET (MRS) The mode registers are loaded via inputs BA[2:0], A[13:0]. BA[2:0] determine which mode register is programmed: * BA2 = 0, BA1 = 0, BA0 = 0 for MR0 * BA2 = 0, BA1 = 0, BA0 = 1 for MR1 * BA2 = 0, BA1 = 1, BA0 = 0 for MR2 * BA2 = 0, BA1 = 1, BA0 = 1 for MR3 The MRS command can only be issued (or reissued) when all banks are idle and in the precharged state (tRP is satisfied and no data bursts are in progress). The controller must wait the specified time tMRD before initiating a subsequent operation such as an ACTIVATE command (see Figure 51 on page 110). There is also a restriction after issuing an MRS command with regard to when the updated functions become available. This parameter is specified by tMOD. Both tMRD and tMOD parameters are shown in Figure 51 on page 110 and Figure 52 on page 111. Violating either of these requirements will result in unspecified operation. ZQ CALIBRATION The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (RON) and ODT values (RTT) over process, voltage, and temperature, provided a dedicated 240 (1 percent) external resistor is connected from the DRAM's ZQ ball to VSSQ. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 128 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations DDR3 SDRAM need a longer time to calibrate RON and ODT at power-up initialization and self refresh exit and a relatively shorter time to perform periodic calibrations. DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQ CALIBRATION LONG (ZQCL) and ZQ CALIBRATION SHORT (ZQCS). An example of ZQ calibration timing is shown in Figure 65. All banks must be precharged and tRP must be met before ZQCL or ZQCS commands can be issued to the DRAM. No other activities (other than another ZQCL or ZQCS command may be issued to another DRAM) can be performed on the DRAM channel by the controller for the duration of tZQINIT or tZQOPER . The quiet time on the DRAM channel helps accurately calibrate RON and ODT. After DRAM calibration is achieved, the DRAM should disable the ZQ ball's current consumption path to reduce power. ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time. Upon self refresh exit, an explicit ZQCL is required if ZQ calibration is desired. In dual-rank systems that share the ZQ resistor between devices, the controller must not allow overlap of tZQINIT, tZQOPER, or tZQCS between ranks. Figure 65: ZQ Calibration Timing (ZQCL and ZQCS) T0 T1 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2 ZQCL NOP NOP NOP Valid Valid ZQCS NOP NOP NOP Valid Address Valid Valid Valid A10 Valid Valid Valid CK# CK Command CKE 1 Valid Valid 1 Valid ODT 2 Valid Valid 2 Valid DQ 3 Activities 3 High-Z tZQINIT or tZQOPER High-Z tZQCS Indicates a Break in Time Scale Notes: Activities Don't Care 1. CKE must be continuously registered HIGH during the calibration procedure. 2. ODT must be disabled via the ODT signal or the MRS during the calibration procedure. 3. All devices connected to the DQ bus should be High-Z during calibration. ACTIVATE Before any READ or WRITE commands can be issued to a bank within the DRAM, a row in that bank must be opened (activated). This is accomplished via the ACTIVATE command, which selects both the bank and the row to be activated. After a row is opened with an ACTIVATE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. However, if the additive latency is programmed correctly, a READ or WRITE command may be issued prior to tRCD (MIN). In this operation, the DRAM enables a READ or WRITE command to be issued after the ACTIVATE command for that bank, but prior to tRCD (MIN) with the requirement that (ACTIVATE-to-READ/WRITE) + AL tRCD (MIN) (see "POSTED CAS ADDITIVE Latency (AL)" on page 117). tRCD (MIN) should be divided by the clock period and rounded up to PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 129 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations the next whole number to determine the earliest clock edge after the ACTIVATE command on which a READ or WRITE command can be entered. The same procedure is used to convert other specification limits from time units to clock cycles. When at least one bank is open, any READ-to-READ command delay or WRITE-toWRITE command delay is restricted to tCCD (MIN). A subsequent ACTIVATE command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). The minimum time interval between successive ACTIVATE commands to the same bank is defined by tRC. A subsequent ACTIVATE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVATE commands to different banks is defined by t RRD. No more than four bank ACTIVATE commands may be issued in a given t FAW (MIN) period, and the tRRD (MIN) restriction still applies. The tFAW (MIN) parameter applies, regardless of the number of banks already opened or closed. Figure 66: Example: Meeting tRRD (MIN) and tRCD (MIN) T0 T1 T2 T3 T4 T5 T8 T9 T10 T11 Command ACT NOP NOP ACT NOP NOP NOP NOP NOP RD/WR Address Row Row Col BA[2:0] Bank x Bank y Bank y CK# CK tRRD tRCD Indicates a Break in Time Scale Don't Care Figure 67: Example: tFAW CK# T0 T1 T4 T5 T8 T9 T10 T11 T19 T20 ACT NOP ACT NOP ACT NOP ACT NOP NOP ACT CK Command Address BA[2:0] Row Row Row Row Row Bank a Bank b Bank c Bank d Bank ey tRRD tFAW Indicates a Break in Time Scale PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 130 Don't Care Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations READ READ bursts are initiated with a READ command. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is automatically precharged at the completion of the burst. If auto precharge is disabled, the row will be left open after the completion of the burst. During READ bursts, the valid data-out element from the starting column address is available READ latency (RL) clocks later. RL is defined as the sum of POSTED CAS ADDITIVE latency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is programmable in the mode register via the MRS command. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge (that is, at the next crossing of CK and CK#). Figure 68 shows an example of RL based on a CL setting of 8 and an AL setting of 0. Figure 68: READ Latency T0 T7 T8 T9 T10 T11 T12 T12 READ NOP NOP NOP NOP NOP NOP NOP CK# CK Command Address Bank a, Col n CL = 8, AL = 0 DQS, DQS# DO n DQ Indicates a Break in Time Scale Notes: Transitioning Data Don't Care 1. DO n = data-out from column n. 2. Subsequent elements of data-out appear in the programmed order following DO n. DQS, DQS# is driven by the DRAM along with the output data. The initial low state on DQS and HIGH state on DQS# is known as the READ preamble (tRPRE). The low state on DQS and the HIGH state on DQS#, coincident with the last data-out element, is known as the READ postamble (tRPST). Upon completion of a burst, assuming no other commands have been initiated, the DQ will go High-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out window hold), and the valid data window are depicted in Figure 79 on page 139. A detailed explanation of tDQSCK (DQS transition skew to CK) is also depicted in Figure 79 on page 139. Data from any READ burst may be concatenated with data from a subsequent READ command to provide a continuous flow of data. The first data element from the new burst follows the last element of a completed burst. The new READ command should be issued tCCD cycles after the first READ command. This is shown for BL8 in Figure 69 on page 133. If BC4 is enabled, tCCD must still be met which will cause a gap in the data output, as shown in Figure 70 on page 133. Nonconsecutive read data is reflected in Figure 71 on page 134. DDR3 SDRAM do not allow interrupting or truncating any READ burst. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 131 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Data from any READ burst must be completed before a subsequent WRITE burst is allowed. An example of a READ burst followed by a WRITE burst for BL8 is shown in Figure 72 on page 134 (BC4 is shown in Figure 73 on page 135). To ensure the read data is completed before the write data is on the bus, the minimum READ-to-WRITE timing is RL + tCCD - WL + 2tCK. A READ burst may be followed by a PRECHARGE command to the same bank provided auto precharge is not activated. The minimum READ-to-PRECHARGE command spacing to the same bank is four clocks and must also satisfy a minimum analog time from the READ command. This time is called tRTP (READ-to-PRECHARGE). tRTP starts AL cycles later than the READ command. Examples for BL8 are shown in Figure 74 on page 135 and BC4 in Figure 75 on page 136. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. The PRECHARGE command followed by another PRECHARGE command to the same bank is allowed. However, the precharge period will be determined by the last PRECHARGE command issued to the bank. If A10 is HIGH when a READ command is issued, the READ with auto precharge function is engaged. The DRAM starts an auto precharge operation on the rising edge which is AL + tRTP cycles after the READ command. DRAM support a tRAS lockout feature (see Figure 77 on page 136). If tRAS (MIN) is not satisfied at the edge, the starting point of the auto precharge operation will be delayed until tRAS (MIN) is satisfied. If tRTP (MIN) is not satisfied at the edge, the starting point of the auto precharge operation will be delayed until tRTP (MIN) is satisfied. In case the internal precharge is pushed out by t RTP, tRP starts at the point at which the internal precharge happens (not at the next rising clock edge after this event). The time from READ with auto precharge to the next ACTIVATE command to the same bank is AL + (tRTP + tRP)*, where "*" means rounded up to the next integer. In any event, internal precharge does not start earlier than four clocks after the last 8n-bit prefetch. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 132 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Figure 69: Consecutive READ Bursts (BL8) T0 T1 READ NOP T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 NOP NOP READ NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command1 tCCD Address2 Bank, Col n Bank, Col b tRPRE tRPST DQS, DQS# DO n DQ3 RL = 5 DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DO b DO b+1 DO b+2 DO b+3 DO b+4 DO b+5 DO b+6 DO b+7 RL = 5 Transitioning Data Notes: 1. 2. 3. 4. Don't Care NOP commands are shown for ease of illustration; other commands may be valid at these times. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0 and T4. DO n (or b) = data-out from column n (or column b). BL8, RL = 5 (CL = 5, AL = 0). Figure 70: Consecutive READ Bursts (BC4) 133 T0 T1 READ NOP T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 NOP NOP READ NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command1 Address2 Bank, Col n Bank, Col b tRPRE tRPST tRPST tRPRE DQS, DQS# DQ3 RL = 5 DO n DO n+1 DO n+2 DO n+3 DO b DO b+1 DO b+2 DO b+3 RL = 5 Transitioning Data Notes: 1. 2. 3. 4. Don't Care NOP commands are shown for ease of illustration; other commands may be valid at these times. The BC4 setting is activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ command at T0 and T4. DO n (or b) = data-out from column n (or column b). BC4, RL = 5 (CL = 5, AL = 0). 1Gb: x4, x8, x16 DDR3 SDRAM Operations Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. tCCD PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Figure 71: Nonconsecutive READ Bursts T0 T1 T2 T3 T4 READ NOP NOP NOP NOP T5 T6 READ NOP T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command Bank a, Col n Address NOP NOP Bank a, Col b CL = 8 CL = 8 DQS, DQS# DO n DQ DO b Transitioning Data Notes: 1. 2. 3. 4. Don't Care AL = 0, RL = 8. DO n (or b) = data-out from column n (or column b). Seven subsequent elements of data-out appear in the programmed order following DO n. Seven subsequent elements of data-out appear in the programmed order following DO b. Figure 72: READ (BL8) to WRITE (BL8) CK# 134 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 READ NOP NOP NOP NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP CK Command1 Address2 tWR tBL = 4 clocks Bank, Col n tWTR Bank, Col b tRPRE tRPST tWPRE tWPST DQS, DQS# DO n DQ3 RL = 5 DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DI n DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 WL = 5 Transitioning Data Notes: DI n+7 Don't Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at T0, and the WRITE command at T6. 3. DO n = data-out from column, DI b = data-in for column b. 4. BL8, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5). 1Gb: x4, x8, x16 DDR3 SDRAM Operations Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. READ-to-WRITE command delay = RL + tCCD + 2tCK - WL PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Figure 73: READ (BC4) to WRITE (BC4) OTF T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 READ NOP NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command1 READ-to-WRITE command delay = RL + tCCD/2 + 2tCK - WL Bank, Col n Address2 tWR tWTR tBL = 4 clocks Bank, Col b tRPRE tRPST tWPRE tWPST DQS, DQS# DO n DQ3 DO n+1 DO n+2 DO n+3 DI n DI n+2 DI n+1 DI n+3 RL = 5 WL = 5 Transitioning Data Notes: 135 1. 2. 3. 4. Don't Care NOP commands are shown for ease of illustration; other commands may be valid at these times. The BC4 OTF setting is activated by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command at T4. DO n = data-out from column n; DI n = data-in from column b. BC4, RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5). T0 T1 T2 T3 T4 READ NOP NOP NOP NOP T5 T6 T7 T8 T9 T10 T11 T12 PRE NOP NOP NOP NOP NOP NOP NOP T13 T14 T15 T16 T17 ACT NOP NOP NOP NOP CK# CK Command Address Bank a, Col n Bank a, (or all) Bank a, Row b tRTP tRP DQS, DQS# DQ tRAS DO n DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 Transitioning Data Don't Care 1Gb: x4, x8, x16 DDR3 SDRAM Operations Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Figure 74: READ to PRECHARGE (BL8) PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Figure 75: READ to PRECHARGE (BC4) CK# T0 T1 T2 T3 T4 READ NOP NOP NOP NOP T5 T6 T7 T8 T9 T10 T11 T12 PRE NOP NOP NOP NOP NOP NOP NOP T13 T14 T15 T16 T17 ACT NOP NOP NOP NOP CK Command Address Bank a, Col n Bank a, (or all) Bank a, Row b tRP tRTP DQS, DQS# DO n DQ tRAS DO n+1 DO n+2 DO n+3 Transitioning Data Don't Care Figure 76: READ to PRECHARGE (AL = 5, CL = 6) T0 T1 T2 T3 T4 T5 T6 T7 T8 READ NOP NOP NOP NOP NOP NOP NOP NOP T9 T10 T11 T12 T13 T14 PRE NOP NOP NOP NOP NOP T15 CK# CK Command Address Bank a, Col n Bank a, (or all) tRTP AL = 5 ACT Bank a, Row b tRP DQS, DQS# DO n DQ DO n+1 DO n+2 DO n+3 136 CL = 6 tRAS Transitioning Data Don't Care T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 Command READ NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Address Bank a, Col n Ta0 CK# CK NOP ACT Bank a, Row b AL = 4 tRTP (MIN) DQS, DQS# DO n DQ DO n+1 DO n+2 DO n+3 CL = 6 tRAS (MIN) tRP Indicates A Break in Time Scale Transitioning Data Don't Care 1Gb: x4, x8, x16 DDR3 SDRAM Operations Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Figure 77: READ with Auto Precharge (AL = 4, CL = 6) 1Gb: x4, x8, x16 DDR3 SDRAM Operations A DQS to DQ output timing is shown in Figure 78 on page 138. The DQ transitions between valid data outputs must be within tDQSQ of the crossing point of DQS, DQS#. DQS must also maintain a minimum HIGH and LOW time of tQSH and tQSL. Prior to the READ preamble, the DQ balls will either be floating or terminated depending on the status of the ODT signal. Figure 79 on page 139 shows the strobe-to-clock timing during a READ. The crossing point DQS, DQS# must transition within tDQSCK of the clock crossing point. The data out has no timing relationship to clock, only to DQS, as shown in Figure 79 on page 139. Figure 79 on page 139 also shows the READ preamble and postamble. Normally, both DQS and DQS# are High-Z to save power (VDDQ). Prior to data output from the DRAM, DQS is driven LOW and DQS# is HIGH for tRPRE. This is known as the READ preamble. The READ postamble, tRPST, is one half clock from the last DQS, DQS# transition. During the READ postamble, DQS is driven LOW and DQS# is HIGH. When complete, the DQ will either be disabled or will continue terminating depending on the state of the ODT signal. Figure 84 on page 142 demonstrates how to measure tRPST. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 137 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Figure 78: Data Output Timing - tDQSQ and Data Valid Window T0 T1 T2 READ NOP NOP CK# T3 T4 T5 T6 T7 T8 T9 T10 NOP NOP NOP NOP NOP NOP NOP NOP CK Command1 RL = AL + CL Address 2 Bank, Col n tDQSQ (MAX) tDQSQ (MAX) tLZ (DQ) MIN tRPST tHZ (DQ) MAX DQS, DQS# tRPRE tQH DQ3 (last data valid) DO n DQ3 (first data no longer valid) DO n tQH DO DO DO DO DO DO DO n+1 n+2 n+3 n+4 n+5 n+6 n+7 DO DO DO DO DO DO DO n+3 n+1 n+2 n+4 n+5 n+6 n+7 DO n All DQ collectively Data valid DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 Data valid Transitioning Data Notes: 138 NOP commands are shown for ease of illustration; other commands may be valid at these times. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at T0. DO n = data-out from column n. BL8, RL = 5 (AL = 0, CL = 5). Output timings are referenced to VDDQ/2 and DLL on and locked. tDQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to clock. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or late) within a burst. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1. 2. 3. 4. 5. 6. 7. Don't Care 1Gb: x4, x8, x16 DDR3 SDRAM Operations t HZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving tHZ (DQS) and tHZ (DQ) or begins driving tLZ (DQS), t LZ (DQ). Figure 80 shows a method to calculate the point when the device is no longer driving tHZ (DQS) and tHZ (DQ) or begins driving tLZ (DQS), tLZ (DQ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters tLZ (DQS), tLZ (DQ), tHZ (DQS), and tHZ (DQ) are defined as single-ended. Figure 79: Data Strobe Timing - READs RL measured to this point T0 T1 T2 T3 T4 T5 T6 CK CK# tDQSCK (MIN) tLZ (DQS) MIN tDQSCK (MIN) tQSH tQSL tDQSCK (MIN) tQSH tDQSCK (MIN) tHZ (DQS) MIN tQSL DQS, DQS# early strobe tRPST tRPRE Bit 0 tLZ (DQS) MAX Bit 1 Bit 2 Bit 3 tDQSCK (MAX) Bit 4 Bit 5 tDQSCK (MAX) Bit 6 tDQSCK (MAX) Bit 7 tHZ (DQS) MAX tDQSCK (MAX) tRPST DQS, DQS# late strobe tQSH tRPRE Bit 0 tQSL Bit 1 tQSH Bit 2 tQSL Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 80: Method for Calculating tLZ and tHZ VOH - xmV VTT + 2xmV VOH - 2xmV VTT + xmV tLZ (DQS), tLZ (DQ) tHZ (DQS), tHZ (DQ) T2 T1 VOL + 2xmV VTT - xmV VOL + xmV VTT - 2xmV PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN T2 tLZ (DQS), tLZ (DQ) begin point = 2 x T1 - T2 tHZ (DQS), tHZ (DQ) end point = 2 x T1 - T2 Notes: T1 1. Within a burst, the rising strobe edge is not necessarily fixed at tDQSCK (MIN) or tDQSCK (MAX). Instead, the rising strobe edge can vary between tDQSCK (MIN) and tDQSCK (MAX). 2. The DQS high pulse width is defined by tQSH, and the DQS low pulse width is defined by tQSL. Likewise, tLZ (DQS) MIN and tHZ (DQS) MIN are not tied to tDQSCK (MIN) (early strobe case) and tLZ (DQS) MAX and tHZ (DQS) MAX are not tied to tDQSCK (MAX) (late strobe case); however, they tend to track one another. 3. The minimum pulse width of the READ preamble is defined by tRPRE (MIN). The minimum pulse width of the READ postamble is defined by tRPST (MIN). 139 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 81: tRPRE Timing CK VTT CK# tA tB DQS VTT Single-ended signal provided as background information tC tD VTT DQS# Single-ended signal provided as background information T1 tRPRE begins DQS - DQS# tRPRE 0V T2 tRPRE ends Resulting differential signal relevant for tRPRE specification Figure 82: tRPST Timing CK VTT CK# tA DQS Single-ended signal, provided as background information VTT tB tC tD DQS# VTT Single-ended signal, provided as background information tRPST DQS - DQS# Resulting differential signal relevant for tRPST specification PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN T1 tRPST begins 140 0V T2 tRPST ends Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations WRITE WRITE bursts are initiated with a WRITE command. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst. If auto precharge is not selected, the row will remain open for subsequent accesses. After a WRITE command has been issued, the WRITE burst may not be interrupted. For the generic WRITE commands used in Figure 85 on page 143 through Figure 93 on page 148, auto precharge is disabled. During WRITE bursts, the first valid data-in element is registered on a rising edge of DQS following the WRITE latency (WL) clocks later and subsequent data elements will be registered on successive edges of DQS. WRITE latency (WL) is defined as the sum of POSTED CAS ADDITIVE latency (AL) and CAS WRITE latency (CWL): WL = AL + CWL. The values of AL and CWL are programmed in the MR0 and MR2 registers, respectively. Prior to the first valid DQS edge, a full cycle is needed (including a dummy crossover of DQS, DQS#) and specified as the WRITE preamble shown in Figure 85 on page 143. The half cycle on DQS following the last data-in element is known as the WRITE postamble. The time between the WRITE command and the first valid edge of DQS is WL clocks tDQSS. Figure 86 on page 144 through Figure 93 on page 148 show the nominal case where tDQSS = 0ns; however, Figure 85 on page 143 includes tDQSS (MIN) and tDQSS (MAX) cases. Data may be masked from completing a WRITE using data mask. The mask occurs on the DM ball aligned to the write data. If DM is LOW, the write completes normally. If DM is HIGH, that bit of data is masked. Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z, and any additional input data will be ignored. Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide a continuous flow of input data. The new WRITE command can be tCCD clocks following the previous WRITE command. The first data element from the new burst is applied after the last element of a completed burst. Figures 86 and 87 on page 144 show concatenated bursts. An example of nonconsecutive WRITEs is shown in Figure 88 on page 145. Data for any WRITE burst may be followed by a subsequent READ command after tWTR has been met (see Figures 89 and 90 on page 146 and Figure 91 on page 147). Data for any WRITE burst may be followed by a subsequent PRECHARGE command providing tWR has been met, as shown in Figure 92 on page 148 and Figure 93 on page 148. Both tWTR and tWR starting time may vary depending on the mode register settings (fixed BC4, BL8 vs. OTF). PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 141 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 83: tWPRE Timing CK VTT CK# T1 tWPRE begins DQS - DQS# 0V tWPRE T2 tWPRE ends Resulting differential signal relevant for tWPRE specification Figure 84: tWPST Timing CK VTT CK# tWPST DQS - DQS# Resulting differential signal relevant for tWPST specification PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 0V T1 tWPST begins T2 tWPST ends 142 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 85: Write Burst T0 T1 WRITE NOP T2 T3 T4 T5 T6 T7 T8 T9 T10 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command1 WL = AL + CWL Address2 Bank, Col n tDQSS tDSH tDSH tDSH tDSH tWPRE tDQSS (MIN) tWPST DQS, DQS# tDQSH tDQSL tDQSH DI n DQ3 tDQSL DI n+1 tDQSH DI n+2 tDQSL DI n+3 tDSH tDQSH DI n+4 tDQSL DI n+5 tDSH tDQSH DI n+6 tDQSL DI n+7 tDSH tDSH tWPRE tDQSS (NOM) tWPST DQS, DQS# tDQSH tDQSL tDQSH DI n DQ3 tDQSL tDQSH tDSS tDSS DI n+1 tDQSL tDQSH tDSS DI n+2 DI n+3 tDQSL tDQSH tDSS DI n+4 DI n+5 tDQSL tDSS DI n+6 DI n+7 tDQSS tWPRE tDQSS (MAX) tWPST DQS, DQS# tDQSH tDQSL tDQSH tDSS DI n DQ3 tDQSL tDQSH tDSS DI n+1 tDQSL tDQSH tDSS DI n+2 DI n+3 tDQSL tDQSH tDSS DI n+4 DI n+5 tDQSL tDSS DI n+6 DI n+7 Transitioning Data Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Don't Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE command at T0. 3. DI n = data-in for column n. 4. BL8, WL = 5 (AL = 0, CWL = 5). 5. tDQSS must be met at each rising clock edge. 6. tWPST is usually depicted as ending at the crossing of DQS, DQS#; however, tWPST actually ends when DQS no longer drives LOW and DQS# no longer drives HIGH. 143 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Figure 86: Consecutive WRITE (BL8) to WRITE (BL8) T0 T1 WRITE NOP T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP tBL = 4 clocks NOP NOP T14 CK# CK Command1 tCCD NOP tWR tWTR Address2 Valid Valid tWPST tWPRE DQS, DQS# DI n DQ3 DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 WL = 5 WL = 5 Transitioning Data Notes: Don't Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE commands at T0 and T4. 3. DI n (or b) = data-in for column n (or column b). 4. BL8, WL = 5 (AL = 0, CWL = 5). Figure 87: Consecutive WRITE (BC4) to WRITE (BC4) via MRS or OTF 144 T0 T1 WRITE NOP T2 T3 T4 T5 T6 T7 T8 T9 T10 NOP NOP WRITE NOP NOP NOP NOP NOP NOP T11 T12 T13 NOP NOP NOP T14 CK# CK Command1 NOP tWR tBL = 4 clocks tWTR Address2 Valid Valid tWPST tWPRE tWPRE tWPST DQS, DQS# DI n DQ3 DI n+1 DI n+2 DI n+3 DI b DI b+1 DI b+2 DI b+3 WL = 5 WL = 5 Transitioning Data Notes: 1. 2. 3. 4. NOP commands are shown for ease of illustration; other commands may be valid at these times. BC4, WL = 5 (AL = 0, CWL = 5). DI n (or b) = data-in for column n (or column b). The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and T4. Don't Care 1Gb: x4, x8, x16 DDR3 SDRAM Operations Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. tCCD PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Figure 88: Nonconsecutive WRITE to WRITE CK# T0 T1 T2 T3 T4 WRITE NOP NOP NOP NOP T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK Command Address WRITE Valid NOP NOP NOP Valid WL = CWL + AL = 7 WL = CWL + AL = 7 DQS, DQS# DI n DQ DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 DM Transitioning Data Notes: 1. 2. 3. 4. Don't Care DI n (or b) = data-in for column n (or column b). Seven subsequent elements of data-in are applied in the programmed order following DO n. Each WRITE command may be to any bank. Shown for WL = 7 (CWL = 7, AL = 0). Figure 89: WRITE (BL8) to READ (BL8) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP T11 Ta0 NOP READ CK# CK 145 Command1 tWTR2 Valid Valid tWPST tWPRE DQS, DQS# DI n DQ4 DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 WL = 5 Indicates a Break in Time Scale Notes: Transitioning Data Don't Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. tWTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write data shown at T9. 3. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and MR0[12] = 1 during the WRITE command at T0. The READ command at Ta0 can be either BC4 or BL8, depending on MR0[1:0] and the A12 status at Ta0. 4. DI n = data-in for column n. 5. RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5). 1Gb: x4, x8, x16 DDR3 SDRAM Operations Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Address3 PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Figure 90: WRITE to READ (BC4 Mode Register Setting) T0 T1 T2 T3 T4 T5 T6 T7 T8 WRITE NOP NOP NOP NOP NOP NOP NOP NOP T9 Ta0 NOP READ CK# CK Command1 tWTR2 Address3 Valid Valid tWPRE tWPST DQS, DQS# DI n DQ4 DI n+1 DI n+2 DI n+3 WL = 5 Indicates a Break in Time Scale Notes: Transitioning Data Don't Care 146 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. tWTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write data shown at T7. 3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0 and the READ command at Ta0. 4. DI n = data-in for column n. 5. BC4 (fixed), WL = 5 (AL = 0, CWL = 5), RL = 5 (AL = 0, CL = 5). 1Gb: x4, x8, x16 DDR3 SDRAM Operations Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Figure 91: WRITE (BC4 OTF) to READ (BC4 OTF) T0 T1 T2 T3 T4 T5 T6 WRITE NOP NOP NOP NOP NOP NOP T7 T8 T9 T10 NOP NOP NOP NOP T11 Tn NOP READ CK# CK Command1 tBL = 4 clocks Address3 tWTR2 Valid Valid tWPST tWPRE DQS, DQS# DI n DQ4 DI n+1 DI n+2 DI n+3 WL = 5 RL = 5 Indicates a Break in Time Scale Notes: 1. 2. 3. Transitioning Data Don't Care 147 NOP commands are shown for ease of illustration; other commands may be valid at these times. controls the WRITE-to-READ delay to the same device and starts after tBL. The BC4 OTF setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and the READ command at Tn. 4. DI n = data-in for column n. 5. BC4, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5). tWTR 1Gb: x4, x8, x16 DDR3 SDRAM Operations Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 92: WRITE (BL8) to PRECHARGE T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 Ta0 Ta1 Command WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP PRE Address Valid CK# CK Valid tWR WL = AL + CWL DQS, DQS# DI n DQ BL8 DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 Indicates a Break in Time Scale Notes: Transitioning Data Don't Care 1. DI n = data-in from column n. 2. Seven subsequent elements of data-in are applied in the programmed order following DO n. 3. Shown for WL = 7 (AL = 0, CWL = 7). Figure 93: WRITE (BC4 Mode Register Setting) to PRECHARGE T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 Ta0 Ta1 Command WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP PRE Address Valid CK# CK Valid tWR WL = AL + CWL DQS, DQS# DI n DQ BC4 DI n+1 DI n+2 DI n+3 Indicates a Break in Time Scale Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Transitioning Data Don't Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The write recovery time (tWR) is referenced from the first rising clock edge after the last write data is shown at T7. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. 3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0. 4. DI n = data-in for column n. 5. BC4 (fixed), WL = 5, RL = 5. 148 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 94: WRITE (BC4 OTF) to PRECHARGE T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP Tn CK# CK Command1 PRE tWR2 Address3 Bank, Col n Valid tWPST tWPRE DQS, DQS# DI n DQ4 DI n+1 DI n+2 DI n+3 WL = 5 Indicates a Break In Time Scale Notes: Transitioning Data Don't Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The write recovery time (tWR) is referenced from the rising clock edge at T9. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. 3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0. 4. DI n = data-in for column n. 5. BC4 (OTF), WL = 5, RL = 5. DQ Input Timing Figure 85 on page 143 shows the strobe to clock timing during a WRITE. DQS, DQS# must transition within 0.25tCK of the clock transitions as limited by tDQSS. All data and data mask setup and hold timings are measured relative to the DQS, DQS# crossing, not the clock crossing. The WRITE preamble and postamble are also shown. One clock prior to data input to the DRAM, DQS must be HIGH and DQS# must be LOW. Then for a half clock, DQS is driven LOW (DQS# is driven HIGH) during the WRITE preamble, tWPRE. Likewise, DQS must be kept LOW by the controller after the last data is written to the DRAM during the WRITE postamble, tWPST. Data setup and hold times are shown in Figure 95 on page 149. All setup and hold times are measured from the crossing points of DQS and DQS#. These setup and hold values pertain to data input and data mask input. Additionally, the half period of the data input strobe is specified by tDQSH and tDQSL. Figure 95: Data Input Timing DQS, DQS# tWPRE DQ tDQSH tWPST tDQSL DI b DM tDS tDH Transitioning Data PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 149 Don't Care Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations PRECHARGE Input A10 determines whether one bank or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA[2:0] select the bank. When all banks are to be precharged, inputs BA[2:0] are treated as "Don't Care." After a bank is precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued. SELF REFRESH The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW. The DLL is automatically disabled upon entering self refresh and is automatically enabled and reset upon exiting self refresh. All power supply inputs (including VREFCA and VREFDQ) must be maintained at valid levels upon entry/exit and during self refresh mode operation. VREFDQ may float or not drive VDDQ/2 while in the self refresh mode under certain conditions: * VSS <VrefDQ < VDD is maintained * VREFDQ is valid and stable prior to CKE going back HIGH * The first WRITE operation may not occur earlier than 512 clocks after VREFDQ is valid * All other self refresh mode exit timing requirements are met The DRAM must be idle with all banks in the precharge state (tRP is satisfied and no bursts are in progress) before a self refresh entry command can be issued. ODT must also be turned off before self refresh entry by registering the ODT ball LOW prior to the self refresh entry command (see "On-Die Termination (ODT)" on page 161 for timing requirements). If RTT_NOM and RTT_WR are disabled in the mode registers, ODT can be a "Don't Care." After the self refresh entry command is registered, CKE must be held LOW to keep the DRAM in self refresh mode. After the DRAM has entered self refresh mode, all external control signals, except CKE and RESET#, become "Don't Care." The DRAM initiates a minimum of one REFRESH command internally within the tCKE period when it enters self refresh mode. The requirements for entering and exiting self refresh mode depend on the state of the clock during self refresh mode. First and foremost, the clock must be stable (meeting tCK specifications) when self refresh mode is entered. If the clock remains stable and the frequency is not altered while in self refresh mode, then the DRAM is allowed to exit self refresh mode after tCKESR is satisfied (CKE is allowed to transition HIGH tCKESR later than when CKE was registered LOW). Since the clock remains stable in self refresh mode (no frequency change), tCKSRE and tCKSRX are not required. However, if the clock is altered during self refresh mode (turned-off or frequency change), then tCKSRE and t CKSRX must be satisfied. When entering self refresh mode, tCKSRE must be satisfied prior to altering the clock's frequency. Prior to exiting self refresh mode, tCKSRX must be satisfied prior to registering CKE HIGH. When CKE is HIGH during self refresh exit, NOP or DES must be issued for tXS time. tXS is required for the completion of any internal refresh that is already in progress and must be satisfied before a valid command not requiring a locked DLL can be issued to the device. tXS is also the earliest time self refresh reentry may occur (see Figure 96 on page 151). Before a command requiring a locked DLL can be applied, a ZQCL command must be issued, tZQOPER timing must be met, and tXSDLL must be satisfied. ODT must be off during tXSDLL. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 150 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 96: Self Refresh Entry/Exit Timing T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Td0 Te0 Tf0 Valid Valid CK# CK tCKSRX1 tCKSRE1 tIS tIH tCPDED tIS CKE tCKESR (MIN)1 tIS ODT2 Valid ODTL RESET#2 Command SRE (REF)3 NOP NOP4 SRX (NOP) NOP5 Address Valid6 Valid7 Valid Valid tXS6, 9 tRP8 tXSDLL7, 9 Enter self refresh mode (synchronous) Exit self refresh mode (asynchronous) Indicates a Break in Time Scale Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Don't Care 1. The clock must be valid and stable meeting tCK specifications at least tCKSRE after entering self refresh mode, and at least tCKSRX prior to exiting self refresh mode, if the clock is stopped or altered between states Ta0 and Tb0. If the clock remains valid and unchanged from entry and during self refresh mode, then tCKSRE and tCKSRX do not apply; however, tCKESR must be satisfied prior to exiting at SRX. 2. ODT must be disabled and RTT off prior to entering self refresh at state T1. If both RTT_NOM and RTT_WR are disabled in the mode registers, ODT can be a "Don't Care." 3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW. 4. A NOP or DES command is required at T2 after the SRE command is issued prior to the inputs becoming "Don't Care." 5. NOP or DES commands are required prior to exiting self refresh mode until state Te0. 6. tXS is required before any commands not requiring a locked DLL. 7. tXSDLL is required before any commands requiring a locked DLL. 8. The device must be in the all banks idle state prior to entering self refresh mode. For example, all banks must be precharged, tRP must be met, and no data bursts can be in progress. 9. Self refresh exit is asynchronous; however, tXS and tXSDLL timings start at the first rising clock edge where CKE HIGH satisfies tISXR at Tc1. tCKSRX timing is also measured so that t ISXR is satisfied at Tc1. 151 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Extended Temperature Usage Micron's DDR3 SDRAM support the optional extended temperature range of 0C to 95C, TC. Thus, the SRT and ASR options must be used at a minimum. The extended temperature range DRAM must be refreshed externally at 2X (double refresh) anytime the case temperature is above 85C (and does not exceed 95C). The external refreshing requirement is accomplished by reducing the refresh period from 64ms to 32ms. However, self refresh mode requires either ASR or SRT to support the extended temperature. Thus either ASR or SRT must be enabled when TC is above 85C or self refresh cannot be used until the case temperature is at or below 85C. Table 72 summarizes the two extended temperature options and Table 73 summarizes how the two extended temperature options relate to one another. Table 72: Field Self Refresh Temperature and Auto Self Refresh Description MR2 Bits Description Self Refresh Temperature (SRT) SRT 7 If ASR is disabled (MR2[6] = 0), SRT must be programmed to indicate TOPER during self refresh: *MR2[7] = 0: Normal operating temperature range (0C to 85C) *MR2[7] = 1: Extended operating temperature range (0C to 95C) If ASR is enabled (MR2[7] = 1), SRT must be set to 0, even if the extended temperature range is supported *MR2[7] = 0: SRT is disabled Auto Self Refresh (ASR) ASR Table 73: 6 When ASR is enabled, the DRAM automatically provides SELF REFRESH power management functions, (refresh rate for all supported operating temperature values) * MR2[6] = 1: ASR is enabled (M7 must = 0) When ASR is not enabled, the SRT bit must be programmed to indicate TOPER during SELF REFRESH operation * MR2[6] = 0: ASR is disabled, must use manual self refresh temperature (SRT) Self Refresh Mode Summary MR2[6] MR2[7] (ASR) (SRT) SELF REFRESH Operation Permitted Operating Temperature Range for Self Refresh Mode 0 0 Self refresh mode is supported in the normal temperature range Normal (0C to 85C) 0 1 Self refresh mode is supported in normal and extended temperature ranges; When SRT is enabled, it increases self refresh power consumption Normal and extended (0C to 95C) 1 0 Self refresh mode is supported in normal and extended temperature ranges; Self refresh power consumption may be temperature-dependent Normal and extended (0C to 95C) 1 1 Illegal PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 152 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Power-Down Mode Power-down is synchronously entered when CKE is registered LOW coincident with a NOP or DES command. CKE is not allowed to go LOW while either an MRS, MPR, ZQCAL, READ, or WRITE operation is in progress. CKE is allowed to go LOW while any of the other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge, or REFRESH) are in progress. However, the power-down IDD specifications are not applicable until such operations have been completed. Depending on the previous DRAM state and the command issued prior to CKE going LOW, certain timing constraints must be satisfied (as noted in Table 74). Timing diagrams detailing the different power-down mode entry and exits are shown in Figure 97 on page 154 through Figure 106 on page 159. Table 74: Command to Power-Down Entry Parameters Last Command Prior to CKE LOW1 Parameter (Min) Parameter Value Figure ACTIVATE tACTPDEN 1tCK Figure 104 on page 158 Idle or active PRECHARGE tPRPDEN 1tCK Figure 105 on page 158 Active READ or READAP tRDPDEN RL + 4tCK + 1tCK Active WRITE: BL8OTF, BL8MRS, BC4OTF tWRPDEN Active WRITE: BC4MRS Active WRITEAP: BL8OTF, BL8MRS, BC4OTF Active WRITEAP: BC4MRS DRAM Status Idle or active tWRAPDEN REFRESH tREFPDEN Power-down REFRESH tXPDLL Idle MODE REGISTER SET tMRSPDEN Idle Notes: WL + 4tCK + tWR/tCK Figure 100 on page 156 Figure 101 on page 156 WL + 2tCK + tWR/tCK Figure 101 on page 156 WL + 4tCK + WR + 1tCK Figure 102 on page 157 WL + 2tCK + WR + 1tCK Figure 102 on page 157 1tCK Figure 103 on page 157 Greater of 10tCK tMOD or 24ns Figure 107 on page 159 Figure 106 on page 159 1. If slow-exit mode precharge power-down is enabled and entered, ODT becomes asynchronous tANPD prior to CKE going LOW and remains asynchronous until tANPD + tXPDLL after CKE goes HIGH. Entering power-down disables the input and output buffers, excluding CK, CK#, ODT, CKE, and RESET#. NOP or DES commands are required until tCPDED has been satisfied, at which time all specified input/output buffers will be disabled. The DLL should be in a locked state when power-down is entered for the fastest power-down exit timing. If the DLL is not locked during power-down entry, the DLL must be reset after exiting powerdown mode for proper READ operation as well as synchronous ODT operation. During power-down entry, if any bank remains open after all in-progress commands are complete, the DRAM will be in active power-down mode. If all banks are closed after all in-progress commands are complete, the DRAM will be in precharge power-down mode. Precharge power-down mode must be programmed to exit with either a slow exit mode or a fast exit mode. When entering precharge power-down mode, the DLL is turned off in slow exit mode or kept on in fast exit mode. The DLL remains on when entering active power-down as well. ODT has special timing constraints when slow exit mode precharge power-down is enabled and entered. Refer to "Asynchronous ODT Mode" on page 173 for detailed ODT usage requirements in slow exit mode precharge power-down. A summary of the two power-down modes is listed in Table 75 on page 154. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 153 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable clock signal must be maintained. ODT must be in a valid state but all other input signals are a "Don't Care." If RESET# goes LOW during power-down, the DRAM will switch out of power-down mode and go into the reset state. After CKE is registered LOW, CKE must remain LOW until tPD (MIN) has been satisfied. The maximum time allowed for powerdown duration is tPD (MAX) (9 x tREFI). The power-down states are synchronously exited when CKE is registered HIGH (with a required NOP or DES command). CKE must be maintained HIGH until tCKE has been satisfied. A valid, executable command may be applied after power-down exit latency, t XP tXPDLL have been satisfied. A summary of the power-down modes is listed in Table 75. For certain CKE-intensive operations, for example, repeating a power-down exit to refresh to power-down entry sequence, the number of clock cycles between power-down exit and power-down entry may not be sufficient enough to keep the DLL properly updated. In addition to meeting tPD when the REFRESH command is used in between power-down exit and power-down entry, two other conditions must be met. First, tXP must be satisfied before issuing the REFRESH command. Second, tXPDLL must be satisfied before the next power-down may be entered. An example is shown in Figure 107 on page 159. Table 75: Power-Down Modes DRAM State MR1[12] DLL State Power-Down Exit Relevant Parameters Active (any bank open) "Don't Care" On Fast tXP Precharged (all banks precharged) 1 On Fast tXP 0 Off Slow tXPDLL to commands that require the DLL to be locked to any other valid command to any other valid command (READ, RDAP, or ODT on) tXP to any other valid command Figure 97: Active Power-Down Entry and Exit T0 T1 T2 Ta1 Ta2 Ta3 Ta4 NOP NOP NOP Valid Ta0 CK# CK Command tCK tCH tCL NOP Valid NOP tPD tIS CKE Address tIH tIH tIS tCKE (MIN) Valid Valid tXP tCPDED Enter power-down mode Exit power-down mode Indicates a Break in Time Scale PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 154 Don't Care Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 98: Precharge Power-Down (Fast-Exit Mode) Entry and Exit T0 T1 T2 T4 T5 NOP NOP T3 Ta0 Ta1 NOP Valid CK# CK tCK tCH Command tCL NOP NOP tCPDED tCKE (MIN) tIH tIS tCKEmin CKE tCKEmin tIS tXP tPD Enter power-down mode Exit power-down mode Indicates a Break in Time Scale Don't Care Figure 99: Precharge Power-Down (Slow-Exit Mode) Entry and Exit T0 T1 T2 T3 T4 Ta NOP NOP Ta1 Tb CK# CK Command tCK tCH PRE tCL NOP NOP Valid1 Valid2 tCKE (MIN) tCPDED tXP tIS tIH CKE tIS tXPDLL tPD Enter power-down mode Exit power-down mode Indicates a Break in Time Scale Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Don't Care 1. Any valid command not requiring a locked DLL. 2. Any valid command requiring a locked DLL. 155 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 100: Power-Down Entry After READ or READ with Auto Precharge (RDAP) CK# T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 READ/ RDAP NOP NOP NOP NOP NOP NOP NOP NOP Ta7 Ta8 Ta9 Ta10 Ta11 Ta12 CK Command NOP tIS NOP tCPDED CKE Address Valid tPD RL = AL + CL DQS, DQS# DQ BL8 DI n DI DI n+1 n+2 DQ BC4 DI n DI n+1 DI n+3 DI n+4 DI n+ 5 DI n+6 DI n+7 DI DI n+2 n+3 tRDPDEN Power-down or self refresh entry Indicates a Break In Time Scale Transitioning Data Don't Care Figure 101: Power-Down Entry After WRITE CK# T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Tb1 Tb2 Tb3 Tb4 CK Command NOP tIS NOP tCPDED CKE Address Valid tWR WL = AL + CWL tPD DQS, DQS# DQ BL8 DI n DI DI n+1 n+2 DI n+3 DQ BC4 DI n DI n+1 DI n+3 DI n+2 DI n+4 DI DI n+5 n+6 DI n+7 tWRPDEN Power-down or self refresh entry1 Indicates A Break in Time Scale Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Transitioning Data Don't Care 1. CKE can go LOW 2tCK earlier if BC4MRS. 156 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 102: Power-Down Entry After WRITE with Auto Precharge (WRAP) CK# T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1 Tb2 WRAP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Tb3 Tb4 CK Command tCPDED tIS CKE Address Valid A10 tPD WR1 WL = AL + CWL DQS, DQS# DQ BL8 DI n DI n+1 DI DI DI n+2 n+3 n+4 DQ BC4 DI n DI n+1 DI DI n+2 n+3 DI n+5 DI n+6 DI n+7 tWRAPDEN Power-down or self refresh entry2 Start internal precharge Indicates a Break in Time Scale Transitioning Data Don't Care 1. tWR is programmed through MR0[11:9] and represents tWR (MIN)ns/tCK rounded up to the next integer tCK. 2. CKE can go LOW 2tCK earlier if BC4MRS. Notes: Figure 103: REFRESH to Power-Down Entry T0 T1 T2 T3 Ta0 NOP NOP Ta1 Ta2 Tb0 CK# CK tCK Command tCH tCL REFRESH NOP tCPDED NOP Valid tCKE (MIN) tPD tIS CKE tXP (MIN) tREFPDEN tRFC (MIN)1 Indicates a Break In Time Scale Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN Don't Care 1. After CKE goes HIGH during tRFC, CKE must remain HIGH until tRFC is satisfied. 157 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 104: ACTIVATE to Power-Down Entry T0 T1 T2 T3 NOP NOP T5 T4 T6 T7 CK# CK tCK Command tCH tCL ACTIVE Address Valid tCPDED tIS tPD CKE tCKE tACTPDEN Don't Care Figure 105: PRECHARGE to Power-Down Entry T0 T1 T2 T3 NOP NOP T4 T5 T6 T7 CK# CK tCK tCH Command Address tCL PRE All/single bank tCPDED tIS tPD CKE tPREPDEN Don't Care PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 158 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 106: MRS Command to Power-Down Entry T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 CK# CK tCK Command MRS Address Valid tCH tCL NOP tCPDED NOP NOP NOP NOP tPD tMRSPDEN tIS CKE Indicates a Break in Time Scale Don't Care Figure 107: Power-Down Exit to Refresh to Power-Down Entry T0 T1 T2 T3 T4 Ta0 NOP REFRESH Ta1 Tb0 CK# CK Command tCK tCH NOP tCL NOP NOP tCPDED NOP NOP tXP1 tIH tIS CKE tIS tPD tXPDLL2 Enter power-down mode Exit power-down mode Enter power-down mode Indicates a Break in Time Scale Notes: Don't Care 1. tXP must be satisfied before issuing the command. 2. tXPDLL must be satisfied (referenced to the registration of power-down exit) before the next power-down can be entered. RESET The RESET signal (RESET#) is an asynchronous signal that triggers any time it drops LOW, and there are no restrictions about when it can go LOW. After RESET# goes LOW, it must remain LOW for 100ns. During this time, the outputs are disabled, ODT (RTT) turns off (High-Z), and the DRAM resets itself. CKE should be brought LOW prior to RESET# being driven HIGH. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power up were executed (see Figure 108 on page 160). All refresh counters on the DRAM are reset, and data stored in the DRAM is assumed unknown after RESET# has gone LOW. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 159 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM Operations Figure 108: RESET Sequence System RESET (warm boot) Stable and valid clock T1 T0 Tc0 Tb0 Ta0 tCK Td0 CK# CK tCL tCL T (MIN) = MAX (10ns, 5tCK) T = 100ns (MIN) RESET# tIOZ T=10ns (MIN) tIS Valid CKE ODT Valid Valid Valid Valid ZQCL Valid tIS MRS MRS MRS MRS Address Code Code Code Code A10 Code Code Code Code BA0 = L BA1 = H BA2 = L BA0 = H BA1 = H BA2 = L BA0 = H BA1 = L BA2 = L BA0 = L BA1 = L BA2 = L Command NOP DM BA[2:0] DQS DQ RTT Valid A10 = H Valid Valid High-Z High-Z High-Z T = 500s (MIN) MR2 All voltage supplies valid and stable tMRD tMRD tXPR MR3 DRAM ready for external commands tMRD MR1 with DLL ENABLE tMOD MR0 with DLL RESET ZQ CAL tZQINIT tDLLK Normal operation Indicates a Break in Time Scale PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D4.fm - Rev G 2/09 EN 160 Don't Care Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) On-Die Termination (ODT) ODT is a feature that enables the DRAM to enable/disable and turn on/off termination resistance for each DQ, DQS, DQS#, and DM for the x4 and x8 configurations (and TDQS, TDQS# for the x8 configuration, when enabled). ODT is applied to each DQ, UDQS, UDQS#, LDQS, LDQS#, UDM, and LDM signal for the x16 configuration. The ODT feature is designed to improve signal integrity of the memory channel by enabling the DRAM controller to independently turn on/off the DRAM's internal termination resistance for any grouping of DRAM devices. The ODT feature is not supported during DLL disable mode. A simple functional representation of the DRAM ODT feature is shown in Figure 109. The switch is enabled by the internal ODT control logic, which uses the external ODT ball and other control information. Figure 109: On-Die Termination ODT To other circuitry such as RCV, ... VDDQ/2 RTT Switch DQ, DQS, DQS#, DM, TDQS, TDQS# Functional Representation of ODT The value of RTT (ODT termination value) is determined by the settings of several mode register bits (see Table 79 on page 164). The ODT ball is ignored while in self refresh mode (must be turned off prior to self refresh entry) or if mode registers MR1 and MR2 are programmed to disable ODT. ODT is comprised of nominal ODT and dynamic ODT modes and either of these can function in synchronous or asynchronous mode (when the DLL is off during precharge power-down or when the DLL is synchronizing). Nominal ODT is the base termination and is used in any allowable ODT state. Dynamic ODT is applied only during writes and provides OTF switching from no RTT or RTT_NOM to RTT_WR. The actual effective termination, RTT_EFF, may be different from the RTT targeted due to nonlinearity of the termination. For RTT_EFF values and calculations, see "ODT Characteristics" on page 52. Nominal ODT ODT (NOM) is the base termination resistance for each applicable ball, it is enabled or disabled via MR1[9, 6, 2] (see Figure 55 on page 115), and it is turned on or off via the ODT ball (see Table 76 on page 162). PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN 161 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Table 76: Truth Table - ODT (Nominal) Note 1 applies to the entire table MR1[9, 6, 2] ODT Pin DRAM Termination State DRAM State Notes 000 0 RTT_NOM disabled, ODT off Any valid 2 000 1 RTT_NOM disabled, ODT on Any valid except self refresh, read 3 000-101 0 RTT_NOM enabled, ODT off Any valid 2 3 000-101 1 RTT_NOM enabled, ODT on Any valid except self refresh, read 110 and 111 X RTT_NOM reserved, ODT on or off Illegal Notes: 1. Assumes dynamic ODT is disabled (see "Dynamic ODT" on page 163 when enabled). 2. ODT is enabled and active during most writes for proper termination, but it is not illegal to have it off during writes. 3. ODT must be disabled during reads. The RTT_NOM value is restricted during writes. Dynamic ODT is applicable if enabled. Nominal ODT resistance RTT_NOM is defined by MR1[9, 6, 2], as shown in Figure 55 on page 115. The RTT_NOM termination value applies to the output pins previously mentioned. DDR3 SDRAM supports multiple RTT_NOM values based on RZQ/n where n can be 2, 4, 6, 8, or 12 and RZQ is 240. RTT_NOM termination is allowed any time after the DRAM is initialized, calibrated, and not performing read access or when it is not in self refresh mode. Write accesses use RTT_NOM if dynamic ODT (RTT_WR) is disabled. If RTT_NOM is used during writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 79 on page 164). ODT timings are summarized in Table 77, as well as listed in Table 54 on page 70. Examples of nominal ODT timing are shown in conjunction with the synchronous mode of operation in "Synchronous ODT Mode" on page 168. Table 77: Symbol ODT Parameter Description Begins at Defined to ODTL on ODT synchronous turn on delay ODT registered HIGH ODTL off ODT synchronous turn off delay ODT registered HIGH RTT_ON tAON RTT_OFF tAOF tAONPD ODT asynchronous turn on delay ODT registered HIGH RTT_ON tAOFPD ODT asynchronous turn off delay ODT registered HIGH RTT_OFF ODTH4 ODT minimum HIGH time after ODT assertion or write (BC4) ODTH8 ODT minimum HIGH time after write (BL8) Write registration with ODT HIGH tAON ODT turn-on relative to ODTL on completion tAOF ODT turn-off relative to ODTL off completion PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN Definition for All DDR3 Speed Bins Units CWL + AL - 2 tCK CWL + AL - 2 tCK 1-9 ns 1-9 ns 4tCK t ODT registered LOW 6tCK t Completion of ODTL on RTT_ON See Table 54 on page 70 ps Completion of ODTL off RTT_OFF 0.5tCK 0.2tCK tCK ODT registered HIGH ODT registered or write registration LOW with ODT HIGH 162 CK CK Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Dynamic ODT In certain application cases, and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command, essentially changing the ODT termination on the fly. With dynamic ODT (RTT_WR) enabled, the DRAM switches from nominal ODT (RTT_NOM) to dynamic ODT (RTT_WR) when beginning a WRITE burst and subsequently switches back to nominal ODT (RTT_NOM) at the completion of the WRITE burst. This requirement is supported by the dynamic ODT feature, as described below: Functional Description The dynamic ODT mode is enabled if either MR2[9] or MR2[10] is set to "1." Dynamic ODT is not supported during DLL disable mode so RTT_WR must be disabled. The dynamic ODT function is described, as follows: * Two RTT values are available--RTT_NOM and RTT_WR: - The value for RTT_NOM is preselected via MR1[9, 6, 2] - The value for RTT_WR is preselected via MR2[10, 9] * During DRAM operation without READ or WRITE commands, the termination is controlled as follows: - Nominal termination strength RTT_NOM is used - Termination on/off timing is controlled via the ODT ball and latencies ODTL on and ODTL off * When a WRITE command (WR, WRAP, WRS4, WRS8, WRAPS4, WRAPS8) is registered, and if dynamic ODT is enabled, the ODT termination is controlled as follows: - A latency of ODTLCNW after the WRITE command: termination strength RTT_NOM switches to RTT_WR - A latency of ODTLCWN8 (for BL8, fixed or OTF) or ODTLCWN4 (for BC4, fixed or OTF) after the WRITE command: termination strength RTT_WR switches back to RTT_NOM - On/off termination timing is controlled via the ODT ball and determined by ODTL on, ODTL off, ODTH4, and ODTH8 - During the tADC transition window, the value of RTT is undefined ODT is constrained during writes and when dynamic ODT is enabled (see Table 78). ODT timings listed in Table 77 on page 162 also apply to dynamic ODT mode. Table 78: Dynamic ODT Specific Parameters Definition for All DDR3 Speed Bins Units RTT switched from RTT_NOM to RTT_WR WL - 2 tCK Write registration RTT switched from RTT_WR to RTT_NOM 4tCK + ODTL off t Change from RTT_WR to RTT_NOM (BL8) Write registration RTT switched from RTT_WR to RTT_NOM 6tCK + ODTL off tCK RTT change skew ODTLCNW completed RTT transition complete 0.5tCK 0.2tCK tCK Symbol Description Begins at Defined to ODTLCNW Change from RTT_NOM to RTT_WR Write registration ODTLCWN4 Change from RTT_WR to RTT_NOM (BC4) ODTLCWN8 tADC PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN 163 CK Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Mode Registers for RTT_NOM Table 79: MR1 (RTT_NOM) M9 M6 M2 RTT_NOM (RZQ) RTT_NOM (Ohms) RTT_NOM Mode Restriction 0 0 0 Off Off n/a 0 0 1 RZQ/4 60 Self refresh 0 1 0 RZQ/2 120 0 1 1 RZQ/6 40 1 0 0 RZQ/12 20 1 0 1 RZQ/8 30 1 1 0 Reserved Reserved n/a 1 1 1 Reserved Reserved n/a 1. RZQ = 240. If RTT_NOM is used during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed. Notes: Table 80: Self refresh, write Mode Registers for RTT_WR MR2 (RTT_WR) RTT_WR (RZQ) RTT_WR (Ohms) M10 M9 0 0 Dynamic ODT off: WRITE does not affect RTT_NOM 0 1 RZQ/4 60 1 0 RZQ/2 120 1 1 Reserved Reserved n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a Table 81: Timing Diagrams for Dynamic ODT Figure and Page Title Figure 110 on page 165 Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 Figure 111 on page 165 Dynamic ODT: Without WRITE Command Figure 112 on page 166 Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 Figure 113 on page 167 Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 Figure 114 on page 167 Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN 164 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN Figure 110: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 NOP NOP NOP NOP WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command Address Valid ODTH4 ODTL off ODTH4 ODT ODTL on ODTLCWN4 tADC (MIN) tAON (MIN) RTT tADC (MIN) RTT_NOM tAOF (MIN) RTT_WR tAON (MAX) RTT_NOM tAOF (MAX) tADC (MAX) tADC (MAX) ODTLCNW DQS, DQS# DQ DI n WL DI n+1 DI n+2 DI n+3 Transitioning Notes: Don't Care 1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM and RTT_WR are enabled. 2. ODTH4 applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example, ODTH4 is satisfied if ODT goes LOW at T8 (four clocks after the WRITE command). 165 Figure 111: Dynamic ODT: Without WRITE Command Command T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Address ODTH4 ODTL on ODTL off ODT tAON (MAX) tAOF (MIN) RTT_NOM RTT tAON (MIN) tAOF (MAX) DQS, DQS# DQ Transitioning Notes: Don't Care 1. AL = 0, CWL = 5. RTT_NOM is enabled and RTT_WR is either enabled or disabled. 2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW; in this example, ODTH4 is satisfied. ODT registered LOW at T5 is also legal. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. CK# CK PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN Figure 112: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 T0 T1 T2 NOP WRS8 NOP T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command ODTLCNW Address Valid ODTH8 ODTLOFF ODTLON ODT tADC (MAX) tAOF (MIN) RTT_WR RTT tAON (MIN) tAOF (MAX) ODTLCWN8 DQS, DQS# WL DI b DQ DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 166 Transitioning Notes: Don't Care 1. Via MRS or OTF; AL = 0, CWL = 5. If RTT_NOM can be either enabled or disabled, ODT can be HIGH. RTT_WR is enabled. 2. In this example, ODTH8 = 6 is satisfied exactly. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Figure 113: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 T0 T1 T2 NOP WRS4 NOP T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command ODTLCNW Address Valid ODTH4 ODTL off ODT ODTL on tADC (MAX) RTT tAOF (MIN) tADC (MIN) RTT_WR RTT_NOM tAON (MIN) tADC (MAX) tAOF (MAX) ODTLCWN4 DQS, DQS# DI n DQ DI n+1 DI n+2 DI n+3 WL Transitioning Notes: Don't Care 1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM and RTT_WR are enabled. 2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example, ODTH4 is satisfied. ODT registered LOW at T5 is also legal. Figure 114: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 T0 T1 T2 NOP WRS4 NOP T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command ODTLCNW Address Valid ODTL off ODTH4 ODT tAOF (MIN) tADC (MAX) ODTL on RTT R_TTWR _WR RTT tAON (MIN) tAOF (MAX) ODTLCWN4 DQS, DQS# WL DI n DQ DI n+1 DI n+2 DI n+3 Transitioning Notes: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN Don't Care 1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM can be either enabled or disabled. If disabled, ODT can remain HIGH. RTT_WR is enabled. 2. In this example ODTH4 = 4 is satisfied exactly. 167 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Synchronous ODT Mode Synchronous ODT mode is selected whenever the DLL is turned on and locked and when either RTT_NOM or RTT_WR is enabled. Based on the power-down definition, these modes are: * Any bank active with CKE HIGH * Refresh mode with CKE HIGH * Idle mode with CKE HIGH * Active power-down mode (regardless of MR0[12]) * Precharge power-down mode if DLL is enabled during precharge power-down by MR0[12] ODT Latency and Posted ODT In synchronous ODT mode, RTT turns on ODTL on clock cycles after ODT is sampled HIGH by a rising clock edge and turns off ODTL off clock cycles after ODT is registered LOW by a rising clock edge. The actual on/off times varies by tAON and tAOF around each clock edge (see Table 82 on page 169). The ODT latency is tied to the WRITE latency (WL) by ODTL on = WL - 2 and ODTL off = WL - 2. Since write latency is made up of CAS WRITE latency (CWL) and ADDITIVE latency (AL), the AL programmed into the mode register (MR1[4, 3]) also applies to the ODT signal. The DRAM's internal ODT signal is delayed a number of clock cycles defined by the AL relative to the external ODT signal. Thus ODTL on = CWL + AL - 2 and ODTL off = CWL + AL - 2. Timing Parameters Synchronous ODT mode uses the following timing parameters: ODTL on, ODTL off, ODTH4, ODTH8, tAON, and tAOF (see Table 82 and Figure 115 on page 169). The minimum RTT turn-on time (tAON [MIN]) is the point at which the device leaves High-Z and ODT resistance begins to turn on. Maximum RTT turn-on time (tAON [MAX]) is the point at which ODT resistance is fully on. Both are measured relative to ODTL on. The minimum RTT turn-off time (tAOF [MIN]) is the point at which the device starts to turn off ODT resistance. Maximum RTT turn off time (tAOF [MAX]) is the point at which ODT has reached High-Z. Both are measured from ODTL off. When ODT is asserted, it must remain HIGH until ODTH4 is satisfied. If a WRITE command is registered by the DRAM with ODT HIGH, then ODT must remain HIGH until ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (see Figure 116 on page 170). ODTH4 and ODTH8 are measured from ODT registered HIGH to ODT registered LOW or from the registration of a WRITE command until ODT is registered LOW. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN 168 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN Table 82: Synchronous ODT Parameters Symbol Description Begins at Definition for All DDR3 Speed Bins Defined to Units ODT registered HIGH RTT_ON AON CWL + AL - 2 t ODT synchronous turn-off delay ODT registered HIGH RTT_OFF tAOF CWL + AL - 2 tCK ODTH4 ODT minimum HIGH time after ODT assertion or WRITE (BC4) ODT registered HIGH, or write registration with ODT HIGH ODT registered LOW 4tCK tCK ODTH8 ODT minimum HIGH time after WRITE (BL8) Write registration with ODT HIGH ODT registered LOW 6tCK tCK tAON ODT turn-on relative to ODTL on completion Completion of ODTL on RTT_ON See Table 54 on page 70 ps tAOF ODT turn-off relative to ODTL off completion Completion of ODTL off RTT_OFF 0.5tCK 0.2tCK tCK ODTL on ODT synchronous turn-on delay ODTL off t CK Figure 115: Synchronous ODT T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 CK# CK 169 CKE AL = 3 AL = 3 CWL - 2 ODT ODTL off = CWL + AL - 2 ODTL on = CWL + AL - 2 tAON (MIN) RTT tAOF (MIN) RTT_NOM tAOF (MAX) tAON (MAX) Transitioning Notes: 1. AL = 3; CWL = 5; ODTL on = WL = 6.0; ODTL off = WL - 2 = 6. RTT_NOM is enabled. Don't Care 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. ODTH4 (MIN) PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN Figure 116: Synchronous ODT (BC4) T0 T1 T2 T3 T4 T5 T6 T7 NOP NOP NOP NOP NOP NOP NOP WRS4 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK CKE Command ODTH4 ODTH4 (MIN) ODTH4 ODT ODTLoff = WL - 2 ODTL off = WL - 2 ODTL on = WL - 2 ODTL on = WL - 2 tAON (MIN) RTT tAOF (MIN) tAON (MAX) RTT_NOM tAON (MAX) tAOF (MIN) RTT_NOM tAOF (MAX) tAOF (MAX) tAON (MIN) Transitioning Notes: Don't Care 170 1. 2. 3. 4. WL = 7. RTT_NOM is enabled. RTT_WR is disabled. ODT must be held HIGH for at least ODTH4 after assertion (T1). ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (T7). ODTH is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of the WRITE command with ODT HIGH to ODT registered LOW. 5. Although ODTH4 is satisfied from ODT registered HIGH at T6, ODT must not go LOW before T11 as ODTH4 must also be satisfied from the registration of the WRITE command at T7. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) ODT Off During READs As the DDR3 SDRAM cannot terminate and drive at the same time, RTT must be disabled at least one-half clock cycle before the READ preamble by driving the ODT ball LOW (if either RTT_NOM or RTT_WR is enabled). RTT may not be enabled until the end of the postamble as shown in the example in Figure 117 on page 172. Note: PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN ODT may be disabled earlier and enabled later than shown in Figure 117 on page 172. 171 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN Figure 117: ODT During READs T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 Command READ NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Address Valid CK# CK ODTL on = CWL + AL - 2 ODTL off = CWL + AL - 2 ODT tAOF (MIN) RTT RTT_NOM RL = AL + CL RTT_NOM tAOF (MAX) tAON (MAX) DQS, DQS# DQ DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 Transitioning Notes: Don't Care 1. ODT must be disabled externally during READs by driving ODT LOW. For example, CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTL on = CWL + AL - 2 = 8; ODTL off = CWL + AL - 2 = 8. RTT_NOM is enabled. RTT_WR is a "Don't Care." 172 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Asynchronous ODT Mode Asynchronous ODT mode is available when the DRAM runs in DLL on mode and when either RTT_NOM or RTT_WR is enabled; however, the DLL is temporarily turned off in precharged power-down standby (via MR0[12]). Additionally, ODT operates asynchronously when the DLL is synchronizing after being reset. See "Power-Down Mode" on page 153 for definition and guidance over power-down details. In asynchronous ODT timing mode, the internal ODT command is not delayed by AL relative to the external ODT command. In asynchronous ODT mode, ODT controls RTT by analog time. The timing parameters tAONPD and tAOFPD (see Table 83 on page 174) replace ODTL on/tAON and ODTL off/tAOF, respectively, when ODT operates asynchronously (see Figure 118 on page 174). The minimum RTT turn-on time (tAONPD [MIN]) is the point at which the device termination circuit leaves High-Z and ODT resistance begins to turn on. Maximum RTT turnon time (tAONPD [MAX]) is the point at which ODT resistance is fully on. tAONPD (MIN) and tAONPD (MAX) are measured from ODT being sampled HIGH. The minimum RTT turn-off time (tAOFPD [MIN]) is the point at which the device termination circuit starts to turn off ODT resistance. Maximum RTT turn-off time (tAOFPD [MAX]) is the point at which ODT has reached High-Z. tAOFPD (MIN) and tAOFPD (MAX) are measured from ODT being sampled LOW. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN 173 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN Figure 118: Asynchronous ODT Timing with Fast ODT Transition T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 CK# CK CKE tIH tIS tIH tIS ODT tAOFPD (MIN) tAONPD (MIN) RTT RTT_NOM tAONPD (MAX) tAOFPD (MAX) Transitioning Notes: Table 83: Don't Care 1. AL is ignored. Asynchronous ODT Timing Parameters for All Speed Bins Symbol Description tAONPD Min Max Units tAOFPD Asynchronous RTT turn-on delay (power-down with DLL off) 2 8.5 ns Asynchronous RTT turn-off delay (power-down with DLL off) 2 8.5 ns 174 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) There is a transition period around power-down entry (PDE) where the DRAM's ODT may exhibit either synchronous or asynchronous behavior. This transition period occurs if the DLL is selected to be off when in precharge power-down mode by the setting MR0[12] = 0. Power-down entry begins tANPD prior to CKE first being registered LOW, and it ends when CKE is first registered LOW. tANPD is equal to the greater of ODTL off + 1tCK or ODTL on + 1tCK. If a REFRESH command has been issued, and it is in progress when CKE goes LOW, power-down entry will end tRFC after the REFRESH command rather than when CKE is first registered LOW. Power-down entry will then become the greater of tANPD and tRFC - REFRESH command to CKE registered LOW. ODT assertion during power-down entry results in an RTT change as early as the lesser of tAONPD (MIN) and ODTL on x tCK + tAON (MIN) or as late as the greater of tAONPD (MAX) and ODTL on x tCK + tAON (MAX). ODT de-assertion during power-down entry may result in an RTT change as early as the lesser of tAOFPD (MIN) and ODTL off x tCK + tAOF (MIN) or as late as the greater of tAOFPD (MAX) and ODTL off x tCK + tAOF (MAX). Table 84 on page 176 summarizes these parameters. If the AL has a large value, the uncertainty of the state of RTT becomes quite large. This is because ODTL on and ODTL off are derived from the WL and WL is equal to CWL + AL. Figure 119 on page 176 shows three different cases: * ODT_A: Synchronous behavior before tANPD * ODT_B: ODT state changes during the transition period with tAONPD (MIN) less than ODTL on x tCK + tAON (MIN) and tAONPD (MAX) greater than ODTL on x tCK + tAON (MAX) * ODT_C: ODT state changes after the transition period with asynchronous behavior PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN 175 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN Table 84: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period Description Min Max Greater of: tANPD or tRFC - refresh to CKE LOW Power-down entry transition period (power-down entry) tANPD Power-down exit transition period (power-down exit) + tXPDLL ODT to RTT turn-on delay (ODTL on = WL - 2) Lesser of: tAONPD (MIN) (1ns) or ODTL on x tCK + tAON (MIN) Greater of: tAONPD (MAX) (9ns) or ODTL on x tCK + tAON (MAX) ODT to RTT turn-off delay (ODTL off = WL - 2) Lesser of: tAOFPD (MIN) (1ns) or ODTL off x tCK + tAOF (MIN) Greater of: tAOFPD (MAX) (9ns) or ODTL off x tCK + tAOF (MAX) tANPD WL - 1 (greater of ODTL off + 1 or ODTL on + 1) Figure 119: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 Ta0 Ta1 Ta2 Ta3 NOP REF NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK CKE Command tRFC (MIN) tANPD PDE transition period 176 ODT A synchronous tAOF (MIN) DRAM RTT A synchronous RTT_NOM ODTL off tAOF (MAX) tAOFPD (MAX) tAOFPD (MIN) DRAM RTT B asynchronous or synchronous RTT_NOM ODTL off + tAOFPD (MAX) ODT C asynchronous tAOFPD (MIN) DRAM RTT C asynchronous RTT_NOM tAOFPD (MAX) Indicates a Break In Time Scale Notes: 1. AL = 0; CWL = 5; ODTL off = WL - 2 = 3. Transitioning Don't Care 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. ODT B asynchronous or synchronous ODTL off + tAOFPD (MIN) 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) The DRAM's ODT may exhibit either asynchronous or synchronous behavior during power-down exit (PDX). This transition period occurs if the DLL is selected to be off when in precharge power-down mode by setting MR0[12] to "0." Power-down exit begins tANPD prior to CKE first being registered HIGH, and it ends tXPDLL after CKE is first registered HIGH. tANPD is equal to the greater of ODTL off + 1tCK or ODTL on + 1tCK. The transition period is tANPD plus tXPDLL. ODT assertion during power-down exit results in an RTT change as early as the lesser of tAONPD (MIN) and ODTL on x tCK + tAON (MIN) or as late as the greater of tAONPD (MAX) and ODTL on x tCK + tAON (MAX). ODT de-assertion during power- down exit may result in an RTT change as early as the lesser of tAOFPD (MIN) and ODTL off x tCK + tAOF (MIN) or as late as the greater of tAOFPD (MAX) and ODTL off x tCK + tAOF (MAX). Table 84 on page 176 summarizes these parameters. If the AL has a large value, the uncertainty of the RTT state becomes quite large. This is because ODTL on and ODTL off are derived from the WL, and WL is equal to CWL + AL. Figure 120 on page 178 shows three different cases: * ODT C: asynchronous behavior before tANPD * ODT B: ODT state changes during the transition period, with tAOFPD (MIN) less than ODTL off x tCK + tAOF (MIN) and ODTL off x tCK + tAOF (MAX) greater than tAOFPD (MAX) * ODT A: ODT state changes after the transition period with synchronous response PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN 177 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN Figure 120: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 NOP NOP NOP NOP NOP Ta6 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Td0 Td1 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK CKE COMMAND tXPDLL tANPD PDX transition period ODT A asynchronous DRAM RTT A asynchronous tAOFPD (MIN) RTT_NOM ODTL off + tAOF (MIN) tAOFPD (MAX) ODT B asynchronous or synchronous RTT B asynchronous or synchronous tAOFPD (MAX) tAOFPD (MIN) RTT_NOM ODTL off + tAOF (MAX) ODTL off ODT C synchronous tAOF (MAX) tAOF (MIN) DRAM RTT C synchronous RTT_NOM 178 Indicates A Break in Time Scale Notes: Transitioning Don't Care 1. CL = 6; AL = CL - 1; CWL = 5; ODTL off = WL - 2 = 8. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) If the time in the precharge power down or idle states is very short (short CKE LOW pulse), the power-down entry and power-down exit transition periods will overlap. When overlap occurs, the response of the DRAM's RTT to a change in the ODT state may be synchronous or asynchronous from the start of the power-down entry transition period to the end of the power-down exit transition period even if the entry period ends later than the exit period (see Figure 121 on page 180). If the time in the idle state is very short (short CKE HIGH pulse), the power-down exit and power-down entry transition periods overlap. When this overlap occurs, the response of the DRAM's RTT to a change in the ODT state may be synchronous or asynchronous from the start of power-down exit transition period to the end of the powerdown entry transition period (see Figure 121 on page 180). PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN 179 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN Figure 121: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Ta0 Ta1 Ta2 Ta3 Ta4 REF NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command CKE PDE transition period tANPD tRFC (MIN) PDX transition period tXPDLL tANPD Short CKE LOW transition period (RTT change asynchronous or synchronous) Indicates a Break in Time Scale 180 Notes: Transitioning Don't Care 1. AL = 0, WL = 5, tANPD = 4. Figure 122: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping T1 T2 T3 T4 T5 T6 T7 T8 T9 Ta0 Ta1 Ta2 Ta3 Ta4 Command NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CKE tANPD tXPDLL tANPD Short CKE HIGH transition period (RTT change asynchronous or synchonous) Indicates A Break in Time Scale Notes: 1. AL = 0, WL = 5, tANPD = 4. Transitioning Don't Care 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. T0 CK# CK 1Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef826aa906/Source: 09005aef82a357c3 DDR3_D5.fm - Rev G 2/09 EN 181 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved.