MicROCHIP 93LC46/56/66 1K/2K/4K 2.0V Microwire Serial EEPROM FEATURES BLOCK DIAGRAM * Single supply with programming operation down to 2.0V (Commercial only) Low power CMOS technology - 1 mA active current typical - 5A standby current (typical) at 3.0V ORG pin selectable memory configuration - 128 x 8 or 64 x 16-bit organization (93LC46) - 256 x 8 or 128 x 16-bit organization(93LC56) - 512 x 8 or 256 x 16-bit organization (93LC66) Self-timed ERASE and WRITE cycles (including auto-erase) Automatic ERAL before WRAL Power on/off data protection circuitry Industry standard 3-wire serial I/O Device status signal during ERASE/WRITE cycles Sequential READ function 10,000,000 ERASE/WRITE cycles guaranteed on 93LC56 and 93LC66 * 1,000,000 EW cycles guaranteed on 93LC46 Data retention > 200 years 8-pin PDIP/SOIC and 14-pin SOIC package (SOIC in JEDEC and EIAJ standards) Temperature ranges supported _ MEMORY ADDRESS ARRAY DECODER ADDRESS COUNTER OUTPUT BUFFER 0 4 DATA REGISTER b MODE DECODE LOGIC cs > CLOCK CLK GENERATOR DESCRIPTION The Microchip Technology Inc. S3LC46/56/66 are 1K, 2K, and 4K low-voltage serial Electrically Erasable PROMs. The device memory is configured as x8 or x16 - Commercial (C): oc to +70C bits, depending on the ORG pin setup. Advanced - Industrial (I): -40C to +85C CMOS technology makes these devices ideal for , low-power, nonvolatile memory applications. The 93LC46/56/66 is available in standard 8-pin DIP and 8/ 14-pin surface mount SOIC packages. The 93LC46X/ 56X/66X are only offered in an "SN package. PACKAGE TYPES soic TT NCcL_|1 14. 9NC DIP soic soic osC? "3| vee 3 O2 12 oO our @ 8 | NU cs sore 4 O00 1 q 222 4 nc gS [INC clLKT] a5 9 7[WVss D5 10[ ORG DID] g38 sf p0s pay 16 3| 4vss por sol nec? 8[ Nc 1997 Microchip Technology Inc. DS11168L-page 1 MCHPS0007393LC46/56/66 1.0 ELECTRICAL CHARACTERISTICS 14 Maximum Ratings* All inputs and outputs wrt Vss .. 0.6V to Vcc +1.0V Storage temperature oe ... BBC to +150C Ambient temp. with power applied.................-65C to +125C Soldering temperature of leads (10 seconds)............. +300C ESD protection on all pins 2.0.0... eee eect eeeeee 4kV Notice: Stresses above those listed under Maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended peri- ods may affect device reliability. PIN tunction Table Name Function cs Chip Select CLK Serial Data Clock DI Serial Data input DO Serial Data Output Vss Ground ORG | Memory Configuration NU Not Utilized NG No Connect Voc Power Supply TABLE 1-1 DC AND AC ELECTRICAL CHARACTERISTICS Commercial (C}: Veco = +2.0V to +6.0V (C): Tamb = O0C to +70C Industrial (|): Veo = +2.5V to +6.0V (I): Tamb = -40C to +85C Parameter Symbol Min. Max. Units Conditions : ViM4 2.0 Veo +1 Vv Vcc>2.7V High level input voltage Ving | 0.7 Veo_| Veo+t Vv [Voo<2.7V Low jevel input voltage Vis 03 08 V Voc > 2.7V ViL2 -03 0.2 Vec Vv Voc <2.7V Low level output voltage VoL _ 0.4 Vv lot = 2.1 mA; Vcc = 4.5V VoL2 _ 02 Vv lol =100 WA; Voc = Vee Min. High level output voltage VoH1 24 _ Vv JOH = -400 pA; Voc = 4.5V VoH2 Vec-0.2 _ Vv IOH = -100 PA; Vcc = Vee Min. input leakage current Iu -10 10 BA VIN = 0.1V to Vcc Output leakage current lLo -10 10 pA VouT = 0.1V to Vcc Pin capacitance CIN, Cout _ 7 pF Vin/VouT = 0 V (Notes 1 & 3) (all inputs/outputs) Tamb = +25C, Fotk = 1 MHz Icc read _ 1 mA FCLK = 2 MHz; Vcc = 6.0V Operating current 500 pA FCLK = 1 MHz; Vcc = 3.0V Icc write _ 3 mA FOLK = 2 MHz; Vcc = 6.0V (Note 3} Standby current Ices 100 pA CLK = CS = OV; Vcc = 6.0V 30 pA CLK = CS = OV; Voc = 3.0V Clock frequency FCLK _ 2 MHz | Vec>4.5V 1 MHz Veo < 4.5V Clock high time TCKH 250 _ ns Clock low time TCKL 250 ns Chip select setup time Tess 50 ns Relative to CLK Chip select hold time TCSH 0 _ ns Relative to CLK Chip select low time Test 250 ns Data input setup time Tois 100 _ ns Relative to CLK Data input hold time TDIH 100 _ ns Relative to CLK Data output delay time TPD 400 ns Ct = 100 pF Data output disable time Tez _ 100 ns Ct = 100 pF (Note 3) Status valid time Tsv _ 500 ns Ci = 100 pF Two _ 10 ms ERASE/WRITE mode (Note 2) Program cycle time i Tec _ 15 ms ERAL mode TWL _ 30 ms WRAL mode Endurance 93LC46 _ 1M _ cycles | 25C, Vcc = 5.0V, Block Mode (Note 4) 93LC56/66 _ 10M _ Note 1: This parameter is tested at Tamb = 25C and Fcuk = 1 MHz. 2: Typical program cycle time is 4 ms per word. 3: This parameter is periodically sampled and not 100% tested. 4: This application is not tested but guaranteed by characterization. For endurancaestimates in a specific applica- tion, please consult the Total Endurance Model which can be obtained on our BBS or website. DS11168L-page 2 1997 Microchip Technology Inc.93LC46/56/66 2.0 PIN DESCRIPTION 2.1 Chip Se cs Ahigh level selects the device. A low level deselects the device and forces it into standby mode. However, a pro- gramming cycle which is already initiated and/or in progress will be completed, regardless of the CS input signal. If CS is brought low during a program cycle, the device will go into standby mode as soon as the pro- gramming cycle is completed. CS must be low for 250 ns minimum (TcsL) between consecutive instructions. If CS is low, the internal con- trol logic is held in a RESET status. 2.2 Serial Clock (CLK) The Serial Clock (CLK) is used to synchronize the com- munication between a master device and the 93LCXX. Cpcodes, addresses, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL). This gives the controlling master freedom in preparing the opcode, address, and data. CLK is a Don't Care if CS is low (device deselected). If CS is high, but the START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for a START condition). CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle. After detecting a START condition, the specified num- ber of clock cycles (respectively low to high transitions of GLK} must be provided. These clock cycles are required to clock in all required opcodes, addresses, and data bits before an instruction is executed (Table 2-1 to Table 2-6). CLK and DI then become don't care inputs waiting for a new START condition to be detected. | Note: GS must go low: bety : . instructions. - x consecutive 2.3 Data In (DI) Data In (Dl) is used to clock in a START bit, opcode, address, and data synchronously with the CLK input. 2.4 Data Out (DO) Data Out (DO) is used in the READ mode to output data synchronously with the CLK input (TPp after the posi- tive edge of CLK). This pin also provides READY/BUSY status information during ERASE and WRITE cycles. READY/BUSY sta- tus information is available on the DO pin if CS is brought high after being low for minimum chip select low time (TCSL) and an ERASE or WRITE operation has been initiated. The status signal is not available on DO, if CS is held low or high during the entire WRITE or ERASE cycle. In all other cases DO is in the HIGH-Z mode. If status is checked alter the ERASE/WRITE cycle, a pull-up resistor on DO is required to read the READY signal. 2.5 Orqanization (O When ORG is tied to Vss, the (x8) memory organiza- tion is selected. When ORG is connected to Vcc or floated, the (x16) memory organization is selected. ORG can only be floated for clock speeds of 1 MHz or less for the (X16) memory organization. For clock speeds greater than 1 MHz, ORG must be tied to Vcc or VSs. 1997 Microchip Technology Inc. DS11168L-page 393LC46/56/66 TABLE 2-1 INSTRUCTION SET FOR 93LC46: ORG = 0 (X 8 ORGANIZATION) Instruction $B Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 W A6 AS A4 A3 A2 Al AG = (RDY/BSY) 10 ERAL 1 00 10x X XK X X (RDY/BSY) 10 EWDS 1 oo oOo xX X X X X HIGH-Z 10 EWEN 1 00 11X xX X X X HIGH-Z 10 READ 1 10 A6 A5 A4 A3 A2 Al AO _ D7 - DO 18 WRITE 1 01 A6 A5 A4 A3 A2 Al AO D7 - DO (RDY/BSY) 18 WRAL 1 00 01X XX X X D7 - DO (RDY/BSY) 18 TABLE 2-2 INSTRUCTION SET FOR 93LC46: ORG = 1 (X 16 ORGANIZATION) Instruction SB Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 11 AS A4 A3 A2 Ai AO = (RDY/BSY) 9 ERAL 1 00 10x XX XxX ~~ (RDY/BSY) g EWDS 1 00 o aX X X X _ HIGH-Z 9 EWEN 1 00 11X XX X _ HIGH-Z 9 READ 1 10 AS A4 AS A2 A1 AO _ 015-Do 25 WRITE 1 | 01 A5 A4 A3 A2 At AO 015 - DO (RDY/BSY) 25 WRAL 1] 00 o 1X X X X Dis - DO (RDY/BSY) 25 TABLE 2-3 INSTRUCTION SET FOR 93LC56: ORG = 0 (X 8 ORGANIZATION) Instruction SB Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 11 X A7 AG AS A4 AB A2 Al AO (RDY/BSY) 12 ERAL 1 00 10% X X XK X X X (RDY/BSY) 12 EWOS 1 00 o aX X X XK X X X HIGH-Z 12 EWEN 4 00 141% XX XK XK XK X _ HIGH-Z 12 READ 1 10 X A7 AB AS A4 A3 A2 Al AO _ D7 - BO 20 WRITE 1 ot X A7 AG AS A4 A3 A2 Ai AO D7 - DO (RDY/BSY) 20 WRAL 1 00 oi1XxX XX XK XK XX 07 - Bo (RDY/BSY) 20 TABLE 2-4 INSTRUCTION SET FOR 93LC56: ORG = 1 (X 16 ORGANIZATION) Instruction SB Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 11 X A6 A5 A4 A3 A2 At AO = (RDY/BSY) 11 ERAL 1 oa 1 0X XX X X xX _ (RDY/BSY) 11 EWDS 1 00 o0oxX XX XX x HIGH-Z 11 EWEN 1 i 00 1 1:X X X XX xX HIGH-Z 11 READ 1 10 X AB A5 A4 A3 A2 Ai AO D15- 00 27 WRITE 1 01 X AB A5 A4 A3 A2 Ai AO 015 - DO (ROY/BSY) 27 WRAL 1 00 0 1X X X X X X Di5- D0 (RDY/BSY) 27 TABLE 2-5 INSTRUCTION SET FOR 93LC66: ORG = 0 (X 8 ORGANIZATION) Instruction SB Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 17 AB A7 A6 A5 A4 A3 A2 Al AO = (RDY/BSY) 12 ERAL 1 oo 10%X XX X X X X _ (RDY/BSY) 12 EWDS 1 00 0 0X X X X X X X _- HIGH-Z 12 EWEN 1 00 1 1X XX XX X X _ HIGH-2Z 12 READ 1 10 A8 A7 AG AS A4 A3 A2 Al AO _ D7 - DO 20 WRITE 1 o1 A8 A7 A6 AS A4 A3 A2 Al AO D7 - DO (RDY/BSY) 20 WRAL 1 00 o1X xX XX X xX X D7 - Bo (RDY/BSY) 20 TABLE 2-6 INSTRUCTION SET FOR 93LC66: ORG = 1 (X 16 ORGANIZATION) Instruction SB , Opcode Address Data in Data Out Req. CLK Cycles READ 1 10 A7 A6 A5 A4 A3 A2 At AO D15 - DO 27 EWEN 1 00 11% XX XK XK X _ High-Z 11 ERASE 1 11 A7 A6 AS A4 A3 Az Al AO _ (RDY/BSY) 11 ERAL 1 a0 10X XX X K X _ (RDY/BSY) aS WRITE 1 01 A7 A6 A5 A4 A3 A2 Ai AO D15- D0 (RDY/BSY) 27 WRAL 1 oo o 1X X X X XK X D15- DO (RDY/BSY) 27 EWDS 1 00 oo XX X X X X High-2 11 DS11168L-page 4 1997 Microchip Technology Inc.93LC46/56/66 3.0 FUNCTIONAL DESCRIPTION When it is connected to ground, the (x8) organization is selected. When the ORG pin is connected to Vcc, the (x16} organization is selected. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state, except when reading data from the device or when checking the READY/BUSY status dur- ing a programming operation. The READY/BUSY status can be verified during an ERASE/WRITE opera- tion by polling the DO pin; DO low indicates that pro- gramming is still in progress, while DO high indicates the device is ready. The DO will enter the HIGH-Z state on the falling edge of the CS. 3.1 START Condition The START bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and Di may change in any combination (except to that of a START condition), without resulting in any device oper- ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL, and WRAL). As soon as CS is high, the device is no longer in the standby mode. An instruction following a START condition will only be executed if the required amount of opcodes, addresses, and data bits for any particular instruction is clocked in. After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new START condition is detected. FIGURE 3-1: SYNCHRONOUS DATA TIMING 3.2 Data In (Dl!) and Data Out (DO) It is possible to connect the Data In (DI) and Data Out (DO) pins together. However, with this configuration, if AO is a logic-high level, it is possible for a bus conflict fo occur during the "dummy zero that precedes the READ operation. Under such a condition the voltage level seen at DO is undefined and will depend upon the relative impedances of Data Out, and the signa! source driving AO. The higher the current sourcing capability of AO, the higher the voltage ai the DO pin. 3.3 Data Protection During power-up, all programming modes of operation are inhibited until Vcc has reached a level greater than 1.4V. During power-down, the source data protection circuitry acts to inhibit all programming modes when Vec has fallen below 1.4V at nominal conditions. The ERASE/WRITE Disable (EWDS) and ERASE/ WRITE Enabie (EWEN) commands give additional pro- tection against accidentally programming during nor- mal operation. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed. ViH cs Vit Vin CLK VIL VIH DI Vit po (READ) vo Do Vou P (PROGRAM) Vou TCSH STATUS VALID 1997 Microchip Technology Inc. DS11168L-page 593LC46/56/66 3.4 ERASE 3.5 Erase All (ERAL) The ERASE instruction forces all data bits of the spec- The Erase All (ERAL) instruction will erase the entire ified address to the logical 1 state. CS is brought low memory array to the logical 1 state. The ERAL cycle following the loading of the last address bit. This falling is identical to the ERASE cycle except for the different edge of the CS pin initiates the self-timed programming opcode. The ERAL cycle is completely self-timed and cycle. commences at the falling edge of the CS. Clocking of in indi AEy the CLK pin is not necessary after the device has The DO pin indicates the READY/BUSY status of the . . a device if CS is brought high after a minimum of 250 ns entered the self clocking mode. The ERAL instruction is low (TCSL). DO at logical "0 indicates that program- guaranteed at Voc = +4.5V to +6.0V. ming is still in progress. DO at logical 1 indicates that The DO pin indicates the READY/BUSY status of the the register at the specified address has been erased device if CS is brought high after a minimum of 250 ns and the device is ready for another instruction. low (TCSL) and before the entire write cycle is complete. The ERASE cycle takes 4 ms per word (Typical). The ERAL cycle takes 15 ms maximum (8 ms typical). FIGURE 3-2: _ERASETIMING Tes. f- <_ C5 cs / *Y STANDBY D1 TED G),Ga co, Co, CANO _ TRI-STATE TRI-STATE FIGURE 3-3: ERAL TIMING Test cs <> _ / STANDBY DI 1 0 0 1 0 et Toz TRESTATE TRI-STATE bo $ s __. Guarantee at Vcc = +4.5V to +6.0V. DS11168L-page 6 1997 Microchip Technology Inc.93LC46/56/66 3.6 ERASE/WRITE Disable and Enable (EWEN, EWDS) The 93LC46/56/66 powers up in the ERASE/WRITE Disable (EWDS) state. Ail programming modes must be preceded by an ERASE/WRITE Enable (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruc- tion is executed or VCC is removed from the device. To protect against accidental data disturb, the EWDS instruction can be used to disable all ERASE/WRITE functions and should follow all programming opera- tions. Execution of a READ instruction is independent of both the EWDS and EWEN instructions. FIGURE 3-4: EWDS TIMING 3.7 READ The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 8-bit (x8 organization) or 16-bit (x16 organization) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (TPD.). Sequential read is possible when CS is held high. The memory data will automatically cycle to the next register and output sequentially. a \ Test / FIGURE 3-5: EWENTIMING cs / Di 1 0 0 1 - Test FIGURE 3-6: READ TIMING a ef DI 1 t TAI-STATE ve 0 KKK OK KK OK OOK KY TRI-STATE js a registered trademark of National Semiconductor Incorporated. a a] 1997 Microchip Technology Inc. DS11168L-page 793LC46/56/66 3.8 WRITE 3.9 Write All (WRAL) The WRITE instruction is followed by 8 bits (or by 16 _ The Write All (WRAL) instruction will write the entire bits) of data which are written into the specified memory array with the data specified in the command. address. After the last data bit is put on the DI pin, CS The WRAL cycle is completely self-timed and com- must be brought low before the next rising edge of the mences at the falling edge of the CS. Clocking of the CLK clock. This falling edge of CS initiates the self- CLK pin is not necessary after the device has entered timed auto-erase and programming cycle. the self clocking mode. The WRAL command does The DO pin indicates the READY/BUSY status of the include an automatic ERAL cycle for the device. There- fore, the WRAL instruction does not require an ERAL instruction, but the chip must be in the EWEN status. The WRAL instruction is guaranteed at Vcc = +4.5V to device, if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is complete. DO at logical O indicates that programming is still in progress. DO at logical "1" indicates that the register at +6.0V. the specified address has been written with the data The DO pin indicates the READY/BUSY status of the specified and the device is ready for another instruc- device if CS is brought high after a minimum of 250 ns tion. low (TCSL). The WRITE cycle takes 4 ms per word (Typical). The WRAL cycle takes 30 ms maximum (16 ms typical). FIGURE 3-7: WRITE TIMING as g a cs / Test | _ STANDBY oA N\A NEXEXEKEEXE bo TRISTATE s 4 BUSY READY TRI_STATE Twe FIGURE 3-8: WRAL TIMING cs / TRISTATE TRESTATE Guarantee at Vcc = +4.5V to +6.0V. DS11168L-page 8 1997 Microchip Technology Inc.93LC46/56/66 NOTES: 1997 Microchip Technology Inc. DS11168L-page 993LC46/56/66 NOTES: DS11168L-page 10 1997 Microchip Technology Inc.93LC46/56/66 93LC46/56/66 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, .g., on pricing or delivery, refer to the factory or the listed sales office.. 93LC46/66/66 /P L Package: | Temperature Range: Device: P = Plastic DIP (300 mil Body), 8-lead SL = Plastic SOIC (107 mil Body), 14-lead SN = Plastic SOIC (150 mil Body), 8-iead SM = Plastic SOIC (207 mil Body), 8-lead Blank = 0C to +70C 1] =-40C to +85C 93LC46 93LC46T 93LC46X 93LC46XT 93LC56 93LC56T 93LC56X 93LC56XT 93LC66 93LC66T 93LC66X 93LC66XT 1K Microwire Serial EEPROM 1K Microwire Serial EERPOM, Tape and Reel 1K Microwire Serial EEPROM in alternate pinouts (SN package only) 1K Microwire Serial EEPROM in alternate pinouts, Tape and Reel (SN package only) 2K Microwire Serial EEPROM 2K Microwire Serial EERPOM, Tape and Reel 2K Microwire Serial EEPROM in alternate pinouts (SN package only) 2K Microwire Serial EEPROM in alternate pinouts, Tape and Reel (SN package only) 4K Microwire Serial EEPROM 4K Microwire Serial EERPOM, Tape and Reel 4K Microwire Serial EEPROM in alternate pinouts (SN package only) 4K Microwire Serial EEPROM in alternate pinouts, Tape and Reel (SN package only) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To detennine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip's Bulletin Board, via your local CompuServe number (CompuServe membership NOT required). 1997 Microchip Technology Inc. DS11168L-page 11WORLDWIDE SALES & SERVICE AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Bivd. 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EUROPE United Kingdom Arizona Microchip Technology Lid. Unit 6, The Courtyard Meadow Bank, Furlong Raad Bourne End, Buckinghamshire SL8 5AJ Tel: 44-1628-851077 Fax: 44-1628-850259 France Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Miichen, Germany Tel: 49-89-627-144 9 Fax: 49-89-627-144-44 Italy Arizona Microchip Technology SAL Centro Direzionale Colleone Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883 JAPAN Microchip Technology Inil. Inc. Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81-4-5471- 6166 Fax: 81-4-5471-6122 5/8/97 All ights reserved. 1997, Microchip Technology Incorporated, USA. 6/97 Information Coniained in this publication regarding device app anS and ihe like is intended for suggestion only and may be Superseded by updates. No representation or warranty is given and no iability is assumed oy Microchip Technology Incorporated with respect to ihe accuracy or use at such information, or infringement of patents or other intetectual property rights arising trom such use or olhenwise. Use of Microchip's products as critical componenis in Ite support systems is not auinorized except with express wnitten approval by Microchip. No hcenses are conveyed, implicitly or othenmse, under any intelleciual property nghts. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. Ail rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS11168L-page 12 Preliminary 1997 Microchip Technology Inc.