NEC PROGRAMMABLE NEC Electronics Inc. INTERRUPT CONTROLLER Description Pin Configuration The uPD8259A is a programmable interrupt controller directly compatible with the 8080A/8085A/8086/8088 microprocessors. It can service eight levels of inter- rupts and contains on-chip logic to expand interrupt capabilities up to 64 levels with the addition of other p#PDB8259A's. The user can choose a selection of priority algorithms to tailor the priority processing to meet his system requirements. These algorithms can be dynamically modified during operation, which expands the versatility of the system. The pPD8259A is completely upward compatible with the PD8259-5, allowing software written for the .PD8259-5 to run on the pPD8259A/-2. 8300027774 Features . . Pin Identification O) Ejight-level priority controller C Programmable base vector address No. Symbol Funetion C) Expandable to 64 levels 1 Cs Chip select input O Programmable interrupt modes (algorithms) 2 WR Write input (J Individual request mask capability = - . 3 RD Read input C1 Single +5 V power supply (no clocks) 1 Full compatibility with 8080A /8085A /8086/8088 an D7-Do Bidirectional data bus 12, 13, 15 CASq-CAS Cascade lines Ordering Information 14 GND Ground Part 16 SP/EN Slave program input / enable buffer Number Package Type output HPD8259AC 28-pin plastic DIP 7 INT interrupt output HPDB259AC-2 28-pin plastic DIP 18-25 iRp-IRy interrupt request inputs 26 INTA Interrupt acknowledge input 27 Ag Command select address input 28 Voc +5 V power supply 8-91uPD8259A NEC Pin Functions Bidirectional Data Bus (D7-Dg) Three-state data bus used for interfacing to the system data bus. This bus carries control words, status infor- mation, and interrupt vector information. Interrupt Request Inputs (IRo-IR7) These are eight asynchronous inputs that operate in two modes. In the edge-triggered mode, the IR input must be raised from low to high and held high until it is acknowledged. In the tevel-triggered mode, the IR input requires only a high. Cascade Lines (CASg-CAS2) These lines are used as a bus which controls multiple pPD8259As in a master/slave configuration. When an pPD8259A is a master, these lines are outputs. When a pPD8259A is used as a slave, the lines are inputs. Chip Select (CS) When CS is low, the CPU can read and write to the pPD8259A. The INTA input operates independently of cs. Command Select Address Input (Ag) The uPD8259A uses this input with CS and WR to de- code command words written by the CPU. Ag is used with CS and RD to decode controller status information for the CPU to read. Typically, Ag is connected to the Ag address lines on the CPU. 8-92 Interrupt (INT) When the pPD8259A receives a valid interrupt request, the INT output goes high to interrupt the CPU. This pin should be connected directly to the interrupt pin on the CPU. Interrupt Acknowledge (INTA) This input line goes active low to indicate that the CPU has received an interrupt request from the PD8259A. INTA enables interrupt vector data onto the data bus. Read Input (RD) When both RD and CS are tow, the .PD8259A sends its status information to the data bus so the CPU can read it. Write Input (WR) The PD8259A can receive command words from the CPU when both WR and CS are low. Slave Program Input/ Enable Buffer Output (SP/EN) This is a dual function pin. In the buffered mode, the en- able buffer output is used to enable the buffer transceiv- ers. In the non-buffered mode, when the SP input is high, the .PD8259A operates as a master and when the SP input is low, the PD8259A operates as a slave. Ground (GND) Ground Power Supply (Vcc) Power supply input, +5 voits.NEC uPD8259A Block Diagram > ) Mm INT V] D2 - Do | Dat AWK, = K 7 eu K A INTA INT utter Control Logic wo = ih it RD + IRo row up head IRy O] WR Wite In Interrupt f* !R2 Ag ho Sarvico |] Priority Request [e IR3 _ Roggster N Resolver Register he IRg cs R) GRR) be IRs _ o H IRg cs 4 ~~ iF Cascade K > Interrupt Mask Register (MR) Bulter ae Comparator SP CASg CAS; CAS? A ou W thtt & P P: P Slave Address Control Data Program Cascade intemal Bus Bus Bus Enable Lines Bus uffer 83-002778B Block Diagram Description Interrupt Request Register (IRR) and In-Service Register (ISR) The interrupt request and in-service registers store the incoming interrupt request signals appearing on the IRo-!R7 lines. The inputs requesting service are stored in the IRR while the interrupts actually being serviced are stored in the ISR. Refer to functional block diagram. A positive transition on an IR input sets the correspond- ing dit in the interrupt request register. At the same time, the INT output of the .PD82594 is set high. The IR input line must remain high until the first INTA input has been received. Multiple non-masked interrupts occurring si- muitaneously can be stored in the IRR. The incoming INTA sets the appropriate iSR bit, which is determined by the programmed interrupt algorithm, and resets the corresponding IRR bit. The ISR bit stays active high dur- ing the interrupt service subroutine until it is reset by the programmed end of interrupt command (EON. Priority Resolver The priority resolver decides the priority of the interrupt levels in the IRR. When the highest priority interrupt is determined, it is loaded into the appropriate bit of the ISR by the first INTA pulse. Data Bus Buffer The three state 8-bit bidirectional data bus buffer inter- faces the 1PD8259A to the systems data bus. It buffers the control word and status information being transfer- red between the ,PD8259A and the processor. Read/Write Logic The read/write logic accepts processor commands and Stores them in its initialization command word (ICW) and operation command word (OCW) registers. This logic also controls the transfer of status information to the processor. 8-93NEC uPD8259A Chip Select (CS) Table 1. PD8259A Basic Operation The .PD8259A is enabled when this input receives an Ap Dy Dy RD WR CS Operation active low signal. When the CS input is high, reading or Processor Input (Read) writing of the pPD8259A is inhibited. 0 0 1 0 JAR, ISRor IR data bus (Note 1) Write (WR) 1 a 1 0 IMR data bus Thi ive | . li he uPDB259A t . Processor Output (Write) is active low signal instructs the 0 receive . 00 TO 0 Data bus > OCW? command data from the processor. 0 0 1 1 0 0 Data bus > OCW3 Read (RD) 0 1 =X 1 0 O Data bus ICW1 When the RD input receives an active low signal, the 1 X X 1 G8 O Data bus > OCW1, ICW2, ICWS, ICW4 status of the interrupt request register, in-service regis- (Note 2) ter, interrupt mask register or binary code of the inter- Disable Function rupt level is placed on the data bus. X xX X 14 1 0 Data bus > high impedance state x X X x x 1 Data bus > high impedance state Interrupt (INT) Nowe ane The interrupt output from the .PD8259A is directly con- nected to the processor's INT input. The voltage levels of this output are compatible with the 8080A/8085A/ 8086/8088. Interrupt Mask Register (IMR) The interrupt mask register stores the bits which will mask the individual interrupt lines. The IMR masks the data in the ISR. Lower priority lines are not affected by masking a higher priority line. interrupt Acknowledge (INTA) INTA pulses cause the .PD8259A to put vectoring infor- mation on the bus. The number of pulses depend upon whether the u.PD8259A is in the ~PD8085A mode or 8086/8088 mode. Command Select Address Input (Ao) Ag is usually connected to the processor's data bus. To- gether with RD and WR, it signals the loading of data into the command register or the reading of status data. Table 1 illustrates the basic operations performed. Note that it is divided into three functions: input, output, and bus disable distinguished by the RD, WR, and CS in- puts. 8-94 {1} The contents of OCW3 written prior to the read operation governs the selection of IRR, {SR or the interrupt level. {2) The sequencer logic on the .PD8259A aligns these commands in the proper order. Cascade Buffer/Comparator The IDs of all p~PD8259As are buffered and compared in the cascade buffer/comparator. See figure 4. The master PD8259A sends the ID of the interrupting slave device along the CASg, CAS and CAS lines to all slave devices. The cascade buffer/comparator compares its preprogrammed ID to the CASo, CAS and CASo lines. The next two INTA pulses strobe the preprogrammed, 2 byte call routine address onto the data bus from the slave whose ID matches the code on the CASp, CAS; and CAS lines. Slave Program (SP) The interrupt capability can be expanded to 64 levels by cascading multiple 4PD8259As in a master plus slaves array. See figure 4. The master controls the slaves through the CASp, CAS, and CAS lines. The SP input to the device selects the CASp, CAS; and CASz lines as either outputs (SP=1) for the master or as inputs (SP =0) for the slaves. If only one PD8259A is used, the SP input must be set to a logic 1, since it is functioning as a master.NEC uPD8259A Absolute Maximum Ratings DC Characteristics Ta = 25C Ta =0to +70C, Vog= +5V 410% Power supply voltage, Vee 0.5 to +7.0 V(Note 1} Limits Test Input voltage, V, 1.0V to Voce + 1.0V Parameter Symbol Min Typ Max Unit Conditions Output voltage, Vo ~O.5VioVog +0.5 inputvoitage Vj = 0.5 08 Vv low Operating temperature, Top Oto +70C Input voltage V 2.0 Vv . Storage temperature, Tsr =6510+150% ign oo+0.8 Power dissipation. Pp OW Output voltage Voy 0.45 V lo,=2.2mA Note: low (1) With respect to ground. Output valtage Voy 2.4 Vi lon = 400 pA high Comment: Exposing the device to stresses above those listed in Abso- g iute Maximum Ratings could cause permanent damage. The device is Interrupt output Voy-int 2.4 loH= 400 pA not meant to be operated under conditions outside the limits de- High voltage 35 loy= 100uA scribed in the operational sections of the specification. Exposure to - oH M absolute maximum rating conditions for extended periods may affect Inputleakage =I} -10 10 HA OV<Vi<Voc device reliability. current (Note 1) Output leakage Ii -10 10 pA 0.45V<Vo<Voo current Vec power lec 85 mA supply current Note: (1} For other inputs. AC Characteristics Timing Requirements Ta =0C to +70C, Veg = +5V 410% Limits yPD8259A pPDB259A-2 Test Parameter Symbol Min Max Min Max Unit Conditions AQ/CS setup to RD /INTA 4 tAHRL 0 0 ns AQ/CS hold atter RD/ INTA t trHAX 0 0 ns. RD pulse width tRERH 235 160 ns AO/CS setup to WR + taHWL 0 0 ns AO/CS hold after WR * twHax 0 0 ns WR pulse width twiwH 290 190 ; ns Data setup to WR t tovwH 240 160 ns Data hold after WR t twupx 0 0 ns Interrupt request width low WuWJH 100 100 ns (Note 1) Cascade setup to second or third teVviAL 55 40 ns INTA 4 (slave only) End of RD to next command tRHRL 160 160 ns End of WR to next command twHaL 190 190 ns End of command ta next command too 500 500 ns (Note 2) (different type} End of INTA sequence tonext INTA tou. 500 500 ns (Note 2) sequence Note: (1) This is the low time required to clear the input latch in the edge-triggered mode. (2) Worst case timing for tcyc_ in an actual microprocessor system is typically much greater than 500 ns (8085A = 1s, 8085-2 = ips, 8086 = 1s, 8086-2 = 625 ns). 8-95uPD8259A NEC AC Characteristics (cont) Timing Responses Ty =0C to + 70C, Voc = +5V 410% Limits uPD8259A uPD8259A-2 Test Parameter Symboi Min Max Min Max Unit Conditions Data valid from RD /INTA 4 tapv 200 120 ns (Notes 1-5) Data float after RD/INTA t troz 10 100 10 85 ns (Notes 1-5) Interrupt output delay TyHIH 350 300 ns (Notes 1-5) Cascade valid from first INTA + taLcv 565 360 ns (Notes 1-5) (master only) Enable active from RD toriNTAT tavet 125 100 ns (Notes 1-5) Enable inactive from RD tor INTA t trHEH 150 150 ns (Notes 1-5) Data valid from stable address taHpv 200 200 ns {Notes 1-5) Cascade valid to valid data tovov 300 200 ns (Notes 1-5} Note: (1) C of data bus = 100 pF (2) Max test C = 100 pF (3) Min test C= 15 pF (4) Cin = 100 pF 8) Ccascape = 100 pF Capacitance AC Test Input Ta = 25C, Voc = GND =0V, fc = 1.0 MHz Limits 24 Test 20 Jest Point 2.0 Parameter Symbol Min Typ Max Unit _Condiitions bas 0g = eetPaints =< gg Input C 10 pF (Note 1) a3-00e779A capacitance 170 C10 20. pF (Note 1) capacitance Note: (1) Unmeasured pins returned to Vgg Timing Waveforms Write Mode Read/INTA Mode _ |}+ twLwH+| 'RLRH wR * eo ADIINTA yy ; x ee, taHWe [towne twHax tRLEL tRHEM cs y x EN Address Bus K Ao K 7 | twHoXx | [+ taHRL * f+ trax cs % Data Bus Address Bus K Ao 7 83-002780A |-triov |_-tanpz- Data Bus =< = = r= 7 b- - taHDV i A B3-002781A 8-96NE Cc uPD8259A Timing Waveforms (cont) INTA Sequence | o tH $CVIAL PECVIAL Co-Cp A tevpv A tlaLcy >} 83.0027634 IR Triggering Timing Requirements Eastlest IR Can Be Removed Latch(t} Latch(1) Laten( Armed Armed Armed ik \ | / Xx \ >". Lx /\SEZ Wy 8080/8085 NOTE (}} Edge triggered mode only 8340027844, Other Timing tRHRL > RDINTA tWHRL WR - 830027824 8-97uPD8259A NEC Functional Description The PD8259A functions are described in following paragraphs under these major headings: Interrupt Sequence 8080/8085A Mode 8086/8088 Mode initialization Command Words Operational Command Words Reading pPD8259A Status Interrupt Sequence The uPD&259A derives its versatility from pro- grammable interrupt modes and the ability to jump to any memory address through programmable CALL instructions. The sequence used by the u.PD8259A to handle an interrupt depends upon whether an 8080A/8085A or 8080/8088 CPU is being used. The following sequence demonstrates how the uPD8259A interacts with the 8080A/8085A systems. (1) An interrupt(s) appearing on IRo-!R7 sets the corresponding 1R bit(s) high. This in turn sets the corresponding IRR bit(s) high. (2) Once the IRR bit(s) has been set, the .PD8259A will resolve priorities according to the preprogrammed interrupt algorithm. It then issues an INT signal to the processor. (3) When the processor receives an INT, it issues an INTA to the PD8259A. (4) The INTA input to the zPD8259A from the processor group sets the highest priority ISR bit and resets the corresponding IRR bit. The INTA also signals the uPD8259A to place an &-bit CALL instruction opcode (11001101) onto its data bus lines. (5) The CALL instruction code instructs the processor group to issue two more INTA pulses to the uPDB259A. 8-98 (6) The two INTA pulses signal the .PD8259A to place its preprogrammed interrupt vector address onto the data bus. The first INTA releases the low order 8 bits of the address and the second iNTA releases the high order 8 bits. The pPD8259As CALL instruction sequence is complete. A preprogrammed EOI command is issued to the .PD8259A at the end of the interrupt service routine. This resets the ISR bit and allows the PD8259A to service the next interrupt. (7 The following sequence demonstrates how the uPD8259A interacts with the 8086/8088 systems. (1), (2), (3) Same as for 8080A/8085A. (4) During the first INTA from the processor, the uPD8259A does not drive the data bus. The highest priority ISR bit is set and the corresponding IRR bit is reset. (5) The p~PD8259A puts vector information onto the data bus on the second INTA pulse from the 8086/8088. (6) There is no third INTA pulse in this mode. In the AEOI mode the ISR bit is reset at the end of the second INTA pulse, or it remains set until an EOI command is issued. 8080/8085A Mode For these processors, the 4PD8259A is controlled by three INTA pulses. The first INTA pulse will cause the uPD8259A to put the CALL opcode onto the data bus. See table 2. The second and third INTA pulses will cause the upper and lower address of the interrupt vector to be released on the bus. See tables 3 and 4. Table 2. Contents of First interrupt Vector ByteN KE C uPD8259A Table 3. Contents of Second Interrupt Vector Byte 8086/8088 Mode iR Interval = 4 In this mode only two [NTA pulses are sent to the Dy | Bg | ds | Dg | D3 | Do | Dy | Dy HPD8259A. After the first INTA pulse, the uPD8259A 7 Ay As Ag 1 1 1 0 0 does not output a CALL but internally sets priority reso- 6 A A A 1 1 , 0 0 lution. If it is a master, it sets the cascade lines. The in- 6 5 terrupt vector is output to the data bus on the second 5 | Ar | Ae | As | 1 0 1 9 o INTA pulse. See table 5. 4 Az Ag As 1 0 0 0 0 3 | a, | Ag | As | 0 1 71 0 0 Initialization Command Words 2 Ay | Ag | As 0 1 0 0 0 ICW1 and ICW2 1 Ar | Ae | As | 0 0 1 0 0 LTIM lf LTIM=1, then the p.PD8259A operates in 0 Az Ag As 0 0 0 0 0 the level interrupt mode. Edge detect logic on the interrupt inputs is disabled. ADI CALL address interval. If AD! = 1 then the in- IR Interval = 8 terval is four; if ADI = 0 then the interval is Dy; Dg Ds Dy D3 D2 Dy Do eight. 7 LA | Aw] 1 1 0 0 0 SNGL (Single) Indicates that there is only one 6 Az Ag 1 1 0 0 0 0 vPD8259A in the system. If SNGL=1, no 5 Ar | As 1 0 1 0 0 0 ICW3 is issued. 4 Az Ag 1 0 0 ) 0 0 IC4 If this bit is set, ICW4 has to be read. If ICW4 3 Ar | As 0 1 1 0 0 0 is not needed, set IC4 to logic 0. 2 Az Ag 0 1 0 0 0 0 A5-A15 Defines the page starting address of the 1 Ay | Ae 0 0 1 0 0 0 service routines. In an 8085A system, the eight request levels generate CALLs to 0 A7 | Ag 0 0 0 0 0 0 : : . eight locations equally spaced in memory. These can be programmed to be spaced at Table 4. Contents of Third Interrupt Vector Byte intervals of four or eight memory locations, Dy Dg Os D4 D3 Dg Dy Do allowing eight routines to occupy a page of 32 or 64 bytes, respectively. | ass Aug | Aig | Arg An | Aig | Ag | Ag a yt specively The address form is two bytes long (Ag-A45). When the 7 , 8086/8088 routine interval is four, Ag-Aq are automatically inserted Table 5 pantents of Interrupt Vector Byte, 808: by the wPD8259A, while A5-A45 are programmed exter- nally. When the routine interval is eight, Ag-As are auto- IR interval = 4 matically inserted by the .PD8259A, while Ag-A1s are D7 Dg Ds Dg D3 Dz Dy Dp programmed externally. Tit | te | ts | tm | ts | 4 1 i The eight-byte interval maintains compatibility with 6 17 Ts Ts 1% Ty 1 1 0 current software, while the four-byte interval is best fora 5 t | 1 | ws | t | Ty 1 0 1 compact jump table. 4 T7 Ts Ts Ty T3 1 0 0 In an 8086/8088 system, T7-T3 are inserted in the five 3 tT | 1 | 1 | Tt | Ts 0 1 1 most significant bits of the vectoring byte. The 5 7 T T T T 0 1 r PD8259A sets the three least significant bits accord- ? 6 5 4 3 ing to the interrupt level. 1 T7 Tg 15 Tg T3 0 0 1 0 Tz Tg Ts Ty T3 0 0 0 8-99NEC uPD8259A ICW3 ICW4 This word is read only when there is more than one SNFM If SNFM =1, the special fully nested mode uPD8259A in the system and cascading will be used. is programmed. SNGL of ICW1 is programmed for logic 0. ICW3 will load _ . the 8-bit slave register. The functions of this register are, BUF tS re ep olbairmnlines oat ned inthe master mode, when SP = 1 or BUF =1andM/S=1 aero an enable output , and the inijCW4, a1 is set for each slave in the system. The mas- master/slave det rmination is by M/S ter then releases byte 1 of the call sequence (for 8080A/ ete y NS. 8085A system) and enables the corresponding siave via M/S If the buffered mode is selected, M/S=1 the cascade lines to release vector bytes 2 and 3 (byte 2 means the .PD8259A is programmed to be only for 8086/8088). a master, M/S=0 means the pPD8259A is In the slave mode, when SP =0 or BUF =1and M/S=0 programmer be a slave. If BUF =0, M/S in ICW4, bits [D2-IDg identify the slave. The slave com- , pares its cascade input with these bits and if they are AEOI lf AEO! =1, the automatic end of interrupt equal, vector bytes 2 and 3 of the call sequence (byte 2 mode is programmed. only for 8086/8088) are released by the slave on the data PM Microprocessor mode: PM=0 sets the bus. puPD8259A for 8085A system operation; pPM = 1sets the p.PD8259A for 8086 system operation. Figure 1 illustrates the command word initialization se- quence, Figure 1. Initialization Sequence Ag Dr Og Ds Ds 03 Da Dy Oo { 0 Az Ag As 1 LIM Apt = SNGL_sICA | ows | 1 AisiTy = AsaiTg = Ata/T5)At2iTg Ans/T3 Ato Ag Aa Jrowe YES (SNGL = 4) NO(SNGL = 0} | 1 Ss Se $5 Sa 83 S2iiD2 S4/lDy 50/100 | Icw3 YES(IC4 = 1) [ 1 0 0 a SFNM = BUF MIS AEOL = uPM | iowa Ready to Accept interrupts 83.002785A 8-100N: KE Cc uPD8259A Figure 2 illustrates the initialization command word for- mat. Figure 2. Initialization Command Word Format Ap =O Dg Ds Dg D3 oO Do rom | 0 | A; As | AS | 1 | um | ADI | sno | ice | | 1=ICW4 Needed 0=No ICW4 Needed 1 = Single 0 = Cascade Mode Call Address Interval 1 = Interval of 4 O = Interval of 8 1 = Level Triggered Mode O = Edge Triggered Mode A7~As of interrupt Vector Address (80/85 Mode Only) Aas | Ata | sg, | Arn | Att rewe | 17 1. T3|7T4 T| Ato Ag | As | Ayq5-Ag of Interrupt Vector Address reese =T Of Interrupt tor Addrese, (8086/8088 Mode} Ao D7 06 Ds Dg D3 D2 Lr Do Icws (Master Device) | Sr | 56 | Ss | 84 | 8s | 82 | s | So | | | | I | = IR Input Has a Slave 0 = IR Input Does Not Have a Slave Ap Dr Ds _ Ds Dg Dg O2 Th Do Icws {Slave Device) Slave iDtt) 3/4 1/0 +10 oj1 Ao Dr De Ds Of Bs D2 BR rows | 1 | 0 | 0 | oO | srw] BUF | M/S | acor | PM | 1 = 8086/8088 Mode 0 = 80/85 Mode 1= Auto EO! 0 = Normal EO! Xx - Non Buff Mode 0 +B Mode/Slave 1 - Mode/Master 4 = Special Fully Nested Mode 0 = Not-Special Fully Nested Mode NOTE: (1) Slave ID Is equal to the corresponding master input. 83-002786B 8-10TuPD8259A NEC Operational Command Words Once the PD8259A has been programmed with initiali- zation command words, it can be programmed for the appropriate interrupt algorithm by the operation com- mand words (OCW). See figure 3. Interrupt algorithms in the p.PD8259A can be changed at any time during pro- gram operation by issuing another set of operation command words. The following sections describe the various algorithms available and their associated OCWs. Interrupt Masks The individual interrupt request input lines are maska- bie by setting the corresponding bits in the interrupt mask register to a logic 1 through OCW1. The actual masking is performed upon the contents of the in- service register. For example, if interrupt request line 3 is to be masked, then only bit 3 of the IMR is set to logic 1. The IMR in turn acts upon the contents of the ISR to mask bit 3. Once the pPD8259A has acknowledged an interrrupt, the masked interrupt input inhibits lower priority re- quests from being acknowledged. There are two means of enabling these lower priority interrupt lines. The first is by issuing an end of interrupt (EON through operation command word 2 (OCW2), thereby resetting the appro- priate ISR bit. The second approach is to select the spe- cial mask mode through OCWS3. The special mask mode (SMM) and end of interrupt (EOl) are described later. Fully Nested Mode The fully nested mode is the PD8259As basic operat- ing mode. It will operate in this mode after the initializa- tion sequence without requiring operation command words for formatting. The order of priority is determined by IRo-IRz. IRo has the highest priority. After the inter- rupt has been acknowledged by the processor and sys- tem controller, only higher priorities will be serviced. Upon receiving an INTA, the priority resolver determines the priority of the interrupt, sets the corresponding IR bit, and outputs the vector address to the data bus. The EO! command resets the corresponding ISR bits at the end of its service routines. Rotating Priority Mode Commands The two variations of rotating priorities are the auto ro- tate and specific rotate modes. These two modes are typically used to service interrupting devices of equiva- lent priorities. Auto Rotate Mode. Programming the auto rotate mode through OCW2 assigns priorities 0-7 to the interrupt re- quest inputs. Interrupt line [Ro is set to the highest prior- ity and IR7 to the lowest. Once an interrupt has been 8-102 serviced, it is automatically assigned the lowest prior- ity. That same input must then wait for the devices ahead of it to be serviced before it can be acknowledged again. The auto rotate mode is selected by program- ming OCW2 in the following way: set rotate priority bit R to a logic 1, program EOI to a logic 1and SECOI toa logic 0. The EOI and SEOI commands are discussed later. The following is an example of the auto rotate mode with de- vices requesting interrupts on line IR and IRs. (1} Before interrupts are serviced: In-service register Priority status register highest priority | IR | IRg | IRs | Ig | IR3 | IRe | IRy | Re | According to the priority status register, [Ro has a higher priority than IRs and wil! be serviced first. (2) After interrupts are serviced: In-service register Priority status register highest priority | IR | IR | Ig | IR | IRg | IRs | iRy | IR | At the completion of IRos service routine, the corres- ponding in-service register bit (IS2) is reset to logic 0 by the preprogrammed EOI command. IR2 is then as- signed the lowest priority level in the priority status reg- ister. The .PD8259A is now ready to service the next highest interrupt, which, in this case, happens to be IRs. Specific Rotate Mode. The priorities are set by program- ming the lowest level via OCW2. Then, the yPD8259A au- tomatically assigns the highest priority. If, for example, IR3 is set to the lowest priority (bits La, Ly, Lo form the binary code of the bottom priority level), then IR4 will be set to the highest priority. The specific rotate mode is selected by programming OCW2 in the following man- ner: set rotate priority bit R to a logic 1, program EOl toa logic 0, SEO! to a logic 1and Lo, Ly, Lo to the lowest prior- ity level. If EOL is set to a logic 1, the ISR bit defined by La, Ly, Lg is reset.NEC uPD8259A End of Interrupt (EO!) and Specific End of Interrupt (SEON) The end of interrupt (EOI) or specific end of interrupt (SEOl) command must be issued to reset the appropri- ate in-service register bit before the completion of a service routine. Once the ISR bit has been reset to logic 0, the uPD8259A is ready to service the next interrupt. Two types of EOls are available to clear the appropriate ISR bit depending on the .PD82594s operating mode. Non-Specific End of Interrupt (EOI). When operating in interrupt modes where the priority order of the interrupt inputs is preserved, such as the fully nested mode, the particular ISR bit to be reset at the completion of the service routine can be determined. A non-specific EOI! command automatically resets the highest priority ISR bit of those set. The highest priority ISR bit must neces- sarily be the interrupt being serviced and must neces- sarily be the service subroutine returned from. Specific End of Interrupt (SEOI). When operating in in- terrupt modes where the priority order of the interrupt inputs is not preserved, such as the rotating priority mode, the last serviced interrupt level may not be known. In these modes, a specific end of interrupt must be issued to clear the ISR bit at the completion of the interrupt service routine. The SEO! is programmed by setting the appropriate bits in OCW2 to logic 1s. See fig- ure 3. Both the EOI and SEOI bits of OCW2 must be set to a logic 1 with Lo, Ly, Lo forming the binary code of the ISR bit to be reset. Special Mask Mode Setting up an interrupt mask through the interrupt mask register by setting the appropriate bits in OCW1 to a logic 1 inhibits lower priority interrupts being acknowledged. In applications requiring that the lower priorities be enabled while the IMR is set, the special mask mode can be used. The SMM is programmed in OCWS3 by setting the appropriate bits to a logic 1. Once the SMM is set, the u.PD8259A remains in this mode until it is reset. The special mask mode does not affect the higher priority interrupts. Poll Mode In poll mode, the processor must be instructed to disable its interrupt input (INT). Interrupt service is initiated through software by a poll command. Poll mode is programmed by setting the poll mode bit in OCWS3 to logic 1 during a WR Pulse. The following RD pulse is then considered as an interrupt acknowledge. If an interrupt input is present, the RD pulse sets the appropriate ISR bit and reads the interrupt priority level. Poll mode is a one time operation and must be programmed through OCW3 before every read. The word format which is strobed onto the data bus during the poll mode follows: D7 Dg Ds Dg D3 Do D, Dg RERSESESES where: | = 1if there is an interrupt requesting service 1 = Oif there are no interrupts Wo-Wp forms the binary code of the highest priority level of the interrupts requesting service. Poll mode can be used when an interrupt service routine is common to several interrupt inputs. The INTA sequence is no longer required; this saves ROM space. Poli mode can also be used to expand the number of interrupts beyond 64. Reading . PD8259A Status The following major registers status is available to the processor by appropriately formatting OCW3 and issuing RD command. Interrupt Request Register The &bit interrupt request register stores the interrupt levels awaiting acknowledgement. The highest priority in-service bit is reset once it has been acknowledged. Note that the interrupt mask register has no effect_on the IRR. Prior to the issuing of the RD command, a WR command must be issued with OCW3. Programmable logic bits RIS and ERIS of OCW3 determine whether the IRR or (SR register is to be read. To read the contents of the IRR, ERIS must be a logic 1, and RIS a logic 0. In-Service Register The 8&-bit in-service register stores the priorities of the interrupt levels being serviced. Assertion of an end of interrupt (EO!) updates the ISR to the next priority level. A WR command must be issued with OCW3 prior to issuing the RD command. both ERIS and RIS should be set to logic 1. Interrupt Mask Register The 8-bit interrupt mask register holds mask data modifying interrupt levels. A WR pulse preceding the RD is not necessary to read the IMR status. The IMR data is available to the data bus when RD is asserted with Ag at logic 1. A single OCW3 is sufficient to enable succesive status reads providing it is of the same register. A status read is overridden by the poll mode when bits P and ERIS of OCWS3 are set to logic 1. 8-103uPD8259A Figure 3. Operation Command Word Format Ag Oo De Ds Os D3 Da ee ce 0; Oo =] Ag D7 Og Ds Da Dg D2 ocwz:| o | R | seo | cor | 0 0 | te | Ts] 1= Correspondl Bitin IRR is Masked. o= No Mask Present for e Correspondit IRR Bit. sponeing Binary Level to be Reset or Put Into Lowest Priority 1 2; 3)4/]5)]6 1 Oo; Tt oe 0 o;}1 1] 0] 0} 14 Oo; o;oa;i4)1 1 Non-Specific End of Interrupt 1= Reset the Highest Priority Bit of ISR 0=No Action Specitic End of Interrupt 1=Lz, Ly, Lo Bits are Used O= Ne Action Ao D7 Ds Ds Da Ds D2 Dy Do Rotate Priority 1= Rotate 0 = Not Rotate cow | o | - [ewmfom] [> [+ [ens] as } Read In-Service Register 0 | No Action 1 No Action 1 | 0 | ReadIR Reg. on Next RD Pulse 1 1 | Read IS Reg.an Next RD Pulse Polling 1 Read Binary Code of Highast Level Requesting interrupt on Next RO Pulse No Action Speciat Mask Mode No Action No Action Read Special Mask alalofo he alelafo Set Speciat Nask 83-002787B 8-104NEC uPD8259A Table 6. Summary of Operation Command Word Programming Ag Dg Dy Ag Dy Dg ocwi 1 X X M7-Mo IMR (interrupt mask register) ocWw3 0 0 1 ESMM SMM WR eats MR data while RD 0 0 } Special mask not affected OcW2 0 0 0 R SEO! EOI 0 1 Special mask not affected 0 0 0 No action 1 0 Reset special mask 0 0 1 Non-specific end of interrupt ! 1 Set special mask 0 1 0 No action ERIS _RIS - 0 1 1 Specific end of interrupt Lo, Ly, o } No action Lg forms binary representation 0 1 No action of level to be reset 1 0 Read IR register status 1 0 0 Noaction 1 1 Read |S register status 1 0 1 Rotate priority at end of inter- Tupt (auto mode) 1 1 0 Rotate priority, Lo, Ly, Lo specifies bottom priority with- out end of interrupt 1 1 1 Rotate priority at end of inter- rupt (specific mode). Lo, Ly, Lo specifies battom priority, and it is in-service register bit is reset. Figure 4. Cascading the .PD8259A GND NOTE: Ao INT uPDB259A (Stave 2) (} Insure that the mand and initialization se Processor Address Bus (16) Processor Control Bua (8) Processor Data Bus (8) Aa CAS CAS 2120 19 18 17 16 18 14 (NT PD&259A ul {Slave 1 CAS2 SP iA iA IR _IR_IR_IR_IR_IR GND B 12 disabled during the i pt input is quence for all ,PD8259As. nws 8 7 6 of any control com- Ao INT uPDB259A (Master) 1A $43 219 83-002788B 8-105yHPD8259A NEC Instruction Set Operation Code # Mnemonic Operation Description By Dg Ds Dg D3 Dg Dy Do Ao Format (Byte 1 Initialization, No ICW4 Required) 1 ICW1A Single, edge triggered A7 Ag As 1 0 1 1 0 0 4 2 iCW1B Single, level triggered Ay Ag Ax 1 1 1 1 0 0 4 3 ICW1C Not single, edge triggered Az Ag Asx 1 0 1 0 0 0 4 4 Icw10 Not single, level triggered Az Ag Ag 1 1 1 0 0 0 4 5 ICW1E Single, edge triggered Ay Ag 0 1 0 0 1 0 0 8 6 CWI F Single, level triggered Ay Ag O 1 0 1 0 0 8 7 ICW1G Not single, edge triggered Ay Ag 0 1 0 0 0 0 0 8 8 ICW1H Not single, level triggered Ay Ag 0 1 1 0 0 0 0 8 (Byte 1 Initialization, ICW4 Required) 9 ICW1 | Single, edge triggered A7 Ag Ag 1 0 1 { 1 0 4 10 ICWIJ Single, level triggered Ay Ag Ag 1 1 1 1 1 0 4 tt ICWIK Nat single, edge triggered Ay Ag Ag 1 0 1 0 1 0 4 120 FCWIL Nat single, level triggered Ay Ag Asx 1 1 1 0 1 0 4 13. ICWIM Single, edge triggered Ay Ag 0 1 0 0 1 1 0 8 14 ICWIN Single, level triggered Ay Ag O 1 1 0 1 1 0 8 15 =ICWIO Nat single, edge triggered Ay Ag 0 1 0 0 0 1 0 8 16 ICWIP Not single, level triggered A; fg 0 1 1 0 0 1 0 8 {Byte 2 Initialization) 17 Icwe Initialize byte 2 Ais Ata Aig Awa An Aigo Ag Ag 1 (Byte 3 Initialization) 18 ICW3M Initialize byte 3 (master) S7 Sg Ss Sq $3 Sp S; Sp 1 19 ICW3S Initialize byte 3 (slave) 0 0 0 90 O $2 Sy Sp 1 (Byte 4 tnitialization) 20 ICW4A Neo action, redundant 0 0. (0 0 0 Q 0 0 1 21 ICW4B Non-buffered, no AEOI, 8086 / 8088 0 0 0 0 0 6 0 1 1 22 ICW4C Non-buffered, AEOI, 80/85 0 0 0 0 O 9 1 0 1 23 ICW4D Non-buffered, AEOI, 8086 / 8088 0 0 0 0 60 90 1 1 1 24 ICW4E No action, redundant 0 O00 (60 0 0 1 0 0 1 25 ICW4F Non-buffered, no AEO!, 8086 / 8088 0 0 0 0 0 1 0 1 1 26 ICW4G Non-buffered AEQ!, 80/85 0 0 0 O 6 1 1 0 1 27 ICW4H Non-buffered, AEOI, 8086 / 8088 0 oO O0 O O 1 1 1 1 28 ICW4 | Buffered, slave, no AEOI, 80/85 0 oOo oO 0 1 0 oO oO 1 29 OICW4 J Buffered, slave, no AEOI, 8086 / 8088 0 0 oO oO 1 ao o 1 1 30 ICW4 K Buffered, stave, AEOI, 80/85 0 0 0 0 1 0 1 0 1 31. ICW4L Buffered, slave, AEO!, 8086 / 8088 0 0 0 oO 1 o 4 1 1 32. ICW4M Buffered, master, no AEQI, 80/85 0 Q 0 0 1 1 0 0 1 33. ICW4N Buffered, master, no AEQI, 8086 / 8088 0 0 0 0 1 1 0 1 1 8-106NEC yuPD8259A Instruction Set (cont) Operation Code # Mnemonic Operation Description Dy, De Ds Dg Dg Dp Dy Dg Ao Format (Byte 4 Initialization) (cant) 34 ICW40 Buffered, master, AEOI, 80/85 0 0 0 0 1 1 1 0 1 35 ICW4P Buffered, master, AEO!, 8086 / 8088 0 0 0 0 1 1 1 1 1 36 ICW4 NA Fully nested, non-bulfered, no AEO!, 8085A 0 0 0 1 0 0 0 0 1 37 ICW4NB ICW4 NB-ICW4 ND are identical to ICW4 B-ICW4 D with the addition of fully nested mode 0 0 0 1 0 0 0 1 1 38 ICW4 NC ICW4 NB-ICW4 ND are identicat to ICW4 B-ICW4 D with the addition of fully nested mode 0 i) 0 1 0 0 1 0 1 39 ICW4 ND ICW4 NB-ICW4 ND are identical to ICW4 B-ICW4 D with the addition of fully nested mode 0 0 0 1 0 0 1 1 1 40 ICW4 NE Fully nested, non-buffered, no AEOI, 80/85 0 0 0 1 0 1 0 0 1 41. ICW4 NF ICW4 NE-ICW4 NP are identical to ICW4 F-ICW4 P with the addition of fully nested mode 0 0 0 1 0 1 0 1 1 42 ICW4NG ICW4 NF-ICW4 NP are identical to ICW4 F-iCW4 P with the addition of fully nested mode 0 0 0 1 0 1 1 0 1 43 IGw4a NH Icw4 NF-ICW4 NP are identical to ICW4 F-ICW4 P with the addition of fully nested mode 0 0 0 1 0 1 1 1 1 44 ICW4NI ICW4 NF-ICW4 NP are identical to |CW4 F-ICW4 P with the addition of fully nested made a 0 0 1 1 0 0 0 1 45 ICW4NJ ICW4 NF-ICW4 NP are identical to ICW4 F-ICW4 P with the addition of fully nested made 0 0 0 1 1 0 0 1 1 46 iCW4 NK 1CW4 NF-ICW4 NP are identical to ICW4 F-ICW4 P with the addition of fully nested mode 0 0 0 1 1 0 1 0 1 47 ICW4NL ICW4 NF-ICW4 NP are identical to ICW4 F-ICW4 P with the addition of fully nested mode 0 0 0 1 1 0 1 1 1 48 ICW4NM ICW4 NEF-ICW4 NP are identical te 1CW4 F-ICW4 P with the addition of fully nested mode 0 0 0 1 1 1 0 0 1 49 ICW4 NN ICW4 NF-ICW4 NP are identical ta ICW4 F-ICW4 P with the addition of fully nested made 0 0 0 1 1 1 0 1 1 50 ICW4 NO ICW4 NF-ICW4 NP are identical to ICW4 F-ICW4 P with the addition of fully nested mode 0 0 0 1 1 1 1 0 1 51 ICW4 NP iCW4 NF-ICW4 NP are identical to 1CW4 F-ICW4 P with the addition of fully nested mode 0 0 0 1 1 1 1 1 1 52. OCW1 Load mask and read mark registers M7 Me Ms Ma M3 Mo My Mo 1 53 OCW2E Non-specific EO! 0 0 1 0 0 0 0 0 0 54 OCW2 SE Specific EOI, Lo-Lo code of tS FF to be reset 0 1 1 0 O lo ty to 0 55 OCW2 RE Rotate on non-specific EOI 4 a 1 0 0 0 0 0) 0 56 OCW2 RSE Ratate on specific EO! Lg-L2 code of line 1 1 1 0 O to kh ly 0 57 OCW2R Ratate in auto EOI (set) 1 Q 0 0 0 0 0 0 0 58 OCW2CR Ratate in auto E01 (clear) 0 0 0 0 0 0 0 0 0 59 OCW2 RS Set priority command 1 1 0 0 @ Lo Ly Lg 0 60 OCW3P Poll made 0 Q 0 0 1 1 0 0 0 61 = OCW3 RIS Read |S register 0 0 0 0 1 0 1 1 0 8-107