Product Folder Order Now Technical Documents Support & Community Tools & Software SN54LVC74A, SN74LVC74A SCAS287U - JANUARY 1993 - REVISED JANUARY 2017 SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 1 Features 3 Description * * * * The SNx4LVC74A devices integrate two positiveedge triggered D-type flip-flops in one convenient device. 1 * * * Operate From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Maximum tpd of 5.2 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25C Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 1000-V Charged-Device Model (C101) 2 Applications * * * * * * * * * * Servers Medical, Healthcare, and Fitness Telecom Infrastructures TVs, Set-Top Boxes, and Audio Test and Measurement Industrial Transport Wireless Infrastructure Enterprise Switching Motor Drives Factory Automation and Control The SN54LVC74A is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC74A is designed for 1.65-V to 3.6-V VCC operation. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The data I/Os and control inputs are overvoltage tolerant. This feature allows the use of these devices for down-translation in a mixed-voltage environment. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SNJ54LVC74AFK LCCC (20) 8.89 mm x 8.89 mm SNJ54LVC74AJ CDIP (14) 19.56 mm x 6.67 mm SNJ54LVC74AW CFP (14) 9.21 mm x 5.97 mm SN74LVC74AD SOIC (14) 8.65 mm x 3.91 mm SN74LVC74ADB SSOP (14) 6.20 mm x 5.30 mm SN74LVC74ANS SO (14) 10.30 mm x 5.30 mm SN74LVC74APW TSSOP (14) 5.00 mm x 4.40 mm SN74LVC74ARGY VQFN (14) 3.50 mm x 3.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram, Each Flip-Flop (Positive Logic) Copyright (c) 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production SN54LVC74A, SN74LVC74A SCAS287U - JANUARY 1993 - REVISED JANUARY 2017 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Absolute Maximum Ratings ...................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 4 Thermal Information: SN74LVC74A ......................... 5 Electrical Characteristics........................................... 5 Timing Requirements: SN54LVC74A ....................... 6 Timing Requirements: SN74LVC74A ....................... 6 Timing Requirements: SN74LVC74A, -40C to 125C and -40C to 85C.......................................... 7 6.9 Switching Characteristics: SN54LVC74A ................. 7 6.10 Switching Characteristics: SN74LVC74A ............... 7 6.11 Switching Characteristics: SN74LVC74A, -40C to 125C and -40C to 85C.......................................... 8 6.12 Operating Characteristics........................................ 8 6.13 Typical Characteristics ............................................ 8 7 Parameter Measurement Information .................. 9 8 Detailed Description ............................................ 10 8.1 8.2 8.3 8.4 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 10 10 10 10 Application and Implementation ........................ 11 9.1 Application Information............................................ 11 9.2 Typical Application ................................................. 11 10 Power Supply Recommendations ..................... 13 11 Layout................................................................... 13 11.1 Layout Guidelines ................................................. 13 11.2 Layout Example .................................................... 13 12 Device and Documentation Support ................. 14 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resource............................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 14 14 14 14 14 14 14 13 Mechanical, Packaging, and Orderable Information ........................................................... 14 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision T (July 2013) to Revision U Page * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 * Changed Package thermal impedance, RJA, values in Thermal Information: SN74LVC74A From: 86 To: 93.7 (D), From: 96 To: 107.3 (DB), From: 76 To: 90.3 (NS), From: 113 To: 121.7 (PW), and From: 47 To: 54.9 (RGY).................... 5 Changes from Revision S (May 2005) to Revision T * 2 Page Extended maximum temperature operating range from 85C to 125C................................................................................. 4 Submit Documentation Feedback Copyright (c) 1993-2017, Texas Instruments Incorporated Product Folder Links: SN54LVC74A SN74LVC74A SN54LVC74A, SN74LVC74A www.ti.com SCAS287U - JANUARY 1993 - REVISED JANUARY 2017 5 Pin Configuration and Functions D, DB, J, PW, NS, or W Package 14-Pin SOIC, SSOP, CDIP, TSSOP, SO, or CFP Top View VCC 2CLR 1CLK 3 12 2D 1PRE 4 11 2CLK 1Q 5 10 2PRE 1Q 6 9 2Q GND 7 8 2Q 1D 1CLK 1PRE 1Q 1Q VCC 13 1 14 2 13 2CLR 3 12 2D 2CLK 4 11 5 10 2PRE 9 2Q 6 Not to scale 7 8 2Q 14 2 1CLR 1 1D GND 1CLR RGY Package 14-Pin VQFN With Exposed Thermal Pad Top View 1D 1CLR NC VCC 2CLR 3 2 1 20 19 FK Package 20-Pin LCCC Top View 1PRE 6 16 2CLK NC 7 15 NC 1Q 8 14 2PRE 2Q 2Q NC GND 1Q 13 NC 12 2D 17 11 18 5 10 4 NC 9 1CLK Not to scale Pin Functions PIN I/O DESCRIPTION NAME CDIP, CFP, PDIP, SO, SOIC, SSOP, TSSOP, VQFN LCCC 1CLK 3 4 I Channel 1 clock input 1CLR 1 2 I Channel 1 clear input. Pull low to set Q output low. 1D 2 3 I Channel 1 data input 1PRE 4 6 I Channel 1 preset input. Pull low to set Q output high. 1Q 5 8 O Channel 1 output 1Q 6 9 O Channel 1 inverted output 2CLK 11 16 I Channel 2 clock input 2CLR 13 19 I Channel 2 clear input. Pull low to set Q output low. 2D 12 18 I Channel 2 data input 2PRE 10 14 I Channel 2 preset input. Pull low to set Q output high. 2Q 9 13 O Channel 2 output 2Q 8 12 O Channel 2 Inverted output GND 7 10 -- Ground NC -- 1, 5, 7, 11, 15, 17 -- No connect VCC 14 20 -- Supply Copyright (c) 1993-2017, Texas Instruments Incorporated Product Folder Links: SN54LVC74A SN74LVC74A Submit Documentation Feedback 3 SN54LVC74A, SN74LVC74A SCAS287U - JANUARY 1993 - REVISED JANUARY 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Supply voltage, VCC Input voltage, VI (2) Output voltage, VO (2) (3) MIN MAX UNIT -0.5 6.5 V -0.5 6.5 V -0.5 VCC + 0.5 V Input clamp current, IIK VI < 0 -50 mA Output clamp current, IOK VO < 0 -50 mA Continuous output current, IO 50 mA Continuous current through VCC or GND 100 mA 150 C Storage temperature, Tstg (1) (2) (3) -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in Recommended Operating Conditions. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions see (1) VCC Supply voltage Operating MIN MAX SN54LVC74A 2 3.6 SN74LVC74A 1.65 3.6 Data retention only VIH High-level input voltage Low-level input voltage VCC = 1.65 V to 1.95 V SN74LVC74A 0.65 x VCC VCC = 2.3 V to 2.7 V SN74LVC74A 1.7 Input voltage VO Output voltage IOH High-level output current VCC = 1.65 V to 1.95 V SN74LVC74A 0.35 x VCC VCC = 2.3 V to 2.7 V SN74LVC74A 0.7 Low-level output current t/v Input transition rise or fall rate (1) 4 V 0.8 0 5.5 V 0 VCC V VCC = 1.65 V SN74LVC74A -4 VCC = 2.3 V SN74LVC74A -8 VCC = 2.7 V -12 VCC = 3 V IOL V 2 VCC = 2.7 V to 3.6 V VI V 1.5 VCC = 2.7 V to 3.6 V VIL UNIT mA -24 VCC = 1.65 V SN74LVC74A VCC = 2.3 V SN74LVC74A 4 8 VCC = 2.7 V 12 VCC = 3 V 24 10 mA ns/V All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004). Submit Documentation Feedback Copyright (c) 1993-2017, Texas Instruments Incorporated Product Folder Links: SN54LVC74A SN74LVC74A SN54LVC74A, SN74LVC74A www.ti.com SCAS287U - JANUARY 1993 - REVISED JANUARY 2017 Recommended Operating Conditions (continued) see(1) TA Operating free-air temperature MIN MAX SN54LVC74A -55 125 SN74LVC74A -40 125 UNIT C 6.4 Thermal Information: SN74LVC74A SN74LVC74A THERMAL METRIC (1) D (SOIC) DB (SSOP) NS (SO) PW (TSSOP) RGY (VQFN) UNIT 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS RJA Junction-to-ambient thermal resistance 93.7 107.3 90.3 121.7 54.9 C/W RJC(top) Junction-to-case (top) thermal resistance 54.8 59.2 48.1 50.3 52.2 C/W RJB Junction-to-board thermal resistance 48 54.6 49.1 63.4 30.8 C/W JT Junction-to-top characterization parameter 20.3 24.1 17.9 6.2 2.4 C/W JB Junction-to-board characterization parameter 47.7 54.1 48.8 62.8 30.9 C/W RJC(bot) Junction-to-case (bottom) thermal resistance -- -- -- -- 12.5 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 A VOH High-level output voltage VCC - 0.2 VCC = 2.7 V to 3.6 V and TA = -40C to 125C (SN74LVC74A only) VCC - 0.2 IOH = -4 mA, VCC = 1.65 V, and TA = -40C to 125C (SN74LVC74A only) 1.2 IOH = -8 mA, VCC = 2.3 V, and TA = -40C to 125C (SN74LVC74A only) 1.7 IOH = -12 mA IOL = 100 A Low-level output voltage TYP MAX UNIT V VCC = 2.7 V 2.2 VCC = 3 V 2.4 IOH = -24 mA, VCC = 3 V VOL MIN VCC = 1.65 V to 3.6 V and TA = -55C to 125C (SN54LVC74A only) 2.2 VCC = 1.65 V to 3.6 V, and TA = -40C to 125C (SN74LVC74A only) 0.2 VCC = 2.7 V to 3.6 V and TA = -55C to 125C (SN54LVC74A only) 0.2 IOL = 4 mA, VCC = 1.65 V, and TA = -40C to 125C (SN74LVC74A only) 0.45 IOL = 8 mA, VCC = 2.3 V, and TA = -40C to 125C (SN74LVC74A only) 0.7 IOL = 12 mA, VCC = 2.7 V V 0.4 IOL = 24 mA, VCC = 3 V 0.55 II Input current VI = 5.5 V or GND, VCC = 3.6 V 5 A ICC Supply current VI = VCC or GND, IO = 0, VCC = 3.6 V 10 A ICC Change in supply current One input at VCC - 0.6 V, other inputs at VCC or GND, and VCC = 2.7 V to 3.6 V 500 A Ci Input capacitance VI = VCC or GND, VCC = 3.3 V, TA = 25C Copyright (c) 1993-2017, Texas Instruments Incorporated Product Folder Links: SN54LVC74A SN74LVC74A 5 Submit Documentation Feedback pF 5 SN54LVC74A, SN74LVC74A SCAS287U - JANUARY 1993 - REVISED JANUARY 2017 www.ti.com 6.6 Timing Requirements: SN54LVC74A over recommended operating free-air temperature range (unless otherwise noted; see Figure 3) MIN fclock Clock frequency tw Pulse duration VCC = 2.7 V tsu 100 PRE or CLR low 3.3 CLK high or low 3.3 Setup time before CLK PRE or CLR inactive th 83 VCC = 3.3 V 0.3 V Data MAX VCC = 2.7 V UNIT MHz ns 3.4 VCC = 3.3 V 0.3 V 3 VCC = 2.7 V ns 2.2 VCC = 3.3 V 0.3 V 2 Hold time, data after CLK 1 ns 6.7 Timing Requirements: SN74LVC74A over recommended operating free-air temperature range (unless otherwise noted; see Figure 3) MIN fclock Clock frequency VCC = 1.8 V or 2.5 V PRE or CLR low tw Pulse duration CLK high or low Data tsu Setup time before CLK PRE or CLR inactive th 6 Hold time, data after CLK VCC = 1.8 V 0.15 V 4.1 VCC = 2.5 V 0.2 V 3.3 VCC = 1.8 V 0.15 V 4.1 VCC = 2.5 V 0.2 V 3.3 VCC = 1.8 V 0.15 V 3.6 VCC = 2.5 V 0.2 V 2.3 VCC = 1.8 V 0.15 V 2.7 VCC = 2.5 V 0.2 V 1.9 VCC = 1.8 V or 2.5 V Submit Documentation Feedback 1 MAX UNIT 83 MHz ns ns ns Copyright (c) 1993-2017, Texas Instruments Incorporated Product Folder Links: SN54LVC74A SN74LVC74A SN54LVC74A, SN74LVC74A www.ti.com SCAS287U - JANUARY 1993 - REVISED JANUARY 2017 6.8 Timing Requirements: SN74LVC74A, -40C to 125C and -40C to 85C over recommended operating free-air temperature range (unless otherwise noted; see Figure 3) MIN fclock Clock frequency VCC = 2.7 V TA = -40C to 125C Pulse duration 100 VCC = 2.7 V or 3.3 V 3.3 CLK high or low VCC = 2.7 V or 3.3 V 3.3 TA = -40C to 125C tsu VCC = 2.7 V TA = -40C to 125C PRE or CLR inactive 3 VCC = 2.7 V 3 th ns 2.2 VCC = 3.3 V 0.3 V 2 TA = -40C to 85C and VCC = 3.3 V 0.3 V Hold time, data after CLK ns 3.4 VCC = 3.3 V 0.3 V TA = -40C to 85C and VCC = 3.3 V 0.3 V Setup time before CLK MHz 150 PRE or CLR low Data UNIT 83 VCC = 3.3 V 0.3 V TA = -40C to 85C and VCC = 3.3 V 0.3 V tw MAX 2 VCC = 2.7 V or 3.3 V 1 ns 6.9 Switching Characteristics: SN54LVC74A over recommended operating free-air temperature range (unless otherwise noted; see Figure 3) PARAMETER fmax Maximum clock frequency FROM (INPUT) TO (OUTPUT) -- -- MIN VCC = 2.7 V Propagation (delay) time Q or Q PRE or CLR MAX 83 VCC = 3.3 V 0.3 V UNIT MHz 100 VCC = 2.7 V CLK tpd TEST CONDITIONS 6 VCC = 2.7 V 1 VCC = 3.3 V 0.3 V 5.2 6.4 VCC = 3.3 V 0.3 V 1 5.4 MIN MAX ns 6.10 Switching Characteristics: SN74LVC74A over recommended operating free-air temperature range (unless otherwise noted; see Figure 3) PARAMETER fmax Maximum clock frequency FROM (INPUT) TO (OUTPUT) -- -- CLKPRE tpd Propagation (delay) time Q or Q or CLR TEST CONDITIONS 83 MHz VCC = 1.8 V 0.15 V 1 7.1 VCC = 2.5 V 0.2 V 1 4.4 VCC = 1.8 V 0.15 V 1 6.9 VCC = 2.5 V 0.2 V 1 4.6 Copyright (c) 1993-2017, Texas Instruments Incorporated Product Folder Links: SN54LVC74A SN74LVC74A UNIT Submit Documentation Feedback ns 7 SN54LVC74A, SN74LVC74A SCAS287U - JANUARY 1993 - REVISED JANUARY 2017 www.ti.com 6.11 Switching Characteristics: SN74LVC74A, -40C to 125C and -40C to 85C over recommended operating free-air temperature range (unless otherwise noted; see Figure 3) PARAMETER fmax FROM (INPUT) TO (OUTPUT) -- -- Maximum clock frequency TEST CONDITIONS MIN VCC = 2.7 V TA = -40C to 125C 100 Propagation (delay) time tpd Q or Q 1 5.2 TA = -40C to 85C and VCC = 3.3 V 0.3 V VCC = 2.7 V Skew (time), output -- -- 1 5.2 1 6.4 VCC = 3.3 V 0.3 V ns 5.4 TA = -40C to 85C and VCC = 3.3 V 0.3 V tsk(o) 6 VCC = 3.3 V 0.3 V TA = -40C to 125C PRE or CLR MHz 150 VCC = 2.7 V TA = -40C to 125C UNIT 83 VCC = 3.3 V 0.3 V TA = -40C to 85C and VCC = 3.3 V 0.3 V CLK MAX 1 5.4 TA = -40C to 85C and VCC = 3.3 V 0.3 V 1 ns 6.12 Operating Characteristics TA = 25C PARAMETER Cpd Power dissipation capacitance per flip-flop TEST CONDITIONS TYP VCC = 1.8 V 24 VCC = 2.5 V 24 VCC = 3.3 V 26 f = 10 MHz UNIT pF 6.13 Typical Characteristics 10 14 12 VCC = 3 V, TA = 25C tpd - Propagation Delay Time - ns tpd - Propagation Delay Time - ns VCC = 3 V, TA = 25C One Output Switching Four Outputs Switching Eight Outputs Switching 10 8 6 4 6 4 2 2 0 50 100 150 200 250 300 CL - Load Capacitance - pF Figure 1. Propagation Delay (Low-to-High Transition) vs Load Capacitance 8 One Output Switching Four Outputs Switching Eight Outputs Switching 8 Submit Documentation Feedback 0 50 100 150 200 250 300 CL - Load Capacitance - pF Figure 2. Figure 2. Propagation Delay (High-to-Low Transition) vs Load Capacitance Copyright (c) 1993-2017, Texas Instruments Incorporated Product Folder Links: SN54LVC74A SN74LVC74A SN54LVC74A, SN74LVC74A www.ti.com SCAS287U - JANUARY 1993 - REVISED JANUARY 2017 7 Parameter Measurement Information VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 2.7 V 3.3 V 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V 2 ns 2 ns 2.5 ns 2.5 ns VM VLOAD CL RL V VCC/2 VCC/2 1.5 V 1.5 V 2 x VCC 2 x VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 k 500 500 500 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM th VI VM Data Input VM VM 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input 0V VOH VM Output VM VOL VM 0V VLOAD/2 VM VOL + V tPZH VOH Output VM tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPHL VM tPZL tPHL tPLH VI Output Control VM VM VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VM VOH - V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. VOH 0 V A. F. VOL Figure 3. Load Circuit and Voltage Waveforms Copyright (c) 1993-2017, Texas Instruments Incorporated Product Folder Links: SN54LVC74A SN74LVC74A Submit Documentation Feedback 9 SN54LVC74A, SN74LVC74A SCAS287U - JANUARY 1993 - REVISED JANUARY 2017 www.ti.com 8 Detailed Description 8.1 Overview The SNx4LVC74A devices feature two independent positive-edge triggered D flip-flops. Integrated preset (PRE) and clear (CLR) functions allow for easy setup and control during operation. The SN54LVC74A device is specified from -55C to 125C, and the SN74LVC74A device is specified from -40C to 125C. 8.2 Functional Block Diagram Copyright (c) 2016, Texas Instruments Incorporated 8.3 Feature Description A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. 8.4 Device Functional Modes Table 1 describes the SNx4LVC74A functionality and interactions between the PRE, CLR, CLK, and D inputs. Table 1. Function Table INPUTS (1) 10 OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H (1) H (1) H H H H L H H L L H H H L X Q0 Q0 This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. Submit Documentation Feedback Copyright (c) 1993-2017, Texas Instruments Incorporated Product Folder Links: SN54LVC74A SN74LVC74A SN54LVC74A, SN74LVC74A www.ti.com SCAS287U - JANUARY 1993 - REVISED JANUARY 2017 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information A common application for the SN74LVC74A is a frequency divider. By connecting the Q output to the D input, the Q output toggles states on each positive edge of the incoming clock signal. Because it takes two positive edges, or two clock pulses, to complete one complete pulse on the output (one pulse to toggle from low to high, another to toggle from high to low), the incoming clock frequency is effectively divided by two. 9.2 Typical Application 3V Clock Input VCC Q 1D Q 1CLK Output GND SN74LVC74A Copyright (c) 2016, Texas Instruments Incorporated Figure 4. Frequency Divider 9.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Avoid bus contention because it can drive currents in excess of maximum limits. The high drive also creates fast edges into light loads, so consider routing and load conditions to prevent ringing. 9.2.2 Detailed Design Procedure 1. Recommended input conditions: - For rise time and fall time specification, see (t/V) in Recommended Operating Conditions. - For specified high and low levels, see (VIH and VIL) in Recommended Operating Conditions. - Inputs are overvoltage tolerant allowing them to go as high as (VI max) in Recommended Operating Conditions at any valid VCC. 2. Recommended maximum output conditions: - Load currents must not exceed (IO max) per output and must not exceed (Continuous current through VCC or GND) total current for the part. These limits are located in Absolute Maximum Ratings. - Outputs must not be pulled above VCC. Copyright (c) 1993-2017, Texas Instruments Incorporated Product Folder Links: SN54LVC74A SN74LVC74A Submit Documentation Feedback 11 SN54LVC74A, SN74LVC74A SCAS287U - JANUARY 1993 - REVISED JANUARY 2017 www.ti.com Typical Application (continued) 9.2.3 Application Curves 60 100 80 TA = 25C, VCC = 3 V, VIH = 3 V, VIL = 0 V, All Outputs Switching 40 TA = 25C, VCC = 3 V, VIH = 3 V, VIL = 0 V, All Outputs Switching 20 I OH - mA I OL - mA 60 40 0 -20 -40 20 -60 0 -80 -20 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 VOL - V Figure 5. Output Drive Current (IOL) vs LOW-level Output Voltage (VOL) 12 Submit Documentation Feedback 1.4 1.6 -100 -1 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VOH - V Figure 6. Output Drive Current (IOH) vs HIGH-level Output Voltage (VOH) Copyright (c) 1993-2017, Texas Instruments Incorporated Product Folder Links: SN54LVC74A SN74LVC74A SN54LVC74A, SN74LVC74A www.ti.com SCAS287U - JANUARY 1993 - REVISED JANUARY 2017 10 Power Supply Recommendations The power supply may be any voltage between the minimum and maximum supply voltage rating located in Recommended Operating Conditions. Each VCC terminal must have a good bypass capacitor to prevent power disturbance. A 0.1-F capacitor is recommended for devices with a single supply. If there are multiple VCC terminals, then 0.01-F or 0.022-F capacitors are recommended for each power terminal. It is permissible to parallel multiple bypass capacitors to reject different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of noise. The bypass capacitor must be installed as close to the power terminal as possible for the best results. 11 Layout 11.1 Layout Guidelines Inputs must not float when using multiple bit logic devices. In many cases, functions or parts of functions of digital logic devices are unused. Some examples include situations when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, they are tied to GND or VCC, whichever makes more sense or is more convenient. 11.2 Layout Example VCC Input Unused Input Output Unused Input Output Input Figure 7. Layout Diagram Copyright (c) 1993-2017, Texas Instruments Incorporated Product Folder Links: SN54LVC74A SN74LVC74A Submit Documentation Feedback 13 SN54LVC74A, SN74LVC74A SCAS287U - JANUARY 1993 - REVISED JANUARY 2017 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: Implications of Slow or Floating CMOS Inputs (SCBA004) 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now. Table 2. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY SN54LVC74A Click here Click here Click here Click here Click here SN74LVC74A Click here Click here Click here Click here Click here 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.7 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 14 Submit Documentation Feedback Copyright (c) 1993-2017, Texas Instruments Incorporated Product Folder Links: SN54LVC74A SN74LVC74A PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) 5962-9761601Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629761601Q2A SNJ54LVC 74AFK 5962-9761601QCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9761601QC A SNJ54LVC74AJ 5962-9761601QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9761601QD A SNJ54LVC74AW 5962-9761601VDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9761601VD A SNV54LVC74AW SN74LVC74AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A SN74LVC74ADBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A SN74LVC74ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A SN74LVC74ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A SN74LVC74ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A SN74LVC74ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A SN74LVC74ADT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A SN74LVC74ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A SN74LVC74APW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A SN74LVC74APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A SN74LVC74APWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LC74A Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 24-Aug-2018 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) SN74LVC74APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A SN74LVC74APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A SN74LVC74APWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A SN74LVC74APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A SN74LVC74ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LC74A SNJ54LVC74AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629761601Q2A SNJ54LVC 74AFK SNJ54LVC74AJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9761601QC A SNJ54LVC74AJ SNJ54LVC74AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9761601QD A SNJ54LVC74AW (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54LVC74A, SN54LVC74A-SP, SN74LVC74A : * Catalog: SN74LVC74A, SN54LVC74A * Automotive: SN74LVC74A-Q1, SN74LVC74A-Q1 * Enhanced Product: SN74LVC74A-EP, SN74LVC74A-EP * Military: SN54LVC74A * Space: SN54LVC74A-SP NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects * Enhanced Product - Supports Defense, Aerospace and Medical Applications * Military - QML certified for Military and Defense Applications * Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 30-Apr-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVC74ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74LVC74ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LVC74ADT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LVC74ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LVC74APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC74APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC74APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC74APWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Apr-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC74ADBR SSOP DB 14 2000 367.0 367.0 38.0 SN74LVC74ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LVC74ADT SOIC D 14 250 367.0 367.0 38.0 SN74LVC74ANSR SO NS 14 2000 367.0 367.0 38.0 SN74LVC74APWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74LVC74APWR TSSOP PW 14 2000 364.0 364.0 27.0 SN74LVC74APWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 SN74LVC74APWT TSSOP PW 14 250 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID (OPTIONAL) A 4X .005 MIN [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 [0.36-0.66] 14X .045-.065 [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 8 7 B .245-.283 [6.22-7.19] .2 MAX TYP [5.08] C .13 MIN TYP [3.3] SEATING PLANE .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 TYP 14X .008-.014 [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL A SEE DETAIL B 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 8 7 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX [0.05] ALL AROUND (.063) [1.6] METAL ( .063) [1.6] SOLDER MASK OPENING METAL (R.002 ) TYP [0.05] .002 MAX [0.05] ALL AROUND SOLDER MASK OPENING DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI's published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. 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Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer's noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2018, Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: SN74LVC74AD SN74LVC74ADR SN74LVC74APWR SN74LVC74ADBR SN74LVC74ARGYR SN74LVC74ADBRG4 SN74LVC74ADE4 SN74LVC74ADG4 SN74LVC74ADRE4 SN74LVC74ADRG4 SN74LVC74ADT SN74LVC74ANSR SN74LVC74APW SN74LVC74APWG4 SN74LVC74APWRE4 SN74LVC74APWRG4 SN74LVC74APWT SN74LVC74APWTG4 SN74LVC74ARGYRG4 SN74LVC74ADTG4