8308I Low Skew, 1-to-8 Differential/LVCMOS-toLVCMOS Fanout Buffer Data Sheet GENERAL DESCRIPTION FEATURES The 8308I is a low-skew, 1-to-8 Fanout Buffer. The 8308I has two selectable clock inputs. The CLK, nCLK pair can accept most differential input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 8 to 16 by utilizing the ability of the outputs to drive two series terminated transmission lines. * Eight LVCMOS/LVTTL outputs, (7 typical output impedance) * Selectable LVCMOS_CLK or differential CLK, nCLK inputs * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Maximum Output Frequency: 350MHz * Output Skew: (3.3V 5%): 100ps (maximum) * Part to Part Skew: (3.3V 5%): 1ns (maximum) The 8308I is characterized for 3.3V core/3.3V output, 3.3V core/2.5V output or 2.5V core/2.5V output operation. Guaranteed output and part-part skew characteristics make the 8308I ideal for those clock distribution applications requiring well defined performance and repeatability. * Supply Voltage Modes: (Core/Output) 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V * -40C to 85C ambient operating temperature * Available in lead-free (RoHS 6) package BLOCK DIAGRAM CLK_EN Pullup PIN ASSIGNMENT Q0 GND CLK_SEL LVCMOS_CLK CLK nCLK CLK_EN OE VDD GND Q1 VDDO D Q LVCMOS_CLK Pullup CLK Pullup nCLK Pulldown CLK_SEL LE 1 Q0 0 Pullup Q1 Q2 Q3 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDDO Q2 GND Q3 VDDO Q4 GND Q5 VDDO Q6 GND Q7 Q4 8308I Q5 24-Lead, 173-MIL TSSOP 4.4mm x 7.8mm x 0.925mm body package G Package Top View Q6 Q7 OE Pullup (c)2015 Integrated Device Technology, Inc 1 December 10, 2015 8308I Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name 1, 11, 13, 15, 17, 19, 21, 23 Q0, Q1, Q7, Q6, Q5, Q4,Q3, Q2 Type Description Output Clock outputs. LVCMOS / LVTTL interface levels. 2, 10, 14, 18, 22 GND Power Power supply ground. 3 CLK_SEL Input Pullup Clock select input. Selects LVCMOS clock input when HIGH. Selects CLK, nCLK inputs when LOW. See Table 3A. LVCMOS / LVTTL interface levels. 4 LVCMOS_CLK Input Pullup Clock input. LVCMOS / LVTTL interface levels. 5 CLK Input Pullup Non-inverting differential clock input. 6 nCLK Input 7 CLK_EN Input Pullup Clock enable. LVCMOS / LVTTL interface levels. 8 OE Input Pullup Output enable. LVCMOS / LVTTL interface levels. See Table 3B. 9 VDD Power Power supply pin. 12, 16, 20, 24 VDDO Power Output supply pins. Pulldown Inverting differential clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF CPD Power Dissipation Capacitance (per output) 12 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k ROUT Output Impedance 5 TABLE 3A. CLOCK SELECT FUNCTION TABLE Control Input 12 TABLE 3B. OE SELECT FUNCTION TABLE Control Input Clock Input CLK_SEL 7 OE Output Operation 0 CLK, nCLK is selected 0 Outputs Q0:Q7 are in Hi-Z (disabled) 1 LVCMOS_CLK is selected 1 Outputs Q0:Q7 are active (enabled) TABLE 3C. CLOCK INPUT FUNCTION TABLE Inputs Outputs Q0:Q7 Input to Output Mode Polarity CLK_SEL LVCMOS_CLK CLK nCLK 0 -- 0 1 LOW Differential to Single Ended Non Inverting 0 -- 1 0 HIGH Differential to Single Ended Non Inverting 0 -- 0 Biased; NOTE 1 LOW Single Ended to Single Ended Non Inverting 0 -- 1 Biased; NOTE 1 HIGH Single Ended to Single Ended Non Inverting 0 -- Biased; NOTE 1 0 HIGH Single Ended to Single Ended Inverting 0 -- Biased; NOTE 1 1 LOW Single Ended to Single Ended Inverting 1 0 -- -- LOW Single Ended to Single Ended Non Inverting 1 1 -- -- HIGH Single Ended to Single Ended Non Inverting NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels". (c)2015 Integrated Device Technology, Inc 2 December 10, 2015 8308I Data Sheet ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 70C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40 TO 85 Symbol Parameter Minimum Typical Maximum Units VDD Power Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 46 mA IDDO Output Supply Current 11 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40 TO 85 Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 46 mA IDDO Output Supply Current 10 mA TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD, VDDO = 2.5V5%, TA = -40 TO 85 Symbol Parameter Minimum Typical Maximum Units VDD Power Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 43 mA IDDO Output Supply Current 10 mA (c)2015 Integrated Device Technology, Inc Test Conditions 3 December 10, 2015 8308I Data Sheet TABLE 4D. DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40 TO 85 Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIN Input Current VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VPP Peak-to-Peak Input Voltage Test Conditions LVCMOS LVCMOS_CLK Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 1.3 V 0.8 V 300 A CLK_EN, OE VIN = VDD or VIN = GND IOH = -24mA 2.4 V IOL = 24mA IOL = 12mA CLK, nCLK 0.15 Input Common Mode Voltage; CLK, nCLK GND + 0.5 NOTE 2, 3 NOTE 1: Outputs capable of driving 50 transmission lines terminated with 50 to VDDO/2. See Parameter Measurement section, "3.3V Output Load AC Test Circuit". NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 3: Common mode voltage is defined as VIH. VCMR 0.55 V 0.30 V 1.3 V VDD - 0.85 V TABLE 4E. DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40 TO 85 Symbol Parameter VIH Input High Voltage Test Conditions VIL Input Low Voltage IIN Input Current VOH Output High Voltage; NOTE 1 IOH = -15mA VOL Output Low Voltage; NOTE 1 IOL = 15mA VPP Peak-to-Peak Input Voltage LVCMOS LVCMOS_CLK Minimum Maximum Units 2 VDD + 0.3 V -0.3 1.3 V 0.8 V 300 A CLK_EN, OE VIN = VDD or VIN = GND CLK, nCLK 1.8 0.15 Input Common Mode Voltage; VCMR CLK, nCLK GND + 0.5 NOTE 2, 3 NOTE 1: Outputs capable of driving 50 transmission lines terminated with 50 to VDDO/2. See Parameter Measurement section, "3.3V Output Load AC Test Circuit". NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 3: Common mode voltage is defined as VIH. (c)2015 Integrated Device Technology, Inc 4 Typical V 0.6 V 1.3 V VDD - 0.85 V December 10, 2015 8308I Data Sheet TABLE 4F. DC CHARACTERISTICS, VDD, VDDO = 2.5V5%, TA = -40 TO 85 Symbol Parameter VIH Input High Voltage Maximum Units LVCMOS Test Conditions VIL Input Low Voltage IIN Input Current VOH Output High Voltage; NOTE 1 IOH = -15mA VOL Output Low Voltage; NOTE 1 IOL = 15mA VPP Peak-to-Peak Input Voltage Minimum 1.7 Typical VDD + 0.3 V LVCMOS_CLK -0.3 0.7 V 0.7 V 300 A CLK_EN, OE VIN = VDD or VIN = GND CLK, nCLK 1.8 V 0.15 Input Common Mode Voltage; CLK, nCLK GND + 0.5 VCMR NOTE 2, 3 NOTE 1: Outputs capable of driving 50 transmission lines terminated with 50 to VDDO/2. See Parameter Measurement section, "3.3V Output Load AC Test Circuit". NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 3: Common mode voltage is defined as VIH. 0.6 V 1.3 V VDD - 0.85 V Maximum 350 Units MHz TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40 TO 85 Symbol fOUT tPD Parameter Output Frequency Propagation Delay; CLK, nCLK; NOTE 1 LVCMOS_CLK; NOTE 2 Test Conditions Minimum Typical 350MHz 2 4 ns 350MHz 2 4 ns tsk(o) Output Skew; NOTE 3, 7 Measured on rising edge @VDDO/2 100 ps tsk(pp) Part-to-Part Skew; NOTE 4, 7 Measured on rising edge @VDDO/2 1 ns tR / tF Output Rise/Fall Time odc Output Duty Cycle tPZL, tPZH Output Enable Time; NOTE 5 0.8V to 2V 0.2 1 ns 150MHz, Ref = CLK, nCLK 45 55 % 5 ns tPLZ, tPHZ Output Disable Time; NOTE 5 5 ns CLK_EN to CLK, 1 ns Clock Enable nCLK tS Setup Time; CLK_EN to LVCNOTE 6 0 ns MOS_CLK CLK, nCLK to 0 ns Clock Enable CLK_EN Hold Time; tH LVCMOS_CLK NOTE 6 1 ns to CLK_EN NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. (c)2015 Integrated Device Technology, Inc 5 December 10, 2015 8308I Data Sheet TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40 TO 85 Symbol fOUT tPD Parameter Output Frequency Propagation Delay; CLK, nCLK; NOTE 1 LVCMOS_CLK; NOTE 2 Test Conditions Minimum 350MHz 350MHz Typical Maximum 350 Units MHz 2 4 ns 2 4 ns tsk(o) Output Skew; NOTE 3, 7 Measured on rising edge @VDDO/2 100 ps tsk(pp) Part-to-Part Skew; NOTE 4, 7 Measured on rising edge @VDDO/2 1 ns tR / tF Output Rise/Fall Time ns odc Output Duty Cycle tPZL, tPZH Output Enable Time; NOTE 5 0.6V to 1.8V 0.2 1.0 150MHz, Ref = CLK, nCLK 45 55 % 5 ns tPLZ, tPHZ Output Disable Time; NOTE 5 5 ns CLK_EN to CLK, 1 ns Clock Enable nCLK tS Setup Time; CLK_EN to LVCNOTE 6 0 ns MOS_CLK CLK, nCLK to 0 ns Clock Enable CLK_EN tH Hold Time; LVCMOS_CLK NOTE 6 1 ns to CLK_EN NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. (c)2015 Integrated Device Technology, Inc 6 December 10, 2015 8308I Data Sheet TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = -40 TO 85 Symbol fOUT tPD Parameter Output Frequency Propagation Delay; CLK, nCLK; NOTE 1 LVCMOS_CLK; NOTE 2 Test Conditions Minimum 350MHz 350MHz Typical Maximum 350 Units MHz 1.5 4.2 ns 1.7 4.4 ns tsk(o) Output Skew; NOTE 3, 7 Measured on rising edge @VDDO/2 160 ps tsk(pp) Part-to-Part Skew; NOTE 4, 7 Measured on rising edge @VDDO/2 2 ns tR / tF Output Rise/Fall Time ns odc Output Duty Cycle tPZL, tPZH Output Enable Time; NOTE 5 0.6V to 1.8V 0.2 1.0 150MHz, Ref = CLK, nCLK 40 60 % 5 ns tPLZ, tPHZ Output Disable Time; NOTE 5 5 ns CLK_EN to CLK, 1 ns Clock Enable nCLK tS Setup Time; CLK_EN to LVCNOTE 6 0 ns MOS_CLK CLK, nCLK to 0 ns Clock Enable CLK_EN tH Hold Time; LVCMOS_CLK NOTE 6 1 ns to CLK_EN NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. (c)2015 Integrated Device Technology, Inc 7 December 10, 2015 8308I Data Sheet PARAMETER MEASUREMENT INFORMATION 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL OUTPUT SKEW PART-TO-PART SKEW (c)2015 Integrated Device Technology, Inc 8 December 10, 2015 8308I Data Sheet PARAMETER MEASUREMENT INFORMATION, CONTINUED PROPAGATION DELAY OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD (c)2015 Integrated Device Technology, Inc 9 December 10, 2015 8308I Data Sheet APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single-ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the FIGURE 1. RECOMMENDED SCHEMATIC FOR WIRING A DIFFERENTIAL INPUT TO ACCEPT SINGLE-ENDED LEVELS (c)2015 Integrated Device Technology, Inc 10 December 10, 2015 8308I Data Sheet DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both differential signals must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for IDT LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 2A. CLK/nCLK INPUT DRIVEN BY IDT'S LVHSTL DRIVER FIGURE 2B. CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm Zo = 50 Ohm LVDS_Driv er CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 2C. CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 2D. CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 2E. CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE (c)2015 Integrated Device Technology, Inc 11 December 10, 2015 8308I Data Sheet SCHEMATIC EXAMPLE Figure 3 shows a schematic example of the 8308I. In this example, the LVCMOS_CLK input is selected. The decoupling capacitors should be physically located near the power pin. VDD Zo = 50 Ohm R1 R9 1K R10 1K R12 1K 43 VDD VDD U1 3.3V LVCMOS/LVTTL VDD R11 1 2 3 4 5 6 7 8 9 10 11 12 Zo = 50 Ohm Ro ~ 7 Ohm 43 3.3V_LVCMOS VDD=3.3V (U1,9) VDD C1 0.1u (U1,12) (U1,16) C2 0.1u VDDO Q2 GND Q3 VDDO Q4 GND Q5 VDDO Q6 GND Q7 24 23 22 21 20 19 18 17 16 15 14 13 C4 0.1u Zo = 50 Ohm R8 (U1,24) (U1,20) C3 0.1u Q0 GND CLK_SEL LVCMOS_CLK CLK nCLK CLK_EN OE VDD GND Q1 VDDO C5 0.1u 43 ICS8308I 3.3V LVCMOS/LVTTL FIGURE 3. 8308I LVPECL BUFFER SCHEMATIC EXAMPLE RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS_CLK INPUT For applications not requiring the use of an LVCMOS_CLK, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the LVCMOS_CLK input to ground. LVCMOS OUTPUTS All unused LVCMOS outputs can be left floating. There should be no trace attached. CLK/nCLK INPUTS For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. LVCMOS CONTROL PINS All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Power On Sequence There is no power on sequence requirement for the VDD and VDDO. If the VDDO is turned on before the VDD, there will be unknown state at the outputs during initial condition when the VDDO is on and VDD is off. (c)2015 Integrated Device Technology, Inc 12 December 10, 2015 8308I Data Sheet RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP JA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 70C/W 63C/W 60C/W TRANSISTOR COUNT The transistor count for 8308I is: 1040 PACKAGE OUTLINE AND DIMENSIONS PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 24 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 E E1 7.90 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -0.10 REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153 (c)2015 Integrated Device Technology, Inc 13 December 10, 2015 8308I Data Sheet TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 8308AGILF ICS8308AGILF 24 Lead "Lead-Free" TSSOP tube -40C to 85C 8308AGILFT ICS8308AGILF 24 Lead "Lead-Free" TSSOP tape & reel -40C to 85C (c)2015 Integrated Device Technology, Inc 14 December 10, 2015 8308I Data Sheet REVISION HISTORY SHEET Rev Table Added Schematic Layout 1 3 4 6 8 14 Features section - added mix supply voltage bullet. Added Mix Power Supply Table. Added Mix DC Characteristics Table. Added Mix AC Characteristics Table. Added Mix Output Load AC Test Circuit Diagram. Ordering Information Table - added "Lead-Free" part number. T8 1 10 14 1 Corrected Block Diagram, added CLK_SEL. Added "Recommendations for Unused Input and Output Pins". Ordering Information Table - added Lead-Free note. Pin Assignment - corrected package information from 300-MIL to 173-MIL. T3B 2 Added OE Select Function Table. T4F T5A - T5C T8 10 12 5 5 -7 14 B T4B T4E T5B B T8 B B C C C C Description of Change 11 A B Page T8 12 14 1 4/16/04 10/20/04 1/12/05 7/25/05 8/4/06 10/16/07 DC Characteristics - corrected VIH min. from 2V to 1.7V; VIL max. from 1.3V to 0.7V. AC Characteristics - added thermal note. Ordering Information Table - deleted ICS prefix from Part/Order Number column. Updated Wiring the Differential Input to Accept Single-ended Levels application note. Added Power On Sequence application note. Recommended for Unusted I/O Pins - changed CLK Input: to LVCMOS_CLK. deleted lead-free note. Removed ICS from the part numbers thoughout the datasheet. Removed reference to leaded devices in features section. Updated header and footer. (c)2015 Integrated Device Technology, Inc Date 15 7/16/09 3/23/11 4/4/13 12/10/15 December 10, 2015 8308I Data Sheet Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright (c)2015 Integrated Device Technology, Inc. All rights reserved.