NJU8753 PRELIMINARY Analog Signal Input Class-D Amplifier with DC-DC Converter for Piezo Speaker PACKAGE OUTLINE GENERAL DESCRIPTION The NJU8753 is an analog signal input monaural class D power amplifier with DC-DC converter for Piezo speaker. Input part operates on 2.85V(typ) and a built-in DC-DC converter generates variable output voltage(up to 12V) with input voltage(2.6 to 4.2V). Therefore, it drives Piezo speaker with louder sound and high efficiency. The NJU8753 incorporates BTL amplifier, which eliminate AC coupling capacitors, capable of driving Piezo speaker with simple external LC low-pass filters. Class D operation achieves lower power operation for Piezo speaker, thus the NJU8753 is suited for battery- powered applications. NJU8753KN1 FEATURES Operating Voltage :2.6 to 3.6V(VDD, VREG) :2.6 to 4.2V(VBAT) :8Vrms(Typ.) @VDDO=10.0V Output voltage Piezo Speaker Driving 1-channel Analog Signal Input, 1-channel BTL output Standby(Hi-Z), Built-in DC-DC Converter Built-in Low Voltage Detector Built-in Short Protector CMOS Technology Package Outline :QFN28 28 VDD VSS IN COM EN1 TEST2 VDDO TERMINAL CONFIGURATION 1 VOUT VR EN2 NC VDDO VDDO OUTP VSS NC VSS OUTN VDDO LX LX TEST1 TEST3 VREG FB VSS VSS1 VSS1 QFN28 Ver.2009-03-10 -1- NJU8753 BLOCK DIAGRAM VDD VSS VREG VOUT TEST1 TEST2 TEST3 Lx VR FB EN2 VSS1 Switching Regulator RFB IN RIN 20k - VDDO 70k OUTP + - COM + VSS Pulse Width Modulator VDDO x5 OUTN VSS Short Protector Soft Start Control Logic Low Voltage Detector EN1 -2- Ver.2009-03-10 NJU8753 NJU3555 TERMINAL DESCRIPTION No. 1, 2, 23 3 4 5, 17, 19, 27 6,7 8,9 10 11 SYMBOL TEST1 TEST3 TEST2 VREG FB I/O Function I Maker test These terminals must be connected to GND. - I Switching regulator Power Supply : VREG=2.85V Switching regulator Feedback resistor connection VSS - Power GND : VSS=0V VSS1 Lx VOUT VR - I - O 12 EN2 I 13, 18 14, 15, 21, 22 16 20 NC - Switching regulator Power GND: VSS1=0V Switching regulator coil connection Switching regulator Power Supply : VOUT=10.0V Switching regulator step-up voltage setting resistor connection Switching regulator Standby Control High : Step-up ON Low : Standby ON This terminal must be connected to VREG when step-up ON. Non connection VDDO - Output Power supply OUTN OUTP O O Negative Output Positive Output Power Amplifier Standby Control 24 EN1 I High : Standby OFF Low : Standby ON This terminal must be connected to VDD when Standby OFF. 25 COM - Analog common 26 IN I Audio Signal Input 28 VDD - Power Supply: VDD=2.85V * VSS terminals(pins 5 and 17 and 19 and 27), VSS1 terminals(pins 6 and 7) should be connected at the nearest point to the IC. * VDDO terminals(pins 14 and 15 and 21 and 22) should be connected at the nearest point to the IC. * OUTP terminal(pin 20), OUTN terminal(pin 16) require Schottky barrier diodes. (Refer to the "TYPICAL APPLICATION CIRCUIT") * Lx terminals(pins 8 and 9) require caution to the extraneous noise including the ESD(electrical static discharge) because the ESD protection can't be designed as well as other terminals. Require extra caution when the input voltage (VBAT: Refer to the "TYPICAL APPLICATION CIRCUIT") to the Lx terminal is supplied directly from the external because the extraneous noise including the ESD appears easily. Ver.2009-03-10 -3- NJU8753 FUNCTIONAL DESCRIPTION (1) Input signal The amount of current passing through a capacitive load increases proportionately with frequency of audio signal. Input filters should be put in the input line to reduce load current at high frequency-band. The 1st-order RC type HPF(High Pass Filter) and the 1st-order RC type LPF(Low Pass Filter) are composed of input filters. fCH1(Cut-off frequency of HPF) and fCL1(Cut-off frequency of LPF) are determined by input resistance(RIN), resistor for LPF(RLPF), capacitor for LPF(CLPF) and AC coupling capacitor(CC). (RLPF, CLPF, CC: Refer to the "TYPICAL APPLICATION CIRCUIT") When RIN=20k, RLPF=2.4k and CLPF=0.022F, CC=2.2F, fCH1 and fCL1 are roughly calculated as following expressions. f CH1 = 1 1 = 5[Hz] 2 ( RIN + RLPF )CC 2 x 3.14 x (20 x 103 + 2.4 x 103 ) x 2.2 x 10-6 f CL1 = 1 1 = 3[kHz] 2 ( RIN // RLPF )CLPF 2 x 3.14 x (20 x 103 // 2.4 x 103 ) x 0.022 x 10-6 When SBDs are added between OUTP and VSS, OUTN and VSS, the fCL1(Cut-off frequency of LPF) must be less than 7KHz. When SBDs are not added, the fCL1 must be less than 3KHz. Input amplitude impressed to IN terminal of IC (VIC) must be less than VDD[Vpp]. When VDD=2.85V, RLPF=2.4k , Audio signal maximum input level VINMAX for considering as VIC<=VDD [Vpp] VINMAX are roughly calculated as following expressions. VINMAX = (R LPF + R IN ) x VIC R IN = (2.4 x 10 3 ) + 20 x 103 x 2.85 3.1[Vpp] 20 x 103 (2) Output signal The OUTP and OUTN generate PWM output signals, which will be converted to analog signal via external 2nd-order or higher LC filter. LC type LPF is composed of the coil (L) and Piezo Speaker (CL). The dump resistance (RDAMP) is connected between the OUTN terminal and the coil between the OUTP terminal and the coil to reduce the cut off frequency (fc) of LPF consumption electric current neighborhood signal input. Set it up so that the value of L, CL and RDAMP may become Gain(Q) <1 of LPF in fc. (L, CL, COUT, RDAMP : Refer to the "TYPICAL APPLICATION CIRCUIT") When L=47H, CL=2.0F, COUT=0.1F, RDAMP =4.7, RDCR=0.2, LPF(fc) and Q are roughly calculated as following expressions. fc = Q= 1 1 = 11[kHz] 2 L(2CL + COUT ) 2 x 3.14 x 47 x 10- 6 x 2 x 2.0 x 10- 6 + 0.1 x 10- 6 1 (RDAMP + RDCR ) ( 1 L = x (2CL + COUT ) (4.7 + 0.2) ) 47 x 10-6 0.7 2 x 2.0 x 10- 6 + 0.1 x 10- 6 ( ) (3) Power Amplifier Standby By setting the EN1 terminal to "L", the standby mode is enabled. In the standby mode, the entire functions of the NJU8753 enter a low-power state, and the output terminals (OUTP and OUTN) are high impedance. (4) Low Voltage Detector When the power supply voltage drops down to below VDD(MIN), the internal oscillation is halted for prevention to generate unwanted frequency, and the output terminals (OUTP, OUTN) become in high impedance. -4- Ver.2009-03-10 NJU8753 NJU3555 (5) Step-up switching regulator The switching regulator is used as power supply(VDDO) for power amplifier of class-D. The PFM controlled switching regulator works with external components, which are coil, capacitor, Schottky barrier diode and step-up voltage setting resistance. By setting the EN2 terminal to "H", the step-up operation is enabled, and in case of "L", standby mode is enabled. Step-up voltage is set by internal reference voltage(VREG / 2) and external resistors. The step-up voltage can be calculated by the following methods: <Calculation of the step-up voltage> The step-up voltage is determined by internal reference voltage(VREF), R1 and R2. (See Figure.2) example: VDD=2.85V, Internal reference voltage(VREF) = VREG / 2=1.425[V], R1=2M, Step-up voltage[V] = VREFx((R1+R2)/R2) = 1.425x((2M + 330k)/330k) = 10.06[V] " R2=330k" Note) *1 Apply VREG first, next VBAT. Otherwise, the voltage stress may cause a permanent damage to the IC. *2 The kickback voltage by the step-up voltage operation varies with the fixed number of the external components and the PCB patterns. Output power supply(VDDO) must not exceed the absolute maximum rating. (6) Short Circuit Protection The short protector, which protects the NJU8753 against high short-circuit current, turns off the output driver. After about 5 seconds from the protection, the NJU8753 returns to normal operation. The short protector functions at the following accidents. -Short between OUTP and OUTN -Short between OUTP and VSS -Short between OUTN and VSS Note) *1 The detectable current and the period for the protection depend on the power supply voltage, chip temperature and ambient temperature. *2 The short protector is not effective for a long term short-circuit current but for an instantaneous accident. Continuous high-current may cause permanent damage to the NJU8753. Ver.2009-03-10 -5- NJU8753 ABSOLUTE MAXIMUM RATINGS PARAMETER CONDITIONS LX Input Voltage VLX FB Input Voltage Input Voltage Operating Temperature Storage Temperature Power Dissipation VFB Vin RATING -0.3 to +4.0 -0.3 to +4.0 -0.3 to +14.0 -0.3 to +9.5 -0.3 to +14.0 -0.3 to +9.5 -0.3 to +4.0 -0.3 to VDD+0.3 Topr -40 to +85 C Tstg -40 to +125 C PD 640 * mW Supply Voltage SYMBOL VDD VREG (Ta=25C) UNIT Note V V VDDO With SBDs Without SBDs With SBDs Without SBDs. V 6 V 6 V V * : Mounted on two-layer board of based on the JEDEC. Note 1) All voltage are relative to "VSS= 0V" reference. Note 2) The LSI must be used inside of the "Absolute maximum ratings". Otherwise, a stress may cause permanent damage to the LSI. -6- Ver.2009-03-10 NJU8753 NJU3555 ELECTRICAL CHARACTERISTIC (Ta=25C, VDD=VREG=2.85V, VBAT=3.7V, VDDO=10V, VSS=VSS1=0V, TEST1=TEST2=TEST3=0V, EN1=EN2=2.85V, Input Signal=1kHz, Input Signal Level=150mVrms,Frequency Band=20Hz to 20kHz, Load Impedance=2.0F, 2nd-order 11kHz LC Filter(Q=0.7), When the SBDs are connected between OUTP and VSS, OUTN and VSS.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Note VDD VDD Supply Voltage 2.6 2.85 3.6 V VREG VREG Supply Voltage 2.6 2.85 3.6 V VBAT VBAT Input Voltage 2.6 3.7 4.2 V With SBDs 6.5 10.0 12.0 VDDO Supply Voltage VDDO V 6 Without SBDs. 6.5 7.5 8.5 Input Impedance ZIN IN terminal 20 K Voltage Gain AV 31 dB THD Input Signal Level =200mVrms THD+N 0.05 0.08 % 4 Vo Output THD+N=10% Maximum Output 8.0 Vrms S/N SN A weight 80 dB 4 Operating Current(Standby) IST EN1=EN2=0V 1 A Operating Current No-load operating ISS 10 15 mA (No signal input) No Signal Input EN1, EN2 terminals VIH VDD V 0.7VDD Input Voltage EN1, EN2 terminals V VIL 0 0.3VDD EN1, EN2 terminals Input Leakage Current ILK 1.0 A Switching regulator fOSC 220 300 380 kHz Oscillating Frequency Switching regulator Step-up Voltage =10.0V 50 mA IOUT VOUT= 10.0V X 95% Maximum Load Current Switching regulator Step-up Voltage =10.0V 100 mV VOUT IOUT =10mA to 50mA Load Stability *The LSI must be used within the "Absolute maximum ratings". Otherwise, a stress may cause permanent damage to the LSI. Note 3) Test system of the THD+N and S/N The THD+N and S/N are tested in the system shown in Figure 1, where a 2nd-order LC LPF and another filter incorporated in an audio analyzer are used. Input Signal NJU8753 2nd-order LC LPF NJU8753 Test Board Filter 20kHz (AES17) THD Measuring Apparatus Audio Analyzer Figure 1. Output THD+N and S/N Test System 2nd-order LC LPF Filters Ver.2009-03-10 : Refer to "Typical Application Circuit" : 22Hz HPF + 20kHz LPF(AES17) (with the A-Weight filter for S/N test) -7- NJU8753 TYPICAL APPLICATION CIRCUIT RDUMP 10F 0.1F VDD 4.7 VDD(28) L 47H OUTP(20) OUTN(16) 10F 0.1F VDD IN 2.4k CIN 0.1F IN(26) CLPF 0.22F COM(25) NJU8753 RLPF RDUMP SBD VREG(3) VSS(5) 4.7 CL:2F COUT 0.1F SBD VSS(27) Piezo Speaker 47uH 0.1F COUT L 22H(DCR=0.5) VBAT Lx(8,9) SBD VDDO(21,22) VDDO(14,15) VOUT(10) 10F EN1(24) EN2(12) TEST1(1) TEST2(23) TEST3(2) VR(11) R1 2M FB(4) VSS1(6,7) VSS(17,19) 22F 0.1F R2 330k 10F 0.1F Figure 2. Application Circuit example Note 4) De-coupling capacitors must be connected between each power supply terminal and GND. Note 5) The LC filter and the schottky barrier diodes should be laid out nearest to the IC. OUTP terminal(pin 20), OUTN terminal(pin 16) require schottky barrier diodes for terminal protection. When SBDs is not used, the VDDO supply voltage maximum is 8.5V. (SBD: When Tj=125C, IR=less than 10mA at reverse voltage12V*1. When Tj=25C, Forward voltage (VF) =0.45V, Forward current (IF) =more than1A at more than 12V) *1 Absolute maximum ratings is more than 20V. Note 6) The LSI must be used inside of the following ratings. Otherwise, a stress may cause permanent damage to the regulator. VDDO (Supply Voltage) Input cut-off frequency Output cut-off frequency Q (The gain of LPFat fc) Piezo Speaker The capacitor between VDDO and VSS The coil for Lx terminal Input voltage SBDs are added No SBDs MAX=12V MAX=8.5V MAX=7kHz MAX=3kHz MAX=15kHz MAX=1 MAX=2.2F MAX=22F MIN=22H MAX=VDD[Vpp] Note 7) The transition time for EN1 and EN2 signals must be less than 100s. Otherwise, a malfunction may be occurred. -8- Ver.2009-03-10 NJU8753 NJU3555 Note 8) Apply VREG first, next VBAT. Otherwise, the voltage stress may cause a permanent damage to the IC. The VDDO is not able to accept from external power supply. Therefore use the DC-DC converter of the NJU8753. Note 9) The Lx terminals require caution to the extraneous noise including the ESD(electrical static discharge) because the ESD protection can't be designed as well as other terminals. Require extra caution when the input voltage (VBAT) to the Lx terminal is supplied directly from the external because the extraneous noise including the ESD appears easily. Note 10) The kickback voltage by the step-up voltage operation varies with the fixed number of the external components and the PCB patterns. Output power supply(VDDO) must not exceed the absolute maximum rating. Note 11) The above circuit shows only application example and does not guarantee the any electrical characteristics. Therefore, please test the circuit carefully to fit your application. The cut off frequency of the LC filter influences the quality of sound. The Q factor of the LC filter must be less than "1". Otherwise, the operating current increase when the frequency of input signal is closed to the cut off frequency. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.2009-03-10 -9- Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NJR: NJU8753KN1