VN7010AJ-E High-side driver with MultiSense analog feedback for automotive applications Datasheet - production data - Self limiting of fast thermal transients - Configurable latch-off on overtemperature or power limitation with dedicated fault reset pin - Loss of ground and loss of VCC - Reverse battery with external components - Electrostatic discharge protection Features Applications Max transient supply voltage VCC 40 V Operating voltage range VCC 4 to 28 V * All types of Automotive resistive, inductive and capacitive loads 10 m * Specially intended for Automotive Headlamps Typ. on-state resistance (per Ch) RON Current limitation (typ) ILIMH 91 A Standby current (max) ISTBY 0.5 A * Automotive qualified * General - Single channel smart high side driver with MultiSense analog feedback - Very low standby current - Compatible with 3 V and 5 V CMOS outputs * MultiSense diagnostic functions - Multiplexed analog feedback of: load current with high precision proportional current mirror, VCC supply voltage and TCHIP device temperature - Overload and short to ground (power limitation) indication - Thermal shutdown indication - OFF-state open-load detection - Output short to VCC detection - Sense enable/ disable * Protections - Undervoltage shutdown - Overvoltage clamp - Load current limitation October 2014 This is information on a product in full production. Description The VN7010AJ-E is a single channel high-side driver manufactured using ST proprietary VIPower(R) technology and housed in PowerSSO-16 package. The device is designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible interface, and to provide protection and diagnostics. The device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality. A dedicated multifunction multiplexed analog output pin delivers sophisticated diagnostic functions such as high precision proportional load current sense, supply voltage feedback and chip temperature sense, in addition to the detection of overload and short circuit to ground, short to VCC and OFF-state open-load. A sense enable pin allows OFF-state diagnosis to be disabled during the module low-power mode as well as external sense resistor sharing among similar devices. DocID022509 Rev 9 1/46 www.st.com Contents VN7010AJ-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 4 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Main electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1 Power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3 Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4 Negative voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 29 4.1.1 4.2 Immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . 30 4.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.4 Multisense - analog current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.5 5 2/46 4.4.1 Principle of Multisense signal generation . . . . . . . . . . . . . . . . . . . . . . . 33 4.4.2 TCASE and VCC monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.4.3 Short to VCC and OFF-state open-load detection . . . . . . . . . . . . . . . . . 36 Maximum demagnetization energy (VCC = 16 V) . . . . . . . . . . . . . . . . . . . 37 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1 6 Diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PowerSSO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1 ECOPACK(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.2 PowerSSO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DocID022509 Rev 9 VN7010AJ-E Contents 7 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 DocID022509 Rev 9 3/46 3 List of tables VN7010AJ-E List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. 4/46 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Switching (VCC = 13 V; -40C < Tj < 150C, unless otherwise specified) . . . . . . . . . . . . . . 11 Logic Inputs (7 V < VCC < 28 V; -40C < Tj < 150C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Protections (7 V < VCC < 18 V; -40C < Tj < 150C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MultiSense (7 V < VCC < 18 V; -40C < Tj < 150C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 MultiSense multiplexer addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ISO 7637-2 - electrical transient conduction along supply line . . . . . . . . . . . . . . . . . . . . . 30 Multisense pin levels in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PowerSSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 DocID022509 Rev 9 VN7010AJ-E List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 IOUT/ISENSE versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Current sense accuracy versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Switching times and Pulse skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MultiSense timings (current sense mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Multisense timings (chip temperature and VCC sense mode) . . . . . . . . . . . . . . . . . . . . . . 19 TDSTKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) . . . . . . . . . . . 21 Latch functionality - behavior in hard short circuit condition . . . . . . . . . . . . . . . . . . . . . . . . 21 Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) 22 Standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Standby state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 IGND(ON) vs. Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Logic input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Logic input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 High level logic input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Low level logic input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Logic Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FaultRST Input clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 On-state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 On-state resistance vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Won vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Woff vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ILIMH vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 OFF-state open-load voltage detection threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Vsense clamp vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Vsenseh vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Multisense and diagnostic - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Multisense block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Analogue HSD - open-load detection in off-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Open-load / short to VCC condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 GND voltage shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . . . . . . . . 38 PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) . . . . . . . . . . . . . . . . . . . . 38 Rthj-amb vs PCB copper area in open box free air conditions . . . . . . . . . . . . . . . . . . . . . . . 39 PowerSSO-16 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 39 Thermal fitting model for PowerSSO-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PowerSSO-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DocID022509 Rev 9 5/46 5 Block diagram and pin description 1 VN7010AJ-E Block diagram and pin description Figure 1. Block diagram 9&& ,QWHUQDOVXSSO\ 9&&*1' &ODPS 8QGHUYROWDJH VKXWGRZQ #ONTROL 'LDJQRVWLF 9&&287 &ODPS )DXOW567 ,1387 *DWH'ULYHU 6(/ 7 9&& 921 /LPLWDWLRQ 6(/ &XUUHQW /LPLWDWLRQ 08; 6(Q 0XOWLVHQVH 3RZHU/LPLWDWLRQ 2YHUWHPSHUDWXUH 7 6KRUWWR9&& 2SHQ/RDGLQ2)) &XUUHQW 6HQVH )DXOW 96(16(+ *1' 287387 *$3*&)7 Table 1. Pin functions Name VCC OUTPUT GND 6/46 Function Battery connection. Power outputs. All the pins must be connected together. Ground connection. Must be reverse battery protected by an external diode / resistor network. INPUT Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs. It controls output switch state. MultiSense Multiplexed analog sense output pin; delivers a current proportional to the selected diagnostic: load current, supply voltage or chip temperature. SEn Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the MultiSense diagnostic pin. SEL0,1 Active high compatible with 3 V and 5 V CMOS outputs pin; they address the MultiSense multiplexer. FaultRST Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in case of fault; If kept low, sets the outputs in auto-restart mode. DocID022509 Rev 9 VN7010AJ-E Block diagram and pin description Figure 2. Configuration diagram (top view) Pow erSSO -16 INPUT Fau ltRS T S En G ND SEL0 SEL1 Mul tiS ense N.C. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 OUT PUT OUT PUT OUT PUT OUT PUT OUT PUT OUT PUT OUT PUT OUT PUT TAB = V CC GAPGCFT00329 Note: Pins 9, 10, 11 and 12 are internally connected; Pins 13, 14, 15 and 16 are internally connected; All output pins must be connected together on PCB Table 2. Suggested connections for unused and not connected pins SEn, SELx, Connection / pin MultiSense N.C. Output Input Floating Not allowed X(1) X X X To ground Through 1 k resistor X Not allowed Through 15 k resistor Through 15 k resistor FaultRST 1. X: do not care. DocID022509 Rev 9 7/46 45 Electrical specification 2 VN7010AJ-E Electrical specification Figure 3. Current and voltage conventions ,6 9&& ,287 )DXOW567 ,6(Q 287387 96(Q 9287 ,6(16( 6(Q ,6(/ 6(/ 96(/ 9)5 9&& 9)Q ,)5 0XOWL6HQVH 96(16( ,,1 6 ,1 ,1387 ,*1' *$3*&)7 Note: VF = VOUT - VCC during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 3 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Table 3. Absolute maximum ratings Symbol Value VCC DC supply voltage 38 -VCC Reverse DC supply voltage 0.3 VCCPK Maximum transient supply voltage (ISO 16750-2:2010 Test B clamped to 40V; RL = 4 ) 40 VCCJS Maximum jump start voltage for single pulse short circuit protection 28 -IGND DC reverse ground pin current 200 IOUT OUTPUT DC output current Internally limited -IOUT Reverse DC output current 35 IIN 8/46 Parameter Unit V mA A INPUT DC input current ISEn SEn DC input current ISEL SEL0,1 DC input current IFR FaultRST DC input current VFR FaultRST DC input voltage DocID022509 Rev 9 -1 to 10 mA 7.5 V VN7010AJ-E Electrical specification Table 3. Absolute maximum ratings (continued) Symbol Value Unit MultiSense pin DC output current (VGND = VCC and VSENSE < 0 V) 10 MultiSense pin DC output current in reverse (VCC < 0V) -20 EMAX Maximum switching energy (single pulse) (TDEMAG = 0.4 ms; Tjstart = 150 C) 168 mJ VESD Electrostatic discharge (JEDEC 22A-114F) - INPUT - MultiSense - SEn, SEL0,1, FaultRST - OUTPUT - VCC 4000 2000 4000 4000 4000 V V V V V VESD Charge device model (CDM-AEC-Q100-011) 750 V ISENSE Tj Tstg 2.2 Parameter mA Junction operating temperature -40 to 150 Storage temperature -55 to 150 C Thermal data Table 4. Thermal data Symbol Parameter Typ. value 51-8)(1) Rthj-board Thermal resistance junction-board (JEDEC JESD 51-5 / Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-5)(2) Rthj-amb 51-7)(1) Thermal resistance junction-ambient (JEDEC JESD Unit 3.9 55 C/W 21.2 1. Device mounted on four-layers 2s2p PCB. 2. Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace. DocID022509 Rev 9 9/46 45 Electrical specification 2.3 VN7010AJ-E Main electrical characteristics 7 V < VCC < 18 V; -40 C < Tj < 150 C, unless otherwise specified. All typical values refer to VCC = 13 V; Tj = 25C, unless otherwise specified. Table 5. Power section Symbol Parameter VCC Operating supply voltage VUSD Undervoltage shutdown Test conditions Min. Typ. Max. Unit 4 13 28 4 V Undervoltage VUSDReset shutdown reset VUSDhyst 5 Undervoltage shutdown hysteresis 0.3 IOUT = 5 A; Tj = 25 C RON Vclamp ISTBY On-state resistance Clamp voltage Supply current in standby at VCC = 13 V(1) IOUT = 5 A; Tj = 150 C 20 IOUT = 5 A; VCC = 4 V; Tj = 25 C 15 IS = 20 mA; Tj = -40C 38 IS = 20 mA; 25C < Tj < 150C 41 52 A VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V VSEL0,1 = 0 V; Tj = 85 C (2) 0.5 A VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V VSEL0,1 = 0 V; Tj = 125 C 3 A 300 550 s 3 5 mA 6 mA VCC = 13 V; VIN = 5 V; VSEn = VFR = VSEL0,1 = 0 V; IOUT = 0 A IS(ON) Supply current VCC = 13 V; VSEn = VFR = VSEL0,1 = 0 V; VIN = 5 V; IOUT = 0 A IGND(ON) Control stage current VCC = 13 V; VSEn = 5 V; consumption in ON VFR = VSEL0,1 = 0 V; VIN = 5 V; state. All channels IOUT = 5 A active. IL(off) VIN = VOUT = 0 V; VCC = 13 V; Tj = 25 C Off-state output current at VCC = 13 V V = V IN OUT = 0 V; VCC = 13 V; Tj = 125 C IOUT = -5 A; Tj = 150 C 1. PowerMOS leakage included. 2. Parameter specified by design; not subject to production test. 10/46 V 46 0.5 Standby mode blanking time Output - VCC diode voltage m VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V VSEL0,1 = 0 V; Tj = 25 C tD_STBY VF 10 DocID022509 Rev 9 60 0 0.01 0.5 A 0 3 0.7 V VN7010AJ-E Electrical specification Table 6. Switching (VCC = 13 V; -40C < Tj < 150C, unless otherwise specified) Symbol Parameter td(on)(1) Turn-on delay time at Tj = 25C (1) Turn-off delay time at Tj = 25C td(off) Test conditions RL = 2.6 (dVOUT/dt)on(1) Turn-on voltage slope at Tj = 25C (dVOUT/dt)off(1) Turn-off voltage slope at Tj = 25C RL = 2.6 Min. Typ. Max. 10 70 120 10 40 100 0.1 0.2 0.7 0.1 0.3 0.7 Unit s V/s WON Switching energy losses at turnon (twon) RL = 2.6 -- 0.9 1.2(2) mJ WOFF Switching energy losses at turnoff (twoff) RL = 2.6 -- 0.6 0.8(2) mJ Differential Pulse skew (tPHL tPLH) RL = 2.6 -90 -40 10 s Max. Unit 0.9 V tSKEW(1) 1. See Figure 6: Switching times and Pulse skew. 2. Parameter guaranteed by design and characterization; not subject to production test. Table 7. Logic Inputs (7 V < VCC < 28 V; -40C < Tj < 150C) Symbol Parameter Test conditions Min. Typ. INPUT characteristics VIL Input low level voltage IIL Low level input current VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage VICL Input clamp voltage VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA A V 5.3 7.2 V IIN = -1 mA -0.7 FaultRST characteristics VFRL Input low level voltage IFRL Low level input current VFRH Input high level voltage IFRH High level input current VFR(hyst) Input hysteresis voltage VFRCL Input clamp voltage 0.9 VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA V A V 5.3 7.5 V IIN = -1 mA -0.7 SEL0,1 characteristics (7 V < VCC < 18 V) VSELL Input low level voltage ISELL Low level input current VSELH Input high level voltage 0.9 VIN = 0.9 V DocID022509 Rev 9 V 1 A 2.1 V 11/46 45 Electrical specification VN7010AJ-E Table 7. Logic Inputs (7 V < VCC < 28 V; -40C < Tj < 150C) (continued) Symbol Parameter ISELH High level input current VSEL(hyst) Input hysteresis voltage VSELCL Test conditions Min. Typ. VIN = 2.1 V Max. Unit 10 A 0.2 IIN = 1 mA Input clamp voltage V 5.3 7.2 V IIN = -1 mA -0.7 SEn characteristics (7 V < VCC < 18 V) VSEnL Input low level voltage ISEnL Low level input current VSEnH Input high level voltage ISEnH High level input current VSEn(hyst) Input hysteresis voltage VSEnCL 0.9 VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage V A V 5.3 7.2 V IIN = -1 mA -0.7 Table 8. Protections (7 V < VCC < 18 V; -40C < Tj < 150C) Symbol Parameter Test conditions ILIMH DC short circuit current ILIML Short circuit current during thermal cycling TTSD Shutdown temperature VCC = 13 V 4 V < VCC < 18 TR Reset temperature(1) TRS Thermal reset of fault diagnostic indication VFR = 0 V; VSEn = 5 V; TJ_SD Dynamic temperature Tj = -40 C; VCC = 13 V Fault reset time for output unlatch(1) VFR = 5 V to 0 V; VSEn = 5 V; VIN = 5 V; VSEL0 = 0 V; VSEL1 = 0 V IOUT = 2 A; L = 6 mH; Turn-off output voltage Tj = -40 C clamp I = 2 A; L = 6 mH; OUT Output voltage drop limitation 65 91 130 130 A 30 150 175 TRS + 1 TRS + 7 200 C 135 IOUT = 0.2 A 60 3 10 DocID022509 Rev 9 K 20 s VCC - 38 V VCC - 41 VCC - 46 VCC - 52 V 20 mV 1. Parameter guaranteed by design and characterization; not subject to production test. 12/46 Unit 7 Tj = 25 C to 150 C VON Max. VCC = 13 V; TR < Tj < TTSD Thermal hysteresis (TTSD - TR)(1) VDEMAG Typ. V(1) THYST tLATCH_RST Min. VN7010AJ-E Electrical specification Table 9. MultiSense (7 V < VCC < 18 V; -40C < Tj < 150C) Symbol Parameter Test conditions Min. MultiSense clamp voltage VSEn = 0 V; ISENSE = 1 mA -17 VSENSE_CL VSEn = 0 V; ISENSE = -1 mA Typ. Max. Unit -12 V 7 V Current Sense characteristics K0 dK0/K0(1)(2) K1 dK1/K1(1)(2) K2 dK2/K2(1)(2) K3 dK3/K3(1)(2) IOUT = 0.9 A; VSENSE = 0.5 V; VSEn = 5 V IOUT/ISENSE Current sense ratio IOUT = 0.9 A; VSENSE = 0.5 V; drift VSEn = 5 V IOUT = 1.5 A; VSENSE = 4 V; VSEn = 5 V IOUT/ISENSE Current sense ratio IOUT = 1.5 A; VSENSE = 4 V; drift VSEn = 5 V IOUT = 6 A; VSENSE = 4 V; VSEn = 5 V IOUT/ISENSE Current sense ratio IOUT = 6 A; VSENSE = 4 V; drift VSEn = 5 V IOUT = 18 A; VSENSE = 4 V; VSEn = 5 V IOUT/ISENSE = 18 A; VSENSE = 4 V; I Current sense ratio OUT VSEn = 5 V; drift Tj = -40 C to 150 C -20 3530 20 4950 -15 3840 4720 0.5 -0.5 0.5 MultiSense enabled: VSEn = 5 V; Channel ON; IOUT = 0 A; Diagnostic selected; VIN = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A; 0 2 MultiSense enabled: VSEn = 5 V; Channel OFF; Diagnostic selected: VIN = 0 V; VSEL0 = 0 V; VSEL1 = 0 V; 0 2 Output Voltage for MultiSense shutdown VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; RSENSE = 2.7 k; IOUT = 5 A VSENSE_SAT Multisense saturation voltage VCC = 7 V; RSENSE = 2.7 K; VSEn = 5 V; VIN = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 18 A; Tj = 150C DocID022509 Rev 9 5 5 % 5140 0 VOUT_MSD(1) % 5640 +10 4710 % 6560 15 -10 4260 7450 5 MultiSense disabled: -1 V < VSENSE < 5 V(1) MultiSense leakage current 5210 -5 MultiSense disabled: VSEn = 0 V; ISENSE0 3190 % A V V 13/46 45 Electrical specification VN7010AJ-E Table 9. MultiSense (7 V < VCC < 18 V; -40C < Tj < 150C) (continued) Symbol ISENSE_SAT(1) IOUT_SAT(1) Parameter Test conditions Min. Typ. Max. Unit CS saturation current VCC = 7 V; VSENSE = 4 V; VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; Tj = 150C 4 mA Output saturation current VCC = 7 V; VSENSE = 4 V; VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; Tj = 150C 24 A OFF-state openVIN = 0 V; VSEn = 5 V; load voltage = 0 V; VSEL1 = 0 V; V detection threshold SEL0 2 OFF-state diagnostic VOL IL(off2) OFF-state output sink current VIN = 0 V; VOUT = VOL; Tj = -40C to 125C -100 tDSTKON OFF-state diagnostic delay time from falling edge of INPUT (see Figure 9) VIN = 5 V to 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A; VOUT = 4 V 100 tD_OL_V Settling time for valid OFF-state VIN = 0 V; VFR = 0 V; open load VSEL0 = 0 V; VSEL1 = 0 V; diagnostic VOUT = 4 V; VSEn = 0 V to 5 V indication from rising edge of SEn tD_VOL OFF-state diagnostic delay time from rising edge of VOUT VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; VOUT = 0 V to 4 V 3 4 V -15 A 700 s 60 s 5 30 s 350 Chip temperature analog feedback VSENSE_TC dVSENSE_TC/dT Transfer function 14/46 MultiSense output voltage proportional to chip temperature Temperature coefficient VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN = 0 V; RSENSE = 1 K; Tj = -40 C 2.325 2.41 2.495 V VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN = 0 V; RSENSE = 1 K; Tj = 25 C 1.985 2.07 2.155 V VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN = 0 V; RSENSE = 1 K; Tj = 125 C 1.435 1.52 1.605 V Tj = -40 C to 150 C -5.5 mV/K VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T T0) DocID022509 Rev 9 VN7010AJ-E Electrical specification Table 9. MultiSense (7 V < VCC < 18 V; -40C < Tj < 150C) (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit 3.16 3.23 3.3 V 6.6 V 30 mA 60 s 5 20 s 100 250 s 100 s 250 s VCC supply voltage analog feedback VSENSE_VCC MultiSense output VCC = 13 V; VSEn = 5 V; voltage VSEL0 = 5 V; VSEL1 = 5 V; proportional to VCC VIN = 0 V; RSENSE = 1 K supply voltage Transfer function(3) VSENSE_VCC = VCC / 4 Fault diagnostic feedback (see Table 10) VSENSEH MultiSense output voltage in fault condition VCC = 13 V; VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A; VOUT = 4 V; RSENSE = 1 k 5 ISENSEH MultiSense output current in fault condition VCC = 13 V; VSENSE = 5 V 7 20 MultiSense timings (current sense mode - see Figure 7) tDSENSE1H Current sense VIN = 5 V; VSEn = 0 V to 5 V; settling time from RSENSE = 1 k; RL = 2.6 rising edge of SEn tDSENSE1L Current sense disable delay time VIN = 5 V; VSEn = 5 V to 0 V; from falling edge of RSENSE = 1 k; RL = 2.6 SEn tDSENSE2H Current sense settling time from rising edge of INPUT VIN = 0 V to 5 V; VSEn = 5 V; RSENSE = 1 k; RL = 2.6 Current sense settling time from rising edge of IOUT (dynamic response to a step change of IOUT) VIN = 5 V; VSEn = 5 V; RSENSE = 1 k; ISENSE = 90 % of ISENSEMAX; RL = 2.6 tDSENSE2H tDSENSE2L Current sense turn-off delay time VIN = 5 V to 0 V; VSEn = 5 V; from falling edge of RSENSE = 1 k; RL = 2.6 INPUT 50 MultiSense timings (chip temperature sense mode - see Figure 8) tDSENSE3H VSENSE_TC settling VSEn = 0 V to 5 V; time from rising VSEL0 = 0 V; VSEL1 = 5 V; RSENSE = 1 k edge of SEn 60 s tDSENSE3L VSENSE_TC disable VSEn = 5 V to 0 V; delay time from VSEL0 = 0 V; VSEL1 = 5 V; falling edge of SEn RSENSE = 1 k 20 s DocID022509 Rev 9 15/46 45 Electrical specification VN7010AJ-E Table 9. MultiSense (7 V < VCC < 18 V; -40C < Tj < 150C) (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit MultiSense timings (VCC voltage sense mode - see Figure 8) tDSENSE4H VSEn = 0 V to 5 V; VSENSE_VCC settling time from VSEL0 = 5 V; VSEL1 = 5 V; rising edge of SEn RSENSE = 1 k 60 s tDSENSE4L VSENSE_VCC VSEn = 5 V to 0 V; disable delay time VSEL0 = 5 V; VSEL1 = 5 V; from falling edge of RSENSE = 1 k SEn 20 s MultiSense timings (Multiplexer transition times)(4) tD_CStoTC MultiSense transition delay from current sense to TC sense VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V to 5 V; IOUT = 2.5 A; RSENSE = 1 k 60 s tD_TCtoCS MultiSense transition delay from TC sense to current sense VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V to 0 V; IOUT = 2.5 A; RSENSE = 1 k 20 s tD_CStoVCC MultiSense transition delay from current sense to VCC sense VIN = 5 V; VSEn = 5 V; VSEn = 5 V; VSEL0 = 5 V; VSEL1 = 0 V to 5 V; IOUT = 2.5 A; RSENSE = 1 k 60 s tD_VCCtoCS MultiSense transition delay from VCC sense to current sense VIN = 5 V; VSEn = 5 V; VSEL0 = 5 V; VSEL1 = 5 V to 0 V; IOUT = 2.5 A; RSENSE = 1 k 20 s tD_TCtoVCC MultiSense transition delay from TC sense to VCC sense VCC = 13 V; Tj = 125 C; VSEn = 5 V; VSEL0 = 0 V to 5 V; VSEL1 = 5 V; RSENSE = 1 k 20 s tD_VCCtoTC MultiSense transition delay from VCC sense to TC sense VCC = 13 V; Tj = 125 C; VSEn = 5 V; VSEL0 = 5 V to 0 V; VSEL1 = 5 V; RSENSE = 1 k 20 s 1. Parameter specified by design; not subject to production test. 2. All values refer to VCC = 13 V; Tj = 25C, unless otherwise specified. 3. VCC sensing and TC are referred to GND potential. 4. Transition delay are measured up to +/- 10% of final conditions. 16/46 DocID022509 Rev 9 VN7010AJ-E Electrical specification <Z Figure 4. IOUT/ISENSE versus IOUT D D d /Khd ("1($'5 Figure 5. Current sense accuracy versus IOUT Z Z /Khd ("1($'5 DocID022509 Rev 9 17/46 45 Electrical specification VN7010AJ-E Figure 6. Switching times and Pulse skew WZRQ 9287 WZRII 9FF 9FF 21 2)) G9287GW G9287GW 9FF W ,1387 WG RII WG RQ WS/+ WS+/ W ("1($'5 Figure 7. MultiSense timings (current sense mode) ,1 +LJK 6(Q /RZ +LJK 6(/ /RZ +LJK 6(/ /RZ ,287 &855(176(16( W'6(16(+ W'6(16(/ W'6(16(+ W'6(16(/ ("1($'5 18/46 DocID022509 Rev 9 VN7010AJ-E Electrical specification Figure 8. Multisense timings (chip temperature and VCC sense mode) +LJK 6(Q /RZ +LJK 6(/ /RZ +LJK 6(/ /RZ 9&& 96(16( 96(16(B9&& 96(16( 96(16(B7& 6(16( W'6(16(+ W'6(16(/ 9&&92/7$*(6(16(02'( W'6(16(+ W'6(16(/ &+,37(03(5$785(6(16(02'( ("1($'5 Figure 9. TDSTKON 9,1387 9287 9287!92/ 0XOWL6HQVH 7'67.21 DocID022509 Rev 9 *$3*&)7 19/46 45 Electrical specification VN7010AJ-E Table 10. Truth table Mode Stand by Conditions INX FR SEn All logic inputs low L L L L X L H L H H H H L X L H L H H VCC < VUSD (falling) X X X Short to VCC L X Open-load L X Refer to Table 11 Inductive loads turn-off L X Nominal load connected; Tj < 150 C Normal Overload or short to GND causing: Tj > TTSD or Tj > Tj_SD Overload Undervoltage OFF-state diagnostics Negative output voltage SELX OUTX MultiSense L Refer to Table 11 Refer to Table 11 L Hi-Z Refer to Table 11 Refer to Table 11 Low quiescent current consumption Outputs configured for auto-restart Outputs configured for Latch-off Refer to Table 11 H L X Comments Output cycles with temperature hysteresis Output latches-off L L Hi-Z Hi-Z H Refer to Table 11 H <0V Re-start when VCC > VUSD + VUSDhyst (rising) External pull-up Refer to Table 11 Table 11. MultiSense multiplexer addressing MultiSense output SEn SEL1 SEL0 MUX channel Nomal mode L X X H L L H L H Output diagnostic H H L TCHIP Sense H H H VCC Sense Overload OFF-state diag.(1) Negative output VSENSE = VSENSEH Hi-Z Hi-Z ISENSE = 1/K * IOUT VSENSE = VSENSEH VSENSE = VSENSE_TC VSENSE = VSENSE_VCC 1. In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is low, Multisense pin delivers feedback according to OFF-State diagnostic. Example 1: FR = 1; IN = 0; OUT = L (latched); MUX channel = channel 0 diagnostic; Mutisense = 0 Example 2: FR = 1; IN = 0; OUT = latched, VOUT > VOL; MUX channel = channel 0 diagnostic; Mutisense = VSENSEH 20/46 DocID022509 Rev 9 VN7010AJ-E 2.4 Electrical specification Waveforms Figure 10. Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) Figure 11. Latch functionality - behavior in hard short circuit condition DocID022509 Rev 9 21/46 45 Electrical specification VN7010AJ-E Figure 12. Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) Figure 13. Standby mode activation 22/46 DocID022509 Rev 9 VN7010AJ-E Electrical specification Figure 14. Standby state diagram 1RUPDO2SHUDWLRQ W!W 'B67%< ,1[ /RZ $1' )DXOW567 /RZ $1' 6(Q /RZ $1' 6(/[ /RZ ,1[ +LJK 25 )DXOW567 +LJK 25 6(Q +LJK 25 6(/[ +LJK 6WDQGE\0RGH *$3*&)7 DocID022509 Rev 9 23/46 45 Electrical specification 2.5 VN7010AJ-E Electrical characteristics curves Figure 15. OFF-state output current Figure 16. Standby current ,67%<>$@ ,ORII>Q$@ 9FF 9 2II6WDWH 9FF 9 9LQ 9RXW 7>&@ 7>&@ ("1($'5 ("1($'5 Figure 17. IGND(ON) vs. Iout Figure 18. Logic input high level voltage 9L+9)5+96(/+96(Q+>9@ ,*1' 21 >P$@ 9FF 9 ,RXW $ 7>&@ 7>&@ ("1($'5 ("1($'5 Figure 19. Logic input low level voltage Figure 20. High level logic input current ,L+,)5+,6(/+,6(Q+>$@ 9LO/9)5/96(//96(Q/>9@ ("1($'5 24/46 7>&@ 7>&@ DocID022509 Rev 9 ("1($'5 VN7010AJ-E Electrical specification Figure 21. Low level logic input current Figure 22. Logic Input hysteresis voltage 9L K\VW 9)5 K\VW 96(/ K\VW 96(Q K\VW >9@ ,L/,)5/,6(//,6(Q/>$@ 7>&@ 7>&@ ("1($'5 ("1($'5 Figure 23. FaultRST Input clamp voltage Figure 24. Undervoltage shutdown 986'>9@ 9)5&/>9@ ,LQ P$ ,LQ P$ 7>&@ 7>&@ ("1($'5 Figure 25. On-state resistance vs. Tcase ("1($'5 Figure 26. On-state resistance vs. VCC 5RQ>P2KP@ 5RQ>P2KP@ 7 & ,RXW $ 9FF 9 7 & 7 & 7 & 9FF>9@ 7>&@ ("1($'5 DocID022509 Rev 9 ("1($'5 25/46 45 Electrical specification VN7010AJ-E Figure 27. Turn-on voltage slope Figure 28. Turn-off voltage slope G9RXWGW 2II>9V@ G9RXWGW 2Q>9V@ 9FF 9 5O 9FF 9 5O 7>&@ 7>&@ ("1($'5 ("1($'5 Figure 30. Woff vs. Tcase Figure 29. Won vs. Tcase :RII>P-@ :RQ>P-@ 7>&@ 7>&@ ("1($'5 Figure 31. ILIMH vs. Tcase ("1($'5 Figure 32. OFF-state open-load voltage detection threshold 92/>9@ ,OLPK>$@ 9FF 9 7>&@ 7>&@ ("1($'5 26/46 DocID022509 Rev 9 ("1($'5 VN7010AJ-E Electrical specification Figure 33. Vsense clamp vs. Tcase Figure 34. Vsenseh vs. Tcase 96(16(+>9@ 96(16(B&/>9@ ,LQ P$ ,LQ P$ 7>&@ 7>&@ ("1($'5 DocID022509 Rev 9 ("1($'5 27/46 45 Protections VN7010AJ-E 3 Protections 3.1 Power limitation The basic working principle of this protection consists of an indirect measurement of the junction temperature swing Tj through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as Tj exceeds the safety level of Tj_SD. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off (FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermo-mechanical fatigue. 3.2 Thermal shutdown In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (see Table 8, FaultRST = Low) or remains off (FaultRST = High). 3.3 Current limitation The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, ILIMH, by operating the output power MOSFET in the active region. 3.4 Negative voltage clamp In case the device drives inductive load, the output voltage reaches negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG (see Table 8), allowing the inductor energy to be dissipated without damaging the device. 28/46 DocID022509 Rev 9 VN7010AJ-E 4 Application information Application information Figure 35. Application diagram +5V VDD OUT V CC Rprot OUT FaultRST INPUT Rprot OUT Logic OUT Rprot SEn Rprot SEL Dld OUTPUT Rprot ADC in Multisense Current mirror GND Cext Rsense OUT R GND D GND GND GND GND GND GND GND 4.1 GND protection network against reverse battery Figure 36. Simplified internal structure 9 9FF 5SURW 5SURW ,1387 6(Q 0&8 'OG 5SURW )DXOW567 287387 5SURW 0XOWLVHQVH *1' 5VHQVH ' *1' 5 *1' *1' *$3*&)7 DocID022509 Rev 9 29/46 45 Application information 4.1.1 VN7010AJ-E Diode (DGND) in the ground line A resistor (typ. RGND = 4.7 k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network. 4.2 Immunity against transient electrical disturbances The immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010. The related function performance status classification is shown in Table 12. Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device only, without components and accessed through VCC and GND terminals. Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: "The function does not perform as designed during the test but returns automatically to normal operation after the test". Table 12. ISO 7637-2 - electrical transient conduction along supply line Test Pulse 2011(E) Test pulse severity level with Status II functional performance status Minimum number of pulses or test time Burst cycle / pulse repetition time Pulse duration and pulse generator internal impedance Level US(1) 1 III -112V 500 pulses 0,5 s 2a III +55V 500 pulses 0,2 s 5s 50s, 2 3a IV -220V 1h 90 ms 100 ms 0.1s, 50 3b IV +150V 1h 90 ms 100 ms 0.1s, 50 4(2) IV -7V 1 pulse min max 2ms, 10 100ms, 0.01 Load dump according to ISO 16750-2:2010 Test B(3) 40V 5 pulse 1 min 400ms, 2 1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6. 2. Test pulse from ISO 7637-2:2004(E). 3. 30/46 With 40 V external suppressor referred to ground (-40C < Tj < 150C). DocID022509 Rev 9 VN7010AJ-E 4.3 Application information MCU I/Os protection If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs. The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. Equation 1 VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak = -150 V; Ilatchup 20mA; VOHC 4.5V 7.5 k Rprot 140 k. Recommended values: Rprot = 15 k 4.4 Multisense - analog current sense Diagnostic information on device and load status are provided by an analog output pin (Multisense) delivering the following signals: * Current monitor: current mirror of channel output current * VCC monitor: voltage propotional to VCC * TCASE: voltage propotional to chip temperature Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and SEn pins, according to the address map in Table 11. DocID022509 Rev 9 31/46 45 Application information VN7010AJ-E VCC Figure 37. Multisense and diagnostic - block diagram Internal Supply VCC - GND Clamp Undervoltage shut-down Control & Diagnostic VCC - OUT Clamp FaultRST INPUT Gate Driver VCC T SEL1 SEL0 VON Limitation VCC SEn Current Limitation MONITOR MultiSense MUX ISENSE RPROT TEMP Fault Diagnostic Power Limitation Overtemperature Temp MONITOR Short to VCC Open-Load in OFF To uC ADC K factor RSENSE Current Sense CURRENT MONITOR Fault VSENSEH GND 32/46 DocID022509 Rev 9 IOUT OUT VN7010AJ-E 4.4.1 Application information Principle of Multisense signal generation Figure 38. Multisense block diagram 9FF ).054 6HQVH026 0DLQ026 287 &XUUHQWVHQVH 9EDW0RQLWRU 0XOWLVHQVH6ZLWFK%ORFN 7HPSHUDWXUHPRQLWRU )DXOW 08/7,6(16( 7RX&$'& 53527 56(16( *$3*&)7 Current monitor When current mode is selected in the Multisense, this output is capable to provide: * Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to known ratio named K * Diagnostics flag in fault conditions delivering fixed voltage VSENSEH The current delivered by the current sense circuit, ISENSE, can be easily converted to a voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection. Normal operation (channel ON, no fault, SEn active) While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using simple equations Current provided by Multisense output: ISENSE = IOUT/K Voltage on RSENSE: VSENSE = RSENSE . ISENSE = RSENSE . IOUT/K DocID022509 Rev 9 33/46 45 Application information VN7010AJ-E Where : * VSENSE is voltage measurable on RSENSE resistor * ISENSE is current provided from Multisense pin in current output mode * IOUT is current flowing through output * K factor represent the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying ratio between IOUT and ISENSE. Failure flag indication In case of power limitation/overtemperature, the fault is indicated by the Multisense pin which is switched to a "current limited" voltage source, VSENSEH (see Table 9). In any case, the current sourced by the Multisense in this condition is limited to ISENSEH (see Table 9). The typical behavior in case of overload or hard short circuit is shown in Figure 10, Figure 11 and Figure 12. Figure 39. Analogue HSD - open-load detection in off-state 9 9EDW 9EDW Q) 9 Q) 5SXOOXS *1' 0LFURFRQWUROOHU *1' 9 && 9'' )DXOW567 287 N ,1387 ([WHUQDO 3XOO 8S VZLWFK 287 /RJLF N 6(Q 287 6(/ N 287387 287387 0XOWLVHQVH 287 &X UUHQWPLUURU N *1' $'&LQ N 5VHQVH 5 *1 ' N '*1 ' Q) 9 287 N &(;7 *1' *1' 34/46 *1' *1' DocID022509 Rev 9 *1' *1' *$3*&)7 VN7010AJ-E Application information Figure 40. Open-load / short to VCC condition 9,1 96(16( 3XOOXSFRQQHFWHG 96(16(+ 2SHQORDG 96(16( 96(16( 3XOOXS GLVFRQQHFWHG W'67.21 6KRUWWR9&& 96(16(+ *$3*&)7 Table 13. Multisense pin levels in off-state Condition Output VOUT > VOL Open-load VOUT < VOL 4.4.2 Short to VCC VOUT > VOL Nominal VOUT < VOL Multisense SEn Hi-Z L VSENSEH H Hi-Z L 0 H Hi-Z L VSENSEH H Hi-Z L 0 H TCASE and VCC monitor In this case, MultiSense output operates in voltage mode and output level is referred to device GND. Care must be taken in case a GND network protection is used, because of a voltage shift is generated between device GND and the microcontroller input GND reference. Figure 41 shows link between VMEASURED and real VSENSE signal. DocID022509 Rev 9 35/46 45 Application information VN7010AJ-E Figure 41. GND voltage shift 9%$7 Q)9 0XOWLVHQVHYROWDJHPRGH 96(16(+ 9&&PRQLWRU 7&$6(PRQLWRU )DXOW567 9&& ,1 6(Q 287 6(/ 6(/ 53527 90($685(' 56(16( 93527 96(16( 0XOWLVHQVH 7RX&$'& *1' 53527 N '*1' '!0'#&4 VCC monitor Battery monitoring channel provides VSENSE = VCC / 4. Case temperature monitor Case temperature monitor is capable to provide information about actual device temperature. Since diode is used for temperature sensing, following equation describe link between temperature and output VSENSE level: VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0) where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40oC to +150oC). 4.4.3 Short to VCC and OFF-state open-load detection Short to VCC A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature of the short circuit. OFF-state open-load with external circuitry Detection of an open-load in off mode requires an external pull-up resistor RPU connecting the output to a positive supply voltage VPU. It is preferable VPU to be switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. RPU must be selected in order to ensure VOUT > VOLmax in accordance with to following equation: Equation 2 V PU - 4 R PU < ----------------------------------------I L ( off2 )min @ 4V 36/46 DocID022509 Rev 9 VN7010AJ-E 4.5 Application information Maximum demagnetization energy (VCC = 16 V) Figure 42. Maximum turn off current versus inductance 91$- 0D[LPXPWXUQRIIFXUUHQWYHUVXVLQGXFWDQFH , $ 91$-6LQJOH3XOVH 5HSHWLWLYHSXOVH7MVWDUW & 5HSHWLWLYHSXOVH7MVWDUW & / P+ 91$- 0D[LPXPWXUQRII(QHUJ\YHUVXV7GHPDJ 91$-6LQJOH3XOVH 5HSHWLWLYHSXOVH7MVWDUW & (>P-@ 5HSHWLWLYHSXOVH7MVWDUW & 7GHPDJ>PV@ ("1($'5 Note: Values are generated with RL = 0 . In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. DocID022509 Rev 9 37/46 45 Package and PCB thermal data VN7010AJ-E 5 Package and PCB thermal data 5.1 PowerSSO-16 thermal data Figure 43. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) ("1($'5 Figure 44. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) 5PQ (/%QMBOF 7$$QMBOF #PUUPN ("1($'5 Table 14. PCB properties Dimension Board finish thickness 1.6 mm +/- 10% Board dimension 77 mm x 86 mm Board Material FR4 Copper thickness (top and bottom layers) 0.070 mm Copper thickness (inner layers) 0.035 mm Thermal vias separation 1.2 mm Thermal via diameter 0.3 mm +/- 0.08 mm Copper thickness on vias 0.025 mm Footprint dimension (top layer) 2.2 mm x 3.9 mm Heatsink copper area dimension (bottom layer) 38/46 Value DocID022509 Rev 9 Footprint, 2 cm2 or 8 cm2 VN7010AJ-E Package and PCB thermal data Figure 45. Rthj-amb vs PCB copper area in open box free air conditions 57+MDPE 57+MDPE ("1($'5 Figure 46. PowerSSO-16 thermal impedance junction ambient single pulse =7+ &: &X IRRWSULQW &X FP &X FP /D\HU 7LPH V *$3*&)7 Equation 3: pulse calculation formula Z TH = R TH + Z THtp ( 1 - ) where = tP/T DocID022509 Rev 9 39/46 45 Package and PCB thermal data VN7010AJ-E Figure 47. Thermal fitting model for PowerSSO-16 *$3*&)7 1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Table 15. Thermal parameters 40/46 Area/island (cm2) Footprint R1 (C/W) 0.15 R2 (C/W) 1.7 R3 (C/W) 2 8 4L 7 7 7 5 R4 (C/W) 16 6 6 4 R5 (C/W) 30 20 10 3 R6 (C/W) 26 20 18 7 C1 (W.s/C) 0.0015 C2 (W.s/C) 0.02 C3 (W.s/C) 0.1 C4 (W.s/C) 0.2 0.3 0.3 0.4 C5 (W.s/C) 0.4 1 1 4 C6 (W.s/C) 3 5 7 18 DocID022509 Rev 9 VN7010AJ-E Package information 6 Package information 6.1 ECOPACK(R) In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 6.2 PowerSSO-16 package information Figure 48. PowerSSO-16 package dimensions ("1($'5 DocID022509 Rev 9 41/46 45 Package information VN7010AJ-E Table 16. PowerSSO-16 mechanical data Millimeters Symbol Min. Typ. 0 1 0 2 5 15 3 5 15 8 A 1.70 A1 0.00 0.10 A2 1.10 1.60 b 0.20 0.30 b1 0.20 c 0.19 c1 0.19 D D1 0.25 0.28 0.25 0.20 0.23 4.90 BSC 3.60 4.20 e 0.50 BSC E 6.00 BSC E1 3.90 BSC E2 1.90 2.50 h 0.25 0.50 L 0.40 0.60 L1 1.00 REF N 16 R 0.07 R1 0.07 S 0.20 Tolerance of form and position 42/46 Max. aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.08 eee 0.10 fff 0.10 ggg 0.15 DocID022509 Rev 9 0.85 VN7010AJ-E 7 Order codes Order codes Table 17. Device summary Order codes Package PowerSSO-16 Tube Tape and reel VN7010AJ-E VN7010AJTR-E DocID022509 Rev 9 43/46 45 Revision history 8 VN7010AJ-E Revision history Table 18. Document revision history Date Revision 23-Nov-2011 1 Initial release 2 Updated Table 1: Pin functions Updated Figure 2: Configuration diagram (top view) Updated Table : Table 3: Absolute maximum ratings: - VCCJS: added row - VCCPK, ISENSE, VESD: updated parameter and value - EMAX, -IOUT: updated parameter Updated Table 4: Thermal data Table 5: Power section: - VUSDReset, IGDN(ON): added row - Vclamp, IGND(ON): updated test conditions and values - IS(ON): updated test conditions Updated Table 6: Switching (VCC = 13 V; -40C < Tj < 150C, unless otherwise specified) Table 8: Protections (7 V < VCC < 18 V; -40C < Tj < 150C): - ILIMH, TR: added note - tLATCH_RST: updated parameters Table 9: MultiSense (7 V < VCC < 18 V; -40C < Tj < 150C): - dK2/K2, VSENSE_CL, VOUT_MSD, tDSENSE1L, tDSENSE2H, tDSENSE2H, tDSENSE2L, tDSENSE3H, tDSENSE3L, tDSENSE4H, tDSENSE4L, tD_CStoTC, tD_TCtoCS, tD_CStoVCC, tD_VCCtoCS, tD_TCtoVCC, tD_VCCtoTC: updated test conditions - K0, dK0/K0, K1, dK1/K1, K2, K3, dK3/K3, ISENSE0, IL(off2), VSENSE_TC, VSENSEH, tDSENSE1H: updated test conditions and values - VSENSE_SAT, ISENSE_SAT, IOUT_SAT, tD_OL_V: added rows - VSENSE_VCC, ISENSEH: updated values Updated Table 11: MultiSense multiplexer addressing Updated Figure 6: Switching times and Pulse skew Removed Figure: Pulse skew Table 10: Truth table: - Overload: updated conditions Table 11: MultiSense multiplexer addressing: - added note Updated Section 2.4: Waveforms Added Chapter 3: Protections and Chapter 4: Application information 07-Dec-2012 44/46 Changes DocID022509 Rev 9 VN7010AJ-E Revision history Table 18. Document revision history (continued) Date Revision Changes 3 Table 3: Absolute maximum ratings: - VCCPK: updated parameter - -VSENSE: removed row - EMAX: updated parameter and value Table 4: Thermal data: - Rthj-board: updated value Table 5: Power section: - VF: updated test conditions Table 6: Switching (VCC = 13 V; -40C < Tj < 150C, unless otherwise specified): - WON, WOFF: updated values Table 9: MultiSense (7 V < VCC < 18 V; -40C < Tj < 150C): - K2, K3: updated values - dK3/K3: updated test conditions Removed Table: Electrical transient requirements (part 1/3), Table: Electrical transient requirements (part 2/3) and Table: Electrical transient requirements (part 3/3) Removed Section: Load dump protection Added Section 4.2: Immunity against transient electrical disturbances Updated Figure 39: Analogue HSD - open-load detection in off-state Updated Table 13: Multisense pin levels in off-state Updated Figure 41: GND voltage shift Added Section 4.5: Maximum demagnetization energy (VCC = 16 V) 03-Sep-2013 4 Table 6: Switching (VCC = 13 V; -40C < Tj < 150C, unless otherwise specified): - WON, WOFF: updated values Table 9: MultiSense (7 V < VCC < 18 V; -40C < Tj < 150C): - K0, K1, K2, K3: updated values Added Figure 4: IOUT/ISENSE versus IOUT and Figure 5: Current sense accuracy versus IOUT Added Section 2.5: Electrical characteristics curves Updated Section 6.2: PowerSSO-16 package information 18-Sep-2013 5 Updated disclaimer. 19-Sep-2013 6 Table 3: Absolute maximum ratings: - EMAX: updated parameter and value Updated Figure 42: Maximum turn off current versus inductance 13-Nov-2013 7 Updated Features list Table 4: Thermal data: - Rthj-amb: updated values 09-Jun-2014 8 Updated Section 6.2: PowerSSO-16 package information 08-Oct-2014 9 Updated Table 16: PowerSSO-16 mechanical data 26-Mar-2013 DocID022509 Rev 9 45/46 45 VN7010AJ-E IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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