This is information on a product in full production.
October 2014 DocID022509 Rev 9 1/46
VN7010AJ-E
High-side driver with MultiSense analog feedback
for automotive applications
Datasheet
-
production data
Features
•Automotive qualified
•General
– Single channel smart high side driver with
MultiSense analog feedback
– Very low standby current
– Compatible with 3 V and 5 V CMOS
outputs
•MultiSense diagnostic functions
– Multiplexed analog feedback of: load
current with high precision proportional
current mirror, V
CC
supply voltage and
T
CHIP
device temperature
– Overload and short to ground (power
limitation) indication
– Therm al sh utdow n indica tion
– OFF-state open-load detection
– Output short to V
CC
detection
– Sense enable/ disable
•Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Configurable latch-off on overtemperature
or power limitation with dedicated fault
reset pi n
– Loss of ground and loss of V
CC
– Reverse battery with external components
– Electros tatic disc har ge protecti on
Applications
•All types of Automotive resistive, inductive and
capacitive loads
•Specially intended for Automotive Headlamps
Description
The VN7010AJ-E is a single channel high-side
driver manufactured using ST proprietary
VIPower
®
technology and housed in
PowerSSO-16 package. The device is designed
to drive 12 V automotive grounded loads through
a 3 V and 5 V CMOS-compatible interface, and to
provide protection and diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown with configurable
latch-off.
A FaultRST pin unlatches the output in case of
fault or disables the latch-off functionality.
A dedicated multifunction multiplexed analog
output pin delivers sophisticated diagnostic
functions such as high precision proportional load
current sense, supply voltage feedback and chip
temperature sense, in addition to the detection of
overload and short circuit to ground, short to V
CC
and OFF-state open-load.
A sense enable pin allows OFF-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices.
Max transient supply voltage V
CC
40 V
Operati ng vol tage range V
CC
4 to 28 V
Typ. on-state resistance (per Ch) R
ON
10 mΩ
Current lim itation (typ) I
LIMH
91 A
Standby current (max) I
STBY
0.5 µA
www.st.com
Contents VN7010AJ-E
2/46 DocID022509 Rev 9
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 E lectrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Main electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3 P rotections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1 Power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3 Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4 Negati v e voltage c lamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 29
4.1.1 Diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2 Immunit y against transient electrical disturbances . . . . . . . . . . . . . . . . . . 30
4.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.4 Mult isense - analog current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.4.1 Principle of Multisense signal generation . . . . . . . . . . . . . . . . . . . . . . . 33
4.4.2 T
CASE
and V
CC
monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.4.3 Short to VCC and OFF-state open-load detection . . . . . . . . . . . . . . . . . 36
4.5 Maximum demagnetization energy (V
CC
= 16 V) . . . . . . . . . . . . . . . . . . . 37
5 P ackage and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1 PowerSSO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6 P ackage information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.1 ECOPACK
®
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.2 PowerSSO-16 package informat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DocID022509 Rev 9 3/46
VN7010AJ-E Contents
3
7 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
List of tables VN7010AJ-E
4/46 DocID022509 Rev 9
List of tables
Table 1. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. Switching (V
CC
= 13 V; -40°C < T
j
< 150°C, unless otherwise specified). . . . . . . . . . . . . . 11
Table 7. Logic Inputs (7 V < V
CC
<28V; -40°C<T
j
< 150°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 8. Protections (7 V < V
CC
< 18 V; -40°C < T
j
< 150°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 9. MultiSense (7 V < V
CC
< 18 V; -40°C < T
j
< 150°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 10. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. MultiSense multiplexer addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 12. ISO 7637-2 - electrical transient conduction along supply line . . . . . . . . . . . . . . . . . . . . . 30
Table 13. Multisense pin levels in off-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 14. PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 15. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16. PowerSSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 17. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
DocID022509 Rev 9 5/46
VN7010AJ-E List of figures
5
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. I
OUT
/I
SENSE
versus I
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. Current sense accuracy versus I
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. Switching times and Pulse skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. MultiSense timings (current sense mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Multisense timings (chip temperature and VCC sense mode) . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. T
DSTKON
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Latch functionality - behavior in hard short circuit condition (T
AMB
<< T
TSD
) . . . . . . . . . . . 21
Figure 11. Latch functionality - behavior in hard short circuit condition . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) 22
Figure 13. Standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14. Standby state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 15. OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 16. Standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17. I
GND(ON)
vs. I
out
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 18. Logic input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19. Logic input low level voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 20. High level logic input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 21. Low level logic input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 22. Logic Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 23. FaultRST Input clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 24. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 25. On-state resistance vs. T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 26. On-state resistance vs. V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 27. Turn-on voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 28. Turn-off voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 29. Won vs. T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 30. Woff vs. T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 31. I
LIMH
vs. T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 32. OFF-state open-load voltage detection threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 33. V
sense
clamp vs. T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 34. V
senseh
vs. T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 35. Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 36. Simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 37. Multisense and diagnostic – block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 38. Multisense block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 39. Analogue HSD – open-load detection in off-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 40. Open-load / short to VCC condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 41. GND voltage shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 42. Maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 43. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . . . . . . . . 38
Figure 44. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7). . . . . . . . . . . . . . . . . . . . 38
Figure 45. R
thj-amb
vs PCB copper area in open box free air conditions . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 46. PowerSSO-16 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 39
Figure 47. Thermal fitting model for PowerSSO-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 48. PowerSSO-16 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Block diagram and pin description VN7010AJ-E
6/46 DocID022509 Rev 9
1 Block diagram and pin description
Figure 1. Block diagram
Table 1. Pin functions
Name Function
V
CC
Battery connection.
OUTPUT Power outputs. All the pins must be connected together.
GND Ground connection. Must be reverse battery protected by an external
diode / resistor network.
INPUT Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V
CMOS outputs. It controls output switch state.
MultiSense Multi plex ed anal og sense output pin ; deliv ers a curre nt pr oportio nal to the
selected diagnostic: load current, supply voltage or chip temperature.
SEn Active h ig h c ompatib le w ith 3 V an d 5 V C MOS output s p in; it enables the
MultiSense diagnostic pin.
SEL
0,1
Active high compatible with 3 V and 5 V CMOS outputs pin; they address
the MultiSense multiplexer.
FaultRST Activ e low comp atible with 3 V and 5 V CMOS output s pin; it unlatc hes the
output in case of fault; If kept low, sets the outputs in auto-restart mode.
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DocID022509 Rev 9 7/46
VN7010AJ-E Block diagram and pin description
45
Figure 2. Configuration diagram (top view)
Note: Pins 9, 10, 11 and 12 are internally connected; Pins 13, 14, 15 and 16 are internally
connected; All output pins must be connected together on PCB
1
2
3
4
5
6
Mul tiS ense
Fau ltR S T OUT PUT
7
8
SEn
N.C.
16
15
14
13
12
11
OUT PUT
OUT PUT
OUT PUT
OUT PUT
10
9
OUT PUT
OUT PUT
OUT PUT
SEL0
SEL1
GND
IN PUT
TAB = V CC
Pow erSSO -16
GAPGCFT00329
Table 2. Suggested connections for unused and not connected pins
Connection / pin MultiSense N.C. Output Input SEn, SELx,
FaultRST
Floating Not allowed X
(1)
1. X: do not care.
XXX
To ground Through 1 kΩ
resistor XNot allowed
Through 15 kΩ
resistor Through 15 kΩ
resistor
Electrical specification VN7010AJ-E
8/46 DocID022509 Rev 9
2 Electrical specification
Fig ure 3. Current and voltage conventions
Note: V
F
= V
OUT
- V
CC
during reverse battery condition.
2.1 Absolute maximum ratings
S tressing the device above the rating listed in Table 3 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to the conditions in table below for extended periods may affect device reliability.
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Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC
DC supply voltage 38
V
-V
CC
Reverse DC supply voltage 0.3
V
CCPK
Maximum trans ien t su pply voltage (ISO 16750-2 : 201 0 Test B
clamped to 40V; R
L
=4Ω)40
V
CCJS
Maximum jump start voltage for single pulse short circuit
protection 28
-I
GND
DC reverse ground pin current 200 mA
I
OUT
OUTPUT DC output current Internally limited A
-I
OUT
Reverse D C output current 35
I
IN
INPUT DC input current
-1 to 10 mA
I
SEn
SEn DC input current
I
SEL
SEL
0,1
DC input current
I
FR
FaultRST DC input current
V
FR
FaultRST DC input volt ag e 7.5 V
DocID022509 Rev 9 9/46
VN7010AJ-E Electrical specification
45
2.2 Thermal data
I
SENSE
MultiSense pin DC output current (V
GND
=V
CC
and
V
SENSE
<0V) 10 mA
MultiSense pin DC output current in reverse (V
CC
< 0V) -20
E
MAX
Maximum switching energy (single pulse)
(T
DEMAG
=0.4ms; T
jstart
=150°C) 168 mJ
V
ESD
Electrostatic discharge (JEDEC 22A-114F)
– INPUT
– MultiSense
– SEn, SEL
0,1
, FaultRST
– OUTPUT
–V
CC
4000
2000
4000
4000
4000
V
V
V
V
V
V
ESD
Charge device model (CDM-AEC-Q100-011) 750 V
T
j
Junction operating temperature -40 to 150 °C
T
stg
Storage temperature -55 to 150
Table 3. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Table 4. Thermal data
Symbol Parameter Typ. value Unit
R
thj-board
Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8)
(1)
1. Device mounted on four-layers 2s2p PCB.
3.9
°C/WR
thj-amb
Thermal resistance junction-ambient (JEDEC JESD 51-5)
(2)
2. Device mounted on two-layers 2s0p PCB with 2 cm
2
heatsink copper trace.
55
R
thj-amb
Thermal resistance junction-ambient (JEDEC JESD 51-7)
(1)
21.2
Electrical specification VN7010AJ-E
10/46 DocID022509 Rev 9
2.3 Main electrical characteristics
7V< V
CC
< 18 V; -40 °C < T
j
< 150 °C, unless otherwise specified.
All typical values refer to V
CC
= 13 V; T
j
= 25°C, unless otherwise specified.
Table 5. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
CC
Operating supply
voltage 41328
V
V
USD
Undervoltage
shutdown 4
V
USDReset
Undervoltage
shutdown reset 5
V
USDhyst
Undervoltage
shutdown hysteresis 0.3
R
ON
On-state resistance
I
OUT
= 5 A; T
j
=25°C 10
mΩI
OUT
= 5 A; T
j
=150°C 20
I
OUT
= 5 A; V
CC
=4V; T
j
=25°C 15
V
clamp
Clamp voltage I
S
= 20 mA; T
j
= -40°C 38 V
I
S
=20mA; 25°C<T
j
< 150°C 41 46 52
I
STBY
Supply cu rrent in
standby at
V
CC
=13V
(1)
1. PowerMOS leakage included.
V
CC
=13V;
V
IN
=V
OUT
=V
FR
=V
SEn
=0V
V
SEL0,1
=0V; T
j
=25°C 0.5 µA
V
CC
=13V;
V
IN
=V
OUT
=V
FR
=V
SEn
=0V
V
SEL0,1
=0V; T
j
=85°C
(2)
2. Parameter specified by design; not subject to production test.
0.5 µA
V
CC
=13V;
V
IN
=V
OUT
=V
FR
=V
SEn
=0V
V
SEL0,1
=0V; T
j
=125°C 3µA
t
D_STBY
Standby mode
blanking time V
CC
=13V; V
IN
=5V;
V
SEn
=V
FR
=V
SEL0,1
=0V; I
OUT
=0A 60 300 550 µs
I
S(ON)
Supply cu rrent V
CC
=13V; V
SEn
=V
FR
=V
SEL0,1
=0V;
V
IN
=5V; I
OUT
=0A 35mA
I
GND(ON)
Contro l stage current
consumption in ON
state. All channels
active.
V
CC
=13V; V
SEn
=5V;
V
FR
=V
SEL0,1
=0V; V
IN
=5V;
I
OUT
=5A 6mA
I
L(off)
Off-state output
current at V
CC
=13V
V
IN
=V
OUT
=0V; V
CC
=13V;
T
j
=25°C 0 0.01 0.5 µA
V
IN
=V
OUT
=0V; V
CC
=13V;
T
j
=125°C 03
V
F
Output - V
CC
diode
voltage I
OUT
=-5A; T
j
= 150 °C 0.7 V
DocID022509 Rev 9 11/46
VN7010AJ-E Electrical specification
45
Table 6. Switching (V
CC
= 13 V; -40°C < T
j
< 150°C, unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)(1)
1. See Figure 6: Switching times and Pulse skew.
Turn-on delay time at T
j
=25°C R
L
=2.6 Ω10 70 120 µs
t
d(off)(1)
Turn-off delay time at T
j
= 25°C 10 40 100
(dV
OUT
/dt)
on(1)
T ur n-on vol tag e slop e at T
j
=25°C R
L
=2.6 Ω0.1 0.2 0.7 V/µs
(dV
OUT
/dt)
off(1)
T ur n-of f vo ltag e slope at T
j
= 25°C 0.1 0.3 0.7
W
ON
Switching energy losses at turn-
on (t
won
)R
L
=2.6 Ω—0.91.2
(2)
2. Parameter guaranteed by design and characterization; not subject to production test.
mJ
W
OFF
Switching energy losses at turn-
off (t
woff
)R
L
=2.6 Ω—0.60.8
(2)
mJ
t
SKEW(1)
Differential Pulse skew (t
PHL
-
t
PLH
)R
L
=2.6 Ω-90 -40 10 µs
Table 7. Logic Inputs (7 V < V
CC
< 28 V; -40°C < T
j
<150°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
INPUT characteristics
V
IL
Input low lev el volt a ge 0.9 V
I
IL
Low level input current V
IN
=0.9V 1 µA
V
IH
Input high level voltage 2.1 V
I
IH
High level inpu t current V
IN
=2.1V 10 µA
V
I(hyst)
Input hyste r es is voltage 0.2 V
V
ICL
Input clam p voltage I
IN
=1mA 5.3 7.2 V
I
IN
=-1mA -0.7
FaultRST characteristics
V
FRL
Input low lev el volt a ge 0.9 V
I
FRL
Low level input current V
IN
=0.9V 1 µA
V
FRH
Input high level voltage 2.1 V
I
FRH
High level inpu t current V
IN
=2.1V 10 µA
V
FR(hyst)
Input hyste r es is voltage 0.2 V
V
FRCL
Input clam p voltage I
IN
=1mA 5.3 7.5 V
I
IN
=-1mA -0.7
SEL
0,1
characteristics (7 V < V
CC
<18V)
V
SELL
Input low lev el volt a ge 0.9 V
I
SELL
Low level input current V
IN
=0.9V 1 µA
V
SELH
Input high level voltage 2.1 V
Electrical specification VN7010AJ-E
12/46 DocID022509 Rev 9
I
SELH
High level inpu t current V
IN
=2.1V 10 µA
V
SEL(hyst)
Input hyste r es is voltage 0.2 V
V
SELCL
Input clam p voltage I
IN
=1mA 5.3 7.2 V
I
IN
=-1mA -0.7
SEn characteristics ( 7 V < V
CC
<18V)
V
SEnL
Input low lev el volt a ge 0.9 V
I
SEnL
Low level input current V
IN
=0.9V 1 µA
V
SEnH
Input high level voltage 2.1 V
I
SEnH
High level inpu t current V
IN
=2.1V 10 µA
V
SEn(hyst)
Input hyste r es is voltage 0.2 V
V
SEnCL
Input clam p voltage I
IN
=1mA 5.3 7.2 V
I
IN
=-1mA -0.7
Table 8. Protections (7 V < V
CC
<18V; -40°C<T
j
< 150°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
LIMH
DC short circuit current V
CC
= 13 V 65 91 130
A
4V<V
CC
<18V
(1)
1. Parameter guaranteed by design and characterization; not subject to production test.
130
I
LIML
Short circuit current
during thermal cycling V
CC
=13V;
T
R
<T
j
<T
TSD
30
T
TSD
Shutdown temperature 150 175 200
°C
T
R
Reset tempera ture
(1)
T
RS
+1 T
RS
+7
T
RS
Thermal reset of fault
diagnostic indication V
FR
=0V; V
SEn
=5V; 135
T
HYST
Thermal hys te r es is
(T
TSD
-T
R
)
(1)
7
ΔT
J_SD
Dynamic temperature T
j
=-40°C;
V
CC
=13V 60 K
t
LATCH_RST
Fault reset time for
output unlatch
(1)
V
FR
= 5 V to 0 V;
V
SEn
=5V; V
IN
=5V;
V
SEL0
=0V;
V
SEL1
=0V
31020µs
V
DEMAG
Turn-off output voltage
clamp
I
OUT
=2A; L=6mH;
T
j
=-40°C V
CC
-38 V
I
OUT
=2A; L=6mH;
T
j
=25°C to 150°C V
CC
-41 V
CC
-46 V
CC
-52 V
V
ON
Output voltage drop
limitation I
OUT
=0.2A 20 mV
Table 7. Logic Inputs (7 V < V
CC
< 28 V; -40°C < T
j
< 150°C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
DocID022509 Rev 9 13/46
VN7010AJ-E Electrical specification
45
Table 9. MultiSense (7 V < V
CC
< 18 V; -40°C < T
j
< 150°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
SENSE_CL
MultiSense clamp
voltage V
SEn
=0V; I
SENSE
=1mA -17 -12 V
V
SEn
=0V; I
SENSE
=-1mA 7 V
Current Sense characteristics
K
0
I
OUT
/I
SENSE
I
OUT
= 0.9 A; V
SENSE
= 0.5 V;
V
SEn
=5V 3190 5210 7450
dK
0
/K
0(1)(2)
Current sense ratio
drift I
OUT
= 0.9 A; V
SENSE
= 0.5 V;
V
SEn
=5V -20 20 %
K
1
I
OUT
/I
SENSE
I
OUT
= 1.5 A; V
SENSE
=4V;
V
SEn
=5V 3530 4950 6560
dK
1
/K
1(1)(2)
Current sense ratio
drift I
OUT
= 1.5 A; V
SENSE
=4V;
V
SEn
=5V -15 15 %
K
2
I
OUT
/I
SENSE
I
OUT
= 6 A; V
SENSE
=4V;
V
SEn
=5V 3840 4720 5640
dK
2
/K
2(1)(2)
Current sense ratio
drift I
OUT
= 6 A; V
SENSE
=4V;
V
SEn
=5V -10 +10 %
K
3
I
OUT
/I
SENSE
I
OUT
=18A; V
SENSE
=4V;
V
SEn
=5V 4260 4710 5140
dK
3
/K
3(1)(2)
Current sense ratio
drift
I
OUT
=18A; V
SENSE
=4V;
V
SEn
=5V;
T
j
= -40 °C to 150 °C -5 5 %
I
SENSE
0
MultiSense
leakage current
MultiSense disabled:
V
SEn
=0V; 00.5
µA
MultiSense disabled:
-1 V < V
SENSE
<5V
(1)
-0.5 0.5
MultiSense enabled:
V
SEn
=5V;
Channel ON; I
OUT
= 0 A;
Diagno sti c sel ec ted;
V
IN
=5V; V
SEL0
=0V;
V
SEL1
=0V; I
OUT
=0A;
02
MultiSense enabled:
V
SEn
= 5 V; Channel OFF;
Diagno sti c sel ec ted:
V
IN
=0V; V
SEL0
=0V;
V
SEL1
=0V;
02
V
OUT_MSD(1)
Output Voltage for
MultiSense
shutdown
V
IN
=5V; V
SEn
=5V;
V
SEL0
=0V; V
SEL1
=0V;
R
SENSE
=2.7kΩ; I
OUT
=5A 5V
V
SENSE_SAT
Multisense
saturati on vol t age
V
CC
=7V; R
SENSE
= 2.7 K;
V
SEn
=5V; V
IN
=5V;
V
SEL0
=0V; V
SEL1
=0V;
I
OUT
=18A; T
j
= 150°C
5V
Electrical specification VN7010AJ-E
14/46 DocID022509 Rev 9
I
SENSE_SAT(1)
CS saturation
current
V
CC
=7V; V
SENSE
=4V;
V
IN
=5V; V
SEn
=5V;
V
SEL0
=0V; V
SEL1
=0V;
T
j
= 150°C
4mA
I
OUT_SAT(1)
Output sa turation
current
V
CC
=7V; V
SENSE
=4V;
V
IN
=5V; V
SEn
=5V;
V
SEL0
=0V; V
SEL1
=0V;
T
j
= 150°C
24 A
OFF-state diagnostic
V
OL
OFF-state open-
load voltage
detecti on thres ho ld
V
IN
=0V; V
SEn
=5V;
V
SEL0
=0V; V
SEL1
=0V; 234V
I
L(off2)
OFF-state output
sink current V
IN
=0V; V
OUT
=V
OL
;
T
j
= -40°C to 125°C -100 -15 µA
t
DSTKON
OFF-state
diagnostic delay
time from falling
edge of INPUT
(see Figure 9)
V
IN
= 5 V to 0 V; V
SEn
=5V;
V
SEL0
=0V; V
SEL1
=0V;
I
OUT
= 0 A; V
OUT
=4V 100 350 700 µs
t
D_OL_V
Settling tim e for
valid OFF-state
open load
diagnostic
indication from
rising edge of SEn
V
IN
=0V; V
FR
=0V;
V
SEL0
=0V; V
SEL1
=0V;
V
OUT
=4V; V
SEn
= 0 V to 5 V 60 µs
t
D_VOL
OFF-state
diagnostic delay
time from rising
edge of V
OUT
V
IN
=0V; V
SEn
=5V;
V
SEL0
=0V; V
SEL1
=0V;
V
OUT
=0V to 4V 530µs
Chip temperature analog feedback
V
SENSE_TC
MultiSense out put
voltage
proportional to chip
temperature
V
SEn
=5V;
V
SEL0
=0V; V
SEL1
=5V;
V
IN
=0V; R
SENSE
=1KΩ;
T
j
=-40°C
2.325 2.41 2.495 V
V
SEn
=5V;
V
SEL0
=0V; V
SEL1
=5V;
V
IN
=0V; R
SENSE
=1KΩ;
T
j
=25°C
1.985 2.07 2.155 V
V
SEn
=5V;
V
SEL0
=0V; V
SEL1
=5V;
V
IN
=0V; R
SENSE
=1KΩ;
T
j
= 125 °C
1.435 1.52 1.605 V
dV
SENSE_TC
/dT Temperature
coefficient T
j
= -40 °C to 150 °C -5.5 mV/K
Transfer function V
SENSE_TC
(T) = V
SENSE_TC
(T
0
)+dV
SENSE_TC
/dT*(T-
T
0
)
Table 9. MultiSense (7 V < V
CC
< 18 V; -40°C < T
j
< 150°C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
DocID022509 Rev 9 15/46
VN7010AJ-E Electrical specification
45
V
CC
supply vo ltage analog feedback
V
SENSE_VCC
MultiSense out put
voltage
proportional to V
CC
supply voltage
V
CC
=13V; V
SEn
=5V;
V
SEL0
=5V; V
SEL1
=5V;
V
IN
=0V; R
SENSE
=1KΩ
3.16 3.23 3.3 V
Transfer function
(3)
V
SENSE_VCC
=V
CC
/4
Fault diagnostic feedback (see Table 10)
V
SENSEH
MultiSense out put
voltage in fault
condition
V
CC
=13V; V
IN
=0V;
V
SEn
=5V; V
SEL0
=0V;
V
SEL1
=0V; I
OUT
= 0 A;
V
OUT
=4V; R
SENSE
=1kΩ
56.6V
I
SENSEH
MultiSense out put
current in fault
condition V
CC
=13V; V
SENSE
=5V 7 20 30 mA
MultiSense timings (current sense mode - see Figure 7)
t
DSENSE1H
Current sense
settling time from
rising edge of SEn
V
IN
=5V; V
SEn
= 0 V to 5 V;
R
SENSE
=1kΩ; R
L
=2.6Ω60 µs
t
DSENSE1L
Current sense
disable delay time
from falling edge of
SEn
V
IN
=5V; V
SEn
= 5 V to 0 V;
R
SENSE
=1kΩ; R
L
=2.6Ω520µs
t
DSENSE2H
Current sense
settling time from
rising edg e of
INPUT
V
IN
= 0 V to 5 V; V
SEn
=5V;
R
SENSE
=1kΩ; R
L
=2.6Ω100 250 µs
Δt
DSENSE2H
Current sense
settling time from
rising edge of I
OUT
(dynamic response
to a step ch ange of
I
OUT
)
V
IN
=5V; V
SEn
=5V;
R
SENSE
=1kΩ;
I
SENSE
= 90 % of I
SENSEMAX
;
R
L
=2.6Ω
100 µs
t
DSENSE2L
Current sense
turn-of f del ay time
from falling edge of
INPUT
V
IN
= 5 V to 0 V; V
SEn
=5V;
R
SENSE
=1kΩ; R
L
=2.6Ω50 250 µs
MultiSense timings (chip temperature sense mode - see Figure 8)
t
DSENSE3H
V
SENSE_TC
settling
time from rising
edge of SEn
V
SEn
= 0 V to 5 V;
V
SEL0
=0V; V
SEL1
=5V;
R
SENSE
=1kΩ
60 µs
t
DSENSE3L
V
SENSE_TC
disable
delay time from
falling edge of SEn
V
SEn
= 5 V to 0 V;
V
SEL0
=0V; V
SEL1
=5V;
R
SENSE
=1kΩ
20 µs
Table 9. MultiSense (7 V < V
CC
< 18 V; -40°C < T
j
< 150°C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Electrical specification VN7010AJ-E
16/46 DocID022509 Rev 9
MultiSen se timin gs (V
CC
voltage sense mode - see Figure 8)
t
DSENSE4H
V
SENSE_VCC
settling time from
rising edge of SEn
V
SEn
= 0 V to 5 V;
V
SEL0
=5V; V
SEL1
=5V;
R
SENSE
=1kΩ
60 µs
t
DSENSE4L
V
SENSE_VCC
disable delay time
from falling edge of
SEn
V
SEn
= 5 V to 0 V;
V
SEL0
=5V; V
SEL1
=5V;
R
SENSE
=1kΩ
20 µs
MultiSense timings (Multiplexer transition times)
(4)
t
D_CStoTC
MultiSense
transition delay
from current sense
to T
C
sense
V
IN
=5V; V
SEn
=5V;
V
SEL0
=0V;
V
SEL1
= 0 V to 5 V;
I
OUT
= 2.5 A; R
SENSE
=1kΩ
60 µs
t
D_TCtoCS
MultiSense
transition delay
from T
C
sense to
current sense
V
IN
=5V; V
SEn
=5V;
V
SEL0
=0V;
V
SEL1
= 5 V to 0 V;
I
OUT
=2.5A; R
SENSE
=1kΩ
20 µs
t
D_CStoVCC
MultiSense
transition delay
from current sense
to V
CC
sense
V
IN
=5V; V
SEn
=5V;
V
SEn
=5V; V
SEL0
=5V;
V
SEL1
= 0 V to 5 V;
I
OUT
=2.5A; R
SENSE
=1kΩ
60 µs
t
D_VCCtoCS
MultiSense
transition delay
from V
CC
sense to
current sense
V
IN
=5V; V
SEn
=5V;
V
SEL0
=5V;
V
SEL1
= 5 V to 0 V;
I
OUT
=2.5A; R
SENSE
=1kΩ
20 µs
t
D_TCtoVCC
MultiSense
transition delay
from T
C
sense to
V
CC
sense
V
CC
=13V; T
j
= 125 °C;
V
SEn
=5V; V
SEL0
= 0 V to
5V; V
SEL1
=5V;
R
SENSE
=1kΩ
20 µs
t
D_VCCtoTC
MultiSense
transition delay
from V
CC
sense to
T
C
sense
V
CC
=13V; T
j
= 125 °C;
V
SEn
=5V; V
SEL0
= 5 V to
0V; V
SEL1
=5V;
R
SENSE
=1kΩ
20 µs
1. Parameter specified by design; not subject to production test.
2. All values refer to V
CC
= 13 V; T
j
= 25°C, unless otherwise specified.
3. V
CC
sensing and T
C
are referred to GND potential.
4. Transition delay are measured up to +/- 10% of final conditions.
Table 9. MultiSense (7 V < V
CC
< 18 V; -40°C < T
j
< 150°C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
DocID022509 Rev 9 17/46
VN7010AJ-E Electrical specification
45
Figure 4. I
OUT
/I
SENSE
ver sus I
OUT
Figure 5. Current sense accuracy versus I
OUT
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Electrical specification VN7010AJ-E
18/46 DocID022509 Rev 9
Figure 6. Switching times and Pulse skew
Figure 7. MultiSense timings (current sense mode)
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VN7010AJ-E Electrical specification
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Figure 8. Multisense timings (chip temperature and V
CC
sense mode)
Figure 9. T
DSTKON
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20/46 DocID022509 Rev 9
Table 10. Truth table
Mode Conditions IN
X
FR SEn SEL
X
OUT
X
MultiSense Comments
Stand by All logic inputs
low LLLLL Hi-Z
Low quiescent
current
consumption
Normal Nominal load
connected;
T
j
<150°C
LX
Refer to
Table 11
L
Refer to
Table 11
HL H Outputs
configured for
auto-restart
HH H Outputs
configured for
Latch-off
Overload
Overload or
short to GND
causing:
T
j
>T
TSD
or
ΔT
j
>ΔT
j_SD
LX
Refer to
Table 11
L
Refer to
Table 11
HL H Output cycles with
temperature
hysteresis
H H L Output latches-off
Undervoltage V
CC
<V
USD
(falling) XXX X L
LHi-Z
Hi-Z
Re-start when
V
CC
>V
USD
+
V
USDhyst
(rising)
OFF-state
diagnostics Short to V
CC
LX Refer to
Table 11 HRefer to
Table 11
Open-lo ad L X H External pull-up
Negative
output
voltage
Inductive
loads turn-off LX Refer to
Table 11 <0V Refer to
Table 11
Table 11. MultiSense multiplexer addressing
SEn SEL
1
SEL
0
MUX
channel
MultiSense output
Nomal mode Overload OFF-state
diag.
(1)
1. In case the output channel corresponding to the selected MUX channel is latched off while the relevant
input is low, Multisense pin delivers feedback according to OFF-State diagnostic.
Example 1: FR = 1; IN = 0; OUT = L (latched); MUX channel = channel 0 diagnostic; Mutisense = 0
Example 2: FR = 1; IN = 0; OUT = latched, V
OUT
>V
OL
; MUX channel = channel 0 diagnostic;
Mutisense = V
SENSEH
Negative
output
LXX Hi-Z
HLLOutput
diagnostic ISENSE =
1/K * IOUT
VSENSE =
VSENSEH
VSENSE =
VSENSEH Hi-Z
HLH
HHLT
CHIP Sense VSENSE =V
SENSE_TC
HHHV
CC Sense VSENSE =V
SENSE_VCC
DocID022509 Rev 9 21/46
VN7010AJ-E Electrical specification
45
2.4 Waveforms
Figure 10. Latch functionality - behav ior in hard short circuit condition (T
AMB
<< T
TSD
)
Figure 11. Latch functionality - behavior in hard short circuit condition
Electrical specification VN7010AJ-E
22/46 DocID022509 Rev 9
Figure 12. Latch functionality - behavior in hard short circuit condition (autorestart mode + latch
off)
Figure 13. Standby mode activation
DocID022509 Rev 9 23/46
VN7010AJ-E Electrical specification
45
Figure 14. Standby state diagram
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2.5 Electrical characteristics curves
Figure 15. OFF-state output current Figure 16. Standby current
Figure 17. I
GND(ON)
vs. I
out
Figure 18. Logic input high level voltage
Figure 19. Logic input low level voltage Figure 20. High level logic input current
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Figure 21. Low level logic input current Figure 22. Logic Input hysteresis voltage
Figure 23. FaultRST Input clamp voltage Figure 24. Underv oltage shutdown
Figure 25. On-state resistance vs. T
case
Figure 26. On-state resistance vs. V
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Figure 27. Turn-on voltage slope Figure 28. Turn-off voltage slope
Figure 29. Won vs. T
case
Figure 30. Woff vs. T
case
Figure 31. I
LIMH
vs. T
case
Figure 32. OFF-state open-load voltage
detection threshold
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VN7010AJ-E Electrical specification
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Figure 33. V
sense
clamp vs. T
case
Figure 34. V
senseh
vs. T
case
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Protections VN7010AJ-E
28/46 DocID022509 Rev 9
3 Protections
3.1 Power limitation
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing ΔT
j
through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as soon
as ΔT
j
exceeds the safety level of ΔT
j_SD
. According to the voltage level on the FaultRST
pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the
maximum instantaneous power which can be handled (FaultRST = Low) or remains off
(FaultRST = High). The protection prevents fast thermal transient effects and, consequently ,
reduces thermo-mechanical fatigue.
3.2 Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), it automatically switches off and the diagnostic indication is triggered.
According to the voltage level on the FaultRST pin, the device switches on again as soon as
its junction temperature drops to T
R
(see Table 8, FaultRST = Low) or remains off
(FaultRST = High).
3.3 Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as
the other components of the system (e.g. bonding wires, wiring harness, connectors, loads,
etc.) from excessive current flow. Consequently, in case of short circuit, overload or during
load power-up, the output current is clamped to a safety level, I
LIMH
, by operating the output
power MOSFET in the active region.
3.4 Negative voltage clamp
In case the device drives inductive load, the output voltage reaches negative value during
turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain
value, V
DEMAG
(see Table 8), allowing the inductor energy to be dissipated without
damaging the device.
DocID022509 Rev 9 29/46
VN7010AJ-E Application information
45
4 Application information
Figure 35. Application diagram
4.1 GND protection network against reverse battery
Figure 36. Simplified internal structure
V
DD
OUT
OUT
OUT
OUT
A DC in
OUT
GND
GND
GND GND
Logic
OUTPUT
GND
FaultRST
INPUT
SEn
SEL
V
CC
Multisense
Current m irror
Rprot
Rprot
Rprot
Rprot
Rprot
+5V
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GND
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GND
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30/46 DocID022509 Rev 9
4.1.1 Diode (D
GND
) in the ground line
A resistor (typ. R
GND
=4.7kΩ) should be inserted in parallel to D
GND
if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network pr oduces a shift (≈600 mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
4.2 Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the V
CC
pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 12.
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:201 1(E), chapter 4. The DUT is intended as the present device
only, without components and accessed through V
CC
and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns automatically
to normal oper a tion after the test”.
Table 12. ISO 7637-2 - electrical transient conduction along supply line
Test
Pulse
2011(E)
Test pulse severity
level with Status II
functional performance
status
Minimum
number of
pulses or test
time
Burst cycle / pulse
repetition time Pulse duration and
pulse generator
internal impedance
Level U
S(1)
1. U
S
is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
min max
1 III -112V 500 pulses 0,5 s 2ms, 10Ω
2a III +55V 500 pulses 0,2 s 5 s 50μs, 2Ω
3a IV -2 20V 1h 90 ms 100 ms 0.1μs, 50 Ω
3b IV +150V 1h 90 ms 100 ms 0.1μs, 50 Ω
4
(2)
2. Test pulse from ISO 7637-2:2004(E).
IV -7V 1 pulse 100ms, 0.01Ω
Load dump according to ISO 16750-2:2010
Test B
(3)
3. With 40 V external suppressor referred to ground (-40°C < T
j
<150°C).
40V 5 pulse 1 min 400ms, 2Ω
DocID022509 Rev 9 31/46
VN7010AJ-E Application information
45
4.3 MCU I/Os protection
If a ground protection network is used and negative transients are present on the V
CC
line,
the control pins will be pulled negative. ST suggests to insert a resistor (R
prot
) in line bot h to
prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
Equation 1
V
CCpeak
/I
latchup
≤ R
prot
≤ (V
OHμC
-V
IH
-V
GND
) / I
IHmax
Calculation example:
For V
CCpeak
= -150 V; I
latchup
≥ 20mA; V
OHμC
≥ 4.5V
7.5 kΩ ≤ R
prot
≤ 140 kΩ.
Recommended values: R
prot
=15kΩ
4.4 Multisense - analog current sense
Diagnostic information on device and load status are provided by an analog output pin
(Multisense) delivering the following signals:
•Current monitor: current mirror of channel output current
•V
CC
monitor: voltage propotional to V
CC
•T
CASE
: voltage propotional to chip temperature
Those signals are routed through an analog multiplexer which is configured and controlled
by means of SELx and SEn pins, according to the address map in Table 11.
Application information VN7010AJ-E
32/46 DocID022509 Rev 9
Figure 37. Multisense and diagnostic – block diagram
SEL
1
SEn
MultiSense
R
SENSE
R
PROT
To uC ADC
OUT
Current
Sense
Fault
Fault
Diagnostic
V
SENSEH
MUX
Temp
V
CC
I
SENSE
I
OUT
K factor
V
CC
MONITOR
TEMP
MONITOR
CURRENT
MONITOR
Gate Driver
VCC – OUT
Clamp
T
VCC – GND
Clamp
Internal Supply
Undervoltage
shut-down
VON
Limitation
Current
Limitation
Power Limitation
Overtemperature
Short to VCC
Open-Load in OFF
SEL
0
Control & Diagnostic
GND
VCC
INPUT
FaultRST
DocID022509 Rev 9 33/46
VN7010AJ-E Application information
45
4.4.1 Principle of Multisense signal generation
Figure 38. Multisense block diagram
Current monitor
When current mode is selected in the Multisense, this output is capable to provide:
•Current mirror proportional to the load current in normal operation, deliv erin g
current proportional to the load according to known ratio named K
•Diagnostics flag in fault conditions delivering fixed voltage V
SENSEH
The current delivered by the current sense circuit, I
SENSE
, can be easily converted to a
voltage V
SENSE
by using an external sense resistor, R
SENSE
, allowing continuous load
monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), V
SENSE
calculation
can be done using simple equations
Current provided by Multisense output: I
SENSE
= I
OUT
/K
Voltage on R
SENSE
:
V
SENSE
= R
SENSE .
I
SENSE
= R
SENSE .
I
OUT
/K
).054
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Application information VN7010AJ-E
34/46 DocID022509 Rev 9
Where :
•V
SENSE
is voltage measurable on R
SENSE
resistor
•I
SENSE
is current provided from Multisense pin in current output mode
•I
OUT
is current flowing through output
•K factor represent the ratio between PowerMOS cells and SenseMOS cells; its spread
includes geometric factor spread, current sense amplifier offset and process
parameters spread of overall circuitry specifying ratio between I
OUT
and I
SENSE
.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the Multisense pin
which is switched to a “current limited” voltage source, V
SENSEH
(see Table 9).
In any case, the current sourced by the Multisense in this condition is limited to I
SENSEH
(see
Table 9).
The typical behavior in case of overload or hard short circuit is shown in Figure 10,
Figure 11 and Figure 12.
Figure 39. Analogue HSD – open-load detection in off-s tate
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DocID022509 Rev 9 35/46
VN7010AJ-E Application information
45
Figure 40. Open-load / short to V
CC
condition
4.4.2 T
CASE
and V
CC
monitor
In this case, MultiSense output operates in voltage mode and output level is referred to
device GND. Care must be taken in case a GND network protection is used, because of a
voltage shift is generated between device GND and the microcontroller input GND
reference.
Figure 41 shows link between V
MEASURED
and real V
SENSE
signal.
Table 13. Multisense pin levels in off-state
Condition Output Multisense SEn
Open-load
V
OUT
>V
OL
Hi-Z L
V
SENSEH
H
V
OUT
<V
OL
Hi-Z L
0H
Short to V
CC
V
OUT
>V
OL
Hi-Z L
V
SENSEH
H
Nominal V
OUT
<V
OL
Hi-Z L
0H
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Application information VN7010AJ-E
36/46 DocID022509 Rev 9
Figure 41. GND voltage shift
V
CC
monitor
Battery monitoring channel provides V
SENSE
= V
CC
/ 4.
Case temperature monitor
Case temperature monitor is capable to provide information about actual device
temperature. Since diode is used for temperature sensing, following equation describe link
between temperature and output V
SENSE
level:
V
SENSE_TC
(T) = V
SENSE_TC
(T
0
)+dV
SENSE_TC
/dT*(T-T
0
)
where dV
SENSE_TC
/ dT ~ typically -5.5 mV/K (for temperature range (-40
o
C to +150
o
C).
4.4. 3 Short to V
CC
and OFF-state open-load detection
Short to V
CC
A short circuit between V
CC
and output is indicated by the relevant current sense pin set to
V
SENSEH
during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor R
PU
connecting
the output to a positive supply voltage V
PU
.
It is preferable V
PU
to be switched off during the module standby mode in order to avoid the
overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
R
PU
must be selected in order to ensure V
OUT
> V
OLmax
in accordance with to following
equation:
Equation 2
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PU
V
PU
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I
Loff2()min @ 4V
-----------------------------------------<
DocID022509 Rev 9 37/46
VN7010AJ-E Application information
45
4.5 Maximum demagnetization energy (V
CC
=16V)
Figure 42. Maximum turn off current v er sus inductance
Note: Values are generated with R
L
=0
Ω.
In case of repetitive pulses, T
jstart
(at the beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves A and B.
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Package and PCB thermal data VN7010AJ-E
38/46 DocID022509 Rev 9
5 Package and PCB thermal data
5.1 PowerSSO-16 thermal data
Figure 43. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)
Figure 44. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7)
Table 14. PCB properties
Dimension Value
Board finish thickness 1.6 mm +/- 10%
Board dimension 77 mm x 86 mm
Board Materi al FR4
Copper thickness (top and bottom layers) 0.070 mm
Copper thickness (inner layers) 0.035 mm
Thermal vias separation 1.2 mm
Thermal via diameter 0.3 mm +/- 0.08 mm
Copper thickness on vias 0.025 mm
Footprint dimension (top layer) 2.2 mm x 3.9 mm
Heatsink copper area dimension (bottom layer) Footprint, 2 cm
2
or 8 cm
2
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DocID022509 Rev 9 39/46
VN7010AJ-E Package and PCB thermal data
45
Figure 45. R
thj-amb
vs PCB copper area in open box free air conditions
Figure 46. PowerSSO-16 thermal impedance junction ambient single pulse
Equation 3: pulse calculation formula
where δ = t
P
/T
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Package and PCB thermal data VN7010AJ-E
40/46 DocID022509 Rev 9
Figure 47. Thermal fitting model for PowerSSO-16
1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
Table 15. Thermal parameters
Area/island (cm
2
) Footprint 2 8 4L
R1 (°C/W) 0.15
R2 (°C/W) 1.7
R3 (°C/W) 7 775
R4 (°C/W) 16 664
R5 (°C/W) 30 20 10 3
R6 (°C/W) 26 20 18 7
C1 (W.s/°C) 0.0015
C2 (W.s/°C) 0.02
C3 (W.s/°C) 0.1
C4 (W.s/°C) 0.2 0.3 0.3 0.4
C5 (W.s/°C) 0.4 1 1 4
C6 (W.s/°C) 3 5 7 18
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DocID022509 Rev 9 41/46
VN7010AJ-E Package information
45
6 Package information
6.1 ECOPACK
®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
6.2 PowerSSO-16 package information
Figure 48. PowerSSO-16 package dimensions
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Package information VN7010AJ-E
42/46 DocID022509 Rev 9
Table 16. PowerSSO-16 mec h anical data
Symbol Millimeters
Min. Typ. Max.
Θ0° 8°
Θ10°
Θ25° 15°
Θ35° 15°
A1.70
A1 0.00 0.10
A2 1.10 1.60
b0.20 0.30
b1 0.20 0.25 0.28
c0.19 0.25
c1 0.19 0.20 0.23
D 4.90 BSC
D1 3.60 4.20
e 0.50 BSC
E 6.00 BSC
E1 3.90 BSC
E2 1.90 2.50
h0.25 0.50
L 0.40 0.60 0.85
L1 1.00 REF
N16
R0.07
R1 0.07
S0.20
Tolerance of form and position
aaa 0.10
bbb 0.10
ccc 0.08
ddd 0.08
eee 0.10
fff 0.10
ggg 0.15
DocID022509 Rev 9 43/46
VN7010AJ-E Order codes
45
7 Order codes
Table 17. Device summary
Package Order codes
Tube Tape and reel
PowerSSO-16 VN7010AJ-E VN7010AJTR-E
Revision history VN7010AJ-E
44/46 DocID022509 Rev 9
8 Revision history
Table 18. Document revision history
Date Revision Changes
23-Nov-2011 1 Initial release
07-Dec-2012 2
Updated Table 1: Pin functions
Updated Figure 2: Configuration diagram (top view)
Updated Table :
Table 3: Absolute maximum ratings:
–V
CCJS
: added row
–V
CCPK
, I
SENSE
, V
ESD
: updated parameter and value
–E
MAX
, -I
OUT
: updated parameter
Updated Table 4: Thermal data
Table 5: Power section:
–V
USDReset
, I
GDN(ON)
: added row
–V
clamp
, I
GND(ON)
: updated test conditions and values
–I
S(ON)
: update d test conditions
Updated Table 6: Switching (V
CC
=13V; -40°C<T
j
<150°C, unless
otherwise specified)
Table 8: Protections (7 V < V
CC
< 18 V; -40°C < T
j
<150°C):
–I
LIMH
, T
R
: added note
–t
LATCH_RST
: updated pa r ameters
Table 9: MultiSense (7 V < V
CC
<18V; -40°C<T
j
<150°C):
–dK
2
/K
2
, V
SENSE_CL
, V
OUT_MSD
, t
DSENSE1L
, t
DSENSE2H
,
Δt
DSENSE2H
, t
DSENSE2L
, t
DSENSE3H
, t
DSENSE3L
, t
DSENSE4H
,
t
DSENSE4L
, t
D_CStoTC
, t
D_TCtoCS
, t
D_CStoVCC
, t
D_VCCtoCS
,
t
D_TCtoVCC
, t
D_VCCtoTC
: updated test conditions
–K
0
, dK
0
/K
0
, K
1
, dK
1
/K
1
, K
2
, K
3
, dK
3
/K
3
, I
SENSE
0
, I
L(off2)
,
V
SENSE_TC
, V
SENSEH
, t
DSENSE1H
: updated test conditions and
values
–V
SENSE_SAT
, I
SENSE_SAT
, I
OUT_SAT
, t
D_OL_V
: added rows
–V
SENSE_VCC
, I
SENSEH
: updated valu es
Updated Table 11: MultiSense multiplexer addressing
Updated Figure 6: Switching times and Pulse skew
Removed Figure: Pulse skew
Table 10: Truth table:
– Overload: updated conditions
Table 11: MultiSense multiplexer addressing:
– added note
Updated Section 2.4: Waveforms
Added Chapte r 3: Protections and Chapter 4: Application
information
DocID022509 Rev 9 45/46
VN7010AJ-E Revision history
45
26-Mar-2013 3
Table 3: Absolute maximum ratings:
–V
CCPK
: updated p aram ete r
–-V
SENSE
: removed row
–E
MAX
: updated parameter and value
Table 4: Thermal data:
–R
thj-board
: updated valu e
Table 5: Power section:
–V
F
: updated test conditions
Table 6: Switching (V
CC
= 13 V; -40°C < T
j
< 150°C, unless
otherwise specified):
–W
ON
, W
OFF
: updated val ues
Table 9: MultiSense (7 V < V
CC
<18V; -40°C<T
j
<150°C):
–K
2
, K
3
: updated values
–dK
3
/K
3
: updated test conditions
Removed Table: Electrical transient requirements (part 1/3), Table:
Electrical transient requirements (part 2/3) and Table: Elec tri cal
transient requirements (part 3/3)
Removed Section: Load dump protection
Added Section 4.2: Immunity against transient electrical
disturbances
Updated Figure 39: Analog ue HSD – op en-loa d det ection in off-st ate
Updated Table 13: Multisense pin levels in off-s t ate
Updated Figure 41: GND voltage shift
Added Section 4.5: Maximum demagnetization energy (V
CC
=16V)
03-Sep-2013 4
Table 6: Switching (V
CC
= 13 V; -40°C < T
j
< 150°C, unless
otherwise specified):
–W
ON
, W
OFF
: updated val ues
Table 9: MultiSense (7 V < V
CC
<18V; -40°C<T
j
<150°C):
–K
0
, K
1
, K
2
, K
3
: updated values
Added Figure 4: I
OUT
/I
SENSE
versus I
OUT
and Figure 5: Current
sense accuracy vers us I
OUT
Added Section 2.5: El ectrical chara cteristics curves
Updated Section 6.2: PowerSSO-16 package information
18-Sep- 201 3 5 Updated discl ai mer.
19-Sep-2013 6 Table 3: Absolute maximum ratings:
–E
MAX
: updated parameter and value
Updated Figure 42: Maximum turn off current versus inductance
13-Nov-2013 7 Updated Features list
Table 4: Thermal data:
–R
thj-amb
: updated val ues
09-Jun-2014 8 Updated Section 6.2: PowerSSO-16 package information
08-Oct-2014 9 Updated Table 16: PowerSSO -16 mechanical data
Table 18. Document revision history (continued)
Date Revision Changes
VN7010AJ-E
46/46 DocID022509 Rev 9
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