2014-2018 Microchip Technology Inc. DS40001775D-page 1
PIC16(L)F1764/5/8/9
Description
The PIC16(L)F1764/5/8/9 family offers intelligent analog with digital peripherals to create up to two independent closed-
loop channels. These 14 and 20-pin devices enable the ability to interconnect the on-chip peripherals to create custom
functions specific to each application; helping simplify the implementation of a complex control system and give
designers the flexibility to innovate.
Core Features
• C Compiler Optimized RISC Architecture
• Only 49 Instructions
• Operating Speed:
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Up to Four 8-Bit Timers
• Up to Three 16-Bit Timers
• Power-on Reset (POR)
• Configurable Power-up Timer (PWRT)
• Brown-out Reset (BOR) with Selectable Trip Point
• Extended Watchdog Timer (EWDT):
- Low-power 31 kHz WDT
- Software-selectable prescaler
- Software-selectable enable
Memory
• Up to 14 Kbytes Flash Program Memory
• Up to 1024 Bytes Data RAM Memory
• Direct, Indirect and Relative Addressing modes
• High-Endurance Flash (HEF):
- 128B of nonvolatile data storage
- 100K erase/write cycles
Operating Characteristics
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF1764/5/8/9)
- 2.3V to 5.5V (PIC16F1764/5/8/9)
• Temperature Range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
eXtreme Low-Power (XLP) Features
• Sleep mode: 50 nA @ 1.8V, typical
• Watchdog Timer: 500 nA @ 1.8V, typical
• Secondary Oscillator: 500 nA @ 32 kHz
• Operating Current:
-8 A @ 32 kHz, 1.8V, typical
-32 A/MHz @ 1.8V, typical
• Low-Power BOR (LPBOR):
- 200 nA in Sleep
Digital Peripherals
• Configurable Logic Cell (CLC):
- Up to three CLCs; up to four selected inputs
- Integrated combinational and state logic
• Up to Two Complementary Output Generators
(COG):
- Push-Pull, Full-Bridge and Steering modes
• Up to Two Capture/Compare/PWM (CCP)
modules
• Pulse-Width Modulators (PWM):
- Up to two 10-bit PWMs
- Up to two 16-bit PWMs
• Peripheral Pin Select (PPS):
- Configure any digital pin to output
• Serial Communications:
- Enhanced USART (EUSART)
- SPI, I2C, RS-232, RS-485, LIN compatible
- Auto-Baud Detect, auto-wake-up on start
• Up to 18 I/O Pins:
- Individually programmable pull-ups
- Slew rate control
- Interrupt-On-Change (IOC) with edge select
• Up to Two Data Signal Modulators (DSM)
Intelligent Analog Peripherals
• 10-Bit Analog-to-Digital Converter (ADC):
- Up to 12 external channels
- Conversion available during Sleep
• Up to Two Operational Amplifiers (OPA):
- Selectable internal and external channels
• Up to Four Fast Comparators (COMP):
- Up to five external inverting inputs
- Up to eight external non-inverting inputs
- Fixed Voltage Reference at non-inverting
input(s)
- Comparator outputs externally accessible
• Digital-to-Analog Converters (DAC):
- Up to two 10-bit resolution DACs
- Up to two 5-bit resolution DACs
14/20-Pin, 8- Bit Flash Microcontrollers
2014-2018 Microchip Technology Inc. DS40001775D-page 2
PIC16(L)F1764/5/8/9
Intelligent Analog Peripherals (Cont.)
• Voltage Reference:
- Fixed Voltage Reference (FVR): 1.024V,
2.048V and 4.096V output levels
• Zero-Cross Detector (ZCD):
- Detect high-voltage AC signal
• Programmable Ramp Generator (PRG):
- Slope compensation
- Ramp generation
• High-Current Drive I/Os:
- 100 mA capacity @ 5V
Clocking Structure
• 16 MHz Internal Oscillator:
- ±1% at calibration
- Selectable frequency range, 32 MHz to
31 kHz
• 31 kHz Low-Power Internal Oscillator
• 4x Phase-Locked Loop (PLL):
- For up to 32 MHz internal operation
• External Oscillator Block with:
- Three External Clock modes up to 32 MHz
TABLE 1: PIC16(L)F1764/5/8/9 FAMILY TYPES
Device
Data Sheet Index
Program Memory F lash
(Words/Kbytes)
High-Endurance Flash (B)
Data SRAM (Bytes)
I/O Pins(2)
16-Bit Timers
8-Bit Timers w/HLT
Comparator
10-Bit ADC (ch)
5/10-Bit DAC
CCP
10/16-Bit PWM
COG
Data Signal Modulator
CLC
Op Amp
Zero-Cross Detect
Programmabl e Ramp Gen
High-Current I/Os
Peripheral Pin Select
EUSART
I2C/SPI
Debug(1)
PIC16(L)F1764 (A) 4096/7 128 512 12 3 1/3 2 8 1/1 1 1/1 1 1 3 1 1 1 2 Y 1 1 I/H
PIC16(L)F1765 (A) 8192/14 128 1024 12 3 1/3 2 8 1/1 1 1/1 1 1 3 1 1 1 2 Y 1 1 I/H
PIC16(L)F1768 (A) 4096/7 128 512 18 31/3 412 2/2 22/2 2 2 3 2 1 2 2 Y 1 1 I/H
PIC16(L)F1769 (A) 8192/14 128 1024 18 31/3 412 2/2 22/2 2 2 3 2 1 2 2 Y 1 1 I/H
Note 1: Debugging Methods: (I) – Integrated on Chip; (H) – via ICD Header; E – Emulation Product.
2: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document.)
A. DS-40001775 PIC16(L)F1764/5/8/9 Data Sheet, 14/20-Pin 8-Bit Flash Microcontrollers.
Note: For other small form factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
TABLE 2: PACKAGES
Packages PDIP SOIC TSSOP QFN SSOP
PIC16(L)F1764
PIC16(L)F1765
PIC16(L)F1768
PIC16(L)F1769
Note: Pin details are subject to change.
2014-2018 Microchip Technology Inc. DS40001775D-page 3
PIC16(L)F1764/5/8/9
PIN DIAGRAMS
FIGURE 1: 14-PIN PDIP, SOIC, TSSOP
FIGURE 2: 16-PIN QFN (4x4)
VDD
RA5
RA4
MCLR/VPP/RA3
RC5
RC4
VSS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC1
RC2
RC3
Note: See Tabl e 3 for location of all peripheral functions.
PIC16(L)F1764
PIC16(L)F1765
1
2
3
4
14
13
12
11
5
6
7
10
9
8
PIC16(L)F1764
PIC16(L)F1765
RA0
RA1
RA2
RC0
9
10
11
12
56
RC4
RC3
RC1
RC2
78
2
3
1
4
RA5
RA4
MCLR/VPP/RA3
RC5
1516 1314
NC
VDD
NC
VSS
Note: See Tabl e 3 for location of all peripheral functions.
2014-2018 Microchip Technology Inc. DS40001775D-page 4
PIC16(L)F1764/5/8/9
FIGURE 3: 20-PIN PDIP, SOIC, SSOP
FIGURE 4: 20-PIN QFN (4x4)
PIC16(L)F1768
PIC16(L)F1769
1
2
3
4
14
13
12
11
5
6
7
10
9
8
VDD
RA5
RA4
MCLR/VPP/RA3
RC5
RC4
VSS
RA0
RA1
RA2
RC0
RC1
RC2
RC3
Note: See Tabl e 4 for location of all peripheral functions.
18
17
16
15
20
19
RC6
RC7
RB7
RB4
RB5
RB6
PIC16(L)F1768
PIC16(L)F1769
Note: See Tab le 4 for location of all peripheral functions.
15 RA1
RA2
RC0
RC1
RC2
11
12
13
14
67
RC7
RB7
RB4
RB5
RB6
8910
2
3
1
181920 1617
5
4
VDD
RA5
RA4
MCLR/VPP/RA3
RC5
RC4
RC3
RC6
VSS
RA0
2014-2018 Microchip Technology Inc. DS40001775D-page 5
PIC16(L)F1764/5/8/9
PIN ALLOCATION TABLES
TABLE 3: 14-PIN AND 16-PIN ALLOCATION TABLE (PIC16(L)F1764/5)
I/O
14-Pin PDIP/SOIC/TSSOP
16-Pin QFN
ADC
Reference
DAC
Op A mp
Comparator
Zero Cross
Programmable
Ramp Generator
Timers
PWM
CCP
COG
CLC
Modulator
EUSART
MSSP
Interrupts
Pull-ups
Hi Current
Basic
RA0 13 12 AN0 VREF-
DAC1REF-
DAC3REF-
DAC1OUT1
DAC3OUT1
—C1IN0+ — — — — — — — — — — IOC Y — ICSPDAT
RA1 12 11 AN1 VREF+
DAC1REF+
DAC3REF+
— — C1IN0-
C2IN0-
— — — — — — — — — — IOC Y — ICSPCLK
RA2 11 10 AN2 — — — — ZCD —T0CKI(1) — — COG1IN(1) — — — — INT(1)
IOC
Y — —
RA3 4 3 — — — — — — — T6IN(1) — — — — MD1CH(1) — — IOC Y — VPP
MCLR
RA4 3 2 AN3 — — — — — — T1G(1)
SOSCO
— — — — MD1CL(1) — — IOC Y — OSC2
CLKOUT
RA5 2 1 — — — — — — — T1CKI(1)
T2IN(1)
SOSCI
— — — CLCIN3(1) MD1MOD(1) — — IOC Y — OSC1
CLKIN
RC0 10 9AN4 — — OPA1IN+ C2IN0+ — — T5CKI(1) — — — — — — SCL(1)
SCK(1,3) IOC Y — —
RC1 9 8 AN5 — — OPA1IN- C1IN1-
C2IN1-
— — T4IN(1) — — — CLCIN2(1) — — SDI(1)
SDA(1,3) IOC Y — —
RC2 8 7 AN6 — — OPA1OUT C1IN2-
C2IN2-
—PRG1IN0 — — — — — — — — IOC Y — —
RC3 7 6 AN7 — — — C1IN3-
C2IN3-
— — T5G(1) — — — CLCIN0(1) — — SS(1) IOC Y — —
RC4 6 5 — — — — — — PRG1R(1) T3G(1) — — — CLCIN1(1) —CK(1) —IOC Y Y —
RC5 54— — — — — — PRG1F(1) T3CKI(1) —CCP1(1) — — — RX(1,3) —IOC Y Y —
VDD 116 — — — — — — — — — — — — — — — — — — VDD
VSS 14 13 — — — — — — —— — — — — ——————VSS
OUT(2) — — — — — — C1OUT — — — PWM3 CCP1 COG1A CLC1OUT MD1OUT DT(3) SDO INT — — —
— — — — — —C2OUT— — —PWM5— COG1B CLC2OUT —TXSDA
(3) — — — —
— — — — — — — — — — — — COG1C CLC3OUT —CK SCK — — — —
— — — — — — — — — — — — COG1D — — —SCL
(3) — — — —
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS Input Selection register. See Table 12-1.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS Output Selection registers. See Ta bl e 1 2- 2 .
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1764/5/8/9
DS40001775D-page 6 2014-2018 Microchip Technology Inc.
TABLE 4: 20-PIN ALLOCATION TABLE (PIC16(L)F1768/9)
I/O
20-Pin PDIP/SOIC/SSOP
20-Pin QFN
ADC
Reference
DAC
Op Amp
Comparator
Zero Cross
Programmable
Ramp Generator
Timers
PWM
CCP
COG
CLC
Modulator
EUSART
MSSP
Interrupts
Pull-ups
Hi Current
Basic
RA0 19 16 AN0 VREF-
DAC1REF-
DAC2REF-
DAC3REF-
DAC4REF-
DAC1OUT1
DAC2OUT1
DAC3OUT1
DAC4OUT1
—C1IN0+
C3IN0+
— — — — — — — — — — IOC Y — ICSPDAT
RA1 18 15 AN1 VREF+
DAC1REF+
DAC2REF+
DAC3REF+
DAC4REF+
— — C1IN0-
C2IN0-
C3IN0-
C4IN0-
— — — — — — — — — — IOC Y — ICSPCLK
RA2 17 14 AN2 — — — — ZCD —T0CKI(1) — — COG1IN(1)
COG2IN(1) — — — — INT(1)
IOC
Y — —
RA3(4) 4 1 — — — — — — — T6IN(1) — — — — MD1CH(1)
MD2CH(1) — — IOC Y — VPP
MCLR
ICD
RA4 320 AN3 — — — — — — T1G(1)
SOSCO
— — — — MD1CL(1)
MD2CL(1) — — IOC Y — OSC2
CLKOUT
RA5 219 — — — — — — — T1CKI(1)
T2IN(1)
SOSCI
— — — CLCIN3(1) MD1MOD(1)
MD2MOD(1) — — IOC Y — OSC1
CLKIN
RB4 13 10 AN10 — — OPA1IN0- — — — — — — — — — — SDI(1)
SDA(1,3) IOC Y — —
RB5 12 9AN11 — — OPA1IN0+ — — — — — — — — — RX(1,3) — IOC Y — —
RB6 11 8 — — — — C1IN1+
C3IN1+
— — — — — — — — — SCL(1)
SCK(1,3) IOC Y — —
RB7 10 7 — — — — C2IN1+
C4IN1+
— — — — — — — — CK(1) — IOC Y — —
RC0 16 13 AN4 — — — C2IN0+
C4IN0+
— — T5CKI(1) — — — — — — — IOC Y — —
RC1 15 12 AN5 — — — C1IN1-
C2IN1-
C3IN1-
C4IN1-
— — T4IN(1) — — — CLCIN2(1) — — — IOC Y — —
RC2 14 11 AN6 — — OPA1OUT
OPA2IN1-
OPA2IN1+
C1IN2-
C2IN2-
—PRG1IN0
PRG2IN1
— — — — — — — — IOC Y — —
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS Input Selection register. See Table 12-1.
2: All pin outputs default to PORT latch data. Any input capable pin can be selected as a digital peripheral output with the PPS Output Selection registers. See Table 12-2.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: Input only.
2014-2018 Microchip Technology Inc. DS40001775D-page 7
PIC16(L)F1764/5/8/9
RC3 7 4 AN7 — — OPA2OUT
OPA1IN1-
OPA1IN1+
C1IN3-
C2IN3-
C3IN3-
C4IN3-
—PRG2IN0
PRG1IN1
T5G(1) — CCP2(1) —CLCIN0(1) — — — IOC Y — —
RC4 6 3 — — — — — — PRG1R(1)
PRG2R(1) T3G(1) — — — CLCIN1(1) — — — IOC Y Y —
RC5 52— — — — — — PRG1F(1)
PRG2F(1) T3CKI(1) — CCP1(1) — — — — — IOC Y Y —
RC6 8 5 AN8 — — OPA2IN0- — — — — — — — — — — SS(1) IOC Y — —
RC7 96AN9 — — OPA2IN0+ — — — — — — — — — — — IOC Y — —
VDD 118 — — — — — — — — — — — — — — — — —
VSS 20 17 — — — — — — — — — — — — — — — ——
OUT(2) — — — — — — C1OUT — — — PWM3 CCP1 COG1A CLC1OUT MD1OUT DT(3) SDO — — — —
— — — — — —C2OUT— — — PWM4 CCP2 COG1B CLC2OUT MD2OUT TX SDA(3) — — — —
— — — — — — C3OUT — — — PWM5 —COG1C CLC3OUT — CK SCK — — — —
— — — — — —C4OUT— — —PWM6—COG1D — — —SCL
(3) — — — —
— — — — — — — — — — — — COG2A — — — — — — — —
— — — — — — — — — — — — COG2B — — — — — — — —
— — — — — — — — — — — — COG2C — — — — — — — —
— — — — — — — — — — — —COG2D — — — — — — — —
TABLE 4: 20-PIN ALLOCATION TABLE (PIC16(L)F1768/9) (CONTINUED)
I/O
20-Pin PDIP/SOIC/SSOP
20-Pin QFN
ADC
Reference
DAC
Op Amp
Comparator
Zero Cross
Programmable
Ramp Generator
Timers
PWM
CCP
COG
CLC
Modulator
EUSART
MSSP
Interrupts
Pull-ups
Hi Current
Basic
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS Input Selection register. See Table 12-1.
2: All pin outputs default to PORT latch data. Any input capable pin can be selected as a digital peripheral output with the PPS Output Selection registers. See Table 12-2.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: Input only.
2014-2018 Microchip Technology Inc. DS40001775D-page 8
PIC16(L)F1764/5/8/9
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 10
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 22
3.0 Memory Organization ................................................................................................................................................................. 24
4.0 Device Configuration .................................................................................................................................................................. 62
5.0 Oscillator Module (with Fail-Safe Clock Monitor) ....................................................................................................................... 70
6.0 Resets ........................................................................................................................................................................................ 87
7.0 Interrupts .................................................................................................................................................................................... 96
8.0 Power-Down Mode (Sleep) ...................................................................................................................................................... 109
9.0 Watchdog Timer (WDT) ........................................................................................................................................................... 113
10.0 Flash Program Memory Control ............................................................................................................................................... 117
11.0 I/O Ports ................................................................................................................................................................................... 134
12.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 152
13.0 Interrupt-On-Change ................................................................................................................................................................ 160
14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 167
15.0 Temperature Indicator Module ................................................................................................................................................. 170
16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 172
17.0 5-Bit Digital-to-Analog Converter (DAC) Module...................................................................................................................... 186
18.0 10-Bit Digital-to-Analog Converter (DAC) Module.................................................................................................................... 190
19.0 Comparator Module.................................................................................................................................................................. 196
20.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 206
21.0 Timer0 Module ......................................................................................................................................................................... 212
22.0 Timer1/3/5 Module with Gate Control....................................................................................................................................... 215
23.0 Timer2/4/6 Module ................................................................................................................................................................... 226
24.0 Capture/Compare/PWM Modules ............................................................................................................................................ 248
25.0 10-Bit Pulse-Width Modulation (PWM) Module ........................................................................................................................ 261
26.0 16-Bit Pulse-Width Modulation (PWM) Module ........................................................................................................................ 267
27.0 Complementary Output Generator (COG) Module................................................................................................................... 293
28.0 Configurable Logic Cell (CLC).................................................................................................................................................. 332
29.0 Operational Amplifier (OPA) Modules ...................................................................................................................................... 346
30.0 Programmable Ramp Generator (PRG) Module ...................................................................................................................... 352
31.0 Data Signal Modulator (DSM) .................................................................................................................................................. 367
32.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 377
33.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 432
34.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 462
35.0 Instruction Set Summary.......................................................................................................................................................... 464
36.0 Electrical Specifications............................................................................................................................................................ 478
37.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 512
38.0 Development Support............................................................................................................................................................... 534
39.0 Packaging Information.............................................................................................................................................................. 538
Appendix A: Data Sheet Revision History ......................................................................................................................................... 559
The Microchip Website ..................................................................................................................................................................... 560
Customer Change Notification Service ............................................................................................................................................. 560
Customer Support ............................................................................................................................................................................. 560
Product Identification System ........................................................................................................................................................... 561
2014-2018 Microchip Technology Inc. DS40001775D-page 9
PIC16(L)F1764/5/8/9
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Website; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer No tific atio n Syst em
Register on our website at www.microchip.com to receive the most current information on all of our products.
2014-2018 Microchip Technology Inc. DS40001775D-page 10
PIC16(L)F1764/5/8/9
1.0 DEVICE OVERVIEW
The PIC16(L)F1764/5/8/9 are described within this data
sheet. See Table 2 for available package configurations.
Figure 1-1 shows a block diagram of the
PIC16(L)F1764/5 devices. Figure 1-2 shows a block
diagram of the PIC16(L)F1768/9 devices. Tab le 1 -2 and
Table 1-3 show the pinout descriptions.
Refer to Ta b l e 1 - 1 for peripherals available per device.
TABLE 1-1: DEVICE PERIPHERAL
SUMMARY
Peripheral
PIC16(L)F1764
PIC16(L)F1765
PIC16(L)F1768
PIC16(L)F1769
Analog-to-Digital Converter (ADC) ●●●●
Fixed Voltage Reference (FVR) ●●●●
Zero-Cross Detection (ZCD) ●●●●
Temperature Indicator ●●●●
Complementary Output Generator (COG)
COG1 ●●●●
COG2 ●●
Programmable Ramp Generator (PRG)
PRG1 ●●●●
PRG2 ●●
10-Bit Digital-to-Analog Converter (DAC)
DAC1 ●●●●
DAC2 ●●
5-Bit Digital-to-Analog Converter (DAC)
DAC3 ●●●●
DAC4 ●●
Capture/Compare/PWM (CCP/ECCP) Modules
CCP1 ●●●●
CCP2 ●●
Comparators
C1 ●●●●
C2 ●●●●
C3 ●●
C4 ●●
Configurable Logic Cell (CLC)
CLC1 ●●●●
CLC2 ●●●●
CLC3 ●●●●
Data Signal Modulator (DSM)
DSM1 ●●●●
DSM2 ●●
Enhanced Universal Synchronous/Asynchronous
Receiver/Transmitter (EUSART)
EUSART ●●●●
Master Synchronous Serial Ports
MSSP ●●●●
Op Amp
Op Amp 1 ●●●●
Op Amp 2 ●●
10-Bit Pulse-Width Modulator (PWM)
PWM3 ●●●●
PWM4 ●●
16-Bit Pulse-Width Modulator (PWM)
PWM5 ●●●●
PWM6 ●●
8-Bit Timers
Timer0 ●●●●
Timer2 ●●●●
Timer4 ●●●●
Timer6 ●●●●
16-Bit Timers
Timer1 ●●●●
Timer3 ●●●●
Timer5 ●●●●
TABLE 1-1: DEVICE PERIPHERAL
SUMMARY (CONTINUED)
Peripheral
PIC16(L)F1764
PIC16(L)F1765
PIC16(L)F1768
PIC16(L)F1769
2014-2018 Microchip Technology Inc. DS40001775D-page 11
PIC16(L)F1764/5/8/9
1.1 Register and Bit Naming
Conventions
1.1.1 REGISTER NAMES
When there are multiple instances of the same
peripheral in a device, the peripheral control registers
will be depicted as the concatenation of a peripheral
identifier, peripheral instance and control identifier. The
control registers section will show just one instance of
all the register names with an ‘x’ in the place of the
peripheral instance number. This naming convention
may also be applied to peripherals when there is only
one instance of that peripheral in the device to maintain
compatibility with other devices in the family that
contain more than one.
1.1.2 BIT NAMES
There are two variants for bit names:
• Short name: Bit function abbreviation
• Long name: Peripheral abbreviation + short name
1.1.2.1 Short Bit Names
Short bit names are an abbreviation for the bit function.
For example, some peripherals are enabled with the
EN bit. The bit names shown in the registers are the
short name variant.
Short bit names are useful when accessing bits in C
programs. The general format for accessing bits by the
short name is RegisterNamebits.ShortName. For
example, the enable bit, EN, in the COG1CON0 regis-
ter can be set in C programs with the instruction
COG1CON0bits.EN = 1.
Short names are generally not useful in assembly
programs because the same name may be used by
different peripherals in different bit positions. When this
occurs, during the include file generation, all instances
of that short bit name are appended with an underscore
plus the name of the register in which the bit resides to
avoid naming contentions.
1.1.2.2 Long Bit Names
Long bit names are constructed by adding a peripheral
abbreviation prefix to the short name. The prefix is
unique to the peripheral thereby making every long bit
name unique. The long bit name for the COG1 enable
bit is the COG1 prefix, G1, appended with the enable
bit short name, EN, resulting in the unique bit name
G1EN.
Long bit names are useful in both C and assembly pro-
grams. For example, in C the COG1CON0 enable bit
can be set with the G1EN = 1 instruction. In assembly,
this bit can be set with the BSF COG1CON0,G1EN
instruction.
1.1.2.3 Bit Fields
Bit fields are two or more adjacent bits in the same
register. Bit fields adhere only to the short bit naming
convention. For example, the three Least Significant
bits of the COG1CON0 register contain the mode
control bits. The short name for this field is MD. There
is no long bit name variant. Bit field access is only
possible in C programs. The following example
demonstrates a C program instruction for setting the
COG1 to the Push-Pull mode:
COG1CON0bits.MD = 0x5;
Individual bits in a bit field can also be accessed with
long and short bit names. Each bit is the field name
appended with the number of the bit position within the
field. For example, the Most Significant mode bit has
the short bit name MD2, and the long bit name is
G1MD2. The following two examples demonstrate
assembly program sequences for setting the COG1 to
Push-Pull mode:
Example 1:
MOVLW ~(1<<G1MD1)
ANDWF COG1CON0,F
MOVLW 1<<G1MD2 | 1<<G1MD0
IORWF COG1CON0,F
Example 2:
BSF COG1CON0,G1MD2
BCF COG1CON0,G1MD1
BSF COG1CON0,G1MD0
1.1.3 REGISTER AND BIT NAMING
EXCEPTIONS
1.1.3.1 Status, Interrupt and Mirror Bits
Status, interrupt enables, interrupt flags and mirror bits
are contained in registers that span more than one
peripheral. In these cases, the bit name shown is
unique, so there is no prefix or short name variant.
1.1.3.2 Legacy Peripherals
There are some peripherals that do not strictly adhere
to these naming conventions. Peripherals that have
existed for many years and are present in almost every
device are the exceptions. These exceptions were
necessary to limit the adverse impact of the new
conventions on legacy code. Peripherals that do
adhere to the new convention will include a table in the
registers section indicating the long name prefix for
each peripheral instance. Peripherals that fall into the
exception category will not have this table. These
peripherals include, but are not limited to, the following:
• EUSART
• MSSP
2014-2018 Microchip Technology Inc. DS40001775D-page 12
PIC16(L)F1764/5/8/9
FIGURE 1-1: PIC16(L) F1764 /5 BLOCK DIAG RAM
PORTA
PORTC
Note 1: See applicable chapters for more information on peripherals.
CPU
Program
Flash Memory
RAM
Timing
Generation
LFINTOSC
Oscillator
MCLR
Figure 1-1
CLKIN
CLKOUT
ADC
10-Bit FVR
Temp .
Indicator EUSART
Comparators
MSSP
Timers
Timers
DAC CCP
PWMs
Op Amp
HFINTOSC/
CLCs
COG
ZCD
DSM
PRG
8-Bit 16-Bit
DAC
5-Bit
10-Bit
2014-2018 Microchip Technology Inc. DS40001775D-page 13
PIC16(L)F1764/5/8/9
FIGURE 1-2: PIC16(L) F1768 /9 BLOCK DIAG RAM
PORTA
PORTB
PORTC
CPU
Program
Flash Memory RAM
Timing
Generation
LFINTOSC
Oscillator
MCLR
Figure 1-1
CLKIN
CLKOUT
ADC
10-Bit FVR
Temp.
Indicator EUSART
Comparators
MSSP
TimersTimers
DACs CCPs
PWMsOp Amps
HFINTOSC/
CLCs
COG
ZCD
DSMs
PRGs
8-Bit 16-Bit
DACs
5-Bit
10-Bit
Note 1: See applicable chapters for more information on peripherals.
2014-2018 Microchip Technology Inc. DS40001775D-page 14
PIC16(L)F1764/5/8/9
TABLE 1-2: PIC16(L)F1764/5 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
RA0/AN0/C1IN0+/VREF-/
DAC1REF-/DAC3REF-/
DAC1OUT1/DAC3OUT1/
ICSPDAT
RA0 TTL/ST CMOS General purpose I/O.
AN0 AN — ADC Channel 0 input.
C1IN0+ AN — Comparator C1 positive input.
VREF- AN — ADC negative reference.
DAC1REF- AN — DAC1 negative reference.
DAC3REF- AN — DAC3 negative reference.
DAC1OUT1 — AN DAC1 voltage output.
DAC3OUT1 — AN DAC3 voltage output.
ICSPDAT ST CMOS ICSP™ data I/O.
RA1/AN1/C1IN0-/C2IN0-/VREF+/
DAC1REF+/DAC3REF+/
ICSPCLK
RA1 TTL/ST CMOS General purpose I/O.
AN1 AN — ADC Channel 1 input.
C1IN0- AN — Comparator C1 negative input.
C2IN0- AN — Comparator C2 negative input.
VREF+ AN — ADC positive reference.
DAC1REF+ AN — DAC1 positive reference.
DAC3REF+ AN — DAC3 positive reference.
ICSPCLK ST — Serial programming clock.
RA2/AN2/ZCD/T0CKI/COG1IN/
INT
RA2 TTL/ST CMOS General purpose I/O.
AN2 AN — ADC Channel 2 input.
ZCD AN — Zero-Cross Detection input.
T0CKI TTL/ST — Timer0 clock input.
COG1IN(1) TTL/ST — Complementary Output Generator 1 input.
INT(1) TTL/ST — Interrupt input.
RA3/T6IN/MD1CH/MCLR/VPP RA3 TTL/ST — General purpose input.
T6IN(1) TTL/ST — Timer6 clock input.
MD1CH(1) TTL/ST — Data Signal Modulator 1 high carrier input.
MCLR ST — Master Clear input.
VPP HV — Programming enable.
RA4/AN3/SOSCO/T1G/
MD1CL/OSC2/CLKOUT
RA4 TTL/ST CMOS General purpose I/O.
AN3 AN — ADC Channel 3 input.
SOSCO — XTAL Secondary Oscillator connection.
T1G(1) TTL/ST — Timer1 gate input.
MD1CL(1) TTL/ST — Data Signal Modulator 1 low carrier input.
OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).
CLKOUT — CMOS FOSC/4 output.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS Input Selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as peripheral digital outputs with the
PPS Output Selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2014-2018 Microchip Technology Inc. DS40001775D-page 15
PIC16(L)F1764/5/8/9
RA5/T1CKI/T2IN/CLCIN3/
MD1MOD/SOSCI/OSC1/CLKIN
RA5 TTL/ST CMOS General purpose I/O.
T1CKI(1) TTL/ST — Timer1 clock input.
T2IN(1) TTL/ST — Timer2 clock input.
CLCIN3(1) TTL/ST — CLC Input 3.
MD1MOD(1) TTL/ST — Data Signal Modulator modulation input.
SOSCI — XTAL Secondary Oscillator connection.
OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).
CLKIN ST — External Clock input (EC mode).
RC0/AN4/OPA1IN+/C2IN0+/
T5CKI/SCL/SCK
RC0 TTL/ST CMOS General purpose I/O.
AN4 AN ADC Channel 4 input.
OPA1IN+ AN — Operational Amplifier 1 non-inverting input.
C2IN0+ AN — Comparator 2 positive input.
T5CKI(1) TTL/ST — Timer5 clock input.
SCL(1,3) I2C—I
2C clock output.
SCK(1) TTL/ST — SPI clock input.
RC1/AN5/OPA1IN-/C1IN1-/
C2IN1-/T4IN/CLCIN2/SDI/SDA
RC1 TTL/ST CMOS General purpose I/O.
AN5 AN XTAL ADC Channel 5 input.
OPA1IN- AN — Operational Amplifier 1 inverting input.
C1IN1- AN — Comparator 1 negative input.
C2IN1- AN — Comparator 2 negative input.
T4IN(1) TTL/ST — Timer4 clock input.
CLCIN2(1) TTL/ST — CLC Input 2.
SDI(1) TTL/ST — SPI data input.
SDA(1) I2C—I
2C data output.
RC2/AN6/OPA1OUT/C1IN2-/
C2IN2-/PRG1IN0
RC2 TTL/ST CMOS General purpose I/O.
AN6 AN — ADC Channel 6 input.
OPA1OUT — AN Operational Amplifier 1 output.
C1IN2- AN — Comparator 1 negative input.
C2IN2- AN — Comparator 2 negative input.
PRG1IN0 AN — Ramp Generator 1 reference voltage input.
RC3/AN7/C1IN3-/C2IN3-/T5G/
CLCIN0/SS
RC3 TTL/ST CMOS General purpose I/O.
AN7 AN — ADC Channel 7 input.
C1IN3- AN — Comparator 1 negative input.
C2IN3- AN — Comparator 2 negative input.
T5G(1) TTL/ST — Timer5 gate input.
CLCIN0(1) TTL/ST — CLC Input 0.
SS(1) TTL/ST — SPI Slave Select input.
TABLE 1-2: PIC16(L)F1764/5 PINOUT DE SC RIPT ION (CONT IN U ED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS Input Selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as peripheral digital outputs with the
PPS Output Selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2014-2018 Microchip Technology Inc. DS40001775D-page 16
PIC16(L)F1764/5/8/9
RC4/T3G/PRG1R/CLCIN1/CK RC4 TTL/ST CMOS General purpose I/O.
T3G(1) TTL/ST — Timer3 gate input.
PRG1R(1) TTL/ST — Ramp generator set_rising input.
CLCIN1(1) TTL/ST — CLC Input 1.
CK(1) TTL/ST — EUSART clock input.
RC5/T3CKI/PRG1F/CCP1/RX RC5 TTL/ST CMOS General purpose I/O.
T3CKI(1) TTL/ST — Timer3 clock input.
PRG1F(1) TTL/ST — Ramp generator set_falling input.
CCP1(1) TTL/ST — CCP1 capture input.
RX(1,3) TTL/ST — EUSART receive input.
VDD VDD Power — Positive supply.
VSS VSS Power — Ground reference.
OUT(2) C1OUT CMOS Comparator 1 output.
C2OUT CMOS Comparator 2 output.
CCP1 CMOS Compare/PWM1 output.
MD1OUT CMOS Data Signal Modulator 1 output.
PWM3 CMOS PWM3 output.
PWM5 CMOS PWM5 output.
COG1A CMOS Complementary Output Generator Output A.
COG1B CMOS Complementary Output Generator Output B.
COG1C CMOS Complementary Output Generator Output C.
COG1D CMOS Complementary Output Generator Output D.
SDA(3) OD I2C data output.
SCK CMOS SPI clock output.
SCL(3) OD I2C clock output.
SDO CMOS SPI data output.
TX CMOS EUSART asynchronous TX data out.
CK CMOS EUSART synchronous clock out.
DT(3) CMOS EUSART synchronous data output.
CLC1OUT CMOS Configurable Logic Cell 1 output.
CLC2OUT CMOS Configurable Logic Cell 2 output.
CLC3OUT CMOS Configurable Logic Cell 3 output.
TABLE 1-2: PIC16(L)F1764/5 PINOUT DE SC RIPT ION (CONT IN U ED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS Input Selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as peripheral digital outputs with the
PPS Output Selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2014-2018 Microchip Technology Inc. DS40001775D-page 17
PIC16(L)F1764/5/8/9
TABLE 1-3: PIC16(L)F1768/9 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
RA0/AN0/C1IN0+/C3IN0+/VREF-/
DAC1REF-/DAC2REF-/
DAC3REF-/DAC4REF-/
DAC1OUT1/DAC2OUT1./
DAC3OUT1/DAC4OUT1/
ICSPDAT
RA0 TTL/ST CMOS General purpose I/O.
AN0 AN — ADC Channel 0 input.
C1IN0+ AN — Comparator C1 positive input.
C3IN0+ AN Comparator C3 positive input.
DAC1REF- AN — DAC1 negative reference.
DAC2REF- AN — DAC2 negative reference.
DAC3REF- AN — DAC3 negative reference.
DAC4REF- AN — DAC4 negative reference.
DAC1OUT1 — AN DAC1 voltage output.
DAC2OUT1 — AN DAC2 voltage output.
DAC3OUT1 — AN DAC3 voltage output.
DAC4OUT1 — AN DAC4 voltage output.
VREF- AN — ADC negative reference.
ICSPDAT ST CMOS ICSP™ data I/O.
RA1/AN1/C1IN0-/C2IN0-/
C3IN0-/C4IN0-/VREF+/
DAC1REF+/DAC2REF+/
DAC3REF+/DAC4REF+/
ICSPCLK
RA1 TTL/ST CMOS General purpose I/O.
AN1 AN — ADC Channel 1 input.
C1IN0- AN — Comparator C1 negative input.
C2IN0- AN — Comparator C2 negative input.
C3IN0- AN — Comparator C3 negative input.
C4IN0- AN — Comparator C4 negative input.
DAC1REF+ AN — DAC1 positive reference.
DAC2REF+ AN — DAC2 positive reference.
DAC3REF+ AN — DAC3 positive reference.
DAC4REF+ AN — DAC4 positive reference.
VREF+ AN — ADC positive reference.
ICSPCLK ST — Serial programming clock.
RA2/AN2/ZCD/T0CKI/COG1IN/
COG2IN/INT
RA2 TTL/ST CMOS General purpose I/O.
AN2 AN — ADC Channel 2 input.
ZCD AN — Zero-Cross Detection input.
T0CKI(1) TTL/ST — Timer0 clock input.
COG1IN(1) TTL/ST — Complementary Output Generator 1 input.
COG2IN(1) TTL/ST — Complementary Output Generator 2 input.
INT(1) TTL/ST — Interrupt input.
RA3/T6IN/MD1CH/MD2CH/
MCLR/VPP
RA3 TTL/ST — General purpose input.
T6IN(1) TTL/ST — Timer6 clock input.
MD1CH(1) TTL/ST — Data Signal Modulator 1 high carrier input.
MD2CH(1) TTL/ST — Data Signal Modulator 2 high carrier input.
MCLR ST — Master Clear input.
VPP HV — Programming enable.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS Input Selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as peripheral digital outputs with the
PPS Output Selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2014-2018 Microchip Technology Inc. DS40001775D-page 18
PIC16(L)F1764/5/8/9
RA4/AN3/SOSCO/T1G/
DSM1CL/DSM2CL/OSC2/
CLKOUT
RA4 TTL/ST CMOS General purpose I/O.
AN3 AN — ADC Channel 3 input.
SOSCO — XTAL Secondary Oscillator connection.
T1G(1) TTL/ST — Timer1 gate input.
DSM1CL(1) TTL/ST — Data Signal Modulator 1 low carrier input.
DSM2CL(1) TTL/ST — Data Signal Modulator 2 low carrier input.
OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).
CLKOUT — CMOS FOSC/4 output.
RA5/T1CKI/T2IN/CLCIN3/
DSM1MOD/DSM2MOD/
SOSCI/OSC1/CLKIN
RA5 TTL/ST CMOS General purpose I/O.
T1CKI(1) TTL/ST — Timer1 clock input.
T2IN(1) TTL/ST — Timer2 clock input.
CLCIN3(1) TTL/ST — CLC Input 3.
DSM1MOD(1) TTL/ST — Data Signal Modulator 1 modulation input.
DSM2MOD(1) TTL/ST — Data Signal Modulator 2 modulation input.
SOSCI XTAL — Secondary Oscillator connection.
OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).
CLKIN ST — External Clock input (EC mode).
RB4/AN10/OPA1IN0-/SDI/SDA RB4 TTL/ST CMOS General purpose I/O.
AN10 AN — ADC Channel 10 input.
OPA1IN0- AN — Operational Amplifier 1 inverting input.
SDI(1) TTL/ST — SPI data input.
SDA(1,3) I2C—I
2C data output.
RB5/AN11/OPA1IN0+/RX RB5 TTL/ST CMOS General purpose I/O.
AN11 AN — ADC Channel 11 input.
OPA1IN0+ AN — Operational Amplifier 1 non-inverting input.
RX(1,3) TTL/ST — EUSART receive input.
RB6/C1IN1+/C3IN1+/SCK/SCL RB6 TTL/ST CMOS General purpose I/O.
C1IN1+ AN — Comparator C1 positive input.
C3IN1+ AN — Comparator C3 positive input.
SCK(1) TTL/ST — SPI clock input.
SCL(1,3) I2C—I
2C clock output.
RB7/C2IN1+/C4IN1+/CK RB7 TTL/ST CMOS General purpose I/O.
C2IN1+ AN — Comparator C2 positive input.
C4IN1+ AN — Comparator C4 positive input.
CK(1) TTL/ST — EUSART clock input.
RC0/AN4/C2IN0+/C4IN0+/
T5CKI
RC0 TTL/ST CMOS General purpose I/O.
AN4 AN ADC Channel 4 input.
C2IN0+ AN — Comparator C2 positive input.
C4IN0+ AN — Comparator C4 positive input.
T5CKI(1) TTL/ST — Timer5 clock input.
TABLE 1-3: PIC16(L)F1768/9 PINOUT DE SC RIPT ION (CONT IN U ED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS Input Selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as peripheral digital outputs with the
PPS Output Selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2014-2018 Microchip Technology Inc. DS40001775D-page 19
PIC16(L)F1764/5/8/9
RC1/AN5/C1IN1-/C2IN1-/
C3IN1-/C4IN1-/T4IN/CLCIN2
RC1 TTL/ST CMOS General purpose I/O.
AN5 AN XTAL ADC Channel 5 input.
C1IN1- AN — Comparator 1 negative input.
C2IN1- AN — Comparator 2 negative input.
C3IN1- AN — Comparator 3 negative input.
C4IN1- AN — Comparator 4 negative input.
T4IN(1) TTL/ST — Timer4 clock input.
CLCIN2(1) TTL/ST — CLC Input 2.
RC2/AN6/OPA1OUT/OPA2IN1-/
OPA2IN1+/C1IN2-/C2IN2-/
PRG1IN0/PRG2IN1
RC2 TTL/ST CMOS General purpose I/O.
AN6 AN — ADC Channel 6 input.
OPA1OUT — AN Operational Amplifier 1 output.
OPA2IN1- AN Operational Amplifier 2 inverting input.
OPA2IN1+ AN Operational Amplifier 2 non-inverting input.
C1IN2- AN — Comparator 1 negative input.
C2IN2- AN — Comparator 2 negative input.
PRG1IN0 AN — Ramp Generator 1 reference voltage input.
PRG2IN1 AN — Ramp Generator 2 reference voltage input.
RC3/AN7/OPA2OUT/OPA1IN1-/
OPA1IN1+/C1IN3-/C2IN3-/
C3IN3-/C4IN3-/PRG1IN1/
PRG2IN0/T5G/CCP2/CLCIN0
RC3 TTL/ST CMOS General purpose I/O.
AN7 AN — ADC Channel 7 input.
OPA2OUT — AN Operational Amplifier 2 output.
OPA1IN1- AN Operational Amplifier 1 inverting input.
OPA1IN1+ AN Operational Amplifier 1 non-inverting input.
C1IN3- AN — Comparator 1 negative input.
C2IN3- AN — Comparator 2 negative input.
C3IN3- AN — Comparator 3 negative input.
C4IN3- AN — Comparator 4 negative input.
PRG1IN1 AN — Ramp Generator 1 reference voltage input.
PRG2IN0 AN — Ramp Generator 2 reference voltage input.
T5G(1) TTL/ST — Timer5 gate input.
CCP2(1) TTL/ST — CCP2 capture input.
CLCIN0(1) TTL/ST — CLC Input 0.
RC4/T3G/PRG1R/PRG2R/
CLCIN1
RC4 TTL/ST CMOS General purpose I/O.
T3G(1) TTL/ST — Timer3 gate input.
PRG1R(1) TTL/ST — Ramp Generator 1 set_rising input.
PRG2R(1) TTL/ST — Ramp Generator 2 set_rising input.
CLCIN1(1) TTL/ST — CLC Input 1.
RC5/T3CKI/PRG1F/PRG2F/
CCP1
RC5 TTL/ST CMOS General purpose I/O.
T3CKI(1) TTL/ST — Timer3 clock input.
PRG1F(1) TTL/ST — Ramp Generator 1 set_falling input.
PRG2F(1) TTL/ST — Ramp Generator 2 set_falling input.
CCP1(1) TTL/ST — CCP1 capture input.
TABLE 1-3: PIC16(L)F1768/9 PINOUT DE SC RIPT ION (CONT IN U ED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS Input Selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as peripheral digital outputs with the
PPS Output Selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2014-2018 Microchip Technology Inc. DS40001775D-page 20
PIC16(L)F1764/5/8/9
RC6/AN8/OPA2IN0-/SS RC6 TTL/ST CMOS General purpose I/O.
AN8 AN — ADC Channel 8 input.
OPA2IN0- AN — Operational Amplifier 2 inverting input.
SS(1) TTL/ST — SPI Slave Select input.
RC7/AN9/OPA2IN0+ RC7 TTL/ST CMOS General purpose I/O.
AN9 AN — ADC Channel 9 input.
OPA2IN0+ AN — Operational Amplifier 2 non-inverting input.
VDD VDD Power — Positive supply.
VSS VSS Power — Ground reference.
OUT(2) C1OUT CMOS Comparator 1 output.
C2OUT CMOS Comparator 2 output.
C3OUT CMOS Comparator 3 output.
C4OUT CMOS Comparator 4 output.
CCP1 CMOS Compare/PWM1 output.
CCP2 CMOS Compare/PWM2 output.
MD1OUT CMOS Data Signal Modulator 1 output.
MD2OUT CMOS Data Signal Modulator 2 output.
PWM3 CMOS PWM3 output.
PWM4 CMOS PWM4 output.
PWM5 CMOS PWM5 output.
PWM6 CMOS PWM6 output.
COG1A CMOS Complementary Output Generator 1 Output A.
COG1B CMOS Complementary Output Generator 1 Output B.
COG1C CMOS Complementary Output Generator 1 Output C.
COG1D CMOS Complementary Output Generator 1 Output D.
COG2A CMOS Complementary Output Generator 2 Output A.
COG2B CMOS Complementary Output Generator 2 Output B.
COG2C CMOS Complementary Output Generator 2 Output C.
COG2D CMOS Complementary Output Generator 2 Output D.
SDA(3) OD I2C data output.
SCK CMOS SPI clock output.
SCL(3) OD I2C clock output.
SDO CMOS SPI data output.
TX CMOS EUSART asynchronous TX data out.
CK CMOS EUSART synchronous clock out.
DT(3) CMOS EUSART synchronous data output.
CLC1OUT CMOS Configurable Logic Cell 1 output.
CLC2OUT CMOS Configurable Logic Cell 2 output.
CLC3OUT CMOS Configurable Logic Cell 3 output.
TABLE 1-3: PIC16(L)F1768/9 PINOUT DE SC RIPT ION (CONT IN U ED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS Input Selection registers.
2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as peripheral digital outputs with the
PPS Output Selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
2014-2018 Microchip Technology Inc. DS40001775D-page 21
PIC16(L)F1764/5/8/9
1.2 Peripheral Connection Matrix
Input selection multiplexers on many of the peripherals
enable selecting the output of another peripheral, such
that the signal path is contained entirely within the
device. Although the peripheral output can also be
routed to a pin with the PPS selection feature, it is not
necessary to do so. Table 1-4 shows all the possible
inter-peripheral signal connections. Please refer to the
corresponding peripheral section to obtain the
multiplexer selection codes for the desired connection.
TABLE 1-4: PERIPHERAL CONNECTION MATRIX
Peripheral Input
Peripheral Output
ADC Trigge r
COG Cloc k
COG Rising/Falling
COG Shutdown
10-Bit DAC
5-Bit DAC
PRG Analog Input
PRG Rising/Falling
Comparator +
Comparator -
CLC
DSM CH
DSM CL
DSM Mod
Op Amp +
Op Amp -
Op Amp Override
10-Bit PWM
16-Bit PWM
CCP Capture
CCP Clock
Timer2/4/6 Clock
Timer2/4/6 Reset
Timer1/3/5 Gate
Timer0 Clock
FVR ●●●●● ●●
ZCD ● ● ●
PRG ●●●
10-Bit DAC ● ● ●●
5-Bit DAC ● ● ●●
CCP ● ● ● ●●●● ● ●
Comparator (sync) ● ●● ●●●●
Comparator (async) ●● ●
CLC ●●● ●●●● ● ● ● ●
DSM
COG ●
EUSART TX/CK ● ●
EUSART DT ● ●
MSSP SCK/SCL ● ●
MSSP SDO/SDA ● ●
Op Amp ●
10-Bit PWM ● ● ● ●●●● ● ●
16-Bit PWM ● ● ● ●●●● ● ●
Timer0 Overflow ● ● ●
Timer2 = T2PR ● ● ● ● ●
Timer4 = T4PR ● ● ● ● ●
Timer6 = T6PR ● ● ● ● ●
Timer2 Postscale ● ● ● ● ● ●
Timer4 Postscale ● ● ● ● ● ●
Timer6 Postscale ● ● ● ● ● ●
Timer1 Overflow ● ● ● ●
Timer3 Overflow ● ● ● ●
Timer5 Overflow ● ● ● ●
SOSC ● ●
FOSC/4 ● ●
FOSC ●●●● ● ●
HFINTOSC ●●●● ● ●
LFINTOSC ● ● ●
MFINTOSC ●
IOCIF ● ● ●
PPS Input Pin ●● ● ● ●● ●●●●●●
2014-2018 Microchip Technology Inc. DS40001775D-page 22
PIC16(L)F1764/5/8/9
2.0 ENHANCED MID-RANGE CPU
This family of devices contains an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect and
Relative Addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
• Automatic Interrupt Context Saving
• 16-Level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set
FIGURE 2-1: CORE BLOCK DIAGRAM
8
14
Program
Bus
Instruction reg
Program Counter
16-Level Stack
(15-bit)
Direct Addr 7
12
Addr MUX
FSR reg
MUX
ALU
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode and
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
8
8
Brown-out
Reset
12
3
Internal
Oscillator
Block
8
Instruction reg 7
Addr MUX
FSR reg
MUX
ALU
W Reg
8
3
Internal
Oscillator
Block
15 Data Bus 8
Instruction Reg 7
RAM Addr
Addr MUX
Indirect
Addr
FSR0 Reg
STATUS Reg
MUX
ALU
VDD
8
3
VSS
Internal
Oscillator
Block
RAM
FSR1 Reg
15
15
MUX
15
Program Memory
Read (PMR)
12
FSR regFSR reg
BSR Reg
5
ConfigurationConfiguration
Configuration
Flash
Program
Memory
2014-2018 Microchip Technology Inc. DS40001775D-page 23
PIC16(L)F1764/5/8/9
2.1 Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”
for more information.
2.2 16-Level Stack with Overflow and
Underflow
These devices have a hardware stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Under-
flow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled, will cause a
Software Reset. See Section 3.5 “Stack” for more
details.
2.3 File Select Regist ers
There are two 16-bit File Select Registers (FSRs).
FSRs can access all file registers and program
memory, which allows one Data Pointer for all memory.
When an FSRn points to program memory, there is one
additional instruction cycle in instructions using INDFn to
allow the data to be fetched. General purpose memory
can now also be addressed linearly, providing the ability
to access contiguous data larger than 80 bytes. There
are also new instructions to support the FSRs. See
Section 3.6 “Indirect Addressing” for more details.
2.4 Instructi on Set
There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 35.0 “Instruction Set Summary” for more
details.
2014-2018 Microchip Technology Inc. DS40001775D-page 24
PIC16(L)F1764/5/8/9
3.0 MEMORY ORGANIZATION
These devices contain the following types of memory:
• Program Memory:
- Configuration Words
- Device ID
-User ID
- Flash Program Memory
• Data Memory:
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
•Stack
• Indirect Addressing
3.1 Program Memory Organization
The enhanced mid-range core has a 15-bit Program
Counter (PC) capable of addressing a 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented for the PIC16(L)F1764/5/8/9 family.
Accessing a location above these boundaries will cause
a wrap around within the implemented memory space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figure 3-1).
3.2 High-Endurance Flash
This device has a 128-byte section of high-endurance
Program Flash Memory (PFM) in lieu of data EEPROM.
This area is especially well suited for nonvolatile data
storage that is expected to be updated frequently over
the life of the end product. See Section 10.2 “Flash
Program Memory Overview” for more information on
writing data to PFM. See Section 3.2.1.2 “Indirect
Read with FS Rn” for more information about using the
FSRn registers to read byte data stored in PFM.
Note 1: The method to access Flash memory
through the PMCON registers is described
in Section 10.0 “Flash Program Memory
Control”.
TABLE 3-1: DEVICE SIZES AND ADDRESSES
Device Pr ogram Mem ory S pace
(Words) Last Program Memory
Address High-Endurance Flash
Memory Address Range(1)
PIC16(L)F1764 4,096 0FFFh 0F80h-0FFFh
PIC16(L)F1765 8,192 1FFFh 1F80h-1FFFh
PIC16(L)F1768 4,096 0FFFh 0F80h-0FFFh
PIC16(L)F1769 8,192 1FFFh 1F80h-1FFFh
Note 1: High-endurance Flash applies to the low byte of each address in the range.
2014-2018 Microchip Technology Inc. DS40001775D-page 25
PIC16(L)F1764/5/8/9
FIGURE 3-1: PROGRAM MEMORY MAP
AND STACK FOR
PIC16(L)F1764/5/8/9
3.2.1 READING PROGRAM MEMORY AS
DATA
There are two methods of accessing constants in
program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSRn to point to the program memory.
3.2.1.1 RETLW Instruction
The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.
EXAMPL E 3-1: RETLW INSTRUCTION
The BRW instruction makes this type of table very
simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available, so the older table read
method must be used.
3.2.1.2 Indirect Read with FSRn
The program memory can be accessed as data by
setting bit 7 of the FSRnH register and reading the
matching INDFn register. The MOVIW instruction will
place the lower eight bits of the addressed word in the
W register. Writes to the program memory cannot be
performed via the INDFn registers. Instructions that
access the program memory via the FSRn require one
extra instruction cycle to complete. Example 3-2
demonstrates accessing the program memory via an
FSRn.
The high directive will set bit 7 if a label points to a
location in program memory.
PC<14:0>
15
0000h
0004h
Stack Level 0
Stack Level 15
Reset Vector
Interrupt Vector
CALL, CALLW
RETURN, RETLW
Stack Level 1
0005h
On-Chip
Program
Memory
Page 0
07FFh
Rollover to Page 0
0800h
0FFFh
1000h
7FFFh
Page 1
Rollover to Page 1
Interrupt, RETFIE
constants
BRW ;Add Index in W to
;program counter to
;select data
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W
2014-2018 Microchip Technology Inc. DS40001775D-page 26
PIC16(L)F1764/5/8/9
EXAMPLE 3-2: ACCESSING PROGRAM
MEMORY VIA FSRn
3.3 Data Memory Organizati on
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-2):
• 12 core registers
• 20 Special Function Registers (SFRs)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSRs). See Section 3.6 “Indirect
Addressing” for more information.
Data memory uses a 12-bit address. The upper five bits
of the address define the Bank address and the lower
seven bits select the registers/RAM in that bank.
3.3.1 CORE REGISTERS
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses, x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Ta bl e 3- 2. For detailed
information, see Tab le 3- 15.
TABLE 3-2: CORE REGISTERS
3.3.1.1 STATUS Register
The STATUS register, shown in Register 3-1, contains:
• The arithmetic status of the ALU
• The Reset status
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits, refer to Section 35.0
“Instruction Set Summary”.
constants
DW DATA0 ;First constant
DW DATA1 ;Second constant
DW DATA2
DW DATA3
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
ADDLW LOW constants
MOVWF FSR1L
MOVLW
HIGH constants
;MSb sets
automatically
MOVWF FSR1H
BTFSC STATUS, C ;carry from ADDLW?
INCF FSR1H, f ;yes
MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W
Note: The C and DC bits operate as Borrow and
Digit Borrow out bits, respectively, in
subtraction.
Addresses BANKx
x00h or x80h INDF0
x01h or x81h INDF1
x02h or x82h PCL
x03h or x83h STATUS
x04h or x84h FSR0L
x05h or x85h FSR0H
x06h or x86h FSR1L
x07h or x87h FSR1H
x08h or x88h BSR
x09h or x89h WREG
x0Ah or x8Ah PCLATH
x0Bh or x8Bh INTCON
2014-2018 Microchip Technology Inc. DS40001775D-page 27
PIC16(L)F1764/5/8/9
REGISTER 3-1: STAT US : STATUS REGIST ER
U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u
— — —TOPD ZDC
(1) C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-5 Unimplemented: Read as ‘0’
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand.
2014-2018 Microchip Technology Inc. DS40001775D-page 28
PIC16(L)F1764/5/8/9
3.3.2 SPECIAL FUNCTION REGISTER
The Special Function Registers (SFRs) are registers
used by the application to control the desired operation
of peripheral functions in the device. The SFR occupies
the 20 bytes after the core registers of every data
memory bank (addresses, x0Ch/x8Ch through
x1Fh/x9Fh). The registers associated with the operation
of each peripheral are described in the corresponding
peripheral chapters of this data sheet.
3.3.3 GENERAL PURPOSE RAM
There are up to 80 bytes of General Purpose Registers
(GPRs) in each data memory bank. The GPR occupies
the space immediately after the SFR of selected data
memory banks. The number of banks selected depends
on the total amount of GPR space available in the
device.
3.3.3.1 Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.6.2
“Linear Data Memory” for more information.
3.3.4 COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
FIGURE 3-2: BANKED MEMORY
PARTITIONING
3.3.5 DEVICE MEMORY MAPS
The memory maps for the device family are shown in
Tables 3-3 through 3-14.
0Bh
0Ch
1Fh
20h
6Fh
70h
7Fh
00h
Common RAM
(16 bytes)
General Purpose RAM
(80 bytes maximum)
Core Registers
(12 bytes)
Special Function Registers
(20 bytes maximum)
Memory Region7-Bit Bank
Offset
PIC16(L)F1764/5/8/9
DS40001775D-page 29 2014-2018 Microchip Technology Inc.
TABLE 3-3: PIC16(L)F1764 MEMORY MAP (BANKS 0-7)
Legend: = Unimplemented data memory locations, read as ‘0’.
Note 1: Unimplemented on PIC16LF1764.
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h
Core Registers
(Ta b l e 3 - 2 )
080h
Core Registers
(Table 3-2)
100h
Core Registers
(Ta b l e 3 - 2 )
180h
Core Registers
(Ta b l e 3 - 2 )
200h
Core Registers
(Table 3-2)
280h
Core Registers
(Ta b l e 3 - 2 )
300h
Core Registers
(Table 3-2)
380h
Core Registers
(Ta b l e 3 - 2 )
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA
00Dh —08Dh—10Dh— 18Dh —20Dh— 28Dh —30Dh—38Dh—
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC
00Fh —08Fh— 10Fh CMOUT 18Fh —20Fh—28Fh—30Fh— 38Fh —
010h —090h— 110h CM1CON0 190h —210h—290h—310h— 390h —
011h PIR1 091h PIE1 111h CM1CON1 191h PMADRL 211h SSP1BUF 291h CCPR1L 311h — 391h IOCAP
012h PIR2 092h PIE2 112h CM1NSEL 192h PMADRH 212h SSP1ADD 292h CCPR1H 312h — 392h IOCAN
013h PIR3 093h PIE3 113h CM1PSEL 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h — 393h IOCAF
014h PIR4 094h PIE4 114h CM2CON0 194h PMDATH 214h SSP1STAT 294h CCP1CAP 314h — 394h —
015h TMR0 095h OPTION_REG 115h CM2CON1 195h PMCON1 215h SSP1CON1 295h —315h— 395h —
016h TMR1L 096h PCON 116h CM2NSEL 196h PMCON2 216h SSP1CON2 296h —316h— 396h —
017h TMR1H 097h WDTCON 117h CM2PSEL 197h VREGCON(1) 217h SSP1CON3 297h —317h— 397h IOCCP
018h T1CON 098h OSCTUNE 118h — 198h —218h—298h—318h— 398h IOCCN
019h T1GCON 099h OSCCON 119h — 199h RC1REG 219h —299h—319h— 399h IOCCF
01Ah T2TMR 09Ah OSCSTAT 11Ah — 19Ah TX1REG 21Ah —29Ah— 31Ah —39Ah—
01Bh T2PR 09Bh ADRESL 11Bh — 19Bh SP1BRGL 21Bh —29Bh— 31Bh — 39Bh MD1CON0
01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SP1BRGH 21Ch — 29Ch —31Ch— 39Ch MD1CON1
01Dh T2HLT 09Dh ADCON0 11Dh — 19Dh RC1STA 21Dh BORCON 29Dh —31Dh—39DhMD1SRC
01Eh T2CLKCON 09Eh ADCON1 11Eh — 19Eh TX1STA 21Eh FVRCON 29Eh CCPTMRS 31Eh — 39Eh MD1CARL
01Fh T2RST 09Fh ADCON2 11Fh — 19Fh BAUD1CON 21Fh ZCD1CON 29Fh —31Fh— 39Fh MD1CARH
020h
General
Purpose
Register
80 Bytes
0A0h
General
Purpose
Register
80 Bytes
120h
General
Purpose
Register
80 Bytes
1A0h
General
Purpose
Register
80 Bytes
220h
General
Purpose
Register
80 Bytes
2A0h
General
Purpose
Register
80 Bytes
320h General Purpose
Register
16 Bytes
3A0h
Unimplemented
Read as ‘0’
32Fh
330h
Unimplemented
Read as ‘0’
06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh
070h
Common RAM
70h-7Fh
0F0h
Accesses
70h-7Fh
170h
Accesses
70h-7Fh
1F0h
Accesses
70h-7Fh
270h
Accesses
70h-7Fh
2F0h
Accesses
70h-7Fh
370h
Accesses
70h-7Fh
3F0h
Accesses
70h-7Fh
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
2014-2018 Microchip Technology Inc. DS40001775D-page 30
PIC16(L)F1764/5/8/9
TABLE 3-4: PIC16LF1765 MEMORY MAP (BANKS 0-7)
Legend: = Unimplemented data memory locations, read as ‘0’.
Note 1: Unimplemented on PIC16LF1765.
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h
Core Registers
(Table 3-2)
080h
Core Registers
(Table 3-2)
100h
Core Registers
(Ta b l e 3 - 2 )
180h
Core Registers
(Ta b l e 3 - 2 )
200h
Core Registers
(Ta b l e 3 - 2 )
280h
Core Registers
(Ta b l e 3 - 2 )
300h
Core Registers
(Ta b l e 3 - 2 )
380h
Core Registers
(Table 3 -2)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA
00Dh —08Dh—10Dh—18Dh—20Dh— 28Dh — 30Dh —38Dh—
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC
00Fh —08Fh— 10Fh CMOUT 18Fh —20Fh—28Fh—30Fh— 38Fh —
010h —090h— 110h CM1CON0 190h — 210h — 290h —310h— 390h —
011h PIR1 091h PIE1 111h CM1CON1 191h PMADRL 211h SSP1BUF 291h CCPR1L 311h — 391h IOCAP
012h PIR2 092h PIE2 112h CM1NSEL 192h PMADRH 212h SSP1ADD 292h CCPR1H 312h — 392h IOCAN
013h PIR3 093h PIE3 113h CM1PSEL 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h — 393h IOCAF
014h PIR4 094h PIE4 114h CM2CON0 194h PMDATH 214h SSP1STAT 294h CCP1CAP 314h — 394h —
015h TMR0 095h OPTION_REG 115h CM2CON1 195h PMCON1 215h SSP1CON 295h —315h— 395h —
016h TMR1L 096h PCON 116h CM2NSEL 196h PMCON2 216h SSP1CON2 296h —316h— 396h —
017h TMR1H 097h WDTCON 117h CM2PSEL 197h VREGCON(1) 217h SSP1CON3 297h —317h— 397h IOCCP
018h T1CON 098h OSCTUNE 118h — 198h — 218h — 298h —318h— 398h IOCCN
019h T1GCON 099h OSCCON 119h — 199h RC1REG 219h — 299h —319h— 399h IOCCF
01Ah T2TMR 09Ah OSCSTAT 11Ah — 19Ah TX1REG 21Ah —29Ah—31Ah—39Ah—
01Bh T2PR 09Bh ADRESL 11Bh — 19Bh SP1BRGL 21Bh —29Bh—31Bh— 39Bh MD1CON0
01Ch T2CON 09Ch ADRESH 11Ch —19ChSP1BRGH21Ch— 29Ch — 31Ch — 39Ch MD1CON1
01Dh T2HLT 09Dh ADCON0 11Dh — 19Dh RC1STA 21Dh BORCON 29Dh — 31Dh —39DhMD1SRC
01Eh T2CLKCON 09Eh ADCON1 11Eh — 19Eh TX1STA 21Eh FVRCON 29Eh CCPTMRS 31Eh — 39Eh MD1CARL
01Fh T2RST 09Fh ADCON2 11Fh — 19Fh BAUD1CON 21Fh ZCD1CON 29Fh —31Fh— 39Fh MD1CARH
020h
General
Purpose
Register
80 Bytes
0A0h
General
Purpose
Register
80 Bytes
120h
General
Purpose
Register
80 Bytes
1A0h
General
Purpose
Register
80 Bytes
220h
General
Purpose
Register
80 Bytes
2A0h
General
Purpose
Register
80 Bytes
320h
General
Purpose
Register
80 Bytes’
3A0h
General
Purpose
Register
80 Bytes’
06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh
070h
Common RAM
70h-7Fh
0F0h
Accesses
70h-7Fh
170h
Accesses
70h-7Fh
1F0h
Accesses
70h-7Fh
270h
Accesses
70h-7Fh
2F0h
Accesses
70h-7Fh
370h
Accesses
70h-7Fh
3F0h
Accesses
70h-7Fh
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
PIC16(L)F1764/5/8/9
DS40001775D-page 31 2014-2018 Microchip Technology Inc.
TABLE 3-5: PIC16(L)F1768 MEMORY MAP (BANKS 0-7)
Legend: = Unimplemented data memory locations, read as ‘0’.
Note 1: Unimplemented on PIC16LF1768.
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h
Core Registers
(Table 3 -2)
080h
Core Registers
(Ta b l e 3 - 2 )
100h
Core Registers
(Table 3-2)
180h
Core Registers
(Ta b l e 3 - 2 )
200h
Core Registers
(Table 3-2)
280h
Core Registers
(Table 3 -2)
300h
Core Registers
(Ta b l e 3 - 2 )
380h
Core Registers
(Table 3-2)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh ODCONB 30Dh SLRCONB 38Dh INLVLB
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC
00Fh —08Fh— 10Fh CMOUT 18Fh —20Fh—28Fh—30Fh—38Fh—
010h —090h— 110h CM1CON0 190h — 210h —290h—310h—390h—
011h PIR1 091h PIE1 111h CM1CON1 191h PMADRL 211h SSP1BUF 291h CCPR1L 311h — 391h IOCAP
012h PIR2 092h PIE2 112h CM1NSEL 192h PMADRH 212h SSP1ADD 292h CCPR1H 312h —392hIOCAN
013h PIR3 093h PIE3 113h CM1PSEL 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h —393hIOCAF
014h PIR4 094h PIE4 114h CM2CON0 194h PMDATH 214h SSP1STAT 294h CCP1CAP 314h — 394h IOCBP
015h TMR0 095h OPTION_REG 115h CM2CON1 195h PMCON1 215h SSP1CON1 295h —315h—395hIOCBN
016h TMR1L 096h PCON 116h CM2NSEL 196h PMCON2 216h SSP1CON2 296h —316h—396hIOCBF
017h TMR1H 097h WDTCON 117h CM2PSEL 197h VREGCON(1) 217hSSP1CON3297h —317h— 397h IOCCP
018h T1CON 098h OSCTUNE 118h CM3CON0 198h — 218h — 298h CCPR2L 318h — 398h IOCCN
019h T1GCON 099h OSCCON 119h CM3CON1 199h RC1REG 219h — 299h CCPR2H 319h — 399h IOCCF
01Ah T2TMR 09Ah OSCSTAT 11Ah CM3NSEL 19Ah TX1REG 21Ah — 29Ah CCP2CON 31Ah — 39Ah —
01Bh T2PR 09Bh ADRESL 11Bh CM3PSEL 19Bh SP1BRGL 21Bh — 29Bh CCP2CAP 31Bh MD2CON0 39Bh MD1CON0
01Ch T2CON 09Ch ADRESH 11Ch CM4CON0 19Ch SP1BRGH 21Ch —29Ch— 31Ch MD2CON1 39Ch MD1CON1
01Dh T2HLT 09Dh ADCON0 11Dh CM4CON1 19Dh RC1STA 21Dh BORCON 29Dh — 31DhMD2SRC39DhMD1SRC
01Eh T2CLKCON 09Eh ADCON1 11Eh CM4NSEL 19Eh TX1STA 21Eh FVRCON 29Eh CCPTMRS 31Eh MD2CARL 39Eh MD1CARL
01Fh T2RST 09Fh ADCON2 11Fh CM4PSEL 19Fh BAUD1CON 21Fh ZCD1CON 29Fh — 31Fh MD2CARH 39Fh MD1CARH
020h
General
Purpose
Register
80 Bytes
0A0h
General
Purpose
Register
80 Bytes
120h
General
Purpose
Register
80 Bytes
1A0h
General
Purpose
Register
80 Bytes
220h
General
Purpose
Register
80 Bytes
2A0h
General
Purpose
Register
80 Bytes
320h General Pur-
pose Register
16 Bytes
3A0h
Unimplemented
Read as ‘0’
32Fh
330h
Unimplemented
Read as ‘0’
06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh
070h
Common RAM
70h-7Fh
0F0h
Accesses
70h-7Fh
170h
Accesses
70h-7Fh
1F0h
Accesses
70h-7Fh
270h
Accesses
70h-7Fh
2F0h
Accesses
70h-7Fh
370h
Accesses
70h-7Fh
3F0h
Accesses
70h-7Fh
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
2014-2018 Microchip Technology Inc. DS40001775D-page 32
PIC16(L)F1764/5/8/9
TABLE 3-6: PIC16(L)F1769 MEMORY MAP (BANKS 0-7)
Legend: = Unimplemented data memory locations, read as ‘0’.
Note 1: Unimplemented on PIC16LF1769.
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h
Core Registers
(Ta b l e 3 - 2 )
080h
Core Registers
(Ta b l e 3 - 2 )
100h
Core Registers
(Ta b l e 3 - 2 )
180h
Core Registers
(Ta b l e 3 - 2 )
200h
Core Registers
(Ta b l e 3 - 2 )
280h
Core Registers
(Ta b l e 3 - 2 )
300h
Core Registers
(Ta b l e 3 - 2 )
380h
Core Registers
(Ta b l e 3 - 2 )
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh ODCONB 30Dh SLRCONB 38Dh INLVLB
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC
00Fh —08Fh—10FhCMOUT18Fh—20Fh—28Fh—30Fh—38Fh—
010h —090h— 110h CM1CON0 190h —210h—290h—310h—390h—
011h PIR1 091h PIE1 111h CM1CON1 191h PMADRL 211h SSP1BUF 291h CCPR1L 311h —391hIOCAP
012h PIR2 092h PIE2 112h CM1NSEL 192h PMADRH 212h SSP1ADD 292h CCPR1H 312h — 392h IOCAN
013h PIR3 093h PIE3 113h CM1PSEL 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h — 393h IOCAF
014h PIR4 094h PIE4 114h CM2CON0 194h PMDATH 214h SSP1STAT 294h CCP1CAP 314h —394hIOCBP
015h TMR0 095h OPTION_REG 115h CM2CON1 195h PMCON1 215h SSP1CON1 295h —315h— 395h IOCBN
016h TMR1L 096h PCON 116h CM2NSEL 196h PMCON2 216h SSP1CON2 296h —316h— 396h IOCBF
017h TMR1H 097h WDTCON 117h CM2PSEL 197h VREGCON(1) 217h SSP1CON3 297h —317h— 397h IOCCP
018h T1CON 098h OSCTUNE 118h CM3CON0 198h —218h— 298h CCPR2L 318h — 398h IOCCN
019h T1GCON 099h OSCCON 119h CM3CON1 199h RC1REG 219h — 299h CCPR2H 319h — 399h IOCCF
01Ah T2TMR 09Ah OSCSTAT 11Ah CM3NSEL 19Ah TX1REG 21Ah — 29Ah CCP2CON 31Ah —39Ah—
01Bh T2PR 09Bh ADRESL 11Bh CM3PSEL 19Bh SP1BRGL 21Bh — 29Bh CCP2CAP 31Bh MD2CON0 39Bh MD1CON0
01Ch T2CON 09Ch ADRESH 11Ch CM4CON0 19Ch SP1BRGH 21Ch —29Ch— 31Ch MD2CON1 39Ch MD1CON1
01Dh T2HLT 09Dh ADCON0 11Dh CM4CON1 19Dh RC1STA 21Dh BORCON 29Dh — 31Dh MD2SRC 39Dh MD1SRC
01Eh T2CLKCON 09Eh ADCON1 11Eh CM4NSEL 19Eh TX1STA 21Eh FVRCON 29Eh CCPTMRS 31Eh MD2CARL 39Eh MD1CARL
01Fh T2RST 09Fh ADCON2 11Fh CM4PSEL 19Fh BAUD1CON 21Fh ZCD1CON 29Fh — 31Fh MD2CARH 39Fh MD1CARH
020h
General
Purpose
Register
80 Bytes
0A0h
General
Purpose
Register
80 Bytes
120h
General
Purpose
Register
80 Bytes
1A0h
General
Purpose
Register
80 Bytes
220h
General
Purpose
Register
80 Bytes
2A0h
General
Purpose
Register
80 Bytes
320h
General
Purpose
Register
80 Bytes
3A0h
General
Purpose
Register
80 Bytes
06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh
070h
Common RAM
70h – 7Fh
0F0h
Accesses
70h-7Fh
170h
Accesses
70h-7Fh
1F0h
Accesses
70h-7Fh
270h
Accesses
70h-7Fh
2F0h
Accesses
70h-7Fh
370h
Accesses
70h-7Fh
3F0h
Accesses
70h-7Fh
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
PIC16(L)F1764/5/8/9
DS40001775D-page 33 2014-2018 Microchip Technology Inc.
TABLE 3-7: PIC16(L)F1764 MEMORY MAP (BANKS 8-23)
BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15
400h
40Bh
Core Registers
(Ta b l e 3 - 2 )
480h
48Bh
Core Registers
(Ta b l e 3 - 2 )
500h
50Bh
Core Registers
(Ta b l e 3 - 2 )
580h
58Bh
Core Registers
(Ta b l e 3 - 2 )
600h
60Bh
Core Registers
(Ta b l e 3 - 2 )
680h
68Bh
Core Registers
(Ta b l e 3 - 2 )
700h
70Bh
Core Registers
(Ta b l e 3 - 2 )
780h
78Bh
Core Registers
(Ta b l e 3 - 2 )
40Ch —48Ch—50Ch—58Ch—60Ch—68Ch—70Ch—78Ch—
40Dh —48Dh—50Dh—58Dh—60Dh— 68Dh COG1PHR 70Dh COG2PHR 78Dh —
40Eh HIDRVC 48Eh —50Eh—58Eh—60Eh— 68Eh COG1PHF 70Eh COG2PHF 78Eh —
40Fh —48Fh— 50Fh OPA1NCHS 58Fh — 60Fh — 68Fh COG1BLKR 70Fh COG2BLKR 78Fh —
410h —490h— 510h OPA1PCHS 590h DACLD 610h — 690h COG1BLKF 710h COG2BLKF 790h —
411h —491h— 511h OPA1CON 591h DAC1CON0 611h — 691h COG1DBR 711h COG2DBR 791h —
412h —492h— 512h OPA1ORS 592h DAC1REFL 612h — 692h COG1DBF 712h COG2DBF 792h —
413h T4TMR 493h TMR3L 513h — 593h DAC1REFH 613h — 693h COG1CON0 713h COG2CON0 793h —
414h T4PR 494h TMR3H 514h —594h— 614h — 694h COG1CON1 714h COG2CON1 794h PRG1RTSS
415h T4CON 495h T3CON 515h —595h— 615h — 695h COG1RIS0 715h COG2RIS0 795h PRG1FTSS
416h T4HLT 496h T3GCON 516h —596h— 616h — 696h COG1RIS1 716h COG2RIS1 796h PRG1INS
417h T4CLKCON 497h —517h— 597h DAC3CON0 617h PWM3DCL 697h COG1RSIM0 717h COG2RSIM0 797h PRG1CON0
418h T4RST 498h —518h— 598h DAC3REF 618h PWM3DCH 698h COG1RSIM1 718h COG2RSIM1 798h PRG1CON1
419h —499h—519h—599h— 619h PWM3CON 699h COG1FIS0 719h COG2FIS0 799h PRG1CON2
41Ah T6TMR 49Ah TMR5L 51Ah —59Ah—61Ah— 69Ah COG1FIS1 71Ah COG2FIS1 79Ah —
41Bh T6PR 49Bh TMR5H 51Bh —59Bh—61Bh— 69Bh COG1FSIM0 71Bh COG2FSIM0 79Bh —
41Ch T6CON 49Ch T5CON 51Ch —59Ch—61Ch— 69Ch COG1FSIM1 71Ch COG2FSIM1 79Ch —
41Dh T6HLT 49Dh T5GCON 51Dh —59Dh—61Dh— 69DhCOG1ASD071DhCOG2ASD079Dh —
41Eh T6CLKCON 49Eh —51Eh—59Eh—61Eh— 69Eh COG1ASD1 71Eh COG2ASD1 79Eh —
41Fh T6RST 49Fh —51Fh—59Fh— 61Fh — 69Fh COG1STR 71Fh COG2STR 79Fh —
420h
Unimplemented
Read as ‘0’
4A0h
Unimplemented
Read as ‘0’
520h
Unimplemented
Read as ‘0’
5A0h
Unimplemented
Read as ‘0’
620h
Unimplemented
Read as ‘0’
6A0h
Unimplemented
Read as ‘0’
720h
Unimplemented
Read as ‘0’
7A0h
Unimplemented
Read as ‘0’
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h
Accesses
70h-7Fh
4F0h
Accesses
70h-7Fh
570h
Accesses
70h-7Fh
5F0h
Accesses
70h-7Fh
670h
Accesses
70h-7Fh
6F0h
Accesses
70h-7Fh
770h
Accesses
70h-7Fh
7F0h
Accesses
70h-7Fh
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh
BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23
800h
80Bh
Core Registers
(Ta b l e 3 - 2 )
880h
88Bh
Core Registers
(Ta b l e 3 - 2 )
900h
90Bh
Core Registers
(Ta b l e 3 - 2 )
980h
98Bh
Core Registers
(Ta b l e 3 - 2 )
A00h
A0Bh
Core Registers
(Ta b l e 3 - 2 )
A80h
A8Bh
Core Registers
(Ta b l e 3 - 2 )
B00h
B0Bh
Core Registers
(Ta b l e 3 - 2 )
B80h
B8Bh
Core Registers
(Ta b l e 3 - 2 )
80Ch
Unimplemented
Read as ‘0’
88Ch
Unimplemented
Read as ‘0’
90Ch
Unimplemented
Read as ‘0’
98Ch
Unimplemented
Read as ‘0’
A0Ch
Unimplemented
Read as ‘0’
A8Ch
Unimplemented
Read as ‘0’
B0Ch
Unimplemented
Read as ‘0’
B8Ch
Unimplemented
Read as ‘0’
86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh
870h
Accesses
70h-7Fh
8F0h
Accesses
70h-7Fh
970h
Accesses
70h-7Fh
9F0h
Accesses
70h-7Fh
A70h
Accesses
70h-7Fh
AF0h
Accesses
70h-7Fh
B70h
Accesses
70h-7Fh
BF0h
Accesses
70h-7Fh
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
Legend: = Unimplemented data memory locations, read as ‘0’.
2014-2018 Microchip Technology Inc. DS40001775D-page 34
PIC16(L)F1764/5/8/9
TABLE 3-8: PIC16(L)F1765 MEMORY MAP (BANKS 8-23)
BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15
400h
40Bh
Core Registers
(Table 3-2)
480h
48Bh
Core Registers
(Ta b l e 3 - 2 )
500h
50Bh
Core Registers
(Table 3-2)
580h
58Bh
Core Registers
(Ta b l e 3 - 2 )
600h
60Bh
Core Registers
(Table 3-2)
680h
68Bh
Core Registers
(Table 3-2)
700h
70Bh
Core Registers
(Ta b l e 3 - 2 )
780h
78Bh
Core Registers
(Table 3-2)
40Ch —48Ch— 50Ch —58Ch—60Ch—68Ch—70Ch— 78Ch —
40Dh —48Dh— 50Dh —58Dh—60Dh— 68Dh COG1PHR 70Dh COG2PHR 78Dh —
40Eh HIDRVC 48Eh —50Eh— 58Eh —60Eh— 68Eh COG1PHF 70Eh COG2PHF 78Eh —
40Fh —48Fh— 50Fh OPA1NCHS 58Fh — 60Fh — 68Fh COG1BLKR 70Fh COG2BLKR 78Fh —
410h —490h— 510h OPA1PCHS 590h DACLD 610h — 690h COG1BLKF 710h COG2BLKF 790h —
411h —491h— 511h OPA1CON 591h DAC1CON0 611h — 691h COG1DBR 711h COG2DBR 791h —
412h —492h— 512h OPA1ORS 592h DAC1REFL 612h — 692h COG1DBF 712h COG2DBF 792h —
413h T4TMR 493h TMR3L 513h — 593h DAC1REFH 613h — 693h COG1CON0 713h COG2CON0 793h —
414h T4PR 494h TMR3H 514h —594h— 614h — 694h COG1CON1 714h COG2CON1 794h PRG1RTSS
415h T4CON 495h T3CON 515h —595h— 615h — 695h COG1RIS0 715h COG2RIS0 795h PRG1FTSS
416h T4HLT 496h T3GCON 516h —596h— 616h — 696h COG1RIS1 716h COG2RIS1 796h PRG1INS
417h T4CLKCON 497h —517h— 597h DAC3CON0 617h PWM3DCL 697h COG1RSIM0 717h COG2RSIM0 797h PRG1CON0
418h T4RST 498h —518h— 598h DAC3REF 618h PWM3DCH 698h COG1RSIM1 718h COG2RSIM1 798h PRG1CON1
419h —499h—519h—599h— 619h PWM3CON 699h COG1FIS0 719h COG2FIS0 799h PRG1CON2
41Ah T6TMR 49Ah TMR5L 51Ah — 59Ah —61Ah— 69Ah COG1FIS1 71Ah COG2FIS1 79Ah —
41Bh T6PR 49Bh TMR5H 51Bh — 59Bh —61Bh— 69Bh COG1FSIM0 71Bh COG2FSIM0 79Bh —
41Ch T6CON 49Ch T5CON 51Ch —59Ch—61Ch— 69Ch COG1FSIM1 71Ch COG2FSIM1 79Ch —
41Dh T6HLT 49Dh T5GCON 51Dh —59Dh—61Dh— 69Dh COG1ASD0 71Dh COG2ASD0 79Dh —
41Eh T6CLKCON 49Eh —51Eh— 59Eh —61Eh— 69Eh COG1ASD1 71Eh COG2ASD1 79Eh —
41Fh T6RST 49Fh —51Fh—59Fh— 61Fh — 69Fh COG1STR 71Fh COG2STR 79Fh —
420h
General
Purpose
Register
80 Bytes
4A0h
General
Purpose
Register
80 Bytes
520h
General
Purpose
Register
80 Bytes
5A0h
General
Purpose
Register
80 Bytes
620h General Purpose
Register 48 Bytes
6A0h
Unimplemented
Read as ‘0’
720h
Unimplemented
Read as ‘0’
7A0h
Unimplemented
Read as ‘0’
64Fh
650h Unimplemented
Read as ‘0’
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h
Accesses
70h-7Fh
4F0h
Accesses
70h-7Fh
570h
Accesses
70h-7Fh
5F0h
Accesses
70h-7Fh
670h
Accesses
70h-7Fh
6F0h
Accesses
70h-7Fh
770h
Accesses
70h-7Fh
7F0h
Accesses
70h-7Fh
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh
BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23
800h
80Bh
Core Registers
(Table 3-2)
880h
88Bh
Core Registers
(Ta b l e 3 - 2 )
900h
90Bh
Core Registers
(Table 3-2)
980h
98Bh
Core Registers
(Ta b l e 3 - 2 )
A00h
A0Bh
Core Registers
(Table 3-2)
A80h
A8Bh
Core Registers
(Table 3-2)
B00h
B0Bh
Core Registers
(Ta b l e 3 - 2 )
B80h
B8Bh
Core Registers
(Table 3-2)
80Ch
Unimplemented
Read as ‘0’
88Ch
Unimplemented
Read as ‘0’
90Ch
Unimplemented
Read as ‘0’
98Ch
Unimplemented
Read as ‘0’
A0Ch
Unimplemented
Read as ‘0’
A8Ch
Unimplemented
Read as ‘0’
B0Ch
Unimplemented
Read as ‘0’
B8Ch
Unimplemented
Read as ‘0’
86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh
870h Accesses
70h-7Fh
8F0h Accesses
70h-7Fh
970h Accesses
70h-7Fh
9F0h Accesses
70h-7Fh
A70h Accesses
70h-7Fh
AF0h Accesses
70h-7Fh
B70h Accesses
70h-7Fh
BF0h Accesses
70h-7Fh
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
Legend: = Unimplemented data memory locations, read as ‘0’.
PIC16(L)F1764/5/8/9
DS40001775D-page 35 2014-2018 Microchip Technology Inc.
TABLE 3-9: PIC16(L)F1768 MEMORY MAP (BANKS 8-23)
BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15
400h
40Bh
Core Registers
(Ta b l e 3 - 2 )
480h
48Bh
Core Registers
(Ta b l e 3 - 2 )
500h
50Bh
Core Registers
(Ta b l e 3 - 2 )
580h
58Bh
Core Registers
(Table 3-2)
600h
60Bh
Core Registers
(Table 3-2)
680h
68Bh
Core Registers
(Table 3-2)
700h
70Bh
Core Registers
(Table 3-2)
780h
78Bh
Core Registers
(Table 3-2)
40Ch —48Ch—50Ch—58Ch—60Ch—68Ch— 70Ch — 78Ch —
40Dh —48Dh—50Dh—58Dh—60Dh— 68Dh COG1PHR 70Dh COG2PHR 78Dh —
40Eh HIDRVC 48Eh — 50Eh — 58Eh — 60Eh — 68Eh COG1PHF 70Eh COG2PHF 78Eh —
40Fh —48Fh— 50Fh OPA1NCHS 58Fh —60Fh— 68Fh COG1BLKR 70Fh COG2BLKR 78Fh —
410h —490h— 510h OPA1PCHS 590h DACLD 610h — 690h COG1BLKF 710h COG2BLKF 790h —
411h —491h— 511h OPA1CON 591h DAC1CON0 611h — 691h COG1DBR 711h COG2DBR 791h —
412h —492h— 512h OPA1ORS 592h DAC1REFL 612h — 692h COG1DBF 712h COG2DBF 792h —
413h T4TMR 493h TMR3L 513h OPA2NCHS 593h DAC1REFH 613h — 693h COG1CON0 713h COG2CON0 793h —
414h T4PR 494h TMR3H 514h OPA2PCHS 594h DAC2CON0 614h — 694h COG1CON1 714h COG2CON1 794h PRG1RTSS
415h T4CON 495h T3CON 515h OPA2CON 595h DAC2REFL 615h — 695h COG1RIS0 715h COG2RIS0 795h PRG1FTSS
416h T4HLT 496h T3GCON 516h OPA2ORS 596h DAC2REFH 616h — 696h COG1RIS1 716h COG2RIS1 796h PRG1INS
417h T4CLKCON 497h —517h— 597h DAC3CON0 617h PWM3DCL 697h COG1RSIM0 717h COG2RSIM0 797h PRG1CON0
418h T4RST 498h —518h— 598h DAC3REF 618h PWM3DCH 698h COG1RSIM1 718h COG2RSIM1 798h PRG1CON1
419h —499h—519h— 599h DAC4CON0 619h PWM3CON 699h COG1FIS0 719h COG2FIS0 799h PRG1CON2
41Ah T6TMR 49Ah TMR5L 51Ah — 59Ah DAC4REF 61Ah PWM4DCL 69Ah COG1FIS1 71Ah COG2FIS1 79Ah PRG2RTSS
41Bh T6PR 49Bh TMR5H 51Bh — 59Bh — 61Bh PWM4DCH 69Bh COG1FSIM0 71Bh COG2FSIM0 79Bh PRG2FTSS
41Ch T6CON 49Ch T5CON 51Ch —59Ch— 61Ch PWM4CON 69Ch COG1FSIM1 71Ch COG2FSIM1 79Ch PRG2INS
41Dh T6HLT 49Dh T5GCON 51Dh —59Dh—61Dh— 69Dh COG1ASD0 71Dh COG2ASD0 79Dh PRG2CON0
41Eh T6CLKCON 49Eh — 51Eh — 59Eh — 61Eh — 69Eh COG1ASD1 71Eh COG2ASD1 79Eh PRG2CON1
41Fh T6RST 49Fh —51Fh—59Fh—61Fh— 69Fh COG1STR 71Fh COG2STR 79Fh PRG2CON2
420h
Unimplemented
Read as ‘0’
4A0h
Unimplemented
Read as ‘0’
520h
Unimplemented
Read as ‘0’
5A0h
Unimplemented
Read as ‘0’
620h
Unimplemented
Read as ‘0’
6A0h
Unimplemented
Read as ‘0’
720h
Unimplemented
Read as ‘0’
7A0h
Unimplemented
Read as ‘0’
46Fh4EFh56Fh5EFh66Fh6EFh76Fh7EFh
470h
Accesses
70h-7Fh
4F0h
Accesses
70h-7Fh
570h
Accesses
70h-7Fh
5F0h
Accesses
70h-7Fh
670h
Accesses
70h-7Fh
6F0h
Accesses
70h-7Fh
770h
Accesses
70h-7Fh
7F0h
Accesses
70h-7Fh
47Fh4FFh57Fh5FFh67Fh6FFh77Fh7FFh
BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23
800h
80Bh
Core Registers
(Ta b l e 3 - 2 )
880h
88Bh
Core Registers
(Ta b l e 3 - 2 )
900h
90Bh
Core Registers
(Ta b l e 3 - 2 )
980h
98Bh
Core Registers
(Table 3-2)
A00h
A0Bh
Core Registers
(Table 3-2)
A80h
A8Bh
Core Registers
(Table 3-2)
B00h
B0Bh
Core Registers
(Table 3-2)
B80h
B8Bh
Core Registers
(Table 3-2)
80Ch
Unimplemented
Read as ‘0’
88Ch
Unimplemented
Read as ‘0’
90Ch
Unimplemented
Read as ‘0’
98Ch
Unimplemented
Read as ‘0’
A0Ch
Unimplemented
Read as ‘0’
A8Ch
Unimplemented
Read as ‘0’
B0Ch
Unimplemented
Read as ‘0’
B8Ch
Unimplemented
Read as ‘0’
86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh
870h
Accesses
70h-7Fh
8F0h
Accesses
70h-7Fh
970h
Accesses
70h-7Fh
9F0h
Accesses
70h-7Fh
A70h
Accesses
70h-7Fh
AF0h
Accesses
70h-7Fh
B70h
Accesses
70h-7Fh
BF0h
Accesses
70h-7Fh
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
Legend: = Unimplemented data memory locations, read as ‘0’.
2014-2018 Microchip Technology Inc. DS40001775D-page 36
PIC16(L)F1764/5/8/9
TABLE 3-10: PIC16(L)F1769 MEMORY MAP (BANKS 8-23)
BANK 8 BANK 9 BANK 10 BANK 1 1 BANK 12 BANK 13 BANK 14 BANK 15
400h
40Bh
Core Registers
(Table 3-2)
480h
48Bh
Core Registers
(Ta b l e 3 - 2 )
500h
50Bh
Core Registers
(Table 3-2)
580h
58Bh
Core Registers
(Ta b l e 3 - 2 )
600h
60Bh
Core Registers
(Table 3-2)
680h
68Bh
Core Registers
(Ta b l e 3 - 2 )
700h
70Bh
Core Registers
(Table 3-2)
780h
78Bh
Core Registers
(Ta b l e 3 - 2 )
40Ch —48Ch—50Ch— 58Ch —60Ch— 68Ch —70Ch— 78Ch —
40Dh —48Dh—50Dh— 58Dh —60Dh— 68Dh COG1PHR 70Dh COG2PHR 78Dh —
40Eh HIDRVC 48Eh — 50Eh —58Eh— 60Eh — 68Eh COG1PHF 70Eh COG2PHF 78Eh —
40Fh — 48Fh — 50Fh OPA1NCHS 58Fh —60Fh— 68Fh COG1BLKR 70Fh COG2BLKR 78Fh —
410h — 490h — 510h OPA1PCHS 590h DACLD 610h — 690h COG1BLKF 710h COG2BLKF 790h —
411h — 491h — 511h OPA1CON 591h DAC1CON0 611h — 691h COG1DBR 711h COG2DBR 791h —
412h — 492h — 512h OPA1ORS 592h DAC1REFL 612h — 692h COG1DBF 712h COG2DBF 792h —
413h T4TMR 493h TMR3L 513h OPA2NCHS 593h DAC1REFH 613h — 693h COG1CON0 713h COG2CON0 793h —
414h T4PR 494h TMR3H 514h OPA2PCHS 594h DAC2CON0 614h — 694h COG1CON1 714h COG2CON1 794h PRG1RTSS
415h T4CON 495h T3CON 515h OPA2CON 595h DAC2REFL 615h — 695h COG1RIS0 715h COG2RIS0 795h PRG1FTSS
416h T4HLT 496h T3GCON 516h OPA2ORS 596h DAC2REFH 616h — 696h COG1RIS1 716h COG2RIS1 796h PRG1INS
417h T4CLKCON 497h —517h— 597h DAC3CON0 617h PWM3DCL 697h COG1RSIM0 717h COG2RSIM0 797h PRG1CON0
418h T4RST 498h —518h— 598h DAC3REF 618h PWM3DCH 698h COG1RSIM1 718h COG2RSIM1 798h PRG1CON1
419h — 499h —519h— 599h DAC4CON0 619h PWM3CON 699h COG1FIS0 719h COG2FIS0 799h PRG1CON2
41Ah T6TMR 49Ah TMR5L 51Ah — 59Ah DAC4REF 61Ah PWM4DCL 69Ah COG1FIS1 71Ah COG2FIS1 79Ah PRG2RTSS
41Bh T6PR 49Bh TMR5H 51Bh —59Bh— 61Bh PWM4DCH 69Bh COG1FSIM0 71Bh COG2FSIM0 79Bh PRG2FTSS
41Ch T6CON 49Ch T5CON 51Ch — 59Ch — 61Ch PWM4CON 69Ch COG1FSIM1 71Ch COG2FSIM1 79Ch PRG2INS
41Dh T6HLT 49Dh T5GCON 51Dh — 59Dh —61Dh— 69Dh COG1ASD0 71Dh COG2ASD0 79Dh PRG2CON0
41Eh T6CLKCON 49Eh — 51Eh —59Eh— 61Eh — 69Eh COG1ASD1 71Eh COG2ASD1 79Eh PRG2CON1
41Fh T6RST 49Fh —51Fh—59Fh—61Fh— 69Fh COG1STR 71Fh COG2STR 79Fh PRG2CON2
420h
General
Purpose
Register
80 Bytes
4A0h
General
Purpose
Register
80 Bytes
520h
General
Purpose
Register
80 Bytes
5A0h
General
Purpose
Register
80 Bytes
620h General Purpose
Register 48 Bytes
6A0h
Unimplemented
Read as ‘0’
720h
Unimplemented
Read as ‘0’
7A0h
Unimplemented
Read as ‘0’
64Fh
650h Unimplemented
Read as ‘0’
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h
Accesses
70h-7Fh
4F0h
Accesses
70h-7Fh
570h
Accesses
70h-7Fh
5F0h
Accesses
70h-7Fh
670h
Accesses
70h-7Fh
6F0h
Accesses
70h-7Fh
770h
Accesses
70h-7Fh
7F0h
Accesses
70h-7Fh
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh
BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23
800h
80Bh
Core Registers
(Table 3-2)
880h
88Bh
Core Registers
(Ta b l e 3 - 2 )
900h
90Bh
Core Registers
(Table 3-2)
980h
98Bh
Core Registers
(Ta b l e 3 - 2 )
A00h
A0Bh
Core Registers
(Table 3-2)
A80h
A8Bh
Core Registers
(Ta b l e 3 - 2 )
B00h
B0Bh
Core Registers
(Table 3-2)
B80h
B8Bh
Core Registers
(Ta b l e 3 - 2 )
80Ch
Unimplemented
Read as ‘0’
88Ch
Unimplemented
Read as ‘0’
90Ch
Unimplemented
Read as ‘0’
98Ch
Unimplemented
Read as ‘0’
A0Ch
Unimplemented
Read as ‘0’
A8Ch
Unimplemented
Read as ‘0’
B0Ch
Unimplemented
Read as ‘0’
B8Ch
Unimplemented
Read as ‘0’
86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh
870h
Accesses
70h-7Fh
8F0h
Accesses
70h-7Fh
970h
Accesses
70h-7Fh
9F0h
Accesses
70h-7Fh
A70h
Accesses
70h-7Fh
AF0h
Accesses
70h-7Fh
B70h
Accesses
70h-7Fh
BF0h
Accesses
70h-7Fh
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
Legend: = Unimplemented data memory locations, read as ‘0’.
PIC16(L)F1764/5/8/9
DS40001775D-page 37 2014-2018 Microchip Technology Inc.
TABLE 3-11: PIC16(L)F1764/5/8/9 MEMORY MAP (BANKS 24-31)
BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31
C00h
C0Bh
Core Registers
(Ta b l e 3 - 2 )
C80h
C8Bh
Core Registers
(Ta b l e 3 - 2 )
D00h
D0Bh
Core Registers
(Ta b l e 3 - 2 )
D80h
D8Bh
Core Registers
(Ta b l e 3 - 2 )
E00h
E0Bh
Core Registers
(Ta b l e 3 - 2 )
E80h
E8Bh
Core Registers
(Ta b l e 3 - 2 )
F00h
F0Bh
Core Registers
(Ta b l e 3 - 2 )
F80h
F8Bh
Core Registers
(Ta b l e 3 - 2 )
C0Ch —C8Ch—D0Ch—
See Ta b le 3 - 12
and Table 3-13
for Register
Mapping Details
See Ta b le 3 - 12
and Table 3-13
for Register
Mapping Details
See Ta b le 3 - 12
and Table 3-13
for Register
Mapping Details
See Ta b le 3 - 12
and Table 3-13
for Register
Mapping Details
See Ta b le 3 - 14
for Register
Mapping Details
C0Dh —C8Dh—D0Dh—
C0Eh —C8Eh—D0Eh—
C0Fh —C8Fh—D0Fh—
C10h —C90h—D10h—
C11h —C91h—D11h—
C12h —C92h—D12h—
C13h —C93h—D13h—
C14h —C94h—D14h—
C15h —C95h—D15h—
C16h —C96h—D16h—
C17h —C97h—D17h—
C18h —C98h—D18h—
C19h —C99h—D19h—
C1Ah —C9Ah—D1Ah—
C1Bh —C9Bh—D1Bh—
C1Ch —C9Ch—D1Ch—
C1Dh —C9Dh—D1Dh—
C1Eh —C9Eh—D1Eh—
C1Fh —C9Fh—D1Fh—
C20h
Unimplemented
Read as ‘0’
CA0h
Unimplemented
Read as ‘0’
D20h
Unimplemented
Read as ‘0’
C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh
C70h
Accesses
70h-7Fh
CF0h
Accesses
70h-7Fh
D70h
Accesses
70h-7Fh
DF0h
Accesses
70h-7Fh
E70h
Accesses
70h-7Fh
EF0h
Accesses
70h-7Fh
F70h
Accesses
70h-7Fh
FF0h
Accesses
70h-7Fh
CFFh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh
Legend: = Unimplemented data memory locations, read as ‘0’.
2014-2018 Microchip Technology Inc. DS40001775D-page 38
PIC16(L)F1764/5/8/9
TABLE 3-12: PIC16(L)F1764/5 MEMORY MAP (BANKS 27-30)
Legend: = Unimplemented data memory locations, read as ‘0’,
Bank 27 Bank 28 Bank 29 Bank 30
D8Ch —E0Ch—E8Ch—F0Ch —
D8Dh —E0Dh—E8Dh—F0Dh —
D8Eh PWMEN E0Eh —E8Eh—F0Eh —
D8Fh PWMLD E0Fh PPSLOCK E8Fh — F0Fh CLCDATA
D90h PWMOUT E10h INTPPS E90h RA0PPS F10h CLC1CON
D91h PWM5PHL E11h T0CKIPPS E91h RA1PPS F11h CLC1POL
D92h PWM5PHH E12h T1CKIPPS E92h RA2PPS F12h CLC1SEL0
D93h PWM5DCL E13h T1GPPS E93h — F13h CLC1SEL1
D94h PWM5DCH E14h CCP1PPS E94h RA4PPS F14h CLC1SEL2
D95h PWM5PRL E15h — E95h RA5PPS F15h CLC1SEL3
D96h PWM5PRH E16h COG1INPPS E96h — F16h CLC1GLS0
D97h PWM5OFL E17h —E97h— F17h CLC1GLS1
D98h PWM5OFH E18h —E98h— F18h CLC1GLS2
D99h PWM5TMRL E19h T2INPPS E99h — F19h CLC1GLS3
D9Ah PWM5TMRH E1Ah T3CKIPPS E9Ah — F1Ah CLC2CON
D9Bh PWM5CON E1Bh T3GPPS E9Bh — F1Bh CLC2POL
D9Ch PWM5INTE E1Ch T4INPPS E9Ch — F1Ch CLC2SEL0
D9Dh PWM5INTF E1Dh T5CKIPPS E9Dh — F1Dh CLC2SEL1
D9Eh PWM5CLKCON E1Eh T5GPPS E9Eh — F1Eh CLC2SEL2
D9Fh PWM5LDCON E1Fh T6INPPS E9Fh — F1Fh CLC2SEL3
DA0h PWM5OFCON E20h SSPCLKPPS EA0h RC0PPS F20h CLC2GLS0
DA1h — E21h SSPDATPPS EA1h RC1PPS F21h CLC2GLS1
DA2h — E22h SSPSSPPS EA2h RC2PPS F22h CLC2GLS2
DA3h —E23h— EA3h RC3PPS F23h CLC2GLS3
DA4h — E24h RXPPS EA4h RC4PPS F24h CLC3CON
DA5h — E25h CKPPS EA5h RC5PPS F25h CLC3POL
DA6h —E26h— EA6h — F26h CLC3SEL0
DA7h —E27h— EA7h — F27h CLC3SEL1
DA8h — E28h CLCIN0PPS EA8h — F28h CLC3SEL2
DA9h — E29h CLCIN1PPS EA9h — F29h CLC3SEL3
DAAh — E2Ah CLCIN2PPS EAAh — F2Ah CLC3GLS0
DABh — E2Bh CLCIN3PPS EABh — F2Bh CLC3GLS1
DACh — E2Ch PRG1FPPS EACh — F2Ch CLC3GLS2
DADh — E2Dh PRG1RPPS EADh — F2Dh CLC3GLS3
DAEh —E2Eh— EAEh —F2Eh —
DAFh —E2Fh—EAFh—F2Fh —
DB0h — E30h MD1CHPPS EB0h —F30h —
DB1h — E31h MD1CLPPS EB1h —F31h —
DB2h — E32h MD1MODPPS EB2h —F32h —
DB3h —E33h— EB3h —F33h —
DB4h —E34h— EB4h —F34h —
DB5h —E35h— EB5h —F35h —
DB6h —E36h— EB6h —F36h —
DB7h —E37h— EB7h —F37h —
DB8h —E38h— EB8h —F38h —
DB9h —E39h— EB9h —F39h —
DBAh —E3Ah— EBAh —F3Ah —
DBBh —E3Bh— EBBh —F3Bh —
DBCh —E3Ch— EBCh —F3Ch —
DBDh —E3Dh— EBDh —F3Dh —
DBEh —E3Eh— EBEh —F3Eh —
DBFh —E3Fh— EBFh —F3Fh —
DC0h
—
E40h
—
EC0h
—
F40h
—
DEFh E6Fh EEFh F6Fh
2014-2018 Microchip Technology Inc. DS40001775D-page 39
PIC16(L)F1764/5/8/9
TABLE 3-13: PIC16(L)F1768/9 MEMORY MAP (BANKS 27-30)
Legend: = Unimplemented data memory locations, read as ‘0’,
Bank 27 Bank 28 Bank 29 Bank 30
D8Ch —E0Ch—E8Ch—F0Ch —
D8Dh —E0Dh—E8Dh—F0Dh —
D8Eh PWMEN E0Eh —E8Eh—F0Eh —
D8Fh PWMLD E0Fh PPSLOCK E8Fh — F0Fh CLCDATA
D90h PWMOUT E10h INTPPS E90h RA0PPS F10h CLC1CON
D91h PWM5PHL E11h T0CKIPPS E91h RA1PPS F11h CLC1POL
D92h PWM5PHH E12h T1CKIPPS E92h RA2PPS F12h CLC1SEL0
D93h PWM5DCL E13h T1GPPS E93h — F13h CLC1SEL1
D94h PWM5DCH E14h CCP1PPS E94h RA4PPS F14h CLC1SEL2
D95h PWM5PRL E15h CCP2PPS E95h RA5PPS F15h CLC1SEL3
D96h PWM5PRH E16h COG1INPPS E96h — F16h CLC1GLS0
D97h PWM5OFL E17h COG2INPPS E97h — F17h CLC1GLS1
D98h PWM5OFH E18h —E98h— F18h CLC1GLS2
D99h PWM5TMRL E19h T2INPPS E99h — F19h CLC1GLS3
D9Ah PWM5TMRH E1Ah T3CKIPPS E9Ah — F1Ah CLC2CON
D9Bh PWM5CON E1Bh T3GPPS E9Bh — F1Bh CLC2POL
D9Ch PWM5INTE E1Ch T4INPPS E9Ch RB4PPS F1Ch CLC2SEL0
D9Dh PWM5INTF E1Dh T5CKIPPS E9Dh RB5PPS F1Dh CLC2SEL1
D9Eh PWM5CLKCON E1Eh T5GPPS E9Eh RB6PPS F1Eh CLC2SEL2
D9Fh PWM5LDCON E1Fh T6INPPS E9Fh RB7PPS F1Fh CLC2SEL3
DA0h PWM5OFCON E20h SSPCLKPPS EA0h RC0PPS F20h CLC2GLS0
DA1h PWM6PHL E21h SSPDATPPS EA1h RC1PPS F21h CLC2GLS1
DA2h PWM6PHH E22h SSPSSPPS EA2h RC2PPS F22h CLC2GLS2
DA3h PWM6DCL E23h — EA3h RC3PPS F23h CLC2GLS3
DA4h PWM6DCH E24h RXPPS EA4h RC4PPS F24h CLC3CON
DA5h PWM6PRL E25h CKPPS EA5h RC5PPS F25h CLC3POL
DA6h PWM6PRH E26h — EA6h RC6PPS F26h CLC3SEL0
DA7h PWM6OFL E27h — EA7h RC7PPS F27h CLC3SEL1
DA8h PWM6OFH E28h CLCIN0PPS EA8h — F28h CLC3SEL2
DA9h PWM6TMRL E29h CLCIN1PPS EA9h — F29h CLC3SEL3
DAAh PWM6TMRH E2Ah CLCIN2PPS EAAh — F2Ah CLC3GLS0
DABh PWM6CON E2Bh CLCIN3PPS EABh — F2Bh CLC3GLS1
DACh PWM6INTE E2Ch PRG1FPPS EACh — F2Ch CLC3GLS2
DADh PWM6INTF E2Dh PRG1RPPS EADh — F2Dh CLC3GLS3
DAEh PWM6CLKCON E2Eh PRG2FPPS EAEh —F2Eh —
DAFh PWM6LDCON E2Fh PRG2RPPS EAFh —F2Fh —
DB0h PWM6OFCON E30h MD1CHPPS EB0h —F30h —
DB1h — E31h MD1CLPPS EB1h —F31h —
DB2h — E32h MD1MODPPS EB2h —F32h —
DB3h — E33h MD2CHPPS EB3h —F33h —
DB4h — E34h MD2CLPPS EB4h —F34h —
DB5h — E35h MD2MODPPS EB5h —F35h —
DB6h — E36h —EB6h—F36h —
DB7h —E37h—EB7h—F37h —
DB8h —E38h— EB8h —F38h —
DB9h — E39h — EB9h —F39h —
DBAh —E3Ah— EBAh —F3Ah —
DBBh —E3Bh— EBBh —F3Bh —
DBCh —E3Ch—EBCh—F3Ch —
DBDh —E3Dh— EBDh —F3Dh —
DBEh —E3Eh— EBEh —F3Eh —
DBFh —E3Fh— EBFh —F3Fh —
DC0h
—
E40h
—
EC0h
—
F40h
—
DEFh E6Fh EEFh F6Fh
2014-2018 Microchip Technology Inc. DS40001775D-page 40
PIC16(L)F1764/5/8/9
TABLE 3-14: PIC16(L)F1764/5/8/9 MEMORY MAP (BANK 31)
Legend: = Unimplemented data memory locations, read as ‘0’,
Bank 31
F8Ch Unimplemented
Read as ‘0’
FE3h
FE4h STATUS_SHAD
FE5h WREG_SHAD
FE6h BSR_SHAD
FE7h PCLATH_SHAD
FE8h FSR0L_SHAD
FE9h FSR0H_SHAD
FEAh FSR1L_SHAD
FEBh FSR1H_SHAD
FECh —
FEDh STKPTR
FEEh TOSL
FEFh TOSH
2014-2018 Microchip Technology Inc. DS40001775D-page 41
PIC16(L)F1764/5/8/9
3.3.6 CORE FUNCTION REGISTERS
SUMMARY
The core function registers listed in Table 3-15 can be
addressed from any bank.
TABLE 3-15: CORE FUNCTION REGISTERS SUMMARY(1)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
All Other
Resets
Bank 0-31
x00h or
x80h INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register) xxxx xxxx uuuu uuuu
x01h or
x81h INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register) xxxx xxxx uuuu uuuu
x02h or
x82h PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x03h or
x83h STATUS — — —TOPD ZDCC---1 1000 ---q quuu
x04h or
x84h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
x05h or
x85h FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x06h or
x86h FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
x07h or
x87h FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
x08h or
x88h BSR — — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000
x09h or
x89h WREG Working Register 0000 0000 uuuu uuuu
x0Ah or
x8Ah PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
x0Bh or
x8Bh INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
Legend: x = unknown; u = unchanged; q = value depends on condition; - = unimplemented, read as ‘0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2014-2018 Microchip Technology Inc. DS40001775D-page 42
PIC16(L)F1764/5/8/9
TABLE 3-16: SPECIAL FUNCTION REGISTER SUMMARY
Add r Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
All O ther
Resets
B ank 0
00Ch PORTA —— RA<5:0>
--xx xxxx --uu uuuu
00Dh PORTB
(2)
RB<7:4> — — — —
xxxx ---- uuuu ----
00Eh PORTC RC<7:6>
(2)
RC<5:0>
xxxx xxxx uuuu uuuu
00Fh —Unimplemented — —
010h —Unimplemented — —
011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
0000 0000 0000 0000
012h PIR2 OSFIF C2IF C1IF — BCL1IF C4IF
(2)
C3IF
(2)
CCP2IF
(2)
000- 0000 000- 0000
013h PIR3 PWM6IF
(2)
PWM5IF COG1IF ZCDIF COG2IF
(2)
CLC3IF CLC2IF CLC1IF
0000 0000 0000 0000
014h PIR4 —— TMR5GIF TMR5IF TMR3GIF TMR3IF TMR6IF TRM4IF
--00 0000 --00 0000
015h TMR0 Timer0 Module Register
0000 0000 0000 0000
016h TMR1L Holding Register for the Least Significant Byte of the 16-Bit TMR1 Register
xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-Bit TMR1 Register
xxxx xxxx uuuu uuuu
018h T1CON CS<1:0> CKPS<1:0> OSCEN SYNC —ON
0000 00-0 uuuu uu-u
019h T1GCON GE GPOL GTM GSPM GGO/DONE GVAL GSS<1:0>
0000 0x00 uuuu uxuu
01Ah T2TMR Holding Register for the 8-Bit TMR2 Register
0000 0000 0000 0000
01Bh T2PR TMR2 Period Register
1111 1111 1111 1111
01Ch T2CON ON CKPS<2:0> OUTPS<3:0>
0000 0000 0000 0000
01Dh T2HLT PSYNC CKPOL CKSYNC MODE<4:0>
0000 0000 0000 0000
01Eh T2CLKCON — — — — CS<3:0>
---- 0000 ---- 0000
01Fh T2RST — — — — RSEL<3:0>
---- 0000 ---- 0000
B ank 1
08Ch TRISA —— TRISA<5:4> —
(1)
TRISA<2:0>
--11 1111 --11 1111
08Dh TRISB
(2)
TRISB<7:4> — — — —
1111 ---- 1111 ----
08Eh TRISC TRISC<7:6>
(2)
TRISC<5:0>
1111 1111 1111 1111
08Fh —Unimplemented — —
090h —Unimplemented — —
091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE
0000 0000 0000 0000
092h PIE2 OSFIE C2IE C1IE — BCL1IE C4IE
(2)
C3IE
(2)
CCP2IE
(2)
000- 0000 000- 0000
093h PIE3 PWM6IE
(2)
PWM5IE COG1IE ZCDIE COG2IE
(2)
CLC3IE CLC2IE CLC1IE
0000 0000 0000 0000
094h PIE4 —— TMR5GIE TMR5IE TMR3GIE TMR3IE TMR6IE TRM4IE
--00 0000 --00 0000
095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0>
1111 1111 1111 1111
096h PCON STKOVF STKUNF —RWDTRMCLR RI POR BOR
00-1 11qq qq-q qquu
097h WDTCON ——WDTPS<4:0>SWDTEN
--01 0110 --01 0110
098h OSCTUNE ——TUN<5:0>
--00 0000 --00 0000
099h OSCCON SPLLEN IRCF<3:0> —SCS<1:0>
0011 1-00 0011 1-00
09Ah OSCSTAT SOSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS
00q0 0q0q qqqq qq0q
09Bh ADRESL ADC Result Register Low
xxxx xxxx uuuu uuuu
09Ch ADRESH ADC Result Register High
xxxx xxxx uuuu uuuu
09Dh ADCON0 — CHS<4:0> GO/DONE ADON
-000 0000 -000 0000
09Eh ADCON1 ADFM ADCS<2:0> — ADNREF ADPREF<1:0>
0000 -000 0000 -000
09Fh ADCON2 TRIGSEL<4:0> — — —
0000 0--- 0000 0---
Legend:
x
= unknown;
u
= unchanged;
q
= value depends on condition; - = unimplemented, read as ‘
0
’;
r
= reserved.
Shaded locations are unimplemented, read as ‘
0
’.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1768/9 only.
3: PIC16(L)F1764/5 only.
4: Unimplemented on PIC16LF1764/5/8/9.
5: PIC16(L)F1768/9 only.
2014-2018 Microchip Technology Inc. DS40001775D-page 43
PIC16(L)F1764/5/8/9
Ban k 2
10Ch LATA —— LATA<5:4> — LATA<2:0>
--xx -xxx --uu -uuu
10Dh LATB
(2)
LATB<7:4> — — — —
xxxx ---- uuuu ----
10Eh LATC LATC<7:6>
(2)
LATC<5:0>
xxxx xxxx uuuu uuuu
10Fh CMOUT — — — — MC4OUT
(2)
MC3OUT
(2)
MC2OUT MC1OUT
---- 0000 ---- 0000
110h CM1CON0 ON OUT —POL ZLF Reserved HYS SYNC
00-0 0100 00-0 0100
111h CM1CON1 — — — — — — INTP INTN
---- --00 ---- --00
112h CM1NSEL — — — — — NCH<2:0>
---- -000 ---- -000
113h CM1PSEL — — — — — PCH<2:0>
---- -000 ---- -000
114h CM2CON0 ON OUT —POL ZLF Reserved HYS SYNC
00-0 0100 00-0 0100
115h CM2CON1 — — — — — — INTP INTN
---- --00 ---- --00
116h CM2NSEL — — — — — NCH<2:0>
---- -000 ---- -000
117h CM2PSEL — — — — — PCH<2:0>
---- -000 ---- -000
118h CM3CON0
(2)
ON OUT —POL ZLF Reserved HYS SYNC
00-0 0100 00-0 0100
119h CM3CON1
(2)
— — — — — — INTP INTN
---- --00 ---- --00
11Ah CM3NSEL
(2)
— — — — — NCH<2:0>
---- -000 ---- -000
11Bh CM3PSEL
(2)
— — — — — PCH<2:0>
---- -000 ---- -000
11Ch CM4CON0
(2)
ON OUT —POL ZLF Reserved HYS SYNC
00-0 0100 00-0 0100
11Dh CM4CON1
(2)
— — — — — — INTP INTN
---- --00 ---- --00
11Eh CM4NSEL
(2)
— — — — — NCH<2:0>
---- -000 ---- -000
11Fh CM4PSEL
(2)
— — — — — PCH<2:0>
---- -000 ---- -000
Ba nk 3
18Ch ANSELA — — — ANSA4 —ANSA<2:0>
---1 -111 ---1 -111
18Dh ANSELB
(2)
ANSB<7:4> — — — —
1111 ---- 1111 ----
18Eh ANSELC ANSC<7:6>
(2)
——ANSC<3:0>
11-- 1111 11-- 1111
18Fh —Unimplemented — —
190h —Unimplemented — —
191h PMADRL Program Memory Address Register Low Byte
0000 0000 0000 0000
192h PMADRH —
(1)
Program Memory Address Register High Byte
1000 0000 1000 0000
193h PMDATL Program Memory Read Data Register Low Byte
xxxx xxxx uuuu uuuu
194h PMDATH —— Program Memory Read Data Register High Byte
--xx xxxx --uu uuuu
195h PMCON1 —
(1)
CFGS LWLO FREE WRERR WREN WR RD
1000 x000 1000 q000
196h PMCON2 Program Memory Control Register 2
0000 0000 0000 0000
197h VREGCON
(4)
— — — — — —VREGPMReserved
---- --01 ---- --01
198h —Unimplemented — —
199h RC1REG EUSART Receive Data Register
0000 0000 0000 0000
19Ah TX1REG EUSART Transmit Data Register
0000 0000 0000 0000
19Bh SP1BRGL SP1BRG<7:0>
0000 0000 0000 0000
19Ch SP1BRGH SP1BRG<15:8>
0000 0000 0000 0000
19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
0000 0000 0000 0000
19Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
0000 0010 0000 0010
19Fh BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
01-0 0-00 01-0 0-00
TABLE 3-16: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Add r Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
All O ther
Resets
Legend:
x
= unknown;
u
= unchanged;
q
= value depends on condition; - = unimplemented, read as ‘
0
’;
r
= reserved.
Shaded locations are unimplemented, read as ‘
0
’.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1768/9 only.
3: PIC16(L)F1764/5 only.
4: Unimplemented on PIC16LF1764/5/8/9.
5: PIC16(L)F1768/9 only.
2014-2018 Microchip Technology Inc. DS40001775D-page 44
PIC16(L)F1764/5/8/9
Ban k 4
20Ch WPUA ——WPUA<5:0
--11 1111 --11 1111
20Dh WPUB
(2)
WPUB<7:4> — — — —
1111 ---- 1111 ----
20Eh WPUC WPUC<7:6>
(2)
WPUC<5:0>
1111 1111 1111 1111
20Fh —Unimplemented — —
210h —Unimplemented — —
211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
212h SSP1ADD ADD<7:0>
0000 0000 0000 0000
213h SSP1MSK MSK<7:0>
1111 1111 1111 1111
214h SSP1STAT SMP CKE D/A PSR/WUA BF
0000 0000 0000 0000
215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0>
0000 0000 0000 0000
216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
0000 0000 0000 0000
217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
0000 0000 0000 0000
218h
—
21Ch
—Unimplemented — —
21Dh BORCON SBOREN BORFS — — — — — BORRDY
10-- ---q uu-- ---u
21Eh FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0>
0q00 0000 0q00 0000
21Fh ZCD1CON EN —OUTPOL——INTPINTN
0-x0 --00 0-x0 --00
B ank 5
28Ch ODCONA ——ODA<5:4> —ODA<2:0>
--00 -000 --00 -000
28Dh ODCONB
(2)
ODB<7:4> — — — —
0000 ---- 0000 ----
28Eh ODCONC ODC<7:6>
(2)
ODC<5:0>
0000 0000 0000 0000
28Fh —Unimplemented — —
290h —Unimplemented — —
291h CCPR1L Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
292h CCPR1H Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
293h CCP1CON EN —OUTFMT MODE<3:0>
0-00 0000 0-00 0000
294h CCP1CAP — — — — — CTS<2:0>
---- -000 ---- -000
295h
—
297h
—Unimplemented — —
298h CCPR2L
(2)
Capture/Compare/PWM Register 2 (LSB)
xxxx xxxx uuuu uuuu
299h CCPR2H
(2)
Capture/Compare/PWM Register 2 (MSB)
xxxx xxxx uuuu uuuu
29Ah CCP2CON
(2)
EN —OUTFMT MODE<3:0>
0-00 0000 0-00 0000
29Bh CCP2CAP
(2)
— — — — — CTS<2:0>
---- -000 ---- -000
29Ch
—
29Dh
—Unimplemented — —
29Eh CCPTMRS P4TSEL<1:0>
(2)
P3TSEL<1:0> C2TSEL<1:0>
(2)
C1TSEL<1:0>
0000 0000 0000 0000
29Fh —Unimplemented — —
TABLE 3-16: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Add r Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
All O ther
Resets
Legend:
x
= unknown;
u
= unchanged;
q
= value depends on condition; - = unimplemented, read as ‘
0
’;
r
= reserved.
Shaded locations are unimplemented, read as ‘
0
’.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1768/9 only.
3: PIC16(L)F1764/5 only.
4: Unimplemented on PIC16LF1764/5/8/9.
5: PIC16(L)F1768/9 only.
2014-2018 Microchip Technology Inc. DS40001775D-page 45
PIC16(L)F1764/5/8/9
Ban k 6
30Ch SLRCONA —— SLRA<5:4> — SLRA<2:0>
--11 -111 --11 -111
30Dh SLRCONB
(2)
SLRB<7:4> — — — —
1111 ---- 1111 ----
30Eh SLRCONC SLRC<7:6>
(2)
SLRC<5:0>
1111 1111 1111 1111
30Fh
—
31Ah
—Unimplemented — —
31Bh MD2CON0
(2)
EN —OUTOPOL— — —BIT
0-00 ---0 0-00 ---0
31Ch MD2CON1
(2)
—— CHPOL CHSYNC —— CLPOL CLSYNC
--00 --00 --00 --00
31Dh MD2SRC
(2)
— — —MS<4:0>
---0 0000 ---0 0000
31Eh MD2CARL
(2)
— — — — CL<3:0>
---- 0000 ---- 0000
31Fh MD2CARH
(2)
— — — — CH<3:0>
---- 0000 ---- 0000
B ank 7
38Ch INLVLA —— INLVLA<5:0>
--11 1111 --11 1111
38Dh INLVLB
(2)
INLVLB<7:4> — — — —
1111 ---- 1111 ----
38Eh INLVLC INLVLC<7:6>
(2)
INLVLC<5:0>
1111 1111 1111 1111
38Fh —Unimplemented — —
390h —Unimplemented — —
391h IOCAP —— IOCAP<5:0>
--00 0000 --00 0000
392h IOCAN ——IOCAN<5:0>
--00 0000 --00 0000
393h IOCAF ——IOCAF<5:0>
--00 0000 --00 0000
394h IOCBP
(2)
IOCBP<7:4> — — — —
0000 ---- 0000 ----
395h IOCBN
(2)
IOCBN<7:4> — — — —
0000 ---- 0000 ----
396h IOCBF
(2)
IOCBF<7:4> — — — —
0000 ---- 0000 ----
397h IOCCP IOCCP<7:6>
(2)
IOCCP<5:0>
0000 0000 0000 0000
398h IOCCN IOCCN<7:6>
(2)
IOCCN<5:0>
0000 0000 0000 0000
399h IOCCF IOCCF<7:6>
(2)
IOCCF<5:0>
0000 0000 0000 0000
39Ah —Unimplemented — —
39Bh MD1CON0 EN —OUTOPOL— — —BIT
0-00 ---0 0-00 ---0
39Ch MD1CON1 —— CHPOL CHSYNC —— CLPOL CLSYNC
--00 --00 --00 --00
39Dh MD1SRC — — —MS<4:0>
---0 0000 ---0 0000
39Eh MD1CARL — — — — CL<3:0>
---- 0000 ---- 0000
39Fh MD1CARH — — — — CH<3:0>
---- 0000 ---- 0000
TABLE 3-16: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Add r Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
All O ther
Resets
Legend:
x
= unknown;
u
= unchanged;
q
= value depends on condition; - = unimplemented, read as ‘
0
’;
r
= reserved.
Shaded locations are unimplemented, read as ‘
0
’.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1768/9 only.
3: PIC16(L)F1764/5 only.
4: Unimplemented on PIC16LF1764/5/8/9.
5: PIC16(L)F1768/9 only.
2014-2018 Microchip Technology Inc. DS40001775D-page 46
PIC16(L)F1764/5/8/9
Ban k 8
40Ch
—
40Dh
—Unimplemented — —
40Eh HIDRVC —— HIDC<5:4> — — — —
--00 ---- --00 ----
40Fh
—
412h
—Unimplemented — —
413h T4TMR Holding Register for the 8-Bit TMR4 Register
0000 0000 0000 0000
413h T4PR TMR4 Period Register
1111 1111 1111 1111
415h T4CON ON CKPS<2:0> OUTPS<3:0>
0000 0000 0000 0000
416h T4HLT PSYNC CKPOL CKSYNC MODE<4:0>
0000 0000 0000 0000
417h T4CLKCON — — — — CS<3:0>
---- 0000 ---- 0000
418h T4RST — — — — RSEL<3:0>
---- 0000 ---- 0000
419h —Unimplemented — —
41Ah T6TMR Holding Register for the 8-Bit TMR4 Register
0000 0000 0000 0000
41Bh T6PR TMR4 Period Register
1111 1111 1111 1111
41Ch T6CON ON CKPS<2:0> OUTPS<3:0>
0000 0000 0000 0000
41Dh T6HLT PSYNC CKPOL CKSYNC MODE<4:0>
0000 0000 0000 0000
41Eh T6CLKCON — — — — CS<3:0>
---- 0000 ---- 0000
41Fh T6RST — — — — RSEL<3:0>
---- 0000 ---- 0000
B ank 9
48Ch
to
492h
—Unimplemented — —
493h TMR3L Holding Register for the Least Significant Byte of the 16-Bit TMR1 Register
xxxx xxxx uuuu uuuu
494h TMR3H Holding Register for the Most Significant Byte of the 16-Bit TMR1 Register
xxxx xxxx uuuu uuuu
495h T3CON CS<1:0> CKPS<1:0> OSCEN SYNC —ON
0000 00-0 uuuu uu-u
496h T3GCON GE GPOL GTM GSPM GGO/DONE GVAL GSS<1:0>
0000 0x00 uuuu uxuu
497h
to
499h
—Unimplemented — —
49Ah TMR5L Holding Register for the Least Significant Byte of the 16-Bit TMR1 Register
xxxx xxxx uuuu uuuu
49Bh TMR5H Holding Register for the Most Significant Byte of the 16-Bit TMR1 Register
xxxx xxxx uuuu uuuu
49Ch T5CON CS<1:0> CKPS<1:0> OSCEN SYNC —ON
0000 00-0 uuuu uu-u
49Dh T5GCON GE GPOL GTM GSPM GGO/DONE GVAL GSS<1:0>
0000 0x00 uuuu uxuu
49Eh
to
49Fh
—Unimplemented — —
TABLE 3-16: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Add r Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
All O ther
Resets
Legend:
x
= unknown;
u
= unchanged;
q
= value depends on condition; - = unimplemented, read as ‘
0
’;
r
= reserved.
Shaded locations are unimplemented, read as ‘
0
’.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1768/9 only.
3: PIC16(L)F1764/5 only.
4: Unimplemented on PIC16LF1764/5/8/9.
5: PIC16(L)F1768/9 only.
2014-2018 Microchip Technology Inc. DS40001775D-page 47
PIC16(L)F1764/5/8/9
Ban k 10
50Ch
—
50Eh
—Unimplemented — —
50Fh OPA1NCHS — — — — NCH<3:0>
---- 0000 ---- 0000
510h OPA1PCHS — — — — PCH<3:0>
---- 0000 ---- 0000
511h OPA1CON EN ——UG— ORPOL ORM<1:0>
0--0 -000 0--0 -000
512h OPA1ORS — — —ORS<4:0>
---0 0000 ---0 0000
513h OPA2NCHS
(2)
— — — — NCH<3:0>
---- 0000 ---- 0000
514h OPA2PCHS
(2)
— — — — PCH<3:0>
---- 0000 ---- 0000
515h OPA2CON
(2)
EN ——UG— ORPOL ORM<1:0>
0--0 -000 0--0 -000
516h OPA2ORS
(2)
— — —ORS<4:0>
---0 0000 ---0 0000
517h
—
51Fh
—Unimplemented — —
B ank 11
590h DACLD --- --- --- --- --- --- DAC2LD
(2)
DAC1LD
---- --00 ---- --00
591h DAC1CON0 EN FM OE1 --- PSS<1:0> NSS<1:0>
000- 0000 000- 0000
592h DAC1REFL REF<7:0>
0000 0000 0000 0000
593h DAC1REFH REF<15:8>
0000 0000 0000 0000
594h DAC2CON0
(2)
EN FM OE1 --- PSS<1:0> NSS<1:0>
000- 0000 000- 0000
595h DAC2REFL
(2)
REF<7:0>
0000 0000 0000 0000
596h DAC2REFH
(2)
REF<15:8>
0000 0000 0000 0000
597h DAC3CON0 EN --- OE1 --- PSS<1:0> NSS<1:0>
0-0- 0000 0-00 0000
598h DAC3REF --- --- --- REF<4:0>
---0 0000 ---0 0000
599h DAC4CON0
(2)
EN --- OE1 --- PSS<1:0> NSS<1:0>
0-0- 0000 0-00 0000
59Ah DAC4REF
(2)
--- --- --- REF<4:0>
---0 0000 ---0 0000
59Bh
to
59Fh
—Unimplemented — —
TABLE 3-16: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Add r Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
All O ther
Resets
Legend:
x
= unknown;
u
= unchanged;
q
= value depends on condition; - = unimplemented, read as ‘
0
’;
r
= reserved.
Shaded locations are unimplemented, read as ‘
0
’.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1768/9 only.
3: PIC16(L)F1764/5 only.
4: Unimplemented on PIC16LF1764/5/8/9.
5: PIC16(L)F1768/9 only.
2014-2018 Microchip Technology Inc. DS40001775D-page 48
PIC16(L)F1764/5/8/9
Ban k 1 2
60Ch
to
616h
—Unimplemented — —
617h PWM3DCL DC<1:0> — — — — — —
xx-- ---- uu-- ----
618h PWM3DCH DC<9:2>
xxxx xxxx uuuu uuuu
619h PWM3CON EN —OUTPOL— — — —
0-00 ---- 0-00 ----
61Ah PWM4DCL
(2)
DC<1:0> — — — — — —
00-- ---- uu-- ----
61Bh PWM4DCH
(2)
DC<9:2>
0000 0000 uuuu uuuu
61Ch PWM4CON
(2)
EN —OUTPOL— — — —
0-00 ---- 0-00 ----
61Dh
—
61Fh
—Unimplemented — —
B ank 1 3
68Ch —Unimplemented — —
68Dh COG1PHR — — COG Rising Edge Phase Delay Count Register
--00 0000 --00 0000
68Eh COG1PHF — — COG Falling Edge Phase Delay Count Register
--00 0000 --00 0000
68Fh COG1BLKR — — COG Rising Edge Blanking Count Register
--00 0000 --00 0000
690h COG1BLKF — — COG Falling Edge Blanking Count Register
--00 0000 --00 0000
691h COG1DBR — — COG Rising Edge Dead-band Count Register
--00 0000 --00 0000
692h COG1DBF — — COG Falling Edge Dead-band Count Register
--00 0000 --00 0000
693h COG1CON0 EN LD — CS<1:0> MD<2:0>
00-0 0000 00-0 0000
694h COG1CON1 RDBS FDBS —— POLD POLC POLB POLA
00-- 0000 00-- 0000
695h COG1RIS0 RIS<7:0>
0000 0000 0000 0000
696h COG1RIS1 RIS15
(2)
RIS<14:8>
0000 0000 0000 0000
697h COG1RSIM0 RSIM<7:0>
0000 0000 0000 0000
698h COG1RSIM1 RSIM15
(2)
RSIM<14:8>
0000 0000 0000 0000
699h COG1FIS0 FIS<7:0>
0000 0000 0000 0000
69Ah COG1FIS1 FIS15
(2)
FIS<14:8>
0000 0000 0000 0000
69Bh COG1FSIM0 FSIM<7:0>
0000 0000 0000 0000
69Ch COG1FSIM1 FSIM15
(2)
FSIM<14:8>
0000 0000 0000 0000
69Dh COG1ASD0 ASE ARSEN ASDBD<1:0> ASDAC<1:0> — —
0001 01-- 0001 01--
69Eh COG1ASD1 AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E
0000 0000 0000 0000
69Fh COG1STR SDATD SDATC SDATB SDATA STRD STRC STRB STRA
0000 0000 0000 0000
TABLE 3-16: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Add r Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
All O ther
Resets
Legend:
x
= unknown;
u
= unchanged;
q
= value depends on condition; - = unimplemented, read as ‘
0
’;
r
= reserved.
Shaded locations are unimplemented, read as ‘
0
’.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1768/9 only.
3: PIC16(L)F1764/5 only.
4: Unimplemented on PIC16LF1764/5/8/9.
5: PIC16(L)F1768/9 only.
2014-2018 Microchip Technology Inc. DS40001775D-page 49
PIC16(L)F1764/5/8/9
Ban k 1 4
70Ch —Unimplemented — —
70Dh COG2PHR
(2)
— — COG Rising Edge Phase Delay Count Register
--00 0000 --00 0000
70Eh COG2PHF
(2)
— — COG Falling Edge Phase Delay Count Register
--00 0000 --00 0000
70Fh COG2BLKR
(2)
— — COG Rising Edge Blanking Count Register
--00 0000 --00 0000
710h COG2BLKF
(2)
— — COG Falling Edge Blanking Count Register
--00 0000 --00 0000
711h COG2DBR
(2)
— — COG Rising Edge Dead-band Count Register
--00 0000 --00 0000
712h COG2DBF
(2)
— — COG Falling Edge Dead-band Count Register
--00 0000 --00 0000
713h COG2CON0
(2)
EN LD — CS<1:0> MD<2:0>
00-0 0000 00-0 0000
714h COG2CON1
(2)
RDBS FDBS —— POLD POLC POLB POLA
00-- 0000 00-- 0000
715h COG2RIS0
(2)
RIS<7:0>
0000 0000 0000 0000
716h COG2RIS1
(2)
RIS<15:8>
0000 0000 0000 0000
717h COG2RSIM0
(2)
RSIM<7:0>
0000 0000 0000 0000
718h COG2RSIM1
(2)
RSIM<15:8>
0000 0000 0000 0000
719h COG2FIS0
(2)
FIS<7:0>
0000 0000 0000 0000
71Ah COG2FIS1
(2)
FIS<15:8>
0000 0000 0000 0000
71Bh COG2FSIM0
(2)
FSIM<7:0>
0000 0000 0000 0000
71Ch COG2FSIM1
(2)
FSIM<15:8>
0000 0000 0000 0000
71Dh COG2ASD0
(2)
ASE ARSEN ASDBD<1:0> ASDAC<1:0> — —
0001 01-- 0001 01--
71Eh COG2ASD1
(2)
AS7E AS6E AS5E AS4E AS3E AS2E AS1E AS0E
0000 0000 0000 0000
71Fh COG2STR
(2)
SDATD SDATC SDATB SDATA STRD STRC STRB STRA
0000 0000 0000 0000
B ank 1 5
78Ch
—
793h
—Unimplemented — —
794h PRG1RTSS — — — — RTSS<3:0>
---- 0000 ---- 0000
795h PRG1FTSS — — — — FTSS<3:0>
---- 0000 ---- 0000
796h PRG1INS — — — —INS<3:0>
---- 0000 ---- 0000
797h PRG1CON0 EN — FEDG REDG MODE<1:0> OS GO
0-00 0000 0-00 0000
798h PRG1CON1 — — — — — RDY FPOL RPOL
---- -000 ---- -000
799h PRG1CON2 LR
(5)
—— ISET<4:0>
0--0 0000 0--0 0000
79Ah PRG2RTSS
(2)
— — — — RTSS<3:0>
---- 0000 ---- 0000
79Bh PRG2FTSS
(2)
— — — — FTSS<3:0>
---- 0000 ---- 0000
79Ch PRG2INS
(2)
— — — —INS<3:0>
---- 0000 ---- 0000
79Dh PRG2CON0
(2)
EN — FEDG REDG MODE<1:0> OS GO
0-00 0000 0-00 0000
79Eh PRG2CON1
(2)
— — — — — RDY FPOL RPOL
---- -000 ---- -000
79Fh PRG2CON2
(2)
LR
(5)
—— ISET<4:0>
0--0 0000 0--0 0000
Bank 16-26
x0Ch/
x8Ch
—
x1Fh/
x9Fh
—Unimplemented — —
TABLE 3-16: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Add r Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
All O ther
Resets
Legend:
x
= unknown;
u
= unchanged;
q
= value depends on condition; - = unimplemented, read as ‘
0
’;
r
= reserved.
Shaded locations are unimplemented, read as ‘
0
’.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1768/9 only.
3: PIC16(L)F1764/5 only.
4: Unimplemented on PIC16LF1764/5/8/9.
5: PIC16(L)F1768/9 only.
