1. General description
The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible
with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual
data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has
complementary outputs (Q and Q).
The set and reset are asynchronous active LOW inputs that operate independent of the
clock input. Information on the data input is transferred to the Q output on the LOW to
HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to
the LOW to HIGH clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features
nBalanced propagation delays
nAll inputs have Schmitt-trigger actions
nInputs accept voltages higher than VCC
nInput levels:
uFor 74AHC74: CMOS level
uFor 74AHCT74: TTL level
nESD protection:
uHBM EIA/JESD22-A114E exceeds 2000 V
uMM EIA/JESD22-A115-A exceeds 200 V
uCDM EIA/JESD22-C101C exceeds 1000 V
nMultiple package options
nSpecified from −40 °C to +85 °C and from −40 °C to +125 °C
74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 05 — 9 June 2008 Product data sheet
74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 9 June 2008 2 of 18
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AHC74
74AHC74D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width
3.9 mm SOT108-1
74AHC74PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body
width 4.4 mm SOT402-1
74AHC74BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 ×3×0.85 mm
SOT762-1
74AHCT74
74AHCT74D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width
3.9 mm SOT108-1
74AHCT74PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body
width 4.4 mm SOT402-1
74AHCT74BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 ×3×0.85 mm
SOT762-1
Fig 1. Functional diagram
mna418
RD
FF
SD
410
Q1Q
2Q
1Q
2Q
5
9
2
12
3
11 6
8
Q
1SD
CP
2CP
1CP
2D
1D D
2SD
113
1RD 2RD
74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 9 June 2008 3 of 18
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
Fig 2. Logic symbol Fig 3. IEC logic symbol
RD
FF
SD
4
Q1Q
1Q
5
2
3
6
Q
1SD
CP
1CP
1D D
11RD
mna420
RD
FF
SD
10
Q2Q
2Q
9
12
11
8
Q
2SD
CP
2CP
2D D
13 2RD
mna419
6
3
2C1
4S
1D
1R
5
8
11
12 C1
10 S
1D
13 R
9
Fig 4. Logic diagram (one flip-flop)
mna421
SD
CP
RD
D
C
C
Q
C
C
C
C
C
C
Q
C
C
74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 9 June 2008 4 of 18
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used
as supply pin or input.
Fig 5. Pin configuration SO14 and TSSOP14 Fig 6. Pin configuration DHVQFN14
74
1RD VCC
1D 2RD
1CP 2D
1SD 2CP
1Q 2SD
1Q 2Q
GND 2Q
001aac449
1
2
3
4
5
6
78
10
9
12
11
14
13
001aac450
74
Transparent top view
1Q 2Q
1Q 2SD
1SD 2CP
1CP 2D
1D 2RD
GND
2Q
1RD
VDD
6 9
GND(1)
5 10
4 11
3 12
2 13
7
8
1
14
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
1RD 1 asynchronous reset direct input (active LOW)
1D 2 data input
1CP 3 clock input (LOW to HIGH, edge-triggered)
1SD 4 asynchronous set direct input (active LOW)
1Q 5 true flip-flop output
1Q 6 complement flip-flop output
GND 7 ground (0 V)
2Q 8 complement flip-flop output
2Q 9 true flip-flop output
2SD 10 asynchronous set direct input (active LOW)
2CP 11 clock input (LOW to HIGH, edge-triggered)
2D 12 data input
2RD 13 asynchronous reset direct input (active LOW)
VCC 14 supply voltage
74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 9 June 2008 5 of 18
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
6. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
↑= LOW to HIGH transition;
Qn+1 = state after the next LOW to HIGH CP transition;
X = don’t care.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP14 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K.
Table 3. Function table[1]
Control Input Output
nSD nRD nCP nD nQ nQ nQn+1 nQn+1
LHXXHLLH
HLXXLHHL
LLXXHH- -
HH↑L- - LH
HH↑H- - HL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7.0 V
VIinput voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5 V [1] −20 - mA
IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] −20 +20 mA
IOoutput current VO = −0.5V to (VCC + 0.5 V) −25 +25 mA
ICC supply current - +75 mA
IGND ground current −75 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb =−40 °C to +125 °C[2] - 500 mW
74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 9 June 2008 6 of 18
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
8. Recommended operating conditions
9. Static characteristics
Table 5. Operating conditions
Symbol Parameter Conditions Min Typ Max Unit
74AHC74
VCC supply voltage 2.0 5.0 5.5 V
VIinput voltage 0 - 5.5 V
VOoutput voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
∆t/∆V input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 ns/V
VCC = 4.5 V to 5.5 V - - 20 ns/V
74AHCT74
VCC supply voltage 4.5 5.0 5.5 V
VIinput voltage 0 - 5.5 V
VOoutput voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
∆t/∆V input transition rise and fall rate VCC = 4.5 V to 5.5 V - - 20 ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °Cto+85°C−40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74AHC74
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V
VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V
VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage VI=V
IH or VIL
IO=−50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO=−50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V
IO=−50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO=−4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V
IO=−8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage VI=V
IH or VIL
IO=50µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO=50µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V
IO=50µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V
IO= 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V
74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 9 June 2008 7 of 18
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
IIinput leakage
current VI= 5.5 Vor GND;
VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 µA
ICC supply current VI=V
CC or GND; IO=0A;
VCC = 5.5 V - - 2.0 - 20 - 40 µA
CIinput
capacitance VI=V
CC or GND - 3 10 - 10 - 10 pF
74AHCT74
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL; VCC = 4.5 V
IO=−50 µA 4.4 4.5 - 4.4 - 4.4 - V
IO=−8.0 mA 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage VI=V
IH or VIL; VCC = 4.5 V
IO=50µA - 0 0.1 - 0.1 - 0.1 V
IO= 8.0 mA - - 0.36 - 0.44 - 0.55 V
IIinput leakage
current VI= 5.5 Vor GND;
VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 µA
ICC supply current VI=V
CC or GND; IO=0A;
VCC = 5.5 V - - 2.0 - 20 - 40 µA
∆ICC additional
supply current per input pin;
VI=V
CC −2.1 V; other pins
at VCC or GND; IO=0A;
VCC = 4.5 V to 5.5 V
- - 1.35 - 1.5 - 1.5 mA
CIinput
capacitance VI=V
CC or GND - 3 10 - 10 - 10 pF
Table 6. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °Cto+85°C−40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 9 June 2008 8 of 18
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max Min Max
74AHC74
tpd propagation
delay nCP to nQ, nQ; see Figure 7 [2]
VCC = 3.0 V to 3.6 V
CL= 15 pF - 5.2 11.9 1.0 14.0 1.0 15.0 ns
CL= 50 pF - 7.4 15.4 1.0 17.5 1.0 19.5 ns
VCC = 4.5 V to 5.5 V
CL= 15 pF - 3.7 7.3 1.0 8.5 1.0 9.5 ns
CL= 50 pF - 5.2 9.3 1.0 10.5 1.0 12.0 ns
nSD, nRD to nQ, nQ;
see Figure 8
VCC = 3.0 V to 3.6 V
CL= 15 pF - 5.4 12.3 1.0 14.5 1.0 15.5 ns
CL= 50 pF - 7.7 15.8 1.0 18.0 1.0 20.0 ns
VCC = 4.5 V to 5.5 V
CL= 15 pF - 3.7 7.7 1.0 9.0 1.0 10.0 ns
CL= 50 pF - 5.3 9.7 1.0 11.0 1.0 12.5 ns
fmax maximum
frequency see Figure 7
VCC = 3.0 V to 3.6 V
CL= 15 pF 80 125 - 45 - 45 - MHz
CL= 50 pF 50 75 - 70 - 70 - MHz
VCC = 4.5 V to 5.5 V
CL= 15 pF 130 170 - 110 - 110 - MHz
CL= 50 pF 90 115 - 75 - 75 - MHz
tWpulse width CP HIGH or LOW;
nSD, nRD LOW;
see Figure 7 and 8
VCC = 3.0 V to 3.6 V 6.0 - - 7.0 - 7.0 - ns
VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns
tsu set-up time nD to nCP; see Figure 7
VCC = 3.0 V to 3.6 V 6.0 - - 7.0 - 7.0 - ns
VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns
thhold time nD to nCP; see Figure 7
VCC = 3.0 V to 3.6 V 0.5 - - 0.5 - 0.5 - ns
VCC = 4.5 V to 5.5 V 0.5 - - 0.5 - 0.5 - ns
trec recovery
time nRD to nCP; see Figure 8
VCC = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns
VCC = 4.5 V to 5.5 V 3.0 - - 3.0 - 3.0 - ns
74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 9 June 2008 9 of 18
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL×VCC2×fo) = sum of the outputs.
CPD power
dissipation
capacitance
fi= 1 MHz; VI= GND to VCC [3] -12- - - - -pF
74AHCT74; VCC = 4.5 V to 5.5 V
tpd propagation
delay nCP to nQ, nQ; see Figure 7 [2]
CL= 15 pF - 3.3 7.8 1.0 9.0 1.0 10.0 ns
CL= 50 pF - 4.8 8.8 1.0 10.0 1.0 11.0 ns
nSD, nRD to nQ, nQ;
see Figure 7
CL= 15 pF - 3.7 10.4 1.0 12.0 1.0 13.0 ns
CL= 50 pF - 5.3 11.4 1.0 13.0 1.0 14.5 ns
fmax maximum
frequency see Figure 7
CL= 15 pF 100 160 - 80 - 80 - MHz
CL= 50 pF 80 140 - 65 - 65 - MHz
tWpulse width CP HIGH or LOW;
nSD, nRD LOW;
see Figure 7 and 8
5.0 - - 5.0 - 5.0 - ns
tsu set-up time nD to nCP; see Figure 7 5.0 - - 5.0 - 5.0 - ns
thhold time nD to nCP; see Figure 7 0-- 0 - 0 -ns
trec recovery
time nRD to nCP; see Figure 8 3.5 - - 3.5 - 3.5 - ns
CPD power
dissipation
capacitance
fi= 1 MHz; VI= GND to VCC [3] -16- - - - -pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max Min Max
74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 9 June 2008 10 of 18
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
11. Waveforms
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 7. Clock pulse width, maximum frequency, set-up times, hold times and input to output propagation delays
mna422
th
tsu
th
tPHL
tPHL
tW
tPLH
tPLH
tsu
1/fmax
VM
VM
VM
VM
VI
GND
VI
GND
nCP input
nD input
VOH
VOL
nQ output
VOH
VOL
nQ output
74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 9 June 2008 11 of 18
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
Measurement points are given in Table 8.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 8. Set and reset pulse widths, recovery time and input to output propagation delays
mna423
trec
tPHL
tPHL
tW
tPLH
tPLH
VM
VM
VM
tW
VM
VM
VI
GND
VI
GND
nSD input
VI
GND
nRD input
nCP input
VOH
VOL
nQ output
VOH
VOL
nQ output
Table 8. Measurement points
Type Input Output
VMVM
74AHC74 0.5 ×VCC 0.5 ×VCC
74AHCT74 1.5 V 0.5 ×VCC
74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 9 June 2008 12 of 18
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
For test data see Table 9.
Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 9. Load circuitry for switching times
001aah768
tW
tW
tr
tr
tf
VM
VI
negative
pulse
GND
VI
positive
pulse
GND
10 %
90 %
90 %
10 % VMVM
VM
tf
VCC
DUT
RT
VIVO
CL
G
Table 9. Test data
Type Input Load Test
VItr, tfCL
74AHC74 VCC ≤3.0 ns 50 pF, 15 pF tPLH, tPHL
74AHCT74 3.0 V ≤3.0 ns 50 pF, 15 pF tPLH, tPHL
74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 9 June 2008 13 of 18
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
12. Package outline
Fig 10. Package outline SOT108-1 (SO14)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 9 June 2008 14 of 18
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
Fig 11. Package outline SOT402-1 (TSSOP14)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.72
0.38 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index
74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 9 June 2008 15 of 18
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
Fig 12. Package outline SOT762-1 (DHVQFN14)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.1
2.9
Dh
1.65
1.35
y1
2.6
2.4 1.15
0.85
e1
2
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
26
13 9
8
7
1
14
X
D
E
C
BA
02-10-17
03-01-27
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 9 June 2008 16 of 18
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CDM Charged Device Model
CMOS Complementary Metal-Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
LSTTL Low-power Schottky Transistor-Transistor Logic
MM Machine Model
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74AHC_AHCT74_5 20080609 Product data sheet - 74AHC_AHCT74_4
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Table 6: the conditions for input leakage current have been changed.
74AHC_AHCT74_4 20050207 Product data sheet - 74AHC_AHCT74_3
74AHC_AHCT74_3 20040429 Product specification - 74AHC_AHCT74_2
74AHC_AHCT74_2 19990923 Product specification - 74AHC_AHCT74_1
74AHC_AHCT74_1 19990805 Product specification - -
74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 9 June 2008 17 of 18
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
© NXP B.V. 2008. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 June 2008
Document identifier: 74AHC_AHCT74_5
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
16 Contact information. . . . . . . . . . . . . . . . . . . . . 17
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
