KAI-29052 6576 (H) x 4384 (V) Interline CCD Image Sensor Description The KAI-29052 Image Sensor is a 29 Megapixel CCD in a 35 mm optical format that provides increased Quantum Efficiency (particularly for NIR wavelengths) compared to members of the standard 5.5 mm family. The sensor shares the same broad dynamic range, excellent imaging performance, and flexible readout architecture as other members of the 5.5 mm pixel family. However, QE at 820 nm has been approximately doubled compared to existing devices, enabling enhanced sensitivity without a corresponding decrease in the Modulation Transfer Function (MTF) of the device. The sensor is available with the Sparse Color Filter Pattern, which provides a 2x improvement in light sensitivity compared to a standard color Bayer part. The KAI-29052 is drop-in compatible with the KAI-29050 Image Sensor, simplifying adoption by camera manufacturers currently working with the KAI-29050. Aspect Ratio Number of Outputs Charge Capacity Output Sensitivity Quantum Efficiency Pan (-AXA, -QXA, -PXA) R, G, B (-FXA, -QXA) Read Noise (f = 40 MHz) Dark Current Photodiode VCCD Dark Current Doubling Temp. Photodiode VCCD Dynamic Range Charge Transfer Efficiency Blooming Suppression Smear Image Lag Maximum Pixel Clock Speed Maximum Frame Rates Quad Output Dual Output Single Output Package Cover Glass Figure 1. KAI-29052 CCD Image Sensor Features * Increased QE, with 2x Improvement at Table 1. GENERAL SPECIFICATIONS Parameter Architecture Total Number of Pixels Number of Effective Pixels Number of Active Pixels Pixel Size Active Image Size www.onsemi.com Typical Value Interline CCD; Progressive Scan 6644 (H) x 4452 (V) 6600 (H) x 4408 (V) 6576 (H) x 4384 (V) 5.5 mm (H) x 5.5 mm (V) 36.17 mm (H) x 24.11 mm (V) 43.47 mm (diag.), 35 mm Optical Format 3:2 1, 2, or 4 20,000 electrons 35 mV/e* 43%, 12%, 5% (540, 850, 920 nm) 39%, 40%, 37% (620, 540, 480 nm) 10 electrons rms 7 electrons/s 140 electrons/s 820 nm * Bayer Color Pattern, Sparse Color Pattern, * * * * * * and Monochrome Configurations Progressive Scan Readout Flexible Readout Architecture High Frame Rate Low Noise Architecture Excellent Smear Performance Package Pin Reserved for Device Identification Applications * Industrial Imaging and Inspection * Medical Imaging * Security and Surveillance ORDERING INFORMATION 7C 9C 66 dB 0.999999 > 300 X Estimated -100 dB < 10 electrons 40 MHz See detailed ordering and shipping information on page 2 of this data sheet. 4 fps 2 fps 1 fps 72 pin PGA AR Coated, 2 Sides NOTE: All Parameters are specified at T = 40C unless otherwise noted. (c) Semiconductor Components Industries, LLC, 2016 May, 2017 - Rev. 0 1 Publication Order Number: KAI-29052/D KAI-29052 ORDERING INFORMATION Table 2. ORDERING INFORMATION Part Number Description Marking Code KAI-29052-AXA-JD-B1 Monochrome, Special Microlens, PGA Package, Sealed Clear Cover Glass with AR Coating (Both Sides), Grade 1 KAI-29052-AXA-JD-B2 Monochrome, Special Microlens, PGA Package, Sealed Clear Cover Glass with AR Coating (Both Sides), Grade 1 KAI-29052-AXA-JD-AE Monochrome, Special Microlens, PGA Package, Sealed Clear Cover Glass with AR Coating (Both Sides), Engineering Grade KAI-29052-FXA-JD-B1 Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR Coating (Both Sides), Grade 1 KAI-29052-FXA-JD-B2 Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR Coating (Both Sides), Grade 2 KAI-29052-FXA-JD-AE Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR Coating (Both Sides), Engineering Grade KAI-29050-QXA-JD-B1 Gen2 Color (Sparse CFA), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR Coating (Both Sides), Grade 1 KAI-29050-QXA-JD-AE Gen2 Color (Sparse CFA), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR Coating (Both Sides), Engineering Grade KAI-29052-AXA Serial Number KAI-29052-FXA Serial Number KAI-29052-QXA Serial Number Table 3. EVALUATION SUPPORT Part Number Description G2-FPGA-BD-14-40-A-GEVK FPGA Board for IT-CCD Evaluation Hardware KAI-72PIN-HEAD-BD-A-GEVB 72 Pin Imager Board for IT-CCD Evaluation Hardware LENS-MOUNT-KIT-C-GEVK Lens Mount Kit for IT-CCD Evaluation Hardware See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. www.onsemi.com 2 KAI-29052 DEVICE DESCRIPTION Architecture H2Bd H2Sd H1Bd H1Sd FDGcd SUB FDGcd H2Bc H2Sc H1Bc H1Sc RDc Rc VDDc VOUTc RDd Rd VDDd VOUTd OOOOOOOOOOOOOOOOOOOO 1 10 22 12 8 3288 3288 12 8 22 10 1 FLD 22 12 GND OGc H2SLc V1T V2T V3T V4T GND OGd H2SLd V1T V2T V3T V4T DevID 22 12 ESD 6576 (H) y 4384 (V) 5.5 mm y 5.5 mm Pixels 12 22 V1B V2B V3B V4B RDa Ra VDDa VOUTa ESD V1B V2B V3B V4B OOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOO 12 Buffer 22 Dark (Last VCCD Phase = V1 a H1S) FLD 1 10 22 12 8 3288 H2Bb H2Sb H1Bb H1Sb FDGab SUB FDGab H2Ba H2Sa H1Ba H1Sa GND OGa H2SLa 3288 12 8 22 10 1 RDb Rb VDDb VOUTb GND OGb H2SLb Figure 2. Block Diagram Dark Reference Pixels Image Acquisition There are 22 dark reference rows at the top and 22 dark rows at the bottom of the image sensor. The dark rows are not entirely dark and so should not be used for a dark reference level. Use the 22 dark columns on the left or right side of the image sensor as a dark reference. Under normal circumstances use only the center 20 columns of the 22 column dark reference due to potential light leakage. An electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the individual silicon photodiodes. These photoelectrons are collected locally by the formation of potential wells at each photo-site. Below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non-linearly dependent on wavelength. When the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. Dummy Pixels Within each horizontal shift register there are 11 leading additional shift phases. These pixels are designated as dummy pixels and should not be used to determine a dark reference level. In addition, there is one dummy row of pixels at the top and bottom of the image. ESD Protection Adherence to the power-up and power-down sequence is critical. Failure to follow the proper power-up and power-down sequences may cause damage to the sensor. See Power-Up and Power-Down Sequence section. Active Buffer Pixels 12 unshielded pixels adjacent to any leading or trailing dark reference regions are classified as active buffer pixels. These pixels are light sensitive but are not tested for defects and non-uniformities. www.onsemi.com 3 KAI-29052 Bayer Color Filter Pattern H2Bd H2Sd H1Bd H1Sd FDGcd SUB FDGcd H2Bc H2Sc H1Bc H1Sc RDc Rc RDd Rd OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO VDDc VOUTc 1 10 22 12 8 3288 3288 VDDd VOUTd 12 8 22 10 1 FLD 22 12 GND OGc H2SLc B G G R V1T V2T V3T V4T GND OGd H 2SLd B G G R V1T V2T V3T V4T DevID ESD V1B V2B V3B V4B 6576 (H) y 4384 (V) 5.5 mm y 5.5 mm Pixels 22 12 12 22 ESD OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO B G G R B G G R 12 Buffer 22 Dark FLD RDa Ra VDDa VOUTa 1 10 22 12 8 3288 RDb Rb = V1 a H 1S) 3288 VDDb VOUTb 12 8 22 10 1 GND OGb H2SLb H2Bb H2Sb H1Bb H1Sb FDGab SUB FDGab H2Ba H2Sa H1Ba H1Sa GND OGa H2SLa (Last VCCD Phase V 1B V 2B V 3B V 4B Figure 3. Bayer Color Filter Pattern Sparse Color Filter Pattern H 2B d H 2S d H 1B d H 1S d FDGcd SUB FDGcd H 2B c H 2S c H 1B c H 1S c RDc RDd Rc Rd VDDc VOUTc VDDd VOUTd OOOOOOOOOOOOOOOO 1 10 22 12 8 3288 3288 12 8 22 10 1 FLD 22 GND OGc H 2SLc GND OGd H 2SLd 12 G P B P V 1T V 2T V 3T V 4T P G P B R P G P P R P G P B P G P G P B R P G P P R P V 1T V 2T V 3T V 4T G DevID ESD 22 6576 (H) y 4384 (V) 5.5 mm y 5.5 mm Pixels 12 V 1B V 2B V 3B V 4B G P B P P G P B R P G P P R P G 12 G P B P P G P B R P G P 22 ESD V 1B V 2B V 3B V 4B P R P G OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO 12 Buffer RDa Ra VDDa VOUTa 1 10 22 12 8 (Last VCCD Phase 3288 = V1 a H 1S) 3288 H 2B b H 2S b FDGab H 1B b H 1S b SUB FDGab H 2B a H 2S a H 1B a H 1S a GND OGa H 2SLa 22 Dark FLD Figure 4. Sparse Color Filter Pattern www.onsemi.com 4 12 8 22 10 1 RDb Rb VDDb VOUTb GND OGb H 2SLb KAI-29052 PHYSICAL DESCRIPTION Pin Description and Device Orientation V3T V1T VDDd GND Rd H2SLd H1Bd H2Sd N/C SUB H2Sc H1Bc H2SLc Rc GND V1T VDDc V3T 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 DevID ESD RDb V4B OGb V2B RDd H2Bb V4T OGd H1Sb V2T H2Bd VOUTd H1Sd FDGab FDGab FDGcd H1Sa FDGcd H1Sc OGa H2Ba OGc RDa H2Bc RDc VOUTc V2T V4T ESD Pixel (1,1) www.onsemi.com 5 V3B Figure 5. Package Pin Description (Top View) V1B Ra VDDb GND GND VDDa Rb V1B VOUTb V3B H2SLb 9 11 13 15 17 19 21 23 25 27 29 31 33 35 H1Bb 7 H2Sb 5 N/C 3 SUB 1 H2Sa VOUTa 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 H2SLa V2B 6 H1Ba V4B 4 KAI-29052 Table 4. PIN DESCRIPTION Pin Name 1 V3B Description Vertical CCD Clock, Phase 3, Bottom Pin Name 72 ESD ESD Protection Disable Description 71 V3T Vertical CCD Clock, Phase 3, Top 3 V1B Vertical CCD Clock, Phase 1, Bottom 70 V4T Vertical CCD Clock, Phase 4, Top 4 V4B Vertical CCD Clock, Phase 4, Bottom 69 V1T Vertical CCD Clock, Phase 1, Top 5 VDDa Output Amplifier Supply, Quadrant a 68 V2T Vertical CCD Clock, Phase 2, Top 6 V2B Vertical CCD Clock, Phase 2, Bottom 67 VDDc Output Amplifier Supply, Quadrant c 7 GND Ground 66 VOUTc Video Output, Quadrant c 8 VOUTa Video Output, Quadrant a 65 GND Ground 9 Ra Reset Gate, Quadrant a 64 RDc Reset Drain, Quadrant c 10 RDa Reset Drain, Quadrant a 63 Rc Reset Gate, Quadrant c 11 H2SLa Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant a 62 OGc Output Gate, Quadrant c 61 H2SLc Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant c 12 OGa Output Gate, Quadrant a 13 H1Ba Horizontal CCD Clock, Phase 1, Barrier, Quadrant a 60 H2Bc Horizontal CCD Clock, Phase 2, Barrier, Quadrant c 14 H2Ba Horizontal CCD Clock, Phase 2, Barrier, Quadrant a 59 H1Bc Horizontal CCD Clock, Phase 1, Barrier, Quadrant c 15 H2Sa Horizontal CCD Clock, Phase 2, Storage, Quadrant a 58 H1Sc Horizontal CCD Clock, Phase 1, Storage, Quadrant c 16 H1Sa Horizontal CCD Clock, Phase 1, Storage, Quadrant a 57 H2Sc Horizontal CCD Clock, Phase 2, Storage, Quadrant c 17 SUB Substrate 56 FDGcd 18 FDGab Fast Line Dump Gate, Bottom 55 N/C No Connect 54 FDGcd Fast Line Dump Gate, Bottom 53 SUB Substrate Fast Line Dump Gate, Top No Connect 19 N/C 20 FDGab 21 H2Sb Horizontal CCD Clock, Phase 2, Storage, Quadrant b 52 H1Sd Horizontal CCD Clock, Phase 1, Storage, Quadrant d 22 H1Sb Horizontal CCD Clock, Phase 1, Storage, Quadrant b 51 H2Sd Horizontal CCD Clock, Phase 2, Storage, Quadrant d 23 H1Bb Horizontal CCD Clock, Phase 1, Barrier, Quadrant b 50 H2Bd Horizontal CCD Clock, Phase 2, Barrier, Quadrant d 24 H2Bb Horizontal CCD Clock, Phase 2, Barrier, Quadrant b 49 H1Bd Horizontal CCD Clock, Phase 1, Barrier, Quadrant d 25 H2SLb Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant b 48 OGd Output Gate, Quadrant b 47 H2SLd 26 Fast Line Dump Gate, Top Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant d OGb Output Gate, Quadrant b 27 Rb Reset Gate, Quadrant b 46 RDd Reset Drain, Quadrant d 28 RDb Reset Drain, Quadrant b 45 Rd Reset Gate, Quadrant d 29 GND Ground 44 VOUTd 30 VOUTb Video Output, Quadrant b 43 GND Ground 31 VDDb Output Amplifier Supply, Quadrant b 42 V2T Vertical CCD Clock, Phase 2, Top 32 V2B Vertical CCD Clock, Phase 2, Bottom 41 VDDd 33 V1B Vertical CCD Clock, Phase 1, Bottom 40 V4T Vertical CCD Clock, Phase 4, Top 34 V4B Vertical CCD Clock, Phase 4, Bottom 39 V1T Vertical CCD Clock, Phase 1, Top 35 V3B Vertical CCD Clock, Phase 3, Bottom 38 DevID 36 ESD ESD Protection Disable 37 V3T 1. Like named pins are internally connected and should have a common drive signal. 2. N/C pins (19, 55) should be left floating. www.onsemi.com 6 Video Output, Quadrant d Output Amplifier Supply, Quadrant d Device Identification Vertical CCD Clock, Phase 3, Top KAI-29052 IMAGING PERFORMANCE Table 5. TYPICAL OPERATION CONDITIONS (Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.) Condition Description Light Source (Note 1) Continuous Red, Green and Blue LED Illumination Operation Nominal Operating Voltages and Timing 1. For monochrome sensor, only green LED used. Table 6. SPECIFICATIONS Symbol Min. Nom. Max. Unit Sampling Plan Temperature Tested at (5C) DSNU - - 5 mVpp Die 27, 40 - 2 5 %rms Die 27, 40 PRNU - 10 30 %pp Die 27, 40 Maximum Photo-response Non-linearity (Note 2) NL - 2 - % Design Maximum Gain Difference Between Outputs (Note 2) DG - 10 - % Design Maximum Signal Error due to Non-linearity Differences (Note 2) DNL - 1 - % Design Horizontal CCD Charge Capacity HNe - 50 - ke- Design Design Die Description ALL CONFIGURATIONS Dark Field Global Non-uniformity Bright Field Global Non-uniformity (Note 1) Bright Field Global Peak to Peak Non-uniformity (Note 1) Vertical CCD Charge Capacity VNe - 40 - ke- Photodiode Charge Capacity (Note 3) PNe - 20 - ke- Horizontal CCD Charge Transfer Efficiency HCTE 0.999995 0.999999 - Die Vertical CCD Charge Transfer Efficiency VCTE 0.999995 0.999999 - Die Photodiode Dark Current IPD - 7 70 e/p/s Die 40 Vertical CCD Dark Current IVD - 140 400 e/p/s Die 40 - 10 e- Design Image Lag Lag - Anti-blooming Factor XAB 300 - - Vertical Smear Smr - -100 - dB Design Read Noise (Note 4) ne-T - 10 - e-rms Design Dynamic Range (Notes 4, 5) DR - 66 - dB Design Output Amplifier DC Offset VODC - 9.4 - V Die Output Amplifier Bandwidth (Note 6) f-3db - 250 - MHz Die Output Amplifier Impedance ROUT - 127 - W Die - mV/e- Design Output Amplifier Sensitivity DV/DN - 35 www.onsemi.com 7 27, 40 Design 27, 40 27, 40 KAI-29052 Table 6. SPECIFICATIONS Description Symbol Min. Nom. Max. Unit Sampling Plan Temperature Tested at (5C) KAI-29052-AXA AND KAI-29052-QXA CONFIGURATIONS Peak Quantum Efficiency QEMAX - 43 - % Design Peak Quantum Efficiency Wavelength lQE - 540 - nm Design Quantum Efficiency (850 nm) QEMAX - 12 - nm Design Peak Quantum Efficiency (920 nm) QEMAX - 5 - nm Design % Design nm Design KAI-29052-FBA AND KAI-29052-QBA GEN2 COLOR CONFIGURATIONS Peak Quantum Efficiency Blue Green Red QEMAX Peak Quantum Efficiency Wavelength Blue Green Red lQE - - - - - - 37 40 39 480 540 620 - - - - - - 1. Per color 2. Value is over the range of 10% to 90% of photodiode saturation. 3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such that the photodiode charge capacity is 700 mV. 4. At 40 MHz. 5. Uses 20 LOG (PNe / ne-T). 6. Assumes 5 pF load. www.onsemi.com 8 KAI-29052 TYPICAL PERFORMANCE CURVES Quantum Efficiency Monochrome with Microlens 0.50 0.45 0.40 Absolute Quantum Efficiency Measured with AR coated cover glass 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 300 350 400 450 500 550 600 650 700 750 800 850 900 Wavelength (nm) KAI-29052 KAI-29050 Figure 6. Monochrome with Microlens Quantum Efficiency www.onsemi.com 9 950 1000 1050 1100 KAI-29052 Color (Bayer RGB) with Microlens 0.50 Measured with AR coated cover glass 0.45 Absolute Quantum Efficiency 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 Wavelength (nm) KAI-29052 Red KAI-29052 Green KAI-29052 Blue KAI-29050 Red KAI-29050 Green KAI-29050 Blue Figure 7. Color (Bayer RGB) with Microlens Quantum Efficiency Color (Sparse FCA) with Microlens 0.50 Measured with AR coated cover glass 0.45 Absolute Quantum Efficiency 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 Wavelength (nm) Pan Red Green Blue Figure 8. Color (Sparse CFA) with Microlens Quantum Efficiency www.onsemi.com 10 KAI-29052 Angular Quantum Efficiency For the curves marked "Horizontal", the incident light angle is varied in a plane parallel to the HCCD. For the curves marked "Vertical", the incident light angle is varied in a plane parallel to the VCCD. Monochrome with Microlens Relative Quantum Efficiency (%) 100 90 Vertical 80 Horizontal 70 60 50 40 30 20 10 0 -40 -30 -20 -10 0 10 20 30 40 Angle (Degrees) Figure 9. Monochrome with Microlens Angular Quantum Efficiency Dark Current vs. Temperature 10000 Photodiode Dark Current (e/s/pixel) 1000 VCCD 100 10 1 0.1 1000/T (K) 2.9 3 3.1 3.2 3.3 3.4 T (5C) 72 60 50 40 30 21 Figure 10. Dark Current vs. Temperature www.onsemi.com 11 KAI-29052 Power - Estimated 2.5 Single Dual Quad Power (W) 2.0 1.5 1.0 0.5 0.0 10 15 20 25 30 35 40 HCCD Frequency (MHz) Figure 11. Power Frame Rates 5.0 5.0 Single Frame Rate (fps) 4.5 Dual (Left/Right) Quad 4.5 4.0 4.0 3.5 3.5 3.0 3.0 2.5 2.5 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 10 15 20 25 30 HCCD Frequency (MHz) Figure 12. Frame Rates www.onsemi.com 12 35 40 KAI-29052 DEFECT DEFINITIONS Table 7. OPERATION CONDITIONS FOR DEFECT TESTING AT 405C Description 1. 2. 3. 4. Condition Operational Mode Two Outputs, using VOUTa and VOUTc, Continuous Readout HCCD Clock Frequency 10 MHz Pixels Per Line (Note 1) 6800 Lines Per Frame (Note 2) 2320 Line Time 715.7 ms Frame Time 1660.5 ms Photodiode Integration Time (PD_Tint) Mode A: PD_Tint = Frame Time = 1660.5 ms, No Electronic Shutter Used VCCD Integration Time (Note 3) 1593.1 ms Temperature 40C Light Source (Note 4) Continuous Red, Green and Blue LED Illumination Operation Nominal Operating Voltages and Timing Horizontal overclocking used. Vertical overclocking used. VCCD Integration Time = 2226 lines x Line Time, which is the total time a pixel will spend in the VCCD registers. For monochrome sensor, only the green LED is used. Table 8. DEFECT DEFINITIONS FOR TESTING AT 405C Description Definition Grade 1 Grade 2 Mono Grade 2 Color Major Dark Field Defective Bright Pixel (Note 1) PD_Tint = Mode A Defect 565 mV 270 540 540 Major Bright Field Defective Dark Pixel (Note 1) Defect 12% Minor Dark Field Defective Bright Pixel PD_Tint = Mode A Defect 282 mV 2700 5400 5400 Cluster Defect (Note 2) A group of 2 to 19 contiguous major defective pixels, but no more than 4 adjacent defects horizontally 20 N/A N/A Cluster Defect (Note 2) A group of 2 to 38 contiguous major defective pixels, but no more than 5 adjacent defects horizontally N/A 50 50 Column Defect (Note 2) A group of more than 10 contiguous major defective pixels along a single column 0 7 27 1. For the color devices (KAI-29052-CXA and KAI-29052-QXA), a bright field defective pixel deviates by 12% with respect to pixels of the same color. 2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects). www.onsemi.com 13 KAI-29052 Table 9. OPERATION CONDITIONS FOR DEFECT TESTING AT 275C Description 1. 2. 3. 4. Condition Operational Mode Two Outputs, using VOUTa and VOUTc, Continuous Readout HCCD Clock Frequency 10 MHz Pixels Per Line (Note 1) 6800 Lines Per Frame (Note 2) 2320 Line Time 715.7 ms Frame Time 1660.5 ms Photodiode Integration Time (PD_Tint) Mode A: PD_Tint = Frame Time = 1660.5 ms, No Electronic Shutter Used VCCD Integration Time (Note 3) 1593.1 ms Temperature 27C Light Source (Note 4) Continuous Red, Green and Blue LED Illumination Operation Nominal Operating Voltages and Timing Horizontal overclocking used. Vertical overclocking used. VCCD Integration Time = 2226 lines x Line Time, which is the total time a pixel will spend in the VCCD registers. For monochrome sensor, only the green LED is used. Table 10. DEFECT DEFINITIONS FOR TESTING AT 275C Description Definition Grade 1 Grade 2 Mono Grade 2 Color Major Dark Field Defective Bright Pixel (Note 1) PD_Tint = Mode A Defect 565 mV 270 540 540 Major Bright Field Defective Dark Pixel (Note 1) Defect 12% Cluster Defect (Note 2) A group of 2 to 19 contiguous major defective pixels, but no more than 4 adjacent defects horizontally 20 N/A N/A Cluster Defect (Note 2) A group of 2 to 38 contiguous major defective pixels, but no more than 5 adjacent defects horizontally N/A 50 50 Column Defect (Note 2) A group of more than 10 contiguous major defective pixels along a single column 0 7 27 1. For the color devices (KAI-29052-CXA and KAI-29052-QXA), a bright field defective pixel deviates by 12% with respect to pixels of the same color. 2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects). Defect Map defects are not included in the defect map. All defective pixels are reference to pixel 1, 1 in the defect maps. See Figure 13: Regions of interest for the location of pixel 1, 1. The defect map supplied with each sensor is based upon testing at an ambient (27_C) temperature. Minor point www.onsemi.com 14 KAI-29052 TEST DEFINITIONS Test Regions of Interest Overclocking Image Area ROI: Pixel (1, 1) to Pixel (6600, 4408) Active Area ROI: Pixel (13, 13) to Pixel (6588, 4396) Center ROI: Pixel (3251, 2155) to Pixel (3350, 2254) The test system timing is configured such that the sensor is overclocked in both the vertical and horizontal directions. See Figure 13 for a pictorial representation of the regions of interest. Only the Active Area ROI pixels are used for performance and defect tests. VOUTc 22 Dark Rows Pixel 1, 1 12 Buffer Rows 22 Dark Rows VOUTa Figure 13. Regions of Interest www.onsemi.com 15 Horizontal Overclock Active Pixels 22 Dark Columns 6576 x 4384 12 Buffer Columns 12 Buffer Columns Pixel 13, 13 22 Dark Columns 12 Buffer Rows KAI-29052 Tests Dark Field Global Non-Uniformity This test is performed under dark field conditions. The sensor is partitioned into 1536 sub regions of interest, each of which is 137 by 137 pixels in size. The average signal level of each of the 1536 sub regions of interest is calculated. The signal level of each of the sub regions of interest is calculated using the following formula: Signal of ROI[i] + (ROI Average in Counts * Horizontal Overclock Average in Counts) @ mV per Count [mV] Where i = 1 to 1536. During this calculation on the 1536 sub regions of interest, the maximum and minimum signal levels are found. The dark field global uniformity is then calculated as the maximum signal found minus the minimum signal level found. (eq. 2) Dark Field Global Non-Uniformity = Maximum Signal - Minimum Signal [mVpp] Global Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 490 V). Prior to this test being performed Global Non-Uniformity + 100 @ (eq. 1) the substrate voltage has been set such that the charge capacity of the sensor is 700 mV. Global non-uniformity is defined as: Active Area Standard Deviation Active Area Signal Global Peak to Peak Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 490 mV). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 700 mV. The sensor is partitioned (eq. 3) [%rms] into 1536 sub regions of interest, each of which is 137 by 137 pixels in size. The average signal level of each of the 1536 sub regions of interest (ROI) is calculated. The signal level of each of the sub regions of interest is calculated using the following formula: Signal of ROI[i] + (ROI Average in Counts * Horizontal Overclock Average in Counts) @ mV per Count [mV] Where i = 1 to 1536. During this calculation on the 1536 sub regions of interest, the maximum and minimum signal levels (eq. 4) are found. The global peak to peak uniformity is then calculated as: Global Peak to Peak Non-Uniformity + 100 @ Maximum Signal * Minimum Signal Active Area Signal [%pp] (eq. 5) Bright Field Defect Test This test is performed with the imager illuminated to a level such that the output is at approximately 490 mV. Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 700 mV. The average signal level of all active pixels is found. The dark threshold is set as: Dark Field Defect Test This test is performed under dark field conditions. The sensor is partitioned into 1536 sub regions of interest, each of which is 137 by 137 pixels in size. In each region of interest, the median value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the defect threshold specified in the "Defect Definitions" section. Dark Defect Threshold = Active Area Signal @ Threshold (eq. 6) * Region of interest #1 selected. This region of interest is The sensor is then partitioned into 1536 sub regions of interest, each of which is 137 by 137 pixels in size. In each region of interest, the average value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified. Example for major bright field defective pixels: * Average value of all active pixels is found to be 490 mV * Dark defect threshold: 490 mV 12% = 59 mV * pixels 13, 13 to pixels 149, 149. Median of this region of interest is found to be 495 mV. Any pixel in this region of interest that is (495 - 59 mV) 436 mV in intensity will be marked defective. All remaining 1536 sub regions of interest are analyzed for defective pixels in the same manner. www.onsemi.com 16 KAI-29052 OPERATION Table 11. ABSOLUTE MAXIMUM RATINGS Description Symbol Minimum Maximum Unit Operating Temperature (Note 1) TOP -50 70 C Humidity (Note 2) RH 5 90 % Output Bias Current (Note 3) IOUT - 60 mA CL - 10 pF Off-Chip Load Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Noise performance will degrade at higher temperatures. 2. T = 25C. Excessive humidity will degrade MTTF. 3. Total for all outputs. Maximum current is -15 mA for each output. Avoid shorting output pins to ground or any low impedance source during operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity). Table 12. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND Description VDDa, VOUTa (Note 1) Minimum Maximum Unit -0.4 17.5 V -0.4 15.5 V V1B, V1T ESD - 0.4 ESD + 24.0 V V2B, V2T, V3B, V3T, V4B, V4T ESD - 0.4 ESD + 14.0 V FDGab, FDGcd ESD - 0.4 ESD + 15.0 V H1Sa, H1Ba, H2Sa, H2Ba, H2SLa, Ra OGa (Note 1) ESD - 0.4 ESD + 14.0 V RDa (Note 1) ESD -10.0 0.0 V SUB (Note 2) -0.4 40.0 V 1. a denotes a, b, c or d. 2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions - AND9183/D. www.onsemi.com 17 KAI-29052 Power-Up and Power-Down Sequence Adherence to the power-up and power-down sequence is critical. Failure to follow the proper power-up and power-down sequences may cause damage to the sensor. Do Not Pulse the Electronic Shutter until ESD is Stable V+ VDD SUB Time ESD V- HCCD VCCD Low and FDG Low Activate All Other Biases when ESD is Stable and Sub is above 3 V Figure 14. Power-Up and Power-Down Sequence 5. The image sensor can be protected from an accidental improper ESD voltage by current limiting the SUB current to less than 10 mA. SUB and VDD must always be greater than GND. ESD must always be less than GND. Placing diodes between SUB, VDD, ESD and ground will protect the sensor from accidental overshoots of SUB, VDD, and ESD during power-up and power-down. See figures shown below. Warnings Regarding Power-Up and Power-Down 1. Activate all other biases when ESD is stable and SUB is above 3 V. 2. Do not pulse the electronic shutter until ESD is stable. 3. VDD cannot be +15 V when SUB is 0 V. 4. The VCCD clock waveform must not have a negative overshoot more than 0.4 V below the ESD voltage. 0.0 V ESD ESD - 0.4 V All VCCD and FDG Clocks Absolute Maximum Overshoot of 0.4 V Figure 15. VCCD Overshoots VDDa SUB GND ESD Figure 16. External Diode Protection www.onsemi.com 18 KAI-29052 DC Bias Operating Conditions Table 13. DC BIAS OPERATING CONDITIONS Pins Symbol Min. Nom. Max. Unit Max. DC Current Reset Drain (Note 1) RDa RD 11.8 12.0 12.2 V 10 mA Output Gate (Note 1) OGa OG -2.2 -2.0 -1.8 V 10 mA Output Amplifier Supply (Notes 1, 2) VDDa VDD 14.5 15.0 15.5 V 11.0 mA Ground GND GND 0.0 0.0 0.0 V -1.0 mA Substrate (Notes 3, 8) SUB VSUB 5.0 VAB VDD V 50 mA ESD Protection Disable (Notes 6, 7) ESD ESD -9.2 -9.0 -8.8 V 50 mA Output Bias Current (Notes 1, 4, 5) VOUTa IOUT -3.0 -7.0 -10.0 mA - Description VDDa RDa Ra 1. a denotes a, b, c or d. 2. The maximum DC current is for one output. IDD = IOUT + ISS. See Figure 17. 3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such that the photodiode charge capacity is the nominal PNe (see Specifications). 4. An output load sink must be applied to each VOUT pin to activate each output amplifier. 5. Nominal value required for 40 MHz operation per output. May be reduced for slower data rates and lower noise. 6. Adherence to the power-up and power-down sequence is critical. See Power-Up and Power-Down Sequence section. 7. ESD maximum value must be less than or equal to V1_L + 0.4 V and V2_L + 0.4 V. 8. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions - AND9183/D. IDD HCCD Floating Diffusion IOUT OGa VOUTa ISS Source Follower #1 Figure 17. Output Amplifier www.onsemi.com 19 Source Follower #2 Source Follower #3 KAI-29052 AC Operating Conditions Table 14. CLOCK LEVELS Description Vertical CCD Clock, Phase 1 Pins (Note 1) Symbol Level Min. Nom. Max. Unit V1B, V1T V1_L Low -9.2 -9.0 -8.8 V V1_M Mid -0.2 0.0 0.2 180 nF (Note 6) V1_H High 12.8 13.0 14.0 V2_L Low -9.2 -9.0 -8.8 V V2_H High -0.2 0.0 0.2 180 nF (Note 6) V3_L Low -9.2 -9.0 -8.8 V V3_H High -0.2 0.0 0.2 180 nF (Note 6) V4_L Low -9.2 -9.0 -8.8 V V4_H High -0.2 0.0 0.2 180 nF (Note 6) H1S_L Low -5.0 (Note 7) -4.4 -4.2 V 600 pF (Note 6) H1S_A Amplitude 4.2 4.4 5.0 (Note 7) H1B_L Low -5.0 (Note 7) -4.4 -4.2 V 400 pF (Note 6) H1B_A Amplitude 4.2 4.4 5.0 (Note 7) H2S_L Low -5.0 (Note 7) -4.4 -4.2 V 580 pF (Note 6) H2S_A Amplitude 4.2 4.4 5.0 (Note 7) H2B_L Low -5.0 (Note 7) -4.4 -4.2 V 400 pF (Note 6) H2B_A Amplitude 4.2 4.4 5.0 (Note 7) V 20 pF (Note 6) V 16 pF (Note 6) Vertical CCD Clock, Phase 2 V2B, V2T Vertical CCD Clock, Phase 3 V3B, V3T Vertical CCD Clock, Phase 4 V4B, V4T Horizontal CCD Clock, Phase 1 Storage Horizontal CCD Clock, Phase 1 Barrier Horizontal CCD Clock, Phase 2 Storage Horizontal CCD Clock, Phase 2 Barrier Horizontal CCD Clock, Last Phase (Note 3) Reset Gate Electronic Shutter (Notes 5, 8) Fast Line Dump Gate H1Sa H1Ba H2Sa H2Ba H2SLa Capacitance (Note 2) H2SL_L Low -5.2 -5.0 -4.8 H2SL_A Amplitude 4.8 5.0 5.2 R_L (Note 4) Low -3.5 -2.0 -1.5 R_H High 2.5 3.0 4.0 SUB VES High 29.0 30.0 40.0 V 12 pF (Note 6) FDGa FDG_L Low -9.2 -9.0 -8.8 V FDG_H High 4.5 5.0 5.5 50 pF (Note 6) Ra 1. 2. 3. 4. 5. 6. 7. a denotes a, b, c or d. Capacitance is total for all like named pins. Use separate clock driver for improved speed performance. Reset low should be set to -3 volts for signal levels greater than 40,000 electrons. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions - AND9183/D. Capacitance values are estimated. If the minimum horizontal clock low level is used (-5.0 V), then the maximum horizontal clock amplitude should be used (5 V amplitude) to create a -5.0 V to 0.0 V clock. 8. Figure 18 shown below shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock are referenced to ground. VES VSUB GND GND Figure 18. Substrate and Electron Shutter Reference to Ground www.onsemi.com 20 KAI-29052 Device Identification The device identification pin (DevID) may be used to determine which ON Semiconductor 5.5 micron pixel interline CCD sensor is being used. Table 15. DEVICE IDENTIFICATION Description Device Identification (Notes 1, 2) Pins Symbol Min. Nom. Max. Unit Max. DC Current DevID DevID 200,000 300,000 400,000 W 50 mA 1. If the Device Identification is not used, it may be left disconnected. 2. After Device Identification resistance has been read during camera initialization, it is recommended that the circuit be disabled to prevent localized heating of the sensor due to current flow through the R_DeviceID resistor. Recommended Circuit Note that V1 must be a different value than V2. V1 V2 R_external DevID ADC R_DeviceID GND KAI-29052 Figure 19. Device Identification Recommended Circuit www.onsemi.com 21 KAI-29052 TIMING Table 16. REQUIREMENTS AND CHARACTERISTICS Description Symbol Min. Nom. Max. Unit Notes Photodiode Transfer tPD 6 - - ms VCCD Leading Pedestal t3P 16 - - ms VCCD Trailing Pedestal t3D 16 - - ms VCCD Transfer Delay tD 4 - - ms VCCD Transfer tV 8 - - ms VVCR 75 - 100 % 1 1, 2 VCCD Clock Cross-Over VCCD Rise, Fall Times tVR, tVF 5 - 10 % FDG Delay tFDG 2 - - ms HCCD Delay tHS 1 - - ms HCCD Transfer te 25.0 29.4 - ns Shutter Transfer tSUB 1 - - ms Shutter Delay tHD 1 - - ms Reset Pulse tR 2.5 - - ns Reset - Video Delay tRV - 2.2 - ns H2SL - Video Delay tHV - 3.1 - ns tLINE 96.3 110.0 - ms 179.4 208.7 - 213.5 246.1 - 427.0 492.2 - Dual HCCD Readout 795.1 925.2 - Single HCCD Readout Line Time Frame Time tFRAME 1. Refer to Figure 24: VCCD Clock Rise Time, Fall Time, and Edge Alignment. 2. Relative to the pulse width. www.onsemi.com 22 Dual HCCD Readout Single HCCD Readout ms Quad HCCD Readout KAI-29052 Timing Diagrams table below. The patterns are defined in Figure 20 and Figure 21. Contact ON Semiconductor Application Engineering for other readout modes. The timing sequence for the clocked device pins may be represented as one of seven patterns (P1-P7) as shown in the Table 17. TIMING DIAGRAMS Device Pin Quad Readout Dual Readout VOUTa, VOUTb Dual Readout VOUTa, VOUTc Single Readout VOUTa V1T P1T P1B P1T P1B V2T P2T P4B P2T P4B V3T P3T P3B P3T P3B V4T P4T P2B P4T P2B V1B P1B V2B P2B V3B P3B V4B P4B H1Sa P5 H1Ba P6 H2Sa (Note 2) H2Ba Ra P7 P5 H1Sb P5 H1Bb P6 P6 H2Sb (Note 2) P6 H2Bb P5 Rb P7 P7 (Note 1) or Off (Note 3) P7 (Note 1) or Off (Note 3) P5 P5 (Note 1) or Off (Note 3) P5 P5 (Note 1) or Off (Note 3) P6 P6 (Note 1) or Off (Note 3) P6 P6 (Note 1) or Off (Note 3) Rc P7 P7 (Note 1) or Off (Note 3) P7 P7 (Note 1) or Off (Note 3) H1Sd P5 P5 (Note 1) or Off (Note 3) P5 P5 (Note 1) or Off (Note 3) H1Sc H1Bc H2Sc (Note 2) H2Bc H1Bd H2Sd (Note 2) P6 P6 P6 (Note 1) or Off (Note 3) H2Bd P6 (Note 1) or Off (Note 3) P6 P5 Rd P7 P7 (Note 1) or Off (Note 3) P7 (Note 1) or Off (Note 3) P7 (Note 1) or Off (Note 3) #Lines/Frame (Minimum) 2226 4452 2226 4452 #Pixels/Line (Minimum) 3333 6666 1. For optimal performance of the sensor. May be clocked at a lower frequency. If clocked at a lower frequency, the frequency selected should be a multiple of the frequency used on the a and b register. 2. H2SLx follows the same pattern as H2Sx. For optimal speed performance, use a separate clock driver. 3. Off = +5 V. Note that there may be operating conditions (high temperature and/or very bright light sources) that will cause blooming from the unused c/d register into the image area. www.onsemi.com 23 KAI-29052 Photodiode Transfer Timing A row of charge is transferred to the HCCD on the falling edge of V1 as indicated in the P1 pattern below. Using this timing sequence, the leading dummy row or line is combined with the first dark row in the HCCD. The "Last Line" is dependent on readout mode - either 2226 or 4452 minimum counts required. It is important to note that, in 1 Pattern 2 tD 3 t3P 4 tPD 5 t3D general, the rising edge of a vertical clock (patterns P1-P4) should be coincident or slightly leading a falling edge at the same time interval. This is particularly true at the point where P1 returns from the high (3rd level) state to the mid-state when P4 transitions from the low state to the high state. 6 tD tV tV P1T tV/2 P2T tV/2 tV/2 tV/2 P3T P4T tV P1B tV/2 tV tV/2 P2B P3B P4B tHS tHS Last Line P5 L1 + Dummy Line L2 P6 P7 Figure 20. Photodiode Transfer Timing P6 pattern). The number of pixels in a row is dependent on readout mode - either 3333 or 6666 minimum counts required. Line and Pixel Timing Each row of charge is transferred to the output, as illustrated below, on the falling edge of H2SL (indicated as tLINE Pattern tV P1T P1B tV tHS P5 P6 te/2 te tR P7 VOUT Pixel 1 Pixel 34 Pixel n Figure 21. Line and Pixel Timing www.onsemi.com 24 KAI-29052 Pixel Timing Detail P5 P6 P7 VOUT tHV tRV Figure 22. Pixel Timing Detail Frame/Electronic Shutter Timing The SUB pin may be optionally clocked to provide electronic shuttering capability as shown below. The resulting photodiode integration time is defined from the falling edge of SUB to the falling edge of V1 (P1 pattern). Pattern tFRAME P1T/B tHD tSUB SUB P6 tINT tHD Figure 23. Electronic Shutter Timing VCCD Clock Edge Alignment VVCR tV 90% 10% tVR tVF tV tVF tVR Figure 24. VCCD Clock Rise Time, Fall Time, and Edge Alignment www.onsemi.com 25 KAI-29052 Line and Pixel Timing - Vertical Binning by 2 tV tV tV tHS P1T P2T P3T P4T P1B P2B P3B P4B tHS P5 P6 P7 VOUT Pixel 1 Pixel n Pixel 34 Figure 25. Line and Pixel Timing - Vertical Binning by 2 Fast Line Dump Timing The FDG pins may be optionally clocked to efficiently remove unwanted lines in the image resulting for increased Clock frame rates at the expense of resolution. Below is an example of a 2 line dump sequence followed by a normal readout line. tFDG V1B V2B FDGab H1S tFDG V1T V2T FDGcd H1S Figure 26. Fast Line Dump Timing www.onsemi.com 26 KAI-29052 STORAGE AND HANDLING Table 18. STORAGE CONDITIONS Description Symbol Minimum Maximum Unit Storage Temperature (Note 1) TST -55 80 C Humidity (Note 2) RH 5 90 % 1. Long-term exposure toward the maximum temperature will accelerate color filter degradation. 2. T = 25C. Excessive humidity will degrade MTTF. For information on ESD and cover glass care and cleanliness, please download the Image Sensor Handling and Best Practices Application Note (AN52561/D) from www.onsemi.com. For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from www.onsemi.com. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from www.onsemi.com. For information on environmental exposure, please download the Using Interline CCD Image Sensors in High Intensity Lighting Conditions Application Note (AND9183/D) from www.onsemi.com. For information on Standard terms and Conditions of Sale, please download Terms and Conditions from www.onsemi.com. For information on soldering recommendations, please download the Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) from www.onsemi.com. www.onsemi.com 27 KAI-29052 MECHANICAL INFORMATION Completed Assembly Notes: 1. See Ordering Information for marking code. 2. Cover glass not to overhang package holes or outer ceramic edges. 3. Glass epoxy not to extend over image array. 4. No materials to interfere with clearance through package holes. 5. Units: IN [MM]. Figure 27. Completed Assembly (1 of 2) www.onsemi.com 28 KAI-29052 Notes: 1. Units: IN [MM]. Figure 28. Completed Assembly (2 of 2) www.onsemi.com 29 KAI-29052 Cover Glass Notes: 1. Substrate = Schott D263T eco 2. Dust, Scratch, Inclusion Specification: a. 20_m Max size in Zone A b. Zone A = 1.474 x 1.000 [16.43 x 10.08] Centered 3. MAR coated both sides 4. Spectral Transmission a. 350-365 nm: T 88% b. 365-405 nm: T 94% c. 405-450 nm: T 98% d. 450-650 nm: T 99% e. 650-690 nm: T 98% f. 690-770 nm: T 94% g. 770-870 nm: T 88% 5. Units: IN [MM] Figure 29. Cover Glass www.onsemi.com 30 KAI-29052 Cover Glass Transmission 100 90 80 Transmission (%) 70 60 50 40 30 20 10 0 200 300 400 500 600 700 800 900 Wavelength (nm) Figure 30. Cover Glass Transmission ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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