TL750M05QKVURQ1 - Texas Instruments

TL750Mxx-Q1, TL751Mxx-Q1

www.ti.com

SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011

AUTOMOTIVE LOW-DROPOUT VOLTAGE REGULATORS

Check for Samples: TL750Mxx-Q1,TL751Mxx-Q1

1FEATURES

•Qualified for Automotive Applications •Load-Dump Protection

•Low Dropout Voltage, Less Than 0.6 V at •Overvoltage Protection

750 mA •Internal Thermal Overload Protection

•Low Quiescent Current •Internal Overcurrent-Limiting Circuitry

•TTL- and CMOS-Compatible Enable on

TL751M Series

DESCRIPTION

The TL750M and TL751M series are low-dropout positive voltage regulators specifically designed for automotive

applications. The TL750M and TL751M series incorporate onboard overvoltage and current-limiting protection

circuitry to protect the devices and the regulated system. Both series are fully protected against load-dump and

reverse-battery conditions. Load-dump protection is up to a maximum of 60 V at the input of the device. Low

quiescent current, even during full-load conditions, makes the TL750M and TL751M series ideal for use in

applications that are permanently connected to the vehicle battery.

The TL750M and TL751M series offers 5-V, 8-V, and 12-V options. The TL751M series has the addition of an

enable (ENABLE) input. The ENABLE input gives complete control over power up, allowing sequential power up

or shutdown. When ENABLE is high, the regulator output is placed in the high-impedance state. The ENABLE

input is TTL and CMOS compatible.

The TL750Mxx and TL751Mxx are characterized for operation over the virtual junction temperature range –40°C

to 125°C.

AVAILABLE OPTIONS(1)

TJPACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING

NOM (V)

TO-263-3 –KTT Reel of 500 TL750M05QKTTRQ1 TL750M05Q1

5 V TO-252-3 –KVU Reel of 2500 TL750M05QKVURQ1 750M05Q

TO-263-3 –KTT Reel of 500 TL750M08QKTTRQ1 TL750M08Q1

8 V TO-252-3 –KVU Reel of 2500 TL750M08QKVURQ1 750M08Q

TO-263-3 –KTT Reel of 500 TL750M12QKTTRQ1 TL750M12Q1

12 V TO-252-3 –KVU Reel of 2500 TL750M12QKVURQ1 750M12Q

–40°C to 125°CTO-263-5 –KTT Reel of 500 TL751M05QKTTRQ1 TL751M05Q1

5 V TO-252-5 –KVU Reel of 2500 TL751M05QKVURQ1 751M05Q

TO-263-5 –KTT Reel of 500 TL751M08QKTTRQ1 TL751M08Q1

8 V TO-252-5 –KVU Reel of 2500 TL751M08QKVURQ1 751M08Q

TO-263-5 –KTT Reel of 500 TL751M12QKTTRQ1 TL751M12Q1

12 V TO-252-5 –KVU Reel of 2500 TL751M12QKVURQ1 751M12Q

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

OUTPUT

COMMON

INPUT

COMMOM

TL750M

KVU (TO-252-3) PACKAGE

(TOP VIEW)

TL751M

KTT (TO-263-5) PACKAGE

(TOP VIEW)

ENABLE

INPUT

OUTPUT

COMMOM

COMMON

ENABLE

TL751M

KVU (TO-252-5) PACKAGE

(TOP VIEW)

OUTPUT

INPUT

TL750M

KTT (TO-263-3) PACKAGE

(TOP VIEW)

OUTPUT

COMMON

INPUT

COMMON

COMMOM

COMMON

Enable

Bandgap

Current

Limiting

Overvoltage/

Thermal

Shutdown

ENABLE

OUTPUT

COMMON

INPUT

28 V

TL750Mxx-Q1, TL751Mxx-Q1

SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011

www.ti.com

NOTE: The COMMON terminal is in electrical contact with the mounting base.

NC –No internal connection

TL751Mxx FUNCTIONAL BLOCK DIAGRAM

TL750Mxx-Q1, TL751Mxx-Q1

www.ti.com

SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)(1)

Continuous input voltage 26 V

Transient input voltage (see Figure 4) 60 V

Continuous reverse input voltage –15 V

Transient reverse input voltage t = 100 ms –50 V

KTT package (3 pin) 26.9°C/W

θJA Package thermal impedance(2) (3) KTT package (5 pin) 26.5°C/W

KVU package 38.6°C/W

TJVirtual junction temperature range –40°C to 150°C

Tstg Storage temperature range –65°C to 150°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient

temperature is PD= (TJ(max) –TA)/θJA. Operating at the absolute maximum TJof 150°C can impact reliability. Due to variation in

individual device electrical characteristics and thermal resistance, the built-in thermal overload protection may be activated at power

levels slightly above or below the rated dissipation.

(3) The package thermal impedance is calculated in accordance with JESD 51.

THERMAL INFORMATION TL750M05

THERMAL METRIC(1) KTT UNITS

3 PINS

θJA Junction-to-ambient thermal resistance(2) 27.5

θJCtop Junction-to-case (top) thermal resistance(3) 43.2

θJB Junction-to-board thermal resistance(4) 17.3 °C/W

ψJT Junction-to-top characterization parameter(5) 2.8

ψJB Junction-to-board characterization parameter(6) 9.3

θJCbot Junction-to-case (bottom) thermal resistance(7) 0.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT

TL75xM05 6 26

VIInput voltage TL75xM08 9 26 V

TL75xM12 13 26

VIH High-level ENABLE input voltage TL751Mxx 2 15 V

VIL Low-level ENABLE input voltage TL751Mxx 0 0.8 V

IOOutput current TL75xMxx 750 mA

TJOperating virtual junction temperature TL75xMxx –40 125 °C

TL750Mxx-Q1, TL751Mxx-Q1

SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011

www.ti.com

TL751Mxx ELECTRICAL CHARACTERISTICS

VI= 14 V, IO= 300 mA, TJ= 25°CTL751Mxx

PARAMETER UNIT

TYP

Response time, ENABLE to output (start-up) 50 µs

TL750M05/TL751M05 ELECTRICAL CHARACTERISTICS

VI= 14 V, IO= 300 mA, ENABLE at 0 V for TL751M05, TJ=–40°C to 125°C (unless otherwise noted)(1)

TL750M05

TL751M05

PARAMETER TEST CONDITIONS UNIT

MIN TYP MAX

Output voltage VI= 6 V to 26 V 4.85 5 5.15 V

VI= 9 V to 16 V, IO= 250 mA 10 25

Line regulation mV

VI= 6 V to 26 V, IO= 250 mA 12 50

Power-supply ripple rejection VI= 8 V to 18 V, f = 120 Hz 55 dB

Load regulation IO= 5 mA to 750 mA 20 50 mV

IO= 500 mA, TJ= 25°C 0.5

Dropout voltage(2) V

IO= 750 mA, TJ= 25°C 0.65

IO= 750 mA 60 75

Current consumption mA

Iq= II–IOIO= 10 mA 5

Shutdown current (TL751M05 only) ENABLE VIH ≥2 V 200 µA

(1) Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be

taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor

on the output, with equivalent series resistance within the guidelines shown in Figure 4.

(2) Measured when the output voltage, VO, has dropped 100 mV from the nominal value obtained at VI= 14 V.

TL750M08/TL751M08 ELECTRICAL CHARACTERISTICS

VI= 14 V, IO= 300 mA, ENABLE at 0 V for TL751M08, TJ=–40°C to 125°C (unless otherwise noted)(1)

TL750M08

TL751M08

PARAMETER TEST CONDITIONS UNIT

MIN TYP MAX

Output voltage VI= 6 V to 26 V 7.76 8 8.24 V

VI= 10 V to 17 V, IO= 250 mA 12 40

Line regulation mV

VI= 9 V to 26 V, IO= 250 mA 15 68

Power-supply ripple rejection VI= 11 V to 21 V, f = 120 Hz 55 dB

Load regulation IO= 5 mA to 750 mA 24 80 mV

IO= 500 mA, TJ= 25°C 0.5

Dropout voltage(2) V

IO= 750 mA, TJ= 25°C 0.65

IO= 750 mA, TJ= 25°C 60 75

Current consumption mA

Iq= II–IOIO= 10 mA 5

Shutdown current (TL751M08 only) ENABLE VIH ≥2 V 200 µA

(1) Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be

taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor

on the output, with equivalent series resistance within the guidelines shown in Figure 4.

(2) Measured when the output voltage, VO, has dropped 100 mV from the nominal value obtained at VI= 14 V.

TL750Mxx-Q1, TL751Mxx-Q1

www.ti.com

SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011

TL750M12/TL751M12 ELECTRICAL CHARACTERISTICS

VI= 14 V, IO= 300 mA, ENABLE at 0 V for TL751M12, TJ=–40°C to 125°C (unless otherwise noted)(1)

TL750M12

TL751M12

PARAMETER TEST CONDITIONS UNIT

MIN TYP MAX

Output voltage VI= 13 V to 26 V 11.76 12 12.24 V

VI= 14 V to 19 V, IO= 250 mA 15 43

Line regulation mV

VI= 13 V to 26 V, IO= 250 mA 20 78

Power-supply ripple rejection VI= 13 V to 23 V, f = 120 Hz 50 55 dB

Load regulation IO= 5 mA to 750 mA 30 120 mV

IO= 500 mA, TJ= 25°C 0.5

Dropout voltage(2) V

IO= 750 mA, TJ= 25°C 0.6

IO= 750 mA, TJ= 25°C 60 75

Current consumption mA

Iq= II–IOIO= 10 mA 5

Shutdown current (TL751M12 only) ENABLE VIH ≥2 V 200 µA

(1) Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be

taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor

on the output, with equivalent series resistance within the guidelines shown in Figure 4.

(2) Measured when the output voltage, VO, has dropped 100 mV from the nominal value obtained at VI= 14 V.

Applied Load

Current

Load

Voltage

∆VL

∆IL

∆VL = ∆IL × ESR

TL750Mxx-Q1, TL751Mxx-Q1

SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011

www.ti.com

PARAMETER MEASUREMENT INFORMATION

The TL750Mxx and TL751Mxx are low-dropout regulators. The output capacitor value and the parasitic

equivalent series resistance (ESR) affect the bandwidth and stability of the control loop for these devices. For

this reason, the capacitor and ESR must be carefully selected for a given operating temperature and load range.

Figure 2 and Figure 3 can be used to establish the appropriate capacitance value and ESR for the best regulator

transient response.

Figure 2 shows the recommended range of ESR for a given load with a 10-µF capacitor on the output. Figure 2

also shows a maximum ESR limit of 2 Ωand a load-dependent minimum ESR limit.

For applications with varying loads, the lightest load condition should be chosen because it is the worst case.

Figure 3 shows the relationship of the reciprocal of ESR to the square root of the capacitance, with a minimum

capacitance limit of 10 µF and a maximum ESR limit of 2 Ω. This figure establishes the amount that the minimum

ESR limit shown in Figure 2 can be adjusted for different capacitor values. For example, where the minimum

load needed is 200 mA, Figure 2 suggests an ESR range of 0.8 Ωto2Ωfor 10 µF. Figure 3 shows that

changing the capacitor from 10 µF to 400 µF can change the ESR minimum by greater than 3/0.5 (or 6).

Therefore, the new minimum ESR value is 0.8/6 (or 0.13 Ω). This allows an ESR range of 0.13 Ωto2Ω,

achieving an expanded ESR range by using a larger capacitor at the output. For better stability in low-current

applications, a small resistance placed in series with the capacitor (see Table 1) is recommended, so that ESRs

better approximate those shown in Figure 2 and Figure 3.

Table 1. Compensation for Increased Stability at Low Currents

MANUFACTURER CAPACITANCE ESR TYP PART NUMBER ADDITIONAL RESISTANCE

AVX 15 µF 0.9 ΩTAJB156M010S 1 Ω

KEMET 33 µF 0.6 ΩT491D336M010AS 0.5 Ω

Figure 1.

2.5

0.4

0.3

0.2

0.1

00.10 0.2 0.3 0.4 0.5

IL- Load Current Rang e - A

This Region Not

Recommended for

Operation

CL= 10 µF

CI= 0.1 µF

f = 120 Hz

Equivalent Series Resistance (ESR) - &

0.5

Potential Instability Region

Min ESR

Boundary

Max ESR Boundary

Region of Best Stability

ÎÎÎÎÎÎÎÎÎÎÎÎ

0 1 2 3 4 54.53.52.51.50.5

0.01

0.015

0.02

0.025

0.03

0.035

0.04

ÏÏÏ

200 µF

ÏÏÏ

1000 µF

1/ESR

0.005

ÏÏÏ

400 µF

Not Recommended

Recommended Min ESR

Potential Instability

Region of

Best Stability

ÏÏÏ

100 µF

ÏÏÏ

22 µF

ÏÏÏ

10 µF

ÎÎ

Stability −

TL750Mxx-Q1, TL751Mxx-Q1

www.ti.com

SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011

OUTPUT CAPACITOR EQUIVALENT

SERIES RESISTANCE (ESR) STABILITY

vs vs

LOAD CURRENT RANGE EQUIVALENT SERIES RESISTANCE (ESR)

Figure 2. Figure 3.

0 100 200

300 400 500 600

V − Transient Input Voltage − V

TJ = 25°C

VI = 14 V + 46e(−t/0.230)

for t ≥ 5 ms

t − Time − ms

tr = 1 ms

00 2 4 6 8 10

− Output Voltage − V

12 14

VI − Input Voltage − V

IO = 10 mA

TJ = 25°C

TL75xM08

TL75xM05

TL750Mxx-Q1, TL751Mxx-Q1

SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011

www.ti.com

TYPICAL CHARACTERISTICS

Table 2. Table of Graphs

FIGURE

Transient input voltage vs Time 4

Output voltage vs Input voltage 5

IO= 10 mA 6

Input current vs Input voltage IO= 100 mA 7

Dropout voltage vs Output current 8

Quiescent current vs Output current 9

Load transient response 10

Line transient response 11

TRANSIENT INPUT VOLTAGE OUTPUT VOLTAGE

vs vs

TIME INPUT VOLTAGE

Figure 4. Figure 5.

00 2 4 6 8 10

120

140

12 14

100

180

200

160

− Input Current − mAII

VI − Input Voltage − V

IO = 10 mA

TJ = 25°C

TL75_M05

TL75_M08

200

100

00 2 4 6 8 10

300

350

12 14

250

150

VI − Input Voltage − V

IO = 100 mA

TJ = 25°C

− Input Current − mAII

TL75_M05

TL75_M08

200

150

125

100

0 50 100 150 200 250

250

300

225

175

IO − Output Current − mA

TJ = 25°C

Dropout Voltage − mV

0 20 40 60 80 100 150

IO − Output Current − mA

TJ = 25°C

VI = 14 V

− Quiescent Current − mA

250 350

TL750Mxx-Q1, TL751Mxx-Q1

www.ti.com

SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011

INPUT CURRENT INPUT CURRENT

vs vs

INPUT VOLTAGE INPUT VOLTAGE

Figure 6. Figure 7.

DROPOUT VOLTAGE QUIESCENT CURRENT

vs vs

OUTPUT CURRENT OUTPUT CURRENT

Figure 8. Figure 9.

200

− 100

− 200

0 50 100 150 200 250

100

150

100

t − Time − µs

− Output Current − mA

300 350

VI(NOM) = VO + 1 V

ESR = 2

CL = 10 µF

TJ = 25°C

− Output Voltage − mVVO

0 20 40 60 80 100 150 250 350

− Output Voltage − mVVO20 mV/DIV1 V/DIV

− Input Voltage − VVIN

t − Time − µs

VI(NOM) = VO + 1 V

ESR = 2

IL = 20 mA

CL = 10 µF

TJ = 25°C

TL750Mxx-Q1, TL751Mxx-Q1

SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011

www.ti.com

LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE

Figure 10. Figure 11.

PACKAGE OPTION ADDENDUM

www.ti.com 21-Apr-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

TL750M05QKTTRQ1 ACTIVE DDPAK/

TO-263 KTT 3 500 Green (RoHS

& no Sb/Br) CU SN Level-3-245C-168 HR

TL750M05QKVURQ1 ACTIVE PFM KVU 3 2500 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR

TL750M08QKVURQ1 ACTIVE PFM KVU 3 2500 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR

TL750M12QKTTRQ1 ACTIVE DDPAK/

TO-263 KTT 3 500 Green (RoHS

& no Sb/Br) CU SN Level-3-245C-168 HR

TL750M12QKVURQ1 ACTIVE PFM KVU 3 2500 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR

TL751M05QKTTRQ1 ACTIVE DDPAK/

TO-263 KTT 5 500 Green (RoHS

& no Sb/Br) CU SN Level-3-245C-168 HR

TL751M05QKVURQ1 ACTIVE PFM KVU 5 2500 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR

TL751M08QKTTRQ1 ACTIVE DDPAK/

TO-263 KTT 5 500 Green (RoHS

& no Sb/Br) CU SN Level-3-245C-168 HR

TL751M08QKVURQ1 ACTIVE PFM KVU 5 2500 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR

TL751M12QKTTRQ1 ACTIVE DDPAK/

TO-263 KTT 5 500 Green (RoHS

& no Sb/Br) CU SN Level-3-245C-168 HR

TL751M12QKVURQ1 ACTIVE PFM KVU 5 2500 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

PACKAGE OPTION ADDENDUM

www.ti.com 21-Apr-2012

Addendum-Page 2

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TL750M05-Q1, TL750M08-Q1, TL750M12-Q1, TL751M05-Q1 :

•Catalog: TL750M05, TL750M08, TL750M12, TL751M05

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TL750M05QKVURQ1 PFM KVU 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2

TL750M08QKVURQ1 PFM KVU 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2

TL750M12QKTTRQ1 DDPAK/

TO-263 KTT 3 500 330.0 24.4 10.6 15.8 4.9 16.0 24.0 Q2

TL750M12QKVURQ1 PFM KVU 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2

TL751M05QKVURQ1 PFM KVU 5 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2

TL751M08QKTTRQ1 DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.6 15.8 4.9 16.0 24.0 Q2

TL751M08QKVURQ1 PFM KVU 5 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2

TL751M12QKTTRQ1 DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.6 15.8 4.9 16.0 24.0 Q2

TL751M12QKVURQ1 PFM KVU 5 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Apr-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TL750M05QKVURQ1 PFM KVU 3 2500 340.0 340.0 38.0

TL750M08QKVURQ1 PFM KVU 3 2500 340.0 340.0 38.0

TL750M12QKTTRQ1 DDPAK/TO-263 KTT 3 500 340.0 340.0 38.0

TL750M12QKVURQ1 PFM KVU 3 2500 340.0 340.0 38.0

TL751M05QKVURQ1 PFM KVU 5 2500 340.0 340.0 38.0

TL751M08QKTTRQ1 DDPAK/TO-263 KTT 5 500 340.0 340.0 38.0

TL751M08QKVURQ1 PFM KVU 5 2500 340.0 340.0 38.0

TL751M12QKTTRQ1 DDPAK/TO-263 KTT 5 500 340.0 340.0 38.0

TL751M12QKVURQ1 PFM KVU 5 2500 340.0 340.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Apr-2012

Pack Materials-Page 2

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