MC33178, MC33179 Low Power, Low Noise Operational Amplifiers The MC33178/9 series is a family of high quality monolithic amplifiers employing Bipolar technology with innovative high performance concepts for quality audio and data signal processing applications. This device family incorporates the use of high frequency PNP input transistors to produce amplifiers exhibiting low input offset voltage, noise and distortion. In addition, the amplifier provides high output current drive capability while consuming only 420 A of drain current per amplifier. The NPN output stage used, exhibits no deadband crossover distortion, large output voltage swing, excellent phase and gain margins, low open-loop high frequency output impedance, symmetrical source and sink AC frequency performance. The MC33178/9 family offers both dual and quad amplifier versions, and is available in DIP and SOIC packages. * 600 Output Drive Capability * Large Output Voltage Swing * Low Offset Voltage: 0.15 mV (Mean) * Low T.C. of Input Offset Voltage: 2.0 V/C * Low Total Harmonic Distortion: 0.0024% (@ 1.0 kHz w/600 Load) * High Gain Bandwidth: 5.0 MHz * High Slew Rate: 2.0 V/s * Dual Supply Operation: 2.0 V to 18 V * ESD Clamps on the Inputs Increase Ruggedness without Affecting Device Performance http://onsemi.com MARKING DIAGRAMS DUAL MC33178P AWL YYWW PDIP-8 P SUFFIX CASE 626 8 1 1 8 SO-8 D SUFFIX CASE 751 8 1 33178 ALYW 1 QUAD 14 PDIP-14 P SUFFIX CASE 646 14 MC33179P AWLYYWW 1 1 14 SO-14 D SUFFIX CASE 751A 14 VCC 8 1 MC33179D AWLYWW 1 Iref Vin + Vin - A WL, L YY, Y WW, W Iref CC VO CM ORDERING INFORMATION Device VEE Figure 1. Representative Schematic Diagram (Each Amplifier) Package Shipping MC33178D SO-8 98 Units/Rail MC33178DR2 SO-8 2500 Tape & Reel MC33178P PDIP-8 50 Units/Rail MC33179D SO-14 55 Units/Rail MC33179DR2 SO-14 2500 Tape & Reel PDIP-14 25 Units/Rail MC33179P Semiconductor Components Industries, LLC, 2002 May, 2002 - Rev. 3 1 = Assembly Location = Wafer Lot = Year = Work Week Publication Order Number: MC33178/D MC33178, MC33179 PIN CONNECTIONS DUAL QUAD CASE 626/751 CASE 646/751A Output 1 1 2 Inputs 1 VEE 3 8 + 4 7 6 + 5 VCC Output 2 Output 1 Inputs 1 Inputs 2 VCC (Top View) Inputs 2 Output 2 1 2 3 14 - 1 4 - + + 4 5 6 13 12 11 + - 2 7 3 + - 10 9 8 Output 4 Inputs 4 VEE Inputs 3 Output 3 (Top View) MAXIMUM RATINGS Rating Symbol Value Unit VS +36 V Input Differential Voltage Range VIDR Note 1 V Input Voltage Range VIR Note 1 V Output Short Circuit Duration (Note 2) tSC Indefinite sec Maximum Junction Temperature TJ +150 C Storage Temperature Range Tstg -60 to +150 C Maximum Power Dissipation PD Note 2 mW Operating Temperature Range TA -40 to +85 C Supply Voltage (VCC to VEE) 1. Either or both input voltages should not exceed VCC or VEE. 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded. (See power dissipation performance characteristic, Figure 2.) http://onsemi.com 2 MC33178, MC33179 DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, TA = 25C, unless otherwise noted.) Characteristics Figure Symbol Input Offset Voltage (RS = 50 , VCM = 0 V, VO = 0 V) (VCC = +2.5 V, VEE = -2.5 V to VCC = +15 V, VEE = -15 V) TA = +25C TA = -40 to +85C 3 |VIO| Average Temperature Coefficient of Input Offset Voltage (RS = 50 , VCM = 0 V, VO = 0 V) TA = -40 to +85C 3 Min 4, 5 Input Offset Current (VCM = 0 V, VO = 0 V) TA = +25C TA = -40 to +85C Max 0.15 - 3.0 4.0 VIO/T V/C - 2.0 - - - 100 - 500 600 - - 5.0 - 50 60 -13 - -14 +14 - +13 50 25 200 - - - IIB nA |IIO| Common Mode Input Voltage Range (VIO = 5.0 mV, VO = 0 V) Large Signal Voltage Gain (VO = -10 V to +10 V, RL = 600 ) TA = +25C TA = -40 to +85C Output Voltage Swing (VID = 1.0 V) (VCC = +15 V, VEE = -15 V) RL = 300 RL = 300 RL = 600 RL = 600 RL = 2.0 k RL = 2.0 k (VCC = +2.5 V, VEE = -2.5 V) RL = 600 RL = 600 6 VICR 7, 8 AVOL nA V VO+ VO- VO+ VO- VO+ VO- - - +12 - +13 - +12 -12 +13.6 -13 +14 -13.8 - - - -12 - -13 VO+ VO- 1.1 - 1.6 -1.6 - -1.1 80 110 - 80 110 - +50 -50 +80 -100 - - Common Mode Rejection (Vin = 13 V) 12 CMR Power Supply Rejection VCC/VEE = +15 V/ -15 V, +5.0 V/ -15 V, +15 V/ -5.0 V 13 PSR 14, 15 Power Supply Current (VO = 0 V) (VCC = 2.5 V, VEE = -2.5 V to VCC = +15 V, VEE = -15 V) MC33178 (Dual) TA = +25C TA = -40 to +85C MC33179 (Quad) TA = +25C TA = -40 to +85C 16 http://onsemi.com 3 V kV/V 9, 10, 11 Output Short Circuit Current (VID = 1.0 V, Output to Ground) Source (VCC = 2.5 V to 15 V) Sink (VEE = -2.5 V to -15 V) Unit mV - - Input Bias Current (VCM = 0 V, VO = 0 V) TA = +25C TA = -40 to +85C Typ dB dB ISC mA ID mA - - - - 1.4 1.6 - - 1.7 - 2.4 2.6 MC33178, MC33179 AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, TA = 25C, unless otherwise noted.) Characteristics Slew Rate (Vin = -10 V to +10 V, RL = 2.0 k, CL = 100 pF, AV = +1.0 V) Gain Bandwidth Product (f = 100 kHz) AC Voltage Gain (RL = 600 , VO = 0 V, f = 20 kHz) Figure Symbol 17, 32 SR Min Typ Max Unit V/s 1.2 2.0 - 18 GBW 2.5 5.0 - MHz 19, 20 AVO - 50 - dB Unity Gain Bandwidth (Open-Loop) (RL = 600 , CL = 0 pF) BW - 3.0 - MHz Gain Margin (RL = 600 , CL = 0 pF) 21, 23, 24 Am - 15 - dB Phase Margin (RL = 600 , CL = 0 pF) 22, 23, 24 m - 60 - Deg 25 CS - -120 - dB BWp - 32 - kHz - - - 0.0024 0.014 0.024 - - - - 150 - Channel Separation (f = 100 Hz to 20 kHz) Power Bandwidth (VO = 20 Vpp, RL = 600 , THD 1.0%) Total Harmonic Distortion (RL = 600 ,, VO = 2.0 Vpp, AV = +1.0 V) (f = 1.0 kHz) (f = 10 kHz) (f = 20 kHz) 26 Open Loop Output Impedance (VO = 0 V, f = 3.0 MHz, AV = 10 V) 27 THD % |ZO| Differential Input Resistance (VCM = 0 V) Rin - 200 - k Differential Input Capacitance (VCM = 0 V) Cin - 10 - pF - - 8.0 7.5 - - - - 0.33 0.15 - - 28 Equivalent Input Noise Current f = 10 Hz f = 1.0 kHz 29 2400 2000 nV/ Hz en pA/ Hz in 4.0 V, IO INPUT OFFSET VOLTAGE (mV) P(MAX), MAXIMUM POWER DISSIPATION (mW) D Equivalent Input Noise Voltage (RS = 100 ,) f = 10 Hz f = 1.0 kHz MC33178P/9P 1600 MC33179D 1200 800 MC33178D 400 0 -60 -40 -20 0 20 40 60 2.0 Unit 1 1.0 Unit 2 0 Unit 3 -1.0 -2.0 -3.0 -4.0 -55 80 100 120 140 160 180 VCC = +15 V VEE = -15 V RS = 10 VCM = 0 V 3.0 -25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (C) TA, AMBIENT TEMPERATURE (C) Figure 2. Maximum Power Dissipation versus Temperature Figure 3. Input Offset Voltage versus Temperature for 3 Typical Units http://onsemi.com 4 125 MC33178, MC33179 120 140 I, IB INPUT BIAS CURRENT (nA) I, IB INPUT BIAS CURRENT (nA) 160 120 100 80 60 40 VCC = +15 V VEE = -15 V TA = 25C 20 0 -15 -10 -5.0 0 5.0 VCM, COMMON MODE VOLTAGE (V) 10 VCC = +15 V VEE = -15 V VCM = 0 V 110 100 90 80 70 60 -55 15 -25 AVOL, OPEN LOOP VOLTAGE GAIN (kV/V) VCC VCC -0.5 V VCC = +5.0 V to +18 V VEE = -5.0 V to -18 V VIO = 5.0 mV VCC -1.0 V VCC -1.5 V VCC -2.0 V VEE +1.0 V VEE +0.5 V -25 0 25 50 75 100 20 50 0 -55 -25 0 25 50 75 Figure 6. Input Common Mode Voltage Range versus Temperature Figure 7. Open Loop Voltage Gain versus Temperature VCC = +15 V VEE = -15 V VO = 0 V TA = 25C 80 40 100 35 120 140 160 0 180 -20 VCC = +15 V VEE = -15 V f = 10 Hz VO = 10 V to +10 V RL = 600 100 TA, AMBIENT TEMPERATURE (C) 10 -10 125 150 1A 200 1B 1A) Phase (RL = 600 ) 2B -30 2A) Phase (RL = 600 CL = 300 pF) 2A -40 1B) Gain (RL = 600 ) 2B) Gain (RL = 600 , CL = 300 pF) -50 2 3 4 5 6 7 8 9 10 f, FREQUENCY (Hz) 220 240 260 20 VO, OUTPUT VOLTAGE (Vpp ) 30 100 200 TA, AMBIENT TEMPERATURE (C) 50 40 125 250 125 , EXCESS PHASE (DEGREES) VEE -55 100 Figure 5. Input Bias Current versus Temperature A VOL, OPEN LOOP VOLTAGE GAIN (dB) V ICR , INPUT COMMON MODE VOLTAGE RANGE (V) Figure 4. Input Bias Current versus Common Mode Voltage 0 25 50 75 TA, AMBIENT TEMPERATURE (C) RL = 10 k 25 RL = 600 20 15 10 5.0 0 280 TA = 25C 30 0 Figure 8. Voltage Gain and Phase versus Frequency 5.0 10 15 VCC, |VEE|, SUPPLY VOLTAGE (V) Figure 9. Output Voltage Swing versus Supply Voltage http://onsemi.com 5 20 VCC TA = -55C VCC -2.0 V VEE +2.0 V Sink TA = -55C VEE +1.0 V CMR, COMMON MODE REJECTION (dB) VO, OUTPUT VOLTAGE (Vpp ) VCC -1.0 V 28 Source TA = +125C VCC = +5.0 V to +18 V VEE = -5.0 V to -18 V TA = +125C VEE 0 5.0 10 15 12 8.0 4.0 0 1.0 k 100 k 1.0 M Figure 11. Output Voltage versus Frequency VCC = +15 V VEE = -15 V VCM = 0 V VCM = 1.5 V TA = -55 to +125C ADM + VCM CMR = 20 Log 100 VO DVCM VO x ADM 1.0 k 10 k f, FREQUENCY (Hz) 100 k 120 80 -PSR ADM + 60 40 20 I, SC OUTPUT SHORT CIRCUIT CURRENT (mA) Source 80 Sink 60 VCC = +15 V VEE = -15 V VID = 1.0 V 20 -9.0 -3.0 0 3.0 VO, OUTPUT VOLTAGE (V) VO PSR = 20 Log VO/ADM VCC 100 1.0 k 10 k f, FREQUENCY (Hz) 100 k 1.0 M Figure 13. Power Supply Rejection versus Frequency Over Temperature 100 40 VCC VEE 0 10 1.0 M TA = -55 to +125C VCC = +15 V VEE = -15 V VCC = 1.5 V +PSR 100 Figure 12. Common Mode Rejection versus Frequency Over Temperature I, SC OUTPUT SHORT CIRCUIT CURRENT (mA) 10 k Figure 10. Output Saturation Voltage versus Load Current 60 0 -15 VCC = +15 V VEE = -15 V RL = 600 AV = +1.0 V THD = 1.0% TA = 25C f, FREQUENCY (Hz) 80 0 10 16 IL, LOAD CURRENT (mA) 100 20 20 20 120 40 24 PSR, POWER SUPPLY REJECTION (dB) V sat , OUTPUT SATURATION VOLTAGE (V) MC33178, MC33179 9.0 15 100 90 VCC = +15 V VEE = -15 V VID = 1.0 V RL < 10 Sink 80 70 Source 60 50 -55 -25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (C) Figure 14. Output Short Circuit Current versus Output Voltage Figure 15. Output Short Circuit Current versus Temperature http://onsemi.com 6 125 1.15 625 TA = +125C 375 TA = +25C 250 TA = -55C 125 0 0 2.0 4.0 6.0 8.0 10 12 14 16 1.05 VCC = +15 V VEE = -15 V Vin = 20 Vpp 1.00 0.95 0.90 - 0.85 0.80 0.75 -55 18 -25 VCC, |VEE| , SUPPLY VOLTAGE (V) 8.0 6.0 VCC = +15 V VEE = -15 V f = 100 kHz RL = 600 CL = 0 pF -25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) 100 30 125 -10 1B 1A 2A 0 -20 1A) Phase V =18 V, V = -18 V CC EE -30 2A) Phase VCC 1.5 V, VEE = -1.5 V 1B) Gain V = 18 V, V = -18 V -40 2B) Gain VCC = 1.5 V, VEE = -1.5 V CC EE -50 100 k 1.0 M -20 -30 200 220 240 260 280 100 M 1.0 M 10 M f, FREQUENCY (Hz) 15 100 120 140 160 200 220 240 260 10 M 180 VCC = +15 V VEE = -15 V RL = 600 TA = 25C CL = 0 pF Figure 19. Voltage Gain and Phase versus Frequency 180 2B 160 Gain -10 Am, OPEN LOOP GAIN MARGIN (dB) 20 120 140 10 -50 100 k , PHASE (DEGREES) 30 125 100 20 80 TA = 25C RL = CL = 0 pF 40 0 100 Phase -40 50 10 75 80 40 0 -55 50 50 AV , VOLTAGE GAIN (dB) GBW, GAIN BANDWIDTH PRODUCT (MHz) 10 2.0 25 Figure 17. Normalized Slew Rate versus Temperature Figure 18. Gain Bandwidth Product versus Temperature A, V VOLTAGE GAIN (dB) 0 VO 100 pF 600 TA, AMBIENT TEMPERATURE (C) Figure 16. Supply Current versus Supply Voltage with No Load 4.0 + Vin , EXCESS PHASE (DEGREES) 500 1.10 SR, SLEW RATE (NORMALIZED) I CC, SUPPLY CURRENT/AMPLIFIER ( A) MC33178, MC33179 280 100 M CL = 10 pF 12 CL = 100 pF 9.0 CL = 300 pF 6.0 3.0 0 -55 VCC = +15 V VEE = -15 V RL = 600 -25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (C) f, FREQUENCY (Hz) Figure 20. Voltage Gain and Phase versus Frequency Figure 21. Open Loop Gain Margin versus Temperature http://onsemi.com 7 125 MC33178, MC33179 12 10 CL = 100 pF 40 30 CL = 300 pF 20 VCC = +15 V VEE = -15 V RL = 600 10 0 -55 -25 60 50 VCC = +15 V VEE = -15 V RT = R1+R2 VO = 0 V TA = 25C 8.0 6.0 4.0 0 25 50 75 100 1.0 k 30 9.0 3.0 + 20 VO CL 600 10 10 0 1.0 k 100 Drive Channel VCC = +15 V CEE = -15 V RL = 600 TA = 25C 140 130 120 110 100 100 1.0 k 10 k 100 k CL, OUTPUT LOAD CAPACITANCE (pF) f, FREQUENCY (Hz) Figure 24. Open Loop Gain Margin and Phase Margin versus Output Load Capacitance Figure 25. Channel Separation versus Frequency 10 VCC = +15 V VO = 2.0 Vpp VEE = -15 V TA = 25C RL = 600 400 AV = 1000 1.0 300 AV = 100 VCC = +15 V VEE = -15 V VO = 0 V TA = 25C 1. AV = 1.0 2. AV = 10 3. AV = 100 4. AV = 1000 200 0.1 0.01 10 1.0 M 500 |Z|, O OUTPUT IMPEDANCE () THD, TOTAL HARMONIC DISTORTION (%) 0 - CS, CHANNEL SEPARATION (dB) 40 m, PHASE MARGIN (DEGREES) 50 A, m OPEN LOOP GAIN MARGIN (dB) VCC = +15 V VEE = -15 V VO = 0 V Gain Margin Vin 0 100 k 10 k 150 60 6.0 10 Figure 23. Phase Margin and Gain Margin versus Differential Source Resistance 18 12 VO RT, DIFFERENTIAL SOURCE RESISTANCE () Figure 22. Phase Margin versus Temperature 15 Phase Margin + R2 TA, AMBIENT TEMPERATURE (C) Phase Margin 30 - Vin 0 100 125 40 20 R1 2.0 Gain Margin m , PHASE MARGIN (DEGREES) CL = 10 pF 50 A, m GAIN MARGIN (dB) m , PHASE MARGIN (DEGREES) 60 AV = 10 100 1.0 k 100 AV = 1.0 10 k 0 1.0 k 100 k f, FREQUENCY (Hz) Figure 26. Total Harmonic Distortion versus Frequency 3 2 1 4 10 k 100 k f, FREQUENCY (Hz) 1.0 M Figure 27. Output Impedance versus Frequency http://onsemi.com 8 10 M 20 pA/ Hz i, n INPUT REFERRED NOISE CURRENT () e, nV/ Hz n INPUT REFERRED NOISE VOLTAGE () MC33178, MC33179 Input Noise Voltage Test Circuit + VO - 18 16 14 12 10 8.0 6.0 4.0 2.0 0 10 VCC = +15 V VEE = -15 V TA = 25C 100 1.0 k f, FREQUENCY (Hz) 10 k 10 k 0.5 0.4 0.1 0 10 V O, OUTPUT VOLTAGE (5.0 V/DIV) 60 RL = 600 50 RL = 2.0 k 40 30 20 10 0 10 100 1.0 k VO VCC = +15 V VEE = -15 V TA = 25C 100 1.0 k f, FREQUENCY (Hz) 10 k 100 k Figure 29. Input Referred Noise Current versus Frequency VCC = +15 V VEE = -15 V TA = 25C 10 k VCC = +15 V VEE = -15 V AV = +1.0 RL = 600 CL = 100 pF TA = 25C t, TIME (2.0 s/DIV) CL, LOAD CAPACITANCE (pF) Figure 30. Percent Overshoot versus Load Capacitance Figure 31. Non-inverting Amplifier Slew Rate VCC = +15 V VEE = -15 V AV = +1.0 RL = 600 CL = 100 pF TA = 25C V O, OUTPUT VOLTAGE (5.0 V/DIV) VCC = +15 V VEE = -15 V AV = +1.0 RL = 600 CL = 100 pF TA = 25C V O, OUTPUT VOLTAGE (50 mV/DIV) PERCENT OVERSHOOT (%) 70 - (RS = 10 k) 0.2 100 80 + RS 0.3 Figure 28. Input Referred Noise Voltage versus Frequency 90 Input Noise Current Test Circuit t, TIME (2.0 ns/DIV) t, TIME (5.0 s/DIV) Figure 32. Small Signal Transient Response Figure 33. Large Signal Transient Response http://onsemi.com 9 MC33178, MC33179 10 k A1 To Receiver - 10 k + 10 k 1.0 F 200 k 120 k From Microphone 2.0 k + 0.05 F 300 A2 820 Tip VR 1N4678 Phone Line 10 k 10 k + A3 Ring VR Figure 34. Telephone Line Interface Circuit APPLICATION INFORMATION MC33179 (quad op amp). Shorting more than one amplifier could easily exceed the junction temperature to the extent of causing permanent damage. This unique device uses a boosted output stage to combine a high output current with a drain current lower than similar bipolar input op amps. Its 60 phase margin and 15 dB gain margin ensure stability with up to 1000 pF of load capacitance (see Figure 24). The ability to drive a minimum 600 load makes it particularly suitable for telecom applications. Note that in the sample circuit in Figure 34 both A2 and A3 are driving equivalent loads of approximately 600 The low input offset voltage and moderately high slew rate and gain bandwidth product make it attractive for a variety of other applications. For example, although it is not single supply (the common mode input range does not include ground), it is specified at +5.0 V with a typical common mode rejection of 110 dB. This makes it an excellent choice for use with digital circuits. The high common mode rejection, which is stable over temperature, coupled with a low noise figure and low distortion, is an ideal op amp for audio circuits. The output stage of the op amp is current limited and therefore has a certain amount of protection in the event of a short circuit. However, because of its high current output, it is especially important not to allow the device to exceed the maximum junction temperature, particularly with the Stability As usual with most high frequency amplifiers, proper lead dress, component placement, and PC board layout should be exercised for optimum frequency performance. For example, long unshielded input or output leads may result in unwanted input/output coupling. In order to preserve the relatively low input capacitance associated with these amplifiers, resistors connected to the inputs should be immediately adjacent to the input pin to minimize additional stray input capacitance. This not only minimizes the input pole frequency for optimum frequency response, but also minimizes extraneous "pick up" at this node. Supplying decoupling with adequate capacitance immediately adjacent to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit great impedance changes over temperature. Additional stability problems can be caused by high load capacitances and/or a high source resistance. Simple compensation schemes can be used to alleviate these effects. http://onsemi.com 10 MC33178, MC33179 If a high source of resistance is used (R1 > 1.0 k), a compensation capacitor equal to or greater than the input capacitance of the op amp (10 pF) placed across the feedback resistor (see Figure 35) can be used to neutralize that pole and prevent outer loop oscillation. Since the closed loop transient response will be a function of that capacitance, it is important to choose the optimum value for that capacitor. This can be determined by the following Equation: CC (1 [R1R2])2 CL (ZOR2) For moderately high capacitive loads (500 pF < CL < 1500 pF) the addition of a compensation resistor on the order of 20 between the output and the feedback loop will help to decrease miller loop oscillation (see Figure 36). For high capacitive loads (CL > 1500 pF), a combined compensation scheme should be used (see Figure 37). Both the compensation resistor and the compensation capacitor affect the transient response and can be calculated for optimum performance. The value of CC can be calculated using Equation (1). The Equation to calculate RC is as follows: (1) where: ZO is the output impedance of the op amp. RC ZO R1R2 (2) R2 R2 CC - R1 - + + R1 ZL CL Figure 35. Compensation for High Source Impedance Figure 36. Compensation Circuit for Moderate Capacitive Loads R2 CC - R1 RC RC + CL Figure 37. Compensation Circuit for High Capacitive Loads http://onsemi.com 11 MC33178, MC33179 PACKAGE DIMENSIONS PDIP-8 P SUFFIX CASE 626-05 ISSUE L 8 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5 -B- 1 4 DIM A B C D F G H J K L M N F -A- NOTE 2 L C J -T- MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --10 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --10 0.030 0.040 N SEATING PLANE D M K G H 0.13 (0.005) M T A M B M SO-8 D SUFFIX CASE 751-07 ISSUE W -X- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. A 8 5 0.25 (0.010) S B 1 M Y M 4 K -Y- G C N X 45 SEATING PLANE -Z- 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M S http://onsemi.com 12 J DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 MC33178, MC33179 PACKAGE DIMENSIONS PDIP-14 P SUFFIX CASE 646-06 ISSUE M 14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B A F DIM A B C D F G H J K L M N L N C -T- SEATING PLANE J K H D 14 PL G M 0.13 (0.005) INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --10 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --10 0.38 1.01 M SO-14 D SUFFIX CASE 751A-03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 14 8 -B- 1 P 7 PL 0.25 (0.010) 7 G B M M F R X 45 C -T- SEATING PLANE D 14 PL 0.25 (0.010) M K M T B S A S http://onsemi.com 13 J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019 MC33178, MC33179 Notes http://onsemi.com 14 MC33178, MC33179 Notes http://onsemi.com 15 MC33178, MC33179 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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