W25Q128BV 3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI -1- Publication Release Date: October 03, 2013 Revision H W25Q128BV Table of Contents 1. GENERAL DESCRIPTION ............................................................................................................... 5 2. FEATURES ....................................................................................................................................... 5 3. PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 6 4. 3.1 Pad Configuration WSON 8x6-mm ...................................................................................... 6 3.2 Pad Description WSON 8x6-mm .......................................................................................... 6 3.3 Pin Configuration SOIC 300-mil ........................................................................................... 7 3.4 Pin Description SOIC 300-mil............................................................................................... 7 3.5 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 8 3.6 Ball Description TFBGA 8x6-mm ......................................................................................... 8 PIN DESCRIPTIONS ........................................................................................................................ 9 4.1 Chip Select (/CS) .................................................................................................................. 9 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................... 9 4.3 Write Protect (/WP)............................................................................................................... 9 4.4 HOLD (/HOLD) ..................................................................................................................... 9 4.5 Serial Clock (CLK) ................................................................................................................ 9 5. BLOCK DIAGRAM .......................................................................................................................... 10 6. FUNCTIONAL DESCRIPTIONS ..................................................................................................... 11 6.1 6.2 SPI OPERATIONS ............................................................................................................. 11 6.1.1 Standard SPI Instructions ..................................................................................................... 11 6.1.2 Dual SPI Instructions ............................................................................................................ 11 6.1.3 Quad SPI Instructions .......................................................................................................... 11 6.1.4 Hold Function ....................................................................................................................... 11 WRITE PROTECTION ....................................................................................................... 12 6.2.1 7. Write Protect Features ......................................................................................................... 12 STATUS REGISTERS AND INSTRUCTIONS ............................................................................... 13 7.1 STATUS REGISTERS........................................................................................................ 13 7.1.1 BUSY Status (BUSY) ........................................................................................................... 13 7.1.2 Write Enable Latch Status (WEL) ......................................................................................... 13 7.1.3 Block Protect Bits (BP2, BP1, BP0) ...................................................................................... 13 7.1.4 Top/Bottom Block Protect Bit (TB)........................................................................................ 13 7.1.5 Sector/Block Protect Bit (SEC) ............................................................................................. 13 7.1.6 Complement Protect Bit (CMP) ............................................................................................ 14 7.1.7 Status Register Protect Bits (SRP1, SRP0).......................................................................... 14 7.1.8 Erase/Program Suspend Status (SUS) ................................................................................ 14 7.1.9 Security Register Lock Bits (LB3, LB2, LB1) ........................................................................ 14 7.1.10 Quad Enable Bit (QE) ......................................................................................................... 15 -2- W25Q128BV 7.2 7.1.11 Status Register Memory Protection (CMP = 0)................................................................... 16 7.1.12 Status Register Memory Protection (CMP = 1)................................................................... 17 INSTRUCTIONS................................................................................................................. 18 7.2.1 Manufacturer and Device Identification ................................................................................ 18 7.2.2 Instruction Set Table 1 (Erase, Program Instructions)(1) ....................................................... 19 7.2.3 Instruction Set Table 2 (Read Instructions) .......................................................................... 20 7.2.4 Instruction Set Table 3 (ID, Security Instructions) ................................................................ 21 7.2.5 Write Enable (06h) ............................................................................................................... 22 7.2.6 Write Enable for Volatile Status Register (50h) .................................................................... 22 7.2.7 Write Disable (04h) ............................................................................................................... 23 7.2.8 Read Status Register-1 (05h) and Read Status Register-2 (35h)......................................... 24 7.2.9 Write Status Register (01h) .................................................................................................. 24 7.2.10 Read Data (03h) ................................................................................................................. 26 7.2.11 Fast Read (0Bh) ................................................................................................................. 27 7.2.12 Fast Read Dual Output (3Bh) ............................................................................................. 28 7.2.13 Fast Read Quad Output (6Bh)............................................................................................ 29 7.2.14 Fast Read Dual I/O (BBh)................................................................................................... 30 7.2.15 Fast Read Quad I/O (EBh) ................................................................................................. 32 7.2.16 Word Read Quad I/O (E7h) ................................................................................................ 34 7.2.17 Octal Word Read Quad I/O (E3h) ....................................................................................... 36 7.2.18 Set Burst with Wrap (77h) .................................................................................................. 38 7.2.19 Continuous Read Mode Bits (M7-0) ................................................................................... 39 7.2.20 Continuous Read Mode Reset (FFh or FFFFh) .................................................................. 39 7.2.21 Page Program (02h) ........................................................................................................... 40 7.2.22 Quad Input Page Program (32h) ........................................................................................ 41 7.2.23 Sector Erase (20h) ............................................................................................................. 42 7.2.24 32KB Block Erase (52h) ..................................................................................................... 43 7.2.25 64KB Block Erase (D8h)..................................................................................................... 44 7.2.26 Chip Erase (C7h / 60h) ....................................................................................................... 45 7.2.27 Erase / Program Suspend (75h) ......................................................................................... 46 7.2.28 Erase / Program Resume (7Ah) ......................................................................................... 47 7.2.29 Power-down (B9h) .............................................................................................................. 48 7.2.30 Release Power-down / Device ID (ABh) ............................................................................. 49 7.2.31 Read Manufacturer / Device ID (90h) ................................................................................. 51 7.2.32 Read Manufacturer / Device ID Dual I/O (92h) ................................................................... 52 7.2.33 Read Manufacturer / Device ID Quad I/O (94h) ................................................................. 53 7.2.34 Read Unique ID Number (4Bh) .......................................................................................... 54 7.2.35 Read JEDEC ID (9Fh) ........................................................................................................ 55 7.2.36 Read SFDP Register (5Ah) ................................................................................................ 56 7.2.37 Erase Security Registers (44h) ........................................................................................... 57 7.2.38 Program Security Registers (42h) ...................................................................................... 58 -3- Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.39 8. ELECTRICAL CHARACTERISTICS .............................................................................................. 60 8.1 Absolute Maximum Ratings (1)(2) ...................................................................................... 60 8.2 9. 10. 8.3 Operating Ranges .............................................................................................................. 60 Power-up Timing and Write Inhibit Threshold(1) ............................................................... 61 8.4 DC Electrical Characteristics .............................................................................................. 62 8.5 AC Measurement Conditions ............................................................................................. 63 8.6 AC Electrical Characteristics .............................................................................................. 64 8.7 AC Electrical Characteristics (cont'd) ................................................................................. 65 8.8 Serial Output Timing ........................................................................................................... 66 8.9 Serial Input Timing.............................................................................................................. 66 8.10 HOLD Timing ...................................................................................................................... 66 8.11 WP Timing .......................................................................................................................... 66 PACKAGE SPECIFICATION .......................................................................................................... 67 9.1 8-Pad WSON 8x6-mm (Package Code E) ......................................................................... 67 9.2 16-Pin SOIC 300-mil (Package Code F) ............................................................................ 68 9.3 24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 Ball Array) ........................................... 69 9.4 24-Ball TFBGA 8x6-mm (Package Code C, 6x4 Ball Array) .............................................. 70 ORDERING INFORMATION .......................................................................................................... 71 10.1 11. Read Security Registers (48h) ........................................................................................... 59 Valid Part Numbers and Top Side Marking ........................................................................ 72 REVISION HISTORY ...................................................................................................................... 73 -4- W25Q128BV 1. GENERAL DESCRIPTION The W25Q128BV (128M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1A for power-down. The W25Q128BV array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q128BV has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See Figure 2.) The W25Q128BV supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual Output and 280MHz (70MHz x 4) for Quad SPI when using the Fast Read Quad SPI instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation. A Hold pin, Write Protect pin and programmable write protection, with top, bottom or complement array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification with a 64-bit Unique Serial Number. 2. FEATURES Family of SpiFlash Memories - W25Q128BV: 128M-bit/16M-byte - 256-byte per programmable page - Standard SPI: CLK, /CS, DI, DO, /WP, /Hold - Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold - Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 Highest Performance Serial Flash - 104/70MHz Dual Output/Quad SPI clocks - 208/280MHz equivalent Dual /Quad SPI - 35MB/S continuous data transfer rate - Up to 5X that of ordinary Serial Flash - More than 100,000 erase/program cycles(1) - More than 20-year data retention Efficient "Continuous Read Mode" - Low Instruction overhead - Continuous Read with 8/16/32/64-Byte Wrap - As few as 8 clocks to address memory - Allows true XIP (execute in place) operation - Outperforms X16 Parallel Flash Low Power, Wide Temperature Range - Single 2.7 to 3.6V supply - 4mA active current, <1A Power-down current - -40C to +85C operating range Flexible Architecture with 4KB sectors - Uniform Sector/Block Erase (4K/32K/64K-Byte) - Program one to 256 bytes - Erase/Program Suspend & Resume Advanced Security Features - Software and Hardware Write-Protect - Top/Bottom, 4KB complement array protection - Lock-Down and OTP array protection - 64-Bit Unique Serial Number for each device - Discoverable Parameters (SFDP) Register - 3X256-Byte Security Registers with OTP locks - Volatile & Non-volatile Status Register Bits Space Efficient Packaging - 8-pad WSON 8x6-mm - 16-pin SOIC 300-mil - 24-ball TFBGA 5X5-mm & 8X6-mm - Contact Winbond for KGD and other options -5- Publication Release Date: October 03, 2013 Revision H W25Q128BV 3. PACKAGE TYPES AND PIN CONFIGURATIONS W25Q128BV is offered in an 8-pad WSON 8x6-mm (package code E), a 16-pin SOIC 300-mil (package code F) and two 24-ball 8x6-mm TFBGAs (package code B, C) as shown in Figure 1a-c respectively. Package diagrams and dimensions are illustrated at the end of this datasheet. 3.1 Pad Configuration WSON 8x6-mm Top View /CS 1 8 VCC DO (IO1) 2 7 /HOLD (IO3) /WP (IO2) 3 6 CLK GND 4 5 DI (IO0) Figure 1a. W25Q128BV Pad Assignments, 8-pad WSON 8x6-mm (Package Code E) 3.2 Pad Description WSON 8x6-mm PAD NO. PAD NAME I/O 1 /CS I 2 DO (IO1) I/O Data Output (Data Input Output 1)*1 3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)*2 4 GND 5 DI (IO0) I/O 6 CLK I 7 /HOLD (IO3) I/O 8 VCC FUNCTION Chip Select Input Ground Data Input (Data Input Output 0)*1 Serial Clock Input Hold Input (Data Input Output 3)*2 Power Supply *1: IO0 and IO1 are used for Standard and Dual SPI instructions *2: IO0 - IO3 are used for Quad SPI instructions -6- W25Q128BV 3.3 Pin Configuration SOIC 300-mil Top View /HOLD (IO3) 1 16 CLK VCC 2 15 DI (IO0) NC 3 14 NC NC 4 13 NC NC 5 12 NC NC 6 11 NC /CS 7 10 GND DO (IO1) 8 9 /WP (IO2) Figure 1b. W25Q128BV Pin Assignments, 16-pin SOIC 300-mil (Package Code F) 3.4 Pin Description SOIC 300-mil PIN NO. PIN NAME I/O FUNCTION 1 /HOLD (IO3) I/O 2 VCC Power Supply 3 N/C No Connect 4 N/C No Connect 5 N/C No Connect 6 N/C No Connect 7 /CS I 8 DO (IO1) I/O Data Output (Data Input Output 1)*1 9 /WP (IO2) I/O Write Protect Input (Data Input Output 2)*2 10 GND Ground 11 N/C No Connect 12 N/C No Connect 13 N/C No Connect 14 N/C No Connect 15 DI (IO0) I/O 16 CLK I Hold Input (Data Input Output 3)*2 Chip Select Input Data Input (Data Input Output 0)*1 Serial Clock Input *1: IO0 and IO1 are used for Standard and Dual SPI instructions. *2: IO0 - IO3 are used for Quad SPI instructions, /WP or /HOLD functions are only available for Standard/Dual SPI. -7- Publication Release Date: October 03, 2013 Revision H W25Q128BV 3.5 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) Top View Top View A1 A2 A3 A4 NC NC NC NC A2 A3 A4 A5 NC NC NC NC B1 B2 B3 B4 B1 B2 B3 B4 B5 NC CLK GND VCC NC CLK GND VCC NC C1 C2 C3 C4 C1 C2 C3 C4 C5 NC /CS NC /WP (IO2) NC /CS NC /WP (IO2) NC D1 D2 D3 D4 D1 D2 D3 D4 D5 NC DO(IO1) NC DO(IO1) E1 E2 E3 NC NC NC DI(IO0) /HOLD(IO3) DI(IO0) /HOLD(IO3) NC E1 E2 E3 E4 E4 E5 NC NC NC NC NC NC Package Code B F1 F2 F3 F4 NC NC NC NC Package Code C Figure 1c. W25Q128BV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code B, C) 3.6 Ball Description TFBGA 8x6-mm BALL NO. PIN NAME I/O FUNCTION B2 CLK I B3 GND Ground B4 VCC Power Supply C2 /CS I C4 /WP (IO2) I/O Write Protect Input (Data Input Output 2)*2 D2 DO (IO1) I/O Data Output (Data Input Output 1)*1 D3 DI (IO0) I/O Data Input (Data Input Output 0)*1 D4 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2 Multiple NC Serial Clock Input Chip Select Input No Connect *1: IO0 and IO1 are used for Standard and Dual SPI instructions. *2: IO0 - IO3 are used for Quad SPI instructions, /WP or /HOLD functions are only available for Standard/Dual SPI. -8- W25Q128BV 4. PIN DESCRIPTIONS 4.1 Chip Select (/CS) The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS input must track the VCC supply level at power-up (see "Write Protection" and Figure 38). If needed a pull-up resister on /CS can be used to accomplish this. 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) The W25Q128BV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge of CLK. Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3. 4.3 Write Protect (/WP) The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register's Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /WP pin function is not available since this pin is used for IO2. See Figure 1a-c for the pin configuration of Quad I/O operation. 4.4 HOLD (/HOLD) The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don't care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3. See Figure 1a-c for the pin configuration of Quad I/O operation. 4.5 Serial Clock (CLK) The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Operations") -9- Publication Release Date: October 03, 2013 Revision H W25Q128BV 5. BLOCK DIAGRAM SFDP Register 000000h Security Register 1 - 3 0000FFh 003000h 002000h 001000h 0030FFh 0020FFh 0010FFh Block Segmentation xxFF00h * xxF000h Sector 15 (4KB) xxFFFFh * xxF0FFh xxEF00h * xxE000h Sector 14 (4KB) xxEFFFh * xxE0FFh xxDF00h * xxD000h Sector 13 (4KB) xxDFFFh * xxD0FFh FFFF00h * Block 255 (64KB) FF0000h Sector 2 (4KB) xx2FFFh * xx20FFh xx1F00h * xx1000h Sector 1 (4KB) xx1FFFh * xx10FFh xx0F00h * xx0000h Sector 0 (4KB) xx0FFFh * xx00FFh Write Protect Logic and Row Decode xx2F00h * xx2000h 80FF00h * Block 128 (64KB) 800000h 80FFFFh * 8000FFh 7FFF00h * Block 127 (64KB) 7F0000h 7FFFFFh * 7F00FFh * * * Write Control Logic Status Register 40FF00h * 400000h Block 64 (64KB) 40FFFFh * 4000FFh 3FFF00h * 3F0000h Block 63 (64KB) 3FFFFFh * 3F00FFh * * * High Voltage Generators 00FF00h * 000000h /HOLD (IO3) CLK /CS SPI Command & Control Logic Page Address Latch / Counter Block 0 (64KB) Beginning Page Address Ending Page Address Column Decode And 256-Byte Page Buffer Data DI (IO0) DO (IO1) 00FFFFh * 0000FFh Byte Address Latch / Counter Figure 2. W25Q128BV Serial Flash Memory Block Diagram - 10 - W25Q128BV * * * * * * /WP (IO2) FFFFFFh * FF00FFh W25Q128BV 6. 6.1 FUNCTIONAL DESCRIPTIONS SPI OPERATIONS 6.1.1 Standard SPI Instructions The W25Q128BV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK. SPI bus operation Mode 0 (0, 0) and 3 (1, 1) are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS. 6.1.2 Dual SPI Instructions The W25Q128BV supports Dual SPI operation when using the "Fast Read Dual Output (3Bh)" and "Fast Read Dual I/O (BBh)" instructions. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become bidirectional I/O pins: IO0 and IO1. 6.1.3 Quad SPI Instructions The W25Q128BV supports Quad SPI operation when using the "Fast Read Quad Output (6Bh)", "Fast Read Quad I/O (EBh)", "Word Read Quad I/O (E7h)" and "Octal Word Read Quad I/O (E3h)" instructions. These instructions allow data to be transferred to or from the device six to eight times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. 6.1.4 Hold Function For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25Q128BV operation to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. The /HOLD function is only available for standard SPI and Dual SPI operation, not during Quad SPI. To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the - 11 - Publication Release Date: October 03, 2013 Revision H W25Q128BV rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept active low for the full duration of the /HOLD operation to avoid resetting the internal logic state of the device. 6.2 WRITE PROTECTION Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern, the W25Q128BV provides several means to protect the data from inadvertent writes. 6.2.1 Write Protect Features Device resets when VCC is below threshold Time delay write disable after Power-up Write enable/disable instructions and automatic write disable after erase or program Software and Hardware (/WP pin) write protection using Status Register Write Protection using Power-down instruction Lock Down write protection until next power-up One Time Program (OTP) write protection * * Note: This feature is available upon special order. Please contact Winbond for details. Upon power-up or at power-down, the W25Q128BV will maintain a reset condition while VCC is below the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 38). While reset, all operations are disabled and no instructions are recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached. If needed a pull-up resister on /CS can be used to accomplish this. After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a writedisabled state of 0. Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits. These settings allow a portion as small as 4KB sector or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status Register section for further information. Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction. - 12 - W25Q128BV 7. STATUS REGISTERS AND INSTRUCTIONS The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the availability of the Flash memory array, if the device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status and Erase/Program Suspend status. The Write Status Register instruction can be used to configure the device write protection features, Quad SPI setting and Security Register OTP lock. Write access to the Status Register is controlled by the state of the nonvolatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and during Standard/Dual SPI operations, the /WP pin. 7.1 STATUS REGISTERS 7.1.1 BUSY Status (BUSY) BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/Program Security Register instruction. During this time the device will ignore further instructions except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status/security register instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions. 7.1.2 Write Enable Latch Status (WEL) Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and Program Security Register. 7.1.3 Block Protect Bits (BP2, BP1, BP0) The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be protected from Program and Erase instructions (see Status Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array protected. 7.1.4 Top/Bottom Block Protect Bit (TB) The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP0, SRP1 and WEL bits. 7.1.5 Sector/Block Protect Bit (SEC) The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0. - 13 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.1.6 Complement Protect Bit (CMP) The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For instance, when CMP=0, a top 4KB sector can be protected while the rest of the array is not; when CMP=1, the top 4KB sector will become unprotected while the rest of the array become read-only. Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0. 7.1.7 Status Register Protect Bits (SRP1, SRP0) The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (S8 and S7). The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection. SRP1 SRP0 /WP Status Register Description 0 0 X Software Protection /WP pin has no control. The Status register can be written to after a Write Enable instruction, WEL=1. [Factory Default] 0 1 0 Hardware Protected When /WP pin is low the Status Register locked and can not be written to. 0 1 1 Hardware Unprotected When /WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1. 1 0 X Power Supply Lock-Down 1 1 X One Time Program(2) Status Register is protected and can not be written to again until the next power-down, power-up cycle.(1) Status Register is permanently protected and can not be written to. Note: 1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state. 2. This feature is available upon special order. Please contact Winbond for details. 7.1.8 Erase/Program Suspend Status (SUS) The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing an Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah) instruction as well as a power-down, power-up cycle. 7.1.9 Security Register Lock Bits (LB3, LB2, LB1) The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The default state of LB[3:1] is 0, Security Registers are unlocked. LB[3:1] can be set to 1 individually using the Write Status Register instruction. LB[3:1] are One Time Programmable (OTP), once it's set to 1, the corresponding 256-Byte Security Register will become read-only permanently. - 14 - W25Q128BV 7.1.10 Quad Enable Bit (QE) The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI operation. When the QE bit is set to a 0 state (factory default), the /WP pin and /HOLD pin are enabled. When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and /WP and /HOLD functions are disabled. WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during standard SPI or Dual SPI operation, the QE bit should never be set to a 1. S7 S6 S5 S4 S3 S2 SRP0 SEC TB BP2 BP1 BP0 S1 S0 WEL BUSY STATUS REGISTER PROTECT 0 (non-volatile) SECTOR PROTECT (non-volatile) TOP/BOTTOM PROTECT (non-volatile) BLOCK PROTECT BITS (non-volatile) WRITE ENABLE LATCH ERASE/WRITE IN PROGRESS Figure 3a. Status Register-1 S15 S14 S13 S12 S11 S10 S9 S8 SUS CMP LB3 LB2 LB1 (R) QE SRP1 SUSPEND STATUS COMPLEMENT PROTECT (non-volatile) SECURITY REGISTER LOCK BITS (non-volatile OTP) RESERVED QUAD ENABLE (non-volatile) STATUS REGISTER PROTECT 1 (non-volatile) Figure 3b. Status Register-2 - 15 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.1.11 Status Register Memory Protection (CMP = 0) STATUS REGISTER(1) W25Q128BV (128M-BIT) MEMORY PROTECTION(3) SEC TB BP2 BP1 BP0 PROTECTED BLOCK(S) PROTECTED ADDRESSES PROTECTED DENSITY PROTECTED PORTION(2) X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 252 thru 255 FC0000h - FFFFFFh 256KB Upper 1/64 0 0 0 1 0 248 thru 255 F80000h - FFFFFFh 512KB Upper 1/32 0 0 0 1 1 240 thru 255 F00000h - FFFFFFh 1MB Upper 1/16 0 0 1 0 0 224 thru 255 E00000h - FFFFFFh 2MB Upper 1/8 0 0 1 0 1 192 thru 255 C00000h - FFFFFFh 4MB Upper 1/4 0 0 1 1 0 128 thru 255 800000h - FFFFFFh 8MB Upper 1/2 0 1 0 0 1 0 thru 3 000000h - 03FFFFh 256KB Lower 1/64 0 1 0 1 0 0 thru 7 000000h - 07FFFFh 512KB Lower 1/32 0 1 0 1 1 0 thru 15 000000h - 0FFFFFh 1MB Lower 1/16 0 1 1 0 0 0 thru 31 000000h - 1FFFFFh 2MB Lower 1/8 0 1 1 0 1 0 thru 63 000000h - 3FFFFFh 4MB Lower 1/4 0 1 1 1 0 0 thru 127 000000h - 7FFFFFh 8MB Lower 1/2 X X 1 1 1 0 thru 255 000000h - FFFFFFh 16MB ALL 1 0 0 0 1 255 FFF000h - FFFFFFh 4KB U - 1/4096 1 0 0 1 0 255 FFE000h - FFFFFFh 8KB U - 1/2048 1 0 0 1 1 255 FFC000h - FFFFFFh 16KB U - 1/1024 1 0 1 0 X 255 FF8000h - FFFFFFh 32KB U - 1/512 1 1 0 0 1 0 000000h - 000FFFh 4KB L - 1/4096 1 1 0 1 0 0 000000h - 001FFFh 8KB L - 1/2048 1 1 0 1 1 0 000000h - 003FFFh 16KB L - 1/1024 1 1 1 0 X 0 000000h - 007FFFh 32KB L - 1/512 Notes: 1. X = don't care 2. L = Lower; U = Upper 3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored. - 16 - W25Q128BV 7.1.12 Status Register Memory Protection (CMP = 1) STATUS REGISTER(1) W25Q128BV (128M-BIT) MEMORY PROTECTION(3) SEC TB BP2 BP1 BP0 PROTECTED BLOCK(S) PROTECTED ADDRESSES PROTECTED DENSITY PROTECTED PORTION(2) X X 0 0 0 0 thru 255 000000h - FFFFFFh 16MB ALL 0 0 0 0 1 0 thru 251 000000h - FBFFFFh 16,128KB Lower 63/64 0 0 0 1 0 0 thru 247 000000h - F7FFFFh 15,872KB Lower 31/32 0 0 0 1 1 0 thru 239 000000h - EFFFFFh 15MB Lower 15/16 0 0 1 0 0 0 thru 223 000000h - DFFFFFh 14MB Lower 7/8 0 0 1 0 1 0 thru 191 000000h - BFFFFFh 12MB Lower 3/4 0 0 1 1 0 0 thru 127 000000h - 7FFFFFh 8MB Lower 1/2 0 1 0 0 1 4 thru 255 040000h - FFFFFFh 16,128KB Upper 63/64 0 1 0 1 0 8 thru 255 080000h - FFFFFFh 15,872KB Upper 31/32 0 1 0 1 1 16 thru 255 100000h - FFFFFFh 15MB Upper 15/16 0 1 1 0 0 32 thru 255 200000h - FFFFFFh 14MB Upper 7/8 0 1 1 0 1 64 thru 255 400000h - FFFFFFh 12MB Upper 3/4 0 1 1 1 0 128 thru 255 800000h - FFFFFFh 8MB Upper 1/2 X X 1 1 1 NONE NONE NONE NONE 1 0 0 0 1 0 thru 255 000000h - FFEFFFh 16,380KB L - 4095/4096 1 0 0 1 0 0 thru 255 000000h - FFDFFFh 16,376KB L - 2047/2048 1 0 0 1 1 0 thru 255 000000h - FFBFFFh 16,368KB L - 1023/1024 1 0 1 0 X 0 thru 255 000000h - FF7FFFh 16,352KB L - 511/512 1 1 0 0 1 0 thru 255 001000h - FFFFFFh 16,380KB U - 4095/4096 1 1 0 1 0 0 thru 255 002000h - FFFFFFh 16,376KB U - 2047/2048 1 1 0 1 1 0 thru 255 004000h - FFFFFFh 16,368KB U -1023/1024 1 1 1 0 X 0 thru 255 008000h - FFFFFFh 16,352KB U - 511/512 Notes: 1. X = don't care 2. L = Lower; U = Upper 3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored. - 17 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2 INSTRUCTIONS The instruction set of the W25Q128BV consists of thirty five basic instructions that are fully controlled through the SPI bus (see Instruction Set table1-3). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first. Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don't care), and in some cases, a combination. Instructions are completed with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in Figures 4 through 37. All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed. 7.2.1 Manufacturer and Device Identification MANUFACTURER ID (MF7-MF0) Winbond Serial Flash EFh Device ID (ID7-ID0) (ID15-ID0) Instruction ABh, 90h, 92h, 94h 9Fh W25Q128BV 17h 4018h - 18 - W25Q128BV 7.2.2 Instruction Set Table 1 (Erase, Program Instructions)(1) INSTRUCTION NAME Write Enable BYTE 1 (CODE) BYTE 2 BYTE 3 BYTE 4 BYTE 5 06h Write Enable for Volatile Status Register 50h Write Disable 04h Read Status Register-1 05h (S7-S0) Read Status Register-2 35h (S15-S8) Write Status Register 01h S7-S0 S15-S8 Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0 Quad Page Program 32h A23-A16 A15-A8 A7-A0 D7-D0, ... Sector Erase (4KB) 20h A23-A16 A15-A8 A7-A0 Block Erase (32KB) 52h A23-A16 A15-A8 A7-A0 Block Erase (64KB) D8h A23-A16 A15-A8 A7-A0 Chip Erase 75h Erase / Program Resume 7Ah Power-down B9h Continuous Read Mode (4) (2) (2) (3) C7h/60h Erase / Program Suspend Reset BYTE 6 FFh FFh Notes: 1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis "()" indicate data being read from the device on the DO pin. 2. The Status Register contents will repeat continuously until /CS terminates the instruction. 3. Quad Page Program Input Data: IO0 = D4, D0, ...... IO1 = D5, D1, ...... IO2 = D6, D2, ...... IO3 = D7, D3, ...... 4. This instruction is recommended when using the Dual or Quad "Continuous Read Mode" feature. See section 7.2.19 & 7.2.20 for more information. - 19 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.3 Instruction Set Table 2 (Read Instructions) BYTE 1 (CODE) BYTE 2 BYTE 3 BYTE 4 BYTE 5 Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0) Fast Read 0Bh A23-A16 A15-A8 A7-A0 dummy Fast Read Dual Output 3Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, ...) Fast Read Quad Output 6Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, ...) Fast Read Dual I/O BBh A23-A8 Fast Read Quad I/O EBh A23-A0, M7-M0 (4) (x,x,x,x, D7-D0, ...) (D7-D0, ...) E7h A23-A0, M7-M0 (4) (x,x, D7-D0, ...) (6) (D7-D0, ...) E3h A23-A0, M7-M0 (4) (D7-D0, ...) 77h xxxxxx, W6-W4 INSTRUCTION NAME Word Read Quad I/O (7) Octal Word Read Quad I/O Set Burst with Wrap (8) (2) A7-A0, M7-M0 (2) (1) (D7-D0, ...) (5) (3) (3) (4) Notes: 1. Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 3. Quad Output Data IO0 = (D4, D0, .....) IO1 = (D5, D1, .....) IO2 = (D6, D2, .....) IO3 = (D7, D3, .....) 4. Quad Input Address Set Burst with Wrap Input IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO0 = x, x, x, x, x, x, W4, x IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO1 = x, x, x, x, x, x, W5, x IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO2 = x, x, x, x, x, x, W6, x IO3 = A23, A19, A15, A11, A7, A3, M7, M3 IO3 = x, x, x, x, x, x, x, x 5. Fast Read Quad I/O Data IO0 = (x, x, x, x, D4, D0, .....) IO1 = (x, x, x, x, D5, D1, .....) IO2 = (x, x, x, x, D6, D2, .....) IO3 = (x, x, x, x, D7, D3, .....) 6. Word Read Quad I/O Data IO0 = (x, x, D4, D0, .....) IO1 = (x, x, D5, D1, .....) IO2 = (x, x, D6, D2, .....) IO3 = (x, x, D7, D3, .....) 7. The lowest address bit must be 0. ( A0 = 0 ) 8. The lowest 4 address bits must be 0. ( A0, A1, A2, A3 = 0 ) - 20 - (3) BYTE 6 (D7-D0) (1) (3) W25Q128BV 7.2.4 Instruction Set Table 3 (ID, Security Instructions) INSTRUCTION NAME BYTE 1 (CODE) BYTE 2 BYTE 3 BYTE 4 ABh dummy dummy dummy 90h dummy dummy 00h 92h A23-A8 A7-A0, M[7:0] (MF[7:0], ID[7:0]) 94h A23-A0, M[7:0] xxxx, (MF[7:0], ID[7:0]) (MF[7:0], ID[7:0], ...) Release Power down/ Device ID Manufacturer/ Device ID (2) Manufacturer/Device ID by Dual I/O Manufacture/Device ID by Quad I/O (MF7-MF0) (ID7-ID0) (ID15-ID8) (ID7-ID0) Memory Type Capacity 4Bh dummy dummy dummy dummy (ID63-ID0) 5Ah 00h 00h A7-A0 dummy (D7-0) (3) 44h A23-A16 A15-A8 A7-A0 (3) 42h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0 (3) 48h A23-A16 A15-A8 A7-A0 dummy (D7-0) Read Unique ID Read SFDP Register Erase Program Read Security Registers (1) (ID7-ID0) (MF7-MF0) 9Fh Security Registers BYTE 6 Manufacturer JEDEC ID Security Registers BYTE 5 Notes: 1. The Device ID will repeat continuously until /CS terminates the instruction. 2. See Manufacturer and Device Identification table for Device ID information. 3. Security Register Address: Security Register 1: Security Register 2: Security Register 3: A23-16 = 00h; A23-16 = 00h; A23-16 = 00h; A15-8 = 10h; A15-8 = 20h; A15-8 = 30h; A7-0 = byte address A7-0 = byte address A7-0 = byte address - 21 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.5 Write Enable (06h) The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to a 1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction. The Write Enable instruction is entered by driving /CS low, shifting the instruction code "06h" into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 Mode 0 Mode 3 Mode 0 Instruction (06h) DI (IO0) High Impedance DO (IO1) Figure 4. Write Enable Instruction Sequence Diagram 7.2.6 Write Enable for Volatile Status Register (50h) The non-volatile Status Register bits described in section 7.1 can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register nonvolatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable for Volatile Status Register instruction (Figure 5) will not set the Write Enable Latch (WEL) bit, it is only valid for the Write Status Register instruction to change the volatile Status Register bit values. /CS Mode 3 CLK 0 1 2 3 4 Mode 0 5 6 7 Mode 3 Mode 0 Instruction (50h) DI (IO0) DO (IO1) High Impedance Figure 5. Write Enable for Volatile Status Register Instruction Sequence Diagram - 22 - W25Q128BV 7.2.7 Write Disable (04h) The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register to a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code "04h" into the DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page Program, Sector Erase, Block Erase and Chip Erase instructions. Write Disable instruction can also be used to invalidate the Write Enable for Volatile Status Register instruction. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 Mode 0 Mode 3 Mode 0 Instruction (04h) DI (IO0) DO (IO1) High Impedance Figure 6. Write Disable Instruction Sequence Diagram - 23 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.8 Read Status Register-1 (05h) and Read Status Register-2 (35h) The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving /CS low and shifting the instruction code "05h" for Status Register-1 or "35h" for Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 7. The Status Register bits are shown in Figure 3a and 3b and include the BUSY, WEL, BP2-BP0, TB, SEC, SRP0, SRP1, QE, LB[3:1], CMP and SUS bits (see Status Register section earlier in this datasheet). The Read Status Register instruction may be used at any time, even while a Program, Erase or Write Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The Status Register can be read continuously, as shown in Figure 7. The instruction is completed by driving /CS high. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 Instruction (05h or 35h) DI (IO0) High Impedance DO (IO1) * Status Register 1 or 2 out 7 6 5 4 * = MSB 3 2 1 Status Register 1 or 2 out 0 7 6 5 4 3 2 1 0 7 * Figure 7. Read Status Register Instruction Sequence Diagram 7.2.9 Write Status Register (01h) The Write Status Register instruction allows the Status Register to be written. Only non-volatile Status Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7 thru 2 of Status Register-1) and CMP, LB3, LB2, LB1, QE, SRP1 (bits 14 thru 8 of Status Register-2) can be written to. All other Status Register bit locations are read-only and will not be affected by the Write Status Register instruction. LB[3:1] are nonvolatile OTP bits, once it is set to 1, it can not be cleared to 0. The Status Register bits are shown in Figure 3 and described in 7.1. To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have been executed for the device to accept the Write Status Register Instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction code "01h", and then writing the status register data byte as illustrated in Figure 8. To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However, SRP1 and LB3, LB2, LB1 can not be changed from "1" to "0" because of the OTP protection for these bits. Upon power off, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will be restored when power on again. - 24 - W25Q128BV To complete the Write Status Register instruction, the /CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not be executed. If /CS is driven high after the eighth clock (compatible with the 25X series) the CMP and QE bits will be cleared to 0. During non-volatile Status Register write operation (06h combined with 01h), after /CS is driven high, the self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics). While the Write Status Register cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0. During volatile Status Register write operation (50h combined with 01h), after /CS is driven high, the Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period. Please refer to 7.1 for detailed Status Register Bit descriptions. Factory default for all status Register bits are 0. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 Mode 0 Instruction (01h) DI (IO0) Mode 3 Status Register 1 in 7 6 5 4 3 * 2 Status Register 2 in 1 0 15 14 13 12 11 10 9 8 * High Impedance DO (IO1) * = MSB Figure 8. Write Status Register Instruction Sequence Diagram - 25 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.10 Read Data (03h) The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The instruction is initiated by driving the /CS pin low and then shifting the instruction code "03h" followed by a 24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by driving /CS high. The Read Data instruction sequence is shown in Figure 9. If a Read Data instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of f R (see AC Electrical Characteristics). /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 Mode 0 Instruction (03h) DI (IO0) 24-Bit Address 23 22 21 3 2 1 0 * Data Out 1 High Impedance DO (IO1) 7 * * = MSB Figure 9. Read Data Instruction Sequence Diagram - 26 - 6 5 4 3 2 1 0 7 W25Q128BV 7.2.11 Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight "dummy" clocks after the 24-bit address as shown in Figure 10. The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the DO pin is a "don't care". /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Mode 0 Instruction (0Bh) 24-Bit Address DI (IO0) 23 22 21 42 43 3 2 1 0 45 46 47 48 * High Impedance DO (IO1) * = MSB /CS 31 32 33 34 35 36 37 38 39 40 41 44 49 50 51 52 53 54 55 CLK Dummy Clocks DI (IO0) DO (IO1) 0 High Impedance Data Out 1 7 6 5 4 * 3 Data Out 2 2 1 0 7 6 5 4 3 2 1 0 7 * Figure 10. Fast Read Instruction Sequence Diagram - 27 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.12 Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins; IO0 and IO1. This allows data to be transferred from the W25Q128BV at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for applications that cache code-segments to RAM for execution. Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight "dummy" clocks after the 24-bit address as shown in Figure 11. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is "don't care". However, the IO0 pin should be high-impedance prior to the falling edge of the first data out clock. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Mode 0 Instruction (3Bh) 24-Bit Address DI (IO0) 23 22 21 42 43 3 2 1 0 45 46 47 48 * High Impedance DO (IO1) * = MSB /CS 31 32 33 34 35 36 37 38 39 40 41 44 49 50 51 52 53 54 55 CLK IO0 switches from Input to Output Dummy Clocks DI (IO0) DO (IO1) 0 6 High Impedance 7 * 4 2 0 6 5 3 1 7 Data Out 1 * 4 2 0 6 5 3 1 7 Data Out 2 * 4 2 0 6 5 3 1 7 Data Out 3 Figure 11. Fast Read Dual Output Instruction Sequence Diagram - 28 - * 4 2 0 6 5 3 1 7 Data Out 4 W25Q128BV 7.2.13 Fast Read Quad Output (6Bh) The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except that data is output on four pins, IO0, IO1, IO2, and IO3. A Quad enable of Status Register-2 must be executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the W25Q128BV at four times the rate of standard SPI devices. The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight "dummy" clocks after the 24-bit address as shown in Figure 12. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is "don't care". However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Mode 0 Instruction (6Bh) 24-Bit Address IO0 23 High Impedance IO1 22 21 42 43 3 2 1 45 46 47 0 * High Impedance IO2 High Impedance IO3 * = MSB /CS 31 32 33 34 35 36 37 38 39 40 41 44 CLK IO0 switches from Input to Output Dummy Clocks IO0 IO1 IO2 IO3 0 High Impedance High Impedance High Impedance 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 Byte 1 Byte 2 Byte 3 Byte 4 Figure 12. Fast Read Quad Output Instruction Sequence Diagram - 29 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.14 Fast Read Dual I/O (BBh) The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications. Fast Read Dual I/O with "Continuous Read Mode" The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the "Continuous Read Mode" bits (M7-0) after the input Address bits (A23-0), as shown in Figure 13a. The upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don't care ("x"). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the "Continuous Read Mode" bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS is raised and then lowered) does not require the BBh instruction code, as shown in Figure 13b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the "Continuous Read Mode" bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A "Continuous Read Mode" Reset instruction can also be used to reset (M7-0) before issuing normal instructions (See 7.2.20 for detail descriptions). /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 Instruction (BBh) A23-16 A15-8 A7-0 M7-0 DI (IO0) 22 20 18 16 14 12 10 8 6 4 2 0 DO (IO1) 23 21 19 17 15 13 11 9 7 5 3 1 * * = MSB 6 4 2 0 7 5 3 1 * /CS 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 CLK IOs switch from Input to Output DI (IO0) 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 DO (IO1) 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 * Byte 1 * Byte 2 * Byte 3 * Byte 4 Figure 13a. Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4 10) - 30 - W25Q128BV /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 0 A23-16 A15-8 A7-0 M7-0 DI (IO0) 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 DO (IO1) 23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 30 31 * * * = MSB /CS 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 CLK IOs switch from Input to Output DI (IO0) 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 DO (IO1) 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 * Byte 1 * Byte 2 * Byte 3 * Byte 4 Figure 13b. Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10) - 31 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.15 Fast Read Quad I/O (EBh) The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy clock are required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction. Fast Read Quad I/O with "Continuous Read Mode" The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the "Continuous Read Mode" bits (M7-0) after the input Address bits (A23-0), as shown in Figure 14a. The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don't care ("x"). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the "Continuous Read Mode" bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the EBh instruction code, as shown in Figure 14b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the "Continuous Read Mode" bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A "Continuous Read Mode" Reset instruction can also be used to reset (M7-0) before issuing normal instructions (See 7.2.20 for detail descriptions). /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 Instruction (EBh) A23-16 A15-8 A7-0 M7-0 Dummy IOs switch from Input to Output Dummy IO0 20 16 12 8 4 0 4 0 4 0 4 0 4 IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 Byte 1 Byte 2 Figure 14a. Fast Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 10) - 32 - Byte 3 W25Q128BV /CS Mode 3 CLK 0 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 Mode 0 A23-16 A15-8 A7-0 M7-0 Dummy IOs switch from Input to Output Dummy IO0 20 16 12 8 4 0 4 0 4 0 4 0 4 IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 Byte 1 Byte 2 Byte 3 Figure 14b. Fast Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) Fast Read Quad I/O with "8/16/32/64-Byte Wrap Around" The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a "Set Burst with Wrap" command prior to EBh. The "Set Burst with Wrap" command can either enable or disable the "Wrap Around" feature for the following EBh commands. When "Wrap Around" is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The "Set Burst with Wrap" instruction allows three "Wrap Bits", W6-4 to be set. The W4 bit is used to enable or disable the "Wrap Around" operation while W6-5 are used to specify the length of the wrap around section within a page. See 7.2.18 for detail descriptions. - 33 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.16 Word Read Quad I/O (E7h) The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lowest Address bit (A0) must equal 0 and only two Dummy clocks are required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Word Read Quad I/O Instruction. Word Read Quad I/O with "Continuous Read Mode" The Word Read Quad I/O instruction can further reduce instruction overhead through setting the "Continuous Read Mode" bits (M7-0) after the input Address bits (A23-0), as shown in Figure 15a. The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don't care ("x"). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the "Continuous Read Mode" bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the E7h instruction code, as shown in Figure 15b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the "Continuous Read Mode" bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A "Continuous Read Mode" Reset instruction can also be used to reset (M7-0) before issuing normal instructions (See 7.2.20 for detail descriptions). /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Mode 0 Instruction (E7h) A23-16 A15-8 A7-0 M7-0 IOs switch from Input to Output Dummy IO0 20 16 12 8 4 0 4 0 4 0 4 0 4 IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 Byte 1 Byte 2 Figure 15a. Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 10) - 34 - Byte 3 W25Q128BV /CS Mode 3 CLK 0 1 2 3 4 6 5 7 8 9 10 11 12 13 Mode 0 A23-16 A15-8 M7-0 A7-0 IOs switch from Input to Output Dummy IO0 20 16 12 8 4 0 4 0 4 0 4 0 4 IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 Byte 1 Byte 2 Byte 3 Figure 15b. Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) Word Read Quad I/O with "8/16/32/64-Byte Wrap Around" The Word Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a "Set Burst with Wrap" command prior to E7h. The "Set Burst with Wrap" command can either enable or disable the "Wrap Around" feature for the following E7h commands. When "Wrap Around" is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The "Set Burst with Wrap" instruction allows three "Wrap Bits", W6-4 to be set. The W4 bit is used to enable or disable the "Wrap Around" operation while W6-5 are used to specify the length of the wrap around section within a page. See 7.2.18 for detail descriptions. - 35 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.17 Octal Word Read Quad I/O (E3h) The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the dummy clocks are not required, which further reduces the instruction overhead allowing even faster random access for code execution (XIP). The Quad Enable bit (QE) of Status Register-2 must be set to enable the Octal Word Read Quad I/O Instruction. Octal Word Read Quad I/O with "Continuous Read Mode" The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the "Continuous Read Mode" bits (M7-0) after the input Address bits (A23-0), as shown in Figure 16a. The upper nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don't care ("x"). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the "Continuous Read Mode" bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the E3h instruction code, as shown in Figure 16b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the "Continuous Read Mode" bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A "Continuous Read Mode" Reset instruction can also be used to reset (M7-0) before issuing normal instructions (See 7.2.20 for detail descriptions). /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Mode 0 Instruction (E3h) A23-16 A15-8 A7-0 IOs switch from Input to Output M7-0 IO0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 Byte 1 Byte 2 Byte 3 Figure 16a. Octal Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 10) - 36 - Byte 4 W25Q128BV /CS Mode 3 CLK 0 1 2 3 4 6 5 7 8 9 10 11 12 13 Mode 0 A23-16 A15-8 A7-0 IOs switch from Input to Output M7-0 IO0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 Byte 1 Byte 2 Byte 3 Byte 4 Figure 16b. Octal Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) - 37 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.18 Set Burst with Wrap (77h) The Set Burst with Wrap (77h) instruction is used in conjunction with "Fast Read Quad I/O" and "Word Read Quad I/O" instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. Certain applications can benefit from this feature and improve the overall system code execution performance. Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low and then shifting the instruction code "77h" followed by 24 dummy bits and 8 "Wrap Bits", W7-0. The instruction sequence is shown in Figure 17. Wrap bit W7 and the lower nibble W3-0 are not used. W4 = 0 W6, W5 0 0 1 1 W4 =1 (DEFAULT) Wrap Around Wrap Length Wrap Around Wrap Length Yes Yes Yes Yes 8-byte 16-byte 32-byte 64-byte No No No No N/A N/A N/A N/A 0 1 0 1 Once W6-4 is set by a Set Burst with Wrap instruction, all the following "Fast Read Quad I/O" and "Word Read Quad I/O" instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the "Wrap Around" function and return to normal read operation, another Set Burst with Wrap instruction should be issued to set W4 = 1. The default value of W4 upon power on is 1. In the case of a system Reset while W4 = 0, it is recommended that the controller issues a Set Burst with Wrap instruction to reset W4 = 1 prior to any normal Read instructions since W25Q128BV does not have a hardware Reset Pin. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 0 Mode 3 Mode 0 don't care Instruction (77h) don't care don't care Wrap Bit IO0 X X X X X X w4 X IO1 X X X X X X w5 X IO2 X X X X X X w6 X IO3 X X X X X X X X Figure 17. Set Burst with Wrap Instruction Sequence - 38 - W25Q128BV 7.2.19 Continuous Read Mode Bits (M7-0) The "Continuous Read Mode" bits are used in conjunction with "Fast Read Dual I/O", "Fast Read Quad I/O", "Word Read Quad I/O" and "Octal Word Read Quad I/O" instructions to provide the highest random Flash memory access rate with minimum SPI instruction overhead, thus allow true XIP (execute in place) to be performed on serial flash devices. M7-0 need to be set by the Dual/Quad I/O Read instructions. M5-4 are used to control whether the 8-bit SPI instruction code (BBh, EBh, E7h or E3h) is needed or not for the next command. When M5-4 = (1,0), the next command will be treated same as the current Dual/Quad I/O Read command without needing the 8-bit instruction code; when M5-4 do not equal to (1,0), the device returns to normal SPI mode, all commands can be accepted. M7-6 and M3-0 are reserved bits for future use, either 0 or 1 values can be used. 7.2.20 Continuous Read Mode Reset (FFh or FFFFh) Continuous Read Mode Reset instruction can be used to set M4 = 1, thus the device will release the Continuous Read Mode and return to normal SPI operation, as shown in Figure 18. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Mode 0 15 Mode 3 Mode 0 Mode Bit Reset for Quad I/O (FFh) Mode Bit Reset for Dual I/O (FFFFh) IO0 IO1 Don't Care IO2 Don't Care IO3 Don't Care Figure 18. Continuous Read Mode Reset for Fast Read Dual/Quad I/O Since W25Q128BV does not have a hardware Reset pin, so if the controller resets while W25Q128BV is set to Continuous Mode Read, the W25Q128BV will not recognize any initial standard SPI instructions from the controller. To address this possibility, it is recommended to issue a Continuous Read Mode Reset instruction as the first instruction after a system Reset. Doing so will release the device from the Continuous Read Mode and allow Standard SPI instructions to be recognized. To reset "Continuous Read Mode" during Quad I/O operation, only eight clocks are needed. The instruction is "FFh". To reset "Continuous Read Mode" during Dual I/O operation, sixteen clocks are needed to shift in instruction "FFFFh". - 39 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.21 Page Program (02h) The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code "02h" followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. The Page Program instruction sequence is shown in Figure 19. If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the same page. One condition to perform a partial page program is that the number of clocks can not exceed the remaining page length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits. /CS Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 Mode 0 2 1 * 0 6 5 4 3 2 1 0 2079 3 2078 21 2077 22 2076 23 Data Byte 1 2075 24-Bit Address 2074 Instruction (02h) DI (IO0) 2073 CLK 7 * * = MSB 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 /CS CLK Mode 0 Data Byte 2 DI (IO0) Mode 3 0 7 * 6 5 4 3 Data Byte 3 2 1 0 7 6 5 4 3 * Data Byte 256 2 1 0 7 6 * Figure 19. Page Program Instruction Sequence Diagram - 40 - 5 4 3 2 1 0 W25Q128BV 7.2.22 Quad Input Page Program (32h) The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can improve performance for PROM Programmer and applications that have slow clock speeds <5MHz. Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction since the inherent page program time is much greater than the time it take to clock-in the data. To use Quad Page Program the Quad Enable in Status Register-2 must be set (QE=1). A Write Enable instruction must be executed before the device will accept the Quad Page Program instruction (Status Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then shifting the instruction code "32h" followed by a 24-bit address (A23-A0) and at least one data byte, into the IO pins. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. All other functions of Quad Page Program are identical to standard Page Program. The Quad Page Program instruction sequence is shown in Figure 20. /CS Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Mode 0 22 21 3 2 1 543 23 542 IO0 539 24-Bit Address 538 Instruction (32h) 541 CLK 0 * IO1 IO2 IO3 * = MSB 33 34 35 36 37 540 32 537 31 536 /CS CLK Mode 0 Byte 253 Byte 254 Byte 255 Byte 256 Byte 1 Byte 2 Byte 3 4 0 4 0 4 0 4 0 4 0 4 0 4 0 IO1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 IO2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 IO3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 IO0 Mode 3 0 * * * * * * * Figure 20. Quad Input Page Program Instruction Sequence Diagram - 41 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.23 Sector Erase (20h) The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "20h" followed a 24-bit sector address (A23-A0) (see Figure 2). The Sector Erase instruction sequence is shown in Figure 21. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Sector Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 29 30 31 Mode 0 Mode 3 Mode 0 Instruction (20h) 24-Bit Address DI (IO0) DO (IO1) 9 23 22 2 * High Impedance * = MSB Figure 21. Sector Erase Instruction Sequence Diagram - 42 - 1 0 W25Q128BV 7.2.24 32KB Block Erase (52h) The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "52h" followed a 24-bit block address (A23-A0) (see Figure 2). The Block Erase instruction sequence is shown in Figure 22. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction will commence for a time duration of tBE1 (See AC Characteristics). While the Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 29 30 31 Mode 3 Mode 0 Instruction (52h) DI (IO0) DO (IO1) 9 Mode 0 24-Bit Address 23 22 2 1 0 * High Impedance * = MSB Figure 22. 32KB Block Erase Instruction Sequence Diagram - 43 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.25 64KB Block Erase (D8h) The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "D8h" followed a 24-bit block address (A23-A0) (see Figure 2). The Block Erase instruction sequence is shown in Figure 23. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction will commence for a time duration of tBE (See AC Characteristics). While the Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 29 30 31 Mode 3 Mode 0 Instruction (D8h) 24-Bit Address DI (IO0) DO (IO1) 9 Mode 0 23 22 2 * High Impedance * = MSB Figure 23. 64KB Block Erase Instruction Sequence Diagram - 44 - 1 0 W25Q128BV 7.2.26 Chip Erase (C7h / 60h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "C7h" or "60h". The Chip Erase instruction sequence is shown in Figure 24. The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). /CS Mode 3 CLK 0 1 2 3 4 5 6 7 Mode 0 Mode 3 Mode 0 Instruction (C7h/60h) DI (IO0) DO (IO1) High Impedance Figure 24. Chip Erase Instruction Sequence Diagram - 45 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.27 Erase / Program Suspend (75h) The Erase/Program Suspend instruction "75h", allows the system to interrupt a Sector or Block Erase operation or a Page Program operation and then read from or program/erase data to, any other sectors or blocks. The Erase/Program Suspend instruction sequence is shown in Figure 25. The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h) are not allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status Register instruction (01h) and Program instructions (02h, 32h, 42h) are not allowed during Program Suspend. Program Suspend is valid only during the Page Program or Quad Page Program operation. The Erase/Program Suspend instruction "75h" will be accepted by the device only if the SUS bit in the Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page Program operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend instruction will be ignored by the device. A maximum of time of "tSUS" (See AC Characteristics) is required to suspend the erase or program operation. The BUSY bit in the Status Register will be cleared from 1 to 0 within "tSUS" and the SUS bit in the Status Register will be set from 0 to 1 immediately after Erase/Program Suspend. For a previously resumed Erase/Program operation, it is also required that the Suspend instruction "75h" is not issued earlier than a minimum of time of "tSUS" following the preceding Resume instruction "7Ah". Unexpected power off during the Erase/Program suspend state will reset the device and release the suspend state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block that was being suspended may become corrupted. When the device is powered up again, it is recommended for the user to repeat the same Erase or Program operation that was interrupted, at the same address location, to avoid the potention data corruption. /CS tSUS Mode 3 CLK 0 1 2 3 4 5 6 7 Mode 0 Mode 3 Mode 0 Instruction (75h) DI (IO0) DO (IO1) High Impedance Accept instructions Figure 25. Erase/Program Suspend Instruction Sequence - 46 - W25Q128BV 7.2.28 Erase / Program Resume (7Ah) The Erase/Program Resume instruction "7Ah" must be written to resume the Sector or Block Erase operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction "7Ah" will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit equals to 0. After issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume instruction "7Ah" will be ignored by the device. The Erase/Program Resume instruction sequence is shown in Figure 26. Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by unexpected power off. It is also required that a subsequent Erase/Program Suspend instruction not to be issued within a minimum of time of "tSUS" following a previous Resume instruction. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 Mode 3 Mode 0 Mode 0 Instruction (7Ah) DI (IO0) Resume previously suspended Program or Erase Figure 26. Erase/Program Resume Instruction Sequence - 47 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.29 Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code "B9h" as shown in Figure 27. The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-down instruction will not be executed. After /CS is driven high, the power-down state will entered within the time duration of tDP (See AC Characteristics). While in the power-down state only the Release from Powerdown / Device ID instruction, which restores the device to normal operation, will be recognized. All other instructions are ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. /CS tDP Mode 3 CLK 0 1 2 3 4 5 6 7 Mode 3 Mode 0 Mode 0 Instruction (B9h) DI (IO0) Stand-by current Figure 27. Deep Power-down Instruction Sequence Diagram - 48 - Power-down current W25Q128BV 7.2.30 Release Power-down / Device ID (ABh) The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, or obtain the devices electronic identification (ID) number. To release the device from the power-down state, the instruction is issued by driving the /CS pin low, shifting the instruction code "ABh" and driving /CS high as shown in Figure 28a. Release from powerdown will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other instructions are accepted. The /CS pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by driving the /CS pin low and shifting the instruction code "ABh" followed by 3-dummy bytes. The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 28a. The Device ID values for the W25Q128BV is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high. When used to release the device from the power-down state and obtain the Device ID, the instruction is the same as previously described, and shown in Figure 28b, except that after /CS is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other instructions will be accepted. If the Release from Power-down / Device ID instruction is issued while an Erase, Program or Write cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on the current cycle. /CS tRES1 Mode 3 CLK 0 1 2 3 4 5 6 7 Mode 3 Mode 0 Mode 0 Instruction (ABh) DI (IO0) Power-down current Stand-by current Figure 28a. Release Power-down Instruction Sequence - 49 - Publication Release Date: October 03, 2013 Revision H W25Q128BV /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 Mode 3 Mode 0 Mode 0 Instruction (ABh) DI (IO0) tRES2 3 Dummy Bytes 23 22 2 1 0 * Device ID High Impedance DO (IO1) 7 6 5 4 3 2 1 0 * * = MSB Power-down current Figure 28b. Release Power-down / Device ID Instruction Sequence Diagram - 50 - Stand-by current W25Q128BV 7.2.31 Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device ID instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code "90h" followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 29. The Device ID values for the W25Q128BV is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving /CS high. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Mode 0 Instruction (90h) Address (000000h) DI (IO0) 23 22 21 42 43 3 2 45 46 1 0 * High Impedance DO (IO1) * = MSB /CS 31 32 33 34 35 36 37 38 39 40 41 44 Mode 3 CLK DI (IO0) Mode 0 0 DO (IO1) 7 Manufacturer ID (EFh) * 6 5 4 3 2 1 0 Device ID Figure 29. Read Manufacturer / Device ID Diagram - 51 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.32 Read Manufacturer / Device ID Dual I/O (92h) The Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 2x speed. The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code "92h" followed by a 24-bit address (A23-A0) of 000000h, 8-bit Continuous Read Mode Bits, with the capability to input the Address bits two bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out 2 bits per clock on the falling edge of CLK with most significant bits (MSB) first as shown in Figure 30. The Device ID values for the W25Q128BV is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving /CS high. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 Instruction (92h) A23-16 DI (IO0) High Impedance DO (IO1) * = MSB A15-8 A7-0 (00h) M7-0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 * * * * /CS 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Mode 3 CLK Mode 0 IOs switch from Input to Output DI (IO0) 0 6 4 2 0 6 4 2 0 6 DO (IO1) 1 7 5 3 1 7 5 3 1 * MFR ID * Device ID 4 2 0 6 7 5 3 1 7 * MFR ID (repeat) * 4 2 0 5 3 1 Device ID (repeat) Figure 30. Read Manufacturer / Device ID Dual I/O Diagram Note: The "Continuous Read Mode" bits M7-0 must be set to Fxh to be compatible with Fast Read Dual I/O instruction. - 52 - W25Q128BV 7.2.33 Read Manufacturer / Device ID Quad I/O (94h) The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 4x speed. The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code "94h" followed by a 24-bit address (A23-A0) of 000000h, 8-bit Continuous Read Mode Bits and then four clock dummy cycles, with the capability to input the Address bits four bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out four bits per clock on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 31. The Device ID values for the W25Q128BV is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving /CS high. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 Instruction (94h) IO0 High Impedance IO1 High Impedance IO2 High Impedance IO3 A7-0 (00h) M7-0 Dummy IOs switch from Input to Output A23-16 A15-8 Dummy 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 MFR ID Device ID /CS 23 24 25 26 27 28 29 30 Mode 3 CLK Mode 0 IO0 0 4 0 4 0 4 0 4 0 IO1 1 5 1 5 1 5 1 5 1 IO2 2 6 2 6 2 6 2 6 2 IO3 3 7 3 7 3 7 3 7 3 MFR ID (repeat) Device ID (repeat) MFR ID (repeat) Device ID (repeat) Figure 31. Read Manufacturer / Device ID Quad I/O Diagram Note: The "Continuous Read Mode" bits M7-0 must be set to Fxh to be compatible with Fast Read Quad I/O instruction. - 53 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.34 Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q128BV device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin low and shifting the instruction code "4Bh" followed by a four bytes of dummy clocks. After which, the 64bit ID is shifted out on the falling edge of CLK as shown in Figure 32. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 Instruction (4Bh) Dummy Byte 1 Dummy Byte 2 DI (IO0) High Impedance DO (IO1) 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 102 24 101 23 100 /CS Mode 3 CLK Mode 0 Dummy Byte 3 Dummy Byte 4 DI (IO0) DO (IO1) High Impedance * = MSB 63 62 * 64-bit Unique Serial Number 61 Figure 32. Read Unique ID Number Instruction Sequence - 54 - 2 1 0 W25Q128BV 7.2.35 Read JEDEC ID (9Fh) For compatibility reasons, the W25Q128BV provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code "9Fh". The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 33. For memory type and capacity values refer to Manufacturer and Device Identification table. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 0 Instruction (9Fh) DI (IO0) Manufacturer ID (EFh) High Impedance DO (IO1) * = MSB /CS 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Mode 3 CLK Mode 0 DI (IO0) Memory Type ID15-8 DO (IO1) 7 * 6 5 4 3 2 Capacity ID7-0 1 0 7 6 5 4 3 2 1 0 * Figure 33. Read JEDEC ID Instruction Sequence - 55 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.36 Read SFDP Register (5Ah) The W25Q128BV features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains information about device configurations, available instructions and other features. The SFDP parameters are stored in one or more Parameter Identification (PID) tables. Currently only one PID table is specified, but more may be added in the future. The Read SFDP Register instruction is compatible with the SFDP standard initially established in 2010 for PC and other applications, as well as the JEDEC standard JESD216 that is published in 2011. Most Winbond SpiFlash Memories shipped after June 2011 (date code 1124 and beyond) support the SFDP feature as specified in the applicable datasheet. The Read SFDP instruction is initiated by driving the /CS pin low and shifting the instruction code "5Ah" followed by a 24-bit address (A23-A0)(1) into the DI pin. Eight "dummy" clocks are also required before the SFDP register contents are shifted out on the falling edge of the 40th CLK with most significant bit (MSB) first as shown in Figure 34. For SFDP register values and descriptions, please refer to the Winbond Application Note for SFDP Definition Table. Note 1: A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-Byte SFDP Register. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Mode 0 Instruction (5Ah) 24-Bit Address DI (IO0) 23 22 21 42 43 3 2 1 0 45 46 47 48 * High Impedance DO (IO1) /CS 31 32 33 34 35 36 37 38 39 40 41 44 49 50 51 52 53 54 55 CLK Dummy Byte DI (IO0) 0 7 6 5 4 3 2 1 0 Data Out 1 DO (IO1) High Impedance * = MSB 7 6 5 4 * 3 Data Out 2 2 1 0 7 6 * Figure 34. Read SFDP Register Instruction Sequence Diagram - 56 - 5 4 3 2 1 0 7 W25Q128BV 7.2.37 Erase Security Registers (44h) The W25Q128BV offers three 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction must be executed before the device will accept the Erase Security Register Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "44h" followed by a 24-bit address (A23-A0) to erase one of the three security registers. ADDRESS A23-16 A15-12 A11-8 A7-0 Security Register #1 00h 0001 0000 Don't Care Security Register #2 00h 0010 0000 Don't Care Security Register #3 00h 0011 0000 Don't Care The Erase Security Register instruction sequence is shown in Figure 35. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed. After /CS is driven high, the self-timed Erase Security Register operation will commence for a time duration of tSE (See AC Characteristics). While the Erase Security Register cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Erase Security Register cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Security Register Lock Bits LB[3:1] in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will be permanently locked, Erase Security Register instruction to that register will be ignored (See 7.1.9 for detail descriptions). /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 29 30 31 Mode 0 Mode 3 Mode 0 Instruction (44h) DI (IO0) DO (IO1) 9 24-Bit Address 23 22 2 1 0 * High Impedance * = MSB Figure 35. Erase Security Registers Instruction Sequence - 57 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 7.2.38 Program Security Registers (42h) The Program Security Register instruction is similar to the Page Program instruction. It allows from one byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Program Security Register Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code "42h" followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. ADDRESS A23-16 A15-12 A11-8 A7-0 Security Register #1 00h 0001 0000 Byte Address Security Register #2 00h 0010 0000 Byte Address Security Register #3 00h 0011 0000 Byte Address The Program Security Register instruction sequence is shown in Figure 36. The Security Register Lock Bits LB[3:1] in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will be permanently locked, Program Security Register instruction to that register will be ignored (See 7.1.9, 7.2.21 for detail descriptions). /CS Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 Mode 0 2 1 0 6 5 4 3 2 1 0 2079 3 2078 21 2077 22 * 2076 23 Data Byte 1 2075 24-Bit Address 2074 Instruction (42h) DI (IO0) 2073 CLK 7 * * = MSB 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 /CS CLK Mode 0 Data Byte 2 DI (IO0) Mode 3 0 7 * 6 5 4 3 Data Byte 3 2 1 0 7 6 5 4 3 * Data Byte 256 2 1 0 7 6 5 * Figure 36. Program Security Registers Instruction Sequence - 58 - 4 3 2 1 0 W25Q128BV 7.2.39 Read Security Registers (48h) The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data bytes to be sequentially read from one of the three security registers. The instruction is initiated by driving the /CS pin low and then shifting the instruction code "48h" followed by a 24-bit address (A23-A0) and eight "dummy" clocks into the DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The byte address is automatically incremented to the next byte address after each byte of data is shifted out. Once the byte address reaches the last byte of the register (byte FFh), it will reset to 00h, the first byte of the register, and continue to increment. The instruction is completed by driving /CS high. The Read Security Register instruction sequence is shown in Figure 37. If a Read Security Register instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Security Register instruction allows clock rates from D.C. to a maximum of FR (see AC Electrical Characteristics). ADDRESS A23-16 A15-12 A11-8 A7-0 Security Register #1 00h 0001 0000 Byte Address Security Register #2 00h 0010 0000 Byte Address Security Register #3 00h 0011 0000 Byte Address /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Mode 0 Instruction (48h) 24-Bit Address DI (IO0) 23 22 21 42 43 3 2 1 0 45 46 47 48 * High Impedance DO (IO1) * = MSB /CS 31 32 33 34 35 36 37 38 39 40 41 44 49 50 51 52 53 54 55 CLK Dummy Byte DI (IO0) 0 7 6 5 4 3 2 1 0 Data Out 1 DO (IO1) High Impedance 7 6 5 4 * 3 Data Out 2 2 1 0 7 6 5 4 3 2 1 0 7 * Figure 37. Read Security Registers Instruction Sequence - 59 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 8. ELECTRICAL CHARACTERISTICS 8.1 Absolute Maximum Ratings (1)(2) PARAMETERS SYMBOL Supply Voltage VCC Voltage Applied to Any Pin VIO Transient Voltage on any Pin VIOT Storage Temperature CONDITIONS RANGE UNIT -0.6 to VCC+0.6 V Relative to Ground -0.6 to VCC+0.4 V <20nS Transient Relative to Ground -2.0V to VCC+2.0V V TSTG -65 to +150 C Lead Temperature TLEAD See Note C Electrostatic Discharge Voltage VESD(3) -2000 to +2000 V Human Body Model Notes: 1.This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent damage. 2.JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms). 3.Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU. 8.2 Operating Ranges PARAMETER Supply Voltage Ambient Temperature, Operating SYMBOL CONDITIONS VCC(1) FR = 70MHz (Dual I/O & Quad SPI) FR = 104MHz (Single / Dual Output) fR = 33MHz TA Industrial SPEC MAX 2.7V 3.6V V -40 +85 C Note: 1.VCC voltage during Read can operate across the min and max range but should not exceed 10% of the programming (erase/write) voltage. - 60 - UNIT MIN W25Q128BV 8.3 Power-up Timing and Write Inhibit Threshold(1) Parameter spec Symbol MIN MAX Unit VCC (min) to /CS Low tVSL(1) 10 Time Delay Before Write Instruction tPUW(1) 1 10 ms Write Inhibit Threshold Voltage VWI 1.0 2.0 V (1) s Note: 1. These parameters are characterized only. VCC VCC (max) Program, Erase and Write Instructions are ignored /CS must track VCC VCC (min) Reset State tVSL Read Instructions Allowed Device is fully Accessible VWI tPUW Time Figure 38. Power-up Timing and Voltage Levels /CS must track VCC during VCC Ramp Up/Down VCC /CS Time Figure 43b. Power-up, Power-Down Requirement - 61 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 8.4 DC Electrical Characteristics SPEC PARAMETER SYMBOL CONDITIONS Input Capacitance CIN(1) VIN = 0V(1) 6 pF Output Capacitance Cout(1) VOUT = 0V(1) 8 pF Input Leakage ILI 2 A I/O Leakage ILO 2 A Standby Current ICC1 /CS = VCC, VIN = GND or VCC 6 50 A Power-down Current ICC2 /CS = VCC, VIN = GND or VCC 1.5 15 A Current Read Data / Dual /Quad 1MHz ICC3(2) C = 0.1 VCC / 0.9 VCC DO = Open 4/5/6 6/7.5/9 mA Current Read Data / Dual /Quad 33MHz ICC3(2) C = 0.1 VCC / 0.9 VCC DO = Open 6/7/8 9/10.5/12 mA Current Read Data / Dual /Quad 50MHz ICC3(2) C = 0.1 VCC / 0.9 VCC DO = Open 7/8/9 10/12/13.5 mA Current Read Data / Dual Output Read/Quad Output Read 80MHz ICC3(2) C = 0.1 VCC / 0.9 VCC DO = Open 10/11/12 15/16.5/18 mA Current Write Status Register ICC4 /CS = VCC 8 12 mA Current Page Program ICC5 /CS = VCC 20 25 mA Current Sector/Block Erase ICC6 /CS = VCC 20 25 mA Current Chip Erase ICC7 /CS = VCC 20 25 mA Input Low Voltage VIL VCC x 0.3 V Input High Voltage VIH Output Low Voltage VOL IOL = 1.6mA Output High Voltage VOH IOH = -100 A MIN TYP MAX VCC x 0.7 V 0.2 VCC - 0.2 Notes: 1. Tested on sample basis and specified through design and characterization data. TA = 25 C, VCC = 3V. 2. Checker Board Pattern. - 62 - UNIT V V W25Q128BV 8.5 AC Measurement Conditions PARAMETER SPEC SYMBOL Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages MIN MAX UNIT CL 30 pF TR, TF 5 ns VIN 0.2 VCC to 0.8 VCC V IN 0.3 VCC to 0.7 VCC V OUT 0.5 VCC to 0.5 VCC V Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. Input and Output Timing Reference Levels Input Levels 0.8 VCC 0.5 VCC 0.2 VCC Figure 39. AC Measurement I/O Waveform - 63 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 8.6 AC Electrical Characteristics SPEC DESCRIPTION SYMBOL ALT UNIT MIN TYP MAX Clock frequency for all Single SPI, Dual Output Instructions except Read Data (03h) FR fC1 D.C. 104 MHz Clock frequency for Dual I/O & Quad SPI Instructions FR fC2 D.C. 70 MHz Clock frequency for Read Data instruction (03h) fR fC3 D.C. 33 MHz Clock High, Low Time for all Quad SPI instructions tCLH1, tCLL1(1) 5 ns Clock High, Low Time for Single/Dual instructions except Read Data (03h) tCLH1, tCLL1(1) 4 ns Clock High, Low Time for Read Data (03h) instruction tCRLH, tCRLL(1) 8 ns Clock Rise Time peak to peak tCLCH(2) 0.1 V/ns Clock Fall Time peak to peak tCHCL(2) 0.1 V/ns 5 ns 5 ns /CS Active Setup Time relative to CLK tSLCH /CS Not Active Hold Time relative to CLK tCHSL Data In Setup Time tDVCH tDSU 2 ns Data In Hold Time tCHDX tDH 5 ns /CS Active Hold Time relative to CLK tCHSH 5 ns /CS Not Active Setup Time relative to CLK tSHCH 5 ns /CS Deselect Time (for Array Read Array Read) tSHSL tCSH 10 ns /CS Deselect Time tSHSL tCSH 50 ns tSHQZ(2) tDIS 7 ns Clock Low to Output Valid tCLQV tV 7 ns Output Hold Time tCLQX tHO Output Disable Time tCSS 0 ns Continued - next page - 64 - W25Q128BV 8.7 AC Electrical Characteristics (cont'd) SPEC DESCRIPTION SYMBOL ALT UNIT MIN TYP MAX /HOLD Active Setup Time relative to CLK tHLCH 5 ns /HOLD Active Hold Time relative to CLK tCHHH 5 ns /HOLD Not Active Setup Time relative to CLK tHHCH 5 ns /HOLD Not Active Hold Time relative to CLK tCHHL 5 ns /HOLD to Output Low-Z tHHQX(2) tLZ 7 ns /HOLD to Output High-Z tHLQZ(2) tHZ 12 ns Write Protect Setup Time Before /CS Low tWHSL(3) 20 ns Write Protect Hold Time After /CS High tSHWL(3) 100 ns tDP(2) 3 s /CS High to Standby Mode without Electronic Signature Read tRES1(2) 3 s /CS High to Standby Mode with Electronic Signature Read tRES2(2) 1.8 s /CS High to next Instruction after Suspend tSUS(2) 20 s /CS High to Power-down Mode Write Status Register Time tW 10 15 ms Byte Program Time (First Byte) (4) tBP1 30 50 s Additional Byte Program Time (After First Byte) (4) tBP2 2.5 12 s Page Program Time tPP 0.7 3 ms Sector Erase Time (4KB) tSE 30 200/400(5) ms Block Erase Time (32KB) tBE1 120 800 ms Block Erase Time (64KB) tBE2 150 1,000 ms Chip Erase Time tCE 25 40 s Notes: 1. Clock high + Clock low must be less than or equal to 1/fC. 2. Value guaranteed by design and/or characterization, not 100% tested in production. 3. Only applicable as a constraint for a Write Status Register instruction when SRP[1:0]=(0,1). 4. For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of bytes programmed. 5. Max Value tSE with <50K cycles is 200ms and >50K & <100K cycles is 400ms. - 65 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 8.8 Serial Output Timing /CS tCLH CLK IO output 8.9 tCLQV tCLQX tCLQX tCLQV tCLL MSB OUT tSHQZ LSB OUT Serial Input Timing /CS tSHSL tCHSL tSLCH tCHSH tSHCH CLK tDVCH IO input tCHDX tCLCH MSB IN tCHCL LSB IN 8.10 /HOLD Timing /CS tHLCH tCHHL tHHCH CLK tCHHH /HOLD tHLQZ tHHQX IO output IO input 8.11 /WP Timing /CS tWHSL tSHWL /WP CLK IO input Write Status Register is allowed - 66 - Write Status Register is not allowed W25Q128BV 9. PACKAGE SPECIFICATION 9.1 8-Pad WSON 8x6-mm (Package Code E) MILLIMETERS Min Nom Max Min INCHES Nom A 0.70 0.75 0.80 Max 0.028 0.030 0.031 A1 0.00 0.02 b 0.35 0.40 0.05 0.000 0.001 0.002 0.48 0.014 0.016 0.019 C 0.19 D 7.90 0.20 0.25 0.007 0.008 0.010 8.00 8.10 0.311 0.315 D2 0.319 4.60 4.65 4.70 0.181 0.183 0.185 E 5.90 6.00 6.10 0.232 0.236 0.240 E2 5.15 5.20 5.25 0.203 0.205 0.207 SYMBOL e 1.27 BSC 0.050 BSC L 0.45 0.50 0.55 0.018 0.020 0.022 y 0.00 --- 0.050 0.000 --- 0.002 - 67 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 9.2 16-Pin SOIC 300-mil (Package Code F) GAUGE PLANE DETAIL A SYMBOL Min MILLIMETERS Nom Max Min INCHES Nom Max A 2.36 2.49 2.64 0.093 0.098 0.104 A1 0.10 --- 0.30 0.004 --- 0.012 A2 --- 2.31 --- --- 0.091 --- b 0.33 0.41 0.51 0.013 0.016 0.020 C 0.18 0.23 0.28 0.007 0.009 0.011 D 10.08 10.31 10.49 0.397 0.406 0.413 E 10.01 10.31 10.64 0.394 0.406 0.419 E1 7.39 7.49 7.59 0.291 0.295 0.299 L 0.38 0.81 1.27 0.015 0.032 0.050 y --- --- 0.076 --- --- 0.003 0 --- 8 0 --- 8 e (2) 1.27 BSC. 0.050 BSC. Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. - 68 - W25Q128BV 9.3 24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 Ball Array) Note: Ball land: 0.45mm. Ball Opening: 0.35mm PCB ball land suggested <= 0.35mm Min Millimeters Nom Max Min Inches Nom Max A --- --- 1.20 --- --- 0.047 A1 0.25 0.30 0.35 0.010 0.012 0.014 A2 --- 0.85 --- --- 0.033 --- b 0.35 0.40 0.45 0.014 0.016 0.018 D 7.90 8.00 8.10 0.311 0.315 0.319 Symbol D1 E 4.00 BSC 5.90 6.00 0.157 BSC 6.10 0.232 0.236 E1 4.00 BSC 0.157 BSC SE 1.00 TYP 0.039 TYP SD 1.00 TYP 0.039 TYP e 1.00 BSC 0.039 BSC - 69 - 0.240 Publication Release Date: October 03, 2013 Revision H W25Q128BV 9.4 24-Ball TFBGA 8x6-mm (Package Code C, 6x4 Ball Array) Note: Ball land: 0.45mm. Ball Opening: 0.35mm PCB ball land suggested <= 0.35mm Min Millimeters Nom Max Min Inches Nom Max A --- --- 1.20 --- --- 0.047 A1 0.25 0.30 0.35 0.010 0.012 0.014 b 0.35 0.40 0.45 0.014 0.016 0.018 D 7.95 8.00 8.05 0.313 0.315 0.317 6.05 0.234 Symbol D1 E 5.00 BSC 5.95 6.00 0.197 BSC 0.236 E1 3.00 BSC 0.118 BSC e 1.00 BSC 0.039 BSC - 70 - 0.238 W25Q128BV 10. ORDERING INFORMATION W(1) 25Q 128B V W = 25Q x I(1) Winbond = SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I/O 128B = 128M-bit V = 2.7V to 3.6V F B = 16-pin SOIC 300-mil = 5x5-1 ball TFBGA 8x6-mm I = E = 8-pad WSON 8x6-mm C = 6x4 ball TFBGA 8x6-mm Industrial (-40C to +85C) (2) G P = Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3) = Green Package with Status Register Power Lock-Down & OTP enabled Notes: 1. The "W" prefix and the Temperature designator "I" are not included on the part marking. 2. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T) or Tray (shape S), when placing orders. 3 .For shipments with OTP feature enabled, please specify when placing orders. - 71 - Publication Release Date: October 03, 2013 Revision H W25Q128BV 10.1 Valid Part Numbers and Top Side Marking The following table provides the valid part numbers for the W25Q128BV SpiFlash Memory. Please contact Winbond for specific availability by density and package type. Winbond SpiFlash memories use a 12-digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages use an abbreviated 10-digit number. Part Numbers for Industrial Grade Temperature: PACKAGE TYPE DENSITY PRODUCT NUMBER TOP SIDE MARKING F SOIC-16 300mil 128M-bit W25Q128BVFIG W25Q128BVFIP 25Q128BVFG 25Q128BVFP E WSON-8 8x6mm 128M-bit W25Q128BVEIG W25Q128BVEIP 25Q128BVEG 25Q128BVEP B(1) TFBGA-24 8x6mm 5x5-1 ball array 128M-bit W25Q128BVBIG W25Q128BVBIP 25Q128BVBG 25Q128BVBP C(1) TFBGA-24 8x6mm 6x4 ball array 128M-bit W25Q128BVCIG W25Q128BVCIP 25Q128BVCG 25Q128BVCP Note: These Package types are Special Order only, please contact Winbond for more information. - 72 - W25Q128BV 11. REVISION HISTORY VERSION DATE PAGE A 03/26/09 All B 05/22/09 45, 67 & 68 Modified tSUS description Updated Ordering Information C 08/20/09 65 & 66 5, 58 & 62 53 Updated package diagrams Updated maximum operation frequency Corrected UID Waveform 07/08/10 68-69 5, 61, 65 50, 54 63 5, 9, 20, 55-57 5, 70 Updated package diagrams Updated maximum operation frequency Corrected 90h & 9Fh waveforms Updated Icc parameters Added SFDP feature Added automotive temperature D E 04/01/11 8, 71-73, 22-68, 46, 56-58 F 07/11/11 56, 57 66 G 04/18/12 56 8, 69 60, 71-72 H 03/10/13 5 60-65 DESCRIPTION New Create Preliminary Added TFBGA package Updated diagrams Added /WP timing diagram Updated Suspend description Update SFDP to JEDEC 1.0 Removed Preliminary designator Updated SFDP spec title to JESD216 Updated tCLH/tCLL Referred to SFDP definition application note Added TFBGA 5x5 Ball Array package Updated operating temperature grades Added TFBGA package Modified DC/AC Electrical Characteristics - 73 - Publication Release Date: October 03, 2013 Revision H W25Q128BV Trademarks Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Information in this document is provided solely in connection with Winbond products. Winbond reserves the right to make changes, corrections, modifications or improvements to this document and the products and services described herein at any time, without notice. - 74 -