74LVX4245MTCX - FAIRCHILD SEMICONDUCTOR

January 1993

Revised September 2003

74LVX4245 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

74LVX4245

8-Bit Dual Supply Translating Transceiver

with 3-STATE Outputs

General Description

The LVX4245 is a du al-supp ly, 8-bit tr ansl ating transcei ver

that is designed to interface between a 5V bus and a 3V

bus in a mixed 3V/5V supply environment. The Transmit/

Receive (T/R) input determines the direction of data flow.

Transmit (active-HIGH) enables data from A Ports to B

Ports; R eceive (ac tive-LOW ) enable s data fro m B Ports to

A Ports. The Output Enable input, when HIGH, disables

both A and B Ports by placing them in a high impedance

condition. The A Port interfaces with the 5V bus; the B Port

interfaces with the 3V bus.

The LVX4245 is suitable for mixed voltage applications

such as laptop computers using 3.3V CPU’s and 5V LCD

displays.

Features

■Bidirectional interface between 5V and 3V buses

■Control inputs compatible with TTL level

■5V data flow at A Port and 3V data flow at B Port

■Outputs source/sink 24 mA at 5V bus; 12 mA at 3V bus

■Guaranteed simultaneous switching noise level and

dynamic thresh ol d per for man ce

■Implements patented EMI reduction circuitry

■Functionally compatible with the 74 series 245

Ordering Code:

Devices also available in Tape and R eel. Speci fy by append ing the suffix let t er “X” to the ordering code.

Logic Symbol

Connection Diagram

Pin Descriptions

Truth Table

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Order Number Package Number Package Description

74LVX4245WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74LVX4245QSC MQA24 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide

74LVX4245MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Nam es Descri ption

OE Output Enable Input

T/R Transmit/Receive Input

A0–A7Side A Inputs or 3-STATE Outputs

B0–B7Side B Inputs or 3-STATE Outputs

Inputs Outputs

OE T/R

L L Bus B Data to Bus A

L H Bus A Data to Bus B

H X HIGH-Z State

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74LVX4245

Logic Diagram

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74LVX4245

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions (Note 2)

Note 1: The “Absolute Maximum Ratings” are those val ues beyond w hich

the saf ety of the device cannot be guarante ed. The device s hould not be

operated at these limits. The parametric values defined in the Electrical

Char ac teristi c s tables are not guar anteed at t he ab s olute maxi m um ratings.

The “R ecomm ended Ope rating Co ndition s” table will define the condit ions

for actu al device operation.

Note 2: Unused inputs must he held HIGH or LOW. They may not float.

DC Electrical Characteristics

Supply Voltage (VCCA, VCCB)−0.5V to +7.0V

DC Input Voltage (VI) @ OE, T/R −0.5V to VCCA + 0.5V

DC Input/Output Voltage (VI/O)

@ An−0.5V to VCCA + 0.5V

@Bn−0.5V to VCCB + 0.5V

DC Input Diode Current (IIN)

@ OE, T/R ±20 mA

DC Output Diode Current (IOK)±50 mA

DC O utput Source or Sink Current

(IO)±50 mA

DC VCC or Ground Current

per Output Pin (ICC or IGND)±50 mA

and Max Current @ ICCA ±200 mA

@ ICCB ±100 mA

Storage Temperature Range

(TSTG)−65°C to +150°C

DC Latch-Up Source or

Sink Current ±300 mA

Supply Voltage

VCCA 4.5V to 5.5V

VCCB 2.7V to 3.6V

Input Voltage (VI) @ OE, T/R 0V to VCCA

Input/Output Voltage (VI/O)

@ An0V to VCCA

@ Bn0V to VCCB

Free Air Operating Temperature (TA)−40°C to +85°C

Minimum Input Edge Rate (∆t/∆V) 8 ns/V

VIN from 30% to 70% of VCC

VCC @ 3.0V, 4.5V, 5.5V

Symbol Parameter VCCA VCCB TA +25°CT

A = −40°C to +85°CUnits Conditions

(V) (V) Typ Guaranteed Limits

VIHA Minimum An, T/R, 5.5 3.3 2.0 2.0

VOUT ≤ 0.1V or

HIGH Level OE 4.5 3.3 2.0 2.0 ≥ VCC − 0.1V

VIHB Input Voltage Bn5.0 3.6 2.0 2.0

5.0 2.7 2.0 2.0

VILA Maximum An, T/R, 5.5 3.3 0.8 0.8

VOUT ≤ 0.1V or

LOW Level OE 4.5 3.3 0.8 0.8 ≥ VCC −0.1V

VILB Input Voltage Bn5.0 2.7 0.8 0.8

5.0 3.6 0.8 0.8

VOHA Minimum HIGH Level 4.5 3.0 4.5 4.4 4.4 VIOUT = −100 µA

Output Voltage 4.5 3.0 4.25 3.86 3.76 IOH = −24 mA

VOHB 4.5 3.0 2.99 2.9 2.9 VIOUT = −100 µA

4.5 3.0 2.8 2.4 2.4 IOH = −12 mA

4.5 2.7 2.5 2.4 2.4 IOL = −8 mA

VOLA Maximum LOW Level 4.5 3.0 0.002 0.1 0.1 V IOUT =100 µA

Output Voltage 4.5 3.0 0.18 0.36 0.44 IOL = 24 mA

VOLB 4.5 3.0 0.002 0.1 0.1 IOUT = 100 µA

4.5 3.0 0.1 0.31 0.4 V IOL = 12 mA

4.5 2.7 0.1 0.31 0.4 IOL = 8 mA

IIN Maximum Input VI = VCCA, GND

Leakage Current 5.5 3.6 ±0.1 ±1.0 µA

@ OE, T/R

IOZA Maximum 3-STATE VI = VIL, VIH

Output Leakage 5.5 3.6 ±0.5 ±5.0 µAOE = VCCA

@ AnVO = VCCA, GND

IOZB Maximum 3-STATE VI = VIL, VIH

Output Leakage 5.5 3.6 ±0.5 ±5.0 µAOE = VCCA

@ BnVO = VCCB, GND

∆ICC Maximum ICCT/Input 5.5 3.6 1.0 1.35 1.5 mA VI = VCCA − 2.1V

@ An, T/R, OE

Input @ Bn5.5 3.6 0.35 0.5 mA VI = VCCB − 0.6V

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74LVX4245

DC Electrical Characteristics (Continued)

Note 3: Maximum test du ration 2.0 m s, one output loaded a t a t im e.

Note 4: Worst case package.

Note 5: Max num ber of outputs defined as (n). D at a inputs ar e driven 0V t o VCC level; one output at GN D .

Note 6: Max num ber of Dat a In puts (n) sw it c hing. (n−1) inputs switching 0V to VCC level. I nput-under-test s w it c hing:

VCC level to threshold (VIHD), OV to threshold (VILD), f = 1 MHz .

AC Electrical Characteristics

Note 7: Voltage Range 5.0V is 5.0V ± 0. 5V.

Note 8: Voltage Range 3.3V is 3.3V ± 0. 3V.

Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specif ic ation applies to any out pu ts switching in the same directio n, eit her HIGH-t o-LOW (tOSHL) or LOW-to-HI GH (t OSLH). Parameter guaranteed by design.

Symbol Parameter VCCA VCCB TA +25°CT

A = −40°C to +85°CUnits Conditions

(V) (V) Typ Guaranteed Limits

ICCA Quiescent VCCA An = VCCA or GND

Supply Current 5.5 3.6 8 80 µAB

n = VCCB or GND,

OE = GND T/R = GND

ICCB Quiescent VCCB An = VCCA or GND

Supply Current 5.5 3.6 5 50 µAB

n = VCCB or GND,

OE = GND T/R = VCCA

VOLPA Quiet Output Maximum 5.0 3.3 1.5 V(Note 4)(Note 5)

VOLPB Dynamic VOL 5.0 3.3 0.8

VOLVA Qu iet Output Minimum 5.0 3.3 −1.2 V(Note 4)(Note 5)

VOLVB Dynamic VOL 5.0 3.3 −0.8

VIHDA Minimum HIGH Level 5.0 3.3 2.0 V(Note 4)(Note 6)

VIHDB Dynamic Input Voltage 5.0 3.3 2.0

VILDA Maximum LOW Level 5.0 3.3 0.8 V(Note 4)(Note 6)

VILDB Dynamic Input Voltage 5.0 3.3 0.8

Symbol Parameters

TA = +25°CT

A = −40°C to +85°CT

A = −40°C to +85°C

Units

CL = 50 pF CL = 50 pF CL = 50 pF

VCCA = 5V (Note 7) VCCA = 5V (Note 7) VCCA = 5V (Note 7)

VCCB = 3.3V (Note 8) VCCB = 3.3V (Note 8) VCCB = 2.7V

Min Typ Max Min Max Min Max

tPHL Propagation Delay 1.0 5.1 8.5 1.0 9.0 1.0 10 .0 ns

tPLH A to B 1.0 5.3 8.5 1.0 9.0 1.0 10.0

tPHL Propagation Delay 1.0 5.4 8.5 1.0 9.0 1.0 10 .0 ns

tPLH B to A 1.0 5.5 8.5 1.0 9.0 1.0 10.0

tPZL Output Enable Time 1.0 6.5 10.0 1.0 10.5 1.0 11.5 ns

tPZH OE to B 1.0 6.7 10.0 1.0 10.5 1.0 11.5

tPZL Output Enable Time 1.0 5.2 9.0 1.0 9.5 1.0 10.0 ns

tPZH OE to A 1.0 5.8 9.0 1.0 9.5 1.0 10.0

tPHZ Output Disable Time 1.0 6.0 9.5 1.0 10.0 1.0 10.0 ns

tPLZ OE to B 1.0 3.3 6.5 1.0 7.0 1.0 7.5

tPHZ Output Disable Time 1.0 3.9 7.0 1.0 7.5 1.0 7.5 ns

tPLZ OE to A 1.0 2.9 6.5 1.0 7.0 1.0 7.5

tOSHL Output to Output

tOSLH Skew (Note 9) 1.0 1.5 1.5 1.5 ns

Data to Output

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74LVX4245

Capacitance

Note 10: CPD is meas ured at 10 M H z

8-Bit Dual Supply Translating Transceiver

The LVX4245 is a dual supply device capable of bidirec-

tional signal translation. This level shifting ability provides

an efficient interface between low voltage CPU local bus

with memo ry and a standar d bus defined by 5V I/O levels.

The device control inputs can be controlled by either the

low vol tage CPU an d core logi c or a bus arbitra tor w ith 5V

I/O levels.

Manufactured on a sub-micron CMOS process, the

LVX4245 is ideal for mixed voltage applications such as

notebook computers using 3.3V CPU’s and 5V peripheral

devices.

Power Up Considerations

To insure the system does not experience unnecessary ICC

current draw, bus contention, or oscillations during power

up, the f ollowing guidel ines should be a dhered to (re fer to

Table 1):

•Power up the control side of t he device first. This is the

VCCA.

•OE should ramp with or ahead of VCCA. This will help

guar d against bus contention.

•The Transmit/Receive control pin (T/R) should ramp with

or ahead of VCCA, this will ensure that the A Port data

pins are configured as inputs. With VCCA receiving

power first, the A I/O Port should be configured as inputs

to help guard against bus contention and oscillations.

•A side data inp uts sh ould be dr iven to a val id logic l eve l.

This will prevent excessive current draw.

The above steps will ensure that no bus contention or oscil-

lations, and therefore no excessive current draw occurs

during the power up cycli ng of these devices. These steps

will help prevent possible damage t o the t ranslator device s

and potential damage to other system components.

TABLE 1. Low Voltage Translator Power Up Sequencing Table

Please reference Application Note AN-5001 for more detailed information on using Fairchild’s LVX Low V o ltage Dual

Supply CMOS Translating Transceivers.

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 4.5 pF VCC = Open

CI/O Input/Output 15 pF VCCA = 5.0V

Capacitance VCCB = 3.3V

CPD Power Dissipation B→A55 pF V

CCA = 5.0V

Capacitance (Note 10) A→B40 pF V

CCB = 3.3V

Device Type VCCA VCCB T/R OE A Side

I/O B Side

I/O Floatable Pin

Allowed

74LVX4245 5V 3V ramp ramp logic outputs No

(power up 1st) (power up 2nd) with VCCA with VCCA 0V or VCCA

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74LVX4245

Applications: Mixed Mode Dual Supply Interface Solution

LVX4245 is designed to solve 3V/5V interfacing issues

when C MO S de vi ces c ann ot toler ate I/O l eve ls ab ove the ir

applied VCC. If an I/O pin of 3V ICs is driven by 5V ICs, the

P-Channel transistor in 3V ICs will conduct causing current

flow from I/O bus to the 3V power supply. The resulting

high current flow ca n cause destr uction of 3V ICs through

latchup effects. To prevent this problem, a current limiting

resist or is used typi cally under d irect connect ion of 3V ICs

and 5V ICs, but it causes speed degradation.

In a better solution, the LVX4245 configures two different

output levels to handle the dual supply interface issues.

The “A” port is a dedicated 5V port to interface 5V ICs. The

“B” port is a dedicated port to interface 3V ICs. Figure 2

shows how LVX4245 fits into a system with 3V subsystem

and 5V subsystem.

This de vice is also co nfigured as a n 8-bit 245 t ransceiver,

giving the designer 3-STATE capabilities and the ability to

select either bidirectional or unidirectional modes. Since

the center 20 pins are also pin compatible to 74 series 245,

as shown in Figu re 1, the designe r co ul d u se th i s devic e i n

either a 3V system or a 5V system without any further work

to re-layout the board.

FIGURE 1. LVX4245 Pin Arrangement is Compatible to

20-Pin 74 Series 245

FIGURE 2. LVX4245 Fits into a System with 3V Subsystem and 5V Subsystem

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74LVX4245

Physical Dim ensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M24B

24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide

Package Number MQA24

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74LVX4245 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC24

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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