74LVX4245MTCX - National Semiconductor

TL/F/11540

74LVX4245 8-Bit Dual Supply Translating Transceiver with TRI-STATE Outputs

March 1996

74LVX4245

8-Bit Dual Supply Translating Transceiver

with TRI-STATEÉOutputs

General Description

The LVX4245 is a dual-supply, 8-bit translating transceiver

that is designed to interface between a 5V bus and a 3V bus

in a mixed 3V/5V supply environment. The Transmit/Re-

ceive (T/R) input determines the direction of data flow.

Transmit (active-HIGH) enables data from A ports to B

ports; Receive (active-LOW) enables data from B ports to A

ports. The Output Enable input, when HIGH, disables both A

and B ports by placing them in a HIGH Z condition. The A

port interfaces with the 5V bus; the B port interfaces with

the 3V bus.

The LVX4245 is suitable for mixed voltage applications such

as laptop computers using 3.3V CPU’s and 5V LCD dis-

plays.

Features

YBidirectional interface between 5V and 3V buses

YControl inputs compatible with TTL level

Y5V data flow at A port and 3V data flow at B port

YOutputs source/sink 24 mA at 5V bus; 12 mA at 3V

bus

YGuaranteed simultaneous switching noise level and dy-

namic threshold performance

YAvailable in SOIC, QSOP and TSSOP packages

YImplements patented Quiet SeriesTM EMI reduction

circuitry

YFunctionally compatible with the 74 series 245

Logic Symbol

TL/F/11540–1

Pin Names Description

OE Output Enable Input

T/R Transmit/Receive Input

A0–A7Side A Inputs or TRI-STATE Outputs

B0–B7Side B Inputs or TRI-STATE Outputs

Connection Diagram

Pin Assignment

for SOIC, QSOP and TSSOP

TL/F/11540–2

SOIC JEDEC QSOP TSSOP

Order Number 74LVX4245WM 74LVX4245QSC 74LVX4245MTC

74LVX4245WMX 74LVX4245QSCX 74LVX4245MTCX

See NS Package Number M24B MQA24 MTC24

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C1996 National Semiconductor Corporation RRD-B30M17/Printed in U. S. A. http://www.national.com

Truth Table

Inputs Outputs

OE T/R

L L Bus B Data to Bus A

L H Bus A Data to Bus B

H X HIGH-Z State

Logic Diagram

TL/F/11540–6

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Absolute Maximum Ratings (Note)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage (VCCA,V

CCB)b0.5V to a7.0V

DC Input Voltage (VI)@OE, T/R b0.5V to VCCA a0.5V

DC Input/Output Voltage (VI/O)

@A(n) b0.5V to VCCA a0.5V

@B(n) b0.5V to VCCB a0.5V

DC Input Diode Current (IIN)@OE, T/R g20 mA

DC Output Diode Current (IOK)g50 mA

DC Output Source or Sink Current (IO)g50 mA

DC VCC or Ground Current

per Output Pin (ICC or IGND)g50 mA

and Max Current @ICCA g200 mA

@ICCB g100 mA

Storage Temperature Range (TSTG)b65§Ctoa

150§C

DC Latch-Up Source or Sink Current g300 mA

Note:

The ‘‘Absolute Maximum Ratings’’ are those values

beyond which the safety of the device cannot be guaran-

teed. The device should not be operated at these limits. The

parametric values defined in the ‘‘Electrical Characteristics’’

table are not guaranteed at the absolute maximum ratings.

The ‘‘Recommended Operating Conditions’’ table will define

the conditions for actual device operation

Recommended Operating

Conditions

Supply Voltage

VCCA 4.5V to 5.5V

VCCB 2.7V to 3.6V

Input Voltage (VI)@OE, T/R 0V to VCCA

Input/Output Voltage (VI/O)

@A(n) 0V to VCCA

@B(n) 0V to VCCB

Free Air Operating Temperature (TA)

74LVX b40§Ctoa

85§C

Minimum Input Edge Rate (Dt/DV) 8 ns/V

VIN from 30% to 70% of VCC

VCC @3.0V, 4.5V, 5.5V

DC Electrical Characteristics

Symbol Parameter VCCA

(V)

VCCB

(V)

74LVX4245 74LVX4245

Units Conditions

TAa25§CTAeb

40§C

to a85§C

Typ Guaranteed Limits

VIHA Minimum A(n), T/R, 5.5 3.3 2.0 2.0

VOUT s0.1V or

High Level OE 4.5 3.3 2.0 2.0 tVCC b0.1V

VIHB Input Voltage B(n) 5.0 3.6 2.0 2.0

5.0 2.7 2.0 2.0

VILA Maximum Low Level A(n), T/R, 5.5 3.3 0.8 0.8

VOUT s0.1V or

Input Voltage OE 4.5 3.3 0.8 0.8 tVCC b0.1V

VILB B(n) 5.0 2.7 0.8 0.8

5.0 3.6 0.8 0.8

VOHA Minimum High Level 4.5 3.0 4.5 4.4 4.4 VIOUT eb

100 mA

Output Voltage 4.5 3.0 4.25 3.86 3.76 IOH eb

24 mA

VOHB 4.5 3.0 2.99 2.9 2.9

IOUT eb

100 mA

4.5 3.0 2.8 2.4 2.4 IOH eb

12 mA

4.5 2.7 2.5 2.4 2.4 IOL eb

8mA

OLA Maximum Low Level 4.5 3.0 0.002 0.1 0.1 VIOUT e100 mA

Output Voltage 4.5 3.0 0.18 0.36 0.44 IOL e24 mA

VOLB 4.5 3.0 0.002 0.1 0.1 IOUT e100 mA

4.5 3.0 0.1 0.31 0.4 V IOL e12 mA

4.5 2.7 0.1 0.31 0.4 IOL e8mA

IN Maximum Input VIeVCCA, GND

Leakage Current 5.5 3.6 g0.1 g1.0 mA

@OE, T/R

IOZA Maximum TRI-STATE VIeVIL,V

Output Leakage 5.5 3.6 g0.5 g5.0 mAOE

CCA

@A(n) VOeVCCA, GND

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DC Electrical Characteristics (Continued)

Symbol Parameter VCCA

(V)

VCCB

(V)

74LVX4245 74LVX4245

Units Conditions

TAea

25§CTAeb

40§C

to a85§C

Typ Guaranteed Limits

IOZB Maximum TRI-STATE VIeVIL,V

Output Leakage 5.5 3.6 g0.5 g5.0 mAOE

CCA

@B(n) VOeVCCB, GND

DICC Maximum ICCT/Input 5.5 3.6 1.0 1.35 1.5 mA VIeVCCA b2.1V

@A(n), T/R,OE

Input @B(n) 5.5 3.6 0.35 0.5 mA VIeVCCB b0.6V

ICCA Quiescent VCCA A(n) eVCCA or GND

Supply Current 5.5 3.6 8 80 mA B(n) eVCCB or GND,

OE eGND T/R eGND

ICCB Quiescent VCCB A(n) eVCCA or GND

Supply Current 5.5 3.6 5 50 mA B(n) eVCCB or GND,

OE eGND T/R eVCCA

VOLPA Quiet Output Maximum 5.0 3.3 1.5 V(Notes 1, 2)

VOLPB Dynamic VOL 5.0 3.3 0.8

VOLVA Quiet Output Minimum 5.0 3.3 b1.2 V(Notes 1, 2)

VOLVB Dynamic VOL 5.0 3.3 b0.8

VIHDA Minimum High Level 5.0 3.3 2.0 V(Notes 1, 3)

VIHDB Dynamic Input Voltage 5.0 3.3 2.0

VILDA Maximum Low Level 5.0 3.3 0.8 V(Notes 1, 3)

VILDB Dynamic Input Voltage 5.0 3.3 0.8

²Maximum test duration 2.0 ms, one output loaded at a time.

Note 1: Worst case package.

Note 2: Max number of outputs defined as (n). Data inputs are driven 0V to VCC level; one output at GND.

Note 3: Max number of Data Inputs (n) switching. (nb1) inputs switching 0V to VCC level. Input-under-test switching: VCC level to threshold (VIHD), OV to threshold

(VILD), f e1 MHz.

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AC Electrical Characteristics

Symbol Parameters

74LVX4245 74LVX4245 74LVX4245

Units

TAea

25§CT

40§Ctoa

85§CT

40§Ctoa

85§C

CLe50 pF CLe50 pF CLe50 pF

*VCCA e5V *VCCA e5V *VCCA e5V

**VCCB e3.3V **VCCB e3.3V VCCB e2.7V

Min Typ Max Min Max Min Max

tPHL Propagation Delay 1.0 5.1 8.5 1.0 9.0 1.0 10.0 ns

tPLH A to B 1.0 5.3 8.5 1.0 9.0 1.0 10.0

tPHL Propagation Delay 1.0 5.4 8.5 1.0 9.0 1.0 10.0 ns

tPLH B to A 1.0 5.5 8.5 1.0 9.0 1.0 10.0

tPZL Output Enable Time 1.0 6.5 10.0 1.0 10.5 1.0 11.5 ns

tPZH OE to B 1.0 6.7 10.0 1.0 10.5 1.0 11.5

tPZL Output Enable Time 1.0 5.2 9.0 1.0 9.5 1.0 10.0 ns

tPZH OE to A 1.0 5.8 9.0 1.0 9.5 1.0 10.0

tPHZ Output Disable Time 1.0 6.0 9.5 1.0 10.0 1.0 10.0 ns

tPLZ OE to B 1.0 3.3 6.5 1.0 7.0 1.0 7.5

tPHZ Output Disable Time 1.0 3.9 7.0 1.0 7.5 1.0 7.5 ns

tPLZ OE to A 1.0 2.9 6.5 1.0 7.0 1.0 7.5

tOSHL Output to Output

tOSLH Skew*** 1.0 1.5 1.5 1.5 ns

Data to Output

*Voltage Range 5.0V is 5.0V g0.5V.

**Voltage Range 3.3V is 3.3V g0.3V.

***Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by

design.

Capacitance

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 4.5 pF VCC eOpen

CI/O Input/Output 15 pF VCCA e5.0V

Capacitance VCCB e3.3V

CPD Power Dissipation B

A55 pF V

CCA e5.0V

Capacitance A

B40 pF V

CCB e3.3V

CPD is measured at 10 MHz

8-Bit Dual Supply Translating Transceiver

The LVX4245 is a dual supply device capable of bidirection-

al signal translation. This level shifting ability provides an

efficient interface between low voltage CPU local bus with

memory and a standard bus defined by 5V I/O levels. The

device control inputs can be controlled by either the low

voltage CPU and core logic or a bus arbitrator with 5V I/O

levels.

Manufactured on a sub-micron CMOS process, the

LVX4245 is ideal for mixed voltage applications such as

notebook computers using 3.3V CPU’s and 5V peripheral

devices.

TL/F/11540–3

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Applications: Mixed Mode Dual Supply Interface Solution

LVX4245 is designed to solve 3V/5V interfacing issues

when CMOS devices cannot tolerate I/O levels above their

applied VCC. If an I/O pin of 3V ICs is driven by 5V ICs, the

P-Channel transistor in 3V ICs will conduct causing current

flow from I/O bus to the 3V power supply. The resulting high

current flow can cause destruction of 3V ICs through latch-

up effects. To prevent this problem, a current limiting resis-

tor is used typically under direct connection of 3V ICs and

5V ICs, but it causes speed degradation.

In a better solution, the LVX4245 configures two different

output levels to handle the dual supply interface issues. The

‘‘A’’ port is a dedicated 5V port to interface 5V ICs. The ‘‘B’’

port is a dedicated port to interface 3V ICs.

Figure 1

shows

how LVX4245 fits into a system with 3V subsystem and 5V

subsystem.

This device is also configured as an 8-bit 245 transceiver,

giving the designer TRI-STATE capabilities and the ability to

select either bidirectional or unidirectional modes. Since the

center 20 pins are also pin compatible to 74 series 245, as

shown in

Figure 2

, the designer could use this device in

either a 3V system or a 5V system without any further work

to re-layout the board.

TL/F/11540–4

FIGURE 2. LVX4245 Pin Arrangement is Compatible to

20-Pin 74 Series 245

TL/F/11540–5

FIGURE 1. LVX4245 Fits into a System with 3V Subsystem and 5V Subsystem

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74LVX4245 Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are

defined as follows:

74LVX 4245 MW X

Temperature Range Family Special Variations

74 eCommercial ‘‘X’’ eTape and Reel

‘‘ ’’ eRail/Tube

Device Type

Package Code

WM eSmall Outline JEDEC

SOIC (0.300×Wide)

QSC eMolded Shrink Small Outline Package, JEDEC

(also known as QSOP)

Physical Dimensions inches

millimeters

24-Lead (0.300×Wide) Small Outline Package (WM)

Order Number 74LVX4245WM or 74LVX4245WMX

NS Package Number M24B

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74LVX4245 8-Bit Dual Supply Translating Transceiver with TRI-STATE Outputs

Physical Dimensions inches (Continued)

24-Lead, Molded Shrink Small Outline Package, JEDEC (QSC)

(also known as: QSOP)

Order Number 74LVX4245QSC or 74LVX4245QSCX

NS Package Number MQA24

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