NE555NB - Philips Semiconductors / NXP Semiconductors

Philips Semiconductors Linear Products Product specification

NE/SA/SE555/SE555CTimer

346

August 31, 1994 853-0036 13721

DESCRIPTION

The 555 monolithic timing circuit is a highly stable controller capable

of producing accurate time delays, or oscillation. In the time delay

mode of operation, the time is precisely controlled by one external

resistor and capacitor. For a stable operation as an oscillator, the

free running frequency and the duty cycle are both accurately

controlled with two external resistors and one capacitor. The circuit

may be triggered and reset on falling waveforms, and the output

structure can source or sink up to 200mA.

FEATURES

•Turn-off time less than 2µs

•Max. operating frequency greater than 500kHz

•Timing from microseconds to hours

•Operates in both astable and monostable modes

•High output current

•Adjustable duty cycle

•TTL compatible

•Temperature stability of 0.005% per °C

APPLICATIONS

•Precision timing

•Pulse generation

•Sequential timing

•Time delay generation

•Pulse width modulation

PIN CONFIGURATIONS

4 5

7 8

GND

TRIGGER

OUTPUT

RESET

GND

TRIGGER

OUTPUT

RESET

DISCHARGE

THRESHOLD

CONTROL VOLTAGE

DISCHARGE

THRESHOLD

CONTROL VOLTAGE

VCC

D, N, FE Packages

TOP VIEW

F Package

ORDERING INFORMATION

DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG #

8-Pin Plastic Small Outline (SO) Package 0 to +70°C NE555D 0174C

8-Pin Plastic Dual In-Line Package (DIP) 0 to +70°C NE555N 0404B

8-Pin Plastic Dual In-Line Package (DIP) -40°C to +85°C SA555N 0404B

8-Pin Plastic Small Outline (SO) Package -40°C to +85°C SA555D 0174C

8-Pin Hermetic Ceramic Dual In-Line Package (CERDIP) -55°C to +125°C SE555CFE

8-Pin Plastic Dual In-Line Package (DIP) -55°C to +125°C SE555CN 0404B

14-Pin Plastic Dual In-Line Package (DIP) -55°C to +125°C SE555N 0405B

8-Pin Hermetic Cerdip -55°C to +125°C SE555FE

14-Pin Ceramic Dual In-Line Package (CERDIP) 0 to +70°C NE555F 0581B

14-Pin Ceramic Dual In-Line Package (CERDIP) -55°C to +125°C SE555F 0581B

14-Pin Ceramic Dual In-Line Package (CERDIP) -55°C to +125°C SE555CF 0581B

Philips Semiconductors Linear Products Product specification

NE/SA/SE555/SE555CTimer

August 31, 1994 347

BLOCK DIAGRAM

COMPARATOR

FLIP FLOP

OUTPUT

STAGE

THRESH-

OLD

VCC

3 1

CONTROL

VOLTAGE

TRIGGER

RESET

DIS-

CHARGE

OUTPUT GND

EQUIVALENT SCHEMATIC

NOTE: Pin numbers are for 8-Pin package

CONTROL VOLTAGE

VCC R1

4.7K R2

330 R3

4.7

R12

6.8K

Q21

Q7Q6

Q2 Q3

Q19 Q22

R13

3.9K

OUTPUT

Q23

82.

Q10

Q11 Q12

Q13

Q20

R11

4.7K

Q18

5K Q17

Q16

Q15

100K

R16

100

Q14

Q25

R15

4.7K

Q24

R14

220

THRESHOLD

TRIGGER

RESET

DISCHARGE

GND

Philips Semiconductors Linear Products Product specification

NE/SA/SE555/SE555CTimer

August 31, 1994 348

ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER RATING UNIT

Supply voltage

VCC SE555 +18 V

NE555, SE555C, SA555 +16 V

PDMaximum allowable power dissipation1600 mW

TAOperating ambient temperature range

NE555 0 to +70 °C

SA555 -40 to +85 °C

SE555, SE555C -55 to +125 °C

TSTG Storage temperature range -65 to +150 °C

TSOLD Lead soldering temperature (10sec max) +300 °C

NOTES:

1. The junction temperature must be kept below 125°C for the D package and below 150°C for the FE, N and F packages. At ambient tempera-

tures above 25°C, where this limit would be derated by the following factors:

D package 160°C/W

FE package 150°C/W

N package 100°C/W

F package 105°C/W

Philips Semiconductors Linear Products Product specification

NE/SA/SE555/SE555CTimer

August 31, 1994 349

DC AND AC ELECTRICAL CHARACTERISTICS

TA = 25°C, VCC = +5V to +15 unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

SE555 NE555/SE555C

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

Min Typ Max Min Typ Max

UNIT

VCC Supply voltage 4.5 18 4.5 16 V

ICC Supply current (low VCC=5V, RL=∞3 5 3 6 mA

state)1VCC=15V, RL=∞10 12 10 15 mA

Timing error (monostable) RA=2kΩ to 100kΩ

tMInitial accuracy2C=0.1µF 0.5 2.0 1.0 3.0 %

∆tM/∆T Drift with temperature 30 100 50 150 ppm/°C

∆tM/∆VSDrift with supply voltage 0.05 0.2 0.1 0.5 %/V

Timing error (astable) RA, RB=1kΩ to 100kΩ

tAInitial accuracy2C=0.1µF 4 6 5 13 %

∆tA/∆T Drift with temperature VCC=15V 500 500 ppm/°C

∆tA/∆VSDrift with supply voltage 0.15 0.6 0.3 1 %/V

VCControl voltage level VCC=15V 9.6 10.0 10.4 9.0 10.0 11.0 V

VCC=5V 2.9 3.33 3.8 2.6 3.33 4.0 V

VCC=15V 9.4 10.0 10.6 8.8 10.0 11.2 V

VTH Threshold voltage

VCC=5V 2.7 3.33 4.0 2.4 3.33 4.2 V

ITH Threshold current30.1 0.25 0.1 0.25 µA

VTRIG Trigger voltage VCC=15V 4.8 5.0 5.2 4.5 5.0 5.6 V

VCC=5V 1.45 1.67 1.9 1.1 1.67 2.2 V

ITRIG Trigger current VTRIG=0V 0.5 0.9 0.5 2.0 µA

VRESET Reset voltage4VCC=15V, VTH =10.5V 0.3 1.0 0.3 1.0 V

IRESET Reset current VRESET=0.4V 0.1 0.4 0.1 0.4 mA

Reset current VRESET=0V 0.4 1.0 0.4 1.5 mA

VCC=15V

ISINK=10mA 0.1 0.15 0.1 0.25 V

ISINK=50mA 0.4 0.5 0.4 0.75 V

VOL Output voltage (low) ISINK=100mA 2.0 2.2 2.0 2.5 V

ISINK=200mA 2.5 2.5 V

VCC=5V

ISINK=8mA 0.1 0.25 0.3 0.4 V

ISINK=5mA 0.05 0.2 0.25 0.35 V

VCC=15V

ISOURCE=200mA 12.5 12.5 V

VOH Output voltage (high) ISOURCE=100mA 13.0 13.3 12.75 13.3 V

VCC=5V

ISOURCE=100mA 3.0 3.3 2.75 3.3 V

tOFF Turn-off time5VRESET=VCC 0.5 2.0 0.5 2.0 µs

tRRise time of output 100 200 100 300 ns

tFFall time of output 100 200 100 300 ns

Discharge leakage current 20 100 20 100 nA

NOTES:

1. Supply current when output high typically 1mA less.

2. Tested at VCC=5V and VCC=15V.

3. This will determine the max value of RA+RB, for 15V operation, the max total R=10MΩ, and for 5V operation, the max. total R=3.4MΩ.

4. Specified with trigger input high.

5. Time measured from a positive going input pulse from 0 to 0.8×VCC into the threshold to the drop from high to low of the output. T rigger is

tied to threshold.

Philips Semiconductors Linear Products Product specification

NE/SA/SE555/SE555CTimer

August 31, 1994 350

TYPICAL PERFORMANCE CHARACTERISTICS

Minimum Pulse Width

Required for Triggering Supply Current

vs Supply Voltage

Low Output Voltage

vs Output Sink Current Low Output Voltage

vs Output Sink Current

Delay Time

vs Temperature

Delay Time

vs Supply Voltage Propagation Delay vs Voltage

Level of Trigger Pulse

High Output Voltage Drop

vs Output Source Current

MINIMUM PULSE WIDTH (ns)

LOWEST VOLTAGE LEVEL OF TRIGGER PULSE

150

125

100

0 0.1 0.2 0.3 0.4 (XVCC)

-55oC

0oC

+25oC

+70oC

+125oC

10.0

8.0

6.0

4.0

2.0

5.0 10.0 15.0

SUPPLY VOLTAGE – VOLTS

SUPPLY CURRENT – mA

1.015

1.010

1.005

1.000

0.995

0.990

0.985

-50 -25 0 +25 +50 +75 +100+125

NORMALIZED DELAY TIME

TEMPERATURE – oC

1.0

0.1

0.001

1.0 2.0 5.0 10 20 50 100

1.0

0.1

0.01

1.0 2.0 5.0 10 20 50 100

1.0

0.1

0.01

1.0 2.0 5.0 10 20 50 100

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

1.015

1.010

1.005

1.000

0.995

0.990

0.985

0 5 10 15 20 0 0.1 0.2 0.3 0.4

300

250

200

150

100

V – VOLTS

OUT

V – VOLTS

OUT

V – VOLTS

OUT

V – VOLTS

OUT

NORMALIZED DELAY TIME

PROPAGATION DELAY – ns

ISINK – mA ISINK – mA ISINK – mA

ISOURCE – mA SUPPLY VOLTAGE – V LOWEST VOLTAGE LEVEL

OF TRIGGER PULSE – XVCC

+125oC

+25oC

-55oC

VCC = 5V VCC = 10V VCC = 15V

-55oC

+25oC

-55oC

+25oC

-55oC

55oC

+25oC

–55oC

+25oC

+125oC

5V ≤ VCC ≤ 15V

-55oC

0oC

+25oC

+70oC

+25oC

Philips Semiconductors Linear Products Product specification

NE/SA/SE555/SE555CTimer

August 31, 1994 351

TYPICAL APPLICATIONS

OUTPUT

FLIP

FLOP

COMP

f1.49

(RA2RB)C

555 OR 1/2 556

DISCHARGE

CONTROL

VOLTAGE

THRESHOLD

TRIGGER

RESET

OUTPUT

.01µF

VCC

OUTPUT

FLIP

FLOP

COMP

555 OR 1/2 556

DISCHARGE

CONTROL

VOLTAGE

THRESHOLD

TRIGGER

RESET

OUTPUT

.01µF

VCC

∆T = 1.1RC

1

3VCC

| ∆t |

Astable Operation

Monostable Operation

Philips Semiconductors Linear Products Product specification

NE/SA/SE555/SE555CTimer

August 31, 1994 352

TYPICAL APPLICATIONS

DURATION OF

TRIGGER PULSE AS

SEEN BY THE TIMER

VCC VCC

10k

2 555

.001µF

NOTE: All resistor values are in Ω

Figure 1. AC Coupling of the Trigger Pulse

SWITCH GROUNDED

AT THIS POINT

OVOLTS

1/3 VCC

VCC

Trigger Pulse Width Requirements and Time

Delays

Due to the nature of the trigger circuitry, the timer will trigger on the

negative going edge of the input pulse. For the device to time out

properly, it is necessary that the trigger voltage level be returned to

some voltage greater than one third of the supply before the time out

period. This can be achieved by making either the trigger pulse

sufficiently short or by AC coupling into the trigger. By AC coupling

the trigger, see Figure 1, a short negative going pulse is achieved

when the trigger signal goes to ground. AC coupling is most

frequently used in conjunction with a switch or a signal that goes to

ground which initiates the timing cycle. Should the trigger be held

low, without AC coupling, for a longer duration than the timing cycle

the output will remain in a high state for the duration of the low

trigger signal, without regard to the threshold comparator state. This

is due to the predominance of Q15 on the base of Q16, controlling

the state of the bi-stable flip-flop. When the trigger signal then

returns to a high level, the output will fall immediately. Thus, the

output signal will follow the trigger signal in this case.

Another consideration is the “turn-off time”. This is the measurement

of the amount of time required after the threshold reaches 2/3 VCC

to turn the output low. To explain further, Q1 at the threshold input

turns on after reaching 2/3 VCC, which then turns on Q5, which turns

on Q6. Current from Q6 turns on Q16 which turns Q17 off. This

allows current from Q19 to turn on Q20 and Q24 to given an output

low. These steps cause the 2µs max. delay as stated in the data

sheet.

Also, a delay comparable to the turn-off time is the trigger release

time. When the trigger is low, Q10 is on and turns on Q11 which turns

on Q15. Q15 turns off Q16 and allows Q17 to turn on. This turns off

current to Q20 and Q24, which results in output high. When the

trigger is released, Q10 and Q11 shut off, Q15 turns off, Q16 turns on

and the circuit then follows the same path and time delay explained

as “turn off time”. This trigger release time is very important in

designing the trigger pulse width so as not to interfere with the

output signal as explained previously.