MB81ES171625-15WFKT - Fujitsu Limited

DS05-11407-3Ea

FUJITSU MICROELECTRONICS

DATA SHEET

2003.6

MEMORY

CMOS

2 × 512 K × 16 BIT / 2 × 256 K × 32 BIT

SINGLE DATA RATE I/F FCRAMTM

Consumer/Embedded Application Specific Memory for SiP

MB81ES171625/173225-12/-15

■DESCRIPTION

The Fujitsu Microelectronics MB81ES171625/173225 is a Fast Cycle Random Access Memory (FCRAM*) con-

taining 16,777,216 bit memory cells accessible in a 2×512K×16 bit / 2×256K×32 bit format. The MB81ES171625/

173225 features a fully synchronous operation referenced to a positive edge clock same as that of SDRAM

operation, whereby all operations are synchronized at a clock input which enables high performance and simple

user interface coexistence.

The MB81ES171625/173225 is utilized using a Fujitsu Microelectronics advanced FCRAM core technology and

designed for low power consumption and low voltage operation than regular synchronous DRAM (SDRAM).

The MB81ES171625/173225 is dedicated for SiP (System in a Package), and ideally suited for various embedded/

consumer applications including digital AVs, and image processing where a large band width and low power

consumption memory is needed.

* : FCRAM is a trademark of Fujitsu Microelectronics Limited, Japan.

■PRODUCT LINEUP

Parameter MB81ES171625/173225

-12 -15

Clock Frequency (Max) 85 MHz 66.7 MHz

Burst Mode Cycle Time (Min) CL = 1 23.4 ns 30 ns

CL = 2 11.7 ns 15 ns

Access Time From Clock (Max) CL = 1 21.9 ns 27 ns

CL = 2 10.2 ns 12 ns

XRAS Cycle Time (Min) 75 ns 75 ns

Operating Current (Max) (IDD1) 30 mA 30 mA

Power Down Mode Current (Max) (IDD2P) 1 mA 1 mA

Self-refresh Current (Max) (IDD6) 5 mA 5 mA

MB81ES171625/173225-12/-15

■ FEATURES

• FCRAM core with Single Data Rate SDRAM interface

•512 K word × 16 bit × 2 bank or 256 K word × 32 bit × 2 bank organization

• Single +1.8 V Supply ±0.15 V tolerance

• CMOS I/O interface

• Programmable burst type, burst length, and CAS latency

Burst type : Sequential Mode, Interleave Mode

Burst length : 1, 2, 4, 8, full column (64 : ×16 bit, 32 : ×32 bit)

CAS latency

MB81ES171625/173225-12

CL = 1 (Min tCK = 23.4 ns, Max 42.7 MHz)

CL = 2 (Min tCK = 11.7 ns, Max 85 MHz)

• 2 K refresh cycles every 16 ms

• Auto- and Self-refresh

• CKE power down mode

• Output Enable and Input Data Mask

• Burst Stop command at full column burst

• Burst read/write

• 85 MHz/66.7 MHz Clock frequency

MB81ES171625/173225-12/-15

■PAD LAYOUT

(Continued)

PA D

DSE

BME

TBST

DQC

⎯

VSS

VDD

VSS

VDD

DQ8

DQ9

DQ10

DQ11

VDDQ

VSSQ

DQ12

DQ13

DQ14

DQ15

⎯

DQM1

A12

A11

A10 (AP)

CLK

CKE

VSSQ

S16

VDDQ

XCS

XRAS

XCAS

XWE

DQM0

⎯

DQ7

DQ6

DQ5

DQ4

VSSQ

VDDQ

DQ3

DQ2

DQ1

DQ0

VDD

VSS

VDD

VSS

⎯

PAD No.84

PAD No.1

MB81ES171625

MB81ES171625/173225-12/-15

(Continued)

PA D

DSE

BME

TBST

DQC

DQ16

DQ17

DQ18

DQ19

VDDQ

VSSQ

DQ20

DQ21

DQ22

DQ23

VSS

VDD

VSS

VDD

DQ24

DQ25

DQ26

DQ27

VDDQ

VSSQ

DQ28

DQ29

DQ30

DQ31

DQM2

DQM3

A12

A11

A10(AP)

CLK

CKE

VSSQ

S32

VDDQ

XCS

XRAS

XCAS

XWE

DQM1

DQM0

DQ15

DQ14

DQ13

DQ12

VSSQ

VDDQ

DQ11

DQ10

DQ9

DQ8

VDD

VSS

VDD

VSS

DQ7

DQ6

DQ5

DQ4

VSSQ

VDDQ

DQ3

DQ2

DQ1

DQ0

⎯

PAD No.84

PAD No.1

MB81ES173225

MB81ES171625/173225-12/-15

■PAD DESCRIPTIONS

• MB81ES171625

• MB81ES173225

Symbol Function

VDD, VDDQ Supply Voltage

VSS, VSSQ Ground

DQ15 to DQ0Data I/O

DQM1 to DQM0DQ MASK

XWE Write Enable

XCAS Column Address Strobe

XRAS Row Address Strobe

XCS Chip Select

BA Bank Select

AP Auto Precharge Enable

A12A0Address Input • Row : A12 to A0 • Column : A5 to A0

CKE Clock Enable

CLK Clock Input

TBST BIST Control

BME Burn In Enable

DSE Disable

DQC BIST Output

S16 × 16 Select

Symbol Function

VDD, VDDQ Supply Voltage

VSS, VSSQ Ground

DQ31 to DQ0Data I/O

DQM3 to DQM0DQ MASK

XWE Write Enable

XCAS Column Address Strobe

XRAS Row Address Strobe

XCS Chip Select

BA Bank Select

AP Auto Precharge Enable

A12 to A0Address Input • Row : A12 to A0 • Column : A4 to A0

CKE Clock Enable

CLK Clock Input

TBST BIST Control

BME Burn In Enable

DSE Disable

DQC BIST Output

S32 × 32 Select

MB81ES171625/173225-12/-15

■BLOCK DIAGRAM

(Continued)

S16

CLK

BME

XCS

XRAS

XCAS

XRAS

XCAS

XWE

DQM1 to DQM0

DQ15 to DQ0

A12 to A0,

A10/AP

I/O

VCC

VSS/VSSQ

VCCQ

CKE

XWE

DSE

TBST

DQC

BANK-1

COMMAND

DECODER

CLOCK

BUFFER

ADDRESS

BUFFER/

BANK

SELECT

I/O DATA

BUFFER/

MODE

FCRAM

CORE

(8,192 × 64 × 16)

COL.

ADDR.

BANK-0

ROW

ADDR.

To each block

CONTROL

SIGNAL

LATCH

MB81ES171625

BIST

COLUMN

ADDRESS

COUNTER

MB81ES171625/173225-12/-15

(Continued)

S32

CLK

BME

XCS

XRAS

XCAS

XRAS

XCAS

XWE

DQM3 to DQM0

DQ31 to DQ0

A12 to A0,

A10/AP

I/O

VCC

VSS/VSSQ

VCCQ

CKE

XWE

DSE

TBST

DQC

BANK-1

COMMAND

DECODER

CLOCK

BUFFER

ADDRESS

BUFFER/

BANK

SELECT

I/O DATA

BUFFER/

MODE

FCRAM

CORE

(8,192 × 32 × 32)

COL.

ADDR.

BANK-0

ROW

ADDR.

To each block

CONTROL

SIGNAL

LATCH

MB81ES173225

BIST

COLUMN

ADDRESS

COUNTER

MB81ES171625/173225-12/-15

■FUNCTIONAL TRUTH TABLE

1. Command Truth Table

V = Valid, L = Logic Low, H = Logic High, X = either L or H.

n = State at current clock cycle, n−1 = state at 1 clock cycle before n.

*1: NOP and DESL commands have the same effect on the part. At DESL command (XCS = “H”) , all input signal

are ignored, but hold the internal state. NOP command (XCS = “L”, XRAS = XCAS = XWE = “H”) is no effect on

device operation and the internal state continue.

*2: BST command is effective on every Burst Length. (BL = 1, 2, 4, 8, full column)

*3: READ, READA, WRIT and WRITA commands should be issued only after the corresponding bank has been

activated (ACTV command) .

Refer to “■ STATE DIAGRAM (Simplified for Single BANK Operation State Diagram).”

*4 ACTV command should be issued only after the corresponding bank has been precharged (PRE or PALL

command) .

*5: Required after power up. Refer to “17. Power-Up Initialization” in “■ FUNCTIONAL DESCRIPTION.”

*6: MRS command should be issued only after all banks have been precharged (PRE or PALL command) and DQ

is in High-Z. Refer to “■ STATE DIAGRAM (Simplified for Single BANK Operation State Diagram).”

Notes: • All commands assumes no CSUS command on previous rising edge of clock.

• All commands are assumed to be valid state transitions.

• All inputs are latched on the rising edge of the clock.

• TBST,BME and DSE should be held Low.

• S16 should be held VIH, and S32 should be held VIL.

Function Com-

mand

CKE XCS XRAS XCAS XWE BA A 10

(AP)

A 12 to

A6A5A4 to

n-1 n

Device Deselect*1DESL H X H X X X X X X X X

No Operation*1NOP H X L H H H X X X X X

Burst Stop*2BST H X L H H L X X X X X

Read*3X16 READ HX L H L H V L X V V

X32 H X L H L H V L X X V

Read with Auto-pre-

charge*3

X16 READA HX L H L H V H X V V

X32 H X L H L H V H X X V

Write*3X16 WRIT HX L H L L V L X V V

X32 H X L H L L V L X X V

Write with Auto-pre-

charge*3

X16 WRITA HX L H L L V H X V V

X32 H X L H L L V H X X V

Bank Active*4ACTV H X L L H H V V V V V

Precharge Single Bank*5PRE H X L L H L V L X X X

Precharge All Banks*5PALL H X L L H L X H X X X

Mode Register Set*5, *6MRS H X L L L L L L V V V

MB81ES171625/173225-12/-15

2. DQM Truth Table

V = Valid, L = Logic Low, H = Logic High, X = either L or H.

n = State at current clock cycle, n−1 = state at 1 clock cycle before n.

Notes: • MB81ES171625; DQM0 and DQM1 controls DQ7 to DQ0 and DQ15 to DQ8, respectively.

• MB81ES173225; DQM0, DQM1, DQM2 and DQM3 controls DQ7 to DQ0, DQ15 to DQ8, DQ23 to DQ16, and

DQ31 to DQ24, respectively.

• TBST, BME and DSE should be held Low.

• S16 should be held VIH, and S32 should be held VIL.

• All commands assumes no CSUS command on previous rising edge of clock.

• All commands are assumed to be valid state transitions.

• All inputs are latched on the rising edge of the clock.

3. CKE Truth Table

V = Valid, L = Logic Low, H = Logic High, X = either L or H.

n = State at current clock cycle, n−1 = state at 1 clock cycle before n.

*1: CSUS command requires that at least one bank is active. Refer to “■ STATE DIAGRAM (Simplified for Single

BANK Operation State Diagram).”

*2: REF and SELF commands should be issued only after all banks have been precharged (PRE or PALL

command) . Refer to “■ STATE DIAGRAM (Simplified for Single BANK Operation State Diagram).”

*3: SELF and PD commands should be issued only after the last read data have been appeared on DQ.

*4: CKE should be held High during tREFC.

Notes: • TBST,BME and DSE should be held Low.

• S16 should be held VIH, and S32 should be held VIL.

• All commands assumes no CSUS command on previous rising edge of clock.

• All commands are assumed to be valid state transitions.

• All inputs are latched on the rising edge of the clock.

Function Command CKE DQM

n-1 n

Data Write/Output Enable ENBL H X L

Data Mask/Output Disable MASK H X H

Current State Function Com-

mand

CKE XCS XRAS XCAS XWE BA A10

(AP)

A12 to

n-1 n

Bank Active Clock Suspend Mode Entry *1CSUS H L X X X X X X X

Any (Except Idle) Clock Suspend Continue *1⎯LL X X X X X X X

Clock Suspend Clock Suspend Mode Exit ⎯LH X X X X X X X

Idle Auto-refresh Command *2REF H H L L L H X X X

Idle Self-refresh Entry *2, *3SELF H L L L L H X X X

Self Refresh Self-refresh Exit *4SELFX LH L H H H X X X

LH H X X X X X X

Idle Power Down Entry *3PD HL L H H H X X X

HL H X X X X X X

Power Down Power Down Exit ⎯LH L H H H X X X

LH H X X X X X X

MB81ES171625/173225-12/-15

4. Operation Command Table (Applicable to single bank)

(Continued)

Current

State XCS XRAS XCAS XWE Addr Command Function

Idle

H X X X X DESL NOP

LH HH X NOP

L H H L X BST NOP*1

L H L H BA, CA, AP READ/READA Illegal*2

L H L L BA, CA, AP WRIT/WRITA

L L H H BA, RA ACTV Bank Active after tRCD

L L H L BA, AP PRE NOP

L L H L AP PALL NOP*1

L L L H X REF/SELF Auto-refresh or Self-reresh*3, *5

LL LL MODE MRS Mode Register Set

(Idle after tRSC) *3, *6

Bank Active

H X X X X DESL

NOPLH HH X NOP

L H H L X BST

L H L H BA, CA, AP READ/READA Begin Read; Determine AP

L H L L BA, CA, AP WRIT/WRITA Begin Write; Determine AP

L L H H BA, RA ACTV Illegal*2

L L H L BA, AP PRE Precharge

L L H L AP PALL Precharge*1

L L L H X REF/SELF Illegal

LL LL MODE MRS

Read

H X X X X DESL NOP (Continue Burst to End →

Bank Active)

LH HH X NOP

L H H L X BST Burst Stop → Bank Active

L H L H BA, CA, AP READ/READA Terminate Burst, NewRead;

Determine AP

L H L L BA, CA, AP WRIT/WRITA Terminate Burst, Start Write;

Determine AP*4

L L H H BA, RA ACTV Illegal*2

L L H L BA, AP PRE Terminate Burst, Precharge →

Idle

L L H L AP PALL Terminate Burst, Precharge →

Idle*1

L L L H X REF/SELF Illegal

LL LL MODE MRS

MB81ES171625/173225-12/-15

(Continued)

Current

State XCS XRAS XCAS XWE Addr Command Function

Write

HX X X X DESL NOP (Continue Burst to End → Bank

Active)

LH H H X NOP

L H H L X BST Burst Stop → Bank Active

L H L H BA, CA, AP READ/READA Terminate Burst, Start Read;

Determine AP*4

L H L L BA, CA, AP WRIT/WRITA Terminate Burst, New Write;

Determine AP

L L H H BA, RA ACTV Illegal*2

L L H L BA, AP PRE Terminate Burst, Precharge → Idle

L L H L AP PALL Terminate Burst, Precharge → Idle*1

L L L H X REF/SELF Illegal

LL L L MODE MRS

Read with

Auto-

precharge

HX X X X DESL NOP (Continue Burst to End →

Precharge → Idle)

LH H H X NOP

L H H L X BST Illegal

L H L H BA, CA, AP READ/READA

Illegal*2

L H L L BA, CA, AP WRIT/WRITA

L L H H BA, RA ACTV

L L H L BA, AP PRE

L L H L AP PALL

IllegalL L L H X REF/SELF

LL L L MODE MRS

Write with

Auto-

precharge

HX X X X DESL NOP (Continue Burst to End →

Precharge → Idle)

LH H H X NOP

L H H L X BST Illegal

L H L H BA, CA, AP READ/READA

Illegal*2

L H L L BA, CA, AP WRIT/WRITA

L L H H BA, RA ACTV

L L H L BA, AP PRE

L L H L AP PALL

IllegalL L L H X REF/SELF

LL L L MODE MRS

MB81ES171625/173225-12/-15

(Continued)

Current

State XCS XRAS XCAS XWE Addr Command Function

Precharging

H X X X X DESL

NOP (Idle after tRP) LH H H X NOP

L H H L X BST

L H L H BA, CA, AP READ/READA

Illegal*2

L H L L BA, CA, AP WRIT/WRITA

L L H H BA, RA ACTV

L L H L BA, AP PRE NOP*7

L L H L AP PALL NOP*1

L L L H X REF/SELF Illegal

L L L L MODE MRS

Bank

Activating

H X X X X DESL NOP (Bank Active after tRCD)

LH H H X NOP

L H H L X BST NOP (Bank Active after tRCD) *1

L H L H BA, CA, AP READ/READA

Illegal*2

L H L L BA, CA, AP WRIT/WRITA

L L H H BA, RA ACTV

L L H L BA, AP PRE

L L H L AP PALL

IllegalL L L H X REF/SELF

L L L L MODE MRS

Refreshing

H X X X X DESL NOP (Idle after tREFC)

LH H H X NOP

L H H L X BST

Illegal

LH L X X READ/READA/

WRIT/WRITA

LL H X X ACTV/

PRE/PALL

LL L X X REF/SELF/

MRS

MB81ES171625/173225-12/-15

(Continued)

ABBREVIATIONS :

V = Valid, L = Logic Low, H = Logic High, X = either L or H.

n = State at current clock cycle, n−1 = state at 1 clock before n.

RA = Row Address BA = Bank Address

CA = Column Address AP = Auto Precharge

*1: Entry may affect other bank.

*2: Illegal to the bank in specified state; entry may be legal to the bank specified by BA, depending on the state of

that bank.

*3: Illegal if any bank is not idle.

*4: Must satisfy bus contention, bus turn around, and/or write recovery requirements.

Refer to “11. READ Interrupted by WRITE (Example @ CL = 2, BL = 4)” and “12. WRITE to READ Timing

(Example @ CL = 1, BL = 4)” in “■ TIMING DIAGRAMS.”

*5: SELF command should be issued only after the last read data has been appeared on DQ.

*6: MRS command should be issued only when all DQ are in High-Z.

*7: NOP in precharging or idle state. PRE may affect to the bank specified by BA and AP.

Notes: • TBST,BME and DSE should be held Low.

• S16 should be held VIH, and S32 should be held VIL.

• All entries in OPERATION COMMAND TABLE assume that the CKE was High during the proceeding clock

cycle and the current clock cycle.

• Illegal means that the device operation and/or data-integrity are not guaranteed. If used, power up sequence

will be asserted after power shut down.

• All commands assume no CSUS command on previous rising edge of clock.

• All commands are assumed to be valid state transitions.

• All inputs are latched on the rising edge of the clock.

Current

State XCS XRAS XCAS XWE Addr Command Function

Mode

Setting

HXXX X DESL NOP (Idle after tRSC)

LHHH X NOP

L H H L X BST

Illegal

LHLX XREAD/READA/

WRIT/WRITA

LLXX X

ACTV/PRE/

PALL/REF/SELF/

MRS

MB81ES171625/173225-12/-15

5. Command Truth Table for CKE

(Continued)

Current

State

CKE

(n-1)

CKE

(n) XCS XRAS XCAS XWE Addr Function

Self-

refresh

H X X X X X X Invalid

LHHX X X XExit Self-refresh

(Self-refresh Recovery → Idle after tREFC)

LHLH H H X

LHLH H L X

IllegalLHLH L X X

LHL L X X X

L L X X X X X Maintain Self-refresh

Self-

refresh

Recovery

L X X X X X X Invalid

HHH X X X XIdle after tREFC

HHL H H H X

HHL H H L X

IllegalHHL H L X X

HHL L X X X

H L X X X X X Illegal*1

Power

Down

H X X X X X X Invalid

LHHX X X XExit Power Down Mode → Idle

LHLH H H X

L L X X X X X NOP (Maintain Power Down Mode)

LHL L X X X

IllegalLHLH L X X

LHLH H L X

All

Banks

Idle

HHH X X X V

Refer to “Operation Command Table”.HHL H X X V

HHL L H X V

H H L L L H X Auto-refresh

H H L L L L V Refer to “Operation Command Table”.

HLHX X X XPower Down

HLLH H H X

HLLH H L X

IllegalHLLH L X X

HLL L H X X

H L L L L H X Self-refresh*2

H L L L L L X Illegal

L X X X X X X Invalid

MB81ES171625/173225-12/-15

(Continued)

V = Valid, L = Logic Low, H = Logic High, X = either L or H.

n = State at current clock cycle, n−1 = state at 1 clock cycle before n.

*1: CKE should be held High for tREFC period.

*2: SELF command should be issued only after the last data has been appeared on DQ.

Notes: • TBST,BME and DSE should be held Low.

• S16 should be held VIH, and S32 should be held VIL.

• All entries in “5. Command Truth Table for CKE” are specified at CKE (n) state and CKE input from

CKE (n−1) to CKE (n) state must satisfy the corresponding setup and hold time for CKE.

Current

State

CKE

(n-1)

CKE

(n) XCS XRAS XCAS XWE Addr Function

Bank Active

Bank

Activating

Read/Write

H H X X X X X Refer to “Operation Command Table”.

H L X X X X X Begin Clock Suspend next cycle

LXX X X X X Invalid

Clock

Suspend

HXX X X X X

L H X X X X X Exit Clock Suspend next cycle

L L X X X X X Maintain Clock Suspend

Any State

Other Than

Listed Above

L X X X X X X Invalid

H H X X X X X Refer to “Operation Command Table”.

H L X X X X X Illegal

MB81ES171625/173225-12/-15

■FUNCTIONAL DESCRIPTION

1. SDR I/F FCRAM Basic Function

Three major differences between SDR I/F FCRAMs and conventional DRAMs are : a synchronized operation,

a burst mode, and a mode register.

The synchronized operation is the fundamental difference. SDR I/F FCRAM uses a clock input for synchroni-

zation, while DRAM is basically asynchronous memory although it has been using two clocks, XRAS and XCAS.

Each operation of DRAM is determined by their timing phase differences while each operation of the SDR I/F

FCRAM is determined by commands and all operations are referenced to a rising edge of a clock.

The burst mode is a very high speed access mode utilizing an internal column address generator. Once a

column address for the first access is set, following addresses are automatically generated by the internal column

address counter.

The mode register is to configure SDR I/F FCRAM operation and function into desired system conditions.

“■ MODE REGISTER TABLE” shows how the SDR I/F FCRAM can be configured for system requirements by

mode register programming.

The program to the mode resister should be excuted after all banks are precharged.

2. FCRAMTM

MB81ES171625/173225 utilizes FCRAM core technology. The FCRAM is an acronym for Fast Cycle Random

Access Memory and provides very fast random cycle time, low latency and low power consumption than regular

DRAMs.

3. Clock (CLK) Input and Clock Enable (CKE)

All input and output signals of the SDR I/F FCRAM use register type buffers. CLK is used as a trigger for the

validated by a rising edge of CLK. CKE is a high active clock enable signal. CKE controls the internal clock

generator. CKE is latched by a rising edge of clock. CKE should become High level on the previous clock cycle

when a basic command is issued. When CKE = Low is latched at a clock input during active cycle, the next clock

will be internally masked. During idle state (all banks have been precharged) , the Power Down mode (standby)

is entered with CKE = Low and this will make extremely low standby current.

4. Chip Select (XCS)

XCS enables all command inputs, XRAS, XCAS, XWE and address inputs. When XCS is High, command signals

are negated but internal operations such as a burst cycle will not be suspended. If such a control isn’t needed,

XCS can be tied to ground level.

5. Command Input (XRAS, XCAS and XWE)

Unlike a conventional DRAM, XRAS, XCAS, and XWE do not directly imply SDR I/F FCRAM operations, such

as Row address strobe by XRAS. Instead, each combination of XRAS, XCAS, and XWE input in conjunction

with XCS input at the rising edge of the CLK determines SDR I/F FCRAM operations. Refer to “■ FUNCTIONAL

TRUTH TABLE.”

6. Address Input (A12 to A0)

Address input selects an arbitrary location of each memory cell matrix, 524,288 (×16 bit) or 262,144 (×32 bit) .

A total of 19( × 16 bit) or 18 ( × 32 bit) address input signals are required to decode 13 bit Row addresses and

6 bit (×16 bit) or 5 bit (×32 bit) Column addresses matrix. The SDR I/F FCRAM adopts an address multiplexer

in order to reduce the pin count of the address line. At a Bank Active command (ACTV) , 13 bit Row addresses

are initially latched and the remainder of 6 bit ( × 16 bit) or 5 bit ( × 32 bit) Column addresses are then latched

by a Column address strobe command of either a Read command (READ or READA) or a Write command

(WRIT or WRITA) . A10 selects READ or READA, WRIT or WRITA and PRE or PALL.

MB81ES171625/173225-12/-15

7. Bank Select (BA)

This SDR I/F FCRAM has two banks.

Bank selection by BA occurs at Bank Active command (ACTV) followed by read (READ or READA) , write (WRIT

or WRITA) , and precharge commands (PRE or PALL) .

8. Data Inputs and Ooutputs (DQ15 to DQ0/DQ31 to DQ0)

Input data is latched and written into the memory at the clock following the write command input. Data output is

obtained by the following conditions followed by a read command input :

tRAC; from the bank active command when tRCD (Min) is satisfied. (This parameter is reference only.)

tCAC; from the read command when tRCD is greater than tRCD (Min) at CL = 1.

tAC ; from the rising edge of the clock after tRAC and tCAC.

The polarity of the output data is identical to that of input data. Data is valid between access time (determined

by the three conditions above) and the next positive clock edge (tOH) .

Refer to “■ AC CHARACTERISTICS”.

9. Data I/O Mask (DQM1, DQM0/DQM3 to DQM0)

DQM is an active high enable input and has an output disable and input mask function. During burst cycle and

when DQM = High is latched by a clock, input is masked at the same clock and output will be masked at the CL

later while internal burst counter will increment by one or will go to the next stage depending on the burst type.

10. Burst Mode Operation

The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row

address and by automatically generating column address. Access time and cycle time of Burst mode is specified

as tCAC/tAC and tCK, respectively. The internal column address counter operation is determined by a mode register

which defines burst type and the burst count length of 1, 2, 4, 8 bits of boundary or full column. In order to

terminate or move from the current burst mode to the next stage while the remaining burst count is more than

1, the following combinations will be required :

(1) Burst Type

The burst type can be selected either sequential or interleave mode. The sequential mode is an incremental

decoding scheme within a boundary address to be determined by count length, it assigns +1 to the previous (or

initial) address until reaching the end of boundary address and then wraps around to the least significant address

( = 0) . The interleave mode is a scrambled decoding scheme for A0 through A2. If the first access of column

address is even (0) , the next address will be odd (1) , or vice-versa.

(2) Burst Mode Termination and Method of Next Stage Set

Current Stage Next Stage Method (Assert the following command)

Burst Read Burst Read Read Command

Burst Read Burst Write 1st Step Mask Command (Normally 3 clock cycles)

2nd Step Write Command after OWD

Burst Write Burst Write Write Command

Burst Write Burst Read Read Command

Burst Read Precharge Precharge Command

Burst Write Precharge Precharge Command

MB81ES171625/173225-12/-15

(3) Counter Operation of Sequential Mode and Interleave Mode

11. Full Column Burst and Burst Stop Command (BST)

The full column burst is an option of burst length and available only at sequential mode of burst type. This full

column burst mode is repeatedly access to the same row. If burst mode reaches the end of column address,

then it wraps around to the first column address ( = 0) and continues to count until interrupted by the new read

(READ) /write (WRIT) , precharge (PRE) , or burst stop (BST) commands. The selection of Auto-precharge

option is illegal during the full column burst operation.

BST command is applicable to terminate the burst operation. If BST command is asserted during the burst mode,

its operation is terminated immediately and the internal state moves to Bank Active.

When a read mode is interrupted by BST command, the output will be in High-Z.

For the detailed rule, please refer to “8. READ Interrupted by Burst Stop (Example @ BL = Full Column) ” in “■

TIMING DIAGRAMS.”

When a write mode is interrupted by BST command, the data to be applied at the same time with BST command

will be ignored.

12. Precharge and Precharge Option (PRE, PALL)

The SDR I/F FCRAM memory core is the same as a conventional DRAM’s, requiring precharge and refresh

operations. Precharge rewrites the bit line and reset the internal Row address line and is executed by the

Precharge command (PRE) . With the Precharge command, SDR I/F FCRAM will automatically be in standby

state after precharge time (tRP) .

The precharged bank is selected by combination of AP and BA when the Precharge command is asserted. If

AP = High, all banks are precharged regardless of BA (PALL) . If AP = Low, a bank to be selected by BA is

precharged (PRE) .

The auto-precharge enters precharge mode at the end of burst mode of read or write without the Precharge

command assertion.

This auto precharge is entered by AP = High when a read or write command is asserted. Refer to “■ FUNC-

TIONAL TRUTH TABLE.”

Burst

Length

Starting Column

Address Sequential Mode Interleave Mode

A2A1A0

2XX 0 0 − 10 − 1

XX1 1 − 01 − 0

X00 0 − 1 − 2 − 30 − 1 − 2 − 3

X01 1 − 2 − 3 − 01 − 0 − 3 − 2

X1 0 2 − 3 − 0 − 12 − 3 − 0 − 1

X11 3 − 0 − 1 − 23 − 2 − 1 − 0

000 0 − 1 − 2 − 3 − 4 − 5 − 6 − 70 − 1 − 2 − 3 − 4 − 5 − 6 − 7

001 1 − 2 − 3 − 4 − 5 − 6 − 7 − 01 − 0 − 3 − 2 − 5 − 4 − 7 − 6

010 2 − 3 − 4 − 5 − 6 − 7 − 0 − 12 − 3 − 0 − 1 − 6 − 7 − 4 − 5

011 3 − 4 − 5 − 6 − 7 − 0 − 1 − 23 − 2 − 1 − 0 − 7 − 6 − 5 − 4

100 4 − 5 − 6 − 7 − 0 − 1 − 2 − 34 − 5 − 6 − 7 − 0 − 1 − 2 − 3

101 5 − 6 − 7 − 0 − 1 − 2 − 3 − 45 − 4 − 7 − 6 − 1 − 0 − 3 − 2

110 6 − 7 − 0 − 1 − 2 − 3 − 4 − 56 − 7 − 4 − 5 − 2 − 3 − 0 − 1

111 7 − 0 − 1 − 2 − 3 − 4 − 5 − 67 − 6 − 5 − 4 − 3 − 2 − 1 − 0

MB81ES171625/173225-12/-15

13. Auto-Refresh (REF)

The Auto-refresh uses the internal refresh address counter. SDR I/F FCRAM Auto-refresh command (REF)

generates the Precharge command internally. All banks of SDR I/F FCRAM should be precharged prior to the

Auto-refresh command. The Auto-refresh command should also be asserted every 7.8 μs or a total 2048 refresh

commands within a 16 ms period.

14. Self-Refresh Entry (SELF)

The Self-refresh function provides automatic refresh by an internal timer as well as the Auto-refresh and will

continue the refresh function until cancelled by SELFX.

The Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF) . Once

SDR I/F FCRAM enters the self-refresh mode, all inputs except for CKE will be “don’t care” (either logic high or

low level state) and outputs will be in a High-Z state. During a self-refresh mode, CKE = Low should be maintained.

SELF command should be issued only after the last read data has been appeared on DQ.

Note : When the burst refresh method is used, a total of 2048 auto-refresh commands must be asserted within 1

ms prior to the self-refresh mode entry.

15. Self-Refresh Exit (SELFX)

To exit the Self-refresh mode, apply minimum tSI after CKE brought high, and then the No operation command

(NOP) or the Deselect command (DESL) should be asserted within one tREFC period. CKE should be held High

within one tREFC period after tSI. Refer to “16. Self-Refresh Entry and Exit Timing” in “■ TIMING DIAGRAMS” for

the detail.

It is recommended to assert an Auto-refresh command just after tREFC period to avoid the violation of refresh

period.

Note : When the burst refresh method is used, a total of 2048 auto-refresh commands must be asserted within 1

ms after the Self-refresh exit.

16. Mode Register Set (MRS)

The mode register of the SDR I/F FCRAM provides a variety of operations. The register consists of 3 operation

fields; Burst Length, Burst Type, and CAS latency. Refer to “■ MODE REGISTER TABLE.”

The mode register can be programmed by the Mode Register Set command (MRS) . Each field is set by the

address line. Once a mode register is programmed, the contents of the register will be held until re-programmed

by another MRS command (or part loses power) . MRS command should be issued only when DQ is in High-Z.

The condition of the mode register is undefined after the power-up stage. It is required to set each field after

initialization of the SDR I/F FCRAM. Refer to “17. Power-Up Initialization”.

17. Power-Up Initialization

SDR I/F FCRAM internal condition after power-up will be undefined. It is required to follow the following Power

On Sequence to execute read or write operation.

1. Apply the power and start the clock. Attempt to maintain either the NOP or DESL command at the input.

2. Maintain stable power, stable clock, and NOP condition for a minimum of 500 μs.

3. Precharge all banks by the Precharge (PRE) or Precharge All command (PALL) .

4. Assert minimum of 2 Auto-refresh commands (REF) .

5. Program the mode register by the Mode Register Set command (MRS) .

In addition, it is recommended that DQM and CKE track VDD to insure that output is High-Z state. The Mode

before 4.

MB81ES171625/173225-12/-15

■STATE DIAGRAM (Simplified for Single BANK Operation State Diagram)

MRS SELF

SELFX

REF

CKE

CKE\

(PD)

ACTV

CKE\ (CSUS)

CKE

BST BST

WRIT WRIT READ READ

CKE

WRITA

WRITA READA

CKE\ (CSUS) CKE\ (CSUS)

CKE\ (CSUS)

PRE or PALL

READA

WRIT

PRE

PALL

PRE

PALL

WRITA

READA

READ

MODE

SET

SELF

REFRESH

IDLE

READ

SUSPEND

BANK

ACTIVE

AUTO

REFRESH

POWER

DOWN

BANK

ACTIVE

SUSPEND

WRITE

SUSPEND

POWER

ON PRECHARGE

READ

WRITE WITH

AUTO

PRECHARGE

READ WITH

AUTO

PRECHARGE

POWER

APPLIED DEFINITION OF ALLOWS

Manual

Input

Automatic

Sequence

READ

SUSPEND

WRITE

SUSPEND

Note : CKE\ means CKE goes Low-level from High-level.

MB81ES171625/173225-12/-15

■BANK OPERATION COMMAND TABLE

• Minimun Clock Latency or Delay Time for Single Bank Operation

*1: Assume all banks are in idle state.

*2: Assume output is in High-Z state.

*3: Assume tRAS (Min) is satisfied.

*4: Assume no I/O conflict.

*5: Assume the last data have been appeared on DQ.

Second

command

(same

bank) MRS ACTV READ READA WRIT WRITA PRE PALL REF SELF BST

First

command

MRS tRSC tRSC tRSC tRSC tRSC tRSC tRSC

ACTV tRCD tRCD tRCD tRCD tRAS tRAS 1

1 1

READA

*1, *2

BL +

tRP

BL +

tRP

BL +

tRP

BL +

tRP

BL +

tRP

BL +

tRP

BL +

tRP

WRIT tWR tWR 11

tDPL

tDPL 1

WRITA

*1, *2

BL-1

+ tDAL

BL-1

+ tDAL

BL-1

+ tDAL

BL-1

+ tDAL

BL-1

+ tDAL

BL-1

+ tDAL

BL-1

+ tDAL

PRE

*1, *2

tRP tRP 1

tRP

*1, *5

tRP 1

PALL

tRP tRP 11tRP

tRP 1

REF tREFC tREFC tREFC tREFC tREFC tREFC tREFC

SELFX tREFC tREFC tREFC tREFC tREFC tREFC tREFC

Illegal Command.

MB81ES171625/173225-12/-15

• Minimum Clock Latency or Delay Time for Multi Bank Operation

*1: Assume all banks are in idle state.

*2: Assume output is in High-Z state.

*3: tRRD (Min) of other bank (the second command will be asserted) is satisfied.

*4: Assume other bank is in active, read or write state.

*5: Assume tRAS (Min) is satisfied.

*6: Assume other banks are not in READA/WRITA state.

*7: Assume the last data have been appeared on DQ.

*8: Assume no I/O conflict.

Second

command

(other

bank)MRS ACTV

READ

READA

WRIT

WRITA PRE PALL REF SELF BST

First

command

MRS tRSC tRSC tRSC tRSC tRSC tRSC tRSC

ACTV

tRRD

*5, *6

tRAS 1

READ

*1, *3

111

READA

*1, *2

BL +

tRP

*1, *3

*5, *8

BL +

tRP

BL +

tRP

BL +

tRP

BL +

tRP

WRIT

*1, *3

11111

tDPL 1

WRITA

*1, *2

BL-1

+ tDAL

*1, *3

BL-1

+ tDAL

BL-1

+ tDAL

BL-1

+ tDAL

BL-1

+ tDAL

PRE

*1, *2

tRP

*1, *3

*5, *6

tRP

*1, *7

tRP 1

PALL

tRP tRP 11tRP

tRP 1

REF tREFC tREFC tREFC tREFC tREFC tREFC tREFC

SELFX tREFC tREFC tREFC tREFC tREFC tREFC tREFC

Illegal Command.

MB81ES171625/173225-12/-15

■MODE REGISTER TABLE

MODE REGISTER SET

BA A12 A11 A10 A9A8*2A7*2A6A5A4A3A2A1A0ADDRESS

0 or 1 0 0 CL BT BL MODE

*1: BL = 1 and Full Column are not applicable to the interleave mode.

*2: A7 and A8 = 1 are reserved for vender test.

A6A5A4CAS Latency

Reserved

A2A1A0

Burst Length

BT = 0 BT = 1 *1

Reserved

Full Column

Reserved

A3Burst Type

Sequential

Interleave

MB81ES171625/173225-12/-15

■ABSOLUTE MAXIMUM RATINGS

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■RECOMMENDED OPERATING CONDITIONS

(Referenced to Vss)

*1 : All voltages are referenced to VSS.

*4 : The maximum junction temperature of FCRAM (Tj) should not be more than +100 °C.

Tj is represented by the power consumption of FCRAM (PFCRAM) and Logic LSI(PD),the thermal resistance of the

package(θja),and the maximum ambient temperature of the SiP(TAmax).

Tjmax[ °C] = TAmax[ °C] + θja[ °C/W] × Σ Pmax[W]

Σ Pmax[W] = PFCRAM + PD

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

representatives beforehand.

Parameter Symbol Rating Unit

Min Max

Voltage of VCC Supply Relative to VSS VDD, VDDQ −0.5 +3.0 V

Voltage at Any Pin Relative to VSS VIN, VOUT −0.5 +3.0 V

Short Circuit Output Current IOUT −13 +13 mA

Storage Temperature TSTG −55 +125 °C

Parameter Symbol Value Unit

Min Typ Max

Supply Voltage*1VDD, VDDQ 1.65 1.8 1.95 V

VSS, VSSQ 000V

Input High Voltage*2VIH VDDQ−0.4 ⎯VDDQ + 0.3 V

Input Low Voltage*3VIL −0.3 ⎯0.4 V

Ambient Temperature TA0⎯+70 °C

Junction Temperature*4Tj 0 ⎯+100 °C

-1.5 V

IL (Max)

3.0 V

IH (Min)

Pulse width ≤ 5 ns

50% of pulse amplitude

Pulse width ≤ 5 ns

*3 : Undershoot limit: VIL (Min)

= VSS –1.5 V for pulse width ≤ 5 ns

acceptable,pulse width measured at 50% of

pulse amplitude.

*2 : Overshoot limit: VIH (Max)

= 3.0 V for pulse width ≤ 5 ns

acceptable,pulse width measured at 50% of

pulse amplitude.

MB81ES171625/173225-12/-15

■CAPACITANCE

(f = 1 MHz, TA = +25 °C)

Parameter Symbol Value Unit

Min Typ Max

Input Capacitance, Except for CLK CIN1 2.0 ⎯5.0 pF

Input Capacitance for CLK CIN2 2.0 ⎯5.0 pF

I/O Capacitance CI/O 2.0 ⎯5.0 pF

MB81ES171625/173225-12/-15

■DC CHARACTERISTICS

(At recommended operating conditions unless otherwise noted.)

(Continued)

Parameter Symbol Condition Value Unit

Min Max

Output High Voltage VOH(DC) IOH = −2 mA VDDQ −0.2 ⎯V

Output Low Voltage VOL(DC) IOL = 2 mA ⎯0.2 V

Input Leakage Current (Any Input) ILI

0 V ≤ VIN ≤ VDDQ;

All other pins not under

test = 0 V

−55μA

Output Leakage Current ILO 0 V ≤ VIN ≤ VDDQ;

Data out disabled −55μA

Average Power Supply Current

(Operating Current) IDD1

Burst Length = 1,

tRC = Min for BL = 1,

tCK = Min,

One bank active,

Output pin open,

Addresses changed up to

one time during tCK (Min) ,

0 V ≤ VIN ≤ VIL Max,

VIH Min ≤ VIN ≤ VDDQ

⎯30 mA

Power Supply Current

(Precharge Standby Current)

IDD2P

CKE = 0 V,

All banks idle, tCK = Min,

Power down mode,

VIL = 0 V,

VIH = VDDQ

⎯1mA

IDD2PS

CKE = 0 V, All banks idle,

CLK = VDDQ or 0 V,

Power down mode,

VIL = 0 V,

VIH = VDDQ

⎯1mA

Power Supply Current

(Precharge Standby Current)

IDD2N

CKE = VDDQ , All banks idle,

tCK = Min,

NOP command only,

Input signals (except to

CMD) are changed one

time during 30 ns,

VIL=0 V,

VIH = VDDQ

⎯4mA

IDD2NS

CKE = VDDQ ,

All banks idle,

CLK = VDDQ or 0 V,

Input signal are stable,

VIL=0 V,

VIH = VDDQ

⎯1mA

MB81ES171625/173225-12/-15

(Continued)

Notes: • All voltages are referenced to VSS,VSSQ.

• DC characteristics are measured after following “17. Power-Up Initialization” procedure in ■FUNCTIONAL

DESCRIPTION.

• IDD depends on output termination, load conditions, clock rate, number of address and/or command change

within certain period. The specified values are obtained with the output open.

Parameter Symbol Condition Value Unit

Min Max

Power Supply Current

(Active Standby Current)

IDD3P

CKE = 0 V ,

Any bank active,

tCK = Min,

VIL = 0 V,

VIH = VDDQ

⎯1mA

IDD3PS

CKE = 0 V ,

Any bank active,

CLK = VDDQ or 0 V,

VIL = 0 V,

VIH = VDDQ

⎯1mA

MB81ES171625/

173225-12

IDD3N

CKE = VDDQ ,

Any bank active,

tCK = Min,

NOP command only,

Input signals (except to

CMD) are changed one

time during 30 ns,

VIL = 0 V,

VIH = VDDQ

⎯13 mA

MB81ES171625/

173225-15 ⎯10 mA

IDD3NS

CKE = VDDQ ,

Any bank active,

CLK = VDDQ or 0 V,

Input signals are stable,

VIL = 0 V,

VIH = VDDQ

⎯1mA

Average Power Supply

Current

(Burst mode Current)

MB81ES171625/

173225-12

IDD4

tCK = Min,

Burst Length = 4,

Output pin open,

All-banks active,

Gapless data,

0 V ≤ VIN ≤ VIL Max,

VIH Min ≤ VIN ≤ VDDQ

⎯51 mA

MB81ES171625/

173225-15 ⎯40 mA

Average Power Supply Current

(Auto Refresh Current) IDD5

Auto-refresh;

tCK = Min,

tREFC = Min,

0 V ≤ VIN ≤ VIL Max,

VIH Min ≤ VIN ≤ VDDQ

⎯73 mA

Average Power Supply Current

(Self Refresh Current) IDD6

Self-refresh;

CLK = VDDQ or 0 V,

CKE= 0 V,

0 V ≤ VIN ≤ VIL Max,

VIH Min ≤ VIN ≤ VDDQ

⎯5mA

MB81ES171625/173225-12/-15

■AC CHARACTERISTICS

(1) Basic AC Characteristics

(At recommended operating conditions unless otherwise noted.)

*1: If input signal transition time (tT) is longer than 1 ns; [ (tT / 2) − 0.5] ns should be added to tCAC (Max) , tAC (Max) ,

tHZ (Max) , and tSI (Min) spec values, [ (tT / 2) − 0.5] ns should be subtracted from tLZ (Min) , tHZ (Min) , and tOH

(Min) spec values, and (tT − 1.0) ns should be added to tCH (Min) , tCL (Min) , tSI (Min) , and tHI (Min) spec values.

*2: This value is for reference only.

*3: Measured under AC test load circuit shown in “ (5) Measurement Condition of AC Characteristics (Load Circuit) ”.

*4: tAC also specifies the access time at burst mode except for first access at CL = 1.

*5: Specified where output buffer is no longer driven.

Notes: • AC characteristics are measured after following “17. Power-Up Initialization” procedure in ■FUNCTIONAL

DESCRIPTION.

• AC characteristics assume tT = 1 ns ,10 pF of capacitive and 50 Ω of terminated load.

Refer to “ (5) Measurement Condition of AC Characteristics (Load Circuit) ”.

• 0.9 V is the reference level for measuring timing of input/output signals.

• Transition times are measured between VIH (Min) and VIL (Max) . Refer to “ (6) Set up, Hold and Delay Time”.

Parameter Symbol

MB81ES171625/173225

Unit-12 -15

Min Max Min Max

Clock Period CL = 1t

CK1 23.4 1000 30 1000 ns

CL = 2t

CK2 11.7 15 ns

Clock High Time *1tCH 4.5 ⎯6⎯ns

Clock Low Time *1tCL 4.5 ⎯6⎯ns

Input Setup Time *1tSI 3⎯3⎯ns

Input Hold Time *1tHI 2⎯2⎯ns

XRAS Access Time *2tRAC ⎯51.9 ⎯57 ns

XCAS Access Time *1, *3tCAC ⎯21.9 ⎯27 ns

Access Time from Clock

(tCK = Min) *1, *3, *4

CL = 1tAC1 ⎯21.9 ⎯27 ns

CL = 2t

AC2 ⎯10.2 12 ns

Output in Low-Z *1tLZ 0⎯0⎯ns

Output in High-Z *1, *5CL = 1tHZ1 2.5102.510ns

CL = 2t

HZ2 2.5102.510ns

Output Hold Time *1, *3tOH 2.5 ⎯2.5 ⎯ns

Time between Auto-Refresh command interval *2tREFI ⎯7.8 ⎯7.8 μs

Time between Refresh tREF ⎯16 ⎯16 ms

Transition Time tT0.5 5 0.5 5 ns

MB81ES171625/173225-12/-15

(2) Base Values for Clock Count/Latency

*: tRC (Min) is not sum of tRAS (Min) and tRP (Min) . Actual clock count of tRC ( RC) must satisfy tRC (Min) , tRAS (Min)

and tRP (Min) .

(3) Clock Count Formula

Note: All base values are measured from the clock edge at the command input to the clock edge for the next

command input. All clock counts are calculated by a simple formula : clock count equals base value divided

by clock period (round up to a whole number) .

Parameter Symbol

MB81ES171625/173225

Unit-12 -15

Min Max Min Max

XRAS Cycle Time * tRC 75 ⎯75 ⎯ns

XRAS Precharge Time tRP 30 ⎯30 ⎯ns

XRAS Active Time tRAS 45 110000 45 110000 ns

XRAS to XCAS Delay Time tRCD 30 ⎯30 ⎯ns

Write Recovery Time tWR 11.7 ⎯15 ⎯ns

XRAS to XRAS Bank Active Delay Time tRRD 11.7 ⎯15 ⎯ns

Data-in to Precharge Lead Time tDPL 11.7 ⎯15 ⎯ns

Data-in to Active/ Refresh Command Period tDAL 1cyc+ tRP ⎯1cyc+ tRP ⎯ns

Refresh Cycle Time tREFC 75 ⎯75 ⎯ns

Mode Resister Set Cycle Time tRSC 45 ⎯45 ⎯ns

Clock ≥ Base Value

Clock Period (Round up to a whole number)

MB81ES171625/173225-12/-15

(4) Latency - Fixed Values

(The latency values on these parameters are fixed regardless of clock period.)

(5) Measurement Condition of AC Characteristics (Load Circuit)

Parameter Symbol MB81ES171625/173225 Unit

-12 -15

CKE to Clock Disable CKE 1 1 cycle

DQM to Output in High-Z CL = 1 DQZ1 1 1 cycle

CL = 2 DQZ2 2 2 cycle

DQM to Input Data Delay DQD 0 0 cycle

Last Output to Write Command Delay OWD 2 2 cycle

Write Command to Input Data Delay DWD 0 0 cycle

Precharge to Output in High-Z Delay CL = 1 ROH1 1 1 cycle

CL = 2 ROH2 2 2 cycle

Burst Stop Command to Output in High-Z Delay CL = 1 BSH1 1 1 cycle

CL = 2 BSH2 2 2 cycle

XCAS to XCAS Delay (Min) CCD 1 1 cycle

XCAS Bank Delay (Min) CBD 1 1 cycle

R1 = 50 Ω

0.9 V

CL = 10 pF

Output

MB81ES171625/173225-12/-15

(6) Setup, Hold and Delay Time

(7) Delay Time for Power Down Exit

VOH

VOL

0.9 V

1.4 V

0.4 V

0.9 V

tCK

tCH

tSI tHI

tCAC, tAC

tLZ

tHZ

tOH

tCL

CLK

VALID

Input

(Control,

Addr. & Data)

Output

Notes : • Reference level of input/output signal is 0.9 V.

• Access time is measured at 0.9 V.

• AC characteristics are also measured in this condition.

: INVALID

CLK

CKE

tSI

ACTV

NOP

1 clock (Min)

Command

H or L

MB81ES171625/173225-12/-15

(8) Pulse Width

(9) Access Time

, t

RAS

, t

RCD

, t

REFI

REFC

, t

DPL

, t

DAL

, t

RSC

, t

RRD

CLK

COMMAND COMMAND

Input

(Control)

Notes : • These parameters are a limit value of the rising edge of the clock from one command input to

the next input.

• Measurement reference voltage is 0.9 V.

: INVALID

CLK

XRAS

XCAS

tAC

tRCD

tRAC

tAC tAC

1 clock at CL = 2

Q (Valid) Q (Valid) Q (Valid)

tCAC

(Output)

MB81ES171625/173225-12/-15

■TIMING DIAGRAMS

1. Clock Enable - READ and WRITE Suspend (@ BL = 4)

2. Clock Enable - Power Down Entry and Exit

CLK

CKE

CLK

DQ D1 D2 D3 D4

Q1 Q2 Q3 Q4

∗1∗1

∗2

∗2∗2

∗3∗3

∗2

tSI tHI tSI tHI tSI tHI

CKE CKE

(NO Change) (NO Change)

NOT

Written

NOT

Written

(Internal)

(Read)

(Write)

(1 clock)*1(1 clock)*1

*1: The latency of the CKE ( CKE) is one clock.

*2: During the read mode, burst counter will not be increased/decreased at the next clock of the CSUS

command. Output data remains the same data.

*3: During the write mode, data at the next clock of the CSUS command is ignored.

CLK

CKE

tSI (Min)

tREF (Max)

NOP PD (NOP) NOP ACTV ∗3

∗2

∗1

1 clock (Min)

H or L

Command

*1: The Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode.

*2: The NOP command should be asserted in conjunction with CKE.

*3: The ACTV command can be latched after tSI + 1 clock (Min) .

MB81ES171625/173225-12/-15

3. Column Address to Column Address Input Delay

4. Different Bank Address Input Delay

CLK

XRAS

XCAS

tRCD (Min) CCD CCD CCD CCD

Row

Address

Column

Address

Address Column

Address

Column

Address

Column

Address

Column

Address

Note : XCAS to XCAS delay ( CCD) can be one or more clock period.

CLK

XRAS

XCAS

tRCD (Min)

tRRD (Min)

CBD CBD

Row

Address

Bank 0 Bank 1 Bank 1 Bank 1Bank 0 Bank 0

Column

Address

Row

Address

Column

Address

Column

Address

Column

Address

Note : XCAS Bank delay ( CBD) can be one or more clock period.

MB81ES171625/173225-12/-15

5. DQM - Input Mask and Output Disable (@ CL = 2, BL = 4)

6. Precharge Timing (Applied to the Same Bank)

CLK

DQM

DQ D1

DQZ2(2clocks)

Q2 Q4

D4D3

DQD

(@ Read)

(@ Write)

End of burst

Masked End of burst

(same clock)

High-Z

CLK

ACTV PRE

RAS

(Min)

Command

Note : PRE means ‘PRE’ or ‘PALL’.

MB81ES171625/173225-12/-15

7. READ Interrupted by Precharge (Example @ CL = 2, BL = 4)

CLK

ROH2

Q1 Q2

Q1 Q2 Q3 Q4

ROH2

(2 clocks)

Command

PRE

No effect (end of burst)

PRE

Notes : • In case of CL = 1, the ROH1 is 1 clock.

• In case of CL = 2, the ROH2 is 2 clocks.

• PRE means ‘PRE’ or ‘PALL’.

High-Z

MB81ES171625/173225-12/-15

8. READ Interrupted by Burst Stop (Example @ BL = Full Column)

9. WRITE Interrupted by Burst Stop (Example @ BL = 2)

BST

QnQn - 2 Qn - 1

BST

QnQn - 2 Qn - 1 Qn + 1

BSH2(2 clocks)

BSH1(1 clock)

CLK

(CL = 1)

(CL = 2)

Command

High-Z

BST

CLK

Command

LAST Dn

Masked

by BST

Command

MB81ES171625/173225-12/-15

10. WRITE Interrupted by Precharge

11. READ Interrupted by WRITE (Example @ CL = 2, BL = 4)

CLK

ACTV

tDPL (Min) tRP (Min)

Command

Dn-1 LAST Dn

Masked

by Precharge

PRE

Note : The precharge command (PRE) should be issued only after the tDPL of final data input is satisfied.

PRE means ‘PRE’ or ‘PALL’.

CLK

DQM

READ WRIT

∗1∗2∗3

OWD

DQZ2(2 clocks)

DWD

Q1D1D2

*1: The First DQM makes high-impedance state High-Z between the last output and the first input data.

*2: The Second DQM makes internal output data mask to avoid bus contention.

*3: The Third DQM in illustrated above also makes internal output data mask. If burst read ends (the final

data output) at or after the second clock of burst write, this third DQM is required to avoid internal bus

contention.

Command

MB81ES171625/173225-12/-15

12. WRITE to READ Timing (Example @ CL = 1, BL = 4)

13. READ with Auto-Precharge (Example @ CL = 2, BL = 2 Applied to same bank)

CLK

DQM

WRIT READ

D1 D2 Q3Q2Q1

tWR (Min)

tACtAC

tCAC (Max) tAC

Command

Masked

by READ

Notes : • The Read command should be issued after tWR of the final data input is satisfied.

• The write data after the READ command is masked by the READ command.

ACTV

CLK

DQM

BL + tRP

ACTV

READA

Q1 Q2

NOP or DESL

Command

*: The Next ACTV command should be issued after BL + tRP from the READA command.

MB81ES171625/173225-12/-15

14. WRITE With Auto-Precharge (Example @ CL = 2, BL = 2 Applied to same bank)

15. Auto-Refresh Timing

ACTV

CLK

DQM

DAL

(Min)

(BL - 1) + t

DAL*

ACTV

WRITA

D1 D2

Command NOP or DESL

*: The Next command should be issued after (BL − 1) + tDAL from the WRITA command.

Notes: • If the final data is masked by DQM, the precharge does not start at the clock of the final data input.

• Once the auto precharge command is asserted, no new command within the same bank can be issued.

• The Auto-precharge command can not be invoked at full column burst operation.

REF∗

REFNOP∗

NOP∗

CLK

REFC

(Min) t

REFC

(Min)

Command Command*3

H or L *4

*1: All banks should be precharged prior to the first Auto-refresh command (REF) .

*2: Either the NOP or DESL command should be asserted within tREFC period while Auto-refresh mode.

*3: Any activation command such as the ACTV or MRS commands other than the REF command should be

asserted after tREFC from the last REF command.

*4: Bank select is ignored at REF command. The refresh address and bank select are selected by the internal

refresh counter.

MB81ES171625/173225-12/-15

16. Self-Refresh Entry and Exit Timing

17. Mode Register Set Timing

NOP ∗1SELF SELFX ∗2NOP ∗3

tSI (Min)

tSI

tREFC

CLK

CKE

∗4

Command H or L Command

*1: The Precharge command (PRE or PALL) should be asserted if any bank is active prior to the Self-refresh

Entry command (SELF) .

*2: The Self-refresh Exit command (SELFX) is latched after tSI.

*3: Either the NOP or DESL command can be used during tREFC period.

*4: CKE should be held high for at least one tREFC period after tSI.

Entry Exit

ACTVMRS

tRSC (Min)

CLK

Command

Address

NOP or DESL

MODE Row

Address

Note : The Mode Register Set command (MRS) should be asserted only after all banks have been

precharged and DQ is in High-Z.

MB81ES171625/173225-12/-15

■ ORDERING INFORMATION

Part number Configuration Shipping form Remarks

MB81ES171625-12WFKT 512 K word × 16 bit × 2 bank Wafer

MB81ES171625-15WFKT 512 K word × 16 bit × 2 bank Wafer

MB81ES173225-12WFKT 256 K word × 32 bit × 2 bank Wafer

MB81ES173225-15WFKT 256 K word × 32 bit × 2 bank Wafer

MB81ES171625/173225-12/-15

MEMO

FUJITSU MICROELECTRONICS LIMITED

Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387

http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South America

FUJITSU MICROELECTRONICS AMERICA, INC.

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Tel: +1-408-737-5600 Fax: +1-408-737-5999

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Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

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http://www.fujitsu.com/sg/services/micro/semiconductor/

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Shanghai 200002, China

Tel: +86-21-6335-1560 Fax: +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.

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Tsimshatsui, Kowloon

Hong Kong

Tel: +852-2377-0226 Fax: +852-2376-3269

http://cn.fujitsu.com/fmc/tw

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-

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