BU-61843F4-162Z - Data Device Corporation (DDC)

BU-6174X/6184X/6186X

DESCRIPTION

The Enhanced Mini-ACE family of

MIL-STD-1553 terminals provide

complete interfaces between a

host processor and a 1553 bus.

These terminals integrate dual

transceiver, protocol logic, and

4K words or 64K words of RAM.

With a 1.0 inch square package,

the Enhanced Mini-ACE is nearly

100% footprint and software com-

patibile with the previous genera-

tion Mini-ACE (Plus) terminals, and

is software compatibile with the

older ACE series.

The Enhanced Mini-ACE is pow-

ered by a choice 5V, or 5V/3.3V

(3.3V logic). Multiprotocol support

of MIL-STD-1553A/B and

STANAG 3838, including versions

incorporating McAir compatible

transmitters, is provided.There is a

choice of 10, 12, 16, or 20 Mhz

clocks. The BC/RT/MT versions

with 64K words of RAM include

built-in RAM parity checking.

BC features include a built-in mes-

sage sequence control engine,

with a set of 20 instructions. This

provides an autonomous means of

implementing multi-frame mes-

sage scheduling, message retry

schemes, data double buffering,

asynchronous message insertion,

and reporting to the host CPU.The

Enhanced Mini-ACE incorporates

a fully autonomous built-in self-test,

which provides comprehensive

testing of the internal protocol logic

and/or RAM.

The Enhanced Mini-ACE RT offers

the same choices of subaddress

buffering as the ACE and Mini-ACE

(Plus), along with a global circular

buffering option, 50% rollover inter-

rupt for circular buffers, an interrupt

status queue, and an "Auto-boot"

option to support MIL-STD-1760.

The Enhanced Mini-ACE terminals

provide the same flexibility in host

interface configurations as the

ACE/Mini-ACE, along with a reduc-

tion in the host processor's worst

case holdoff time.

ENHANCED MINIATURE ADVANCED

COMMUNICATIONS ENGINE

(ENHANCED MINI-ACE)

TRANSCEIVER

CH. A

TRANSCEIVER

CH. B

DUAL

ENCODER/DECODER,

MULTIPROTOCOL

AND

MEMORY

MANAGEMENT

RT ADDRESS

SHARED

RAM

ADDRESS BUS

PROCESSOR

AND

MEMORY

INTERFACE

LOGIC

DATA BUS D15-D0

A15-A0

DATA

BUFFERS

ADDRESS

BUFFERS

PROCESSOR

DATA BUS

PROCESSOR

ADDRESS BUS

MISCELLANEOUS

INCMD

CLK_IN, TAG_CLK,

MSTCLR,SSFLAG/EXT_TRG

RTAD4-RTAD0, RTADP

TRANSPARENT/BUFFERED, STRBD, SELECT,

RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,

MSB/LSB/DTGRT

IOEN, MEMENA-OUT, READYD

ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,

8/16-BIT/DTREQ, POLARITY_SEL/DTACK

INT

PROCESSOR

AND

MEMORY

CONTROL

INTERRUPT

REQUEST

TX/RX_A

TX/RX_B

* SEE ORDERING INFORMATION FOR AVAILABLE MEMORY

FEATURES

•

FULLY INTEGRATED 1553A/B NOTICE 2,

MCAIR, STANAG 3838 INTERFACE TERMINAL

•

COMPATIBLE WITH MINI-ACE (PLUS)

AND ACE GENERATIONS

•

CHOICE OF :

•

RT OR BC/RT/MT IN SAME FOOTPRINT

•

RT OR BC/RT/MT WITH 4K RAM

•

BC/RT/MTWITH 64K RAM,WITH RAM PARITY

•

CHOICE OF 5V OR 3.3V LOGIC

•

5V TRANSCEIVER WITH 1760 AND

MCAIR COMPATIBLE OPTIONS

•

COMPREHENSIVE BUILT-IN SELF-TEST

•

FLEXIBLE PROCESSOR/MEMORY

INTERFACE, WITH REDUCED HOST WAIT TIME

•

CHOICE OF 12, 12, 18, OR 20 MHZ CLOCK

•

HIGHLY AUTONOMOUS BC WITH

BUILT-IN MESSAGE SEQUENCE CONTROL:

•

FRAME SCHEDULING

•

BRANCHING

•

ASYNCHRONOUS MESSAGE INSERTION

•

GENEERAL PURPOSE QUEUE

•

USER-DEFINED INTERRUPTS

•

ADVANCED RT FUNCTIONS

•

GLOBAL CIRCULAR BUFFERING

•

INTERRUPT STATUS QUEUE

•

50% CIRCULAR BUFFER ROLLOVER

INTERRPTS

0.88

1.08

1.28

1.68

0.69

0.89

1.09

1.49

0.77

0.97

1.17

1.57

0.58

0.78

0.98

1.38

0.22

0.42

0.62

1.02

5.5

3.6

5.5

160

260

360

560

100

200

300

500

140

240

340

540

180

280

480

4.5

3.0

4.75

POWER DISSIPATION

Total Hybrid

!BU-61865

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

!BU-61864

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

!BU-61845, BU-61745

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

!BU-61863, BU-61743

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

Hottest Die

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

POWER SUPPLY REQUIREMENTS

Voltages/Tolerances

!+5V (RAM for 61864(5),

Logic for BU-61XX5) (Note 11)

!+3.3V (Logic for BU-61XX3/4)

(Note 11)

!+5V (Ch. A, Ch. B)

Current Drain (Total Hybrid)

!BU-61865

• +5V (Logic, RAM, Ch. A, Ch. B)

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

!BU-61864

• +5V (RAM, Ch. A, Ch. B)

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

• 3.3V Logic

!BU-61845. BU-61745

• +5V (Logic, RAM, Ch. A, Ch. B)

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

!BU-61743

• +5V (Ch. A, Ch. B)

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

• 3.3V Logic

UNITSMAXTYPMINPARAMETER

TABLE 1. EHANCED MINI-ACE SERIES SPECIFICATIONS (Cont’d)

5.0

3.3

5.0

µA

0.7

0.2•Vcc

-50

-33

-50

-33

0.4

-3.4

2.1

0.8•Vcc

0.4

1.0

-10

-350

-10

-350

-10

2.4

3.4

LOGIC

VIH

All signals except CLK_IN

CLK_IN

VIL

All signals except CLK_IN

CLK_IN

Schmidt Hysteresis

All signals except CLK_IN

CLK_IN

IIH, IIL

All signals except CLK_IN

IIH (Vcc=5.5V, VIN=Vcc)

IIH (Vcc=5.5V, VIN=2.7V)

IIL (Vcc=3.6V, VIN=Vcc)

IIH (Vcc=3.6V, VIH=2.7V)

IIL (Vcc=5.5V, VIH=0.4V)

IIL (Vcc=3.6V, VIH=0.4V)

CLK_IN

IIH

IIL

VOH (Vcc=4.5V, VIH=2.7V,

VIL=0.2V, IOH=max)

VOH (Vcc=3.0V, VIH=2.7V,

VIL=0.2V, IOH=max)

VOL (Vcc=4.5V, VIH=2.7V,

VIL=0.2V, IOL=max)

VOL (Vcc=3.0V, VIH=2.7V,

VIL=0.2V, IOL=max)

IOL

IOH

CI(Input Capacitance)

CIO (Bi-directional signal input

capacitance)

Vp-p

MVP-P

mVpeak

nsec

250

300

150

250

-250

100

200

TRANSMITTER

Differential Output Voltage

!Direct Coupled Across 35 Ω,

Measured on Bus

!Transformer Coupled Across

70 Ω, Measured on Bus

(BU-61XXXXX-XX0,

BU-61XXXXX-XX2) (Note 13)

Output Noise, Differential (Direct

Coupled)

Output Offset Voltage, Transformer

Coupled Across 70 ohms

Rise/Fall Time

(BU-61XXXX3,

BU-61XXXX4)

kΩ

Vp-p

Vpeak

0.860

2.5

0.200

RECEIVER

Differential Input Resistance

(Notes 1-6)

Differential Input Capacitance

(Notes 1-6)

Threshold Voltage, Transformer

Coupled, Measured on Stub

Common Mode Voltage (Note 7)

6.0

7.0

6.0

-0.3

ABSOLUTE MAXIMUM RATING

Supply Voltage

!Logic +5V or +3.3V

!RAM +5V

!Transceiver +5V (Note 11)

Logic

!Voltage Input Range for +5V

Logic (BU-61XX5)

!Voltage Input Range for +3.3V

Logic (BU-61XX3/4)

UNITSMAXTYPMINPARAMETER

TABLE 1. EHANCED MINI-ACE SERIES SPECIFICATIONS

in.

(mm)

1.0 X 1.0 X 0.155

(25.4 x 25.4 x 3.94)

°C/W

°C

µs

MHz

150

+300

19.5

23.5

51.5

131

0.01

0.1

0.001

0.01

2.5

9.5

10.0

10.5

18.5

22.5

50.5

129.5

660.5

16.0

12.0

10.0

20.0

-55

-65

17.5

21.5

49.5

127

-0.01

-0.10

0.001

-0.01

Weight oz

(g)

0.6

(17)

PHYSICAL CHARACTERISTICS

Size

THERMAL

Thermal Resistance, Junction-to-Case,

Hottest Die (θJC)

Operating Junction Temperature

Storage Temperature

Lead Temperature (soldering, 10 sec.)

1553 MESSAGE TIMING

Completion of CPU Write

(BC Start)-to-Start of Next Message

for (Non-enhanced BC Mode)

BC Intermessage Gap (Note 8)

Non-enhanced

(Mini-ACE compatible) BC mode

Enhanced BC mode (Note 9)

BC/RT/MT Response Timeout (Note 10)

!18.5 nominal

!22.5 nominal

!50.5 nominal

!128.0 nominal

RT Response Time

(mid-parity to mid-sync) (Note 11)

Transmitter Watchdog Timeout

CLOCK INPUT

Frequency

!Nominal Value

• Default Mode

• Option

!Long Term Tolerance

• 1553A Compliance

• 1553B Compliance

!Short Term Tolerance, 1 second

• 1553A Compliance

• 1553B Compliance

!Duty Cycle

UNITSMAXTYPMINPARAMETER

TABLE 1. EHANCED MINI-ACE SERIES SPECIFICATIONS (Cont’d) NOTES:

Notes 1 through 6 are applicable to the Receiver Differential

Resistance and Differential Capacitance specifications:

(1) Specifications include both transmitter and receiver (tied together

internally).

(2) Impedance parameters are specified directly between pins TX/RX

A(B) and of the Enhanced Mini-ACE hybrid.

(3) It is assumed that all power and ground inputs to the hybrid are

connected.

(4) The specifications are applicable for both unpowered and powered

conditions.

(5) The specifications assumea2voltrmsbalanced, differential, sinu-

soidal input. The applicable frequency range is 75 kHz to 1 MHz.

(6) Minimum resistance and maximum capacitance parameters are

guaranteed over the operating range, but are not tested.

(7) Assumes a common mode voltage within the frequency range of

dc to 2 MHz, applied to pins of the isolation transformer on the stub

side (either direct or transformer coupled), and referenced to

hybrid ground. Transformer must be a DDC recommended trans-

former or other transformer that provides an equivalent minimum

CMRR.

(8) Typical value for minimum intermessage gap time. Under software

control, this may be lengthened to 65,535 ms - message time, in

increments of 1 µs. If ENHANCED CPU ACCESS, bit 14 of

Configuration Register #6, is set to logic "1", then host accesses

during BC Start-of-Message (SOM) and End-of-Message (EOM)

transfer sequences could have the effect of lengthening the inter-

message gap time. For each host access during an SOM or EOM

sequence, the intermessage gap time will be lengthened by 6

clock cycles. Since there are 7 internal transfers during SOM, and

5 during EOM, this could theoretically lengthen the intermessage

gap by up to 72 clock cycles;i.e., up to 7.2 ms with a 10 MHz clock,

6.0 µs with a 12 MHz clock, 4.5 µs with a 16 MHz clock, or 3.6 µs

with a 20 MHz clock.

(9) For Enhanced BC mode, the typical value for intermessage gap

time is approximately 10 clock cycles longer than for the non-

enhanced BC mode.That is, an addition of 1.0 µs at 10 MHz, 833

ns at 12 MHz, 625 ns at 16 MHz, or 500 ns at 20 MHz.

(10) Software programmable (4 options). Includes RT-to-RT Timeout

(measured mid-parity of transmit Command Word to mid-sync of

transmitting RT Status Word).

(11) Measured from mid-parity crossing of Command Word to mid-sync

crossing of RT's Status Word.

(12) External 10 pF Tantalum and 0.1 µF capacitors should be located

as close as possible to Pins 20 and 72, and a 0.1 µF at pin 37.For

BU-61864 and BU-61865, there should also be a 0.1 µF at pin 26.

(13) MIL-STD-1760 requires a 20 Vp-p minimum output on the stub

connection.

)B(ARX/TX

INTRODUCTION

The BU-61743/61745 RT, and BU-61843/61845/61864/61865

BC/RT/MT Enhanced Mini-ACE family of MIL-STD-1553 termi-

nals comprise a complete integrated interface between a host

processor and a MIL-STD-1553 bus. All members of the

Enhanced Mini-ACE family are packaged in the same 1.0 square

inch flatpack package. The Enhanced Mini-ACE hybrids are

nearly 100% footprint and software compatible with the previous

generation Mini-ACE and Mini-ACE Plus terminals, and are soft-

ware compatibility with the original ACE series.

The Enhanced Mini-ACE provides complete multiprotocol sup-

port of MIL-STD-1553A/B/McAir and STANAG 3838.All versions

integrate dual transceiver; along with protocol, host interface,

memory management logic; and a minimum of 4K words of

RAM. In addition, the BU-61864 and BU-61865 BC/RT/MT ter-

minals include 64K words of internal RAM, with built-in parity

checking.

The Enhanced Mini-ACEs include a 5V, voltage source trans-

ceiver for improved line driving capability, with options for MIL-

STD-1760 and McAir compatibility. As a means of reducing

power consumption, there are versions for which the logic is

Enhanced Mini-ACE may operate with a choice of 10, 12, 16, or

20 MHz clock inputs.

One of the new salient features of the Enhanced Mini-ACE is its

Enhanced bus controller architecture.The Enhanced BC's high-

ly autonomous message sequence control engine provides a

means for offloading the host processor for implementing multi-

frame message scheduling, message retry schemes, data dou-

ble buffering, and asynchronous message insertion. For the pur-

pose of performing messaging to the host processor, the

Enhanced BC mode includes a General Purpose Queue, along

with user-defined interrupts.

A second major new feature of the Enhanced Mini-ACE is the

incorporation of a fully autonomous built-in self-test. This test

provides comprehensive testing of the internal protocol logic. A

separate test verifies the operation of the internal RAM. Since

the self-tests are fully autonomous, they eliminate the need for

the host to write and read stimulus and response vectors.

The Enhanced Mini-ACE RT offers the same choices of single,

double, and circular buffering for individual subaddresses as

ACE and Mini-ACE (Plus). New enhancements to the RT archi-

tecture include a global circular buffering option for multiple (or

all) receive subaddresses, a 50% rollover interrupt for circular

buffers, an interrupt status queue for logging up to 32 interrupt

events, and an option to automatically initialize to RT mode with

the Busy bit set. The interrupt status queue and 50% rollover

interrupt features are also included as improvements to the

Enhanced Mini-ACE's Monitor architecture.

To minimize board space and "glue" logic, the Enhanced Mini-

ACE terminals provide the same wide choice of host interface

configurations as the ACE and Mini-ACE (Plus). This includes

support of interfaces to 16-bit or 8-bit processors, memory or

port type interfaces, and multiplexed or non-multiplexed

address/data buses. In addition, with respect to ACE/Mini-ACE

(Plus), the worst case processor wait time has been significant-

ly reduced.For example, assuming a 16 MHz clock, this time has

been reduced from 2.8 µsto 632 ns for read accesses, and to

570 ns for write accesses.

The Enhanced Mini-ACE series terminals operate over the full

military temperature range of -55 to +125°C. Available screened

to MIL-PRF-38534C, the terminals are ideal for military and

industrial processor-to-1553 applications.

TRANSCEIVERS

The transceivers in the Enhanced Mini-ACE series terminals are

fully monolithic, requiring only a +5 volt power input. The trans-

mitters are voltage sources, which provide improved line driving

capability over current sources. This serves to improve perfor-

mance on long buses with many taps.The transmitters also offer

an option which satisfies the MIL-STD-1760 requirement for a

minimum of 20 volts peak-to-peak, transformer coupled output.

Besides eliminating the demand for an additional power supply,

the use of a +5V-only transceiver requires the use of a step-up,

rather than a step-down, isolation transformer. This provides the

advantage of a higher terminal input impedance than is possible

for a 15 volt or 12 volt transmitter. As a result, there is a greater

margin for the input impedance test, mandated for the 1553 val-

idation test. This characteristic allows for longer cable lengths

between a system connector and the isolation transformers of an

embedded 1553 terminal.

To provide compatibility to McAir specs, the Enhanced Mini-

ACEs are available with an option for transmitters with increased

rise and fall times.

Additionally, for MIL-STD-1760 applications, the Enhanced Mini-

ACE provides an option for a minimum stub voltage level of 20

volts peak-to-peak, transformer coupled.

The receiver sections of the Enhanced Mini-ACE are fully com-

pliant with MIL-STD-1553B Notice 2 in terms of front end over-

voltage protection, threshold, common mode rejection, and word

error rate.

The software interface of the Enhanced Mini-ACE to the host

processor consists of 24 internal operational registers for normal

operation, an additional 24 test registers, plus 64K words of

shared memory address space.The Enhanced Mini-ACE's 4K X

16 or 64K X 17 internal RAM resides in this address space.

For normal operation, the host processor only needs to access

the lower 32 register address locations (00-1F). The next 32

locations (20-3F) should be reserved, since many of these are

used for factory test.

BC General Purpose Queue Pointer /

RT-MT Interrupt Status Queue Pointer Register

(RD/WR)

11111

BC General Purpose Flag Register (WR)

Interrupt Mask Register #2 (RD/WR)

RESERVED

Interrupt Status Register #2 (RD)

BC Condition Code Register (RD)

BIT Test Status Register (RD)

Configuration Register #7 (RD/WR)

Configuration Register #6 (RD/WR)00011

Test Mode Register 711101

Test Mode Register 6

Test Mode Register 4

Test Mode Register 2

Test Mode Register 5

Test Mode Register 3

Test Mode Register 1

Test Mode Register 000001

RT BIT Word Register (RD)11110

RT Status Word Register (RD)01110

Non-Enhanced BC Frame Time / Enhanced BC

Initial Instruction Pointer / RT Last Command /

MT Trigger Word Register(RD/WR)

10110

BC Time Remaining to Next Message Register

(RD)

00110

BC Frame Time Remaining Register (RD)11010

RT / Monitor Data Stack Address Register (RD)01010

Configuration Register #5 (RD/WR)10010

Configuration Register #4 (RD/WR)00010

Configuration Register #3 (RD/WR)11100

Interrupt Status Register #1 (RD)01100

Time Tag Register (RD/WR)10100

BC Control Word /

RT Subaddress Control Word Register (RD/WR)

00100

Non-Enhanced BC/RT Command Stack Pointer /

Enhanced BC Instruction List Pointer Register

(RD)

11000

Start/Reset Register (WR)11000

Configuration Register #2 (RD/WR)01000

Configuration Register #1 (RD/WR)10000

Interrupt Mask Register #1 (RD/WR)00000

A0A1A2A3A4

DESCRIPTION/ACCESSIBILITY

ADDRESS LINES

TABLE 2. ADDRESS MAPPING

INTERNAL REGISTERS

The address mapping for the Enhanced Mini-ACE registers is illustrated in TABLE 2:

TABLE 3. INTERRUPT MASK REGISTER #1

(READ/WRITE 00H)

BIT DESCRIPTION

15(MSB) RESERVED

14 RAM PARITY ERROR

13 BC/RT TRANSMITTER TIMEOUT

12 BC/RT COMMAND STACK ROLLOVER

11 MT COMMAND STACK ROLLOVER

10 MT DATA STACK ROLLOVER

9HANDSHAKE FAIL

8BC RETRY

7RT ADDRESS PARITY ERROR

6TIME TAG ROLLOVER

5RT CIRCULAR BUFFER ROLLOVER

4RT SUBADDRESS CONTROL WORD EOM

3BC END OF FRAME

2FORMAT ERROR

1BC STATUS SET / RT MODE CODE / MT PATTERN TRIGGER

0(LSB) END OF MESSAGE

TABLE 4. CONFIGURATION REGISTER #1

(READ/WRITE 01H)

BIT BC FUNCTION (Bits

11-0 Enhanced Mode Only) RT WITHOUT ALTERNATE

STATUS RT WITH ALTERNATE

STATUS (Enhanced Only) MONITOR FUNCTION

(Enhanced mode only bits 12-0)

15 (MSB) RT/BC-MT (logic 0) (logic 1) (logic 1) (logic o)

14 MT/BC-RT (logic 0) (logic 0) (logic 0) (logic 1)

13 CURRENT AREA B/A CURRENT AREA B/A CURRENT AREA A/B CURRENT AREA B/A

12 MESSAGE STOP-ON-ERROR MESSAGE MONITOR ENABLED

(MMT) MESSAGE MONITOR

ENABLED MESSAGE MONITOR ENABLED

11 FRAME STOP-ON-ERROR S10 TRIGGER WORD ENABLED

10 STATUS SET

STOP-ON-MESSAGE BUSY S09 START-ON-TRIGGER

9STATUS SET

STOP-ON-FRAME SERVICE REQUEST S08 STOP-ON-TRIGGER

8FRAME AUTO-REPEAT SUBSYSTEM FLAG S07 NOT USED

7EXTERNAL TRIGGER ENABLED RTFLAG (Enhanced Mode Only) S06 EXTERNAL TRIGGER ENABLED

6INTERNAL TRIGGER ENABLED NOT USED S05 NOT USED

5INTERMESSAGE GAP TIMER

ENABLED NOT USED S04 NOT USED

4RETRY ENABLED NOT USED S03 NOT USED

3DOUBLED/SINGLE RETRY NOT USED S02 NOT USED

2BC ENABLED (Read Only) NOT USED S01 MONITOR ENABLED(Read Only)

1BC FRAME IN PROGRESS

(Read Only) NOT USED S00 MONITOR TRIGGERED

(Read Only)

0 (LSB) BC MESSAGE IN PROGRESS

(Read Only) RT MESSAGE IN PROGRESS

(Enhanced mode only,Read Only) RT MESSAGE IN

PROGRESS (Read Only) MONITOR ACTIVE

(Read Only)

DYNAMIC BUS CONTROL

ACCEPTANCE

SEPARATE BROADCAST DATA0(LSB)

ENHANCED RT MEMORY MANAGEMENT1

CLEAR SERVICE REQUEST2

LEVEL/PULSE* INTERRUPT REQUEST3

INTERRUPT STATUS AUTO CLEAR4

LOAD TIME TAG ON SYNCHRONIZE5

CLEAR TIME TAG ON SYNCHRONIZE6

TIME TAG RESOLUTION 07

TIME TAG RESOLUTION 18

TIME TAG RESOLUTION 29

256-WORD BOUNDARY DISABLE10

OVERWRITE INVALID DATA11

RX SA DOUBLE BUFFER ENABLE12

BUSY LOOKUP TABLE ENABLE13

RAM PARITY ENABLE14

ENHANCED INTERRUPTS

15(MSB)

DESCRIPTIONBIT

TABLE 5. CONFIGURATION REGISTER #2

(READ/WRITE 02H)

TABLE 6. START/RESET REGISTER

(WRITE 03H)

BIT DESCRIPTION

15(MSB) RESERVED

14 RESERVED

RESERVED

CLEAR SELF-TEST REGISTER

INITIATE RAM SELF-TEST

CLEAR RT HALT

7INITIATE PROTOCOL SELF-TEST

6BC/MT STOP-ON-MESSAGE

5BC STOP-ON-FRAME

4TIME TAG TEST CLOCK

3TIME TAG RESET

2INTERRUPT RESET

1BC/MT START

0(LSB) RESET

COMMAND STACK POINTER 00(LSB)

••

COMMAND STACK POINTER 15

15(MSB)

DESCRIPTIONBIT

TABLE 7. BC/RT COMMAND STACK POINTER REG.

(READ 03H)

RT-to-RT FORMAT0(LSB) BROADCAST FORMAT1MODE CODE FORMAT2

SUBSYSTEM FLAG BIT MASK

1553A/B SELECT3EOM INTERRUPT ENABLE4MASK BROADCAST BIT5OFF-LINE SELF-TEST6BUS CHANNEL A/B7RETRY ENABLED8RESERVED BITS MASK9TERMINAL FLAG BIT MASK10

BUSY BIT MASK12 SERVICE REQUEST BIT MASK13 MESSAGE ERROR MASK14 RESERVED

15(MSB) DESCRIPTIONBIT

TABLE 8. BC CONTROL WORD REGISTER

(READ/WRITE 04H)

BCST: MEMORY MANAGEMENT 0 (MM0)0(LSB) BCST: MEMORY MANAGEMENT 1 (MM1)1BCST:MEMORY MANAGEMENT 2 (MM2)2

TX: MEMORY MANAGEMENT 1 (MM1)

BCST: CIRC BUF INT3BCST: EOM INT4RX: MEMORY MANAGEMENT 0 (MM0)5RX: MEMORY MANAGEMENT 1 (MM1)6RX: MEMORY MANAGEMENT 2 (MM2)7RX: CIRC BUF INT8RX: EOM INT9TX: MEMORY MANAGEMENT 0 (MM0)10

TX: MEMORY MANAGEMENT 2 (MM2)12 TX: CIRC BUF INT13 TX: EOM INT14 RX: DOUBLE BUFFER ENABLE

15(MSB) DESCRIPTIONBIT

TABLE 9. RT SUBADDRESS CONTROL WORD

(READ/WRITE 04H)

TIME TAG 00(LSB)

••

TIME TAG 15

15(MSB)

DESCRIPTIONBIT

TABLE 10. TIMETAG REGISTER

(READ/WRITE 05H)

END OF MESSAGE0(LSB)

BC STATUS SET / RT MODE CODE /

MT PATTERN TRIGGER

FORMAT ERROR2

MT COMMAND STACK ROLLOVER

BC END OF FRAME3

RT SUBADDRESS CONTROL WORD EOM4

RT CIRCULAR BUFFER ROLLOVER5

TIME TAG ROLLOVER6

RT ADDRESS PARITY ERROR7

BC RETRY8

HANDSHAKE FAIL9

MT DATA STACK ROLLOVER10

BC/RT COMMAND STACK ROLLOVER12

TRANSMITTER TIMEOUT13

RAM PARITY ERROR14

MASTER INTERRUPT

15(MSB)

DESCRIPTIONBIT

TABLE 11. INTERRUPT STATUS REGISTER #1

(READ 06H)

ENHANCED MODE CODE HANDLING0(LSB)

1553A MODE CODES ENABLE1

RTFAIL / RTFLAG WRAP ENABLE2

MT COMMAND STACK SIZE 0

BUSY RX TRANSFER DISABLE3

ILLEGAL RX TRANSFER DISABLE4

ALTERNATE STATUS WORD ENABLE5

OVERRIDE MODE T/R ERROR6

ILLEGALIZATION DISABLED7

MT DATA STACk SIZE 08

MT DATA STACk SIZE 19

MT DATA STACk SIZE 210

MT COMMAND STACK SIZE 112

BC/RT COMMAND STACK SIZE 013

BC/RT COMMAND STACK SIZE 114

ENHANCED MODE ENABLE

15(MSB)

DESCRIPTIONBIT

TABLE 12. CONFIGURATION REGISTER #3

(READ/WRITE 07H)

RT ADDRESS PARITY0(LSB)

RT ADDRESS 01

RT ADDRESS 12

EXPANDED CROSSING ENABLED

RT ADDRESS 23

RT ADDRESS 34

RT ADDRESS 45

RT ADDRESS LATCH/TRANSPARENT6

BROADCAST DISABLED7

GAP CHECK ENABLED8

RESPONSE TIMEOUT SELECT 09

RESPONSE TIMEOUT SELECT 110

EXTERNAL TX INHIBIT B12

EXTERNAL TX INHIBIT A13

SINGLE-ENDED SELECT14

12 / 16 MHZ CLOCK SELECT15(MSB)

DESCRIPTIONBIT

TABLE 14. CONFIGURATION REGISTER #5

(READ/WRITE 09H)

RT / MONITOR DATA STACK ADDRESS 00(LSB) •• •• •• RT / MONITOR DATA STACK ADDRESS 15

15(MSB) DESCRIPTIONBIT

TABLE 15. RT / MONITOR DATA STACK ADDRESS REGISTER

(READ/WRITE 0AH)

TEST MODE 00(LSB)

TEST MODE 11

TEST MODE 22

BROADCAST MASK ENA/XOR

LATCH RT ADRRESS WITH CONFIG #53

MT TAG GAP OPTION4

VALID BUSY/NO DATA5

VALID M.E./NO DATA6

2ND RETRY ALT/SAME BUS7

1ST RETRY ALT/SAME BUS8

RETRY IF STATUS SET9

RETRY IF -A AND M.E.10

EXPANDED BC CONTROL WORD ENABLE12

MODE COMMAND OVERRIDE BUSY13

INHIBIT BIT WORD IF BUSY14

EXTERNAL BIT WORD ENABLE

15(MSB)

DESCRIPTIONBIT

TABLE 13. CONFIGURATION REGISTER #4

(READ/WRITE 08H)

BC FRAME TIME REMAINING 00(LSB)

••

BC FRAME TIME REMAINING 15

15(MSB)

DESCRIPTIONBIT

TABLE 16. BC FRAME TIME REMAINING REGISTER

(READ/WRITE 0BH)

Note: resolution = 100 µs per LSB

BC MESSAGE TIME REMAINING 00(LSB)

••

BC MESSAGE TIME REMAINING 15

15(MSB)

DESCRIPTIONBIT

TABLE 17. BC MESSAGE TIME REMAINING REGISTER

(READ/WRITE 0CH)

Note: resolution = 1 µs per LSB

BIT 0

0(LSB)

••

BIT 15

15(MSB)

DESCRIPTIONBIT

TABLE 18. BC FRAME TIME / RT LAST COMMAND /

MT TRIGGER REGISTER (READ/WRITE 0DH)

TABLE 19. RT STATUS WORD REGISTER

(READ/WRITE 0EH)

BIT DESCRIPTION

15(MSB) LOGIC “0”

12 LOGIC “0”

14 LOGIC “0”

13 LOGIC “0”

10 MESSAGE ERROR

9INSTRUMENTATION

8SERVICE REQUEST

7 RESERVED

6 RESERVED

5 RESERVED

4BROADCAST COMMAND RECEIVED

3 BUSY

LOGIC “0”

2SUBSYSTEM FLAG

1DYNAMIC BUS CONTROL ACCEPT

0(LSB) TERMINAL FLAG

COMMAND WORD CONTENTS ERROR0(LSB)

RT-to-RT 2ND COMMAND WORD ERROR1

RT-to-RT NO RESPONSE ERROR2

TRANSMITTER SHUTDOWN B

RT-to-RT GAP / SYNCH / ADDRESS ERROR3

PARITY / MANCHESTER ERROR RECEIVED4

INCORRECT SYNC RECEIVED5

LOW WORD COUNT6

HIGH WORD COUNT7

BIT TEST FAIL8

TERMINAL FLAG INHIBITED9

TRANSMITTER SHUTDOWN A10

HANDSHAKE FAILURE12

LOOP TEST FAILURE A13

LOOP TEST FAILURE B14

TRANSMITTER TIMEOUT

15(MSB)

DESCRIPTIONBIT

TABLE 20. RT BIT WORD REGISTER

(WRITE 0FH)

CLOCK SELECT 00(LSB)

CLOCK SELECT 11

64-WORD REGISTER SPACE2

GLOBAL CIRCULAR BUFFER SIZE 2

RESERVED3

ENHANCED MESSAGE MONITOR4

RT ADDRESS SOURCE5

INTERRUPT STATUS QUEUE ENABLE6

DISABLE MESSAGES TO INTERRUPT STATUS QUEUE7

DISABLE MESSAGES TO INTERRUPT STATUS QUEUE8

GLOBAL CIRCULAR BUFFER SIZE 09

GLOBAL CIRCULAR BUFFER SIZE 110

GLOBAL CIRCULAR BUFFER ENABLE12

COMMAND STACK POINTER INCREMENT ON EOM

(RT, MT)

ENHANCED CPU ACCESS14 ENHANCED BUS CONTROLLER

15(MSB)

DESCRIPTIONBIT

TABLE 21. CONFIGURATION REGISTER #6

(READ/WRITE 18H)

MODE CODE RESET / INCMD SELECT

0(LSB) ENHANCED BC WATCHDOG TIMER ENABLED

ENHANCED TIMETAG SYNCHRONIZE

MEMORY MANAGEMENT BASE ADDRESS 11

1553B RESPONSE TIME3RT HALT ENABLE

RESERVED5

RESERVED6

RESERVED7

RESERVED8

RESERVED9

MEMORY MANAGEMENT BASE ADDRESS 1010

MEMORY MANAGEMENT BASE ADDRESS 1212

MEMORY MANAGEMENT BASE ADDRESS 1313

MEMORY MANAGEMENT BASE ADDRESS 1414

MEMORY MANAGEMENT BASE ADDRESS 15

15(MSB)

DESCRIPTIONBIT

TABLE 22. CONFIGURATION REGISTER #7

(READ/WRITE 19H)

EQUAL FLAG / GENERAL PURPOSE FLAG 10(LSB)

LESS THAN FLAG / GENERAL PURPOSE FLAG 11

GENERAL PURPOSE FLAG 22

MESSAGE STATUS SET

GENERAL PURPOSE FLAG 33

GENERAL PURPOSE FLAG 44

GENERAL PURPOSE FLAG 55

GENERAL PURPOSE FLAG 66

GENERAL PURPOSE FLAG 77

NO RESPONSE8

FORMAT ERROR9

GOOD BLOCK TRANSFER10

BAD MESSAGE12

RETRY 013

RETRY 114

ALWAYS15(MSB)

DESCRIPTIONBIT

TABLE 23. BC CONDITION REGISTER

(READ 1BH)

SET GENERAL PURPOSE FLAG 00(LSB)

SET GENERAL PURPOSE FLAG 11

SET GENERAL PURPOSE FLAG 22

CLEAR GENERAL PURPOSE FLAG 3

SET GENERAL PURPOSE FLAG 33

SET GENERAL PURPOSE FLAG 44

SET GENERAL PURPOSE FLAG 55

SET GENERAL PURPOSE FLAG 66

SET GENERAL PURPOSE FLAG 77

CLEAR GENERAL PURPOSE FLAG 08

CLEAR GENERAL PURPOSE FLAG 19

CLEAR GENERAL PURPOSE FLAG 210

CLEAR GENERAL PURPOSE FLAG 412

CLEAR GENERAL PURPOSE FLAG 513

CLEAR GENERAL PURPOSE FLAG 614

CLEAR GENERAL PURPOSE FLAG 715(MSB)

DESCRIPTIONBIT

TABLE 24. BC GENERAL PURPOSE FLAG REGISTER

(WRITE 1BH)

LOGIC ”0”0(LSB)

LOGIC ”0”1

LOGIC ”0”2

LOGIC ”1”

LOGIC ”0”3

LOGIC ”0”4

RAM BUILT-IN TEST IN-PASSED5

RAM BUILT-IN TEST IN-PROGRESS6

RAM BUILT-IN TEST COMPLETE7

LOGIC ”0”8

LOGIC ”0”9

LOGIC ”0”10

PROTOCOL BUILT-IN TEST ABORT12

PROTOCOL BUILT-IN TEST PASSED13

PROTOCOL BUILT-IN TEST IN-PROGRESS14

PROTOCOL BUILT-IN TEST COMPLETE15(MSB)

DESCRIPTIONBIT

TABLE 25. BIT TEST STATUS FLAG REGISTER

(READ 1CH)

NOT USED0(LSB)

BIT TEST COMPLETE1

ENHANCED BC IRQ02

CALL STACK POINTER REGISTER ERROR

ENHANCED BC IRQ13

ENHANCED BC IRQ24

ENHANCED BC IRQ35

MONITOR DATA STACK 50% ROLLOVER6

MONITOR COMMAND STACK 50% ROLLOVER7

RT CIRCULAR BUFFER 50% ROLLOVER8

RT COMMAND STACK 50% ROLLOVER9

BC TRAP OP CODE10

GENERAL PURPOSE QUEUE /

INTERRUPT STATUS QUEUE ROLLOVER

ILLEGAL COMMAND13

BC OP CODE PARITY ERROR14

NOT USED15(MSB)

DESCRIPTIONBIT

TABLE 26. INTERRUPT MASK REGISTER #2

(READ/WRITE 1DH)

INTERRUPT CHAIN BIT0(LSB)

BIT TEST COMPLETE1

ENHANCED BC IRQ02

CALL STACK POINTER REGISTER ERROR

ENHANCED BC IRQ13

ENHANCED BC IRQ24

ENHANCED BC IRQ35

MONITOR DATA STACK 50% ROLLOVER6

MONITOR DATA STACK 50% ROLLOVER7

RT CIRCULAR BUFFER 50% ROLLOVER8

RT COMMAND STACK 50% ROLLOVER9

BC TRAP OP CODE10

GENERAL PURPOSE QUEUE /

INTERRUPT STATUS QUEUE ROLLOVER

ILLEGAL COMMAND13

BC OP CODE PARITY ERROR14

MASTER INTERRUPT15(MSB)

DESCRIPTIONBIT

TABLE 27. INTERRUPT STATUS REGISTER #2

(READ 1EH)

QUEUE POINTER ADDRESS 00(LSB)

QUEUE POINTER ADDRESS 11

QUEUE POINTER ADDRESS 22

QUEUE POINTER BASE ADDRESS 11

QUEUE POINTER ADDRESS 33

QUEUE POINTER ADDRESS 44

QUEUE POINTER ADDRESS 55

QUEUE POINTER BASE ADDRESS 66

QUEUE POINTER BASE ADDRESS 77

QUEUE POINTER BASE ADDRESS 88

QUEUE POINTER BASE ADDRESS 99

QUEUE POINTER BASE ADDRESS 1010

QUEUE POINTER BASE ADDRESS 1212

QUEUE POINTER BASE ADDRESS 1313

QUEUE POINTER BASE ADDRESS 1414

QUEUE POINTER BASE ADDRESS 1515(MSB)

DESCRIPTIONBIT

TABLE 28. BC GENERAL PURPOSE QUEUE POINTER REGISTER

RT, MT INTERRUPT STATUS QUEUE POINTER REGISTER

(READ/WRITE1FH)

COMMAND WORD CONTENTS ERROR0(LSB)

RT-to-RT 2ND COMMAND ERROR1

RT-to-RT GAP / SYNC / ADDRESS ERROR2

RT-to-RT FORMAT

INVALID WORD3

INCORRECT DATA SYNC4

WORD COUNT ERROR5

ILLEGAL COMMAND WORD6

DATA STACK ROLLOVER7

LOOP TEST FAIL8

NO RESPONSE TIMEOUT9

FORMAT ERROR10

ERROR FLAG12

CHANNEL B/A13

SOM14

EOM

15(MSB)

DESCRIPTIONBIT

TABLE 30. RT MODE BLOCK STATUS WORD

GAP TIME (LSB)

MODE_CODE0(LSB)

CONTIGUOUS DATA / GAP1

CHANNEL B/A2

COMMAND / DATA3

ERROR4

BROADCAST5

THIS RT6

WORD FLAG7

••

GAP TIME (MSB)15(MSB)

DESCRIPTIONBIT

TABLE 32. WORD MONITOR IDENTIFICATION WORD

DATA WORD COUNT / MODE CODE BIT 00(LSB)

DATA WORD COUNT / MODE CODE BIT 11

DATA WORD COUNT / MODE CODE BIT 22

REMOTE TERMINAL ADDRESS BIT 0

DATA WORD COUNT / MODE CODE BIT 33

DATA WORD COUNT / MODE CODE BIT 44

SUBADDRESS / MODE BIT 05

SUBADDRESS / MODE BIT 16

SUBADDRESS / MODE BIT 27

SUBADDRESS / MODE BIT 38

SUBADDRESS / MODE BIT 49

TRANSMIT / RECEIVE10

REMOTE TERMINAL ADDRESS BIT 112

REMOTE TERMINAL ADDRESS BIT 213

REMOTE TERMINAL ADDRESS BIT 314

REMOTE TERMINAL ADDRESS BIT 415(MSB)

DESCRIPTIONBIT

TABLE 31. 1553 COMMAND WORD

NOTE: TABLES 29 TO 35 ARE NOT REGISTERS, BUT THEY ARE WORDS STORED IN RAM.

INVALID WORD

0(LSB)

INCORRECT SYNC TYPE1

WORD COUNT ERROR2

STATUS SET

WRONG STATUS ADDRESS / NO GAP3

GOOD DATA BLOCK TRANSFER4

RETRY COUNT 05

RETRY COUNT 16

MASKED STATUS SET7

LOOP TEST FAIL8

NO RESPONSE TIMEOUT9

FORMAT ERROR10

ERROR FLAG12

CHANNEL B/A13

SOM14

EOM

15(MSB)

DESCRIPTIONBIT

TABLE 29. BC MODE BLOCK STATUS WORD

COMMAND WORD CONTENTS ERROR0(LSB)

RT-to-RT 2ND COMMAND ERROR1

RT-to-RT GAP / SYNC / ADDRESS ERROR2

RT-to-RT TRANSFER

INVALID WORD3

INCORRECT SYNC4

WORD COUNT ERROR5

RESERVED6

DATA STACK ROLLOVER7

GOOD DATA BLOCK TRANSFER8

NO RESPONSE TIMEOUT9

FORMAT ERROR10

ERROR FLAG12

CHANNEL B/A13

SOM14

EOM

15(MSB)

DESCRIPTIONBIT

TABLE 33. MESSAGE MONITOR MODE BLOCK STATUS WORD

TERMINAL FLAG0(LSB)

DYNAMIC BUS CONTROL ACCEPTANCE1

SUBSYSTEM FLAG2

REMOTE TERMINAL ADDRESS BIT 0

BUSY3

BROADCAST COMMAND RECEIVED4

RESERVED5

RESERVED6

RESERVED7

SERVICE REQUEST8

INSTRUMENTATION9

MESSAGE ERROR10

REMOTE TERMINAL ADDRESS BIT 112

REMOTE TERMINAL ADDRESS BIT 213

REMOTE TERMINAL ADDRESS BIT 314

REMOTE TERMINAL ADDRESS BIT 415(MSB)

DESCRIPTIONBIT

TABLE 35. 1553B STATUS WORD

NON-TEST REGISTER FUNCTION SUMMARY

A summary of the Enhanced Mini-ACE's 24 non-test registers

follows.

Interrupt Mask Registers #1 and #2 are used to enable and

disable interrupt requests for various events and conditions.

Configuration Registers #1 and #2 are used to select the

Enhanced Mini-ACE's mode of operation, and for software con-

trol of RT Status Word bits, Active Memory Area, BC Stop-On-

Error, RT Memory Management mode selection, and control of

the Time Tag operation.

Start/Reset Register is used for "command" type functions such

as software reset, BC/MT Start, Interrupt reset, Time Tag Reset,

Time Tag Register Test, Initiate protocol self-test, Initiate RAM

self-test, Clear self-test register, and Clear RT Halt. The

Start/Reset Register also includes provisions for stopping the BC

in its auto-repeat mode, either at the end of the current message

or at the end of the current BC frame.

BC/RT Command Stack Register allows the host CPU to

determine the pointer location for the current or most recent

message.

BC Instruction List Pointer Register may be read to determine

the current location of the Instruction List Pointer for the

Enhanced BC mode.

BC Control Word/RT Subaddress Control Word Register: In

BC mode, allows host access to the current word or most recent

BC Control Word. The BC Control Word contains bits that select

the active bus and message format, enable off-line self-test,

“1” FOR MESSAGE INTERRUPT EVENT

”0” FOR NON-MESSAGE INTERRUPT EVENT

END-OF-MESSAGE (EOM) RAM PARITY ERROR1

SUBADDRESS CONTROL

WORD EOM PROTOCOL SELF-TEST

COMPLETE

RT CIRCULAR BUFFER 50%

ROLLOVER NOT USED

MODE CODE INTERRUPT RT ADDRESS PARITY

ERROR

FORMAT ERROR TIME TAG ROLLOVER4HANDSHAKE FAIL NOT USED5

RT COMMAND (DESCRIPTOR)

STACK ROLLOVER NOT USED6

RT COMMAND (DESCRIPTOR)

STACK 50% ROLLOVER NOT USED7

MONITOR COMMAND

(DESCRIPTOR) STACK

ROLLOVER NOT USED8

MONITOR COMMAND

(DESCRIPTOR) STACK 50%

ROLLOVER NOT USED9

RT CIRCULAR BUFFER

ROLLOVER NOT USED10

MONITOR DATA STACK

ROLLOVER NOT USED12

MONITOR DATA STACK 50%

ROLLOVER NOT USED13

ILLEGAL COMMAND NOT USED14 TRANSMITTER TIMEOUT NOT USED15

DEFINTION FOR MESSAGE

INTERRUPT EVENT

DEFINITION FOR

NON-MESSAGE

INTERRUPT EVENT

BIT

TABLE 34. RT/MONITOR INTERRUPT STATUS WORD

(FOR INTERRUPT STATUS QUEUE)

BC FrameTime/ RT Last Command /MTTriggerWord Register.

In BC mode, this register is used to program the BC frame time,

for use in the frame auto-repeat mode.The resolution of this reg-

ister is 100 µs/LS, with a range up to 6.55 seconds. In RT mode,

this register stores the current (or most previous) 1553

Command Word processed by the Enhanced Mini-ACE RT. In

the Word Monitor mode, this register is used to specify a 16-bit

Trigger (Command) Word. The Trigger Word may be used to

start or stop the monitor, or to generate interrupts.

BC Initial Instruction List Pointer Register enables the host to

assign the starting address for the enhanced BC Instruction List.

RT Status Word Register and BIT Word Registers provide

read-only indications of the RT Status and BIT Words.

Test Mode Registers 0-7. These registers are included for fac-

tory test. In normal operation, these registers do not need to be

accessed by the host processor.

Configuration Registers #6 and #7 are used to enable the

Enhanced Mini-ACE features that extend beyond the architec-

ture of the ACE/Mini-ACE (Plus). These include the Enhanced

BC mode; RT Global Circular Buffer (including buffer size); the

RT/MT Interrupt Status Queue, including valid/invalid message

filtering; enabling a software-assigned RT address; clock fre-

quency selection; a base address for the "non-data" portion of

Enhanced Mini-ACE memory; LSB filtering for the Synchronize

(with data) time tag operations; and enabling a watchdog timer

for the Enhanced BC message sequence control engine.

BC Condition Code Register is used to enable the host proces-

sor to read the current value of the Enhanced BC Message

Sequence Control Engine's condition flags.

BC General Purpose Flag Register allows the host processor

to be able to set, clear, or toggle any of the Enhanced BC

Message Sequence Control Engine's General Purpose condition

flags.

BITTest Status Register is used to provide read-only access to

the status of the protocol and RAM built-in self-tests (BIT).

BC General Purpose Queue Pointer provides a means for ini-

tializing the pointer for the General Purpose Queue, for the

Enhanced BC mode.In addition, this register enables the host to

determine the current location of the General Purpose Queue

pointer, which is incremented internally by the Enhanced BC

message sequence control engine.

RT/MT Interrupt Status Queue Pointer Register provides a

means for initializing the pointer for the Interrupt Status Queue,

for RT, MT, and RT/MT modes. In addition, this register enables

the host to determine the current location of the Interrupt Status

Queue pointer, which is incremented by the RT/MT message

processor.

masking of Status Word bits, enable retires and interrupts, and

specify MIL-STD-1553A or -1553B error handling. In RT mode,

this register allows host access to the current or most recent

Subaddress Control Word. The Subaddress Control Word is

used to select the memory management scheme and enable

interrupts for the current message.

TimeTag Register maintains the value of a real-time clock. The

resolution of this register is programmable from among 2, 4, 8,

16, 32, and 64 µs/LSB. The Start-of-Message (SOM) and End-

of-Message (EOM) sequences in BC, RT, and Message Monitor

modes cause a write of the current value of the Time Tag

Interrupt Status Register #1 and #2 allow the host processor

to determine the cause of an interrupt request by means of one

or two read accesses. The interrupt events of the two Interrupt

Status Registers are mapped to correspond to the respective bit

positions in the two Interrupt Mask Registers. Interrupt Status

cate an interrupt event from Interrupt Status Register #1.

Configuration Registers #3, #4, and #5 are used to enable

many of the Enhanced Mini-ACE's advanced features that were

implemented by the prior generation products, the ACE and

Mini-ACE (Plus). For BC, RT, and MT modes, use of the

ENHANCED MODE enables the various read-only bits in

Configuration Register #1. For BC mode, ENHANCED mode

features include the expanded BC Control Word and BC Block

Status Word, additional Stop-On-Error and Stop-On-Status Set

functions, frame auto-repeat, programmable intermessage gap

times, automatic retires, expanded Status Word Masking, and

the capability to generate interrupts following the completion of

any selected message. For RT mode, the enhanced mode fea-

tures include the expanded RT Block Status Word, combined

RT/Selective Message Monitor mode, automatic setting of the

TERMINAL FLAG Status Word bit following a loop test failure;

the double buffering scheme for individual receive (broadcast)

subaddresses, and the alternate (fully software programmable)

RT Status Word. For MT mode, use of the enhanced mode

enables the Selective Message Monitor, the combined

RT/Selective Monitor modes, and the monitor triggering capabil-

ity.

RT/Monitor Data Stack Address Register provides a read-only

indication of the last data word stored for RT or Monitor modes.

BC FrameTime Remaining Register provides a read-only indi-

cation of the time remaining in the current BC frame. In the

enhanced BC mode, this timer may be used for minor or major

frame control, or as a watchdog timer for the BC message

sequence control processor.The resolution of this register is 100

µs/LSB.

BC Time Remaining to Next Message Register provides a

read-only indication of the time remaining before the start of the

next message in a BC frame. In the enhanced BC mode, this

timer may be also be used for the BC message sequence con-

trol processor's Delay (DLY) instruction, or for minor or major

frame control.The resolution of this register is 1 µs/LSB.

BUS CONTROLLER (BC) ARCHITECTURE

The BC functionality for the Enhanced Mini-ACE includes two

separate architectures: (1) the older, non-Enhanced mode,

which provides complete compatibility with the previous ACE

and Mini-ACE (Plus) generation products; and (2) the newer,

Enhanced BC mode.The Enhanced BC mode offers several new

powerful architectural features.These includes the incorporation

of a highly autonomous BC message sequence control engine,

which greatly serves to offload the operation of the host CPU.

The Enhanced BC's message sequence control engine provides

a high degree of flexibility for implementing major and minor

frame scheduling; capabilities for inserting asynchronous mes-

sages in the middle of a frame; to separate 1553 message data

from control/status data for the purpose of implementing double

buffering and performing bulk data transfers; for implementing

message retry schemes, including the capability for automatic

bus channel switchover for failed messages; and for reporting

various conditions to the host processor by means of 4 user-

defined interrupts and a general purpose queue.

In both the non-Enhanced and Enhanced BC modes, the

Enhanced Mini-ACE BC implements all MIL-STD-1553B mes-

sage formats. Message format is programmable on a message-

by-message basis by means the BC Control Word and the

bit of the Command Word for the respective message. The BC

Control Word allows 1553 message format, 1553A/B type RT,

bus channel, self-test, and Status Word masking to be specified

on an individual message basis. In addition, automatic retries

and/or interrupt requests may be enabled or disabled for individ-

ual messages. The BC performs all error checking required by

MIL-STD-1553B. This includes validation of response time, sync

type and sync encoding, Manchester II encoding, parity, bit

count, word count, Status Word RT Address field, and various

R/T

RT-to-RT transfer errors. The Enhanced Mini-ACE BC response

timeout value is programmable with choices of 18, 22, 50, and

130 µs. The longer response timeout values allow for operation

over long buses and/or the use of repeaters.

In its non-Enhanced mode, the Enhanced Mini-ACE may be pro-

grammed to process BC frames of up to 512 messages with no

processor intervention. In the Enhanced BC mode, there is no

explicit limit to the number of messages that may be processed

in a frame.In both modes, it is possible to program for either sin-

gle frame or frame auto-repeat operation. In the auto-repeat

mode, the frame repetition rate may be controlled either inter-

nally, using a programmable BC frame timer, or from an external

trigger input.

ENHANCED BC MODE: MESSAGE SEQUENCE CONTROL

One of the major new architectural features of the Enhanced

Mini-ACE series is its advanced capability for BC message

sequence control. The Enhanced Mini-ACE supports highly

autonomous BC operation, which greatly offloads the operation

of the host processor.

The operation of the Enhanced Mini-ACE's message sequence

control engine is illustrated in FIGURE 2. The BC message

sequence control involves an instruction list pointer register; an

instruction list which contains multiple 2-word entries;a message

control/status stack, which contains multiple 8-word or 10-word

descriptors; and data blocks for individual messages.

The initial value of the instruction list pointer register is initialized

by the host processor (via Register 0D), and is incremented by

the BC message sequence processor (host readable via

FIGURE 2. BC MESSAGE SEQUENCE CONTROL

OP CODE

DATA BLOCK

MESSAGE

CONTROL/STATUS

PARAMETER

(POINTER)

BLOCK

BC INSTRUCTION

LIST

BC INSTRUCTION

LIST POINTER REGISTER

BC CONTROL

WORD

COMMAND WORD

(Rx Command for

RT-to-RT transfer)

DATA BLOCK POINTER

TIME-TO-NEXT MESSAGE

TIME TAG WORD

BLOCK STATUS WORD

LOOPBACK WORD

RT STATUS WORD

2nd (Tx) COMMAND WORD

(for RT-to-RT transfer)

2nd RT STATUS WORD

(for RT-to-RT transfer)

INITIALITIZE BY REGISTER

0D (RD/WR); READ CURRENT

VALUE VIA REGISTER 03

(RD ONLY)

processor fetches the operation referenced by the instruction list

pointer register from the instruction list.

Note that the pointer parameter referencing the first word of a

message's control/status block (the BC Control Word) must con-

tain an address value that is modulo 8. Also, note that if the

message is an RT-to-RT transfer, the pointer parameter must

contain an address value that is modulo 16.

OP CODES

The instruction list pointer register references a pair of words in

the BC instruction list: an op code word, followed by a parameter

word.The format of the op code word, which is illustrated in FIG-

URE 3, includes a 5-bit op code field and a 5-bit condition code

field.The op code identifies the instruction to be executed by the

BC message sequence controller.

Most of the operations are conditional, with execution dependent

on the contents of the condition code field. Bits 3-0 of the condi-

tion code field identifies a particular condition. Bit 4 of the condi-

tion code field identifies the logic sense ("1" or "0") of the select-

ed condition code on which the conditional execution is depen-

dent.TABLE 36 lists all the op codes, along with their respective

mnemonic, code value, parameter, and description. TABLE 37

defines all the condition codes.

Eight of the condition codes (8 through F) are set or cleared as

the result of the most recent message. The other eight are

defined as "General Purpose" condition codes GP0 through

GP7.There are three mechanisms for programming the values of

the General Purpose Condition Code bits: (1) They may be set,

cleared, or toggled by the host processor, by means of the BC

GENERAL PURPOSE FLAG REGISTER; (2) they may be set,

cleared, or toggled by the BC message sequence control

processor, by means of the GP Flag Bits (FLG) instruction; and

(3) GP0 and GP1 only (but none of the others) may be set or

cleared by means of the BC message sequence control proces-

sor's Compare Frame Timer (CFT) or Compare Message Timer

(CMT) instructions.

The host processor also has read-only access to the BC condi-

tion codes by means of the BC CONDITION CODE REGISTER.

Note that four (4) instructions are unconditional. These are

Compare to Frame Timer (CFT), Compare to Message Timer

(CMT), GP Flag Bits (FLG), and Execute and Flip (XQF). For

these instructions, the Condition Code Field is "don't care".That

is, these instructions are always executed, regardless of the

result of the condition code test.

All of the other instructions are conditional.That is, they will only

be executed if the condition code specified by the condition code

field in the op code word tests true. If the condition code field

tests false, the instruction list pointer will skip down to the next

instruction.

As shown in TABLE 36, many of the operations include a single-

word parameter. For an XEQ (execute message) operation, the

parameter is a pointer to the start of the message’s Control /

Status block. For other operations, the parameter may be an

address, a time value, an interrupt pattern, a mechanism to set

or clear general purpose flag bits, or an immediate value. For

several op codes, the parameter is "don't care" (not used).

As described above, some of the op codes will cause the mes-

sage sequence control processor to execute messages. In this

case, the parameter references the first word of a message

Control/Status block. With the exception of RT-to-RT transfer

messages, all message status/control blocks are eight words

long: a block control word, time-to-next-message parameter,

data block pointer, command word, status word, loopback word,

block status word, and time tag word.

In the case of an RT-to-RT transfer message, the size of the mes-

sage control/status block increases to 16 words. However, in this

case, the last six words are not used; the ninth and tenth words

are for the second command word and second status word.

The third word in the message control/status block is a pointer

that references the first word of the message's data word block.

Note that the data word block stores only data words, which are

to be either transmitted or received by the BC. By segregating

data words from command words, status words, and other con-

trol and "housekeeping" functions, this architecture enables the

use of convenient, usable data structures, such as circular

buffers and double buffers.

Other operations support program flow control;i.e., jump and call

capability.The call capability includes maintenance of a call stack

which supports a maximum of four (4) entries; there is also a

return instruction.In the case of a call stack overrun or underrun,

the BC will issue a CALL STACK POINTER REGISTER ERROR

interrupt, if enabled.

Other op codes may be used to delay for a specified time; start

a new BC frame; wait for an external trigger to start a new frame;

do comparisons based on frame time and time-to-next message;

load the time tag or frame time registers; halt; and issue host

interrupts. In the case of host interrupts, the message control

processor passes a 4-bit user-defined interrupt vector to the

host, by means of the Enhanced Mini-ACE's Interrupt Status

The purpose of the FLG instruction is to enable the message

sequence controller to set, clear, or toggle the value(s) of any or

all of the eight general purpose condition flags.

FIGURE 3. BC OP CODE FORMAT

15 1011121314 56789 01234

1 00OpCode Field 11 0 Condition Code Field

The op code parity bit encompasses all sixteen bits of the op

code word. This bit must be programmed for odd parity. If the

message sequence control processor fetches an undefined op

code word, an op code word with even parity, or bits 9-5 of an op

code word do not have a binary pattern of 01010, the message

sequence control processor will immediately halt the BC's oper-

ation. In addition, if enabled, a BC TRAP OP CODE interrupt will

be issued. Also, if enabled, a parity error will result in an OP

CODE PARITY ERROR interrupt.

TABLE 37 describes the Condition Codes.

TABLE 36. BC OPERATIONS FOR MESSAGE SEQUENCE CONTROL

INSTRUCTION MNEMONIC OP CODE

(HEX) PARAMETER CONDITIONAL

UNCONDITIONAL DESCRIPTION

Interrupt

Request

Execute

Message

IRQ

XEQ

0006

0001

Interrupt

Bit Pattern

in 4 LS bits

Message Control /

Status Block

Address

Conditional

Generate an interrupt if the condition flag tests TRUE, otherwise

continue execution at the next OpCode in the instruction list.

The passed parameter (Interrupt Bit Pattern) specifies which of

the ENHANCED BC IRQ bit(s) (bits 5-2) will be set in Interrupt

Status Register #2. Only the four LSBs of the passed parameter

are used. A parameter where the four LSBs are logic "0" will

not generate an interrupt.

Executes the message at the specified Message Control/Status

Block Address if the condition flag tests TRUE, otherwise contin-

ue execution at the next OpCode in the instruction list.

Compare to

Frame Timer

Halt

Jump

CFT

HLT

JMP

000A

0007

0002

Delay Time Value

(Resolution

= 100µS / LSB)

Not Used

(Don’t Care)

Instruction List

Addrss

Unconditional

Conditional

Compare Time Value to Frame Time Counter and set or clear

the LT and EQ flag based on the results of the compare.

Stop execution of the Message Sequence Control Program until

a new BC Start is issued by the host if the condition flag tests

TRUE, otherwise continue execution at the next OpCode in the

instruction list.

Jump to the OpCode specified in the Instruction List if the condi-

tion flag tests TRUE, otherwise continue execution at the next

OpCode in the instruction list.

Compare to

Message

Timer

Delay

Subroutine

Call

CMT

DLY

CAL

000B

0008

0003

Delay Time Value

(Resolution

= 1µS / LSB)

Delay Time Value

(Resolution = 1µS)

Instruction List

Addrss

Unconditional

Conditional

Compare Time Value to Message Time Counter and set or clear

the LT and EQ flag based on the results of the compare.

Delay the time specified by the Time parameter before executing

the next OpCode if the condition flag tests TRUE, otherwise

continue execution at the next OpCode without delay. The delay

generated will use the Time to Next Message Timer.

Jump to the OpCode specified by the Instruction List Address

and push the Address of the Next OpCode on the Call Stack if

the condition flag test TRUE, otherwise continue execution at

the next OpCode in the instruction list. Note that the maximum

depth of the subroutine call stack is four.

GP Flag Bits

Wait Until

Frame Timer

Subroutine

Retrn

FLG

WFT

RTN

000C

0009

0004

Used to set,

clear, or toggle GP

(General Purpose)

Flag bits

(See description)

Not Used

(Don’t Care)

Not Used

(Don’t Care)

Unconditional

Conditional

Used to set, toggle, or clear any or all of the eight general pur-

pose flags.The table below illustrates the use of the GP Flag

Bits instruction for the case of GP0 (General Purpose Flag 0).

Bits 1 and 9 of the parameter byte affect flag GP1, bits 2 and 10

effect GP2, etc., according to the following rules:

Wait until Frame Time counter is equal to Zero before continuing

execution of the Message Sequence Control Program if the

condition flag tests TRUE, otherwise continue execution at the

next OpCode without delay.

Return to the OpCode popped off the Call Stack if the condition

flag tests TRUE, otherwise continue execution at the next

OpCode in the instruction list.

Bit 8

Bit 0 Effect on GP0

No Change

Set Flag

Clear Flag

Toggle Flag

Push Block

Status Word PBS 0011 Not Used

(Don't Care) Conditional Push the Block Status Word for the most recent message on

the General Purpose Queue if the condition flag tests TRUE,

otherwise continue execution at the next OpCode in the

instruction list.

TABLE 36. BC OPERATIONS FOR MESSAGE SEQUENCE CONTROL (Cont’d)

INSTRUCTION MNEMONIC OP CODE

(HEX) PARAMETER DESCRIPTION

Load Time Tag

Counter LTT 000D Time Value.

Resolution

(µs/LSB) is

defined by bits 9,

8, and 7 of

Configuration

Conditional Load Time Tag Counter with Time Value if the condition flag

tests TRUE, otherwise continue execution at the next

OpCode in the instruction list.

Load Frame

TimerLoad

Frame

LFT 000E Time Value (reso-

lution = 100

µs/LSB)

Conditional Load Frame Timer Register with the Time Value parameter

if the condition flag tests TRUE, otherwise continue execu-

tion at the next OpCode in the instruction list.

Start Frame

Timer SFT 000F Not Used

(Don't Care) Conditional Start Frame Time Counter with Time Value in Time Frame

execution at the next OpCode in the instruction list.

Push Time Tag

(Don't Care) Conditional Push the value of the Time Tag Register on the General

Purpose Queue if the condition flag tests TRUE, otherwise

continue execution at the next OpCode in the instruction

list.

Push

Immediate

Value

PSI 0012 Immediate Value Conditional Push Immediate data on the General Purpose Queue if the

condition flag tests TRUE, otherwise continue execution at

the next OpCode in the instruction list.

Push Indirect PSM 0013 Memory

Address Conditional Push the data stored at the specified memory location on

the General Purpose Queue if the condition flag tests TRUE,

otherwise continue execution at the next OpCode in the

instruction list.

Wait for

External

Trigger

WTG 0014 Not Used

(Don't Care) Conditional Wait for a logic "0"-to-logic "1" transition on the EXT_TRIG

input signal before proceeding to the next OpCode in the

instruction list if the condition flag tests TRUE, otherwise

continue execution at the next OpCode without delay

Execute and

Flip XQF 0015 Message

Control /

Status Block

Address

Unconditional Execute (unconditionally) the message referenced by the

Message Control/Status Block Address. Following the pro-

cessing of this message, if the condition flag tests TRUE,

the BC will toggle bit 4 in the Message Control/Status Block

Address, and store the new Message Block Address as the

updated value of the parameter following the XQF instruc-

tion code. As a result, the next time that this line in the

instruction list is executed, the Message Control/Status

Block at the updated address (old address XOR 0010h),

rather than the old address, will be processed. If the condi-

tion flag tests FALSE, the value of the Message

Control/Status Block Address parameter will not change.

CONDITIONAL

UNCONDITIONAL

TABLE 37. CONDITION CODES

BIT

CODE

LT/GP0

EQ/GP1

RETRY0

RETRY1

RETRY0

RETRY01

GP2

GP3

GP4

GP5

GP6

GP7

NORESP

GD BLK

XFER

NAME

(BIT4=0)

These two bits reflect the retry status of the most recent message. The number of times that the mes-

sage was retried is delineated by these two bits as shown below:

RETRY COUNT 1 RETRY COUNT 0 Number of

(bit 14) (bit 13) Message Retries

000

011

1 0 N/A

112

FUNCTIONAL DESCRIPTION

INVERSE

(BIT4=1)

GT/GP0

NE/GP1

ALWAYS

Less Than Flag set or cleared after CFT or CMT operation. Also, General Purpose Flag 0 may be set or

cleared by a FLG operation.

NEVERF

GP2

GP3

GP4

GP5

GP6

GP7

RESP

Equal Flag set or cleared after CFT or CMT operation. Also, General Purpose Flag 1 may also be set or

cleared by a FLG operation.

GD BLK

XFER

BAD

MESSAGE GOOD

MESSAGE

The ALWAYS bit should be set to designate an instruction as unconditional. The inverse (NEVER) bit

can be used to implement a NOP instruction.

CBAD MESSAGE indicates either a format error, loop test fail, or no response error for the most recent

message. Note that a "Status Set" condition has no effect on the "BAD MESSAGE/GOOD MESSAGE"

condition code.

FMT ERR FMT ERR9FMT ERR indicates that the received portion of the most recent message contained one or more viola-

tions of the 1553 message validation criteria (sync, encoding, parity, bit count, word count, etc.), or the

RT's status word received from a responding RT contained an incorrect RT address field.

MASKED

STATUS

BIT

MASKED

STATUS

BIT

General Purpose Flags may be set, cleared, or toggled by a FLG operation.The host processor can

set, clear, or toggle these flags in the same way as the FLG instruction by means of the BC GENERAL

PURPOSE FLAG REGISTER.

Indicates that one or both of the following conditions have occurred for the most recent message: (1) If

one (or more) of the Status Mask bits (14 through 9) in the BC Control Word is logic "0" and the corre-

sponding bit(s) is (are) set (logic "1") in the received RT Status Word. In the case of the RESERVED

BITS MASK (bit 9) set to logic "0," any or all of the 3 Reserved Status Word bits being set will result in

a MASKED STATUS SET condition; and/or (2) If BROADCAST MASK ENABLED/XOR (bit 11 of

Configuration Register #4) is logic "1" and the MASK BROADCAST bit of the message's BC Control

Word is logic "0" and the BROADCAST COMMAND RECEIVED bit in the received RT Status Word is

logic "1.".

NORESP indicates that an RT has either not responded or has responded later than the BC No

Response Timeout time. The Enhanced Mini-ACE's No Response Timeout Time is defined per

MIL-STD-1553B as the time from the mid-bit crossing of the parity bit of the last word transmitted by the

BC to the mid-sync crossing of the RT Status Word.The value of the No Response Timeout value is

programmable from among the nominal values 18.5, 22.5, 50.5, and 130 µs (±1 µs) by means of bits 10

and 9 of Configuration Register #5.

AFor the most recent message, GD BLK XFER will be set to logic "1" following completion of a valid

(error-free) RT-to-BC transfer, RT-to-RT transfer, or transmit mode code with data message.This bit is

set to logic "0" following an invalid message. GOOD DATA BLOCK TRANSFER is always logic "0" fol-

lowing a BC-to-RT transfer, a mode code with data, or a mode code without data. The Loop Test has

no effect on GOOD DATA BLOCK TRANSFER. GOOD DATA BLOCK TRANSFER may be used to

determine if the transmitting portion of an RT-to-RT transfer was error free.

BC MESSAGE SEQUENCE CONTROL

The BC Enhanced Mini-ACE BC message sequence control

capability enables a high degree of offloading of the host proces-

sor. This includes using the various timing functions to enable

autonomous structuring of major and minor frames. In addition,

by implementing conditional jumps and subroutine calls, the

message sequence control processor greatly simplifies the

insertion of asynchronous, or "out-of-band" messages.

Execute and Flip Operation. The Enhanced Mini-ACE BC's

XQF, or "Execute and Flip" operation, provides some unique

capabilities.Following execution of this unconditional instruction,

if the condition code tests TRUE, the BC will modify the value of

the current XQF instruction's pointer parameter by toggling bit 4

of the pointer.That is, if the selected condition flag tests true, the

value of the parameter will be updated to the value = old

address XOR 0010h. As a result, the next time that this line in

the instruction list is executed, the Message Control/Status Block

at the updated address (old address XOR 0010h) will be

processed, rather than the one at the old address.The operation

of the XQF instruction is illustrated in FIGURE 4.

There are multiple ways of utilizing the "execute and flip" instruc-

tion. One is to facilitate the implementation of a double buffering

data scheme for individual messages. This allows the message

sequence control processor to "ping-pong" between a pair of

data buffers for a particular message. By so doing, the host

processor can access one of the two DataWord blocks, while the

BC reads or writes the alternate Data Word block.

A second application of the "execute and flip" capability is in con-

junction with message retries. This allows the BC to not only

switch buses when retrying a failed message, but to automati-

cally switch buses permanently for all future times that the same

message is to be processed. This not only provides a high

degree of autonomy from the host CPU, but saves BC band-

width, by eliminating the need for future attempts to process

messages on an RT's failed channel.

XQF

POINTER XX00h

(part of) BC INSTRUCTION LIST MESSAGE

CONTROL/STATUS

BLOCK 0

DATA BLOCK 0

XX00h

MESSAGE

CONTROL/STATUS

BLOCK 1

DATA BLOCK 1

POINTER

FIGURE 4. EXECUTE and FLIP (XQF) OPERATION

GENERAL PURPOSE QUEUE

General Purpose Queue. The Enhanced Mini-ACE BC allows

for the creation of a general purpose queue. This data structure

provides a means for the message sequence processor to con-

vey information to the BC host. The BC op code repertoire pro-

vides mechanisms to push various items on this queue. These

include the contents of the Time Tag Register, the Block Status

Word for the most recent message, an immediate data value, or

the contents of a specified memory address.

FIGURE 5 illustrates the operation of the BC General Purpose

Queue. Note that the BC General Purpose Queue Pointer

64); that is, the location following the last location written by the

BC message sequence control engine.

If enabled, a BC GENERAL PURPOSE QUEUE ROLLOVER

interrupt will be issued when the value of the queue pointer

address rolls over at a 64-word boundary.The rollover will always

occur at a modulo 64 address.

LAST LOCATION

BC GENERAL

PURPOSE QUEUE

(64 Locations)

BC GENERAL

PURPOSE QUEUE

POINTER

FIGURE 5. BC GENERAL PURPOSE QUEUE

REMOTE TERMINAL (RT) ARCHITECTURE

The Enhanced Mini-ACE's RT architecture builds upon that of the

ACE and Mini-ACE. The Enhanced Mini-ACE provides multipro-

tocol support, with full compliance to all of the commonly used

data bus standards, including MIL-STD-1553A, MIL-STD-1553B

Notice 2, STANAG 3838, General Dynamics 16PP303, and

McAirA3818, A5232, and A5690.For the Enhanced Mini-ACE RT

mode, there is programmable flexibility enabling the RT to be con-

figured to fulfill any set of system requirements.This includes the

capability to meet the MIL-STD-1553A response time require-

ment of 2 to 5 µs, and multiple options for mode code subad-

dresses, mode codes, RT status word, and RT BIT word.

The Enhanced Mini-ACE RT protocol design implements all of the

MIL-STD-1553B message formats and dual redundant mode

codes. The design has passed validation testing for MIL-STD-

1553B compliance. The Enhanced Mini-ACE RT performs com-

prehensive error checking including word and format validation,

and checks for various RT-to-RT transfer errors. One of the main

features of the Enhanced Mini-ACE RT is its choice of memory

management options. These include single buffering by subad-

dress, double buffering for individual receive subaddresses, cir-

cular buffering by individual subaddresses, and global circular

buffering for multiple (or all) subaddresses.

Other features of the Enhanced Mini-ACE RT include a set of

interrupt conditions, an flexible status queue with filtering based

on valid and/or invalid messages, flexible command illegalization,

programmable busy by subaddress, multiple options on time tag-

ging, and an "auto-boot" feature which allows the RT to initialize

as an online RT with the busy bit set following power turn-on.

RT MEMORY ORGANIZATION

TABLE 38 illustrates a typical memory map for an Enhanced Mini-

ACE RT with 4K RAM.The two Stack Pointers reside in fixed loca-

tions in the shared RAM address space: address 0100 (hex) for

the Area A Stack Pointer and address 0104 for the Area B Stack

Pointer. In addition to the Stack Pointer, there are several other

areas of the shared RAM address space that are designated as

fixed locations (all shown in bold).These are for the Area A and

Area B lookup tables, the illegalization lookup table, the busy

lookup table, and the mode code data tables.

The RT lookup tables (referenceTABLE 39) provide a mechanism

for allocating data blocks for individual transmit, receive, or broad-

cast subaddresses. The RT lookup tables include subaddress

control words as well as the individual data block pointers. If com-

mand illegalization is used, address range 0300-03FF is used for

command illegalizing.The descriptor stack RAM area, as well as

the individual data blocks, may be located in any of the non-fixed

areas in the shared RAM address space.

Note that in TABLE 38, there is no area allocated for "Stack B".

This is shown for purpose of simplicity of illustration. Also, note

that in TABLE 38, the allocated area for the RT command stack is

256 words. However, larger stack sizes are possible.That is, the

RT command stack size may be programmed for 256 words (64

messages), 512, 1024, or 2048 words (512 messages) by means

of bits 14 and 13 of Configuration Register 3.

Data Block 1000FE0-0FFF •• •• •

·•Data Block 60420-043F Data Block 50400-041F Command Illegalizing Table0300-03FF

RESERVED

Data Block 1-40280-02FF Data Block 00260-027F (not used)0248-025F Busy Bit Lookup Table0240-0247 Lookup Table B01C0-023F Lookup Table A0140-01BF Mode Code Data0110-013F Mode Code Selective Interrupt Table0108-010F

Global Circular Buffer B Pointer

Stack Pointer B

0105

0104 RESERVED0102-0103 Global Circular Buffer A Pointer

Stack Pointer A

0101

0100 Stack A0000-00FF

DESCRIPTION

ADDRESS

(HEX)

0106-0107

TABLE 38. TYPICAL RT MEMORY MAP (SHOWN FOR 4K RAM)

Subaddress

Control Word

Lookup Pointer

Table

(Optional)

SACW SA0

SACW SA31

0220

023F

01A0

01BF

Broadcast

Lookup Pointer

Table

(Optional)

Bcst SA0

Bcst SA31

0200

021F

0180

019F

Transmit

Lookup Pointer

Table

Tx SA0

Tx SA31

01E0

01FF

0160

017F

Receive

(/Broadcast)

Lookup Pointer

Table

Rx(/Bcst) SA0

Rx(/Bcst) SA31

01C0

01DF

0140

015F

COMMENTDESCRIPTIONAREA BAREA A

TABLE 39. RT LOOK-UP TABLES

RT MEMORY MANAGEMENT

The Enhanced Mini-ACE provides a variety of RT memory man-

agement capabilities.As with the ACE and Mini-ACE, the choice

of memory management scheme is fully programmable on a

transmit/receive/broadcast subaddress basis.

In compliance with MIL-STD-1553B Notice 2, received data from

broadcast messages may be optionally separated from non-

broadcast received data.For each transmit, receive or broadcast

subaddress, either a single-message data block, a double

buffered configuration (two alternating Data Word blocks), or a

variable-sized (128 to 8192 words) subaddress circular buffer

may be allocated for data storage. The memory management

scheme for individual subaddresses is designated by means of

the subaddress control word (reference TABLE 40).

For received data, there is also a global circular buffer mode. In

this configuration, the data words received from multiple (or all)

subaddresses are stored in a common circular buffer structure.

Like the subaddress circular buffer, the size of the global circular

buffer is programmable, with a range of 128 to 8192 data words.

The double buffering feature provides a means for the host

processor to easily access the most recent, complete received

block of valid Data Words for any given subaddress. In addition

to helping ensure data sample consistency, the circular buffer

options provide a means for greatly reducing host processor

overhead for multi-message bulk data transfer applications.

End-of-message interrupts may be enabled either globally (fol-

lowing all messages), following error messages, on a

transmit/receive/broadcast subaddress or mode code basis, or

when a circular buffer reaches its midpoint (50% boundary) or

lower (100%) boundary. A pair of interrupt status registers allow

the host processor to determine the cause of all interrupts by

means of a single read operation.

Subaddress -

specific circular buffer

of specified size.

8192-Word

(for receive and / or broadcast subaddresses only)

Global Circular Buffer:The buffer size is specified by

Configuration Register #6, bits 11-9.The pointer to the global

circular buffer is stored at address 0101 (for Area A) or address

0105 (for Area B)

4096-Word010 1

1024-Word000 1

512-Word110 0

256-Word010 0

128-Word100 0

For Receive or Broadcast:

Double Buffered

For Transmit: Single Message

Single Message

SUBADDRESS CONTROL WORD BITS

MM0

MEMORY MANAGEMENT SUBADDRESS

BUFFER SCHEME DESCRIPTION

MM1

DOUBLE-BUFFERED OR

GLOBAL CIRCULAR BUFFER

(bit 15) MM2

TABLE 40. RT SUBADDRESS CONTROL WORD - MEMORY MANAGEMENT OPTIONS

2048-Word100 1

SINGLE BUFFERED MODE

The operation of the single buffered RT mode is illustrated in

FIGURE 6. In the single buffered mode, the respective lookup

table entry must be written by the host processor. Received data

words are written to, or transmitted data words are read from the

data word block with starting address referenced by the lookup

table pointer. In the single buffered mode, the current lookup

table pointer is not updated by the Enhanced Mini-ACE memory

management logic. Therefore, if a subsequent message is

received for the same subaddress, the same Data Word block

will be overwritten or overread.

SUBADDRESS DOUBLE BUFFERING MODE

The Enhanced Mini-ACE provides a double buffering mechanism

for received data, that may be selected on an individual subad-

dress basis for any or all receive (and/or broadcast) subad-

dresses. This is illustrated in FIGURE 7. It should be noted that

the Subaddress Double Buffering mode is applicable for receive

data only, not for transmit data. Double buffering of transmit

messages may be easily implemented by software techniques.

The purpose of the subaddress double buffering mode is to pro-

vide data sample consistency to the host processor. This is

accomplished by allocating two 32-word data word blocks for

each individual receive (and/or broadcast receive) subaddress.

At any given time, one of the blocks will be designated as the

"active "1553 block while the other will be considered as "inac-

tive".The data words for the next receive command to that sub-

address will be stored in the active block. Following receipt of a

valid message, the Enhanced Mini-ACE will automatically switch

the active and inactive blocks for that subaddress. As a result,

the latest, valid, complete data block is always accessible to the

host processor.

CIRCULAR BUFFER MODE

The operation of the Enhanced Mini-ACE's circular buffer RT

memory management mode is illustrated in FIGURE 8.As in the

single buffered and double buffered modes, the individual lookup

table entries are initially loaded by the host processor. At the

start of each message, the lookup table entry is stored in the

third position of the respective message block descriptor in the

descriptor stack area of RAM. Receive or transmit data words

are transferred to (from) the circular buffer, starting at the loca-

tion referenced by the lookup table pointer.

In general, the location after the last data word written or read

(modulo the circular buffer size) during the message is written to

the respective lookup table location during the end-of-message

sequence.By so doing, data for the next message for the respec-

tive transmit, receive(/broadcast), or broadcast subaddress will

be accessed from the next lower contiguous block of locations in

the circular buffer.

For the case of a receive (or broadcast receive) message with a

data word error, there is an option such that the lookup table

pointer will only be updated following receipt of a valid message.

That is, the pointer will not be updated following receipt of a

message with an error in a data word. This allows failed mes-

sages in a bulk data transfer to be retried without disrupting the

circular buffer data structure, and without intervention by the

RT's host processor.

FIGURE 6. RT SINGLE BUFFERED MODE

DATA

BLOCKS

DATA BLOCK

BLOCK STATUS WORD

TIME TAG WORD

DATA BLOCK POINTER

RECEIVED COMMAND

WORD

DESCRIPTOR

STACKS

LOOK-UP

TABLE ADDR

LOOK-UP TABLE

(DATA BLOCK ADDR)

15 13 0

CURRENT

AREA B/A

CONFIGURATION

POINTERS

(See note)

Note: Lookup table is not used for mode commands when enchanced mode codes are enabled.

FIGURE 7. RT DOUBLE BUFFERED MODE

15 13 0

BLOCK STATUS WORD

TIME TAG WORD

DATA BLOCK POINTER

RECEIVED COMMAND

WORD

CONFIGURATION

POINTERS DESCRIPTOR

STACK

CURRENT

AREA B/A

DATA

BLOCKS

DATA

BLOCK 1

DATA

BLOCK 0

X..X 0 YYYYY

X..X 1 YYYYY

RECEIVE DOUBLE

BUFFER ENABLE

SUBADDRESS

CONTROL WORD

MSB

DATA BLOCK POINTER

LOOK-UP

TABLES

FIGURE 8. RT CIRCULAR BUFFERED MODE

CIRCULAR

BUFFER

ROLLOVER

15 13 0

RECEIVED

(TRANSMITTED)

MESSAGE

DATA

(NEXT LOCATION)

128,

256

8192

WORDS

POINTER TO

CURRENT

DATA BLOCK

POINTER TO

NEXT DATA

BLOCK

LOOK-UP TABLE

ENTRY

CIRCULAR

DATA

BUFFER

LOOK-UP TABLES

LOOK-UP

TABLE

ADDRESS

BLOCK STATUS WORD

TIME TAG WORD

DATA BLOCK POINTER

RECEIVED COMMAND

WORD

CONFIGURATION

POINTERS DESCRIPTOR

STACK

CURRENT

AREA B/A

1. TX/RS/BCST_SA look-up table entry is updated following valid receive (broadcast) message

or following completion of transit message

Notes:

2. For the Global Circular Buffer Mode, the pointer is read from and re-written to Address 0101 (for Area A)

or Adress 0105 (for Area B).

GLOBAL CIRCULAR BUFFER

Beyond the programmable choice of single buffer mode, double

buffer mode, or circular buffer mode, programmable on an indi-

vidual subaddress basis, the Enhanced Mini-ACE RT architec-

ture provides an additional option, a variable sized global circu-

lar buffer.The Enhanced Mini-ACE RT allows for a mix of single

buffered, double buffered, and individually circular buffered sub-

addresses, along with the use of the global double buffer for any

arbitrary group of receive(/broadcast) or broadcast subaddress-

es.

In the global circular buffer mode, the data for multiple receive

subaddresses is stored in the same circular buffer data structure.

The size of the global circular buffer may be programmed for

128, 256, 512, 1024, 2048, 4096, or 8192 words, by means of

bits 11, 10, and 9 of Configuration Register #6. As shown in

TABLE 40, individual subaddresses may be mapped to the glob-

al circular buffer by means of their respective subaddress control

words.

The pointer to the Global Circular Buffer will be stored in location

0101 (for Area A), or location 0105 (for Area B).

The global circular buffer option provides a highly efficient

method for storing received message data. It allows for fre-

quently used subaddresses to be mapped to individual data

blocks, while also providing a method for asynchronously

received messages to infrequently used subaddresses to be

logged to a common area. Alternatively, the global circular

buffer provides an efficient means for storing the received data

words for all subaddresses. Under this method, all received

data words are stored chronologically, regardless of subad-

dress.

RT DESCRIPTOR STACK

The descriptor stack provides a chronology of all messages

processed by the Enhanced Mini-ACE RT. Reference Figures 6,

7, and 8. Similar to BC mode, there is a four-word block descrip-

tor in the Stack for each message processed.The four entries to

each block descriptor are the Block StatusWord,Time Tag Word,

the pointer to the start of the message's data block, and the 16-

bit received Command Word.

The RT Block StatusWord includes indications of whether a par-

ticular message is ongoing or has been completed, what bus

channel it was received on, indications of illegal commands, and

flags denoting various message error conditions. For the double

buffering, subaddress circular buffering, and global circular

buffering modes, the data block pointer may be used for locating

the data blocks for specific messages. Note that for mode code

commands, there is an option to store the transmitted or

received data word as the third word of the descriptor, in place of

the data block pointer.

The Time Tag Word provides a 16-bit indication of relative time

for individual messages. The resolution of the Enhanced Mini-

ACE's time tag is programmable from among 2, 4, 8, 16, 32, or

64 µs/LSB.There is also a provision for using an external clock

input for the time tag (consult factory). If enabled, there is a time

tag rollover interrupt, which is issued when the value of the time

tag rolls over from FFFF(hex) to 0.Other time tag options include

the capabilities to clear the time tag register following receipt of

a Synchronize (without data) mode command and/or to set the

time tag following receipt of a Synchronize (with data) mode

command. For that latter, there is an added option to filter the

"set" capability based on the LSB of the received data word

being equal to logic "0".

RT INTERRUPTS

The Enhanced Mini-ACE offers a great deal of flexibility in terms

of RT interrupt processing. By means of the Enhanced Mini-

ACE's two Interrupt Mask Registers, the RT may be programmed

to issue interrupt requests for the following events/conditions:

End-of-(every)Message, Message Error, Selected (transmit or

receive) Subaddress, 100% Circular Buffer Rollover, 50%

Circular Buffer Rollover, 100% Descriptor Stack Rollover, 50%

Descriptor Stack Rollover, Selected Mode Code, Transmitter

Timeout, Illegal Command, and Interrupt Status Queue Rollover.

Interrupts for 50%Rollovers of Stacks and Circular Buffers.

The Enhanced Mini-ACE RT and Monitor are capable of issuing

host interrupts when a subaddress circular buffer pointer or stack

pointer crosses its mid-point boundary. For RT circular buffers,

this is applicable for both transmit and receive subaddresses.

Reference FIGURE 9. There are four interrupt mask and inter-

rupt status register bits associated with the 50% rollover

function:

(1) RT circular buffer;

(2) RT command (descriptor) stack;

(3) Monitor command (descriptor) stack; and

(4) Monitor data stack.

The 50% rollover interrupt is beneficial for performing bulk data

transfers.For example, when using circular buffering for a partic-

ular receive subaddress, the 50% rollover interrupt will inform the

host processor when the circular buffer is half full. At that time,

the host may proceed to read the received data words in the

upper half of the buffer, while the Enhanced Mini-ACE RT writes

received data words to the lower half of the circular buffer. Later,

when the RT issues a 100% circular buffer rollover interrupt, the

host can proceed to read the received data from the lower half of

the buffer, while the Enhanced Mini-ACE RT continues to write

received data words to the upper half of the buffer.

Interrupt status queue. The Enhanced Mini-ACE RT, Monitor,

and combined RT/Monitor modes include the capability for gen-

erating an interrupt status queue. As illustrated in Figure 10, this

provides a chronological history of interrupt generating events

and conditions. In addition to the Interrupt Mask Register, the

Interrupt Status Queue provides additional filtering capability,

such that only valid messages and/or only invalid messages may

result in the creation of an entry to the Interrupt Status Queue.

Queue entries for invalid and/or valid messages may be disabled

by means of bits 8 and 7 of configuration register #6.

The interrupt status queue is 64 words deep, providing the capa-

bility to store entries for up to 32 messages. These events and

conditions include both message-related and non-message

related events. Note that the Interrupt Vector Queue Pointer

lowing the last vector/pointer pair written by the Enhanced Mini-

ACE RT.

The pointer to the Interrupt Status Queue is stored in the

INTERRUPT VECTOR QUEUE POINTER REGISTER (register

address 1F). This register must be initialized by the host, and is

subsequently incremented by the RT message processor. The

interrupt status queue is 64 words deep, providing the capability

to store entries for up to 32 messages.

The queue rolls over at addresses of modulo 64.The events that

result in queue entries include both message-related and non-

message-related events. Note that the Interrupt Vector Queue

Pointer Register will always point to the next location (modulo 64)

following the last vector/pointer pair written by the Enhanced

Mini-ACE RT, Monitor, or RT/Monitor.

Each event that causes an interrupt results in a two-word entry

to be written to the queue.The first word of the entry is the inter-

rupt vector. The vector indicates which interrupt event(s)/condi-

tion(s) caused the interrupt.

The interrupt events are classified into two categories: message

interrupt events and non-message interrupt events. Message-

based interrupt events include End-of-Message, Selected mode

code, Format error, Subaddress control word interrupt, RT

Circular buffer Rollover, Handshake failure, RT Command stack

rollover, transmitter timeout, MT Data Stack rollover,

MT Command Stack rollover, RT Command Stack 50% rollover,

MT Data Stack 50% rollover, MT Command Stack 50% rollover,

and RT Circular buffer 50% rollover. Non-message interrupt

FIGURE 10. RT (and MONITOR) INTERRUPT STATUS QUEUE

(shown for message Interrupt event)

INTERRUPT

VECTOR

DATA WORD

BLOCK

DESCRIPTOR

STACK

PARAMETER

(POINTER)

INTERRUPT STATUS QUEUE

(64 Locations)

INTERRUPT VECT OR

QUEUE POINTER

BLOCK STATUS WORD

TIME TAG

DATA BLOCK POINTER

RECIEVED COMMAND

VECTOR

FIGURE 9. 50%and 100%ROLLOVER INTERRUPTS

DATA POINTER

CIRCULAR

BUFFER*

(128,256,...8192 WORDS)

LOOK-UP TABLE

RECIEVED

(TRANSMITTED)

MESSAGE DATA

BLOCK STATUS WORD

TIME TA G WORD

DATA BLOCK POINTER

RECIEVED COMMAND WORD

DESCRIPTOR STACK

50%

ROLLOVER

INTERRUPT

50%

The example shown is for an RT Subaddress Circular Buffer.

The 50% and 100% Rollover Interrupts are also applicable to

the RT Global Circulat Buffer, RT Command Stack,

Monitor Command Stack, and Monitor Data Stack.

Note 100%

ROLLOVER

INTERRUPT

100%

RT COMMAND ILLEGALIZATION

The Enhanced Mini-ACE provides an internal mechanism for RT

Command Word illegalizing. By means of a 256-word area in

shared RAM, the host processor may designate that any mes-

sage be illegalized, based on the command word bit, sub-

address, and word count/mode code fields.The Enhanced Mini-

ACE illegalization scheme provides the maximum in flexibility,

allowing any subset of the 4096 possible combinations of broad-

cast/own address, bit, subaddress, and word count/mode

code to be illegalized.

The address map of the Enhanced Mini-ACE's illegalizing table

is illustrated in TABLE 41.

R/T

TABLE 41. ILLEGALIZATIONTABLE MEMORY MAP

3FC

3BE

37D

3C2

381

33F

300

ADDRESS

Own Addr / Tx, SA 30.WC15-0

Own Addr / Rx, SA 31. MC15-0

Brdcst / Tx, SA 30. WC31-16

Own Addr / Tx, SA 1.WC15-0

Own Addr / Rx, SA 0. MC31-16

Brdcst / Rx, SA 31. MC31-16

Brdcst / Rx, SA 0. MC15-0

DESCRIPTION

3FD

3BF

37E

3C3

382

340

301

Own Addr / Tx, SA 30.WC31-16

Own Addr / Rx, SA 31. MC31-16

Brdcst / Tx, SA 31. MC15-0

Own Addr / Tx, SA 1.WC31-16

Own Addr / Rx, SA 1.WC15-0

Brdcst / Tx, SA 0. MC15-0

Brdcst / RX,SA 0. MC31-16

3FE

3C0

37F

383

341

302

Own Addr / Tx, SA 31. MC15-0

Own Addr / Tx, SA 0. MC15-0

Brdcst / Tx, SA 31. MC31-16

Own Addr / Rx, SA 1.WC31-16

Brdcst / Tx, SA 1.MC31-16

Brdcst / Rx, SA 1.WC15-0

•

3FF

3C1

380

342

303

•

Own Addr / Tx, SA 31. MC31-16

Own Addr / Tx, SA 0. MC31-16

Own Addr / Rx, SA 0. MC15-0

Brdcst / Tx, SA 1.WC15-0

Brdcst / Rx, SA 1.WC31-16

events/conditions include time tag rollover, RT address parity

error, RAM parity error, and BIT completed.

Bit 0 of the interrupt vector (interrupt status) word indicates

whether the entry is for a message interrupt event (if bit 0 is logic

"1") or a non-message interrupt event (if bit 0 is logic "0").It is not

possible for one entry on the queue to indicate both a message

interrupt and a non-message interrupt.

As illustrated in FIGURE 10, for a message interrupt event, the

parameter word is a pointer. The pointer will reference the first

word of the RT or MT command stack descriptor (i.e., the Block

Status Word).

For a RAM Parity Error non-message interrupt, the parameter

will be the RAM address where the parity check failed. For the

RT address Parity Error, Protocol Self-test Complete, and Time

Tag rollover non-message interrupts, the parameter is not used;

it will have a value of 0000.

If enabled, an INTERRUPT STATUS QUEUE ROLLOVER inter-

rupt will be issued when the value of the queue pointer address

rolls over at a 64-word address boundary.

BUSY BIT

The Enhanced Mini-ACE RT provides two different methods for

setting the Busy status word bit: (1) globally, by means of

Configuration Register #1; or (2) on a T/R-bit/subaddress basis,

by means of a RAM lookup table. If the host CPU asserts the

bit to logic “0“ in Configuration Register #1, the Enhanced

Mini-ACE RT will respond to all non-broadcast commands with

the Busy bit set in its RT Status Word.

Alternatively, there is a Busy lookup table in the Enhanced Mini-

ACE shared RAM. By means of this table, it is possible for the

host processor to set the busy bit for any selectable subset of the

128 combinations of broadcast/own address, bit, and sub-

address.

If the busy bit is set for a transmit command, the Enhanced Mini-

ACE RT will respond with the busy bit set in the status word, but

will not transmit any data words.If the busy bit is set for a receive

command, the RT will also respond with the busy status bit set.

There are two programmable options regarding the reception of

data words for a non-mode code receive command for which the

RT is busy: (1) to transfer the received data words to shared

RAM; or (2) to not transfer the data words to shared RAM.

RT ADDRESS

The Enhanced Mini-ACE offers several different options for des-

ignating the Remote Terminal address.These include the follow-

ing: (1) hardwired, by means of the 5 RT ADDRESS inputs, and

the RT ADDRESS PARITY input; (2) by means of the RT

ADDRESS (and PARITY) inputs, but latched via hardware, on

the rising edge of the RT_AD_LAT input signal; (3) input by

means of the RT ADDRESS (and PARITY) inputs, but latched via

host software; and (4) software programmable, by means of an

internal register. In all four configurations, the RT address is

readable by the host processor.

R/T

BUSY

RT BUILT-IN-TEST (BIT) WORD

The bit map for the Enhanced Mini-ACE's internal RT Built-in-

Test (BIT) Word is indicated in TABLE 42.

COMMAND WORD CONTENTS ERROR0(LSB) RT-to-RT 2ND COMMAND WORD ERROR1RT-to-RT NO RESPONSE ERROR2

TRANSMITTER SHUTDOWN B

RT-to-RT GAP / SYNC ADDRESS ERROR3PARITY / MANCHESTER ERROR RECEIVED4INCORRECT SYNC RECEIVED5LOW WORD COUNT6HIGH WORD COUNT7BIT TEST FAILURE8TERMINAL FLAG INHIBITED9TRANSMITTER SHUTDOWN A10

HANDSHAKE FAILURE12 LOOP TEST FAILURE A13 LOOP TEST FAILURE B14 TRANSMITTER TIMEOUT15(MSB)

DESCRIPTIONBIT

TABLE 42. RT BIT WORD

RT AUTO-BOOT OPTION

If utilized, the RT pin-programmable auto-boot option allows the

Enhanced Mini-ACE RT to automatically initialize as an active

remote terminal with the Busy status word bit set to logic "1"

immediately following power turn-on. This is a useful feature for

MIL-STD-1760 applications, in which the RT is required to be

responding within 150 ms after power-up. This feature is avail-

able for versions of the Enhanced Mini-ACE with 4K words of

RAM.

OTHER RT FEATURES.

The Enhanced Mini-ACE includes options for the Terminal flag

status word bit to be set either under software control and/or

automatically following a failure of the loopback self-test. Other

software programmable RT options include software program-

mable RT status and RT BIT words, automatic clearing of the

Service Request bit following receipt of a Transmit vector word

mode command, options regarding Data Word transfers for the

Busy and Message error (illegal) Status word bits, and options

for the handling of 1553A and reserved mode codes.

MONITOR ARCHITECTURE

The Enhanced Mini-ACE includes three monitor modes:

(1) A Word Monitor mode.

(2) A selective message monitor mode.

(3) A combined RT/message monitor mode.

For new applications, it is recommended that the selective mes-

sage monitor mode be used, rather than the word monitor mode.

Besides providing monitor filtering based on RT address,

bit, and subaddress, the message monitor eliminates the need to

determine the start and end of messages by software.

WORD MONITOR MODE

In the Word Monitor Terminal mode, the Enhanced Mini-ACE

monitors both 1553 buses. After the software initialization and

Monitor Start sequences, the Enhanced Mini-ACE stores all

Command, Status, and Data Words received from both buses.

For each word received from either bus, a pair of words is stored

to the Enhanced Mini-ACE's shared RAM. The first word is the

word received from the 1553 bus. The second word is the

Monitor Identification (ID), or "Tag" word. The ID word contains

information relating to bus channel, word validity, and inter-word

time gaps.The data and ID words are stored in a circular buffer

in the shared RAM address space.

WORD MONITOR MEMORY MAP

A typical word monitor memory map is illustrated in TABLE 43.

TABLE 43 assumes a 64K address space for the Enhanced Mini-

ACE's monitor. The Active Area Stack pointer provides the

address where the first monitored word is stored.In the example,

it is assumed that the Active Area Stack Pointer for Area A (loca-

tion 0100) is initialized to 0000. The first received data word is

R/T

stored in location 0000, the ID word for the first word is stored in

location 0001, etc.

The current Monitor address is maintained by means of a

counter register. This value may be read by the CPU by means

of the Data Stack Address Register. It is important to note that

when the counter reaches the Stack Pointer address of 0100 or

0104, the initial pointer value stored in this shared RAM location

will be overwritten by the monitored data and ID Words.When

the internal counter reaches an address of FFFF (or 0FFF, for an

Enhanced Mini-ACE with 4K RAM), the counter rolls over to

0000.

WORD MONITOR TRIGGER

In the Word Monitor mode, there is a pattern recognition trigger

and a pattern recognition interrupt. The 16-bit compare word for

both the trigger and the interrupt is stored in the Monitor Trigger

Word Register. The pattern recognition interrupt is enabled by

setting the MT Pattern Trigger bit in Interrupt Mask Register #1.

The pattern recognition trigger is enabled by setting the Trigger

Enable bit in Configuration Register #1 and selecting either the

Start-on-trigger or the Stop-on-trigger bit in Configuration

The Word Monitor may also be started by means of a low-to-high

transition on the EXT_TRIG input signal.

SELECTIVE MESSAGE MONITOR MODE

The Enhanced Mini-ACE Selective Message Monitor provides

monitoring of 1553 messages with filtering based on RT

address, bit, and subaddress with no host processor inter-

vention. By autonomously distinguishing between 1553 com-

mand and status words, the Message Monitor determines when

messages begin and end, and stores the messages into RAM,

based on a programmable filter of RT address, bit, and sub-

address.

The selective monitor may be configured as just a monitor, or as

acombined RT/Monitor. In the combined RT/Monitor mode, the

Enhanced Mini-ACE functions as an RT for one RT address

(including broadcast messages), and as a selective message

monitor for the other 30 RT addresses.The Enhanced Mini-ACE

Message Monitor contains two stacks, a command stack and a

data stack, that are independent from the RT command stack.

The pointers for these stacks are located at fixed locations in

RAM.

MONITOR SELECTION FUNCTION

Following receipt of a valid command word in Selective Monitor

mode, the Enhanced Mini-ACE will reference the selective mon-

itor lookup table to determine if the particular command is

enabled.The address for this location in the table is determined

by means of an offset based on the RT Address, bit, and

Subaddress bit 4 of the current command word, and concate-

nating it to the monitor lookup table base address of 0280 (hex).

R/T

Third Received 1553 Word

•

Received 1553 Words and Identification Word

•

FFFF

Stack Pointer

(Fixed Location - gets overwritten)

0100

•

Third Identification Word005

Second Identification Word0003 Second Received 1553 Word0002 First Identification Word0001 First Received 1553 Word0000

FUNCTION

HEX

ADDRESS

0004

TABLE 43. TYPICAL WORD MONITOR MEMORY MAP

The bit location within this word is determined by subaddress bits

3-0 of the current command word.

If the specified bit in the lookup table is logic "0", the command

is not enabled, and the Enhanced Mini-ACE will ignore this com-

mand. If this bit is logic "1", the command is enabled and the

Enhanced Mini-ACE will create an entry in the monitor command

descriptor stack (based on the monitor command stack pointer),

and store the data and status words associated with the com-

mand into sequential locations in the monitor data stack.In addi-

tion, for an RT-to-RT transfer in which the receive command is

selected, the second command word (the transmit command) is

stored in the monitor data stack.

The address definition for the Selective Monitor Lookup TABLE

is illustrated in TABLE 44.

For this example, the Monitor Command Stack size is assumed

to be 1K words, and the Monitor Data Stack size is assumed to

be 2K words.

FIGURE 11 illustrates the Selective Message Monitor operation.

Upon receipt of a valid CommandWord, the Enhanced Mini-ACE

will reference the Selective Monitor Lookup Table to determine if

the current command is enabled. If the current command is dis-

abled, the Enhanced Mini-ACE monitor will ignore (and not store)

the current message.If the command is enabled, the monitor will

create an entry in the Monitor Command Stack at the address

location referenced by the Monitor Command Stack Pointer, and

an entry in the monitor data stack starting at the location refer-

enced by the Monitor Data Stack Pointer.

The format of the information in the data stack depends on the

format of the message that was processed. For example, for a

BC-to-RT transfer (receive command), the monitor will store the

command word in the monitor command descriptor stack, with

the data words and the receiving RT's status word stored in the

monitor data stack.

The size of the monitor command stack is programmable, with

choices of 256, 1K, 4K, or 16K words. The monitor data stack

size is programmable with choices of 512, 1K, 2K, 4K, 8K, 16K,

32K or 64K words.

SUBADDRESS 40(LSB) TRANSMIT / RECEIVE1RTAD_02

Logic “0”

RTAD_13RTAD_24RTAD_35RTAD_46Logic “1”7Logic “0”8Logic “1”9Logic “0”10

Logic “0”12

Logic “0”13 Logic “0”14 Logic “0”15(MSB)

DESCRIPTIONBIT

TABLE 44. MONITOR SELECTION TABLE LOOKUP ADDRESS

SELECTIVE MESSAGE MONITOR MEMORY

ORGANIZATION

A typical memory map for the ACE in the Selective Message

Monitor mode, assuming a 4K RAM space, is illustrated in

TABLE 45.This mode of operation defines several fixed locations

in the RAM.These locations are allocated in a way in which none

of them overlap with the fixed RT locations. This allows for the

combined RT/Selective Message Monitor mode.

The fixed memory map consists of two Monitor Command Stack

Pointers (locations 102 and 106 hex), two Monitor Data Stack

Pointers (locations 103 and 107 hex), and a Selective Message

Monitor Lookup Table (locations 0280 through 02FF hex).

Monitor Command Stack Pointer B (fixed location)

Monitor Data Stack A0800-0FFF Monitor Command Stack A0400-07FF Not Used0300-03FF Selective Monitor Lookup Table (fixed location)0280-02FF Not Used0108-027F Monitor Data Stack Pointer B (fixed location)0107

Not Used0104-0105 Monitor Data Stack Pointer A (fixed location)0103 Monitor Command Stack Pointer A (fixed location)0102 Not Used

0000-0101

DESCRIPTION

ADDRESS

(HEX)

0106

TABLE 45. TYPICAL SELECTIVE MESSAGE MONITOR MEMORY

MAP (shown for 4K RAM for “Monitor only” mode)

MISCELLANEOUS

CLOCK INPUT

The Enhanced Mini-ACE decoder is capable of operating from a

10, 12, 16, or 20 MHz clock input. Depending on the configura-

tion of the specific model Enhanced Mini-ACE terminal, the

selection of the clock input frequency may be chosen by one of

either two methods.For all versions, the clock frequency may be

specified by means of the host processor writing to Configuration

the versions incorporating 4K (but not 64K) words of internal

RAM, the clock frequency may be specified by means of the

input signals that are otherwise used as the A15 and A14

address lines.

ENCODER/DECODERS

For the selected clock frequency, there is internal logic to derive

the necessary clocks for the Manchester encoder and decoders.

For all clock frequencies, the decoders sample the receiver out-

puts on both edges of the input clock. By in effect doubling the

decoders' sampling frequency, this serves to widen the tolerance

to zero-crossing distortion, and reduce the bit error rate.

For interfacing to fiber optic transceivers (e.g., for MIL-STD-1773

applications), the decoders are capable of operating with single-

ended, rather than double-ended, input signals. For applications

Monitor Interrupts. Selective monitor interrupts may be issued

for End-of-message and for conditions relating to the monitor

command stack pointer and monitor data stack pointer. The lat-

ter, which are shown in FIGURE 9, include Command Stack 50%

Rollover, Command Stack 100% Rollover, Data Stack 50%

Rollover, and Data Stack 100% Rollover.

The 50% rollover interrupts may be used to inform the host

processor when the command stack or data stack is half full. At

that time, the host may proceed to read the received messages

in the upper half of the respective stack, while the Enhanced

Mini-ACE monitor writes messages to the lower half of the stack.

Later, when the monitor issues a 100% stack rollover interrupt,

the host can proceed to read the received data from the lower

half of the stack, while the Enhanced Mini-ACE monitor contin-

ues to write received data words to the upper half of the stack.

INTERRUPT STATUS QUEUE

Like the Enhanced Mini-ACE RT, the Selective Monitor mode

includes the capability for generating an interrupt status queue.

As illustrated in FIGURE 10, this provides a chronological histo-

ry of interrupt generating events. Besides the two Interrupt Mask

Registers, the Interrupt Status Queue provides additional filter-

ing capability, such that only valid messages and/or only invalid

messages may result in entries to the Interrupt Status Queue.

The interrupt status queue is 64 words deep, providing the capa-

bility to store entries for up to 32 monitored messages.

15 13 0

BLOCK STATUS WORD

TIME TAG WORD

DATA BLOCK POINTER

RECEIVED COMMAND

WORD

CONFIGURATION

STACK POINTERS MONITOR

COMMAND STACKS

CURRENT

AREA B/A

MONITOR DATA

STACKS

MONITOR DATA

BLOCK #N + 1

MONITOR DATA

BLOCK #N

CURRENT

COMMAND WORD

MONITOR DATA

STACK POINTERS

IF THIS BIT IS "0" (NOT SELECTED)

NO WORDS ARE STORED IN EITHER

THE COMMAND STACK OR DATA STACK.

IN ADDITION, THE COMMAND AND DATA

STACK POINTERS WILL NOT BE UPDATED.

NOTE

SELECTIVE MONITOR

LOOKUP TABLES

SELECTIVE MONITOR

ENABLE

(SEE NOTE)

OFFSET BASED ON

RTA4-RTA0, T/R, SA4

FIGURE 11. SELECTIVE MESSAGE MONITOR MEMORY MANAGEMENT

involving the use of single-ended transceivers, it is suggested

that you contact the factory at DDC regarding a transceiverless

version of the Enhanced Mini-ACE.

TIME TAG

The Enhanced Mini-ACE includes an internal read/writable Time

Tag Register. This register is a CPU read/writable 16-bit counter

with a programmable resolution of either 2, 4, 8, 16, 32, or 64 µs

per LSB. Another option allows software controlled incrementing

of theTime Tag Register. This supports self-test for theTime Tag

Tag Register is loaded into the second location of the respective

descriptor stack entry ("TIME TAG WORD") for both the BC and

RT modes.

The functionality involving the Time Tag Register that's compati-

ble with ACE/Mini-ACE (Plus) includes:the capability to issue an

interrupt request and set a bit in the Interrupt Status Register

when the Time Tag Register rolls over FFFF to 0000; for RT

mode, the capability to automatically clear theTime Tag Register

following reception of a Synchronize (without data) mode com-

mand, or to load the Time Tag Register following a Synchronize

(with data) mode command.

Additional time tag features supported by the Enhanced Mini-

ACE include the capability for the BC to transmit the contents of

the Time Tag Register as the data word for a Synchronize (with

data) mode command;the capability for the RT to "filter" the data

word for the Synchronize with data mode command, by only

loading the Time Tag Register if the LSB of the received data

word is "0"; an instruction enabling the BC Message Sequence

Control engine to load the Time Tag Register with a specified

value; and an instruction enabling the BC Message Sequence

Control engine to write the value of the Time Tag Register to the

General Purpose Queue.

INTERRUPTS

The Enhanced Mini-ACE series terminals provide many pro-

grammable options for interrupt generation and handling. The

interrupt output pin ( ) has three software programmable

mode of operation: a pulse,aleveloutput cleared under soft-

ware control, or a level output automatically cleared following a

read of the Interrupt Status Register (#1 or #2).

Individual interrupts are enabled by the two Interrupt Mask

Registers. The host processor may determine the cause of the

interrupt by reading the two Interrupt Status Registers, which

provide the current state of interrupt events and conditions. The

Interrupt Status Registers may be updated in two ways. In one

interrupt handling mode, a particular bit in Interrupt Status

corresponding bit in Interrupt Mask Register #1 or #2 is enabled.

In the enhanced interrupt handling mode, a particular bit in the

one of the Interrupt Status Registers will be updated if the

event/condition occurs regardless of the value of the corre-

sponding Interrupt Mask Register bit. In either case, the respec-

tive Interrupt Mask Register (#1 or #2) bit is used to enable an

interrupt for a particular event/condition.

INT

The Enhanced Mini-ACE supports all the interrupt events from

ACE/Mini-ACE (Plus), including RAM Parity Error, Transmitter

Timeout, BC/RT Command Stack Rollover, MT Command Stack

and Data Stack Rollover, Handshake Error, BC Retry, RT

Address Parity Error, Time Tag Rollover, RT Circular Buffer

Rollover, BC Message, RT Subaddress, BC End-of-Frame,

Format Error, BC Status Set, RT Mode Code, MT Trigger, and

End-of-Message.

For the Enhanced Mini-ACE's Enhanced BC mode, there are

four user-defined interrupt bits. The BC Message Sequence

Control Engine includes an instruction enabling it to issue these

interrupts at any time.

For RT and Monitor modes, the Enhanced Mini-ACE architecture

include an Interrupt Status Queue. This provides a mechanism

for logging messages that result in interrupt requests. Entries to

the Interrupt Status Queue may be filtered such that only valid

and/or invalid messages will result in entries on the queue.

The Enhanced Mini-ACE incorporates additional interrupt condi-

tions beyond ACE/Mini-ACE (Plus), based on the addition of

Interrupt Mask Register #2 and Interrupt Status Register #2.This

is accomplished by chaining the two Interrupt Status Registers

using the INTERRUPT CHAIN BIT (bit 0) in Interrupt Status

Status Register #1. Additional interrupts include "Self-Test

Completed", masking bits for the Enhanced BC Control

Interrupts, 50% Rollover interrupts for RT Command Stack, RT

Circular Buffers, MT Command Stack, and MT Data Stack; BC

Op Code Parity Error, (RT) Illegal Command, (BC) General

Purpose Queue or (RT/MT) Interrupt Status Queue Rollover,

Call Stack Pointer Register Error, BC Trap Op Code, and the four

User-Defined interrupts for the Enhanced BC mode.

BUILT-IN TEST

A salient feature of the Enhanced Mini-ACE is its highly

autonomous self-test capability. This includes both protocol and

RAM self-tests.Either or both of these self-tests may be initiated

by command(s) from the host processor.

The protocol test consists of a toggle test of 95% of the termi-

nal's logic gates. The test includes a comprehensive test of all

registers, Manchester encoder and decoders, transmitter failsafe

timer, and protocol logic.This test is completed in approximately

32,000 clock cycles.That is, about 1.6 ms with a 20 MHz clock,

2.0 ms at 16 MHz, 2.7 ms at 12 MHz, and 3.2 ms at 10 MHz.

There is also a separate built-in test for the Enhanced Mini-

ACE's 4K X 16 or 16K X 16 shared RAM. This test consists of

writing and then reading/verifying the two walking patterns "data

= address" and "data = address inverted". This test takes 10

clock cycles per word.For an Enhanced Mini-ACE with 4K words

of RAM, this is about 2.0 ms with a 20 MHz clock, 2.6 ms at 16

MHz, 3.4 ms at 12 MHz, or 4.1 ms at 10 MHz. For an Enhanced

Mini-ACE with 64K words of RAM, this test takes about 32.8 ms

with a 20 MHz clock, 40.1 ms at 16 MHz, 54.6 ms at 12 MHz, or

65.6 ms at 10 MHz.

The Enhanced Mini-ACE built-in test may be initiated by a com-

mand from the host processor, via the START/REST REGIS-

TER. For RT mode, this may include the host processor invoking

self-test following receipt of an Initiate self-test mode command.

The results of the self-test are host accessible by means of the

BIT status register. For RT mode, the result of the self-test may

be communicated to the bus controller via bit 8 of the RT BIT

word ("0" = pass, "1" = fail).

Assuming that the protocol self-test passes, all of the register

and shared RAM locations will be restored to their state prior to

the self-test, with the exception of the 60 RAM address locations

0342-037D and the TIME TAG REGISTER. Note that for RT

mode, these locations map to the illegalization lookup table for

"broadcast transmit subaddresses 1 through 30" (non-mode

code subaddresses). Since MIL-STD-1553 does not define

these as valid command words, this section of the illegalization

lookup table is normally not used.TheTIME TAG REGISTER will

continue to increment during the self-test.

If there is a failure of the protocol self-test, it is possible to access

information about the first failed vector. This may be done by

means of the Enhanced Mini-ACE's upper registers (register

addresses 32 through 63).Through these registers, it is possible

to determine the self-test ROM address of the first failed vector,

the expected response data pattern (from the ROM), the register

or memory address, and the actual (incorrect) data value read

from register or memory.The on-chip self-test ROM is 4K X 24.

Note that the RAM self-test is destructive. That is, following the

RAM self-test, regardless of whether the test passes or fails, the

shared RAM is not restored to its state prior to this test.

Following a failed RAM self-test, the host may read the internal

RAM to determine which location(s) failed the walking pattern

test.

RAM PARITY

The BC/RT/MT version of the Enhanced Mini-ACE is available

with options of 4K or 64K words of internal RAM. For the 64K

option, the RAM is 17 bits wide. The 64K X 17 internal RAM

allows for parity generation for RAM write accesses, and parity

checking for RAM read accesses.This includes host RAM acess-

es, as well as acesses by the Enhanced Mini-ACE’s internal

logic.When the Enhanced Mini-ACE detects a RAM parity error,

it reports it to the host processor by means of an interrupt and a

modes, the RAM address where a parity error was detected will

be stored on the Interrupt Status Queue (if enabled).

RELOCATABLE MEMORY MANAGEMENT LOCATIONS

In the Enhanced Mini-ACE's default configuration, there is a

fixed

area of shared RAM addresses, 0000h-03FF, that is allocated for

storage of the BC's or RT's pointers, counters, tables, and other

"non-message" data structures. As a means of reducing the

overall memory address space for using multiple Enhanced Mini-

ACEs in a given system (e.g., for use with the DMA interface

configuration), the Enhanced Mini-ACE allows this area of RAM

to be relocated by means of 6 configuration register bits.To pro-

vide backwards compatibility to ACE and Mini-ACE, the default

for this RAM area is 0000h-03FFh.

HOST PROCESSOR INTERFACE

The Enhanced Mini-ACE supports a wide variety of processor

interface configurations. These include shared RAM and DMA

configurations, straightforward interfacing for 16-bit and 8-bit

buses, support for both non-multiplexed and multiplexed

address/data buses, non-zero wait mode for interfacing to a

processor address/data buses, and zero wait mode for interfac-

ing (for example) to microcontroller I/O ports. In addition, with

respect to the ACE/Mini-ACE, the Enhanced Mini-ACE provides

two major improvements: (1) reduced maximum host access

time for shared RAM mode; and (2) increased maximum DMA

grant time for the transparent/DMA mode.

The Enhanced Mini-ACE's maximum host holdoff time (time prior

to the assertion of the handshake signal) has been sig-

nificantly reduced. For ACE/Mini-ACE, this maximum holdoff

time is 10 internal word transfer cycles, resulting in an overall

holdoff time of approximately 2.8 µs, using a 16 MHz clock. By

comparison, using the Enhanced Mini-ACE's ENHANCED CPU

ACCESS feature, this worst-case holdoff time is reduced signifi-

cantly, to a single internal transfer cycle. For example, when

operating the Enhanced Mini-ACE in its 16-bit buffered, non-zero

wait configuration with a 16 MHz clock input, this results in a

maximum overall host transfer cycle time of 632 ns for a read

cycle, or 570 ns for a write cycle.

In addition, for using the ACE or Mini-ACE in the

transparent/DMA configuration, the maximum request-to-grant

time, which occurs prior to an RT start-of-message sequence, is

4.0 µs with a 16 MHz clock, or 3.5 µs with a 12 MHz clock. For

the Enhanced Mini-ACE functioning as a MIL-STD-1553B RT,

this time has been increased to 8.5 µs at 10 MHz, 10 µs at 16

MHz, 9 µs at 12 MHz, and 10.5 µs at 20MHz. This provides

greater flexibility, particularly for systems in which a host has to

arbitrate among multiple DMA requestors.

By far, the most commonly used processor interface configura-

tion is the 16-bit buffered, non-zero wait mode.This configuration

may be used to interface between 16-bit or 32-bit microproces-

sors and an Enhanced Mini-ACE. In this mode, only the

Enhanced Mini-ACE's internal 4K or 64K words of internal RAM

are used for storing 1553 message data and associated "house-

keeping" functions. That is, in this configuration, the Enhanced

Mini-ACE will never attempt to access memory on the host bus.

FIGURE 12 illustrates a generic connection diagram between a

16-bit (or 32-bit) microprocessor and an Enhanced Mini-ACE for

the 16-bit buffered configuration, while Figures 13 and 14, and

associated tables illustrate the processor read and write timing

respectively.

READYD

HOST

Enhanced

55 Ω

CH. A

TX/RXA

55 Ω

CH. B

TX/RXB

RTAD4-RTAD0 RT

ADDRESS,

PARITY

RTADP

D15-D0

+5V (3.3V)

(NOTE 5)

CLK IN

CLOCK

OSCILLATOR

N/C

POLARITY_SEL

(NOTE 2)

ZERO_WAIT

(NOTE 3)

ADDRESS

DECODER

SELECT

MEM/REG

RD/WR

STRBD

READYD

TAG_CLK

RD/WR

CPU STROBE

CPU ACKNOWLEDGE (NOTE 4)

RESET

+5V

MSTCLR

SSFLAG/EXT_TRIG

INT

CPU INTERRUPT REQUEST

NOTES:

3. ZERO_WAIT SHOULD BE STRAPPED TO

LOGIC "1" FOR NON-ZERO WAIT INTERFACE

AND TO LOGIC "0" FOR ZERO WAIT INTERFACE.

4. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY

FOR NON-ZERO WAIT TYPE OF INTERFACE.

5. +3.3V POWER FOR BU-61743 / 61843 / 61864 ONLY

1. CPU ADDRESS LATCH SIGNAL PROVIDED BY

PROCESSORS WITH MULTIPLEXED ADDRESS/DATA

BUSES. FOR PROCESSORS WITH NON-MULTIPLEXED

ADDRESS AND DATA BUSSES, ADDR_LAT SHOULD BE

CONNECTED TO +5V.

2. IF POLARITY_SEL = "1", RD/WR IS HIGH TO READ,

LOW TO WRITE.

IF POLARITY_SEL = "0", RD/WR IS LOW TO READ,

HIGH TO WRITE.

A15-A12

A11-A0

N/C

ADDR_LAT

TRANSPARENT/BUFFERED

CPU ADDRESS LATCH (NOTE 1)

+5V

16/8_BIT

TRIGGER_SEL

MSB/LSB

+5V

Mini-ACE

FIGURE 12. HOST PROCESSOR INTERFACE - 16-BIT BUFFERED CONFIGURATION

CLOCK IN

VALID

t3 t8

t11

t13 t15

VALID t10

t4 t9 t12

t19

;

;;

VALID

t16

t17

SELECT

(Note 2,7)

(Note 2)

(Note 3,4,7)

(Note 4,5)

STRBD

MEM/REG

RD/WR

IOEN

(Note 2,6)

(Note 6)

(Note 7,8,9)

READYD

A15-A0

D15-D0

;

;;

;;;

;;

t2 t6 t14 t18

FIGURE 13. CPU READING RAM / REGISTER (16-BIT BUFFERED, NONZERO WAIT)

NOTES:

1. For the 16-bit buffered nonzero wait configuration, must be connected to logic "0". and

must be connected to logic "1". The inputs TRIGGER_SEL and MSB/LSB may be connected to either +5V or ground.

2. and may be tied together. goes low on the first rising CLK edge when • is sampled low (satisfying t1)

and the Enhanced Mini-ACE's protocol/memory management logic is not accessing the internal RAM. When this occurs, goes low, start-

ing the transfer cycle. After goes low, may be released high.

3. must be presented high for memory access, low for register access.

4. and are buffered transparently until the first falling edge of CLK after goes low. After this CLK edge, and

become latched internally.

5. The logic sense for in the diagram assumes that POLARITY_SEL is connected to logic "1." If POLARITY_SEL is connected to logic "0,"

must be asserted low to read.

6. The timing for , and D15-D0 assumes a 50 pf load. For loading above 50 pf, the validity of , , and D15-D0 is

delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max.

7. The timing for A15-A0, and assumes that ADDR-LAT is connected to logic "1." Refer to Address Latch timing for additional

details.

8. The address bus A15-A0 is internally buffered transparently until the first rising edge of CLK after goes low. After this CLK edge, A15-A0

become latched internally.

9. Setup time given for use in worst case timing calculations. None of the Enhanced Mini-ACE input signals are required to be synchronized to the

system clock.When and do not meet the setup time of t1, but occur during the setup window of an internal flip-flop, an addi-

tional clock cycle will be inserted between the falling clock edge that latches and and the rising clock edge that latches the

Address (A15-A0). When this occurs, the delay from falling to falling (t11) increases by one clock cycle and the address hold

time (t10) must be increased be one clock cycle.

READYD

IOEN

WR/RD

REG/MEM

STRBD

SELECT

IOEN

SELECT

REG/MEM

READYD

IOEN

READYD

IOEN

WR/RD

REG/MEM

IOEN

WR/RD

REG/MEM

SELECT

IOEN

STRBD

SELECT

IOEN

STRBD

SELECT

8/16/DTREQ

WAITZERO

BUFFERED/TTRANSPAREN

2, 6

3, 4, 5, 7

2, 6

7, 8

6, 9

3, 4, 5, 7

6, 9

7, 8, 9

3, 4, 5, 7

2, 6

MAXTYPMIN UNITS

MAXTYPMIN

DESCRIPTIONREF

4.4

155

555

655

138

430

2.8

3.7

∞

355

165150135

265250235 205187.5170

315300285

2.2

105

NOTES

2, 9

2, 6 117

µs4.4(contended access, with ENHANCED CPU SELECT = “0” @10 MHz)

ns150(uncontended access @10 MHz) ns550(contended access, with ENHANCED CPU SELECT = “1” @12 MHz)

ns650(contended access, with ENHANCED CPU SELECT = “1” @10 MHz)

ns133(uncontended access @12 MHz)

ns425(contended acces, with ENHANCED CPU SELECT = “1” s @16 MHz) µs2.8(contended access, with ENHANCED CPU SELECT = “0” @16 MHz)

µs3.7(contended access, with ENHANCED CPU SELECT = “0” @12 MHz)

ns40@10 MHz

ns32@12 MHz

ns67@10 MHz ns50@12 MHz

ns71@10 MHz ns54@12 MHz

ns40CLOCK IN rising edge delay to output data validt19

ns0STRBD high hold time from READYD risingt18

ns40STRBD rising delay to output data tri-statet17

ns0Output Data hold time following STRBD rising edget16

ns30STRBD rising edge delay to IOEN rising edge and READYD rising edget15

∞

READYD falling to STRBD rising release timet14

ns40CLOCK IN rising edge delay to READYD fallingt13

t12

ns0SELECT hold time following IOEN fallingt6

ns30@16 MHz

ns350(contended access, with ENHANCED CPU SELECT = “1” @20 MHz)

ns30Address valid setup time prior to CLOCK IN rising edget9

ns165150135IOEN falling delay to READYD falling (@20 MHz)

ns265250235@12 MHz ns205187.5170@16 MHz

ns30MEM/REG, RD/WR hold time following CLOCK IN falling edget8

ns33@16 MHz

ns21Output Data valid prior to READYD falling (@20 MHz)

ns315300285@10 MHz

ns30Address hold time following CLOCK IN rising edget10

t11

ns10MEM/REG, RD/WR setup time prior to CLOCK IN falling edget7

ns40CLOCK IN rising edge delay to IOEN falling edget5

ns17Time for Address to become valid following SELECT and STRBD low (@20 MHz)

ns21@16 MHz ns15

Time for MEM/REG and RD/WR to become valid following SELECT and STRBD

low(@20 MHz)

µs2.2(contended access, with ENHANCED CPU SELECT = “0” @20 MHz) ns100SELECT and STRBD low to IOEN low (uncontended access @20 MHz)

t2 ns10SELECT and STRBD low setup time prior to clock rising edget1

3.3V LOGIC5V LOGIC

TABLE FOR FIGURE 13. CPU READING RAM OR REGISTERS (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)

ns112(uncontended access @16 MHz)

CLOCK IN

t18

t16

VALID

t8 t9

t14

t15 t17

VALID t12

t10

t11

VALID t13

SELECT

(Note 2,7)

(Note 2)

(Note 3,4,7)

(Note 4,5)

STRBD

MEM/REG

RD/WR

IOEN

(Note 2,6)

(Note 6)

(Note 9,10)

(Note 7,8,9,10)

READYD

A15-A0

D15-D0

FIGURE 14. CPU WRITING RAM / REGISTER (16-BIT BUFFERED, NONZERO WAIT)

NOTES:

1. For the 16-bit buffered nonzero wait configuration must be connected to logic "0", and

must be connected to logic "1".The inputs TRIGGER_SEL and MSB/LSB may be connected to either +5V or ground.

2. and may be tied together. goes low on the first rising CLK edge when • is sampled low (satisfying

t1) and the Enhanced Mini-ACE's protocol/memory management logic is not accessing the internal RAM. When this occurs, goes low, start-

ing the transfer cycle. After goes low, may be released high.

3. must be presented high for memory access, low for register access.

4. and are buffered transparently until the first falling edge of CLK after goes low. After this CLK edge, and

become latched internally.

5. The logic sense for in the diagram assumes that POLARITY_SEL is connected to logic "1." If POLARITY_SEL is connected to logic "0,"

must be asserted high to write.

6. The timing for the and outputs assumes a 50 pf load. For loading above 50 pf, the validity of and is delayed

by an additional 0.14 ns/pf typ, 0.28 ns/pf max.

7. The timing for A15-A0, , and assumes that ADDR-LAT is connected to logic "1." Refer to Address Latch timing for addi-

tional details.

9. The address bus A15-A0 and data bus D15-D0 are internally buffered transparently until the first rising edge of CLK after goes low. After

this CLK edge, A15-A0 and D15-D0 become latched internally.

10. Setup time given for use in worst case timing calculations. None of the Enhanced Mini-ACE input signals are required to be synchronized to the

system clock.When and do not meet the setup time of t1, but occur during the setup time of an internal flip-flop, an addition-

al clock cycle may be inserted between the falling clock edge that latches and and the rising clock edge that latches the

address (A15-A0) and data (D15-D0). When this occurs, the delay from falling to falling (t14) increases by one clock cycle and

the address and data hold time (t12 and t13) must be increased by one clock.

READYD

IOEN

WR/RD

REG/MEM

STRBD

SELECT

IOEN

SELECT

REG/MEM

READYD

IOEN

READYD

IOEN

WR/RD

REG/MEM

IOEN

WR/RD

REG/MEM

SELECT

IOEN

STRBD

SELECT

IOEN

STRBD

SELECT

8/16/DTREQ

WAITZERO

BUFFERED/TTRANSPAREN

(uncontended access @16 MHz) 112 ns

TABLE FOR FIGURE 14. CPU WRITING RAM OR REGISTERS (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)

3.3V LOGIC5V LOGIC

@16 MHz

t1 SELECT and STRBD low setup time prior to clock rising edge 10 ns

t2 SELECT and STRBD low to IOEN low (uncontended access @20 MHz) 100 ns

(contended access, with ENHANCED CPU SELECT = “0” @20 MHz) 2.2 µs

Tme for MEM/REG and RD/WR to become valid following SELECT and STRBD

low(@20 MHz) 15 ns

@16 MHz 21 ns

Time for Address to become valid following SELECT and STRBD low (@20 MHz) 17 ns

Time for data to become valid following SELECT and STRBD low ( @20 MHz ) 37 ns

t7 SELECT hold time following IOEN falling 0ns

@12 MHz

t10 Address valid setup time prior to CLOCK IN rising edge 30 ns

IOEN falling delay to READYD falling @20 MHz 85 100 115 ns

t12 Address valid hold time prior to CLOCK IN rising edge 30 ns

85 100 115

6, 9

@16 MHz

t8 MEM/REG, RD/WR setup time prior to CLOCK IN falling edge 10 ns

110 125 140 ns110 125 140

6, 9

@12 MHz 152 167

t11 Data valid setup time prior to CLOCK IN rising edge 10 ns

t9 MEM/REG, RD/WR setup time following CLOCK IN falling edge 30 ns

(contended access, with ENHANCED CPU SELECT = “1” @20 MHz) 350 ns

@10 MHz

@16 MHz 30 ns

t6 CLOCK IN rising edge delay to IOEN falling edge 40 ns

t13 Data valid hold time following CLOCK IN rising edge 10 ns

t15 CLOCK IN rising edge delay to READYD falling 40 ns

t16 READYD falling to STRBD rising release time ∞ns

t17 STRBD rising delay to IOEN rising edge and READYD rising edge 30 ns

t18 STRBD high hold time from READYD rising 0ns

182 ns152 167 182

6, 9

t14

@10 MHz 185 200 215 ns185 200 215

6, 9

@12 MHz 50 ns

@10 MHz 67 ns

@12 MHz 32 ns

@10 MHz 40 ns

(contended access, with ENHANCED CPU SELECT = “0” @12 MHz) 3.7 µs

(contended access, with ENHANCED CPU SELECT = “0” @16 MHz) 2.8 µs

(contended acces, with ENHANCED CPU SELECT = “1” @16 MHz) 425 ns

(uncontended access @12 MHz) 133 ns

(contended access, with ENHANCED CPU SELECT = “1” @10 MHz) 650 ns

(contended access, with ENHANCED CPU SELECT = “1” @12 MHz) 550 ns

(uncontended access @10 MHz) 150 ns

(contended access, with ENHANCED CPU SELECT = “0” @10 MHz) 4.4 µs

1172, 6

2, 10

NOTES

105

2.2

355

∞

3.7

2.8

430

138

655

555

155

4.4

REF DESCRIPTION MIN TYP MAX UNITS

MIN TYP MAX

2, 6

3, 4, 5, 7

7, 8

7, 8, 9

3, 4, 5, 7

2, 6

3, 4, 5, 7

2, 6

INTERFACETO MIL-STD-1553 BUS

FIGURE 15 illustrates the interface between the various versions

of the Enhanced Mini-ACE series and a MIL-STD-1553 bus.

Connections for both direct (short stub) and transformer (long

stub) coupling, as well as the nominal peak-to-peak voltage lev-

els at various points (when transmitting), are indicated in the dia-

gram.

FIGURE 15. ENHANCED MINI-ACE INTERFACE TO MIL-STD-1553 BUS

Enhanced

MINI-ACE

DATA

BUS

55 Ω

TX/RX

(1:2.5)

11.6 Vpp 28 Vpp

1 FT MAX

(1:1.79)

11.6 Vpp 20 Vpp

(1:1.14)

COUPLING

TRANSFORMER

0.75 Z0

LONG STUB

(TRANSFORMER

COUPLED)

20 FT MAX

28Vpp

SHORT STUB

(DIRECT COUPLED)

NOTE: Z0= 70 TO 85 OHMS

ISOLATION

TRANSFORMER

ISOLATION

TRANSFORMER

7 Vpp

7Vpp

TRANSFORMERS

Beta Transformer Technology Corporation (BTTC), a subsidiary

of DDC, manufactures transformers in a variety of mechanical

configurations with the required turns ratios of 1:2.5 direct cou-

pled, and 1:1.79 transformer coupled. TABLE 46 provides a list-

ing of many of these. TABLE 46 provides a listing of many of

these transformers.

For further information, contact BTTC at 631-244-7393 or at

www.bttc-beta.com.

LPB-5015

B-3310

HLP-6015

Dual epoxy transformer, side by side, surface mount, 0.930" X 0.630", 0.155 max height

Single metal transformer, hermetically sealed, surface mount, 0.630" X 0.630", 0.175" max height

B-3261

HLP-6014

Dual epoxy transformer, side by side, flat pack, 0.930" X 0.630", 0.155 max height

Single metal transformer, hermetically sealed, flat pack, 0.630" X 0.630", 0.175" max height

B-3300Dual epoxy transformer, side by side, through-hole, 0.930" X 0.630", 0.155 max height

TST-9027Dual epoxy transformer, twin stacked, flat pack, 0.625" X 0.625", 0.280" max height

TST-9017Dual epoxy transformer, twin stacked, surface mount, 0.625" X 0.625", 0.280" max height

TST-9007Dual epoxy transformer, twin stacked, 0.625" X 0.625", 0.280" max height

B-3819

LPB-5014

Single epoxy transformer, surface mount, hi-temp solder, 0.625"X 0.625", 0.220"max height.

May be used with BU-6XXXXX4 versions of the Enhanced Mini-ACE.B-3819

Single epoxy transformer, flat pack, 0.625" X 0.625", 0.150" max height

B-3227Single epoxy transformer, surface mount, 0.625" X 0.625", 0.275" max height

B-3231Single epoxy transformer, flat pack, 0.625" X 0.625", 0.275" max height

B-3818

B-3226

Single epoxy transformer, through-hole, 0.625 X 0.625, 0.220"max height.

May be used with BU-6XXXXX4 versions of the Enhanced Mini-ACE.

Single epoxy transformer, through-hole, 0.625 X 0.625, 0.250" max height

BTTC PART NO.TRANSFORMER CONFIGURATION

Single epoxy transformer, surface mount, 0.625" X 0.625", 0.150" max height

TABLE 46. BTTC TRANSFORMERS FOR USE WITH ENHANCED MINI-ACE

NOTES:

1. For the BU-6XXXXX4versions of the Enhanced Mini-ACE, which include the McAir-compatible transceivers, only the B-3818 or B-3819 trans-

formers (shown in bold in the table) may be used.

2. For the BU-6XXXXX3 versions of the Enhanced Mini-ACE with -1553B transceivers, any of the transformers listed in the table may be used.

SIGNAL NAME PIN DESCRIPTION

TX/RX-A (I/O) 5

TX/RX-A (I/O) 7

TX/RX-B (I/O) 13

TX/RX-B (I/O) 16

Analog Transmit/Receive Input/Outputs. Connect directly to 1553 isolation transformers.

1553 ISOLATION TRANSFORMER INTERFACE (4)

TABLE 47. SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS

16-bit bi-directional data bus. This bus interfaces the host processor to the Enhanced Mini-ACE's internal registers and

internal RAM. In addition, in transparent mode, this bus allows data transfers to take place between the internal proto-

col/memory management logic and up to 64K x 16 of external RAM. Most of the time, the outputs for D15 through D0 are

in the high impedance state. They drive outward in the buffered or transparent mode when the host CPU reads the inter-

nal RAM or registers.

Also, in the transparent mode, D15-D0 will drive outward (towards the host) when the protocol/management logic is

accessing (either reading or writing) internal RAM, or writing to external RAM. In the transparent mode, D15-D0 drives

inward when the CPU writes internal registers or RAM, or when the protocol/memory management logic reads external

RAM.

D10

D0 (LSB)

38D1

43D2

44D3

D4 39

45D5

36D6

47D7

46D8 51

52D11

49D12

DATA BUS (16)

48D13

50D14

53D15 (MSB)

DESCRIPTIONPINSIGNAL NAME

+5V Vcc CH A

SIGNAL NAME

72 Channel A transceiver power.

+5V Vcc CH B 20 Channel B transceiver power.

+5V / +3.3V Logic 37 Logic power. For BU-61864/61843/61743, this pin must be connected to +3.3V.

For BU-61865/61845/61745, this pin must be connected to +5V.

+5V RAM 26 For BU-61864 or BU-61865, this pin must be connected to +5V.

Note that for BU-6184X/6174X, this pin assumes the function UPADDREN.

GROUND 17 Ground.

POWER AND GROUND

67 67

DESCRIPTIONBU-61864(5)

(64K RAM) BU-61843(5) /

61743(5)

(4KK RAM)

SIGNAL NAME

PROCESSOR ADDRESS BUS

BU-61843(5) /

61743(5)

(4KK RAM)

DESCRIPTION

70A12 / RTBOOT

71A13 / Vcc -LOGIC

A14 / CLK_SEL_0

A15 / CLK_SEL_1

For BU-61864(5) (64K RAM version), this signal is always configured as address line A12. Refer

to the description for A11-A0 below.

For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "1", this signal

operates as A12.

For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "0", then this

signal functions as RTBOOT. If RTBOOT is connected to logic "0", the Enhanced Mini-ACE will

initialize in RT mode with the Busy status word bit set following power turn-on. If RTBOOT hard-

wired to logic "1", the Enhanced Mini-ACE will initialize in either Idle mode (for an RT-only part), or

in BC mode (for a BC/RT/MT part).

A12

For BU-61864(5) (64K RAM version), this signal is always configured as address line A13. Refer

to the description for A11-A0 below.

For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "1", this signal

operates as A13.

For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "0", then

this signal MUST be connected to +5V/+3.3V-LOGIC (logic "1").

A13

For BU-61864(5) (64K RAM version), this signal is always configured as address line A14. Refer

to the description of A11-A0 below.

For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "1", this signal

operates as A14.

For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "0", then this

signal operates as CLK_SEL_1. In this case, CLK_SEL_1 and CLK_SEL_0 are used to select the

Enhanced Mini-ACE's clock frequency, as defined in the description for A15/CLK_SEL1 above.

A14

For BU-61864(5) (64K RAM version), this signal is always configured as address line A15 (MSB).

Refer to the description for A11-A0 below.

For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "1", this signal

operates as address line A15.

For BU-61843(5)/61743(5) (4K RAM version), if UPADDREN is connected to logic "0", this signal

operates as CLK_SEL_1. In this case, A15/CLK_SEL_1 and A14/CLK_SEL_0 are used to select

the Enhanced Mini-ACE's clock frequency, as follows:

Clock

CLK_SEL_1 CLK_SEL_0 Frequency

0010MHz

0120MHz

1012MHz

1116MHz

A15

BU-61864(5)

(64K RAM)

BU-61843(5) /

61743(5)

(4KK RAM)

PROCESSOR ADDRESS BUS (CONTINUED)

DESCRIPTION

A0(LSB)

A10

A11

SIGNAL NAME

A0(LSB)

A10

Lower 12 bits of 16-bit bi-directional address bus. In both the buffered and transparent modes,

the host CPU accesses the Enhanced Mini-ACE registers and internal RAM by means of A11 -

A0 (4K version). For the 64K versions, A15 - A12 are also used for this purpose.

In buffered mode, A12-A0 (or A15-A0) are inputs only. In the transparent mode, A12-A0 (or

A15-A0) are inputs during CPU accesses and become outputs, driving outward (towards the

CPU) when the 1553 protocol/memory management logic accesses up to 64K words of external

RAM.

In transparent mode, the address bus is driven outward only when the signal DTACK is low

(indicating that the Enhanced Mini-ACE has control of the RAM interface bus) and IOEN is high,

indicating a non-host access. Most of the time, including immediately after power turn-on, A12-

A0 (or A15-A0) will be in high impedance (input) state.

BU-61864(5)

(64K RAM)

A11

Data Transfer Acknowledge or Polarity Select. In 16-bit buffered mode, if POL_SEL is connected to logic "1", RD/WR

should be asserted high (logic "1") for a read operation and low (logic "0") for a write operation. In 16-bit buffered

mode, if POL_SEL is connected to logic "0", RD/WR should be asserted low (logic "0") for a read operation and high

(logic "1") for a write operation.

In 8-bit buffered mode (TRANSPARENT/ BUFFERED = “0" and 16/8 = "0"), POL_SEL input signal used to control the

logic sense of the MSB/LSB signal. If POL_SEL is connected to logic “0", MSB/LSB should be asserted low (logic "0")

to indicate the transfer of the least significant byte and high (logic "1") to indicate the transfer of the most significant

byte. If POL_SEL is connected to logic “1", MSB/LSB should be asserted high (logic "1") to indicate the transfer of the

least significant byte and low (logic "0") to indicate the transfer of the most significant byte.

In transparent mode, active low output signal (DTACK) used to indicate acceptance of the processor/RAM interface bus

in response to a data transfer grant (DTGRT). The Enhanced Mini-ACE's RAM transfers over A15-A0 and D15-D0 will

be framed by the time that DTACK is asserted low.

Data Transfer Grant or Most Significant Byte/Least Significant Byte.

In 8-bit buffered mode, input signal (MSB/LSB) used to indicate which byte is currently being transferred (MSB or LSB).

The logic sense of MSB/LSB is controlled by the POL_SEL input. MSB/LSB is not used in the 16-bit buffered mode.

In transparent mode, active low input signal (DTGRT) asserted in response to the DTREQ output to indicate that control

of the external processor/RAM bus has been transferred from the host processor to the Enhanced Mini-ACE.

Data Transfer Request or Data Bus Select. In buffered mode, input signal 16/8 used to select between the 16 bit data

transfer mode (16/8= "1") and the 8-bit data transfer mode (16/8 = "0").

In transparent mode (16-bit only), active low level output signal DTREQ used to request access to the processor/RAM

interface bus (address and data buses).

Memory Write or Zero Wait . In buffered mode, input signal (ZEROWAIT) used to select between the zero wait mode

(ZEROWAIT = “0") and the non-zero wait mode (ZEROWAIT = "1").

In transparent mode, active low output signal (MEMWR) asserted low during memory write transfers to strobe data into

external RAM (normally connected to the WR input signal on external RAM chips).

Memory Output Enable or Address Latch.

In buffered mode, the ADDR_LAT input is used to configure the buffers for A15-A0, SELECT, MEM/REG, and MSB/LSB

(for 8-bit mode only) in latched mode (when low) or transparent mode (when high).That is, the Enhanced Mini-ACE's

internal transparent latches will track the values on A15-A0, SELECT, MEM/REG, and MSB/LSB when ADDR_LAT is

high, and latch the values when ADDR_LAT goes low.

In general, for interfacing to processors with a non-multiplexed address/data bus, ADDR_LAT should be hardwired to

logic "1". For interfacing to processors with a multiplexed address/data bus, ADDR_LAT should be connected to a signal

that indicates a valid address when ADDR_LAT is logic "1".

In transparent mode, MEMOE output signal is used to enable data outputs for external RAM read cycles (normally con-

nected to the OE input signal on external RAM chips).

Strobe Data. Used in conjunction with SELECT to initiate and control the data transfer cycle between the host proces-

sor and the ENHANCED MINI-ACE. STRBD must be asserted low through the full duration of the transfer cycle.

Read/Write. For a host processor access, RD/WR selects between reading and writing. In the 16-bit buffered mode, if

POL_SEL is logic "0, then RD/WR should be low (logic “0") for read accesses and high (logic "1") for write accesses. If

POL_SEL is logic "1", or the interface is configured for a mode other than 16-bit buffered mode, then RD/WR is high

(logic "1") for read accesses and low (logic "0") for write accesses.

Generally connected to a CPU address decoder output to select the Enhanced Mini-ACE for a transfer to/from either

RAM or register.

DESCRIPTION

PROCESSOR INTERFACE CONTROL

POL_SEL (1) /

DTACK (0)

MSB / LSB (1) /

DTGRT (1)

16 / 8 (1) /

DTREQ (0)

ZEROWAIT (1) /

MEMWR (0)

ADDR_LAT(1) /

MEMOE (0)

STRBD (1)

RD / WR

SELECT (1)

SIGNAL NAME

DESCRIPTION

PROCESSOR INTERFACE CONTROL

SIGNAL NAME

I/O Enable.Tri-state control for external address and data buffers. Generally not used in buffered mode. When low, indi-

cates that the Enhanced Mini-ACE is currently performing a host access to an internal register, or internal or (for trans-

parent mode) external RAM. In transparent mode, IOEN (low) should be used to enable external address and data bus

tri-state buffers.

IOEN(0) 58

Handshake output to host processor. For a nonzero wait state read access, READYD is asserted at the end of a host

transfer cycle to indicate that data is available to be read on D15 through D0 when asserted (low). For a nonzero wait

state write cycle, READYD is asserted at the end of the cycle to indicate that data has been transferred to a register or

RAM location. For both nonzero wait reads and writes, the host must assert STRBD low until READYD is asserted low.

In the (buffered) zero wait state mode, this output is normally logic "0", indicating that the Enhanced Mini-ACE is in a

state ready to accept a subsequent host transfer cycle. In zero wait mode, READYD will transition from low to high during

(or just after) a host transfer cycle, when the Enhanced Mini-ACE initiates its internal transfer to or from registers or inter-

nal RAM.When the Enhanced Mini-ACE completes its internal transfer, READYD returns to logic "0", indicating it is

ready for the host to initiate a subsequent transfer cycle.

READYD 56

Used to select between the buffered mode (when strapped to logic “0”) and transparent/DMA mode (when strapped to

logic “1") for the host processor interface.

TRANSPARENT /

BUFFERED 55

Memory Enable or Trigger Select input. In 8-bit buffered mode, input signal (TRIG-SEL) used to select the order in which

byte pairs are transferred to or from the Enhanced MINI-ACE by the host processor. In the 8-bit buffered mode,

TRIG_SEL should be asserted high (logic 1) if the byte order for both read operations and write operations is MSB fol-

lowed by LSB. TRIG_SEL should be asserted low (logic 0) if the byte order for both read operations and write opera-

tions is LSB followed by MSB.

This signal has no operation in the 16-bit buffered mode (it does not need to be connected).

In transparent mode, active low input MEMENA_IN, used as a Chip Select (CS) input to the Enhanced Mini-ACE's inter-

nal shared RAM. If only internal RAM is used, should be connected directly to the output of a gate that is OR'ing the

DTACK and IOEN output signals.

Memory/Register. Generally connected to either a CPU address line or address decoder output. Selects between mem-

ory access (MEM/REG = "1") or register access (MEM/REG = "0").

Subsystem Flag (RT) or External Trigger (BC/Word Monitor) input. In RT mode, if this input is asserted low, the

Subsystem Flag bit will be set in the ENHANCED MINI-ACE's RT Status Word. If the SSFLAG input is logic "0" while bit

8 of Configuration Register #1 has been programmed to logic "1" (cleared), the Subsystem Flag RT Status Word bit will

become logic "1," but bit 8 of Configuration Register #1, SUBSYSTEM FLAG, will return logic "1" when read. That is, the

sense on the SSFLAG input has no effect on the SUBSYSTEM FLAG register bit.

In the non-enhanced BC mode, this signal operates as an External Trigger input. In BC mode, if the external BC Start

option is enabled (bit 7 of Configuration Register #1), a low to high transition on this input will issue a BC Start com-

mand, starting execution of the current BC frame.

In the enhanced BC mode, during the execution of a Wait for External Trigger (WTG) instruction, the Enhanced Mini-ACE

BC will wait for a low-to-high transition on EXT_TRIG before proceeding to the next instruction.

In the Word Monitor mode, if the external trigger is enabled (bit 7 of Configuration Register #1), a low to high transition

on this input will initiate a monitor start.

This input has no effect in Message Monitor mode.

TRIG_SEL (1) /

MEMENA_IN (1)

MEM / REG(1)

SSFLAG (1) /

EXT_TRIG(1)

DESCRIPTION

RTAD0 (LSB) (1)

RTAD1 (1)

RTAD2 (1)

RTAD3 (1)

RTAD4 (MSB) (1)

SIGNAL NAME

RT ADDRESS

RT Address Latch. Input signal used to control the Enhanced MINI-ACE's internal RT address latch. If RT_AD_LAT is

connected to logic "0", then the Enhanced Mini-ACE RT is configured to accept a hardwired (transparent) RT address

from RTAD4-RTAD) and RTADP.

If RT_AD_LAT is initially logic "0", and then transitions to logic "1", the values presented on RTAD4-RTAD0 and RTADP

will be latched internally on the rising edge of RT_AD_LAT.

If RT_AD_LAT is connected to logic "1", then the Enhanced Mini-ACE's RT address is latchable under host processor

control. In this case, there are two possibilities: (1) If bit 5 of Configuration Register #6, RT ADDRESS SOURCE, is pro-

grammed to logic "0" (default), then the source of the RT Address is the RTAD4-RTAD0 and RTADP input signals; (2) If

RT ADDRESS SOURCE is programmed to logic "1", then the source of the RT Address is the lower 6 bits of the proces-

sor data bus, D5-D1 (for RTAD4-0) and D0 (for RTADP).

In either of these two cases (with RT_AD_LAT = "1"), the processor will cause the RT address to be latched by: (1) writ-

ing bit 15 of Configuration Register #3, ENHANCED MODE, to logic "1"; (2) writing bit 3 of Configuration Register #4,

LATCH RT ADDRESS WITH CONFIGURATION REGISTER #5, to logic "1"; and (3) writing to Configuration Register #5.

In the case of RT ADDRESS SOURCE = "1", then the values of RT address and RT address parity must be written to

the lower 6 bits of Configuration Register #5, via D5-D0. In the case where RT ADDRESS SOURCE = "0", the bit values

presented on D5-D0 become "don't care" .

RT_AD_LAT (1) 31

Remote Terminal Address Parity. This input signal must provide an odd parity sum with RTAD4-RTAD0 in order for the

RT to respond to non-broadcast commands.That is, there must be an odd number of logic "1"s from among RTAD-4-

RTAD0 and RTADP.

RT Address inputs. If bit 5 of Configuration Register #6, RT ADDRESS SOURCE, is programmed to logic "0" (default),

then the Enhanced Mini-ACE's RT address is provided by means of these 5 input signals. In addition, if RT ADDRESS

SOURCE is logic "0", the source of RT address parity is RTADP.

There are many methods for using these input signals for designating the Enhanced Mini-ACE's RT address. For details,

refer to the description of RT_AD_LAT.

If RT ADDRESS SOURCE is programmed to logic "1", then the Enhanced Mini-ACE's source for its RT address and par-

ity is under software control, via data lines D5-D0. In this case, the RTAD4-RTAD0 and RTADP signals are not used.

RTADP (1) 40

TX_INH_B (1)

TX_INH_A (1)

MSTCLR(1)

CLOCK_IN (1)

INCMD (O) /

MCRST (O)

INT (0)

UPADDREN

Transmitter inhibit inputs for the Channel A and Channel B MIL-STD-1553 transmitters.

For normal operation, these inputs should be connected to logic "0".To force a shutdown

of Channel A and/or Channel B, a value of logic "1" should be applied to the respective

TX_INH input.

Master Clear. Negative true Reset input, normally asserted low following power turn-on.

20 MHz, 16 MHz, 12 MHz, or 10 MHz clock input.

In-command or Mode Code Reset.The function of this pin is controlled by bit 0 of

Configuration Register #7, MODE CODE RESET/INCMD SELECT.

If this register bit is logic "0" (default), INCMD will be active on this pin. For BC, RT, or

Selective Message Monitor modes, INCMD is asserted low whenever a message is being

processed by the Enhanced Mini-ACE. In Word Monitor mode, INCMD will be asserted

low for as long as the monitor is online.

For RT mode, if MODE CODE RESET/INCMD SELECT is programmed to logic "1",

MCRST will be active. In this case, MCRST will be asserted low for two clock cycles fol-

lowing receipt of a Reset remote terminal mode command.

In BC or Monitor modes, if MODE CODE RESET/INCMD SELECT is logic "1", this signal

is inoperative; i.e., in this case, it will always output a value of logic "1".

Interrupt Request output. If the LEVEL/PULSE interrupt bit (bit 3) of Configuration

INT to signal an interrupt request.

If LEVEL/PULSE is high, a low level interrupt request output will be asserted on INT.The

level interrupt will be cleared (high) after either: (1) The processor writes a value of logic

"1" to INTERRUPT RESET, bit 2 of the Start/Reset Register; or (2) If bit 4 of

Configuration Register #2, INTERRUPT STATUS AUTO-CLEAR is logic "1", then it will

only be necessary to read the Interrupt Status Register (#1 and/or #2) that is requesting

an interrupt that has been enabled by the corresponding Interrupt Mask Register.

However, for the case where both Interrupt Status Register #1 and Interrupt Status

interrupt status registers in order to clear INT.

For BU-61864/61865, this pin is +5V-RAM and MUST be connected to +5V.

For BU-61743(5) and 61843(5), this signal is used to control the function of the upper 4

address inputs (A15-A12). For these versions of Enhanced Mini-ACE, if UPADDREN is

connected to logic "1", then these four signals operate as address lines A15-A12.

For BU-61843(5)/61743(5), if UPADDREN is connected to logic "0", then A15 and A14

function as CLK_SEL_1 and CLK_SEL_0 respectively; A13 MUST be connected to Vcc-

LOGIC (+5V or +3.3V); and A12 functions as RTBOOT.

BU-61843(5) /

61743(5)

(4KK RAM)

BU-61864(5)

(64K RAM)

MISCELLANEOUS

SIGNAL NAME

DESCRIPTION

For factory test only. Do not connect for normal operation.

XCVR_TP (ZAP VOLTB)

XCVR_TP (RESET)

P2(*)

P3(*)

P4(*)

XCVR_TP (READOUTB)

XCVR_TP (CLOCK)

XCVR_TP (READOUTA)

FACTORY TEST

XCVR_TP (ZAP VOLTA) P1(*)

SIGNAL NAME PIN

P6(*)

P5(*)

(*) Note that the Test Output pins are recessed pads located on the bottom of the package.

D138

RTADP

QFP

RTAD1

D12

BU-61864(5)

BC/RT/MT

(64K RAM)

D13

PACKAGE

DO42

D243

A13/+5V/3.3V LOGIC

D344

RTAD1

D1348

TABLE 48. PACKAGE PINOUTS

BU-61843(5)

BC / RT / MT, (4K RAM)

BU-61743(5)

RT ONLY, (4K RAM)

RTADP

PGA

(NOTE1)

D1249

INT

READYD

TRANSPARENT/

BUFFERED

D10

D1450

D15

D951 B9

D1152

D15

D10

D11

TRANSPARENT/

BUFFERED

D14

READYD56 B8

INT57 C8

RD / WR

STRBD

SELECT

TX_INH_B

TX_INH_A

IOEN58

TX_INH_A

TX_INH_B

IOEN

SELECT

STRBD62 A6

RD / WR63 A5

LOGIC GND

A15/CLK_SEL_1

LOGIC GND

MSB/LSB/DTGRTMSB/LSB/DTGRT

LOGIC GND

A1566 C5

LOGIC GND67 B6

A12/RTBOOT

A5A5

A1270 B3

A1371 B1

+5V Vcc-CH. A+5V Vcc-CH. A72 J3

MEM/REG1

MSTCLR

A11

QFP

MEM/REG

A10

BU-61864(5)

BC/RT/MT

(64K RAM)

PACKAGE

TX/RX_A5

A14/CLK_SEL_0

A86

RTAD3

TX/RX_A7

A14

TX/RX_A

A10

A711

TABLE 48. PACKAGE PINOUTS

BU-61843(5)

BC / RT / MT, (4K RAM)

BU-61743(5)

RT ONLY, (4K RAM)

A11

PGA

(NOTE1)

A212

MSTCLR

+5V Vcc-CH. B

LOGIC GND

TX/RX_B13

TX/RX-B

ADDR_LAT/MEMOE14 G4

A015

TX/RX-B

LOGIC GND

ADDR_LAT/MEMOE

TX/RX_B

LOGIC GND19 J8

+5V Vcc-CH. B20 A9

UPADDREN

INCMD/MCRST

8/16-BIT/DTREQ

ZEROWAIT/MEMWR

RTAD221

ZEROWAIT/MEMWR

RTAD2

8/16-BIT/DTREQ

INCMD/MCRST25 H3

+5V RAM26 H4

CLOCK_IN

POL_SEL/DTACK

TRIG_SEL/MEMENA_IN

A1A1

TRIG_SEL/MEMENA_IN

POL_SEL/DTACK29 J6

CLOCK_IN30 H6

RTAD0

SSFLAG/ EXT_TRIG

RT_AD_LATRT_AD_LAT

SSFLAG/ EXT_TRIG

RTAD033 H7

RTAD334 G8

+5V/3.3V LOGIC

RTAD4RTAD4

+5V/3.3V LOGIC37 D3

TABLE 48. PACKAGE PINOUTS

BU-61864(5)

BC/RT/MT

(64K RAM)

PACKAGE BU-61843(5)

BC / RT / MT, (4K RAM)

BU-61743(5)

RT ONLY, (4K RAM)

QFP PGA

(NOTE1)

P1 ** D4 XCVR TP

(ZAP VOLTA) XCVR TP

(ZAP VOLTA)

P2 ** F5 XCVR TP (READOUTB) XCVR TP (READOUTB)

P3 ** D5 XCVR TP (READOUTA) XCVR TP (READOUTA)

N/A

P4 **

GND

XCVR TP(CLOCK)

GND

XCVR TP(CLOCK)

N/A

P5 **

GND

XCVR TP (RESET_L)

GND

XCVR TP (RESET_L)

N/A

P6 **

GND

XCVR TP

(ZAP VOLTB)

GND

XCVR TP

(ZAP VOLTB)

** Note that the Test Output pins on the flat pack are pads located on the

bottom of the package.

NOTE 1:This column is shown for reference only.There is no PGA pack-

age for the initial product release.

1.000 SQ ±0.010

(25.400 ±0.254)

VIEW "B"

0.018 ±0.002

(0.457 ±0.051) 0.050 ±0.005

(1.270 ±0.127)

Notes:

1) Dimensions are in inches (mm).

2) Package Material: Alumina (AL2O3)

3) Lead Material: Kovar, Plated by 50µ in. minimum nickel under 60µ in. minimum gold.

4) There are 6 test pads located on the bottom of the package. These pads are recessed

so as not to interfere when mounting the hybrid There are no user connections to these pads.

VIEW "B"

2.000 ±0.015

(50.800 ±0.381)

0.500 ±0.005

(12.70 ±0.127)

0.200 ±0.005

(5.080 ±0.127)

0.850 ±0.008

(21.590 ±0.203)

0.010 ±0.002

(0.254 ±0.051)

0.035 ±0.005

(0.889 ±0.127) 0.040 ±0.004

(1.016 ±0.102)

0.050 ±0.005

(1.270 ±0.127)

0.090 ±0.010

(2.286 ±0.254)

0.155 MAX

(3.94)

BOTTOM VIEW

SIDE VIEW

VIEW "A"

INDEX DENOTES

PIN NO. 1

P2 P1

P6 P5 P4 P3

0.100 DIA.

(2.540) (see note 4)

FIGURE 16. MECHANICAL OUTLINE DRAWING FOR 72-LEAD FLATPACK

1.00 SQ ±0.01

(25.40 ±0.25)

VIEW "B"

Notes:

1) Dimensions are in inches (mm).

2) Package Material: Alumina (AL2O3)

3) Lead Material: Kovar, Plated by 50µ in.

minimum nickel under 60µ in. minimum gold.

4) There are 6 test pads located on the bottom of

the package. These pads are recessed so as

not to interfere when mounting the hybrid.

There are no user connections to these pads.

VIEW "B"

1.38 ±0.02

(35.05 ±0.51)

0.19 ±0.01

(4.83 ±0.25)

0.850 ±0.008

(21.590 ±0.203)

0.08 MIN FLAT

(2.03)

0.155 MAX

(3.94)

0.018 ±0.002

(0.457 ±0.051) 0.050 ±0.005

(1.270 ±0.127)

BOTTOM VIEW

SIDE VIEW

VIEW "A"

INDEX DENOTES

PIN NO. 1

P2 P1

P6 P5 P4 P3

0.100 DIA.

(2.540) (see note 4)

0.010 ±0.002

(0.254 ±0.051)

0.012 R. MAX

(0.305 R.)

0.05 MIN FLAT

(1.27)

0.006 -0.004,+0.010

(0.152 -0.100,+ 0.254)

1.024 MAX TYP.

(26.010)

FIGURE 17. MECHANICAL OUTLINE DRAWING FOR 72-PIN GULL LEAD PACKAGE

ORDERING INFORMATION

BU-61745F3-120X

Supplemental Process Requirements:

S = Pre-Cap Source Inspection

L = Pull Test

Q = Pull Test and Pre-Cap Inspection

K = One Lot Date Code

W = One Lot Date Code and PreCap Source

Y = One Lot Date Code and 100% Pull Test

Z = One Lot Date Code, PreCap Source and 100% Pull Test

Blank = None of the Above

Test Criteria:

0 = Standard Testing

2 = MIL-STD-1760 Amplitude Compliant

Process Requirements:

0 = Standard DDC practices, no Burn-In

1 = MIL-PRF-38534 Compliant

2=B*

3 = MIL-PRF-38534 Compliant with PIND Testing

4 = MIL-PRF-38534 Compliant with Solder Dip

5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip

6 = B* with PIND Testing

7 = B* with Solder Dip

8 = B* with PIND Testing and Solder Dip

9 = Standard DDC Processing with Solder Dip, no Burn-In

Temperature Range/Data Requirements:

1 = -55°C to +125°C

2 = -40°C to +85°C

3 = 0°C to +70°C

4 = -55°C to +125°C with Variables Test Data

5 = -40°C to +85°C with Variables Test Data

6 = Custom Part (Reserved)

7 = Custom Part (Reserved)

8 = 0°C to +70°C with Variables Test Data

Voltage/Transceiver Option:

3 = +5 Volts rise/fall times = 100 to 300 ns (-1553B)

4 = +5 Volts rise/fall times = 200 to 300 ns (-1553B and McAir compatible)

Package Type:

F = Flat Pack

G = “Gull Wing” (Formed Lead)

Logic / RAM Voltage

3 = 3.3 Volt (Applicable only for BU-61743 and BU-61843)

4 = 3.3 and 5 Volt (Applicable only for BU-61684)

5=5Volt

Product Type:

BU-6174 = RT only with 4K RAM

BU-6184 = BC /RT / MT with 4K x 16 RAM

BU-6186 = BC /RT / MT with 64K x 17 RAM

—1015, Table 1BURN-IN A2001CONSTANT ACCELERATION C1010TEMPERATURE CYCLE A and C1014SEAL —2009, 2010, 2017, and 2032INSPECTION CONDITION(S)METHOD(S)

MIL-STD-883

TEST

STANDARD DDC PROCESSING

NOTES

A-01/00-500 PRINTED IN THE U.S.A.

ILC DATA DEVICE CORPORATION

REGISTERED TO ISO 9001

FILE NO. A5976

The information in this data sheet is believed to be accurate; however, no responsibility is

assumed by Data Device Corporation for its use, and no license or rights are

granted by implication or otherwise in connection therewith.

Specifications are subject to change without notice.

105 Wilbur Place, Bohemia, NewYork 11716-2482

For Technical Support - 1-800-DDC-5757 ext. 7382 or 7234

Headquarters - Tel: (631) 567-5600, Fax: (631) 567-7358

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