SERIAL PRESENCE DETECT PC100 Unbuffered DIMM
Rev 0.1 Apr.
2000
PC100 Unbuffered DIMM(168pin)
SPD Specification(128Mb C-die base)
Rev. 0.1
Apr. 2000
SERIAL PRESENCE DETECT PC100 Unbuffered DIMM
Rev 0.1 Apr.
2000
M366S1724CT0-C1H/C1L
Byte # Function Described Function Supported Hex value Note
-1H -1L -1H -1L
0# of bytes written into serial memory at module manufacturer 128bytes 80h
1Total # of bytes of SPD memory device 256bytes (2K-bit) 08h
2Fundamental memory type SDRAM 04h
3# of row address on this assembly 12 0Ch 1
4# of column address on this assembly 909h 1
5# of module Rows on this assembly 2 Rows 02h
6Data width of this assembly 64 bits 40h
7...... Data width of this assembly -00h
8Voltage interface standard of this assembly LVTTL 01h
9SDRAM cycle time @CAS latency of 3 10ns 10ns A0h A0h 2
10 SDRAM access time from clock @CAS latency of 3 6ns 6ns 60h 60h 2
11 DIMM configuration type Non parity 00h
12 Refresh rate & type 15.625us, support self refresh 80h
13 Primary SDRAM width x16 10h
14 Error checking SDRAM width None 00h
15 Minimum clock delay for back-to-back random column address tCCD = 1CLK 01h
16 SDRAM device attributes : Burst lengths supported 1, 2, 4, 8 & full page 8Fh
17 SDRAM device attributes : # of banks on SDRAM device 4 banks 04h
18 SDRAM device attributes : CAS latency 2 & 3 06h
19 SDRAM device attributes : CS latency 0 CLK 01h
20 SDRAM device attributes : Write latency 0 CLK 01h
21 SDRAM module attributes Non-buffered, non-registered
& redundant addressing 00h
22 SDRAM device attributes : General +/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge 0Eh
23 SDRAM cycle time @CAS latency of 2 10ns 12ns A0h C0h 2
24 SDRAM access time from clock @CAS latency of 2 6ns 7ns 60h 70h 2
25 SDRAM cycle time @CAS latency of 1 - - 00h 00h
26 SDRAM access time from clock @CAS latency of 1 - - 00h 00h
27 Minimum row precharge time (=tRP)20ns 20ns 14h 14h
28 Minimum row active to row active delay (tRRD)20ns 20ns 14h 14h
29 Minimum RAS to CAS delay (=tRCD)20ns 20ns 14h 14h
30 Minimum activate precharge time (=tRAS)50ns 50ns 32h 32h
31 Module Row density 2 Rows of 64MB 10h
32 Command and address signal input setup time 2ns 2ns 20h 20h
33 Command and address signal input hold time 1ns 1ns 10h 10h
34 Data signal input setup time 2ns 2ns 20h 20h
• Organization : 16Mx64
• Composition : 8Mx16 *8
• Used component part # : K4S281632C-TC1H/C1L
• # of rows in module : 2 Rows
• # of banks in component : 4 banks
• Feature : 1,375mil height & double sided component
• Refresh : 4K/64ms
• Contents ;
SERIAL PRESENCE DETECT PC100 Unbuffered DIMM
Rev 0.1 Apr.
2000
Byte # Function Described Function Supported Hex value Note
-1H -1L -1H -1L
35 Data signal input hold time 1ns 1ns 10h 10h
36~61 Superset information (maybe used in future) -00h
62 SPD data revision code PC100 SPD Spec. Ver. 1.2A 12h
63 Checksum for bytes 0 ~ 62 -0Eh 3Eh
64 Manufacturer JEDEC ID code Samsung CEh
65~71 ...... Manufacturer JEDEC ID code Samsung 00h
72 Manufacturing location Onyang Korea 01h
73 Manufacturer part # (Memory module) M4Dh
74 Manufacturer part # (DIMM configuration) 333h
75 Manufacturer part # (Data bits) Blank 20h
76 ...... Manufacturer part # (Data bits) 636h
77 ...... Manufacturer part # (Data bits) 636h
78 Manufacturer part # (Mode & operating voltage) S53h
79 Manufacturer part # (Module depth) 131h
80 ...... Manufacturer part # (Module depth) 737h
81 Manufacturer part # (Refresh, # of banks in Comp. & interface) 232h
82 Manufacturer part # (Composition component) 434h
83 Manufacturer part # (Component revision) C43h
84 Manufacturer part # (Package type) T54h
85 Manufacturer part # (PCB revision & type) 030h
86 Manufacturer part # (Hyphen) " - " 2Dh
87 Manufacturer part # (Power) C43h
88 Manufacturer part # (Minimum cycle time) 1 1 31h 31h
89 Manufacturer part # (Minimum cycle time) HL48h 4Ch
90 Manufacturer part # (TBD) Blank 20h
91 Manufacturer revision code (For PCB) 030h
92 ...... Manufacturer revision code (For component) C-die (4th Gen.) 43h
93 Manufacturing date (Week) - - 3
94 Manufacturing date (Year) - - 3
95~98 Assembly serial # - - 4
99~125 Manufacturer specific data (may be used in future) Undefined -5
126 System frequency for 100MHz 100MHz 64h
127 PC100 specification details Detailed 100MHz Information FFh FDh
128+ Unused storage locations Undefined -5
1. The bank select address is excluded in counting the total # of addresses.
2. This value is based on the component specification.
3. These bytes are programmed by code of Date Week & Date Year with BCD format.
4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #.
5. These bytes are Undefined and can be used for Samsung ′s own purpose.
Note :
SERIAL PRESENCE DETECT PC100 Unbuffered DIMM
Rev 0.1 Apr.
2000
M366S3323CT0-C1H/C1L
Byte # Function Described Function Supported Hex value Note
-1H -1L -1H -1L
0# of bytes written into serial memory at module manufacturer 128bytes 80h
1Total # of bytes of SPD memory device 256bytes (2K-bit) 08h
2Fundamental memory type SDRAM 04h
3# of row address on this assembly 12 0Ch 1
4# of column address on this assembly 10 0Ah 1
5# of module Rows on this assembly 2 Rows 02h
6Data width of this assembly 64 bits 40h
7...... Data width of this assembly -00h
8Voltage interface standard of this assembly LVTTL 01h
9SDRAM cycle time @CAS latency of 3 10ns 10ns A0h A0h 2
10 SDRAM access time from clock @CAS latency of 3 6ns 6ns 60h 60h 2
11 DIMM configuration type Non parity 00h
12 Refresh rate & type 15.625us, support self refresh 80h
13 Primary SDRAM width x8 08h
14 Error checking SDRAM width None 00h
15 Minimum clock delay for back-to-back random column address tCCD = 1CLK 01h
16 SDRAM device attributes : Burst lengths supported 1, 2, 4, 8 & full page 8Fh
17 SDRAM device attributes : # of banks on SDRAM device 4 banks 04h
18 SDRAM device attributes : CAS latency 2 & 3 06h
19 SDRAM device attributes : CS latency 0 CLK 01h
20 SDRAM device attributes : Write latency 0 CLK 01h
21 SDRAM module attributes Non-buffered, non-registered
& redundant addressing 00h
22 SDRAM device attributes : General +/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge 0Eh
23 SDRAM cycle time @CAS latency of 2 10ns 12ns A0h C0h 2
24 SDRAM access time from clock@CAS latency of 2 6ns 7ns 60h 70h 2
25 SDRAM cycle time @CAS latency of 1 - - 00h 00h
26 SDRAM access time from clock@CAS latency of 1 - - 00h 00h
27 Minimum row precharge time (=tRP)20ns 20ns 14h 14h
28 Minimum row active to row active delay (tRRD)20ns 20ns 14h 14h
29 Minimum RAS to CAS delay (=tRCD)20ns 20ns 14h 14h
30 Minimum activate precharge time (=tRAS)50ns 50ns 32h 32h
31 Module Row density 2 Rows of 128MB 20h
32 Command and address signal input setup time 2ns 2ns 20h 20h
33 Command and address signal input hold time 1ns 1ns 10h 10h
34 Data signal input setup time 2ns 2ns 20h 20h
• Organization : 32Mx64
• Composition : 16Mx8 *16
• Used component part # : K4S280832C-TC1H/C1L
• # of rows in module : 2 Rows
• # of banks in component : 4 banks
• Feature : 1,375mil height & double sided component
• Refresh : 4K/64ms
• Contents ;
SERIAL PRESENCE DETECT PC100 Unbuffered DIMM
Rev 0.1 Apr.
2000
Byte # Function Described Function Supported Hex value Note
-1H -1L -1H -1L
35 Data signal input hold time 1ns 1ns 10h 10h
36~61 Superset information (maybe used in future) -00h
62 SPD data revision code PC100 SPD Spec. Ver. 1.2A 12h
63 Checksum for bytes 0 ~ 62 -17h 47h
64 Manufacturer JEDEC ID code Samsung CEh
65~71 ...... Manufacturer JEDEC ID code Samsung 00h
72 Manufacturing location Onyang Korea 01h
73 Manufacturer part # (Memory module) M4Dh
74 Manufacturer part # (DIMM configuration) 333h
75 Manufacturer part # (Data bits) Blank 20h
76 ...... Manufacturer part # (Data bits) 636h
77 ...... Manufacturer part # (Data bits) 636h
78 Manufacturer part # (Mode & operating voltage) S53h
79 Manufacturer part # (Module depth) 333h
80 ...... Manufacturer part # (Module depth) 333h
81 Manufacturer part # (Refresh, # of banks in Comp. & interface) 232h
82 Manufacturer part # (Composition component) 333h
83 Manufacturer part # (Component revision) C43h
84 Manufacturer part # (Package type) T54h
85 Manufacturer part # (PCB revision & type) 030h
86 Manufacturer part # (Hyphen) " - " 2Dh
87 Manufacturer part # (Power) C43h
88 Manufacturer part # (Minimum cycle time) 1 1 31h 31h
89 Manufacturer part # (Minimum cycle time) HL48h 4Ch
90 Manufacturer part # (TBD) Blank 20h
91 Manufacturer revision code (For PCB) 030h
92 ...... Manufacturer revision code (For component) C-die (4th Gen.) 43h
93 Manufacturing date (Week) - - 3
94 Manufacturing date (Year) - - 3
95~98 Assembly serial # - - 4
99~125 Manufacturer specific data (may be used in future) Undefined -5
126 System frequency for 100MHz 100MHz 64h
127 PC100 specification details Detailed 100MHz Information FFh FDh
128+ Unused storage locations Undefined -5
1. The bank select address is excluded in counting the total # of addresses.
2. This value is based on the component specification.
3. These bytes are programmed by code of Date Week & Date Year with BCD format.
4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #.
5. These bytes are Undefined and can be used for Samsung ′s own purpose.
Note :
SERIAL PRESENCE DETECT PC100 Unbuffered DIMM
Rev 0.1 Apr.
2000
M374S3323CT0-C1H/C1L
Byte # Function Described Function Supported Hex value Note
-1H -1L -1H -1L
0# of bytes written into serial memory at module manufacturer 128bytes 80h
1Total # of bytes of SPD memory device 256bytes (2K-bit) 08h
2Fundamental memory type SDRAM 04h
3# of row address on this assembly 12 0Ch 1
4# of column address on this assembly 10 0Ah 1
5# of module Rows on this assembly 2 Rows 02h
6Data width of this assembly 72 bits 48h
7...... Data width of this assembly -00h
8Voltage interface standard of this assembly LVTTL 01h
9SDRAM cycle time @CAS latency of 3 10ns 10ns A0h A0h 2
10 SDRAM access time from clock @CAS latency of 3 6ns 6ns 60h 60h 2
11 DIMM configuration type ECC 02h
12 Refresh rate & type 15.625us, support self refresh 80h
13 Primary SDRAM width x8 08h
14 Error checking SDRAM width x8 08h
15 Minimum clock delay for back-to-back random column address tCCD = 1CLK 01h
16 SDRAM device attributes : Burst lengths supported 1, 2, 4, 8 & full page 8Fh
17 SDRAM device attributes : # of banks on SDRAM device 4 banks 04h
18 SDRAM device attributes : CAS latency 2 & 3 06h
19 SDRAM device attributes : CS latency 0 CLK 01h
20 SDRAM device attributes : Write latency 0 CLK 01h
21 SDRAM module attributes Non-buffered, non-registered
& redundant addressing 00h
22 SDRAM device attributes : General +/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge 0Eh
23 SDRAM cycle time @CAS latency of 2 10ns 12ns A0h C0h 2
24 SDRAM access time from clock @CAS latency of 2 6ns 7ns 60h 70h 2
25 SDRAM cycle time @CAS latency of 1 - - 00h 00h
26 SDRAM access time from clock @CAS latency of 1 - - 00h 00h
27 Minimum row precharge time (=tRP)20ns 20ns 14h 14h
28 Minimum row active to row active delay (tRRD)20ns 20ns 14h 14h
29 Minimum RAS to CAS delay (=tRCD)20ns 20ns 14h 14h
30 Minimum activate precharge time (=tRAS)50ns 50ns 32h 32h
31 Module Row density 2 Rows of 128MB 20h
32 Command and address signal input setup time 2ns 2ns 20h 20h
33 Command and address signal input hold time 1ns 1ns 10h 10h
34 Data signal input setup time 2ns 2ns 20h 20h
• Organization : 32Mx72
• Composition : 16Mx8 *18
• Used component part # : K4S280832C-TC1H/C1L
• # of rows in module : 2 Rows
• # of banks in component : 4 banks
• Feature : 1,375mil height & double sided component
• Refresh : 4K/64ms
• Contents ;
SERIAL PRESENCE DETECT PC100 Unbuffered DIMM
Rev 0.1 Apr.
2000
Byte # Function Described Function Supported Hex value Note
-1H -1L -1H -1L
35 Data signal input hold time 1ns 1ns 10h 10h
36~61 Superset information (maybe used in future) -00h
62 SPD data revision code PC100 SPD Spec. Ver. 1.2A 12h
63 Checksum for bytes 0 ~ 62 -29h 59h
64 Manufacturer JEDEC ID code Samsung CEh
65~71 ...... Manufacturer JEDEC ID code Samsung 00h
72 Manufacturing location Onyang Korea 01h
73 Manufacturer part # (Memory module) M4Dh
74 Manufacturer part # (DIMM configuration) 333h
75 Manufacturer part # (Data bits) Blank 20h
76 ...... Manufacturer part # (Data bits) 737h
77 ...... Manufacturer part # (Data bits) 434h
78 Manufacturer part # (Mode & operating voltage) S53h
79 Manufacturer part # (Module depth) 333h
80 ...... Manufacturer part # (Module depth) 333h
81 Manufacturer part # (Refresh, # of banks in Comp. & interface) 232h
82 Manufacturer part # (Composition component) 333h
83 Manufacturer part # (Component revision) C43h
84 Manufacturer part # (Package type) T54h
85 Manufacturer part # (PCB revision & type) 030h
86 Manufacturer part # (Hyphen) " - " 2Dh
87 Manufacturer part # (Power) C43h
88 Manufacturer part # (Minimum cycle time) 1 1 31h 31h
89 Manufacturer part # (Minimum cycle time) HL48h 4Ch
90 Manufacturer part # (TBD) Blank 20h
91 Manufacturer revision code (For PCB) 030h
92 ...... Manufacturer revision code (For component) C-die (4th Gen.) 43h
93 Manufacturing date (Week) - - 3
94 Manufacturing date (Year) - - 3
95~98 Assembly serial # - - 4
99~125 Manufacturer specific data (may be used in future) Undefined -5
126 System frequency for 100MHz 100MHz 64h
127 PC100 specification details Detailed 100MHz Information FFh FDh
128+ Unused storage locations Undefined -5
1. The bank select address is excluded in counting the total # of addresses.
2. This value is based on the component specification.
3. These bytes are programmed by code of Date Week & Date Year with BCD format.
4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #.
5. These bytes are Undefined and can be used for Samsung ′s own purpose.
Note :
