Features Description The FAN3100 2 A gate driver is designed to drive an Nchannel enhancement-mode MOSFET in low -side sw itching applications by providing high peak current pulses during the short sw itching intervals. The driver is available w ith either TTL (FAN3100T) or CMOS (FAN3100C) input thresholds. Internal circuitry provides an under-voltage lockout function by holding the output LOW until the supply voltage is w ithin the operating range. The FAN3100 delivers fast MOSFET sw itching performance, w hich helps maximize efficiency in highfrequency pow er converter designs. 3 A Peak Sink/Source at V DD = 12 V 4.5 to 18 V Operating Range 2.5 A Sink / 1.8 A Source at V OUT = 6 V Dual-Logic Inputs Allow Configuration as Non-Inverting or Inverting w ith Enable Function Internal Resistors Turn Driver Off If No Inputs 13 ns Typical Rise Time and 9 ns Typical Fall-Time w ith 1 nF Load Choice of TTL or CMOS Input Thresholds MillerDriveTM Technology Typical Propagation Delay Time Under 20 ns w ith Input Falling or Rising 6-Lead, 2x2 mm MLP or 5-Pin, SOT23 Packages Rated from -40C to 125C Ambient Applications Sw itched-Mode Pow er Supplies (SMPS) High-Efficiency MOSFET Sw itching Synchronous Rectifier Circuits FAN3100 drivers incorporate MillerDriveTM architecture for the final output stage. This bipolar-MOSFET combination provides high peak current during the Miller plateau stage of the MOSFET turn-on / turn-off process to minimize sw itching loss, w hile providing rail-to-rail voltage sw ing and reverse current capability. The FAN3100 also offers dual inputs that can be configured to operate in non-inverting or inverting mode and allow implementation of an enable function. If one or both inputs are left unconnected, internal resistors bias the inputs such that the output is pulled LOW to hold the pow er MOSFET off. The FAN3100 is available in a lead-free finish, 2x2 mm, 6lead, Molded Leadless Package (MLP) for the smallest size w ith excellent thermal performance; or industrystandard, 5-pin, SOT23. DC-to-DC Converters Motor Control Functional Pin Configurations IN+ 1 AGND 2 VDD 3 VDD 1 GND 2 IN+ 3 5 OUT 4 IN- 6 IN5 PGND 4 OUT (c) 2007 Semiconductor Components Industries, LLC. December-2017, Rev . 2 Publication Order Number: FAN3100T/D FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver FAN3100C / FAN3100T Single 2 A High-Speed, Low-Side Gate Driver Figure 2. SOT23-5 (Top View ) Ordering Information Part Number Input Threshold Package Packing Method Quantity / Reel FAN3100CMPX CMOS 6-Lead, 2x2 mm MLP Tape & Reel 3000 FAN3100CSX CMOS 5-Pin, SOT23 Tape & Reel 3000 FAN3100TMPX TTL 6-Lead, 2x2 mm MLP Tape & Reel 3000 FAN3100TSX TTL 5-Pin, SOT23 Tape & Reel 3000 Package Outlines IN+ 1 VDD 1 GND 2 IN+ 3 5 OUT 4 IN- 6 IN- AGND 2 5 PGND VDD 3 4 OUT Figure 3. 6-Lead MLP (Top View ) Figure 4. SOT23-5 (Top View ) Thermal Characteristics(1) JL(2) JT(3) JA(4) JB(5) JT(6) Units 6-Lead, 2x2 mm Molded Leadless Package (MLP) 2.7 133 58 2.8 42 C/W SOT23-5 56 99 157 51 5 C/W Package Notes: 1. Estimates derived from thermal simulation; actual values depend on the application. 2. Theta_JL (JL): Thermal resistance betw een the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a PCB. 3. Theta_JT (JT ): Thermal resistance betw een the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top-side heatsink. 4. Theta_JA (JA ): Thermal resistance betw een junction and ambient, dependent on the PCB design, heat sinking, and airflow . The value given is for natural convection w ith no heatsink using a 2SP2 board, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. 5. Psi_JB (JB ): Thermal characterization parameter providing correlation betw een semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in Note 4. For the MLP-6 package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOT23-5 package, the board reference is defined as the PCB copper adjacent to pin 2. 6. Psi_JT (JT ): Thermal characterization parameter providing correlation betw een the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in Note 4. www.onsemi.com 2 FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Figure 1. 6-Lead MLP (Top View ) SOT23 MLP Name Pin # Pin # 1 3 VDD 2 AGND 2 GND Pin Description Supply Voltage. Provides pow er to the IC. Analog ground for input signals (MLP only). Connect to PGND underneath the IC. Ground (SOT-23 only). Common ground reference for input and output circuits. 3 1 IN+ Non-Inverting Input. Connect to VDD to enable output. 4 6 IN- Inverting Input. Connect to AGND or PGND to enable output. 5 4 OUT Pad P1 5 PGND Gate Drive Output: Held LOW unless required inputs are present and V DD is above UVLO threshold. Therm al Pad (MLP only). Exposed metal on the bottom of the package, w hich is electrically connected to pin 5. Pow er Ground (MLP only). For output drive circuit; separates sw itching noise from inputs. Output Logic IN+ IN- OUT 0(7) 0 0 0(7) 1(7) 0 1 0 1 1 1(7) 0 Note: 7. Default input signal if no external connection is made. www.onsemi.com 3 FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Pin Definitions 1 VDD 5 OUT 2 GND 3 VDD 4 OUT 5 PGND UVLO 100k VDD_OK IN+ 3 100k 100k IN- 4 Figure 5. Sim plified Block Diagram (SOT23 Pin-out) UVLO 100k VDD_OK IN+ 1 100k 100k IN- 6 AGND 2 0.4 Figure 6. Sim plified Block Diagram (MLP Pin-out) www.onsemi.com 4 FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Block Diagrams Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit -0.3 20.0 V V DD VDD to PGND V IN Voltage on IN+ and IN- to GND, AGND, or PGND GND - 0.3 V DD + 0.3 V Voltage on OUT to GND, AGND, or PGND GND - 0.3 V DD + 0.3 V +260 C V OUT TL Lead Soldering Temperature (10 Seconds) TJ Junction Temperature -55 +150 C TST G Storage Temperature -65 +150 C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter V DD Supply Voltage Range V IN Input Voltage IN+, IN- TA Operating Ambient Temperature www.onsemi.com 5 Min. Max. Unit 4.5 18.0 V 0 V DD V -40 +125 C FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Absolute Maximum Ratings Unless otherw ise noted, V DD = 12 V, TJ = -40C to +125C. Currents are defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit Supply V DD IDD Operating Range 4.5 (8) Supply Current Inputs/EN Not Connected 18.0 V FAN3100C 0.20 0.35 mA FAN3100T 0.50 0.80 mA V ON Turn-On Voltage 3.5 3.9 4.3 V V OFF Turn-Off Voltage 3.3 3.7 4.1 V Inputs (FAN3100T) V INL_T IN+, IN- Logic LOW Voltage, Maximum V INH_T IN+, IN- Logic HIGH Voltage, Minimum 0.8 V 2.0 V IIN+ Non-inverting Input IN from 0 to V DD -1 175 A IIN- Inverting Input IN from 0 to V DD -175 1 A 0.8 V V HYS IN+, IN- Logic Hysteresis Voltage 0.2 0.4 Inputs (FAN3100C) V INL_C IN+, IN- Logic LOW Voltage V INH_C IN+, IN- Logic HIGH Voltage 30 %V DD 70 %V DD IINL IN Current, LOW IN from 0 to V DD -1 175 A IINH IN Current, HIGH IN from 0 to V DD -175 1 A V HYS_C IN+, IN- Logic Hysteresis Voltage 17 %V DD Output OUT Current, Mid-Voltage, Sinking(9) OUT at V DD/2, CLOAD = 0.1 F, f = 1 kHz 2.5 A ISOURCE OUT Current, Mid-Voltage, Sourcing(9) OUT at V DD/2, CLOAD = 0.1 F, f = 1 kHz -1.8 A IPK_SINK OUT Current, Peak, Sinking(9) CLOAD = 0.1 F, f = 1 kHz 3 A OUT Current, Peak, Sourcing(9) CLOAD = 0.1 F, f = 1 kHz -3 A ISINK IPK_SOURCE (10) tRISE Output Rise Time CLOAD = 1000 pF 13 20 ns tFALL Output Fall Time(10) CLOAD = 1000 pF 9 14 ns tD1, tD2 tD1, tD2 IRVS Output Prop. Delay, CMOS Inputs (10) Output Prop. Delay, TTL Inputs (10) 0 - 12 V IN; 1 V/ns Slew Rate 7 15 28 ns 0 - 5 V IN; 1 V/ns Slew Rate 9 16 30 ns Output Reverse Current Withstand(9) 500 Notes: 8. Low er supply current due to inactive TTL circuitry. 9. Not tested in production. 10. See Timing Diagrams of Figure 7 and Figure 8. www.onsemi.com 6 mA FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Electrical Characteristics 90% 90% Output Output 10% Input 10% VINH Input VINL tD1 tD2 tRISE VINH VINL tD2 tD1 tFALL Figure 7. Non-Inverting tFALL Figure 8. Inverting www.onsemi.com 7 tRISE FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Timing Diagrams Typical characteristics are provided at 25C and V DD=12 V unless otherw ise noted. Figure 9. IDD (Static) vs. Supply Voltage Figure 10. IDD (Static) vs. Supply Voltage Figure 11. IDD (No-Load) vs. Frequency Figure 12. IDD (No-Load) vs. Frequency Figure 13. IDD (1 nF Load) vs. Frequency Figure 14. IDD (1 nF Load) vs. Frequency www.onsemi.com 8 FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Typical Performance Characteristics Typical characteristics are provided at 25C and V DD=12 V unless otherw ise noted. Figure 15. IDD (Static) vs. Tem perature Figure 16. IDD (Static) vs. Tem perature Figure 17. Input Thresholds vs. Supply Voltage Figure 18. Input Thresholds vs. Supply Voltage Figure 19. Input Thresholds % vs. Supply Voltage www.onsemi.com 9 FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Typical Performance Characteristics Typical characteristics are provided at 25C and V DD=12 V unless otherw ise noted. Figure 20. CMOS Input Thresholds vs. Tem perature Figure 21. TTL Input Thresholds vs. Tem perature Figure 22. UVLO Thresholds vs. Tem perature Figure 23. UVLO Hysteresis vs. Tem perature Figure 24. Propagation Delay vs. Supply Voltage Figure 25. Propagation Delay vs. Supply Voltage www.onsemi.com 10 FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Typical Performance Characteristics Typical characteristics are provided at 25C and V DD=12 V unless otherw ise noted. Figure 26. Propagation Delay vs. Supply Voltage Figure 27. Propagation Delay vs. Supply Voltage Figure 28. Propagation Delay vs. Tem perature Figure 29. Propagation Delay vs. Tem perature Figure 30. Propagation Delay vs. Tem perature Figure 31. Propagation Delay vs. Tem perature www.onsemi.com 11 FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Typical Performance Characteristics Typical characteristics are provided at 25C and V DD=12 V unless otherw ise noted. Figure 32. Fall Tim e vs. Supply Voltage Figure 33. Rise Tim e vs. Supply Voltage Figure 34. Rise and Fall Tim e vs. Tem perature Figure 35. Rise / Fall Waveform s w ith 1 nF Load Figure 36. Rise / Fall Waveform s w ith 10 nF Load www.onsemi.com 12 FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Typical Performance Characteristics Typical characteristics are provided at 25C and V DD=12 V unless otherw ise noted. Figure 37. Quasi-Static Source Current w ith V DD=12 V Figure 38. Quasi-Static Sink Current w ith V DD=12 V Figure 39. Quasi-Static Source Current w ith V DD=8 V Figure 40. Quasi-Static Sink Current w ith V DD=8 V VDD 470F Al. El. 4.7F ceramic Current Probe LECROY AP015 IOUT IN 1kHz 1F ceramic VOUT CLOAD 0.1F Figure 41. Quasi-Static IOUT / V OUT Test Circuit www.onsemi.com 13 FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Typical Performance Characteristics Input Thresholds The FAN3100 offers TTL or CMOS input thresholds. In the FAN3100T, the input thresholds meet industry-standard TTL logic thresholds, independent of the V DD voltage, and there is a hysteresis voltage of approximately 0.4 V. These levels permit the inputs to be driven from a range of input logic signal levels for w hich a voltage over 2 V is considered logic HIGH. The driving signal for the TTL inputs should have fast rising and falling edges w ith a slew rate of 6 V/s or faster, so the rise time from 0 to 3.3 V should be 550 ns or less. With reduced slew rate, circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input, causing erratic operation. In the FAN3100C, the logic input thresholds are dependent on the V DD level and, w ith V DD of 12 V, the logic rising edge threshold is approximately 55% of V DD and the input falling edge threshold is approximately 38% of V DD. The CMOS input configuration offers a hysteresis voltage of approximately 17% of V DD. The CMOS inputs can be used w ith relatively slow edges (approaching DC) if good decoupling and bypass techniques are incorporated in the system design to prevent noise from violating the input voltage hysteresis w indow . This allow s setting precise timing intervals by fitting an R-C circuit betw een the controlling signal and the IN pin of the driver. The slow rising edge at the IN pin of the driver introduces a delay betw een the controlling signal and the OUT pin of the driver. Static Supply Current In the IDD (static) typical performance graphs (Figure 9 Figure 10 and Figure 15 - Figure 16), the curve is produced w ith all inputs floating (OUT is LOW) and indicates the low est static IDD current for the tested configuration. For other states, additional current flow s through the 100 k resistors on the inputs and outputs show n in the block diagrams (see Figure 5 - Figure 6). In these cases, the actual static IDD current is the value obtained from the curves plus this additional current. MillerDriveTM Gate Drive Technology FAN3100 drivers incorporate the MillerDriveTM architecture show n in Figure 42 for the output stage, a combination of bipolar and MOS devices capable of providing large currents over a w ide range of supply voltage and temperature variations. The bipolar devices carry the bulk of the current as OUT sw ings betw een 1/3 to 2/3 V DD and the MOS devices pull the output to the high or low rail. The purpose of the MillerDriveTM architecture is to speed up sw itching by providing the highest current during the Miller plateau region w hen the gate-drain capacitance of the MOSFET is being charged or discharged as part of the turn-on / turn-off process. For applications that have zero voltage sw itching during the MOSFET turn-on or turn-off interval, the driver supplies high peak current for fast sw itching even though the Miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the MOSFET is sw itched on. The output pin slew rate is determined by V DD voltage and the load on the output. It is not user adjustable, but if a slow er rise or fall time at the MOSFET gate is needed, a series resistor can be added. VDD Input stage VOUT Figure 42. MillerDriveTM Output Architecture Under-Voltage Lockout The FAN3100 start-up logic is optimized to drive ground referenced N-channel MOSFETs w ith a under-voltage lockout (UVLO) function to ensure that the IC starts up in an orderly fashion. When V DD is rising, yet below the 3.9 V operational level, this circuit holds the output LOW, regardless of the status of the input pins. After the part is active, the supply voltage must drop 0.2 V before the part shuts dow n. This hysteresis helps prevent chatter w hen low V DD supply voltages have noise from the pow er sw itching. This configuration is not suitable for driving high-side P-channel MOSFETs because the low output voltage of the driver w ould turn the P-channel MOSFET on w ith V DD below 3.9 V. VDD Bypass Capacitor Guidelines To enable this IC to turn a pow er device on quickly, a local, high-frequency, bypass capacitor CBYP w ith low ESR and ESL should be connected betw een the VDD and GND pins w ith minimal trace length. This capacitor is in addition to bulk electrolytic capacitance of 10F to 47F often found on driver and controller bias circuits. A typical criterion for choosing the value of CBYP is to keep the ripple voltage on the V DD supply 5%. Often this is achieved w ith a value 20 times the equivalent load capacitance CEQV , defined here as Qgate/V DD. Ceramic capacitors of 0.1F to 1F or larger are common choices, as are dielectrics, such as X5R and X7R, w hich have good temperature characteristics and high pulse current capability. If circuit noise affects normal operation, the value of CBYP may be increased to 50-100 times the CEQV , or CBYP may be split into tw o capacitors. One should be a larger value, based on equivalent load capacitance, and the other a smaller value, such as 1-10 nF, mounted closest to the VDD and GND pins to carry the higher-frequency components of the current pulses. www.onsemi.com 14 FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Applications Information The FAN3100 incorporates fast-reacting input circuits, short propagation delays, and pow erful output stages capable of delivering current peaks over 2 A to facilitate voltage transition times from under 10 ns to over 100 ns. The follow ing layout and connection guidelines are strongly recommended: Keep high-current output and pow er ground paths separate from logic input signals and signal ground paths. This is especially critical w hen dealing w ith TTL-level logic thresholds. Keep the driver as close to the load as possible to minimize the length of high-current traces. This reduces the series inductance to improve high-speed sw itching, w hile reducing the loop area that can radiate EMI to the driver inputs and other surrounding circuitry. The FAN3100 is available in tw o packages w ith slightly different pinouts, offering similar performance. In the 6-pin MLP package, Pin 2 is internally connected to the input analog ground and should be connected to pow er ground, Pin 5, through a short direct path underneath the IC. In the 5-pin SOT23, the internal analog and pow er ground connections are made through separate, individual bond w ires to Pin 2, w hich should be used as the common ground point for pow er and control signals. Many high-speed pow er circuits can be susceptible to noise injected from their ow n output or other external sources, possibly causing output retriggering. These effects can be especially obvious if the circuit is tested in breadboard or non-optimal circuit layouts w ith long input, enable, or output leads. For best results, make connections to all pins as short and direct as possible. The turn-on and turn-off current paths should be minimized as discussed in the follow ing sections. Figure 43 show s the pulsed gate drive current path w hen the gate driver is supplying gate charge to turn the MOSFET on. The current is supplied from the local bypass capacitor, CBYP , and flow s through the driver to the MOSFET gate and to ground. To reach the high peak currents possible, the resistance and inductance in the path should be minimized. The localized CBYP acts to contain the high peak current pulses w ithin this driverMOSFET circuit, preventing them from disturbing the sensitive analog circuitry in the PWM controller. VDD Figure 44 show s the current path w hen the gate driver turns the MOSFET off. Ideally, the driver shunts the current directly to the source of the MOSFET in a small circuit loop. For fast turn-off times, the resistance and inductance in this path should be minimized. VDD VDS CBYP FAN3100 PWM Figure 44. Current Path for MOSFET Turn-Off Truth Table of Logic Operation The truth table indicates the operational states using the dual-input configuration. In a non-inverting driver configuration, the IN- pin should be a logic LOW signal. If the IN- pin is connected to logic HIGH, a disable function is realized, and the driver output remains LOW regardless of the state of the IN+ pin. IN+ IN- OUT 0 0 0 0 1 0 1 0 1 1 1 0 In the non-inverting driver configuration in Figure 45, the IN- pin is tied to ground and the input signal (PWM) is applied to IN+ pin. The IN- pin can be connected to logic HIGH to disable the driver and the output remains LOW, regardless of the state of the IN+ pin. VDD PWM IN+ IN- FAN3100 OUT GND Figure 45. Dual-Input Driver Enabled, Non-Inverting Configuration In the inverting driver application show n in Figure 46, the IN+ pin is tied HIGH. Pulling the IN+ pin to GND forces the output LOW, regardless of the state of the IN- pin. VDD VDS CBYP IN+ PWM FAN3100 IN- FAN3100 OUT GND PWM Figure 43. Current Path for MOSFET Turn-On www.onsemi.com 15 Figure 46. Dual-Input Driver Enabled, Inverting Configuration FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Layout and Connection Guidelines At pow er up, the driver output remains LOW until the V DD voltage reaches the turn-on threshold. The magnitude of the OUT pulses rises w ith V DD until steady-state V DD is reached. The non-inverting operation illustrated in Figure 47 show s that the output remains LOW until the UVLO threshold is reached, then the output is in-phase w ith the input. VDD Turn-on Threshold IN- IN+ OUT Figure 47. Non-Inverting Start-Up Waveform s For the inverting configuration of Figure 46, start-up w aveforms are show n in Figure 48. With IN+ tied to VDD and the input signal applied to IN-, the OUT pulses are inverted w ith respect to the input. At pow er up, the inverted output remains LOW until the V DD voltage reaches the turn-on threshold, then it follow s the input w ith inverted phase. VDD Turn-on Threshold IN- IN+ (VDD) PGAT E = QG * V GS * f SW Figure 48. Inverting Start-Up Waveform s Thermal Guidelines Gate drivers used to sw itch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of pow er. It is important to determine the driver pow er dissipation and the resulting junction temperature in the application to ensure that the part is operating w ithin acceptable temperature limits. The total pow er dissipation in a gate driver is the sum of tw o components; PGAT E and PDYNAMIC: (1) Gate Driving Loss: The most significant pow er loss results from supplying gate current (charge per unit time) to sw itch the load MOSFET on and off at the sw itching frequency. The pow er dissipation that results from driving a MOSFET at a specified gate- (2) Dynamic Pre-drive / Shoot-through Current: A pow er loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-dow n resistors, can be obtained using the IDD (no-Load) vs. Frequency graphs in Typical Performance Characteristics to determine the current IDYNAMIC draw n from V DD under actual operating conditions: PDYNAMIC = IDYNAMIC * V DD (3) Once the pow er dissipated in the driver is determined, the driver junction rise w ith respect to circuit board can be evaluated using the follow ing thermal equation, assuming JB w as determined for a similar thermal design (heat sinking and air flow ): TJ = PT OT AL * JB + TB (4) w here: = driver junction temperature TJ JB = (psi) thermal characterization parameter relating temperature rise to total pow er dissipation TB = board temperature in location defined in the Thermal Characteristics table. In a typical forw ard converter application w ith 48 V input, as show n in Figure 49, the FDS2672 w ould be a potential MOSFET selection. The typical gate charge w ould be 32 nC w ith V GS = V DD = 10 V. Using a TTL input driver at a sw itching frequency of 500 kHz, the total pow er dissipation can be calculated as: PGAT E = 32 nC * 10 V * 500 kHz = 0.160 W (5) PDYNAMIC = 8 mA * 10 V = 0.080 W (6) PT OT AL = 0.24 W (7) The 5-pin SOT23 has a junction-to-lead characterization parameter JB = 51C/W. OUT PT OT AL = PGAT E + PDYNAMIC source voltage, V GS , w ith gate charge, QG, at sw itching frequency, f SW , is determined by: thermal In a system application, the localized temperature around the device is a function of the layout and construction of the PCB along w ith airflow across the surfaces. To ensure reliable operation, the maximum junction temperature of the device must be prevented from exceeding the maximum rating of 150C; w ith 80% derating, TJ w ould be limited to 120C. Rearranging Equation 4 determines the board temperature required to maintain the junction temperature below 120C: TB,MAX = TJ - PT OT AL * JB (8) TB,MAX = 120C - 0.24W * 51C/W = 108C (9) For comparison purposes, replace the 5-pin SOT23 used in the previous example w ith the 6-pin MLP package w ith JB = 2.8C/W. The 6-pin MLP package can operate at a PCB temperature of 119C, w hile maintaining the junction temperature below 120C. This illustrates that the physically smaller MLP package w ith thermal pad offers a more conductive path to remove the heat from the driver. Consider the tradeoffs betw een reducing overall circuit size w ith junction temperature reduction for increased reliability. www.onsemi.com 16 FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Operational Waveforms VIN ENABLE Active LOW FAN3100 IN+ PWM AGND VDD 1 6 2 5 3 4 INPGND OUT Figure 49. Forw ard Converter, Prim ary-Side Gate Drive (MLP Package Show n) Q1 VIN T2 T1 D1 VDD VSEC D2 FAN3100 PWM Q2 CC 0.1F Figure 50. Driver for Tw o-Transistor Forw ard Converter Gate Transform er VIN Q1 T1 D1 PWM Control/ Isolation SR L VOUT Q5 VSEC D2 Q3 Q2 VDRV ISOLATION FAN3100 Figure 51. Secondary Synchronous Rectifier Driver VDD R FAN3100C IN OUT C Delay IN OUT Figure 52. Program m able Delay Using CMOS Input www.onsemi.com 17 FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Typical Application Diagrams Part Num ber Type Gate Drive (11) (Sink/Src) Input Threshold Logic Package FAN3100C Single 2A +2.5 A / -1.8A CMOS Single Channel of Tw o-Input/One-Output SOT23-5, MLP6 FAN3100T Single 2A +2.5 A / -1.8A TTL Single Channel of Tw o-Input/One-Output SOT23-5, MLP6 FAN3226C Dual 2 A +2.4 A / 1.6 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 FAN3226T Dual 2 A +2.4 A / 1.6 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 FAN3227C Dual 2 A +2.4 A / 1.6 A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 FAN3227T Dual 2 A +2.4 A / 1.6 A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 FAN3228C Dual 2 A +2.4 A / 1.6 A CMOS Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8 FAN3228T Dual 2 A +2.4 A / 1.6 A TTL Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8 FAN3229C Dual 2 A +2.4 A / 1.6 A CMOS Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8 FAN3229T Dual 2 A +2.4 A / 1.6 A TTL Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8 FAN3223C Dual 4 A +4.3 A / 2.8 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 FAN3223T Dual 4 A +4.3 A / 2.8 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 FAN3224C Dual 4 A +4.3 A / 2.8 A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 FAN3224T Dual 4 A +4.3 A / 2.8 A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 FAN3225C Dual 4 A +4.3 A / 2.8 A CMOS Dual Channels of Two-Input/One-Output SOIC8, MLP8 FAN3225T Dual 4 A +4.3 A / 2.8 A TTL Dual Channels of Two-Input/One-Output SOIC8, MLP8 Note: 11. Typical currents w ith OUT at 6 V and V DD = 12 V. www.onsemi.com 18 FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Table 1. Related Products 2.0 0.05 C A 1.72 1.68 B 2X 6 4 0.15 2.0 1.21 2.25 0.90 0.52(6X) 0.05 C PIN#1 IDENT TOP VIEW 1 2X 3 0.65 0.42(6X) RECOMMENDED LAND PATTERN 0.750.05 0.10 C 0.200.05 NOTES: 0.08 C SIDE VIEW 0.0250.025 SEATING PLANE C A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC MO-229 REGISTRATION B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 2009. 2.000.05 1.400.05 (0.70) (0.20)4X PIN #1 IDENT 1 3 D. LAND PATTERN RECOMMENDATION IS EXISTING INDUSTRY LAND PATTERN. E. DRAWING FILENAME: MKT-MLP06Krev5. (0.40) 0.320.05 (6X) 0.800.05 (0.60) 6 4 0.300.05 (6X) 0.65 1.30 0.10 0.05 C A B C BOTTOM VIEW Figure 53. 2x2 m m , 6-Lead, Molded Leadless Package (MLP) Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact an ON Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor's worldwide terms and conditions, specifically the warranty therein, which covers ON Semiconductor products. www.onsemi.com 19 FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Physical Dimensions 3.00 2.80 5 SYMM CL 0.95 0.95 A 4 B 3.00 2.60 1.70 1.50 1 2 2.60 3 (0.30) 1.00 0.50 0.30 0.95 1.90 0.20 C A B 0.70 TOP VIEW LAND PATTERN RECOMMENDATION SEE DETAIL A 1.30 0.90 1.45 MAX 0.15 0.05 0.22 0.08 C 0.10 C NOTES: UNLESS OTHEWISE SPECIFIED GAGE PLANE A) THIS PACKAGE CONFORMS TO JEDEC MO-178, ISSUE B, VARIATION AA, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) MA05Brev5 0.25 8 0 0.55 0.35 0.60 REF SEATING PLANE Figure 54. 5-Lead SOT-23 Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact an ON Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor's worldwide terms and conditions, specifically the warranty therein, which covers ON Semiconductor products. www.onsemi.com 20 FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver Physical Dimensions FAN3100C / FAN3100T -- Single 2 A High-Speed, Low-Side Gate Driver ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. "Typical" parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax : 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. Amer ican Technical Suppor t: 800-282-9855 Toll ON Semiconductor Website: www.onsemi.com Free USA/Canada. Or der Liter atur e: http://www.onsemi.com/orderlit Eur ope, Middle East and Afr ica Technical Suppor t: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5817-1050 www.onsemi.com 21 For additional information, please contact your local Sales Representative