© 2007 Sem ic onduc t or C om ponent s I ndus t ries , LLC . Public at ion Order N um ber:
December-2017, R ev. 2 FAN3100T/D
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
FAN3100C / F AN3100T
Single 2 A High-Speed, Low-Side Gate Driver
Features
3 A Peak Sink/Source at VDD = 12 V
4.5 to 18 V O perating Range
2.5 A Sink / 1.8 A Source at VOUT = 6 V
Dual-Logic Inputs Allow Configuration as
Non-Inverting or Inverting with Enable Function
Internal Resistors Turn Driver Off If No Inputs
13 ns Typical Rise Time and 9 ns Typical Fall-Time
w ith 1 nF Load
Choice of TTL or CMOS Input Thresholds
Mil lerDrive™ Technology
Typical Propagati on Delay Ti me Under 20 ns with
Input Fal ling or Rising
6-Lead, 2x2 mm MLP or 5 -Pin, SOT23 Packages
Rated from –40°C to 125°C Ambient
Applications
Sw itched-Mode Pow er Supplies (SMPS)
High-Efficiency MOSFET Sw itching
Synchronous Rectifier Circui ts
DC-to-DC Converters
Motor Control
Description
The FAN3100 2 A gate driver is des igned to drive an N-
channel enhancement-mode MOSFET in low -side
sw itching applications by providing high peak current
puls es during the shor t switching interv als. The dr iv er is
available with either TTL (FAN3100T) or CMOS
(FAN3100C) input thresholds. Internal circuitry provides
an under-voltage lockout function by holding the output
LOW until the suppl y voltage i s wi thin the operating range.
The FAN3100 delivers fast MOSFET switching
performance, which helps maximize efficiency in high-
frequency power converter designs.
FAN3100 dri vers incorporate Mi llerDrive™ architecture for
the final output stage. This bipolar-MOSFET combination
prov ides high peak curr ent during the Miller plateau s tage
of the MOSFET turn-on / turn-off process to minimize
sw itching loss, w hile providing rail-to-rail voltage sw ing
and reverse current capabili ty.
The FAN3100 also offers dual inputs that can be
configured to operate in non-inverting or inverting mode
and allow implementation of an enable f unc tion. If one or
both inputs are left unconnected, internal resistors bias
the inputs s uch that the output is pulled LOW to hold the
power MOSFET off.
The FA N3100 is av ailable in a lead-free finish, 2x2 mm, 6-
lead, Molded Leadless Package (MLP) for the smallest
size with excellent thermal performance; or industry-
standard, 5-pin, SOT23.
Functional Pin Configurations
1 6
52
43
IN+
AGND
VDD
IN-
PGND
OUT
1
2
3
5
4
VDD
GND
IN+ IN−
OUT
www.onsemi.com
2
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Figure 1. 6-Lead MLP (Top View)
Figure 2. SOT23-5 (Top View)
Ordering Information
Part Num ber Input
Threshold Package P acking Method Quantity / Reel
FAN3100CMPX CMOS 6-Lead, 2x2 mm MLP Tape & Reel 3000
FAN3100CSX CMOS 5-Pin, SOT23 Tape & Reel 3000
FAN3100TMPX TTL 6-Lead, 2x2 mm MLP Tape & Reel 3000
FAN3100TSX TTL 5-Pin, SOT23 Tape & Reel 3000
Pack a ge Outlines
1 6
52
43
IN+
AGND
VDD
IN−
PGND
OUT
1
2
3
5
4
VDD
GND
IN+ IN−
OUT
Figure 3. 6-Lead MLP (Top View)
Figure 4. SOT23-5 (Top View)
Thermal Characteristics(1)
Package
Θ
JL(2)
Θ
JT(3)
Θ
JA(4)
Ψ
JB(5)
Ψ
JT(6) Units
6-Lead, 2x2 mm Molded Leadless Package (MLP) 2.7 133 58 2.8 42 °C/W
SOT23-5 56 99 157 51 5 °C/W
Notes:
1. Estimates deri ved from thermal simulation; actual val ues depend on the appl ication.
2. Theta_JL (ΘJL): T hermal resistance between the semiconductor junction and the bottom surface of all the leads
(incl uding any thermal pad) that are typical ly soldered to a PCB.
3. Theta_JT (ΘJT): Thermal resistance between the semiconductor junction and the top surface of the package,
assumi ng it is held at a uniform temperature by a top-side heatsink.
4. Theta_JA (ΘJA): Thermal resi stance between j unction and ambi ent, dependent on the PCB design, heat sinking, and
ai rflow. The value given is for natural convection wi th no heatsink using a 2SP2 board, as specified in J EDEC
standards JESD51-2, JESD51-5, and JESD51-7, as appropriate.
5. Psi_JB (ΨJB): T hermal characterization parameter providing correlation between semiconductor junction temperature
and an appl ication circuit board reference point for the thermal environment defined in Note 4. For the MLP-6
package, the board reference i s defined as the PCB copper connected to the thermal pad and protruding from ei ther
end of the package. For the SOT23-5 package, the board reference is defined as the PCB copper adjacent to pin 2.
6. Psi_JT (ΨJT): Thermal characterization parameter providing correl ation between the semiconductor junction
temperature and the center of the top of the package for the thermal environment defined in Note 4.
www.onsemi.com
3
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Pin Definitions
SOT23
Pin # MLP
Pi n # Name Pi n De scri pti on
1 3 VDD Supply Voltage. Provides pow er to the IC.
2 AGND Analog ground for input si gnals (MLP only). Connect to PGND underneath the IC.
2 GND Ground (SOT-23 only). Common ground reference for input and output circui ts.
3 1 IN+ Non-Inverting Input. Connect to VDD to enable output.
4 6 IN- Inverting Input. Connect to AGND or PGND to enable output.
5 4 OUT Gate Driv e Output: Held LOW unl ess required inputs are present and VDD is above UVLO
threshold.
Pad P1 Thermal Pad (MLP only). Exposed metal on the bottom of the pack age, which is
el ectrically connected to pin 5.
5 PGND Power Ground (MLP only). For output drive circuit; separates sw itching noise from
inputs.
Output Logic
IN+ IN− OUT
0(7) 0 0
0(7) 1(7) 0
1 0 1
1 1(7) 0
Note:
7. Default input signal if no external connecti on is made.
www.onsemi.com
4
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Block Diagrams
IN
-4
1
VDD
5OUT
2GND
UVLO
V
DD_OK
IN+ 3
100kΩ
100kΩ
100kΩ
Figure 5. S implified Block Diagram (SOT23 Pin-out)
IN
-
6
3
VDD
4
OUT
5
PGND
UVLO
V
DD_OK
IN+
1
100kΩ
100kΩ
100kΩ
AGND
2
0.4Ω
Figure 6. S implified Block Diagram (MLP Pin-out)
www.onsemi.com
5
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Absolute Max imum Ratings
Stres ses exc eeding the abs olute max imum r atings may damage the dev ice. The dev ice may not f unc tion or be operable
above the rec ommended operating conditions and stres sing the parts to these levels is not rec ommended. In addition,
extended ex posur e to stres ses above the rec ommended operating conditions may af fec t dev ic e reliability. The abs olute
maximum ratings are stress rati ngs onl y.
Symbol
Parameter Min. Max. Unit
VDD VDD to PGND -0.3 20.0 V
VIN Voltage on IN+ and IN- to GND, AGND, or PGND GND - 0.3 VDD + 0.3 V
VOUT Voltage on OUT to GND, AGND, or PGND GND - 0.3 VDD + 0.3 V
TL Lead Soldering Temperature (10 Seconds) +260 ºC
TJ Junction Temperature -55 +150 ºC
TSTG Storage T emperature -65 +150 ºC
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor
does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter Min. Max. Unit
VDD Supply Voltage Range 4.5 18.0 V
VIN Input Voltage IN+, IN- 0 VDD V
TA Operating Ambient Temperature -40 +125 ºC
www.onsemi.com
6
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Electrical Characteristics
Unless otherw ise noted, V DD = 12 V, TJ = -40° C to +125°C. Currents are defined as positi ve i nto the device and negative
out of the device.
Symbol Parameter Conditions Min. Typ. Max. Unit
Supply
VDD Operating Range 4.5 18.0 V
IDD Supply Current
Inputs/EN Not Connected FAN3100C(8) 0.20 0.35 mA
FAN3100T 0.50 0.80 mA
VON Turn-On Voltage 3.5 3.9 4.3 V
VOFF Turn-Off Voltage 3.3 3.7 4.1 V
Inputs (FAN3100T)
VINL_T IN+, IN- Logic LOW Voltage, Maximum 0.8 V
VINH_T IN+, IN- Logic HIGH Voltage, Minimum 2.0 V
IIN+ Non-inverting Input IN from 0 to VDD -1 175 µA
IIN- Inverting Input IN from 0 to VDD -175 1 µA
VHYS IN+, IN- Logic Hysteresis Voltage 0.2 0.4 0.8 V
Inputs (FAN3100C)
VINL_C IN+, IN- Logic LOW Voltage 30 %VDD
VINH_C IN+, IN- Logic HIGH Voltage 70 %VDD
IINL IN Current, LOW IN from 0 to VDD -1 175 µA
IINH IN Current, HIGH IN from 0 to VDD -175 1 µA
VHYS_C IN+, IN- Logic Hysteresis Voltage 17 %VDD
Output
ISINK OUT Current, Mid-Voltage, Sinking(9) OUT at VDD/2,
CLOAD = 0.1 µF, f = 1 kHz 2.5 A
ISOURCE OUT Current, Mid-Voltage, Sourcing(9) OUT at VDD/2,
CLOAD = 0.1 µF, f = 1 kHz -1.8 A
IPK_SINK OUT Current, Peak, Sinking(9) CLOAD = 0.1 µF, f = 1 kHz 3 A
IPK_SOURCE OUT Current, Peak, Sourcing(9) CLOAD = 0.1 µF, f = 1 kHz -3 A
tRISE O utput Ri se Time(10) CLOAD = 1000 pF 13 20 ns
tFALL Output Fall Time(10) CLOAD = 1000 pF 9 14 ns
tD1, tD2 Output Prop. Delay, CMOS Inputs(10) 0 – 12 VIN; 1 V/ns Slew Rate 7 15 28 ns
tD1, tD2 Output Prop. Delay, TTL Inputs(10) 0 – 5 VIN; 1 V/ns Slew Rate 9 16 30 ns
IRVS Output Reverse Current Withstand(9) 500 mA
Notes:
8. Lower suppl y current due to inactive TTL circuitry.
9. Not tested in production.
10. See Timing Diagrams of Figure 7 and Figure 8.
www.onsemi.com
7
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Timing Diagrams
90%
10%
Output
Input
t
D1
t
D2
t
RISE
t
FALL
V
INL
V
INH
90%
10%
Output
Input
t
D1
t
D2
t
FALL
t
RISE
V
INL
V
INH
Figure 7. Non-Inverting
Figure 8. Inverting
www.onsemi.com
8
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25° C and VDD=12 V unless otherwi se noted.
Figure 9. IDD (Static) vs. Supp ly Voltage
Figure 10. IDD (Static) vs. Supply Voltage
Figure 11. IDD (No-Load) v s. Frequency
Figure 12. IDD (No-Load) v s. Frequency
Figure 13. I
DD
(1 nF Load) vs. Frequency
Figure 14. I
DD
(1 nF Load) vs. Frequency
www.onsemi.com
9
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25° C and VDD=12 V unless otherwi se noted.
Figure 15. IDD (Stati c) vs. Temperature
Figure 16. IDD (Stati c) vs. Temperature
Figure 17. Input Thresholds vs. Supply Voltage
Figure 18. Input Thresholds vs. Supply Voltage
Figure 19. Input Thresholds % vs. Suppl y Voltage
www.onsemi.com
10
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25° C and VDD=12 V unless otherwi se noted.
Figure 20. C MOS Input Threshol ds vs. Temperature
Figure 21. TTL Input Thresholds vs. Temperature
Figure 22. UVLO Thresholds vs. Temperature
Figure 23. UVLO Hysteresis vs. Temp erature
Figure 24. Propagati on Del ay vs. Supply Voltage
Figure 25. Propagati on Del ay vs. Supply Voltage
www.onsemi.com
11
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25° C and VDD=12 V unless otherwi se noted.
Figure 26. Propagati on Del ay vs. Supply Voltage
Figure 27. Propagati on Del ay vs. Supply Voltage
Figure 28. Propagati on Del ay vs. Tempera ture
Figure 29. Propagati on Del ay vs. Tempera ture
Figure 30. P ropagation Delay vs. Temperature
Figure 31. Propagati on Del ay vs. Tempera ture
www.onsemi.com
12
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25° C and VDD=12 V unless otherwi se noted.
Figure 32. Fall Time vs. Supply Voltage
Figure 33. Ri se Time vs. Supply Voltage
Figure 34. Ri se and Fall Time vs. Temperature
Figure 35. Rise / Fall Wa v eforms with 1 nF Load
Figure 36. Rise / Fall Wa v eforms with 10 nF Loa d
www.onsemi.com
13
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25° C and VDD=12 V unless otherwi se noted.
Figure 37. Quasi-Static Source Current wi th VDD=12 V
Figure 38. Quasi-Static S ink Current with VDD=12 V
Figure 39. Quasi-Static S ource Current with VDD=8 V
Figure 40. Quasi-Static S ink Current with VDD=8 V
470µF
Al. El.
VDD
V
OUT
1µF
ceramic
4.7µF
ceramic
C
LOAD
0.1µF
I
OUT
IN
1kHz
Current Probe
LECROY AP015
Figure 41. Quasi-Static I
OUT
/ V
OUT
Test Circuit
www.onsemi.com
14
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Applica tions Information
Input Thresholds
The FA N3 100 offers TTL or CMOS input thresholds. In the
FAN3100T, the input thresholds meet industry-standard
TTL logic thres holds , independent of the VDD voltage, and
there is a hysteresis voltage of approximately 0.4 V.
These levels permit the inputs to be driven from a range of
input logic signal levels for w hich a voltage over 2 V is
considered logic HIGH. The driving signal for the TTL
inputs should have fast rising and falling edges w ith a
slew rate of 6 V /µs or fas ter, s o the rise time from 0 to
3.3 V should be 550 ns or les s. With reduc ed slew rate,
circuit noise could cause the driver input voltage to
exceed the hysteresis voltage and retrigger the driver
i nput, causing erratic operation.
In the FAN3100C, the logic i nput thresholds are dependent
on the VDD level and, w ith VDD of 12 V, the logic rising
edge thres hold is approximately 55% of VDD and the input
falling edge threshold is approximately 38% of V DD. The
CMOS input configuration offers a hysteresis voltage of
approximately 17% of VDD. The CMO S inputs can be used
with relatively slow edges (approaching DC) if good
decoupling and bypass techniques are incorporated in the
system design to prevent noise from violating the input
voltage hysteresis w indow . This allow s setting precise
timing intervals by fitting an R-C circuit between the
controlling signal and the IN pin of the driver. The slow
rising edge at the IN pin of the driver introduc es a delay
between the controlling signal and the OUT pin of the
driver.
Static Supply Current
In the IDD (static) typical performance graphs (Figure 9 -
Figure 10 and Figure 15 - Figure 16), the curve is
produced with all inputs floating (OUT is LOW) and
indicates the lowest static IDD current for the tested
configuration. For other states, additional current flow s
through the 100 kΩ resistors on the inputs and outputs
show n in the bloc k diagrams (see Figure 5 - Figure 6). In
these cases, the actual static IDD current is the value
obtained from the curves plus this addi tional current.
MillerDrive™ Gate Drive Tec hnolog y
FAN3100 drivers incorporate the MillerDrive™
architecture show n in Figure 42 for the output stage, a
combination of bipolar and MOS devices capable of
providing large currents over a w ide range of supply
voltage and temperature variations. The bipolar devices
carry the bul k of the current as OUT swings between 1/3
to 2/3 V DD and the MOS devices pul l the output to the high
or low rail.
The purpose of the MillerDrive™ arc hitectur e is to s peed
up s witching by pr oviding the highes t current dur ing the
Miller plateau region when the gate-drain capac itance of
the MOSFET is being charged or discharged as part of the
turn-on / turn-off process.
For applications that hav e zero v oltage sw itching during
the MOSFET turn-on or turn-off interval, the driver
supplies high peak current for fast sw itching even though
the Miller plateau is not present. This situation often
occ urs in sy nchronous rec tif ier applications bec ause the
body diode is generally conducting bef ore the MOSFET is
sw itched on.
The output pin slew rate is determined by VDD voltage and
the load on the output. It is not user adjustable, but if a
slower rise or fall time at the MOSFET gate is needed, a
series resistor can be added.
Input
stage
VDD
VOUT
Figure 42. MillerDrive™ Output Architecture
Under-Voltage Lockout
The FAN3100 start-up logic is optimized to drive ground
referenced N-channel MOSFETs with a under-voltage
lockout (UVLO) f unc tion to ens ure that the IC starts up i n
an orderly fashion. When VDD is rising, yet below the
3.9 V operational lev el, this circ uit holds the output LOW,
regardless of the status of the input pins. After the part is
active, the supply voltage must drop 0.2 V before the part
shuts dow n. This hy steres is helps prev ent chatter when
low VDD supply voltages have noise from the pow er
sw itching. This configuration is not suitable for driving
high-side P-channel MOSFETs because the low output
voltage of the driver w ould turn the P-channel MOSFET on
w ith VDD below 3.9 V.
VDD Bypass Capa citor Guidelin es
To enable this IC to turn a pow er device on quickly, a
local, high-frequency, bypass capacitor CBYP w ith low
ESR and ESL should be connected between the VDD and
GND pins w ith minimal trace length. This capacitor is in
addition to bulk electrolytic capacitance of 10µF to 47µF
often found on driver and controller bias circui ts.
A typical criterion for choosing the value of CBYP is to
keep the ripple v oltage on the V DD supply ≤5%. Often this
is achieved w ith a value ≥ 20 times the equivalent load
capacitance CEQV, defined here as Qgate/VDD. Ceramic
capac itors of 0.1µF to 1 µF or l arger are common choices,
as are dielectrics, such as X5R and X7R, w hich have
good temperature characteristics and high pulse current
capability.
If c irc uit nois e af f ects normal operation, the value of CBYP
may be inc reas ed to 50-100 times the CEQV, or CBYP may
be split into tw o capacitors. One should be a l arger value,
based on equivalent load capacitance, and the other a
smaller value, such as 1-10 nF, mounted closest to the
VDD and GND pins to carry the higher-frequency
components of the current pulses.
www.onsemi.com
15
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Layout and Connection Guidelines
The FAN3100 incorporates fast-reacting input circuits,
short propagation delays, and powerful output stages
capable of deliver ing curr ent peaks ov er 2 A to f ac ilitate
voltage trans ition times f rom under 10 ns to over 100 ns.
The following layout and connection guidelines are
strongl y recommended:
Keep high-current output and pow er ground paths
separate from logic input signals and signal ground
paths. This is especially critical when dealing with
TTL-level logi c thresholds.
Keep the driver as cl ose to the load as possible to
mini mize the length of high-current traces. This
reduces the series inductance to i mprove high-speed
sw itching, while reducing the l oop area that can
radiate EMI to the driver inputs and other surrounding
circuitry.
The FAN3100 is available in two packages wi th
slightly different pinouts, offering similar
performance. In the 6-pin MLP package, Pin 2 is
i nternally connected to the input analog ground and
should be connected to power ground, Pin 5, through
a short di rect path underneath the IC. In the 5-pin
SOT23, the internal analog and power ground
connections are made through separate, individual
bond wires to Pin 2, which should be used as the
common ground point for pow er and control signals.
Many high-speed power ci rcuits can be susceptible
to noise i njected from their ow n output or other
external sources, possibly causing output re-
triggering. These effects can be especi ally obvious i f
the circuit is tested i n breadboard or non-optimal
circuit l ayouts w ith long input, enabl e, or output
leads. For best results, make connections to al l pins
as short and direct as possible.
The turn-on and turn-off current paths should be
mini mized as discussed in the following sections.
Figure 43 shows the pulsed gate drive current path when
the gate driver is supplying gate charge to turn the
MOSFET on. The current is supplied from the local bypass
capacitor, CBYP, and flows through the driver to the
MOSFET gate and to ground. To reach the high peak
currents possible, the resistance and inductance in the
path should be minimized. The localized CBYP acts to
contain the high peak current pulses w ithin this driver-
MOSFET circuit, preventing them from disturbing the
sensitive analog circuitry in the PWM controller.
PWM
VDS
VDD
CBYP
FAN3100
Figure 43. Current Path for MOSFET Turn-On
Figure 44 show s the current path w hen the gate driver
turns the MOSFET off. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn-off times, the resistance and
i nductance in this path should be minimized.
PWM
V
DS
V
DD
C
BYP
FAN3100
Figure 44. Current Path for MOSFET Turn-Off
Truth Table of Logic Oper ation
The truth table indicates the operational states using the
dual-input configuration. In a non-inverting driver
configuration, the IN- pin should be a logic LOW signal. If
the IN- pi n is connected to logic HIGH, a disable function is
realized, and the driver output remains LOW regardless of
the state of the IN+ pin.
IN+
IN-
OUT
0
0
0
0
1
0
1
0
1
1
1
0
In the non-inverting driver configuration in Figure 45, the
IN- pin is tied to ground and the input signal (PWM) is
applied to IN+ pin. The IN- pin can be connec ted to logic
HIGH to disable the driver and the output remains LOW,
regardless of the state of the IN+ pin.
VDD
GND
IN-
IN+ OUT
PWM FAN3100
Figure 45. Dual-Input Driver Enabled,
Non-Inverting Configuration
In the inverting driver applic ation show n in Figure 46, the
IN+ pin is tied HIGH. Pulling the IN+ pin to GND f or ces the
output LOW, regardl ess of the state of the IN- pin.
VDD
GND
IN-
IN+ OUT
PWM FAN3100
Figure 46. Dual-Input Driver Enabled,
Inverting Configuration
www.onsemi.com
16
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Operational Waveforms
A t power up, the driver output remains LOW until the VDD
voltage reaches the turn-on thres hold. The magnitude of
the OUT pulses rises w ith VDD until steady-state VDD is
reached. The non-inverting operation illustrated in Figure
47 show s that the output remains LOW until the UVLO
thres hold is reac hed, then the output is in-phase with the
input.
V
DD
IN+
IN-
OUT
Turn-on Threshold
Figure 47. Non-Inverting Start-Up Waveforms
For the inverting configuration of Figure 46, start-up
wav ef orms are show n in Figure 48. With IN+ tied to VDD
and the input signal applied to IN–, the OUT pulses are
inverted with respect to the input. At power up, the
inverted output remains LOW until the VDD voltage
reaches the turn-on threshold, then it follow s the input
with inverted phase.
V
DD
IN+
(V
DD
)
IN-
OUT
Turn-on Threshold
Figure 48. Inverting Start-Up Waveforms
Thermal Guidelin es
Gate drivers us ed to sw itc h MOSFETs and IGBTs at high
frequencies can dissi pate significant amounts of pow er. It
is impor tant to determine the driver pow er dissipation and
the resulting junction temperature in the application to
ensure that the part is operating within acceptable
temperature limits.
The total power diss ipation in a gate driver is the s um of
two components; PGATE and PDYNAMIC:
PTOTAL = PGATE + PDYNAMIC (1)
Gate Driving Loss: The mos t signif icant power loss
results from supplying gate c urr ent (char ge per unit
time) to sw itch the load MOSFET on and off at the
sw itching frequency. The pow er dissipation that
results from driving a MOSFET at a specified gate-
source voltage, VGS, w ith gate charge, QG, at
sw itching frequency, fSW, is determined by:
PGATE = QG • VGS • fSW
(2)
Dynamic Pre-drive / Shoot-through Current: A pow er
loss resulting from internal current consumption
under dynamic operating conditions, including pin
pull-up / pull-dow n resistors, can be obtained using
the IDD (no-Load) vs. Frequency graphs in Typical
Performance Characteristics to determine the current
IDYNAMIC draw n from VDD under actual operating
conditions:
PDYNAMIC = IDYNAMIC • VDD
(3)
Onc e the power dissipated in the driver is determined, the
driver junction rise with respect to circuit board can be
evaluated using the f ollowing thermal equation, as suming
ψ
JB was determined for a similar thermal design (heat
sinking and air flow):
TJ = PTOTAL •
ψ
JB + TB (4)
where:
TJ = driver juncti on temperature
ψ
JB = (psi) thermal characterization parameter
relating temperature rise to total power
dissipation
TB = board temperature in locati on defi ned in the
Thermal Characteristics table.
In a typical f orward c onverter application with 48 V i nput,
as shown in Figure 49, the FDS2672 would be a potential
MOSFET selection. The typical gate charge would be
32 nC w ith V GS = VDD = 10 V. Using a TTL i nput driver at a
sw itching frequency of 500 kHz, the total power
dissipation can be calculated as:
PGATE = 32 nC • 10 V • 500 kHz = 0.160 W (5)
PDYNAMIC = 8 mA • 10 V = 0.080 W
(6)
PTOTAL = 0.24 W (7)
The 5-pin SOT23 has a junction-to-lead thermal
characterization parameter
ψ
JB = 51°C/W.
In a s ystem applic ation, the localized temperatur e around
the dev ice is a f unc tion of the layout and c onstr uction of
the PCB along with airflow across the surfaces. To
ensure reliable operation, the maximum junction
temperature of the device must be prevented from
exceeding the maximum rating of 150°C; w ith 80%
derating, TJ w ould be limited to 120°C. Rearranging
Equation 4 determines the board temperature r equired to
maintain the junction temperature below 120°C:
TB,MAX = TJ - PTOTAL •
ψ
JB (8)
TB,MAX = 120°C – 0.24W • 51°C/W = 108°C (9)
For comparison purpos es, r eplace the 5-pin SOT23 used
in the pr evious example with the 6-pin MLP pack age with
ψ
JB = 2.8°C/W. The 6-pin MLP pac kage can operate at a
PCB temperature of 119°C, while maintaining the junction
temperature below 120°C. This illustrates that the
physical ly smaller MLP package w ith thermal pad offers a
mor e conduc tive path to r emov e the heat f rom the dr iver .
Consider the tradeoffs betw een reducing overall circuit
size with junction temperature reduction for increased
reliability.
www.onsemi.com
17
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Typical Applica tion Diagrams
IN+ IN-
OUT
VDD
V
IN
PGND
FAN3100
PWM
ENABLE
Active LOW
1
2
34
5
6
AGND
Figure 49. Forward Con verter, Primary-Side Gate Drive (MLP Packa ge Shown)
V
IN
Q2
V
SEC
D1
D2
Q1
T1
V
DD
CC
PWM
0.1µF
T2
FAN3100
Figure 50. Driver f or Two-Transistor Forward Conv erter Gate Transformer
V
IN
V
OUT
PWM
Control/
Isolation
Q5
L
Q2
VSEC
D1
D2
Q1
Q3
T1
ISOLATION
V
DRV
FAN3100
SR
Figure 51. Sec ond ary Synchronous Rectifier Driver
V
DD
FAN3100C
IN OUT
R
C
Delay
IN
OUT
Figure 52. Programmable Delay Using CMOS Input
www.onsemi.com
18
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Table 1. Related P roducts
Part
Number Type Gate
Drive(11)
(Sink/Src)
Input
Threshold
Logic Package
FAN3100C Single
2 A +2.5 A / -1.8A CMOS Si ngle Cha nnel of Two-Input/One-Output SOT23-5 , MLP6
FAN3100T Single
2 A +2.5 A / -1.8A TTL S i ngle Cha nnel of Two-Input/One-Output SOT23-5, MLP6
FAN3226C Dual 2 A +2.4 A / -
1.6 A CMOS Dual Inverti ng Channels + Dual Enabl e S OIC8, M L P8
FAN3226T Dual 2 A +2.4 A / -
1.6 A TTL Dual Inverting Channel s + Dual Enabl e S OIC8, M L P8
FAN3227C Dual 2 A +2.4 A / -
1.6 A CMOS Dual Non-Inverting Channel s + Dual Enabl e S OIC8 , ML P 8
FAN3227T Dual 2 A +2.4 A / -
1.6 A TTL Dual Non-Inverting Channel s + Dual Enabl e S OIC8 , ML P8
FAN3228C Dual 2 A +2.4 A / -
1.6 A CMOS Dual Channel s of Two-Input/One-Outp u t, Pin Config.1 SOIC8 , ML P8
FAN3228T Dual 2 A +2.4 A / -
1.6 A TTL Dual Channel s of Two-Input/One-Outp u t, Pin Config.1 SOIC8, MLP8
FAN3229C Dual 2 A +2.4 A / -
1.6 A CMOS Dual Channel s of Two-Input/One-Outpu t, P in Config.2 SOIC8, MLP8
FAN3229T Dual 2 A +2.4 A / -
1.6 A TTL Dual Channel s of Two-Input/One-Outp u t, Pin Config.2 SOIC8, MLP8
FAN3223C Dual 4 A +4.3 A / -
2.8 A CMOS Dual Inverti ng Channels + Dual Enabl e S OIC8, M L P8
FAN3223T Dual 4 A +4.3 A / -
2.8 A TTL Dual Inverting Channel s + Dual Enabl e S OIC8, M L P8
FAN3224C Dual 4 A +4.3 A / -
2.8 A CMOS Dual Non-Inverting Channel s + Dual Enabl e S OIC8 , ML P 8
FAN3224T Dual 4 A +4.3 A / -
2.8 A TTL Dual Non-Inverting Channel s + Dual Enabl e S OIC8 , MLP8
FAN3225C Dual 4 A +4.3 A / -
2.8 A CMOS Dual Channel s of Two-Input/One-Output SOIC8, ML P8
FAN3225T Dual 4 A +4.3 A / -
2.8 A TTL Dual Channel s of Two-Input/One-Output SOIC8, M L P 8
Note:
11. Typical currents with OUT at 6 V and VDD = 12 V.
www.onsemi.com
19
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Physical Dimensions
TOP VIEW
0.05 C
0.05 C
2X
2X 2.0
2.0
PIN#1 IDENT
AB
SIDE VIEW
RECOMMENDED
LAND PATTERN
BOTTOM VIEW
SEATING
PLANE
13
4
6
4
6
3
1
PIN #1 IDENT
0.65 1.30
1.21
0.52(6X)
0.90
0.42(6X)
0.65
2.25
1.68
(0.40)
(0.70)
NOTES:
A. PACKAGE DOES NOT FULLY CONFORM
TO JEDEC MO-229 REGISTRATION
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
E. DRAWING FILENAME: MKT-MLP06Krev5.
2.00±0.05
1.40±0.05
0.80±0.05
(0.20)4X
0.32±0.05
0.10 C A B
0.05 C
0.30±0.05(6X)
(6X)
(0.60)
0.08 C
0.10 C0.75±0.05
0.025±0.025 C
0.20±0.05
1.72
0.15
Figure 53. 2x2 mm, 6-Lead, Molded Leadless Package (MLP)
Package draw ings are provided as a service to customers consi dering ON Semi conductor components. Drawings may change
i n any manner without noti ce. Please note the revision and/or date on the drawing and contact an ON Semiconductor
representative to verify or obtain the most recent revi sion. Package specifi cations do not expand the terms of ON
Semiconductor’s worldw ide terms and conditions, speci ficall y the w arranty therein, w hi ch covers ON Semiconductor
products.
www.onsemi.com
20
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
Physical Dimensions
5
1
4
32
LAND PATTERN RECOMMENDATION
B
AL
C
0.10 C
0.20 C A B
0.60 REF
0.55
0.35 SEATING PLANE
0.25
GAGE PLANE
8°
0°
NOTES: UNLESS OTHEWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MO-178, ISSUE B, VARIATION AA,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
1.45 MAX
1.30
0.90
0.15
0.05
1.90
0.95 0.50
0.30
3.00
2.60
1.70
1.50
3.00
2.80
SYMM
C0.950.95
2.60
0.70
1.00
SEE DETAIL A
0.22
0.08
C) MA05Brev5
TOP VIEW
(0.30)
Figure 54. 5-Lead SOT-23
Package draw ings are provided as a service to customers consi dering ON Semi conductor components. Drawings may change
i n any manner without noti ce. Please note the revision and/or date on the drawing and contact an ON Semiconductor
representative to verify or obtain the most recent revi sion. Package specifi cations do not expand the terms of ON
Semiconductor’s worldw ide terms and conditions, speci ficall y the w arranty therein, w hi ch covers ON Semiconductor
products.
www.onsemi.com
21
FAN3100C / FAN3100T — Single 2 A High-Speed, Low-Side Gate Driver
ON Semi conductor and t he ON Semic onductor l og o ar e tr ademar ks of Semi conductor C omponents Indus tr i es, LLC dba ON Semi conduc tor or its subsidiaries in the
U ni ted States and/or other countr i es . ON Semi conduc tor owns the r i g ht s to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A
listing of ON Semiconductor’s product/patent coverage may be accessed at ww w .onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make
changes without further notice to any products herein. ON Semiconductor mak es no warranty , representation or guarantee regarding the suitability of its products for any
par ti c ul ar pur pose, nor does ON Semic onductor ass ume any l i abil i ty ar i si ng out of the application or use of any product or circuit, and specifically disclaims any and all
l i abi li ty, i ncl udi ng wi thout l i mitat ion s peci al , c onseq uenti al or i nc i dental damages. Buyer i s r es ponsi bl e for i ts pr oduct s and appl i cati ons usi ng ON Semi conductor
products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applicati ons infor mati on pr ovi ded by
ON Semi conductor . “ Typic al” par ameter s whi ch may be pr ovi ded in ON Semi conductor dat a sheets and/or specifications can and do v ary in different applications and
actual per for mance may var y over t ime. Al l oper ati ng par ameter s , i nc ludi ng “ T ypi cal s ” must be val i dated for eac h c ust omer application by customer’s technical ex perts.
ON Semi conductor does not c onvey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for
use as a critical component in life support sy stems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction
or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any suc h unintended or unaut hor iz ed
appl i cat ion, Buyer shal l indemni fy and hol d ON Semic onductor and i ts offi c er s, empl oyees , s ubsi di ar ies , affi l iates , and di s tr i butor s har ml ess agai nst al l cl ai ms , c osts ,
damag es, and expenses, and r eas onabl e attor ney fees ar i si ng out of, di r ectl y or i ndi r ectl y, any c l aim of per sonal i nj ur y or death as soc i ated wi th s uch uni ntended or
unauthor i z ed use, even i f s uch cl ai m al l eg es that ON Semi conduc tor was negl i g ent r eg ar di ng t he desi g n or manufactur e of the part. ON Semiconductor is an Equal
Opportunity /Affirmativ e Action Employ er. This literature is subject to all applicable copy right laws and is not for resale in any m anner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFI LLMENT:
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aur ora, Colorado 80011 U SA
Phone: 303-675-2175 or 800-344-3860 Toll Free
USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
N. American Technical Support: 800-282-9855 Toll
Free
USA/Canada.
Europe, Middle Ea st and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81-3-5817-1050
ON Semiconductor Websi te: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
