(R) DEVICE SPECIFICATION S3040A S3040A SONET/SDH CLOCK RECOVERY UNIT SONET/SDH CLOCK RECOVERY UNIT BiCMOS PECL CLOCK GENERATOR FEATURES * * * * * * * * * GENERAL DESCRIPTION Micro-power Bipolar technology Complies with Bellcore, and ITU-T specifications for jitter tolerance, jitter transfer and jitter generation On-chip high frequency PLL with internal loop filter for clock recovery Supports clock recovery for OC-48/STM-16 (2488.32 Mbit/s) NRZ data 155.52 MHz reference frequency Lock detect--monitors frequency Low-jitter serial interface +5 V supply 32 TQFP Package The function of the S3040 clock recovery unit is to derive high speed timing signals for SONET/SDHbased equipment. The S3040 is implemented using AMCC's proven Phase Locked Loop (PLL) technology. The S3040 receives an OC-48/STM-16 scrambled NRZ signal and recovers the clock from the data. The chip outputs a differential bit clock and retimed data. The S3040 utilizes an on-chip PLL which consists of a phase detector, a loop filter, and a Voltage Controlled Oscillator (VCO). The phase detector compares the phase relationship between the VCO output and the serial data input. A loop filter converts the phase detector output into a smooth DC voltage, and the DC voltage is input to the VCO whose frequency is varied by this voltage. A block diagram is shown in Figure 2. 8 8 S3041 MUX 8 8 8 8 8 8 April 4, 2000 / Revision D 8 S3042 DeMUX OTX S3040 ORX ORX 8 S3042 8 S3040 DeMUX OTX S3041 MUX 8 8 S3045 8 8 8 8 8 8 Network Interface Processor 8 S3045 Network Interface Processor Figure 1. System Block Diagram 1 SONET/SDH CLOCK RECOVERY UNIT S3040A Table 1. Suggested Interface Devices S3040 OVERVIEW The S3040 supports clock recovery for the OC-48/ STM-16 data rate. Differential serial data is input to the chip at the specified rate and clock recovery is performed on the incoming data stream. An external oscillator is required to minimize the PLL lock time and provide a stable output clock source in the absence of serial input data. Retimed data and clock are output from the S3040. Sumitomo OC-48 Optical Receiver AMCC S3044 OC-48 DeMUX AMCC S3042 OC-48 DeMUX Figure 2. S3040 Functional Block Diagram CAP 1,2 LOOP FILTER VCO REFCLKP/N BYPASS SERCLKOP/N CLOCK DIVIDER LOCK DETECTOR LOCKDET LCKREFN PHASE DETECTOR SERDATOP/N SDN SERDATIP/N 2 April 4, 2000 / Revision D S3040A SONET/SDH CLOCK RECOVERY UNIT S3040 FUNCTIONAL DESCRIPTION The S3040 clock recovery device performs the clock recovery function for SONET OC-48 serial data links. The chip extracts the clock from the serial data inputs and provides retimed clock and data outputs. A 155.52 MHz reference clock is required for phase locked loop start-up and proper operation under loss of signal conditions. An integral prescaler and phase locked loop circuit is used to multiply this reference to the nominal bit rate. Clock Recovery Clock recovery, as shown in the block diagram in Figure 2, generates a clock that is at the same frequency as the incoming data bit rate at the serial data input. The clock is phase aligned by a PLL so that it samples the data in the center of the data eye pattern. Lock Detect The S3040 contains a lock detect circuit which monitors the integrity of the serial data inputs. If the received serial data fails the frequency test, the PLL will be forced to lock to the local reference clock. This will maintain the correct frequency of the recovered clock output under loss of signal or loss of lock conditions. If the recovered clock frequency deviates from the local reference clock frequency by more than the ppm stated in Table 3, the PLL will be declared out of lock. The lock detect circuit will poll the input data stream in an attempt to reacquire lock to data. If the recovered clock frequency is determined to be within the ppm stated in Table 3, the PLL will be declared in lock and the lock detect output will go active. The phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency discriminator. Output pulses from the discriminator indicate the required direction of phase corrections. These pulses are smoothed by an integral loop filter. The output of the loop filter controls the frequency of the Voltage Controlled Oscillator (VCO), which generates the recovered clock. Frequency stability without incoming data is guaranteed by an alternate reference input (REFCLK) that the PLL locks onto when data is lost. If the frequency of the incoming signal with respect to REFCLKP/N varies by greater than the ppm specified in Table 3, the PLL will be declared out of lock, and the PLL will lock to the reference clock. The assertion of SDN will also cause an out of lock condition. The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET data signal. This transfer function yields the typical capture time stated in Table 3 for random incoming NRZ data. The total loop dynamics of the clock recovery PLL yield a jitter tolerance which exceeds the minimum tolerance proposed for SONET equipment by the Bellcore TA-NWT-000253 standard, shown in Figure 4. April 4, 2000 / Revision D 3 S3040A CHARACTERISTICS SONET/SDH CLOCK RECOVERY UNIT Figure 3. Input Jitter Tolerance Specification Performance The S3040 PLL complies with the jitter specifications proposed for SONET/SDH equipment defined by the Bellcore Specifications: GR-253-CORE, Issue 2, December 1995 and ITU-T Recommendations: G.958 document, when used with differential inputs and outputs. Sinusodal Input Jitter Amplitude 15 (UI p-p) 1.5 0.4 Input Jitter Tolerance Input jitter tolerance is defined as the peak to peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1 dB optical/electrical power penalty. SONET input jitter tolerance requirements are shown in Figure 3. The measurement condition is the input jitter amplitude which causes an equivalent of 1 dB power penalty. Jitter Transfer Jitter transfer function is defined as the ratio of jitter on the output OC-N/STS-N signal to the jitter applied on the input OC-N/STS-N signal versus frequency. Jitter transfer requirements are shown in Figure 4. The measurement condition is that input sinusoidal jitter up to the mask level in Figure 3 be applied. f0 f2 f1 ft OC/STS Level f0 (Hz) f1 (Hz) f2 (Hz) f3 (kHz) ft (kHz) 48 10 600 6000 100 1000 Figure 4. Jitter Transfer Specification P slope = -20 dB/decade Jitter Transfer Acceptable Jitter Generation The jitter of the serial clock and serial data outputs shall not exceed 0.01 UI rms when a serial data input with no jitter is presented to the serial data inputs. (See Table 3). f3 Frequency Range fc Frequency OC/STS Level fc (MHz) P (dB) 481,2 2 0.1 1. Bellcore Specifications: GR-253- CORE, Issue 2, December 1995. 2. ITU-T Recommendations: G.958. 4 April 4, 2000 / Revision D S3040A SONET/SDH CLOCK RECOVERY UNIT Table 2. Pin Assignment and Descriptions Pin Name Level I/O Pin# Description SERDATIP/N Diff. PECL I 5,6 Serial Data In. (Internal Termination.) Clock is recovered from the transitions on these inputs. TTL I 20 Bypass Enable. Active High. Used during production test to bypass the VCO in the PLL. Tie to ground for normal operation. 11 Signal Detect. Active Low. A single-ended 10K PECL input to be driven by the external optical receiver module to indicate a loss of received optical power. When SDN is inactive, the data on the Serial Data In (SERDATIP/N) pins will be internally forced to a constant zero, and the PLL will be forced to lock to the REFCLK inputs. When SDN is active, data on the SERDATIP/N pins will be processed normally. 8,9 Reference Clock. 155.52 MHz input used to establish the initial operating frequency of the clock recovery PLL and also used as a standby clock in the absence of data, during reset or when SDN is inactive. I 28,27 Loop Filter Capacitor. The loop filter capacitor and resistors are connected to these pins. The resistor values are 82 5%. The capacitor value should be 1.0 F 10% tolerance, X7'R dielectric, 50 volt rating is recommended. (See Figure 13.) BYPASS SDN PECL REFCLKP/N Diff. PECL CAP1 CAP2 I I LCKREFN TTL I 10 Lock to Reference. Active Low. When active, the serial clock output will be forced to lock to the local reference clock input [REFCLK]. SERDATOP/N CM L O 19,18 Serial Data Out. This signal is the delayed version of the incoming data stream (SERDATI) updated on the falling edge of Serial Clock Out (SERCLKO). SERCLKOP/N CML O 23, 22 Serial Clock Out. This signal is phase aligned with Serial Data Out (SERDATOP/N). (See Figure 7.) LOCKDET TTL O 16 Lock Detect. Clock recovery indicator. Set High when the internal clock recovery has locked onto the incoming data stream. LOCKDET is an asynchronous output. AVCC +5V 2, 29 Analog power supply. AVEE 3,4, 21,30 Analog GND connection. VCC 12,14, 25 Power Supply. VEE 13,15, 26 Ground connection connected to exposed heatsink. NC 1, 7, 17, 24, 31, 32 April 4, 2000 / Revision D No connection. 5 SONET/SDH CLOCK RECOVERY UNIT S3040A 32 31 30 29 28 27 26 25 NC NC AVEE AVCC CAP1 CAP2 VEE VCC Figure 5. S3040 Pinout. S3040 (32 TQFP) TOP VIEW 24 23 22 21 20 19 18 17 NC SERCLKOP SERCLKON AVEE BYPASS SERDATOP SERDATON NC 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 REFCLKN LCKREFN SDN VCC VEE VCC VEE LOCKDET NC AVCC AVEE AVEE SERDATIP SERDATIN NC REFCLKP 6 April 4, 2000 / Revision D S3040A SONET/SDH CLOCK RECOVERY UNIT Figure 6. 32 TQFP Package TOP VIEW CONNECTED TO VEE BOTTOM VIEW Note: The S3040 package is equipped with an embedded conductive heatsink on the bottom (board side). Active circuitry and vias should not appear in the area immediately under the package. This heatsink is electrically biased to the VEE potential of the S3040. For optimum thermal management, a foil surface at ground (or VEE if other than ground) is recommended immediately under the package, and connected with multiple vias to the internal plane(s) of similar potential. Thermally conductive epoxy or other conductive interposer can be used to establish a good thermal dissipation path. Thermal Management Device S3040 April 4, 2000 / Revision D ja 36 C/W with heatsink soldered to ground plane jc 2 C/W 7 SONET/SDH CLOCK RECOVERY UNIT S3040A Table 3. Performance Specifications Parameters Min Nominal VCO Center Frequency Typ Max 2.5 12% Units Conditions GHz Data Output Jitter with VCO locked to REFCLK STS-48 155.52 MHz Ref. Clk 0.01 UI (rms) rms jitter, SDN active Data Output Jitter with VCO locked to SERDATIP/N STS-48 0.01 UI (rms) With no jitter on serial data inputs +100 pp m Reference Clock Frequency Tolerance -100 Capture Range Lock Range Capture Time 200 12% 32 ppm sec With respest to fixed reference frequency Minimum transition density of 20% Acquisition Lock Time Reference Clock Input Duty Cycle 16 sec 70% % of UI 1.0 ns 20% to 80% of amplitude 100 15 0 ps 20% to 80%, 50 load, 1pF cap 30% Reference Clock Rise and Fall Times CML Output Rise & Fall Times 8 Frequency difference at which out of lock is declared (REFCLK compared to the divided down VCO clock) 125 600 73 2 pp m Frequency difference at which receive PLL is declared in lock (REFCLK compared to the divided down VCO clock) 244 300 366 pp m tSU Setup time w.r.t. SERCLKOP 100 ps tH Hold time w.r.t. SERCLKOP 100 ps With device already powered up and valid ref. clk. April 4, 2000 / Revision D S3040A SONET/SDH CLOCK RECOVERY UNIT Table 4. Recommended Operating Conditions Parameter Min Ambient Temperature under Bias (industrial) Max Units -40 +85 C 0 +70 C Junction Temperature under Bias -10 +130 C Voltage on VCC with Respect to GND 4.75 5.25 V Voltage on Any TTL Input Pin 0.0 VC C V VCC -2 VC C V 220 250 mA Typ Max Units Ambient Temperature under Bias (commercial) Voltage on Any PECL Input Pin ICC Supply Current Typ 5. 0 Table 5. Absolute Maximum Ratings Parameter Min Storage Temperature -65 +150 C Voltage on VCC with Respect to GND -0.5 +7.0 V Voltage on any TTL Input Pin -0.5 +5.5 V VCC -2.0 VCC V TTL Output Sink Current 20 mA TTL Output Source Current 10 mA Voltage on any PECL Input Pin EDS Rating The S3040 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1500 V except pin 5, pin 6, pin 27, and pin 28. Figure 7. Receiver Output Timing Diagram Duty Cycle MAX 50% SERCLKOP tS Duty Cycle MIN tH SERDATOP/N Note: Setup and hold time is the time in pico seconds from the cross-over point of the reference signal to the cross-over point of the output. April 4, 2000 / Revision D 9 SONET/SDH CLOCK RECOVERY UNIT S3040A Table 6. Serial Input/Output DC Characteristics1 (TA = -40C to +85 C, VCC = 5 V 5%) Parameter Signal Name Min Max Units Conditions VIL Input Low Voltage VCC -2.00 VCC -1.47 Volts Guaranteed Input Low Voltage for all single ended inputs VIH2 Input High Voltage VCC -1.18 VCC -0.80 Volts Guaranteed Input High Voltage for all single ended inputs VIL2 Input Low Voltage VCC -2.0 VCC -0.70 Volts Guaranteed Input Low Voltage for all Differential inputs VIH2 Input High Voltage VCC -1.70 VCC -0.45 Volts Guaranteed Input Low Voltage for all Differential inputs VID2 Input Diff Voltage 40 1000 mV Guaranteed Input Diff Voltage for all Differential inputs uA Input Low Current 0 450 IIL VCC = MAX, VIL = Vcc -2 V SERDATIP/N 3.0 6.0 mA VCC = MAX, VDiff = 0.5 V REFCLKP REFCLKN SDN 100 450 uA VCC = MAX, VIL = Vcc -2 V 100 500 uA VCC = MAX, VIH = Vcc -0.80 V SERDATIP/N 3.5 6.4 mA VCC = MAX, VDiff = 0.5 V REFCLKP REFCLKN 100 500 uA VCC = MAX, VIH = Vcc -0.80 V IIH 1. 2. Description 2 Input High Current SDN VOL Output Low Voltage VCC -1.4 VCC -0.5 Volts 100 Line to Line VOH Output High Voltage VCC -0.4 VCC Volts 100 Line to Line VOD CML Output singleSERDATOP/N ended Voltage Swing SERCLKOP/N 280 600 mV 100 Line to Line VOD CML Output Diff Voltage Swing 560 1200 mV 100 Line to Line SERDATOP/N SERCLKOP/N These conditions will be met with no airflow. These input levels provide a zero-noise immunity and should only be tested in a static, noise-free environment. Table 7. TTL Input/Output DC Characteristics1 (TA = -40C to +85 C, VCC = 5 V 5%) Parameter Max Units 0.8 Volts Guaranteed Input Low Voltage for all inputs 2.0 Volts Guaranteed Input Low Voltage for all inputs -1 mA VCC = MAX, VIN = 0.5 V 50.0 uA VCC = MAX, VIN = 2.7 V 1.0 mA VCC = MAX, VIN = 5.25 V -5.0 mA VCC = MAX, VOUT = 0.5 V Volts VCC = MIN, IIN = -18.0 mA Volts VCC = MIN, IOL = 4 mA Volts VCC = MIN, IOH = -1.0 mA Input Low Voltage Input High Voltage IIL Input Low Current IIH Input High Current II Input High Current at Max VCC IOS Output Short Circuit Current -40 VIK Input Clamp Diode Voltage -1.2 VOL TTL Output Low Voltage VOH TTL Output High Voltage VIH 10 Min 2 VIL 1. 2. Description 2 0.5 2.4 Conditions These conditions will be met with no airflow. These input levels provide a zero-noise immunity and should only be tested in a static, noise-free environment. April 4, 2000 / Revision D S3040A SONET/SDH CLOCK RECOVERY UNIT Figure 8. +5 V Differential PECL Driver to S3040 Input Direct Coupled Termination +5 V Zo=50 330 330 +5 V Vcc -0.4 V 100 Zo=50 Vcc -0.4 V S3040 SERDATIP/N Figure 9. +5 V Differential PECL Driver to S3040 Input AC Coupled Termination +5 V 0.01 F Zo=50 330 330 +5 V Vcc -0.4 V 100 0.01 F Z =50 o Vcc -0.4 V S3040 SERDATIP/N Figure 10. S3040 CML Output Driver to S3042/S3044 Terminations +5 V 0.01 F Zo=50 +3.3 V Vcc -0.65 100 0.01 F S3040 SERDATOP/N SERCLKOP/N April 4, 2000 / Revision D Zo=50 Vcc -0.65 S3042/44 SERDATIP/N SERCLKIP/N 11 SONET/SDH CLOCK RECOVERY UNIT S3040A Figure 11. +3.3 V Single Ended LVPECL Driver to S3040 Reference Clock Input AC Coupled Termination +3.3 V 0.01 F Zo=50 150 Vcc -1.3 V +5 V 51 0.01 F Vcc -1.3 V S3043 155MCK S3040 REFCLKP/N Figure 12. +5 V Differential PECL Driver to S3040 Reference Clock Input AC Coupled Termination +5 V 0.01 F 330 330 0.01 F Vcc -1.3 V +5 V Zo=50 100 Zo=50 Vcc -1.3 V 155.52 MHz OSCILLATOR S3040 REFCLKP/N Figure 13. Loop Filter Capacitor Connections 82 CAP1 1.0 F CAP2 82 S3040 12 April 4, 2000 / Revision D S3040A SONET/SDH CLOCK RECOVERY UNIT Ordering Information PACKAGE 3040 A - 32 TQFP XXXX - X O 900 CE RT 1 IS X D S-commercial/ Industrial DEVICE E PREFIX IFI Applied Micro Circuits Corporation * 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 * (800)755-2622 * Fax: (858) 450-9885 http://www.amcc.com AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 2000 Applied Micro Circuits Corporation April 4, 2000 / Revision D 13