S3040A
SONET/SDH CLOCK RECOVERY UNIT
1
April 4, 2000 / Revision D
BiCMOS PECL CLOCK GENERATOR
DEVICE
SPECIFICATION
SONET/SDH CLOCK RECOVERY UNIT S3040A
®
FEATURES
•Micro-power Bipolar technology
•Complies with Bellcore, and ITU-T specifica-
tions for jitter tolerance, jitter transfer and
jitter generation
•On-chip high frequency PLL with internal
loop filter for clock recovery
•Supports clock recovery for
OC-48/STM-16
(2488.32 Mbit/s)
NRZ data
•155.52 MHz reference frequency
•Lock detect—monitors frequency
•Low-jitter serial interface
•+5 V supply
•32 TQFP Package
GENERAL DESCRIPTION
The function of the S3040 clock recovery unit is to
derive high speed timing signals for SONET/SDH-
based equipment. The S3040 is implemented using
AMCC’s proven Phase Locked Loop (PLL) technology.
The S3040 receives an OC-48/STM-16 scrambled
NRZ signal and recovers the clock from the data.
The chip outputs a differential bit clock and retimed
data.
The S3040 utilizes an on-chip PLL which consists
of a phase detector, a loop filter, and a Voltage
Controlled Oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter con-
verts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO
whose frequency is varied by this voltage. A block
diagram is shown in Figure 2.
Figure 1. System Block Diagram
Network Interface
Processor
S3045
S3041
MUX
S3042
DeMUX
S3042
DeMUX
S3041
MUX
OTX ORX
OTX
ORX
8
8
8
8
8
8
8
8
8
8
8
88
8
8
8
8
8
8
8
Network Interface
Processor
S3045
S3040
S3040
S3040A SONET/SDH CLOCK RECOVERY UNIT
2April 4, 2000 / Revision D
S3040 OVERVIEW
The S3040 supports clock recovery for the OC-48/
STM-16 data rate. Differential serial data is input to
the chip at the specified rate and clock recovery is
performed on the incoming data stream. An external
oscillator is required to minimize the PLL lock time and
provide a stable output clock source in the absence of
serial input data. Retimed data and clock are output
from the S3040.
Figure 2. S3040 Functional Block Diagram
SERCLKOP/N
LOCKDET
SERDATOP/N
REFCLKP/N
BYPASS
LCKREFN
SERDATIP/N
LOOP
FILTER VCO
CLOCK
DIVIDER
PHASE DETECTOR
LOCK
DETECTOR
SDN
CAP 1,2
Table 1. Suggested Interface Devices
Sumitomo OC-48 Optical Receiver
AMCC S3044 OC-48 DeMUX
AMCC S3042 OC-48 DeMUX
S3040A
SONET/SDH CLOCK RECOVERY UNIT
3
April 4, 2000 / Revision D
S3040 FUNCTIONAL DESCRIPTION
The S3040 clock recovery device performs the clock
recovery function for SONET OC-48 serial data links.
The chip extracts the clock from the serial data inputs
and provides retimed clock and data outputs. A
155.52 MHz reference clock is required for phase
locked loop start-up and proper operation under loss
of signal conditions. An integral prescaler and phase
locked loop circuit is used to multiply this reference to
the nominal bit rate.
Clock Recovery
Clock recovery, as shown in the block diagram in
Figure 2, generates a clock that is at the same fre-
quency as the incoming data bit rate at the serial
data input. The clock is phase aligned by a PLL so
that it samples the data in the center of the data eye
pattern.
The phase relationship between the edge transi-
tions of the data and those of the generated clock
are compared by a phase/frequency discriminator.
Output pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of
the Voltage Controlled Oscillator (VCO), which
generates the recovered clock.
Frequency stability without incoming data is guaran-
teed by an alternate reference input (REFCLK) that
the PLL locks onto when data is lost. If the frequency
of the incoming signal with respect to REFCLKP/N
varies by greater than the ppm specified in Table 3,
the PLL will be declared out of lock, and the PLL will
lock to the reference clock. The assertion of SDN will
also cause an out of lock condition.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET
data signal. This transfer function yields the typical
capture time stated in Table 3 for random incoming
NRZ data.
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which exceeds the minimum
tolerance proposed for SONET equipment by the
Bellcore TA-NWT-000253 standard, shown in Figure 4.
Lock Detect
The S3040 contains a lock detect circuit which monitors
the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be
forced to lock to the local reference clock. This will
maintain the correct frequency of the recovered clock
output under loss of signal or loss of lock conditions. If
the recovered clock frequency deviates from the local
reference clock frequency by more than the ppm stated
in Table 3, the PLL will be declared out of lock. The
lock detect circuit will poll the input data stream in an
attempt to reacquire lock to data. If the recovered clock
frequency is determined to be within the ppm stated in
Table 3, the PLL will be declared in lock and the lock
detect output will go active.
S3040A SONET/SDH CLOCK RECOVERY UNIT
4April 4, 2000 / Revision D
Figure 3. Input Jitter Tolerance Specification
Figure 4. Jitter Transfer Specification
1. Bellcore Specifications: GR-253- CORE, Issue 2, December 1995.
2. ITU-T Recommendations: G.958.
f0 f1 f2 f3 ft
0.4
1.5
15
Sinusodal
Input Jitter
Amplitude
(UI p-p)
Frequency
OC/STS
Level f0
(Hz) f2
(Hz) f3
(kHz) ft
(kHz)
f1
(Hz)
48 10 600 6000 100 1000
fc
P
Jitter
Transfer
Frequency
Acceptable
Range
slope = -20 dB/decade
CHARACTERISTICS
Performance
The S3040 PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the
Bellcore Specifications: GR-253-CORE, Issue 2, De-
cember 1995 and ITU-T Recommendations: G.958
document, when used with differential inputs and out-
puts.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to
peak amplitude of sinusoidal jitter applied on the
input signal that causes an equivalent 1 dB opti-
cal/electrical power penalty. SONET input jitter
tolerance requirements are shown in Figure 3.
The measurement condition is the input jitter am-
plitude which causes an equivalent of 1 dB power
penalty.
Jitter Transfer
Jitter transfer function is defined as the ratio of jitter
on the output OC-N/STS-N signal to the jitter applied
on the input OC-N/STS-N signal versus frequency.
Jitter transfer requirements are shown in Figure 4.
The measurement condition is that input sinusoidal
jitter up to the mask level in Figure 3 be applied.
Jitter Generation
The jitter of the serial clock and serial data outputs
shall not exceed 0.01 UI rms when a serial data input
with no jitter is presented to the serial data inputs.
(See Table 3).
OC/STS
Level fc
(MHz) P
(dB)
48
1,2
2 0.1
S3040A
SONET/SDH CLOCK RECOVERY UNIT
5
April 4, 2000 / Revision D
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Table 2. Pin Assignment and Descriptions
S3040A SONET/SDH CLOCK RECOVERY UNIT
6April 4, 2000 / Revision D
1
2
3
4
5
6
7
8
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
S3040
(32 TQFP)
NC
SERCLKOP
SERCLKON
AVEE
BYPASS
SERDATOP
SERDATON
NC
9
10
SDN
VCC
VEE
VCC
VEE
LOCKDET
REFCLKN
LCKREFN 32
31 AVEE
AVCC
CAP1
CAP2
VEE
VCC
NC
NC
NC
AVCC
AVEE
AVEE
SERDATIP
SERDATIN
NC
REFCLKP
TOP VIEW
16
Figure 5. S3040 Pinout.
S3040A
SONET/SDH CLOCK RECOVERY UNIT
7
April 4, 2000 / Revision D
Note: The S3040 package is equipped with an embedded conductive heatsink on the bottom (board side). Active circuitry and vias should not
appear in the area immediately under the package. This heatsink is electrically biased to the VEE potential of the S3040. For optimum thermal
management, a foil surface at ground (or VEE if other than ground) is recommended immediately under the package, and connected with
multiple vias to the internal plane(s) of similar potential. Thermally conductive epoxy or other conductive interposer can be used to establish a
good thermal dissipation path.
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Thermal Management
Figure 6. 32 TQFP Package
TOP VIEW
BOTTOM VIEW
CONNECTED
TO VEE
S3040A SONET/SDH CLOCK RECOVERY UNIT
8April 4, 2000 / Revision D
Table 3. Performance Specifications
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ycneuqerFkcolCecnerefeR ecnareloT 001-001+mpp
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llaFdnaesiRkcolCecnerefeR semiT 0.1snedutilpmafo%08ot%02
semiTllaF&esiRtuptuOLMC001051sp05,%08ot%02 Ω,daol
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521006237mpp
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442003663mpp
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S3040A
SONET/SDH CLOCK RECOVERY UNIT
9
April 4, 2000 / Revision D
Table 4. Recommended Operating Conditions
Table 5. Absolute Maximum Ratings
Note: Setup and hold time is the time in pico seconds from the cross-over point of the reference signal to the cross-over point of
the output.
SERDATOP/N
SERCLKOP
tS tH
50% Duty Cycle MIN
Duty Cycle MAX
Figure 7. Receiver Output Timing Diagram
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saiBrednuerutarepmeTnoitcnuJ01-031+C˚
DNGottcepseRhtiwCCVnoegatloV57.40.552.5V
niPtupnILTTynAnoegatloV0.0CCVV
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tnerruCylppuSCCI 022052Am
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The S3040 is rated to the following ESD voltages based on the human body model:
1. All pins are rated at or above 1500 V except pin 5, pin 6, pin 27, and pin 28.
EDS Rating
S3040A SONET/SDH CLOCK RECOVERY UNIT
10 April 4, 2000 / Revision D
Table 7. TTL Input/Output DC Characteristics
1
DescriptionParameter ConditionsMin Max Units
VIL
2
VIH
2
IIL
IIH
II
IOS
VIK
VOL
VOH
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Input High Current at Max
VCC
Output Short Circuit Current
Input Clamp Diode Voltage
TTL Output Low Voltage
TTL Output High Voltage
Guaranteed Input Low Voltage for all inputs
VCC = MAX, VIN = 0.5 V
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 5.25 V
VCC = MAX, VOUT = 0.5 V
VCC = MIN, IIN = -18.0 mA
VCC = MIN, IOL = 4 mA
VCC = MIN, IOH = -1.0 mA
2.0
-1
-40
2.4
0.8
50.0
1.0
-5.0
0.5
Volts
Volts
mA
uA
mA
mA
Volts
Volts
-1.2 Volts
Guaranteed Input Low Voltage for all inputs
(TA = -40°C to +85° C, VCC = 5 V ± 5%)
(TA = -40°C to +85° C, VCC = 5 V ± 5%)
1. These conditions will be met with no airflow.
2. These input levels provide a zero-noise immunity and should only be tested in a static, noise-free environment.
Description
Parameter
ConditionsMin Max UnitsSignal Name
VIL
2
Input Low Voltage Guaranteed Input Low Voltage
for all single ended inputs
VCC
-2.00
VCC
-1.47
Volts
VIH
2
Input High Voltage Guaranteed Input High Voltage
for all single ended inputs
VCC
-1.18
VCC
-0.80
Volts
VIL
2
Input Low Voltage Guaranteed Input Low Voltage
for all Differential inputs
VCC
-2.0
VCC
-0.70
Volts
VIH
2
Input High Voltage Guaranteed Input Low Voltage
for all Differential inputs
VCC
-1.70
VCC
-0.45
Volts
VOL
Output Low Voltage
100 Ω Line to Line
VCC -1.4 VCC -0.5 Volts
IIL Input Low Current VCC = MAX, VIL = Vcc -2 V
0450 uA
3.0 6.0 mA
SDN
SERDATIP/N
IIH Input High Current VCC = MAX, VIH = Vcc -0.80 V
VCC = MAX, VDiff = 0.5 V
100 500 uA
3.5 6.4 mA
SDN
SERDATIP/N
VOH
Output High Voltage
100 Ω Line to Line
VCC -0.4 VCC Volts
VID
2
Input Diff Voltage Guaranteed Input Diff Voltage
for all Differential inputs
40 1000 mV
VCC = MAX, VDiff = 0.5 V
100 450 uA
REFCLKP
REFCLKN VCC = MAX, VIL = Vcc -2 V
100 500 uA
REFCLKP
REFCLKN VCC = MAX, VIH = Vcc -0.80 V
VOD
CML Output single-
ended Voltage Swing
100 Ω Line to Line
280 600 mV
SERDATOP/N
SERCLKOP/N
VOD
CML Output Diff
Voltage Swing
100 Ω Line to Line
560 1200 mV
SERDATOP/N
SERCLKOP/N
1. These conditions will be met with no airflow.
2. These input levels provide a zero-noise immunity and should only be tested in a static, noise-free environment.
Table 6. Serial Input/Output DC Characteristics
1
S3040A
SONET/SDH CLOCK RECOVERY UNIT
11
April 4, 2000 / Revision D
Vcc -0.4 V
Vcc -0.4 V
+5 V
100 Ω
330 Ω
330 Ω
S3040
SERDATIP/N
+5 V
Zo=50 Ω
Zo=50 Ω
Vcc -0.4 V
Vcc -0.4 V
S3040
SERDATIP/N
+5 V
330 Ω
330 Ω
100 Ω
0.01 µF
0.01 µF
+5 V
Zo=50 Ω
Zo=50 Ω
Figure 8. +5 V Differential PECL Driver to S3040 Input Direct Coupled Termination
Figure 9. +5 V Differential PECL Driver to S3040 Input AC Coupled Termination
+5 V
S3040
SERDATOP/N
SERCLKOP/N
+3.3 V
S3042/44
SERDATIP/N
SERCLKIP/N
0.01 µFVcc -0.65
0.01 µF
100 Ω
Vcc -0.65
Zo=50 Ω
Zo=50 Ω
Figure 10. S3040 CML Output Driver to S3042/S3044 Terminations
S3040A SONET/SDH CLOCK RECOVERY UNIT
12 April 4, 2000 / Revision D
Figure 11. +3.3 V Single Ended LVPECL Driver to S3040 Reference Clock
Input AC Coupled Termination
Figure 12. +5 V Differential PECL Driver to S3040 Reference Clock
Input AC Coupled Termination
Vcc -1.3 V
Vcc -1.3 V
S3040
REFCLKP/N
+3.3 V
51 Ω
150 Ω
0.01 µF
0.01 µF+5 V
S3043
155MCK
Zo=50 Ω
CAP1
82 Ω
1.0 µF
CAP2
82 Ω
S3040
Figure 13. Loop Filter Capacitor Connections
Vcc -1.3 V
Vcc -1.3 V
S3040
REFCLKP/N
+5 V
100 Ω
330 Ω
330 Ω
0.01 µF
0.01 µF
+5 V
155.52 MHz
OSCILLATOR
Zo=50 Ω
Zo=50 Ω
S3040A
SONET/SDH CLOCK RECOVERY UNIT
13
April 4, 2000 / Revision D
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright ® 2000 Applied Micro Circuits Corporation
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121
Phone: (858) 450-9333 • (800)755-2622 • Fax: (858) 450-9885
http://www.amcc.com
PREFIX DEVICE PACKAGE
S-commercial/ 3040 A – 32 TQFP
Industrial
Ordering Information
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