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DATA BRIEF
September 2004
For furth er information con tact your local ST sales office.
ST22L032, ST22L064
ST22L096, ST22L128
Smartcard 32-Bit RISC MCU with 32, 64, 96, 128 Kbytes
EEPROM, Javacard™ HW Execution & Cryptogra phic Libra ry
7
PRODUCT FEATURES
■32-BIT RISC CPU WITH 24-BIT LINE AR
MEMORY AD D R ESSING
■246 KBYTES USER ROM
■8 KBYTES USER RAM
■32 (L032), 64 (L064), 96 (L096) or 128 (L128)
KBYTES USER EEPR O M
32-BIT RISC CP U
■DUAL INSTRUCTION SET, JAVACARD™
AND NATIVE
■4-STA GE PIPELINE
■16 GENERAL PURPO SE 32-BIT
REGISTERS, AND SPECIAL R EGI STERS
■4 MASKABLE INTERRUPT LEVEL S
■SUPERVISOR AND USER MODES
SECURITY
■CPU SECURITY INSTRUCTIONS
–Dedicated instruct ions for DES and T riple
DES implementation
–Dedicated instructions (Mult i ply and
Accumulate) for efficient implementation
of modular arithmetic and elliptic curves
based cryptosystems
–CRC instruction (IS O 3309 16-bit
Checksum)
■RANDOM NUMBER GENERATOR
■EEPROM FLASH PROGRAMMING MODE
■CLOCK AND POWER MANAG EMENT
■VOLTAG E AND CL OCK FREQU EN CY
SENSORS
■ADVANCED MEMORY PROTECTION
–Memo r y Pr o t e c tion U ni t for application
firewalling and peripheral acces s control
–Domain switchi n g securel y contr oll e d by
protected Context S tack
–Native/Java, Code /Data memory
attributes wi th 128-byte granularity
■FOUR WO RKING STACKS
–Java stack with both 16 and 32-bit
accesses
–User and Supervisor mode stacks
–Security Cont ext Stack
Figure 1. Delivery Form
4
4
4
4
Micromodule Wafer
ST22L032, L064, L 096, L128
2/7
CRYPTOGRAPHIC LIBRARY
The Crypto Library is provided as a separate ROM
area with an ac ces s t hrough a unique en try poi nt.
This library provides optimized -for the SmartJ
core- and secured implementation of the following
features:
■ASYMMETRICAL AL GORITH MS
–RSA signature/verification
–Prime num ber generat ion (up to 1024-bit)
–RSA key comput ation (up to 2048-bit)
■HASH FUNCTION
–SHA-1
■SYMMETRICAL ALGORITHMS
–DES, Trip l e D E S, AES
CRYPTOGRAPHY PERFORMANCE
The following table provides the cryptographic
performances of the ST22Lxxx based on ST Cryp-
to Library.
Table 1. Preliminary Crypto gr aph ic
Performances
MEMORY
■HIGHLY REL IABLE CMOS EEPROM
TECHNOLOGY
–Error Correction Code for single bi t fail
within a 32-bit word
–10 years data retention, 500,000 Erase/
Write cycles en durance
–1 to 128 by tes Erase or Program in 2 ms
typical
■HIGH PERF ORMANCE MEMORY
–Dual memory buses for data and
instruction
–Byte, Short (2) and Word (4) load and
store
–Address aut o-increme nt
OTHER FEATURES
■HARDW ARE ASYNCHRONOUS SERIAL
INTERFACE ( ASI)
–1M baud rat e capa bilit y
–2 seri al I/O por ts compati ble ISO 7816-3
T=0 and T= 1
■2 USER CONFIGURA BLE 12-BI T AND 16-
BIT TIMERS WITH INTERRUPT
■CENTRAL INTERRUPT CONTROLLER
WITH UP TO 16 INPUT LINES
■EXTERNA L CLO CK FROM 1 MHz TO 10
MHz
■1.62 V TO 5.5 V SUPPLY VOLTAGE
■TEMPERA TURE RANGE -25° C to +85° C
■POWER SAVI N G STAN DBY MODE
■ESD PROTECT ION GREATER T HAN 5000 V
■UNIQUE IDENTIFICATION PER DIE
■TYPICAL I NTERNAL FREQUENCY UP TO
33 MHz
■SOFT WARE CONTRO LLED CLOCK
MANAGEMENT
Algorithm Function Time(1)
1. Int ernal cl ock at 33 MH z
RSA
1024 bits
Signature with CRT 79.0 ms
Signature without CRT(2)
2. CRT : Chines e Reminder Theorem
242.0 ms
Verification (e=0x10001) 3.6 ms
RSA
2048 bits
Signature with CRT 485.0 ms
Signature without CRT 1.7 s
Verification (e=0x10001) 11.0 ms
DES Triple 18 µs
Single 8 µs
SHA-1 512-bit Block 194 µs
AES-128 Encryption including subkey
computation 85 µs
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ST22L032, L064, L096, L128
DESCRIPTION
The ST22Lxxx is a member o f the SmartJ™ pla t-
form using a 32-bit Reduced Instruction Set Com-
puter (RISC) core to execute both Native RISC
instructions and JavaCard™2.x Technology in-
struction (byte codes) directly(See Figure 2.
"SmartJ™ Platform EEPROM Architecture", on
page 3) .
Direct JavaCard™ byte code execution provides
high performance advantage over processors that
emulate the JavaCard™ byte code instruction set.
The product features a 24-bit wide linear address-
ing capability and includes User ROM, User RAM,
and User EEPROM.
Memory and Peripheral accesses are controlled
by a Memory Protection Unit t hat allows to imple-
ment firewalls between applications .
Memories are accessed via two different buses,
allowing simultaneous accesses to code and data.
Memory load and stores can be perf ormed at byt e,
short (2-bytes), or word (4-bytes) granularity, with
optional pointer auto increm ent.
The ST22 core in cludes dedicated instructions to
accelerate performanc es of the following algoriths:
–D ES and Triple DES
–Modular Arithmetic on big numbers,
–C haracteristic two field arithmetic to s upp ort
e ff ic ien t ly El lip t ic C ur ve s,
–CRC 16-bit ISO 3309.
The product has clock an d power man agem ent, 2
User configurable Timers, a Central Interrupt Con-
troller and a Random Number Gener ator.
Figure 2. SmartJ™ P latform EEPR O M Architecture
POWER MANAGEMENT
32-bit
RISC
CORE
CLOCK MANAGEMENT
MPU
RAM
BUS 2
BUS 1
SECURITY
TIMER
RNG
...
...
ASI
PERIPHERALS
ISO
7816
ROM EEPROM
ST22L032, L064, L 096, L128
4/7
The product has two execution modes. Java mode
is used w hen JavaCard™ 2.x byte codes are be-
ing executed. Native mode is used for long JavaC-
ard™ byte codes, Native methods and system
routines. The processor enters Java mode when a
dispatch (DISP) instruction is enc ountered. When
executing in Native mode, there are two privilege
levels, User and Supervisor. Some instructions
can only be executed in Supervisor mode.
Instructions are of variable length, from 1 to 4
bytes in Native m ode.
Specia l i nstruct ions ex ist for single -cycle st ack op -
erations, a frequent occurrence in Java code.
Short branches and conditional branche s within a
1 KByte block or the entire 16-MByte instruction
space are supported. T he product has four stages
of pipel ine in Native mode: f etch, decode, execute
and write-back. In Java mode, there are five stag-
es of pipeline: byte code-fetch, byte code-decode,
decode, execu te and write-back.
The CPU core has 16 32-bit general purpose reg-
isters, as well as special registers of variable
length.
The chip also features a very high performance
Asynchronous Serial Interface (ASI) to support
high speed serial communication protocols com-
patible with ISO 7816 standard.
It is manufactured using the highly reliable ST
CMOS E EPR OM technology.
EMBEDDED SOFTWARE
The Hardware Software Interface (HSI) imple-
ments the Hardware abstraction layer. It consists
of C interfaces to the EEPROM memory and pe-
ripherals. The drivers are:
–Non Volatile Memory
–Async hronou s Serial Interface
–Central Interr upt Controller
–Timer
–Random Number Generator
–Cl ock Manager
–Memory Protection Unit
–Sensors
–Security
Note:
–The HS I driver sof tw are layer is a C-orient ed
API allowing efficient and secureac cess to the
peripheral s and Non Volatile Memory for
programmi ng or erasing.
–Only the OS and JavaCard™ Virtual Machine
(JVM ) domains can acces s the HSI software
layer (In the fol lowing t he t erm OS wil l refer to
the software layer that is directly interfaced to
the HSI).
CRYPTOGRAPHIC LIBRARY
ST proposes a complete set of firmware subrou-
tines to allow fast and easy implementation of
cryptographic protocols. These subroutines have
been optim ized according to the S T22 core speci-
ficities and dedicated instruction s. Security issues
have been addressed to provide state of the art
security. The wh ole library i s located in a specific
ROM area access through a single entry point.
Following features are available through library:
■ASYMMETRICAL AL GORITH MS:
–Basic mo dular arithmetic for various
lengths in cludi ng modular product for odd
modulus.
–More elabo rate functions (with separate
fast and secure versions) such as
exponentiation, RSA s ignatures and
verifications for modulo l ength up to 2048
bits long.
–Full internal RSA key generation. This
guarantees that the secret key will never
be known outside the chip and will
contribute to the overall system security.
–Long random number generat i on
–SHA-1
■SYMMETRICAL ALGORITHMS
–DES, T riple DES
–AES- 128 , 1 9 2, 25 6
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ST22L032, L064, L096, L128
SOFTWARE DEVELOPMENT ENVIRONMENT
Modularity, flexibility and methodology are the key
words for the SmartJ™ Development Tools Plat-
form. Using the same interface, the developers are
able to create, compi le and debug a project.
The SmartJ™ Integrated Development environ-
ment (IDE) includes:
–A code Generation c hai n: C/C++ com piler,
assembler and linker. The assembler supports
both native and JavaCard™ instruction sets.
–An instruct ion se t simu lator, a cycle accurat e
simul ator, a C/C++ source level debugger.
Software and Hardware tools allow to
efficiently generate, then validate all code and
application embbeded softwares for the
SmartJ™ platform.
Figure 3. SmartJ™ IDE
ST22L032, L064, L 096, L128
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Figure 4. SmartJ™ Code Ge nera t i on Tools
Figure 5. SmartJ™ C o de V ali dation Tools
C/C++
Standard
Libraries
C/C++ Compiler
Linker
C/C++ Source Asm Source
Native/Java Assembler
Object
Files
SCP 160c/PRZ
HSI
Library C ry p to .
Library
D ev ice S et-u p
Application
Debugger GU I
D EBUG G ER CO RE
> Console.exe Third party tools ST PLAYER
In teg rate d Developmen t Environm ent
Sm artCard Pod
Sm ar tC ard
Reader
Cycle
accurate
Simulator
Instruc tion
Set Simulator Monitor
FPG A
Board
160d
ASI
TimerRandom...
PC/SC
Virtual interface
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ST22L032, L064, L096, L128
Information furnished is believed to be accurate and reliable. However, S TMi croelectronics assumes no responsibi lity for the consequences
of use of such information nor for any inf ringement of patents or other rights of third parties which may result from it s use. No license is granted
by i m pl i cation or oth erwise under any patent or paten t rights of STMi croelectron i cs . Specifications ment i oned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as c ri tical components in lif e support devices or systems wi t hout express wri t ten approval of STM i croelectronics.
The ST l ogo i s a regist ered tra dem ark of STM i croelectronic s.
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