FPD-Link III
2 Lane
VDDIO
1.8V
IDx
DOUT0+
DOUT0-
1.1V
IN_CLK-/+
HDMI
HPD
DDC
CEC
DOUT1+
DOUT1-
RIN0+
RIN0-
RIN1+
RIN1-
CLK+/-
CLK2+/-
FPD-Link
(Open LDI)
D0+/-
D1+/-
D2+/-
D3+/-
D4+/-
D5+/-
D6+/-
D7+/-
DS90UH949-Q1
Serializer DS90UH948-Q1
Deserializer
IDx
D_GPIO
(SPI)
D_GPIO
(SPI)
LVDS
Display
1080p60
or Graphic
Processor
Graphics
Processor
IN_D0-/+
IN_D1-/+
IN_D2-/+
I2C
VDDIO
(3.3V / 1.8V)
3.3V
I2C
1.2V1.8V
HDCP ± High-Bandwidth Content Protection
HDMI ± High Definition Multimedia Interface
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
DS90UH949-Q1
SNLS453 –NOVEMBER 2014
DS90UH949-Q1 1080p HDMI to FPD-Link III Bridge Serializer with HDCP
1 Features 3 Description
The DS90UH949-Q1 is a HDMI to FPD-Link III bridge
1• Supports TMDS Clock up to 170 MHz for WUXGA device which, in conjunction with the FPD-Link III
(1920x1200) and 1080p60 Resolutions with 24-Bit DS90UH940-Q1/DS90UH948-Q1 deserializers,
Color Depth provides 1-lane or 2-lane high-speed serial streams
• Single and Dual FPD-Link III Outputs over cost-effective 50Ωsingle-ended coaxial or 100Ω
differential shielded twisted-pair (STP) cables. It
• High-Definition Multimedia (HDMI) v1.4b Inputs serializes a HDMI v1.4b input supporting video
• HDMI-Mode DisplayPort (DP++) Inputs resolutions up to WUXGA and 1080p60 with 24-bit
• Integrated HDCP v1.4 Cipher Engine with On- color depth.
Chip Key Storage The FPD-Link III interface supports video and audio
• HDMI Audio Extraction for up to 8 Channels data transmission and full duplex control, including
• High Speed Back Channel Supporting GPIO up to I2C and SPI communication, over the same
2 Mbps differential link. Consolidation of video data and
control over two differential pairs reduces the
• Supports up to 15 Meters of Cable with Automatic interconnect size and weight and simplifies system
Temperature and Aging Compensation design. EMI is minimized by the use of low voltage
• Tracks Spread Spectrum Input Clock to Reduce differential signaling, data scrambling, and
EMI randomization. In backward compatible mode, the
• I2C (Master/Slave) with 1Mbps Fast-Mode Plus device supports up to WXGA and 720p resolutions
with 24-bit color depth over a single differential link.
• SPI Pass-Through Interface
• Backward compatible with DS90UH926Q-Q1 and The DS90UH949-Q1 supports HDCP Repeater
applications where all authentication and encryption
DS90UH928Q-Q1 FPD-Link III Deserializers functions are handled without the need for an
• Automotive Grade Product: AEC-Q100 Grade 2 external controller. HDMI audio and video data are
Qualified decrypted at the input and re-encrypted prior to
sending onto the FPD-Link III interface.
2 Applications The DS90UH949-Q1 supports multi-channel audio
• Automotive Infotainment: received through HDMI or an external I2S interface.
– IVI Head Units and HMI Modules The device also supports an optional auxiliary audio
interface.
– Rear Seat Entertainment Systems
– Digital Instrument Clusters Device Information(1)
• Security and Surveillance Camera PART NUMBER PACKAGE BODY SIZE (NOM)
• Consumer Input HDMI Port DS90UH949-Q1 VQFN RGC (64) 9.00 mm X 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Applications Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UH949-Q1
SNLS453 –NOVEMBER 2014
www.ti.com
Table of Contents
8.3 Feature Description................................................. 18
1 Features.................................................................. 18.4 Device Functional Modes........................................ 31
2 Applications ........................................................... 18.5 Programming........................................................... 34
3 Description............................................................. 18.6 Register Maps......................................................... 37
4 Applications Diagram............................................ 19 Application and Implementation ........................ 71
5 Revision History..................................................... 29.1 Applications Information.......................................... 71
6 Pin Configuration and Functions......................... 39.2 Typical Applications ................................................ 71
7 Specifications......................................................... 710 Power Supply Recommendations ..................... 76
7.1 Absolute Maximum Ratings ..................................... 710.1 Power Up Requirements And PDB Pin................. 76
7.2 Handling Ratings....................................................... 711 Layout................................................................... 77
7.3 Recommended Operating Conditions....................... 711.1 Layout Guidelines ................................................. 77
7.4 Thermal Information.................................................. 811.2 Layout Example .................................................... 78
7.5 DC Electrical Characteristics .................................... 912 Device and Documentation Support................. 79
7.6 AC Electrical Characteristics................................... 11 12.1 Documentation Support ....................................... 79
7.7 DC And AC Serial Control Bus Characteristics ...... 12 12.2 Trademarks........................................................... 79
7.8 Recommended Timing for the Serial Control Bus .. 13 12.3 Electrostatic Discharge Caution............................ 79
7.9 Typical Characteristics............................................ 16 12.4 Glossary................................................................ 79
8 Detailed Description............................................ 17 13 Mechanical, Packaging and Orderable
8.1 Overview................................................................. 17 Information........................................................... 79
8.2 Functional Block Diagram....................................... 17
5 Revision History
DATE REVISION NOTES
November 2014 * Initial release.
2Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: DS90UH949-Q1
VDD18
VDDIO
SDIN / GPIO0
RES0
IN_D0-
VTERM
IN_D0+
VDDHA11
IN_D1-
IN_D1+
SCL
VDDHS11
VDD18
RES2
PDB
VDDA11
D_GPIO0 / MOSI
DOUT0-
DOUT0+
MCLK
VDDS11
DOUT1-
DOUT1+
IN_D2-
VDDHA11
CEC
IN_D2+
VDD18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VDDHA11
I2S_DC / GPIO2
I2S_DD / GPIO3
VDDHA11
LFT
MODE_SEL0
IDx
RX_5V
IN_CLK-
IN_CLK+
VDDL11
X1
REM_INTB
SCLK / I2CSEL
VDDL11
RES1
VDDHS11
DDC_SDA
NC1
DDC_SCL
NC0
SDA
INTB
D_GPIO3 / SS
D_GPIO2 / SPLK
I2S_WC / GPIO7_REG
I2S_DB / GPIO5_REG
I2S_CLK / GPIO8_REG
I2S_DA / GPIO6_REG
D_GPIO1 / MISO
MODE_SEL1
NC2
HPD
SWC / GPIO1
DS90UH949-Q1
DAP = GND
VDDP11
VDDIO
64 VQFN
Top View
DS90UH949-Q1
www.ti.com
SNLS453 –NOVEMBER 2014
6 Pin Configuration and Functions
64 PINS
Top View
Pin Functions
PIN I/O, TYPE DESCRIPTION
NAME NO.
HDMI TMDS INPUT
IN_CLK- 49 I, TMDS TMDS Clock Differential Input
IN_CLK+ 50
IN_D0- 55 I, TMDS TMDS Data Channel 0 Differential Input
IN_D0+ 56
IN_D1- 59 I, TMDS TMDS Data Channel 1 Differential Input
IN_D1+ 60
IN_D2- 62 I, TMDS TMDS Data Channel 2 Differential Input
IN_D2+ 63
OTHER HDMI
HPD 42 O, Open- Hot Plug Detect Output. Pull up to RX_5V with a 1kΩresistor
Drain
RX_5V 43 I HDMI 5V Detect Input
DDC_SDA 44 IO, Open- DDC Slave Serial Data
Drain Pull up to RX_5V with a 47kΩresistor
DDC_SCL 45 I, Open-Drain DDC Slave Serial Clock
Pull up to RX_5V with a 47kΩresistor
Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: DS90UH949-Q1
DS90UH949-Q1
SNLS453 –NOVEMBER 2014
www.ti.com
Pin Functions (continued)
PIN I/O, TYPE DESCRIPTION
NAME NO.
CEC 1 IO, Open- Consumer Electronic Control Channel Input/Output Interface.
Drain Pull-up with a 27kΩresistor to 3.3V
X1 39 I, LVCMOS Optional Oscillator Input: This pin is the optional reference clock for CEC. It must be
connected to a 25 MHz 0.1% (1000ppm), 45-55% duty cycle clock source at CMOS-level
1.8V. Leave it open if unused.
FPD-LINK III SERIAL
DOUT0- 26 O FPD-Link III Inverting Output 0
The output must be AC-coupled with a 0.1µF capacitor for interfacing with 92x deserializers
and 33nF capacitor for 94x deserializers
DOUT0+ 27 O FPD-Link III True Output 0
The output must be AC-coupled with a 0.1µF capacitor for interfacing with 92x deserializers
and 33nF capacitor for 94x deserializers
DOUT1- 22 O FPD-Link III Inverting Output 1
The output must be AC-coupled with a 0.1µF capacitor for interfacing with 92x deserializers
and 33nF capacitor for 94x deserializers
DOUT1+ 23 O FPD-Link III True Output 1
The output must be AC-coupled with a 0.1µF capacitor for interfacing with 92x deserializers
and 33nF capacitor for 94x deserializers
LFT 20 Analog FPD-Link III Loop Filter
Connect to a 10nF capacitor to GND
CONTROL
SDA 14 IO, Open- I2C Data Input / Output Interface
Drain Open drain. Must have an external pull-up to resistor to 1.8V or 3.3V. See I2CSEL pin. DO
NOT FLOAT.
Recommended pull-up: 4.7kΩ.
SCL 15 IO, Open- I2C Clock Input / Output Interface
Drain Open drain. Must have an external pull-up resistor to 1.8V or 3.3V. See I2CSEL pin. DO
NOT FLOAT.
Recommended pull-up: 4.7kΩ.
I2CSEL 6 I, LVCMOS I2C Voltage Level Strap Option
Tie to VDDIO with a 10kΩresistor for 1.8V I2C operation.
Leave floating for 3.3V I2C operation.
This pin is read as an input at power up.
IDx 19 Analog I2C Serial Control Bus Device ID Address Select
MODE_SEL0 18 Analog Mode Select 0. See Table 6.
MODE_SEL1 32 Analog Mode Select 1. See Table 6.
PDB 31 I, LVCMOS Power-Down Mode Input Pin
INTB 13 O, Open- Open Drain. Remote interrupt. Active LOW.
Drain Pull up to VDDIO with a 4.7kΩresistor.
REM_INTB 40 O, Open- Remote interrupt. Mirrors status of INTB_IN from the deserializer.
Drain Note: External pull-up to 1.8V required. Recommended pull-up: 4.7kΩ.
INTB = H, Normal Operation
INTB = L, Interrupt Request
SPI PINS (DUAL LINK MODE ONLY)
MOSI 8 IO, LVCMOS SPI Master Out Slave In. Shared with D_GPIO0
MISO 10 IO, LVCMOS SPI Master In Slave Out. Shared with D_GPIO1
SPLK 11 IO, LVCMOS SPI Clock. Shared with D_GPIO2
SS 12 IO, LVCMOS SPI Slave Select. Shared with D_GPIO3
HIGH SPEED (HS) BIDIRECTIONAL CONTROL CHANNEL GPIO PINS (DUAL LINK MODE ONLY)
D_GPIO0 8 IO, LVCMOS HS GPIO0. Shared with MOSI
D_GPIO1 10 IO, LVCMOS HS GPIO1. Shared with MISO
D_GPIO2 11 IO, LVCMOS HS GPIO2. Shared with SPLK
D_GPIO3 12 IO, LVCMOS HS GPIO3. Shared with SS
4Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: DS90UH949-Q1
DS90UH949-Q1
www.ti.com
SNLS453 –NOVEMBER 2014
Pin Functions (continued)
PIN I/O, TYPE DESCRIPTION
NAME NO.
BIDIRECTIONAL CONTROL CHANNEL (BCC) GPIO PINS
GPIO0 4 IO, LVCMOS BCC GPIO0. Shared with SDIN
GPIO1 5 IO, LVCMOS BCC GPIO1. Shared with SWC
GPIO2 37 IO, LVCMOS BCC GPIO2. Shared with I2S_DC
GPIO3 38 IO, LVCMOS BCC GPIO3. Shared with I2S_DD
REGISTER-ONLY GPIO
GPIO5_REG 36 IO, LVCMOS General Purpose Input/Output 5
Local register control only. Shared with I2S_DB
GPIO6_REG 35 IO, LVCMOS General Purpose Input/Output 6
Local register control only. Shared with I2S_DA
GPIO7_REG 33 IO, LVCMOS General Purpose Input/Output 7
Local register control only. Shared with I2S_WC
GPIO8_REG 34 IO, LVCMOS General Purpose Input/Output 8
Local register control only. Shared with I2S_CLK
SLAVE MODE LOCAL I2S CHANNEL PINS
I2S_WC 33 I, LVCMOS Slave Mode I2S Word Clock Input. Shared with GPIO7_REG
I2S_CLK 34 I, LVCMOS Slave Mode I2S Clock Input. Shared with GPIO8_REG
I2S_DA 35 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO6_REG
I2S_DB 36 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO5_REG
I2S_DC 37 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO2
I2S_DD 38 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO3
AUXILIARY I2S CHANNEL PINS
SWC 5 O, LVCMOS Master Mode I2S Word Clock Ouput. Shared with GPIO1
SCLK 6 O, LVCMOS Master Mode I2S Clock Ouput. Shared with I2CSEL. This pin is sampled following power-up
as I2CSEL, then it will switch to SCLK operation as an output.
SDIN 4 I, LVCMOS Master Mode I2S Data Input. Shared with GPIO0
MCLK 16 IO, LVCMOS Master Mode I2S System Clock Input/Output
POWER and GROUND
VTERM 57 Power 3.3V (±5%) Supply for DC-coupled internal termination OR
1.8V (±5%) Supply for AC-coupled internal termination
Refer to Figure 25 or Figure 26.
VDD18 24 Power 1.8 (±5%) Analog supply. Refer to Figure 25 or Figure 26.
51
64
VDDA11 9 Power 1.1V(±5%) Analog supply. Refer to Figure 25 or Figure 26.
VDDHA11 52 Power 1.1V(±5%) TMDS supply. Refer to Figure 25 or Figure 26.
54
58
61
VDDHS11 21 Power 1.1V(±5%) supply. Refer to Figure 25 or Figure 26.
28
VDDL11 7 Power 1.1V(±5%) Digital supply. Refer to Figure 25 or Figure 26.
41
VDDP11 17 Power 1.1V(±5%) PLL supply. Refer to Figure 25 or Figure 26.
VDDS11 25 Power 1.1V(±5%) Serializer supply. Refer to Figure 25 or Figure 26.
VDDIO 3 Power 1.8V (±5%) IO supply. Refer to Figure 25 or Figure 26.
46
GND Thermal GND Ground. Connect to Ground plane with at least 9 vias.
Pad
OTHER
RES0 2 Reserved. Tie to GND.
RES1 29
Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: DS90UH949-Q1
DS90UH949-Q1
SNLS453 –NOVEMBER 2014
www.ti.com
Pin Functions (continued)
PIN I/O, TYPE DESCRIPTION
NAME NO.
RES2 30 Reserved. Connect with 50Ωto GND.
NC0 47 No connect. Leave floating. Do not connect to VDD or GND.
NC1 48
NC2 53
6Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: DS90UH949-Q1
DS90UH949-Q1
www.ti.com
SNLS453 –NOVEMBER 2014
7 Specifications
7.1 Absolute Maximum Ratings MIN MAX UNIT
Supply Voltage – VDD11 −0.3 1.7 V
Supply Voltage – VDD18 -0.3 2.5 V
Supply Voltage – VDDIO −0.3 2.5 V
OpenLDI Inputs -0.3 2.75 V
LVCMOS I/O Voltage −0.3 (VDDIO + 0.3) V
1.8V Tolerant I/O -0.3 2.5 V
3.3V Tolerant I/O -0.3 4.0 V
5V Tolerant I/O -0.3 5.3 V
FPD-Link III Output Voltage −0.3 1.7 V
Junction Temperature 150 °C
For soldering specifications:
see product folder at www.ti.com and www.ti.com/lit/an/snoa549c/snoa549c.pdf
7.2 Handling Ratings MIN MAX UNIT
Tstg Storage temperature range 64 Lead VQFN Package -65 +150 °C
Human body model (HBM), per AEC Q100-002(1) -2 +2 kV
V(ESD) Electrostatic discharge Charged device model (CDM), per AEC Q100-011 -750 +750 V
Air Discharge (DOUT0+, DOUT0-, DOUT1+, DOUT1-) -15 +15
ESD Rating (IEC 61000-4-2) kV
RD= 330Ω, CS= 150pF Contact Discharge (DOUT0+, DOUT0-, DOUT1+, DOUT1-) -8 +8
ESD Rating (ISO10605) Air Discharge (DOUT0+, DOUT0-, DOUT1+, DOUT1-) -15 +15
RD= 330Ω, CS= 150pF kV
Contact Discharge (DOUT0+, DOUT0-, DOUT1+, DOUT1-) -8 +8
RD= 2KΩ, CS= 150pF or 330pF
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions MIN NOM MAX UNIT
Supply Voltage (VDD11) 1.045 1.1 1.155 V
Supply Voltage (VDD18) 1.71 1.8 1.89 V
LVCMOS Supply Voltage (VDDIO) 1.71 1.8 1.89 V
VDDI2C, 1.8V Operation 1.71 1.8 1.89 V
VDDI2C, 3.3V Operation 3.135 3.3 3.465 V
HDMI Termination (VTERM), DC-coupled 3.135 3.3 3.465 V
HDMI Termination (VTERM), AC-coupled 1.71 1.8 1.89 V
Operating Free Air Temperature (TA)−40 +25 +105 °C
TMDS Frequency 25 170 MHz
Supply Noise(1) (DC-50MHz) 25 mVP-P
(1) Supply noise testing was done without any capacitors or ferrite beads connected. A sinusoidal signal is AC coupled to the VDD11 supply
of the serializer until the deserializer loses lock.
Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: DS90UH949-Q1
DS90UH949-Q1
SNLS453 –NOVEMBER 2014
www.ti.com
7.4 Thermal Information VQFN
THERMAL METRIC(1) UNIT
64 PINS
RθJA Junction-to-ambient thermal resistance 25.8
RθJC(top) Junction-to-case (top) thermal resistance 11.4
RθJB Junction-to-board thermal resistance 5.1 °C/W
ψJT Junction-to-top characterization parameter 0.2
ψJB Junction-to-board characterization parameter 5.1
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
8Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: DS90UH949-Q1
DS90UH949-Q1
www.ti.com
SNLS453 –NOVEMBER 2014
7.5 DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT
1.8V LVCMOS I/O
High Level Input SCLK/I2CSEL,
VIH 0.65 * VDDIO V
Voltage PDB,
D_GPIO0/MOSI,
Low Level Input
VIL 0 0.35 * VDDIO V
D_GPIO1/MISO,
Voltage D_GPIO2/SPLK,
D_GPIO3/SS,
SDIN/GPIO0,
SWC/GPIO1,
MCLK
I2S_DC/GPIO2,
I2S_DD/GPIO3,
I2S_DB/GPIO5_RE
IIN Input Current VIN = 0V or 1.89V −10 10 μA
G,
I2S_DA/GPIO6_RE
G,
I2S_CLK/GPIO8_R
EG,
I2S_WC/GPIO7_R
EG
High Level Output
VOH IOH =−4mA 0.7 * VDDIO VDDIO V
Voltage
Low Level Output
VOL IOL = +4mA GND 0.26 * VDDIO V
Voltage Same as above
Output Short Circuit
IOS VOUT = 0V -50 mA
Current
TRI-STATE™ Output
IOZ VOUT = 0V or VDDIO, PDB = L −10 10 μA
Current
TMDS INPUTS -- FROM HDMI v1.4b SECTION 4.2.5
Input Common-Mode IN_D[2:0]+,
VICM1 VTERM - 400 VTERM - 37.5 mV
Voltage IN_D[2:0]-
Input Common-Mode IN_CLK+, IN_CLK-
VICM2 IN_CLK ≤170MHz VTERM - 10 VTERM + 10 mV
Voltage VTERM = 1.8V (+,-
5%) or VTERM =
Input Differential
VIDIFF 150 1200 mVP-P
3.3V (+,- 5%)
Voltage Level IN_D[2:0]+,
Termination
RTMDS Differential IN_D[2:0]- 90 100 110 Ω
Resistance IN_CLK+, IN_CLK-
HDMI IO -- FROM HDMI v1.4b SECTION 4.2.7 to 4.2.9
4.8 5.3 V
VRX_5V +5V Power Signal RX_5V 50 mA
I5V_Sink +5V Input Current
High Level Output
VOH,HPD IOH = -4mA 2.4 5.3 V
Voltage, HPD HPD, RPU = 1 kΩ
Low Level Output
VOL,HPD IOL = +4mA GND 0.4 V
Voltage, HPD
Power-Down Input
IIZ,HPD PDB = L -10 10 uA
Current, HPD
Low Level Input
VIL,DDC 0.3*VDD,DDC V
Voltage, DDC
High Level Input DDC_SCL,
VIH,DDC 0.7*VDD,DDC V
Voltage, DDC DDC_SDA
Power-Down Input
IIZ,DDC PDB = L -10 10 µA
Current, DDC
Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: DS90UH949-Q1
DS90UH949-Q1
SNLS453 –NOVEMBER 2014
www.ti.com
DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT
High Level Input
VIH,CEC 2 V
Voltage, CEC
Low Level Input
VIL,CEC 0.8 V
Voltage, CEC
Input Hysteresis,
VHY,CEC 0.4 V
CEC CEC
Low Level Output
VOL,CEC GND 0.6 V
Voltage, CEC
High Level Output
VOH,CEC 2.5 3.63 V
Voltage, CEC
IOFF_CE Power-Down Input PDB = L -1.8 1.8 µA
CCurrent, CEC
FPD-LINK III DIFFERENTIAL DRIVER
Output Differential
VODp-p 900 1200 mVp-p
Voltage
Output Voltage
ΔVOD 1 50 mV
Unbalance
Output Differential
VOS 550 mV
Offset Voltage DOUT[1:0]+,
DOUT[1:0]-
Offset Voltage
ΔVOS 1 50 mV
Unbalance
Output Short Circuit
IOS FPD-Link III Outputs = 0V -50 mA
Current
Termination
RTSingle-ended 40 50 60 Ω
Resistance
SUPPLY CURRENT (1)
IDD11 330 mA
Supply Current, Colorbar Pattern
Normal Operation
IDD18 50 mA
IDD,VTER VTERM Current, Colorbar Pattern 60 mA
MNormal Operation
IDDZ11 15 mA
Supply Current, PDB = L
Power Down Mode
IDDZ18 5 mA
IDDZ,VTE VTERM Current, Colorbar Pattern 5 mA
RM Power Down Mode
(1) Specification is ensured by bench characterization.
10 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: DS90UH949-Q1
DS90UH949-Q1
www.ti.com
SNLS453 –NOVEMBER 2014
7.6 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT
GPIO FREQUENCY(1)
Rb,FC Forward Channel GPIO Single-Lane, IN_CLK = 25MHz GPIO[3:0], 0.25 *
Frequency - 96MHz D_GPIO[3:0] IN_CLK MHz
Dual-Lane, IN_CLK/2 = 25MHz 0.125 *
- 85MHz IN_CLK
tGPIO,FC GPIO Pulse Width, Single-Lane, IN_CLK = 25MHz GPIO[3:0], >2 / IN_CLK
Forward Channel - 96MHz D_GPIO[3:0] s
Dual-Lane, IN_CLK/2 = 25MHz >2 /
- 85MHz (IN_CLK/2)
TMDS INPUT
Skew-Intra Maximum Intra-Pair IN_CLK±, 0.4 UITMDS(2)
Skew IN_D[2:0]±
Skew-Inter Maximum Inter-Pair 0.2*Tchar(3) ns
Skew + 1.78ns
ITJIT Input Total Jitter IN_CLK± 0.3 UITMDS(2)
Tolerance
FPD-LINK III OUTPUT
tLHT Low Voltage Differential
Low-to-High Transition 80 ps
Time
tHLT Low Voltage Differential
High-to-Low Transition 80 ps
Time
tXZD Output Active to OFF PDB = L 100 ns
Delay
tPLD Lock Time (HDMI Rx) 5 ms
tSD Delay — Latency IN_CLK± 145*T(2) s
Random Pattern Single-Lane:
High pass
filter
IN_CLK/20
Output Total
tDJIT 0.3 UIFPD3(4)
Jitter(Figure 5 )Dual-lane:
High pass
filter
IN_CLK/40
Jitter Transfer Function
λSTXBW 960 kHz
(-3dB Bandwidth)
Jitter Transfer Function
δSTX 0.1 dB
Peaking
(1) Back channel rates are available on the companion deserializer datasheet.
(2) One bit period of the TMDS input.
(3) Ten bit periods of the TMDS input.
(4) One bit period of the serializer output.
Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: DS90UH949-Q1
DS90UH949-Q1
SNLS453 –NOVEMBER 2014
www.ti.com
7.7 DC And AC Serial Control Bus Characteristics
Over VDDI2C supply and temperature ranges unless otherwise specified. VDDI2C can be 1.8V (+,- 5%) or 3.3V (+,- 5%) (refer to
I2CSEL pin description for 1.8V or 3.3V operation).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH,I2C 0.7*
SDA and SCL, VDDI2C = 1.8V V
VDDI2C
Input High Level, I2C 0.7*
SDA and SCL, VDDI2C = 3.3V V
VDDI2C
VIL,I2C 0.3*
SDA and SCL, VDDI2C = 1.8V V
VDDI2C
Input Low Level Voltage, I2C 0.3*
SDA and SCL, VDDI2C = 3.3V V
VDDI2C
VHY Input Hysteresis, I2C SDA and SCL, VDDI2C = 1.8V or 3.3V >50 mV
VOL,I2C Output Low Level, I2C SDA and SCL, VDDI2C = 1.8V, Fast-Mode, 3mA Sink 0.2 *
GND V
Current VDDI2C
SDA and SCL, VDDI2C = 3.3V, 3mA Sink Current GND 0.4 V
IIN,I2C Input Current, I2C SDA and SCL, VDDI2C = 0V -800 -600 µA
SDA and SCL, VDDI2C = VDD18 or VDD33 -10 +10 µA
CIN,I2C Input Capacitance, I2C SDA and SCL 5 pF
12 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: DS90UH949-Q1
DS90UH949-Q1
www.ti.com
SNLS453 –NOVEMBER 2014
7.8 Recommended Timing for the Serial Control Bus
Over I2C supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSCL SCL Clock Frequency Standard-Mode >0 100 kHz
Fast-Mode >0 400 kHz
Fast-Mode Plus >0 1 MHz
tLOW SCL Low Period Standard-Mode 4.7 µs
Fast-Mode 1.3 µs
Fast-Mode Plus 0.5 µs
tHIGH SCL High Period Standard-Mode 4.0 µs
Fast-Mode 0.6 µs
Fast-Mode Plus 0.26 µs
tHD;STA Hold time for a start or a Standard-Mode 4.0 µs
repeated start condition Fast-Mode 0.6 µs
Fast-Mode Plus 0.26 µs
tSU;STA Set Up time for a start or a Standard-Mode 4.7 µs
repeated start condition Fast-Mode 0.6 µs
Fast-Mode Plus 0.26 µs
tHD;DAT Data Hold Time Standard-Mode 0 µs
Fast-Mode 0 µs
Fast-Mode Plus 0 µs
tSU;DAT Data Set Up Time Standard-Mode 250 ns
Fast-Mode 100 ns
Fast-Mode Plus 50 ns
tSU;STO Set Up Time for STOP Standard-Mode 4.0 µs
Condition Fast-Mode 0.6 µs
Fast-Mode Plus 0.26 µs
tBUF Bus Free Time Standard-Mode 4.7 µs
Between STOP and START Fast-Mode 1.3 µs
Fast-Mode Plus 0.5 µs
trSCL & SDA Rise Time, Standard-Mode 1000 ns
Fast-Mode 300 ns
Fast-Mode Plus 120 ns
tfSCL & SDA Fall Time, Standard-Mode 300 ns
Fast-Mode 300 ns
Fast-Mode Plus 120 ns
tSP Input Filter Fast-Mode 50 ns
Fast-Mode Plus 50 ns
Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: DS90UH949-Q1
RX_5V
IN_CLK
(Diff.)
DOUT
(Diff.) Driver OFF, VOD = 0V Driver On
VDD
VDDIO
tPLD
PDB
0V
tHLT
tLHT
(DOUT+) - (DOUT-) 20%
80%
VOD
DS90UH949-Q1
SNLS453 –NOVEMBER 2014
www.ti.com
Figure 1. Serializer VOD Output
Figure 2. Output Transition Times
Figure 3. Serializer Lock Time
14 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: DS90UH949-Q1
I2S_WC
I2S_D[A,B,C,D]
I2S_CLK VIH
VIL
tHC
tLC
tsr thr
T
SCL
SDA
tHD;STA
tLOW tr
tHD;DAT tHIGH
tf
tSU;DAT
tSU;STA tSU;STO
tf
START REPEATED
START STOP
tHD;STA
START
tSP
trBUF
t
DOUT
(Diff.)
tDJIT
tBIT (1 UI)
EYE OPENING 0V
tDJIT
210
||
START
BIT STOP
BIT
SYMBOL N
210
||
START
BIT STOP
BIT
SYMBOL N-1
210
||
START
BIT STOP
BIT
SYMBOL N-2
210
||
START
BIT STOP
BIT
SYMBOL N-3
210
STOP
BIT
SYMBOL N-4
||
DOUT
|
IN_CLK
tSD
NN-1 N+1 N+2
| |
IN_D[2:0]
DS90UH949-Q1
www.ti.com
SNLS453 –NOVEMBER 2014
Figure 4. Latency Delay
Figure 5. Serializer Output Jitter
Figure 6. Serial Control Bus Timing Diagram
Figure 7. I2S Timing Diagram
Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: DS90UH949-Q1
DS90UH949-Q1
SNLS453 –NOVEMBER 2014
www.ti.com
7.9 Typical Characteristics
Figure 8. Serializer Output at 2.975Gbps (85MHz TMDS Figure 9. Serializer Output at 3.36Gbps (96MHz TMDS
Clock) Clock)
16 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: DS90UH949-Q1
FPD-Link III Digital
HDMI Controller
Digital
HDMI RX
PHY
FPD-Link
III TX
Digital
FPD3 TX
Analog
Bridge Control
Digital
TMDS
DDC
HPA
FPD-Link III
Audio
PLL Audio
FIFO
Packet
FIFO
KSV
FIFO
EDID/
Config
NVM
EDID
I/F
I2S Audio
Video
HDCP
Key
NVM
RX_5V
I2C Optional
Secondary
I2S
Digital
TMDS
Interface
FPD3 TX
Analog FPD-Link III
FPD-Link
III TX
Digital
PAT
GEN
H
D
C
P
H
D
C
P
DS90UH949-Q1
www.ti.com
SNLS453 –NOVEMBER 2014
8 Detailed Description
8.1 Overview
The DS90UH949-Q1 converts an HDMI interface (3 TMDS data channels + 1 TMDS Clock) to an FPD-Link III
interface. This device transmits a 35-bit symbol over a single serial pair operating up to 3.36Gbps line rate, or
two serial pairs operating up to 2.975Gbps line rate. The serial stream contains an embedded clock, video
control signals, RGB video data, and audio data. The payload is DC-balanced to enhance signal quality and
support AC coupling.
The DS90UH949-Q1 serializer is intended for use with a DS90UH926Q-Q1, DS90UH928Q-Q1, DS90UH940-Q1,
DS90UH948-Q1 deserializer.
The DS90UH949-Q1 serializer and companion deserializer incorporate an I2C compatible interface. The I2C
compatible interface allows programming of serializer or deserializer devices from a local host controller. In
addition, the devices incorporate a bidirectional control channel (BCC) that allows communication between
serializer/deserializer as well as remote I2C slave devices.
The bidirectional control channel (BCC) is implemented via embedded signaling in the high-speed forward
channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to
serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial
link from one I2C bus to another. The implementation allows for arbitration with other I2C compatible masters at
either side of the serial link.
8.2 Functional Block Diagram
Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: DS90UH949-Q1
DS90UH949-Q1
SNLS453 –NOVEMBER 2014
www.ti.com
8.3 Feature Description
8.3.1 High-Definition Multimedia Interface (HDMI)
HDMI is a leading interface standard used to transmit digital video and audio from sources (such as a DVD
player) to sinks (such as an LCD display). The interface is capable of transmitting high-definition video, audio,
and also supports HDCP. Other HDMI signals consist of various control and status data that travel bidirectionally.
8.3.1.1 HDMI Receive Controller
The HDMI Receiver is an HDMI version 1.4b compliant receiver. The HDMI receiver is capable of operation at
greater than 1080p resolutions. The configuration used in the DS90UH949-Q1does not include version 1.4b
features such as the ethernet channel (HEC) or Audio Return Channel (ARC).
8.3.2 Transition Minimized Differential Signaling
HDMI uses Transition Minimized Differential Signaling (TMDS) over four differential pairs (3 TMDS channels and
1 TMDS clock) to transmit video and audio data. TMDS is widely used to transmit high-speed serial data. The
technology incorporates a form of 8b/10b encoding and its differential signaling allows it to reduce
electromagnetic interference (EMI) and achieve high skew tolerance.
8.3.3 Enhanced Display Data Channel
The Display Data Channel or DDC is a collection of digital communication protocols between a computer display
and a graphics adapter that enables the display to communicate its supported display modes to the adapter and
allow the computer host to adjust monitor parameters, such as brightness and contrast.
8.3.4 Extended Display Identification Data (EDID)
EDID is a data structure provided by a digital display to describe its capabilities to a video source. By providing
this information, the video source can then send video data with proper timing and resolution that the display
supports. The DS90UH949-Q1 supports several options for delivering display identification (EDID) information to
the HDMI graphics source. The EDID information is accessible via the DDC interface and comply with the DDC
and EDID requirements given in the HDMI v1.4b specification.
The EDID configurations supported are as follows:
• External local EDID (EEPROM)
• Internal EDID loaded into device memory
• Remote EDID connected to I2C bus at deserializer side
• Internal pre-programmed EDID
The EDID mode selected should be configurable from the MODE_SEL pins, or from internal control registers. For
all modes, the EDID information should be accessible at the default address of 0xA0.
8.3.4.1 External Local EDID (EEPROM)
The DS90UH949-Q1 can be configured to allow a local EEPROM EDID device. The local EDID device may
implement any EDID configuration allowable by the HDMI v1.4b and DVI 1.0 standards, including multiple
extension b